content
stringlengths 1
1.04M
⌀ |
|---|
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
end process;
-- Blocking assignment
process is
variable a : integer;
begin
a := 2;
a := a + (a * 3);
end process;
-- Assert and report
process is
begin
assert true;
assert false severity note;
assert 1 > 2 report "oh no" severity failure;
report "hello";
report "boo" severity error;
end process;
-- Function calls
process is
begin
x := foo(1, 2, 3);
a := "abs"(b);
end process;
-- If
process is
begin
if true then
x := 1;
end if;
test: if true then
x := y;
end if test;
if x > 2 then
x := 5;
else
y := 2;
end if;
if x > 3 then
null;
elsif x > 5 then
null;
elsif true then
null;
else
x := 2;
end if;
end process;
-- Null
process is
begin
null;
end process;
-- Return
process is
begin
return 4 * 4;
end process;
-- While
process is
begin
while n > 0 loop
n := n - 1;
end loop;
loop
null;
end loop;
end process;
-- Delayed assignment
process is
begin
x <= 4 after 5 ns;
x <= 5 after 1 ns, 7 after 8 ns;
x <= 5, 7 after 8 ns;
x <= inertial 5;
x <= transport 4 after 2 ns;
x <= reject 4 ns inertial 6 after 10 ns;
end process;
-- For
process is
begin
for i in 0 to 10 loop
null;
end loop;
for i in foo'range loop
null;
end loop;
end process;
-- Exit
process is
begin
exit;
exit when x = 1;
end process;
-- Procedure call
process is
begin
foo(x, y, 1);
bar;
foo(a => 1, b => 2, 3);
end process;
-- Case
process is
begin
case x is
when 1 =>
null;
when 2 =>
null;
when 3 | 4 =>
null;
when others =>
null;
end case;
end process;
-- Next
process is
begin
next;
next when foo = 5;
end process;
-- Signal assignment to aggregate
process is
begin
( x, y, z ) <= foo;
end process;
-- Case statement range bug
process is
begin
case f is
when 1 =>
for i in x'range loop
end loop;
end case;
end process;
end architecture;
|
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
end process;
-- Blocking assignment
process is
variable a : integer;
begin
a := 2;
a := a + (a * 3);
end process;
-- Assert and report
process is
begin
assert true;
assert false severity note;
assert 1 > 2 report "oh no" severity failure;
report "hello";
report "boo" severity error;
end process;
-- Function calls
process is
begin
x := foo(1, 2, 3);
a := "abs"(b);
end process;
-- If
process is
begin
if true then
x := 1;
end if;
test: if true then
x := y;
end if test;
if x > 2 then
x := 5;
else
y := 2;
end if;
if x > 3 then
null;
elsif x > 5 then
null;
elsif true then
null;
else
x := 2;
end if;
end process;
-- Null
process is
begin
null;
end process;
-- Return
process is
begin
return 4 * 4;
end process;
-- While
process is
begin
while n > 0 loop
n := n - 1;
end loop;
loop
null;
end loop;
end process;
-- Delayed assignment
process is
begin
x <= 4 after 5 ns;
x <= 5 after 1 ns, 7 after 8 ns;
x <= 5, 7 after 8 ns;
x <= inertial 5;
x <= transport 4 after 2 ns;
x <= reject 4 ns inertial 6 after 10 ns;
end process;
-- For
process is
begin
for i in 0 to 10 loop
null;
end loop;
for i in foo'range loop
null;
end loop;
end process;
-- Exit
process is
begin
exit;
exit when x = 1;
end process;
-- Procedure call
process is
begin
foo(x, y, 1);
bar;
foo(a => 1, b => 2, 3);
end process;
-- Case
process is
begin
case x is
when 1 =>
null;
when 2 =>
null;
when 3 | 4 =>
null;
when others =>
null;
end case;
end process;
-- Next
process is
begin
next;
next when foo = 5;
end process;
-- Signal assignment to aggregate
process is
begin
( x, y, z ) <= foo;
end process;
-- Case statement range bug
process is
begin
case f is
when 1 =>
for i in x'range loop
end loop;
end case;
end process;
end architecture;
|
architecture a of b is
begin
-- Wait statements
process is
begin
wait for 1 ns;
block_forever: wait;
wait on x;
wait on x, y, z(1 downto 0);
wait on w(1) for 2 ns;
wait until x = 3;
wait until y = x for 5 ns;
wait on x until x = 2 for 1 ns;
end process;
-- Blocking assignment
process is
variable a : integer;
begin
a := 2;
a := a + (a * 3);
end process;
-- Assert and report
process is
begin
assert true;
assert false severity note;
assert 1 > 2 report "oh no" severity failure;
report "hello";
report "boo" severity error;
end process;
-- Function calls
process is
begin
x := foo(1, 2, 3);
a := "abs"(b);
end process;
-- If
process is
begin
if true then
x := 1;
end if;
test: if true then
x := y;
end if test;
if x > 2 then
x := 5;
else
y := 2;
end if;
if x > 3 then
null;
elsif x > 5 then
null;
elsif true then
null;
else
x := 2;
end if;
end process;
-- Null
process is
begin
null;
end process;
-- Return
process is
begin
return 4 * 4;
end process;
-- While
process is
begin
while n > 0 loop
n := n - 1;
end loop;
loop
null;
end loop;
end process;
-- Delayed assignment
process is
begin
x <= 4 after 5 ns;
x <= 5 after 1 ns, 7 after 8 ns;
x <= 5, 7 after 8 ns;
x <= inertial 5;
x <= transport 4 after 2 ns;
x <= reject 4 ns inertial 6 after 10 ns;
end process;
-- For
process is
begin
for i in 0 to 10 loop
null;
end loop;
for i in foo'range loop
null;
end loop;
end process;
-- Exit
process is
begin
exit;
exit when x = 1;
end process;
-- Procedure call
process is
begin
foo(x, y, 1);
bar;
foo(a => 1, b => 2, 3);
end process;
-- Case
process is
begin
case x is
when 1 =>
null;
when 2 =>
null;
when 3 | 4 =>
null;
when others =>
null;
end case;
end process;
-- Next
process is
begin
next;
next when foo = 5;
end process;
-- Signal assignment to aggregate
process is
begin
( x, y, z ) <= foo;
end process;
-- Case statement range bug
process is
begin
case f is
when 1 =>
for i in x'range loop
end loop;
end case;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company: Mike Field <[email protected]>
--
-- Module Name: accumulator - Behavioral
--
-- Description: Accumulate the 'up' and 'down' pulses from a rotary encoder.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity accumulator is
Port ( clk : in STD_LOGIC;
up : in STD_LOGIC;
down : in STD_LOGIC;
dir : out STD_LOGIC;
value : out STD_LOGIC_VECTOR (31 downto 0));
end accumulator;
architecture Behavioral of accumulator is
signal total : unsigned(value'range) := (others => '0');
signal s_dir : std_logic := '0';
begin
value <= std_logic_vector(total);
dir <= s_dir;
process(clk)
begin
if rising_edge(clk) then
if up = down then
null;
elsif up = '1' then
total <= total + 1;
s_dir <= '1';
else -- down must = '1'
total <= total - 1;
s_dir <= '0';
end if;
end if;
end process;
end Behavioral; |
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_finals_buckets_if_plb_master_if is
component nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component nfa_finals_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.1
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end entity;
architecture rtl of nfa_finals_buckets_if_ap_fifo_uw is
type memtype is array (0 to DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal mStorage : memtype;
signal mInPtr, mNextInPtr, mOutPtr : UNSIGNED(ADDR_WIDTH - 1 downto 0);
signal internal_empty_n, internal_full_n : STD_LOGIC;
signal internal_use_word : STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0);
begin
mNextInPtr <= mInPtr + 1;
if_dout <= mStorage(CONV_INTEGER(mOutPtr));
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
use_word <= internal_use_word;
process (clk, reset)
begin
if reset = '1' then
mInPtr <= (others => '0');
mOutPtr <= (others => '0');
internal_use_word <= (others => '0');
else
if clk'event and clk = '1' then
if if_read = '1' and internal_empty_n = '1' then
mOutPtr <= mOutPtr + 1;
end if;
if if_write = '1' and internal_full_n = '1' then
mStorage(CONV_INTEGER(mInPtr)) <= if_din;
mInPtr <= mNextInPtr;
end if;
if (if_read = '1' and if_write = '0') then
internal_use_word <= internal_use_word - '1';
elsif (if_read = '0' and if_write = '1') then
internal_use_word <= internal_use_word + '1';
end if;
end if;
end if;
end process;
process (mInPtr, mOutPtr, mNextInPtr)
begin
if mInPtr = mOutPtr then
internal_empty_n <= '0';
else
internal_empty_n <= '1';
end if;
if mNextInPtr = mOutPtr then
internal_full_n <= '0';
else
internal_full_n <= '1';
end if;
end process;
end architecture;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity nfa_finals_buckets_if_plb_master_if is
generic
(
C_PLB_AWIDTH : integer := 32;
C_PLB_DWIDTH : integer := 64;
PLB_ADDR_SHIFT : integer := 3
);
port
(
-- ADD USER PORTS BELOW THIS LINE ------------------
--USER ports added here
-- ADD USER PORTS ABOVE THIS LINE ------------------
-- DO NOT EDIT BELOW THIS LINE ---------------------
-- Bus protocol ports, do not add to or delete
PLB_Clk : in std_logic;
PLB_Rst : in std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to C_PLB_AWIDTH-1);
M_BE : out std_logic_vector(0 to C_PLB_DWIDTH/8-1);
M_busLock : out std_logic;
M_lockErr : out std_logic;
M_MSize : out std_logic_vector(0 to 1);
M_priority : out std_logic_vector(0 to 1);
M_rdBurst : out std_logic;
M_request : out std_logic;
M_RNW : out std_logic;
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_wrBurst : out std_logic;
M_wrDBus : out std_logic_vector(0 to C_PLB_DWIDTH-1);
PLB_MBusy : in std_logic;
PLB_MWrBTerm : in std_logic;
PLB_MWrDAck : in std_logic;
PLB_MAddrAck : in std_logic;
PLB_MRdBTerm : in std_logic;
PLB_MRdDAck : in std_logic;
PLB_MRdDBus : in std_logic_vector(0 to (C_PLB_DWIDTH-1));
PLB_MRdWdAddr : in std_logic_vector(0 to 3);
PLB_MRearbitrate : in std_logic;
PLB_MSSize : in std_logic_vector(0 to 1);
-- signals from user logic
BUS_RdData : out std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus read return data to user_logic
BUS_WrData : in std_logic_vector(C_PLB_DWIDTH-1 downto 0); -- Bus write data
BUS_address : in std_logic_vector(31 downto 0); -- physical address
BUS_size : in std_logic_vector(31 downto 0); -- burst size of word
BUS_req_nRW : in std_logic; -- req type 0: Read, 1: write
BUS_req_BE : in std_logic_vector(C_PLB_DWIDTH/8-1 downto 0); -- Bus write data byte enable
BUS_req_full_n : out std_logic; -- req Fifo full
BUS_req_push : in std_logic; -- req Fifo push (new request in)
BUS_rsp_nRW : out std_logic; -- return data FIFO rsp type
BUS_rsp_empty_n: out std_logic; -- return data FIFO empty
BUS_rsp_pop : in std_logic -- return data FIFO pop
);
attribute SIGIS : string;
attribute SIGIS of PLB_Clk : signal is "Clk";
attribute SIGIS of PLB_Rst : signal is "Rst";
end entity;
------------------------------------------------------------------------------
-- Architecture section
------------------------------------------------------------------------------
architecture IMP of nfa_finals_buckets_if_plb_master_if is
component nfa_finals_buckets_if_ap_fifo is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end component;
component nfa_finals_buckets_if_ap_fifo_uw is
generic (
DATA_WIDTH : integer := 32;
ADDR_WIDTH : integer := 4;
DEPTH : integer := 16);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
use_word: OUT STD_LOGIC_VECTOR(ADDR_WIDTH -1 downto 0));
end component;
constant PLB_DW : integer := C_PLB_DWIDTH;
constant PLB_BYTE_COUNT : integer := PLB_DW/8;
constant REQ_FIFO_WIDTH : integer := 1 + PLB_BYTE_COUNT + 32 + 32; --nRW + BE + 32 bits phy addr + size
constant FIFO_ADDR_WIDTH : integer := 5;
constant FIFO_DEPTH : integer := 32;
-- request FIFO
signal req_fifo_empty_n : STD_LOGIC;
signal req_fifo_pop : STD_LOGIC;
signal req_fifo_dout : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
signal req_fifo_full_n : STD_LOGIC;
signal req_fifo_push : STD_LOGIC;
signal req_fifo_din : STD_LOGIC_VECTOR(REQ_FIFO_WIDTH - 1 downto 0);
-- burst write counter (only push burst data in and ignore all burst write request except the first one)
signal req_burst_write: STD_LOGIC; -- whether last request is a burst write
signal req_burst_write_counter: STD_LOGIC_VECTOR(31 downto 0);
-- write data FIFO (for bus write data)
signal wd_fifo_empty_n : STD_LOGIC;
signal wd_fifo_pop : STD_LOGIC;
signal wd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_dout_mirror : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_full_n : STD_LOGIC;
signal wd_fifo_push : STD_LOGIC;
signal wd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal wd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
-- read data FIFO (for bus read returned data)
signal rd_fifo_empty_n : STD_LOGIC;
signal rd_fifo_pop : STD_LOGIC;
signal rd_fifo_dout : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_full_n : STD_LOGIC;
signal rd_fifo_push : STD_LOGIC;
signal rd_fifo_din : STD_LOGIC_VECTOR(PLB_DW - 1 downto 0);
signal rd_fifo_use_word: STD_LOGIC_VECTOR(FIFO_ADDR_WIDTH -1 downto 0);
signal req_address : std_logic_vector(0 to C_PLB_AWIDTH -1);-- bus request word address
signal req_fifo_dout_req_size : std_logic_vector(31 downto 0); -- req_size -1
signal req_size : std_logic_vector(0 to 27); -- burst size of 16 word block
signal request, req_nRW: std_logic;
signal req_BE : std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal pending_rd_req_burst_mode: std_logic;
signal pending_rd_req_burst_size: std_logic_vector(3 downto 0);
signal pending_wr_req_burst_mode: std_logic;
signal pending_wr_req_burst_size: std_logic_vector(3 downto 0);
signal pending_read, pending_write: std_logic;
signal burst_mode, burst_last : std_logic;
signal burst_size : std_logic_vector(3 downto 0); -- maximum burst 16 words
--signals for write data mirror
signal conv_mode_comb : std_logic_vector(1 downto 0); -- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal conv_counter_comb: std_logic_vector(1 downto 0);
signal wr_data_phase : std_logic;
signal dataConv_last: std_logic;
signal dp_dataConv_last: std_logic;
signal dp_dataConv_word_addr: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_conv_mode : std_logic_vector(1 downto 0); -- 00:NO conv, 01:128/32, 10:64/32, 11:128/64
signal dp_dataConv_wd_burst_counter: std_logic_vector(1 downto 0);
signal dp_dataConv_wd_BE: std_logic_vector(PLB_BYTE_COUNT-1 downto 0);
signal dp_PLB_MSSize : std_logic_vector(1 downto 0);
--signals for read data mirror
signal PLB_MRdDAck_reg : std_logic;
signal dp_dataConv_rd_conv_mode : std_logic_vector(1 downto 0);-- 00: NO conv, 01: 128/32, 10: 64/32, 11: 128/64
signal dp_dataConv_rd_burst_counter, dp_dataConv_rd_burst_counter_reg: std_logic_vector(1 downto 0);
signal PLB_MRdDBus_reverse : std_logic_vector(PLB_DW-1 downto 0);
-- signals with dp_ prefix stand for data phase signals
-- signals with req_ prefix stand for request phase signals
begin
-- interface to user logic
BUS_RdData <= rd_fifo_dout;
BUS_req_full_n <= req_fifo_full_n and wd_fifo_full_n;
BUS_rsp_nRW <= '0';
BUS_rsp_empty_n <= rd_fifo_empty_n;
-- interface to PLB
M_abort <= '0';
M_busLock <= '0';
M_lockErr <= '0';
M_MSize <= "01"; -- 00:32b dev, 01:64b, 10:128b, 11:256b
M_size <= "0000" when (burst_mode = '0' or burst_size = "0000") else "1011"; -- single rw or 64 bits burst
M_type <= "000"; -- memory trans
M_priority <= "00";
M_RNW <= not req_nRW;
M_rdBurst <= '1' when pending_rd_req_burst_mode = '1' and
(pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /="00") else '0';
process (PLB_MSSize)
begin
M_wrBurst <= '0';
if (pending_wr_req_burst_mode = '1' and
(pending_wr_req_burst_size /= "0000" or dp_dataConv_wd_burst_counter /="00")) then
M_wrBurst <= '1';
elsif (request = '1' and req_nRW = '1' and pending_write = '0' and
burst_mode = '1' and burst_size /="0000" and wd_fifo_use_word > burst_size) then
M_wrBurst <= '1';
end if;
end process;
-- write data mirror section
process (PLB_MSSize)
begin
if (C_PLB_DWIDTH = 64 and PLB_MSSize = "00") then
conv_mode_comb <= "10"; -- conv 64:32
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "01") then
conv_mode_comb <= "11"; -- conv 128:64
conv_counter_comb <= "01";
elsif (C_PLB_DWIDTH = 128 and PLB_MSSize = "00") then
conv_mode_comb <= "01"; -- conv 128:32
conv_counter_comb <= "11";
else
conv_mode_comb <= "00"; -- do not need conv
conv_counter_comb <= "00";
end if;
end process;
process (burst_mode, burst_size, conv_mode_comb, req_address, req_BE)
begin
dataConv_last <= '0';
if (burst_mode = '0' or burst_size = "0000") then
if (conv_mode_comb = "00") then -- no conv
dataConv_last <= '1';
elsif (conv_mode_comb = "10") then -- 64:32 conv
if (req_address(29)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "11") then -- 128:64 conv
if (req_address(28)='1' or req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
end if;
elsif (conv_mode_comb = "01") then -- 128:32 conv
if (req_address(28 to 29) = "00" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT*3/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "01" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT/2)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/2)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "10" and req_BE(PLB_BYTE_COUNT-1 downto PLB_BYTE_COUNT*3/4)=CONV_STD_LOGIC_VECTOR(0,PLB_BYTE_COUNT/4)) then
dataConv_last <= '1';
elsif (req_address(28 to 29) = "11") then
dataConv_last <= '1';
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_word_addr <= (others => '0');
dp_dataConv_wd_conv_mode <= (others =>'0');
dp_dataConv_wd_burst_counter <= (others => '0');
dp_dataConv_wd_BE <= (others => '0');
dp_dataConv_last <= '0';
wr_data_phase <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
dp_dataConv_wd_BE <= req_BE;
dp_dataConv_last <= dataConv_last;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and
(PLB_MWrDAck = '0' or (burst_mode = '1' and burst_size /= "0000"))) then
wr_data_phase <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if ((pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0')) then
wr_data_phase <= '0';
end if;
end if;
if (PLB_MAddrAck = '1' and req_nRW = '1' and dp_dataConv_wd_conv_mode = "00") then
if (PLB_MWrDAck = '0') then
-- only AddrAck asserted
dp_dataConv_wd_conv_mode <= conv_mode_comb;
dp_dataConv_word_addr <= req_address(28 to 29);
dp_dataConv_wd_burst_counter <= conv_counter_comb;
else
-- Xilinx PLB v4.6 support assert addrAck & wrDAck at the same cycle
if (dataConv_last = '0') then
dp_dataConv_wd_conv_mode <= conv_mode_comb;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +1;
elsif (PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= req_address(28 to 29) +2;
end if;
if (conv_mode_comb /= "00") then -- need conv
dp_dataConv_wd_burst_counter <= conv_counter_comb -1;
end if;
end if;
end if;
if (wr_data_phase = '1' and PLB_MWrDAck = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
(pending_wr_req_burst_mode = '0' and dp_dataConv_last = '1'))) then
dp_dataConv_wd_conv_mode <= "00";
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1') then
if (dp_PLB_MSSize = "01") then -- 64 bits slave
dp_dataConv_word_addr <= dp_dataConv_word_addr +2;
else
dp_dataConv_word_addr <= dp_dataConv_word_addr +1;
end if;
if ((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size /= "0000") or
dp_dataConv_wd_burst_counter /= "00") then
if (dp_dataConv_wd_burst_counter = "00") then
if (dp_dataConv_wd_conv_mode = "01") then -- 128/32
dp_dataConv_wd_burst_counter <= "11";
elsif (dp_dataConv_wd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_wd_burst_counter <= "01";
end if;
else
dp_dataConv_wd_burst_counter <= dp_dataConv_wd_burst_counter -1;
end if;
end if;
end if;
end if;
end process;
process(PLB_MWrDAck, wr_data_phase, dp_dataConv_wd_burst_counter, burst_mode, conv_counter_comb, conv_mode_comb, req_BE)
begin
wd_fifo_pop <= '0';
if (PLB_MWrDAck = '1') then
if (wr_data_phase = '1') then
if ((pending_wr_req_burst_mode = '1' and dp_dataConv_wd_burst_counter = "00") or
(dp_dataConv_wd_conv_mode /= "00" and dp_dataConv_last = '1') or
dp_dataConv_wd_conv_mode = "00" )then
wd_fifo_pop <= '1';
end if;
else
-- got addrAck and wrDAck at the same cycle
if (burst_mode = '1' and burst_size /= "0000" and conv_counter_comb = "00") then
wd_fifo_pop <= '1';
elsif ((burst_mode = '0' or burst_size = "0000") and dataConv_last = '1') then
wd_fifo_pop <= '1';
end if;
end if;
end if;
end process;
process(wd_fifo_dout, wr_data_phase, req_address, dp_dataConv_wd_conv_mode, dp_dataConv_word_addr)
begin
wd_fifo_dout_mirror <= wd_fifo_dout;
if (wr_data_phase = '0') then -- we do not know slave bus width, perform default convert
if (C_PLB_DWIDTH = 32) then
wd_fifo_dout_mirror <= wd_fifo_dout;
elsif (C_PLB_DWIDTH = 64) then
if (req_address(29) = '0') then
wd_fifo_dout_mirror <= wd_fifo_dout;
else
wd_fifo_dout_mirror(PLB_DW/2-1 downto 0) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
wd_fifo_dout_mirror(PLB_DW-1 downto PLB_DW/2) <= wd_fifo_dout(PLB_DW-1 downto PLB_DW/2);
end if;
elsif (C_PLB_DWIDTH = 128) then
case req_address(28 to 29) is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
else -- in data phase
wd_fifo_dout_mirror <= wd_fifo_dout;
if ((dp_dataConv_wd_conv_mode = "10" and dp_dataConv_word_addr(0) = '1') or
(dp_dataConv_wd_conv_mode = "11" and dp_dataConv_word_addr(1) = '1')) then -- conv 64:32 or 128:64
wd_fifo_dout_mirror(C_PLB_DWIDTH/2-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
wd_fifo_dout_mirror(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH/2);
elsif (dp_dataConv_wd_conv_mode = "01") then -- conv 128:32
case dp_dataConv_word_addr is
when "00" =>
wd_fifo_dout_mirror <= wd_fifo_dout;
when "01" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH/2-1 downto C_PLB_DWIDTH/4);
when "10" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH*3/4-1 downto C_PLB_DWIDTH/2);
when "11" =>
wd_fifo_dout_mirror(C_PLB_DWIDTH/4-1 downto 0) <= wd_fifo_dout(C_PLB_DWIDTH-1 downto C_PLB_DWIDTH*3/4);
when others => null;
end case;
end if;
end if;
end process;
process(wd_fifo_dout_mirror)
variable i: integer;
begin
for i in 0 to C_PLB_DWIDTH-1 loop
M_wrDBus(i) <= wd_fifo_dout_mirror(i);
end loop;
end process;
process (request, req_nRW, pending_read, burst_mode, rd_fifo_full_n, rd_fifo_use_word,
pending_write, wd_fifo_empty_n, wd_fifo_use_word, burst_size)
begin
M_request <= '0';
if (request = '1') then
if (req_nRW = '0' and pending_read = '0') then -- read request
if ((burst_mode = '0' or burst_size = "0000") and rd_fifo_full_n = '1') then
M_request <= '1';
elsif (rd_fifo_use_word(4) = '0') then -- 16 words slots available
M_request <= '1';
end if;
elsif (req_nRW = '1' and pending_write = '0') then -- write request
if ((burst_mode = '0' or burst_size = "0000") and wd_fifo_empty_n = '1') then
M_request <= '1';
elsif (wd_fifo_use_word > burst_size) then
M_request <= '1';
end if;
end if;
end if;
end process;
M_ABus(0 to C_PLB_AWIDTH - 1) <= req_address;
process(req_nRW, burst_mode, burst_size, req_BE)
variable i:integer;
begin
M_BE <= (others => '0');
if (burst_mode = '1') then
if (burst_size = "0000") then
M_BE <= (others => '1'); -- first single,then burst 16
else
M_BE(0 to 3) <= burst_size; -- fixed length burst
end if;
elsif (req_nRW = '0') then
M_BE <= (others => '1');
else
for i in 0 to PLB_BYTE_COUNT-1 loop
M_BE(i) <= req_BE(i);
end loop;
end if;
end process;
-- user req FIFO, for both read request and write request
U_req_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo
generic map(
DATA_WIDTH => REQ_FIFO_WIDTH,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => req_fifo_empty_n,
if_read => req_fifo_pop,
if_dout => req_fifo_dout,
if_full_n => req_fifo_full_n,
if_write => req_fifo_push,
if_din => req_fifo_din
);
req_fifo_push <= BUS_req_push and not req_burst_write;
req_fifo_din <= BUS_req_nRW & BUS_req_BE & BUS_address & BUS_size;
req_fifo_dout_req_size <= req_fifo_dout(31 downto 0) -1;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
req_burst_write <= '0';
req_burst_write_counter <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (req_fifo_push = '1' and BUS_req_nRW = '1' and BUS_size(31 downto 1) /= "0000000000000000000000000000000") then
req_burst_write <= '1';
req_burst_write_counter <= BUS_size - 1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write = '1') then
req_burst_write_counter <= req_burst_write_counter -1;
end if;
if (BUS_req_push = '1' and BUS_req_nRW = '1' and req_burst_write_counter = X"00000001") then-- last burst write data
req_burst_write <= '0';
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
request <= '0';
req_size <= (others => '0');
req_nRW <= '0';
req_address(0 to C_PLB_AWIDTH - 1) <= (others => '0');
burst_mode <= '0';
burst_size <= (others => '0');
req_fifo_pop <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
req_fifo_pop <= '0';
if ((request = '0' and req_fifo_empty_n = '1') or PLB_MAddrAck = '1') then
if (PLB_MAddrAck = '1' and (burst_mode = '0' or burst_size ="0000") and dataConv_last = '0') then
request <= '1';
if (conv_mode_comb(1) = '1') then -- 2:1 conv
req_BE(PLB_BYTE_COUNT/2-1 downto 0) <= (others => '0');
else -- 128:32
if (req_address(28 to 29) = "00") then
req_BE(PLB_BYTE_COUNT/4-1 downto 0) <= (others => '0');
elsif (req_address(28 to 29) = "01") then
req_BE(PLB_BYTE_COUNT/2-1 downto PLB_BYTE_COUNT/4) <= (others => '0');
elsif (req_address(28 to 29) = "10") then
req_BE(PLB_BYTE_COUNT*3/4-1 downto PLB_BYTE_COUNT/2) <= (others => '0');
end if;
end if;
if (PLB_MSSize = "00") then -- 32 bits slave
req_address <= req_address + 4;
elsif (PLB_MSSize = "01") then -- 64 slave
req_address <= req_address + 8;
end if;-- 128 bits slave does not need conversion cycle
elsif (PLB_MAddrAck = '1' and burst_mode = '1' and burst_last = '0') then
request <= '1'; -- req next burst section, this will be pending until previous burst finished
req_size(0 to 27) <= req_size(0 to 27) - 1;
req_address(0 to C_PLB_AWIDTH - PLB_ADDR_SHIFT - 1) <= req_address(0 to C_PLB_AWIDTH -PLB_ADDR_SHIFT -1) + burst_size +1;
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
-- low bits of addr must be reset for possible data_conv modifications of 10 lines above
burst_mode <= '1';
burst_size <= "1111"; -- burst 16 words
else
if (req_fifo_empty_n = '1') then
req_fifo_pop <= '1';
end if;
request <= req_fifo_empty_n; -- fetch next user_req, may be a vaild req or a null req
req_size(0 to 27) <= req_fifo_dout_req_size(31 downto 4); --remaining burst transfer except current one
req_nRW <= req_fifo_dout(REQ_FIFO_WIDTH-1);
req_BE <= req_fifo_dout(REQ_FIFO_WIDTH-2 downto 64);
req_address <= req_fifo_dout(63 downto 32);
if (req_fifo_dout(REQ_FIFO_WIDTH-1) = '0') then -- read request
req_address(C_PLB_AWIDTH-PLB_ADDR_SHIFT to C_PLB_AWIDTH-1) <= (others => '0');
end if;
-- long burst request will be split to 1stReq: 1-16 words, all next req: 16 words
if (req_fifo_dout_req_size /= X"00000000") then -- more than 1 word, burst
burst_mode <= req_fifo_empty_n; -- fetched req may be null req
-- req of burst 17 will be single + burst 16, please check burst_size also
else
burst_mode <= '0';
end if;
burst_size(3 downto 0) <= req_fifo_dout_req_size(3 downto 0);-- 0:single, 1-15: burst 2-16words
end if;
end if;
end if;
end process;
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_read <= '0';
pending_write <= '0';
dp_PLB_MSSize <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00") or
(pending_rd_req_burst_mode = '0'))) then
pending_read <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='0') then
pending_read <= '1';
end if;
if (PLB_MWrDAck = '1' and wr_data_phase = '1' and
((pending_wr_req_burst_mode = '1' and pending_wr_req_burst_size = "0000" and dp_dataConv_wd_burst_counter = "00") or
pending_wr_req_burst_mode = '0')) then
pending_write <= '0';
elsif (PLB_MAddrAck = '1' and req_nRW='1' and
(PLB_MWrDAck = '0' or burst_size /= "0000")) then
pending_write <= '1';
end if;
if (PLB_MAddrAck = '1') then
dp_PLB_MSSize <= PLB_MSSize;
end if;
end if;
end process;
process(req_size)
begin
if (req_size(0 to 27) = "000000000000000000000000000") then
burst_last <= '1'; -- one request is ok
else
burst_last <= '0';
end if;
end process;
-- user write data FIFO, for data of bus write request
U_wd_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => wd_fifo_empty_n,
if_read => wd_fifo_pop,
if_dout => wd_fifo_dout,
if_full_n => wd_fifo_full_n,
if_write => wd_fifo_push,
if_din => wd_fifo_din,
use_word => wd_fifo_use_word
);
wd_fifo_push <= BUS_req_push and BUS_req_nRW;
wd_fifo_din <= BUS_WrData;
-- returned bus read data fifo
U_rd_nfa_finals_buckets_if_fifo: component nfa_finals_buckets_if_ap_fifo_uw
generic map(
DATA_WIDTH => PLB_DW,
ADDR_WIDTH => FIFO_ADDR_WIDTH,
DEPTH => FIFO_DEPTH)
port map(
clk => PLB_Clk,
reset => PLB_Rst,
if_empty_n => rd_fifo_empty_n,
if_read => rd_fifo_pop,
if_dout => rd_fifo_dout,
if_full_n => rd_fifo_full_n,
if_write => rd_fifo_push,
if_din => rd_fifo_din,
use_word => rd_fifo_use_word
);
process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
dp_dataConv_rd_conv_mode <= (others =>'0');
dp_dataConv_rd_burst_counter <= (others => '0');
dp_dataConv_rd_burst_counter_reg <= (others => '0');
PLB_MRdDAck_reg <= '0';
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0' and dp_dataConv_rd_conv_mode = "00") then
dp_dataConv_rd_conv_mode <= conv_mode_comb;
dp_dataConv_rd_burst_counter <= conv_counter_comb;
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size = "0000" and dp_dataConv_rd_burst_counter = "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter = "00")))then
dp_dataConv_rd_conv_mode <= "00";
end if;
if (PLB_MRdDAck = '1' and
((pending_rd_req_burst_mode = '1' and (pending_rd_req_burst_size /= "0000" or dp_dataConv_rd_burst_counter /= "00")) or
(pending_rd_req_burst_mode = '0' and dp_dataConv_rd_burst_counter /= "00")))then
if (dp_dataConv_rd_burst_counter = "00") then
if (dp_dataConv_rd_conv_mode = "01") then -- 128/32
dp_dataConv_rd_burst_counter <= "11";
elsif (dp_dataConv_rd_conv_mode(1) = '1') then -- 64/32 or 128/64
dp_dataConv_rd_burst_counter <= "01";
end if;
else
dp_dataConv_rd_burst_counter <= dp_dataConv_rd_burst_counter -1;
end if;
end if;
dp_dataConv_rd_burst_counter_reg <= dp_dataConv_rd_burst_counter;
PLB_MRdDAck_reg <= PLB_MRdDAck;
end if;
end process;
rd_fifo_push <= '1' when PLB_MRdDAck_reg = '1' and dp_dataConv_rd_burst_counter_reg = "00" else '0';
process(PLB_MRdDBus)
variable i: integer;
begin
-- change to little endian
for i in 0 to C_PLB_DWIDTH-1 loop
PLB_MRdDBus_reverse(i) <= PLB_MRdDBus(i);
end loop;
end process;
process(PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
rd_fifo_din <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MRdDAck = '1') then
case dp_dataConv_rd_conv_mode is
when "00" => rd_fifo_din <= PLB_MRdDBus_reverse;
when "10" | "11" =>
if (dp_dataConv_rd_burst_counter = "00") then
rd_fifo_din(PLB_DW-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
else
rd_fifo_din(PLB_DW/2-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/2-1 downto 0);
end if;
when "01" =>
case dp_dataConv_rd_burst_counter is
when "00" =>
rd_fifo_din(PLB_DW-1 downto PLB_DW*3/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "01" =>
rd_fifo_din(PLB_DW*3/4-1 downto PLB_DW/2) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "10" =>
rd_fifo_din(PLB_DW/2-1 downto PLB_DW/4) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when "11" =>
rd_fifo_din(PLB_DW/4-1 downto 0) <= PLB_MRdDBus_reverse(PLB_DW/4-1 downto 0);
when others => null;
end case;
when others => null;
end case;
end if;
end if;
end process;
rd_fifo_pop <= BUS_rsp_pop;
pending_read_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_rd_req_burst_mode <= '0';
pending_rd_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '0') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_rd_req_burst_mode <= burst_mode;
end if;
pending_rd_req_burst_size <= burst_size;
elsif (PLB_MRdDAck = '1' and pending_rd_req_burst_mode = '1') then
if (dp_dataConv_rd_burst_counter = "00") then
pending_rd_req_burst_size <= pending_rd_req_burst_size - 1;
if (pending_rd_req_burst_size = "0000") then
pending_rd_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
pending_write_req_p: process (PLB_Clk, PLB_Rst)
begin
if (PLB_Rst = '1') then
pending_wr_req_burst_mode <= '0';
pending_wr_req_burst_size <= (others => '0');
elsif (PLB_Clk'event and PLB_Clk = '1') then
if (PLB_MAddrAck = '1' and req_nRW = '1') then
if (burst_mode = '1' and burst_size /= "0000") then
pending_wr_req_burst_mode <= '1';
end if;
pending_wr_req_burst_size <= burst_size;
if (PLB_MWrDAck = '1') then
if (conv_counter_comb = "00") then
pending_wr_req_burst_size <= burst_size -1;
else
pending_wr_req_burst_size <= burst_size;
end if;
end if;
elsif (PLB_MWrDAck = '1' and pending_wr_req_burst_mode = '1') then
if (dp_dataConv_wd_burst_counter = "00") then
pending_wr_req_burst_size <= pending_wr_req_burst_size - 1;
if (pending_wr_req_burst_size = "0000") then
pending_wr_req_burst_mode <= '0';
end if;
end if;
end if;
end if;
end process;
end IMP;
|
-- file: player/calculate_position.vhd
-- authors: Alexandre Medeiros and Gabriel Lopes
--
-- A Flappy bird implementation in VHDL for a Digital Circuits course at
-- Unicamp.
--
-- Calculate current position based on internal register for position and
-- current speed value.
library ieee ;
use ieee.std_logic_1164.all ;
entity calculate_position is
generic (
V_RES : natural := 96 -- Vertical Resolution
) ;
port (
jump : in std_logic ;
gravity : in integer range 0 to V_RES - 1 ;
position : out integer range 0 to V_RES - 1 ;
clock : in std_logic ;
enable : in std_logic ;
reset : in std_logic
) ;
end calculate_position ;
architecture behavior of calculate_position is
--signal y: integer range 0 to V_RES - 1 := V_RES / 2 ;
signal my_speed : integer range - V_RES to V_RES - 1 ;
begin
process (clock, reset)
variable y: integer range 0 to V_RES - 1 := V_RES / 2 ;
begin
if reset = '1' then
y := V_RES / 2 ;
elsif enable = '1' and rising_edge(clock) then
y := y + my_speed ;
end if;
position <= y ;
end process;
process (clock, reset)
variable sp : integer range - V_RES to V_RES - 1 := -5 ;
begin
if reset = '1' then
sp := -5 ;
elsif enable = '1' and rising_edge(clock) then
if jump = '1' then
sp := -5 ;
else
sp := sp + gravity ;
end if ;
end if ;
my_speed <= sp;
end process ;
end behavior;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.fpupack.all;
entity mul_24 is
port(
clk_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
end mul_24;
architecture rtl of mul_24 is
signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_fract_o: std_logic_vector(2*FRAC_WIDTH+1 downto 0);
signal s_start_i, s_ready_o : std_logic;
signal a_h, a_l, b_h, b_l : std_logic_vector(11 downto 0);
signal a_h_h, a_h_l, b_h_h, b_h_l, a_l_h, a_l_l, b_l_h, b_l_l : std_logic_vector(5 downto 0);
type op_6 is array (7 downto 0) of std_logic_vector(5 downto 0);
type prod_6 is array (3 downto 0) of op_6;
type prod_48 is array (4 downto 0) of std_logic_vector(47 downto 0);
type sum_24 is array (3 downto 0) of std_logic_vector(23 downto 0);
type a is array (3 downto 0) of std_logic_vector(23 downto 0);
type prod_24 is array (3 downto 0) of a;
signal prod : prod_6;
signal sum : sum_24;
signal prod_a_b : prod_48;
signal count : integer range 0 to 4;
type t_state is (waiting,busy);
signal s_state : t_state;
signal prod2 : prod_24;
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_start_i<=start_i;
end if;
end process;
-- Output Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
ready_o<=s_ready_o;
-- end if;
--end process;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
count <= 0;
elsif count=4 and s_state=busy then
s_state <= waiting;
s_ready_o <= '1';
count <=0;
elsif s_state=busy then
count <= count + 1;
else
s_state <= waiting;
s_ready_o <= '0';
end if;
end if;
end process;
s_sign_o <= s_signa_i xor s_signb_i;
--"000000000000"
-- A = A_h x 2^N + A_l , B = B_h x 2^N + B_l
-- A x B = A_hxB_hx2^2N + (A_h xB_l + A_lxB_h)2^N + A_lxB_l
a_h <= s_fracta_i(23 downto 12);
a_l <= s_fracta_i(11 downto 0);
b_h <= s_fractb_i(23 downto 12);
b_l <= s_fractb_i(11 downto 0);
a_h_h <= a_h(11 downto 6);
a_h_l <= a_h(5 downto 0);
b_h_h <= b_h(11 downto 6);
b_h_l <= b_h(5 downto 0);
a_l_h <= a_l(11 downto 6);
a_l_l <= a_l(5 downto 0);
b_l_h <= b_l(11 downto 6);
b_l_l <= b_l(5 downto 0);
prod(0)(0) <= a_h_h; prod(0)(1) <= b_h_h;
prod(0)(2) <= a_h_h; prod(0)(3) <= b_h_l;
prod(0)(4) <= a_h_l; prod(0)(5) <= b_h_h;
prod(0)(6) <= a_h_l; prod(0)(7) <= b_h_l;
prod(1)(0) <= a_h_h; prod(1)(1) <= b_l_h;
prod(1)(2) <= a_h_h; prod(1)(3) <= b_l_l;
prod(1)(4) <= a_h_l; prod(1)(5) <= b_l_h;
prod(1)(6) <= a_h_l; prod(1)(7) <= b_l_l;
prod(2)(0) <= a_l_h; prod(2)(1) <= b_h_h;
prod(2)(2) <= a_l_h; prod(2)(3) <= b_h_l;
prod(2)(4) <= a_l_l; prod(2)(5) <= b_h_h;
prod(2)(6) <= a_l_l; prod(2)(7) <= b_h_l;
prod(3)(0) <= a_l_h; prod(3)(1) <= b_l_h;
prod(3)(2) <= a_l_h; prod(3)(3) <= b_l_l;
prod(3)(4) <= a_l_l; prod(3)(5) <= b_l_h;
prod(3)(6) <= a_l_l; prod(3)(7) <= b_l_l;
process(clk_i)
begin
if rising_edge(clk_i) then
if count < 4 then
prod2(count)(0) <= (prod(count)(0)*prod(count)(1))&"000000000000";
prod2(count)(1) <= "000000"&(prod(count)(2)*prod(count)(3))&"000000";
prod2(count)(2) <= "000000"&(prod(count)(4)*prod(count)(5))&"000000";
prod2(count)(3) <= "000000000000"&(prod(count)(6)*prod(count)(7));
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if count > 0 and s_state=busy then
sum(count-1) <= prod2(count-1)(0) + prod2(count-1)(1) + prod2(count-1)(2) + prod2(count-1)(3);
end if;
end if;
end process;
-- Last stage
prod_a_b(0) <= sum(0)&"000000000000000000000000";
prod_a_b(1) <= "000000000000"&sum(1)&"000000000000";
prod_a_b(2) <= "000000000000"&sum(2)&"000000000000";
prod_a_b(3) <= "000000000000000000000000"&sum(3);
prod_a_b(4) <= prod_a_b(0) + prod_a_b(1) + prod_a_b(2) + prod_a_b(3);
s_fract_o <= prod_a_b(4);
end rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.fpupack.all;
entity mul_24 is
port(
clk_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
end mul_24;
architecture rtl of mul_24 is
signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_fract_o: std_logic_vector(2*FRAC_WIDTH+1 downto 0);
signal s_start_i, s_ready_o : std_logic;
signal a_h, a_l, b_h, b_l : std_logic_vector(11 downto 0);
signal a_h_h, a_h_l, b_h_h, b_h_l, a_l_h, a_l_l, b_l_h, b_l_l : std_logic_vector(5 downto 0);
type op_6 is array (7 downto 0) of std_logic_vector(5 downto 0);
type prod_6 is array (3 downto 0) of op_6;
type prod_48 is array (4 downto 0) of std_logic_vector(47 downto 0);
type sum_24 is array (3 downto 0) of std_logic_vector(23 downto 0);
type a is array (3 downto 0) of std_logic_vector(23 downto 0);
type prod_24 is array (3 downto 0) of a;
signal prod : prod_6;
signal sum : sum_24;
signal prod_a_b : prod_48;
signal count : integer range 0 to 4;
type t_state is (waiting,busy);
signal s_state : t_state;
signal prod2 : prod_24;
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_start_i<=start_i;
end if;
end process;
-- Output Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
ready_o<=s_ready_o;
-- end if;
--end process;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
count <= 0;
elsif count=4 and s_state=busy then
s_state <= waiting;
s_ready_o <= '1';
count <=0;
elsif s_state=busy then
count <= count + 1;
else
s_state <= waiting;
s_ready_o <= '0';
end if;
end if;
end process;
s_sign_o <= s_signa_i xor s_signb_i;
--"000000000000"
-- A = A_h x 2^N + A_l , B = B_h x 2^N + B_l
-- A x B = A_hxB_hx2^2N + (A_h xB_l + A_lxB_h)2^N + A_lxB_l
a_h <= s_fracta_i(23 downto 12);
a_l <= s_fracta_i(11 downto 0);
b_h <= s_fractb_i(23 downto 12);
b_l <= s_fractb_i(11 downto 0);
a_h_h <= a_h(11 downto 6);
a_h_l <= a_h(5 downto 0);
b_h_h <= b_h(11 downto 6);
b_h_l <= b_h(5 downto 0);
a_l_h <= a_l(11 downto 6);
a_l_l <= a_l(5 downto 0);
b_l_h <= b_l(11 downto 6);
b_l_l <= b_l(5 downto 0);
prod(0)(0) <= a_h_h; prod(0)(1) <= b_h_h;
prod(0)(2) <= a_h_h; prod(0)(3) <= b_h_l;
prod(0)(4) <= a_h_l; prod(0)(5) <= b_h_h;
prod(0)(6) <= a_h_l; prod(0)(7) <= b_h_l;
prod(1)(0) <= a_h_h; prod(1)(1) <= b_l_h;
prod(1)(2) <= a_h_h; prod(1)(3) <= b_l_l;
prod(1)(4) <= a_h_l; prod(1)(5) <= b_l_h;
prod(1)(6) <= a_h_l; prod(1)(7) <= b_l_l;
prod(2)(0) <= a_l_h; prod(2)(1) <= b_h_h;
prod(2)(2) <= a_l_h; prod(2)(3) <= b_h_l;
prod(2)(4) <= a_l_l; prod(2)(5) <= b_h_h;
prod(2)(6) <= a_l_l; prod(2)(7) <= b_h_l;
prod(3)(0) <= a_l_h; prod(3)(1) <= b_l_h;
prod(3)(2) <= a_l_h; prod(3)(3) <= b_l_l;
prod(3)(4) <= a_l_l; prod(3)(5) <= b_l_h;
prod(3)(6) <= a_l_l; prod(3)(7) <= b_l_l;
process(clk_i)
begin
if rising_edge(clk_i) then
if count < 4 then
prod2(count)(0) <= (prod(count)(0)*prod(count)(1))&"000000000000";
prod2(count)(1) <= "000000"&(prod(count)(2)*prod(count)(3))&"000000";
prod2(count)(2) <= "000000"&(prod(count)(4)*prod(count)(5))&"000000";
prod2(count)(3) <= "000000000000"&(prod(count)(6)*prod(count)(7));
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if count > 0 and s_state=busy then
sum(count-1) <= prod2(count-1)(0) + prod2(count-1)(1) + prod2(count-1)(2) + prod2(count-1)(3);
end if;
end if;
end process;
-- Last stage
prod_a_b(0) <= sum(0)&"000000000000000000000000";
prod_a_b(1) <= "000000000000"&sum(1)&"000000000000";
prod_a_b(2) <= "000000000000"&sum(2)&"000000000000";
prod_a_b(3) <= "000000000000000000000000"&sum(3);
prod_a_b(4) <= prod_a_b(0) + prod_a_b(1) + prod_a_b(2) + prod_a_b(3);
s_fract_o <= prod_a_b(4);
end rtl;
|
-------------------------------------------------------------------------------
--
-- Project: <Floating Point Unit Core>
--
-- Description: multiplication entity for the multiplication unit
-------------------------------------------------------------------------------
--
-- 100101011010011100100
-- 110000111011100100000
-- 100000111011000101101
-- 100010111100101111001
-- 110000111011101101001
-- 010000001011101001010
-- 110100111001001100001
-- 110111010000001100111
-- 110110111110001011101
-- 101110110010111101000
-- 100000010111000000000
--
-- Author: Jidan Al-eryani
-- E-mail: [email protected]
--
-- Copyright (C) 2006
--
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR
-- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
-- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
library ieee ;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library work;
use work.fpupack.all;
entity mul_24 is
port(
clk_i : in std_logic;
fracta_i : in std_logic_vector(FRAC_WIDTH downto 0); -- hidden(1) & fraction(23)
fractb_i : in std_logic_vector(FRAC_WIDTH downto 0);
signa_i : in std_logic;
signb_i : in std_logic;
start_i : in std_logic;
fract_o : out std_logic_vector(2*FRAC_WIDTH+1 downto 0);
sign_o : out std_logic;
ready_o : out std_logic
);
end mul_24;
architecture rtl of mul_24 is
signal s_fracta_i, s_fractb_i : std_logic_vector(FRAC_WIDTH downto 0);
signal s_signa_i, s_signb_i, s_sign_o : std_logic;
signal s_fract_o: std_logic_vector(2*FRAC_WIDTH+1 downto 0);
signal s_start_i, s_ready_o : std_logic;
signal a_h, a_l, b_h, b_l : std_logic_vector(11 downto 0);
signal a_h_h, a_h_l, b_h_h, b_h_l, a_l_h, a_l_l, b_l_h, b_l_l : std_logic_vector(5 downto 0);
type op_6 is array (7 downto 0) of std_logic_vector(5 downto 0);
type prod_6 is array (3 downto 0) of op_6;
type prod_48 is array (4 downto 0) of std_logic_vector(47 downto 0);
type sum_24 is array (3 downto 0) of std_logic_vector(23 downto 0);
type a is array (3 downto 0) of std_logic_vector(23 downto 0);
type prod_24 is array (3 downto 0) of a;
signal prod : prod_6;
signal sum : sum_24;
signal prod_a_b : prod_48;
signal count : integer range 0 to 4;
type t_state is (waiting,busy);
signal s_state : t_state;
signal prod2 : prod_24;
begin
-- Input Register
process(clk_i)
begin
if rising_edge(clk_i) then
s_fracta_i <= fracta_i;
s_fractb_i <= fractb_i;
s_signa_i<= signa_i;
s_signb_i<= signb_i;
s_start_i<=start_i;
end if;
end process;
-- Output Register
--process(clk_i)
--begin
-- if rising_edge(clk_i) then
fract_o <= s_fract_o;
sign_o <= s_sign_o;
ready_o<=s_ready_o;
-- end if;
--end process;
-- FSM
process(clk_i)
begin
if rising_edge(clk_i) then
if s_start_i ='1' then
s_state <= busy;
count <= 0;
elsif count=4 and s_state=busy then
s_state <= waiting;
s_ready_o <= '1';
count <=0;
elsif s_state=busy then
count <= count + 1;
else
s_state <= waiting;
s_ready_o <= '0';
end if;
end if;
end process;
s_sign_o <= s_signa_i xor s_signb_i;
--"000000000000"
-- A = A_h x 2^N + A_l , B = B_h x 2^N + B_l
-- A x B = A_hxB_hx2^2N + (A_h xB_l + A_lxB_h)2^N + A_lxB_l
a_h <= s_fracta_i(23 downto 12);
a_l <= s_fracta_i(11 downto 0);
b_h <= s_fractb_i(23 downto 12);
b_l <= s_fractb_i(11 downto 0);
a_h_h <= a_h(11 downto 6);
a_h_l <= a_h(5 downto 0);
b_h_h <= b_h(11 downto 6);
b_h_l <= b_h(5 downto 0);
a_l_h <= a_l(11 downto 6);
a_l_l <= a_l(5 downto 0);
b_l_h <= b_l(11 downto 6);
b_l_l <= b_l(5 downto 0);
prod(0)(0) <= a_h_h; prod(0)(1) <= b_h_h;
prod(0)(2) <= a_h_h; prod(0)(3) <= b_h_l;
prod(0)(4) <= a_h_l; prod(0)(5) <= b_h_h;
prod(0)(6) <= a_h_l; prod(0)(7) <= b_h_l;
prod(1)(0) <= a_h_h; prod(1)(1) <= b_l_h;
prod(1)(2) <= a_h_h; prod(1)(3) <= b_l_l;
prod(1)(4) <= a_h_l; prod(1)(5) <= b_l_h;
prod(1)(6) <= a_h_l; prod(1)(7) <= b_l_l;
prod(2)(0) <= a_l_h; prod(2)(1) <= b_h_h;
prod(2)(2) <= a_l_h; prod(2)(3) <= b_h_l;
prod(2)(4) <= a_l_l; prod(2)(5) <= b_h_h;
prod(2)(6) <= a_l_l; prod(2)(7) <= b_h_l;
prod(3)(0) <= a_l_h; prod(3)(1) <= b_l_h;
prod(3)(2) <= a_l_h; prod(3)(3) <= b_l_l;
prod(3)(4) <= a_l_l; prod(3)(5) <= b_l_h;
prod(3)(6) <= a_l_l; prod(3)(7) <= b_l_l;
process(clk_i)
begin
if rising_edge(clk_i) then
if count < 4 then
prod2(count)(0) <= (prod(count)(0)*prod(count)(1))&"000000000000";
prod2(count)(1) <= "000000"&(prod(count)(2)*prod(count)(3))&"000000";
prod2(count)(2) <= "000000"&(prod(count)(4)*prod(count)(5))&"000000";
prod2(count)(3) <= "000000000000"&(prod(count)(6)*prod(count)(7));
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if count > 0 and s_state=busy then
sum(count-1) <= prod2(count-1)(0) + prod2(count-1)(1) + prod2(count-1)(2) + prod2(count-1)(3);
end if;
end if;
end process;
-- Last stage
prod_a_b(0) <= sum(0)&"000000000000000000000000";
prod_a_b(1) <= "000000000000"&sum(1)&"000000000000";
prod_a_b(2) <= "000000000000"&sum(2)&"000000000000";
prod_a_b(3) <= "000000000000000000000000"&sum(3);
prod_a_b(4) <= prod_a_b(0) + prod_a_b(1) + prod_a_b(2) + prod_a_b(3);
s_fract_o <= prod_a_b(4);
end rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:g8_to_rgb888:1.0
-- IP Revision: 2
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_g8_to_rgb888_0_0 IS
PORT (
g8 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END system_g8_to_rgb888_0_0;
ARCHITECTURE system_g8_to_rgb888_0_0_arch OF system_g8_to_rgb888_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_g8_to_rgb888_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT g8_to_rgb888 IS
PORT (
g8 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
rgb888 : OUT STD_LOGIC_VECTOR(23 DOWNTO 0)
);
END COMPONENT g8_to_rgb888;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF system_g8_to_rgb888_0_0_arch: ARCHITECTURE IS "g8_to_rgb888,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF system_g8_to_rgb888_0_0_arch : ARCHITECTURE IS "system_g8_to_rgb888_0_0,g8_to_rgb888,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF system_g8_to_rgb888_0_0_arch: ARCHITECTURE IS "system_g8_to_rgb888_0_0,g8_to_rgb888,{x_ipProduct=Vivado 2016.4,x_ipVendor=xilinx.com,x_ipLibrary=user,x_ipName=g8_to_rgb888,x_ipVersion=1.0,x_ipCoreRevision=2,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED}";
BEGIN
U0 : g8_to_rgb888
PORT MAP (
g8 => g8,
rgb888 => rgb888
);
END system_g8_to_rgb888_0_0_arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
pull_sense : out std_logic;
c2n_motor : in std_logic;
c2n_sense : in std_logic;
c2n_read : in std_logic;
c2n_write : in std_logic );
end c2n_record;
architecture gideon of c2n_record is
signal stream_en : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal sel : std_logic;
signal read_s : std_logic;
signal read_c : std_logic;
signal read_d : std_logic;
signal read_event : std_logic;
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal diff : unsigned(23 downto 0);
signal remain : unsigned(2 downto 0);
signal error : std_logic;
signal irq_en : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_din : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 63;
type t_state is (idle, listen, encode, multi1, multi2, multi3);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of read_c : signal is "no";
begin
pull_sense <= sel and enabled;
filt: entity work.spike_filter generic map (10) port map(clock, read_s, read_c);
process(clock)
variable v_diff : unsigned(10 downto 0);
begin
if rising_edge(clock) then
if fifo_full='1' and enabled='1' then
error <= '1';
end if;
-- signal capture
stream_en <= c2n_sense and enabled and c2n_motor;
read_s <= (c2n_read and not sel) or (c2n_write and sel);
read_d <= read_c;
case mode is
when "00" =>
read_event <= read_c and not read_d; -- rising edge
when "01" =>
read_event <= not read_c and read_d; -- falling edge
when others =>
read_event <= read_c xor read_d; -- both edges
end case;
-- filter for false pulses
-- if counter(23 downto 4) = X"00000" then
-- read_event <= '0';
-- end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(0)='0' and enabled='1' then -- getting disabled
read_event <= '1'; -- why??
end if;
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(5 downto 4);
sel <= req.data(6);
irq_en <= req.data(7);
end if;
elsif req.read='1' then
resp.ack <= '1';
if req.address(11)='0' then
resp.data <= status;
else
resp.data <= fifo_dout;
end if;
end if;
resp.irq <= irq_en and fifo_almostfull;
-- listening process
if stream_en='1' then
if phi2_tick='1' then
counter <= counter + 1;
end if;
else
counter <= (others => '0');
end if;
fifo_write <= '0';
case state is
when idle =>
if stream_en='1' then
state <= listen;
end if;
when listen =>
if read_event='1' then
diff <= counter;
if phi2_tick='1' then
counter <= to_unsigned(1, counter'length);
else
counter <= to_unsigned(0, counter'length);
end if;
state <= encode;
elsif enabled='0' then
state <= idle;
end if;
when encode =>
fifo_write <= '1';
if diff > 2040 then
fifo_din <= X"00";
state <= multi1;
else
v_diff := diff(10 downto 0) + remain;
if v_diff(10 downto 3) = X"00" then
fifo_din <= X"01";
else
fifo_din <= std_logic_vector(v_diff(10 downto 3));
end if;
remain <= v_diff(2 downto 0);
state <= listen;
end if;
when multi1 =>
fifo_din <= std_logic_vector(diff(7 downto 0));
fifo_write <= '1';
state <= multi2;
when multi2 =>
fifo_din <= std_logic_vector(diff(15 downto 8));
fifo_write <= '1';
state <= multi3;
when multi3 =>
fifo_din <= std_logic_vector(diff(23 downto 16));
fifo_write <= '1';
state <= listen;
when others =>
null;
end case;
if reset='1' then
fifo_din <= (others => '0');
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
mode <= "00";
sel <= '0';
remain <= "000";
irq_en <= '0';
end if;
end if;
end process;
fifo_read <= '1' when req.read='1' and req.address(11)='1' else '0';
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 512,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => fifo_din,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= not fifo_empty;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when listen,
"11" when others;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
pull_sense : out std_logic;
c2n_motor : in std_logic;
c2n_sense : in std_logic;
c2n_read : in std_logic;
c2n_write : in std_logic );
end c2n_record;
architecture gideon of c2n_record is
signal stream_en : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal sel : std_logic;
signal read_s : std_logic;
signal read_c : std_logic;
signal read_d : std_logic;
signal read_event : std_logic;
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal diff : unsigned(23 downto 0);
signal remain : unsigned(2 downto 0);
signal error : std_logic;
signal irq_en : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_din : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 63;
type t_state is (idle, listen, encode, multi1, multi2, multi3);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of read_c : signal is "no";
begin
pull_sense <= sel and enabled;
filt: entity work.spike_filter generic map (10) port map(clock, read_s, read_c);
process(clock)
variable v_diff : unsigned(10 downto 0);
begin
if rising_edge(clock) then
if fifo_full='1' and enabled='1' then
error <= '1';
end if;
-- signal capture
stream_en <= c2n_sense and enabled and c2n_motor;
read_s <= (c2n_read and not sel) or (c2n_write and sel);
read_d <= read_c;
case mode is
when "00" =>
read_event <= read_c and not read_d; -- rising edge
when "01" =>
read_event <= not read_c and read_d; -- falling edge
when others =>
read_event <= read_c xor read_d; -- both edges
end case;
-- filter for false pulses
-- if counter(23 downto 4) = X"00000" then
-- read_event <= '0';
-- end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(0)='0' and enabled='1' then -- getting disabled
read_event <= '1'; -- why??
end if;
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(5 downto 4);
sel <= req.data(6);
irq_en <= req.data(7);
end if;
elsif req.read='1' then
resp.ack <= '1';
if req.address(11)='0' then
resp.data <= status;
else
resp.data <= fifo_dout;
end if;
end if;
resp.irq <= irq_en and fifo_almostfull;
-- listening process
if stream_en='1' then
if phi2_tick='1' then
counter <= counter + 1;
end if;
else
counter <= (others => '0');
end if;
fifo_write <= '0';
case state is
when idle =>
if stream_en='1' then
state <= listen;
end if;
when listen =>
if read_event='1' then
diff <= counter;
if phi2_tick='1' then
counter <= to_unsigned(1, counter'length);
else
counter <= to_unsigned(0, counter'length);
end if;
state <= encode;
elsif enabled='0' then
state <= idle;
end if;
when encode =>
fifo_write <= '1';
if diff > 2040 then
fifo_din <= X"00";
state <= multi1;
else
v_diff := diff(10 downto 0) + remain;
if v_diff(10 downto 3) = X"00" then
fifo_din <= X"01";
else
fifo_din <= std_logic_vector(v_diff(10 downto 3));
end if;
remain <= v_diff(2 downto 0);
state <= listen;
end if;
when multi1 =>
fifo_din <= std_logic_vector(diff(7 downto 0));
fifo_write <= '1';
state <= multi2;
when multi2 =>
fifo_din <= std_logic_vector(diff(15 downto 8));
fifo_write <= '1';
state <= multi3;
when multi3 =>
fifo_din <= std_logic_vector(diff(23 downto 16));
fifo_write <= '1';
state <= listen;
when others =>
null;
end case;
if reset='1' then
fifo_din <= (others => '0');
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
mode <= "00";
sel <= '0';
remain <= "000";
irq_en <= '0';
end if;
end if;
end process;
fifo_read <= '1' when req.read='1' and req.address(11)='1' else '0';
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 512,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => fifo_din,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= not fifo_empty;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when listen,
"11" when others;
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 242/130/136/1
library work;
use work.io_bus_pkg.all;
entity c2n_record is
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
phi2_tick : in std_logic;
c64_stopped : in std_logic;
pull_sense : out std_logic;
c2n_motor : in std_logic;
c2n_sense : in std_logic;
c2n_read : in std_logic;
c2n_write : in std_logic );
end c2n_record;
architecture gideon of c2n_record is
signal stream_en : std_logic;
signal mode : std_logic_vector(1 downto 0);
signal sel : std_logic;
signal read_s : std_logic;
signal read_c : std_logic;
signal read_d : std_logic;
signal read_event : std_logic;
signal enabled : std_logic;
signal counter : unsigned(23 downto 0);
signal diff : unsigned(23 downto 0);
signal remain : unsigned(2 downto 0);
signal error : std_logic;
signal irq_en : std_logic;
signal status : std_logic_vector(7 downto 0);
signal fifo_din : std_logic_vector(7 downto 0);
signal fifo_dout : std_logic_vector(7 downto 0);
signal fifo_read : std_logic;
signal fifo_full : std_logic;
signal fifo_empty : std_logic;
signal fifo_almostfull : std_logic;
signal fifo_flush : std_logic;
signal fifo_write : std_logic;
signal toggle : std_logic;
signal cnt2 : integer range 0 to 63;
type t_state is (idle, listen, encode, multi1, multi2, multi3);
signal state : t_state;
signal state_enc : std_logic_vector(1 downto 0);
attribute register_duplication : string;
attribute register_duplication of stream_en : signal is "no";
attribute register_duplication of read_c : signal is "no";
begin
pull_sense <= sel and enabled;
filt: entity work.spike_filter generic map (10) port map(clock, read_s, read_c);
process(clock)
variable v_diff : unsigned(10 downto 0);
begin
if rising_edge(clock) then
if fifo_full='1' and enabled='1' then
error <= '1';
end if;
-- signal capture
stream_en <= c2n_sense and enabled and c2n_motor;
read_s <= (c2n_read and not sel) or (c2n_write and sel);
read_d <= read_c;
case mode is
when "00" =>
read_event <= read_c and not read_d; -- rising edge
when "01" =>
read_event <= not read_c and read_d; -- falling edge
when others =>
read_event <= read_c xor read_d; -- both edges
end case;
-- filter for false pulses
-- if counter(23 downto 4) = X"00000" then
-- read_event <= '0';
-- end if;
-- bus handling
resp <= c_io_resp_init;
if req.write='1' then
resp.ack <= '1'; -- ack for fifo write as well.
if req.address(11)='0' then
enabled <= req.data(0);
if req.data(0)='0' and enabled='1' then -- getting disabled
read_event <= '1'; -- why??
end if;
if req.data(1)='1' then
error <= '0';
end if;
fifo_flush <= req.data(2);
mode <= req.data(5 downto 4);
sel <= req.data(6);
irq_en <= req.data(7);
end if;
elsif req.read='1' then
resp.ack <= '1';
if req.address(11)='0' then
resp.data <= status;
else
resp.data <= fifo_dout;
end if;
end if;
resp.irq <= irq_en and fifo_almostfull;
-- listening process
if stream_en='1' then
if phi2_tick='1' then
counter <= counter + 1;
end if;
else
counter <= (others => '0');
end if;
fifo_write <= '0';
case state is
when idle =>
if stream_en='1' then
state <= listen;
end if;
when listen =>
if read_event='1' then
diff <= counter;
if phi2_tick='1' then
counter <= to_unsigned(1, counter'length);
else
counter <= to_unsigned(0, counter'length);
end if;
state <= encode;
elsif enabled='0' then
state <= idle;
end if;
when encode =>
fifo_write <= '1';
if diff > 2040 then
fifo_din <= X"00";
state <= multi1;
else
v_diff := diff(10 downto 0) + remain;
if v_diff(10 downto 3) = X"00" then
fifo_din <= X"01";
else
fifo_din <= std_logic_vector(v_diff(10 downto 3));
end if;
remain <= v_diff(2 downto 0);
state <= listen;
end if;
when multi1 =>
fifo_din <= std_logic_vector(diff(7 downto 0));
fifo_write <= '1';
state <= multi2;
when multi2 =>
fifo_din <= std_logic_vector(diff(15 downto 8));
fifo_write <= '1';
state <= multi3;
when multi3 =>
fifo_din <= std_logic_vector(diff(23 downto 16));
fifo_write <= '1';
state <= listen;
when others =>
null;
end case;
if reset='1' then
fifo_din <= (others => '0');
enabled <= '0';
counter <= (others => '0');
toggle <= '0';
error <= '0';
mode <= "00";
sel <= '0';
remain <= "000";
irq_en <= '0';
end if;
end if;
end process;
fifo_read <= '1' when req.read='1' and req.address(11)='1' else '0';
fifo: entity work.sync_fifo
generic map (
g_depth => 2048, -- Actual depth.
g_data_width => 8,
g_threshold => 512,
g_storage => "block",
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => fifo_read,
wr_en => fifo_write,
din => fifo_din,
dout => fifo_dout,
flush => fifo_flush,
full => fifo_full,
almost_full => fifo_almostfull,
empty => fifo_empty,
count => open );
status(0) <= enabled;
status(1) <= error;
status(2) <= fifo_full;
status(3) <= fifo_almostfull;
status(4) <= state_enc(0);
status(5) <= state_enc(1);
status(6) <= stream_en;
status(7) <= not fifo_empty;
with state select state_enc <=
"00" when idle,
"01" when multi1,
"01" when multi2,
"01" when multi3,
"10" when listen,
"11" when others;
end gideon;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Nov 10 10:29:04 2004
-- cmd: H:/work/mix_new/MIX/mix_0.pl -strip -nodelta ../genwidth.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-rtl-conf-c.vhd,v 1.2 2004/11/10 09:54:09 wig Exp $
-- $Date: 2004/11/10 09:54:09 $
-- $Log: inst_a_e-rtl-conf-c.vhd,v $
-- Revision 1.2 2004/11/10 09:54:09 wig
-- testcase extended
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.46 2004/08/18 10:45:45 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.32 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_a_e_rtl_conf / inst_a_e
--
configuration inst_a_e_rtl_conf of inst_a_e is
for rtl
-- Generated Configuration
for inst_aa : inst_aa_e
use configuration work.inst_aa_e_rtl_conf;
end for;
for inst_ab : inst_ab_e
use configuration work.inst_ab_e_rtl_conf;
end for;
-- __I_NO_CONFIG_VERILOG --for inst_ac : inst_ac_e
-- __I_NO_CONFIG_VERILOG -- use configuration work.inst_ac_e_rtl_conf;
-- __I_NO_CONFIG_VERILOG --end for;
end for;
end inst_a_e_rtl_conf;
--
-- End of Generated Configuration inst_a_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity cw3 is
port(
LEDG9 : out vl_logic;
UP : in vl_logic;
clk : in vl_logic;
DOWN : in vl_logic;
bcd0 : out vl_logic_vector(3 downto 0);
bcd1 : out vl_logic_vector(3 downto 0);
LED0 : out vl_logic_vector(7 downto 0);
LED1 : out vl_logic_vector(7 downto 0)
);
end cw3;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: icache
-- File: icache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
entity icache is
generic (
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 1 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_ulogic
);
end;
architecture rtl of icache is
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others=>'1');
constant fline : std_logic_vector((ILINE_BITS -1) downto 0) := (others=>'0');
constant SETBITS : integer := log2x(ISETS);
constant ILRUBITS : integer := lru_table(ISETS);
constant LRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant LRAM_BITS : integer := log2(lramsize) + 10;
constant LRAMCS_EN : boolean := false;
subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0);
type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers
type rdatatype is (itag, idata, memory); -- sources during cache read
type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type;
subtype lock_type is std_logic_vector(0 to ISETS-1);
type par_type is array (0 to ISETS-1) of std_logic_vector(1 downto 0);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to ISETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(ILRUBITS-1 downto 0) := lru;
if isetlock = 1 then
unlocked := ISETS-1;
for i in ISETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case ISETS is
when 2 =>
if isetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru;
case ISETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(ILRUBITS-1 downto 0);
return(new_lru);
end;
type icache_control_type is record -- all registers
req, burst, holdn : std_ulogic;
overrun : std_ulogic; --
underrun : std_ulogic; --
istate : std_logic_vector(1 downto 0); -- FSM vector
waddress : std_logic_vector(31 downto 2); -- write address buffer
valid : std_logic_vector(ilinesize-1 downto 0); -- valid bits
hit : std_ulogic;
su : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
flush3 : std_ulogic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_ulogic;
rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter
lrr : std_ulogic;
setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
diagset : std_logic_vector(log2x(ISETS)-1 downto 0);
lock : std_ulogic;
end record;
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(IOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1;
lru : lru_array;
end record;
signal r, c : icache_control_type; -- r is registers, c is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant icfg : std_logic_vector(31 downto 0) :=
cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0, lram, lramsize, lramstart, 0);
begin
ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn)
variable rdatasel : rdatatype;
variable twrite, diagen, dwrite : std_ulogic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : cdatatype;
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((ilinesize -1) downto 0);
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_ulogic;
variable enable : std_ulogic;
variable error : std_ulogic;
variable whit, hit, valid : std_ulogic;
variable cacheon : std_ulogic;
variable v : icache_control_type;
variable branch : std_ulogic;
variable eholdn : std_ulogic;
variable mds, write : std_ulogic;
variable memaddr : std_logic_vector(31 downto 2);
variable set : integer range 0 to MAXSETS-1;
variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
variable ctwrite, cdwrite, validv : std_logic_vector(0 to MAXSETS-1);
variable wlrr : std_ulogic;
variable vl : lru_reg_type;
variable vdiagset, rdiagset : integer range 0 to ISETS-1;
variable lock : std_logic_vector(0 to ISETS-1);
variable wlock, sidle : std_ulogic;
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable lramacc, ilramwr, lramcs : std_ulogic;
begin
-- init local variables
v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl;
vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW);
mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
v.flush3 := r.flush2; sidle := '0';
if icen /= 0 then
cacheon := dco.icdiag.cctrl.ics(0) and not r.flush;
else cacheon := '0'; end if;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
wtag(TAG_HIGH downto TAG_LOW) := r.waddress(TAG_HIGH downto TAG_LOW);
wlrr := r.lrr; wlock := r.lock;
set := 0; ctwrite := (others => '0'); cdwrite := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0'); ilramwr := '0';
lramacc := '0'; lramcs := '0';
-- random replacement counter
if ISETS > 1 then
if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
if isetlock = 1 then
for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop;
end if;
--local ram access
if (lram = 1) and (ici.fpc(31 downto 24) = LRAM_START) then lramacc := '1'; end if;
-- generate cache hit and valid bits
hit := '0';
for i in ISETS-1 downto 0 loop
if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
then hit := not r.flush; set := i; end if;
validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(i)(ilinesize -1 downto 0));
end loop;
if (lramacc = '1') and (ISETS > 1) then set := 1; end if;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
valid := validv(set);
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main state machine
case r.istate is
when "00" => -- main state and cache hit
v.valid := icramo.tag(set)(ilinesize-1 downto 0);
v.hit := hit; v.su := ici.su; sidle := '1';
-- if (ici.inull or eholdn) = '0' then
if eholdn = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := dco.icdiag.cctrl.burst and not lastline;
if (eholdn and not (ici.inull or lramacc)) = '1' then
if not (cacheon and hit and valid) = '1' then
v.istate := "01"; v.req := '1';
v.holdn := '0'; v.overrun := '1';
else
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
v.waddress := ici.fpc(31 downto 2);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
if (ISETS > 1) then
if (irepl = lru) then
vl.set := conv_std_logic_vector(set, SETBITS);
vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW);
end if;
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (((not hit) and (not r.flush)) = '1') then
case irepl is
when rnd =>
if isetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS);
for i in ISETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1));
when lrr =>
v.setrepl := (others => '0');
if isetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS);
else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if;
end case;
end if;
if (isetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
when "01" => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.waddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.inull)) and
not (write or r.underrun);
if mcio.ready = '1' then
-- mds := not (v.overrun and not r.underrun);
mds := not (r.overrun and not r.underrun);
-- v.req := r.burst;
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
if mcio.grant = '1' then
v.req := dco.icdiag.cctrl.burst and r.burst and
(not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and
not (v.underrun and not cacheon);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
if (dco.icdiag.cctrl.ics(0) and not r.flush2) = '1' then
v.istate := "10"; v.holdn := '0';
else
v.istate := "00"; v.flush := r.flush2; v.holdn := '1';
if r.overrun = '1' then taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
end if;
end if;
when "10" => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := "00"; v.flush := r.flush2;
when others => v.istate := "00";
end case;
if mcio.retry = '1' then v.req := '1'; end if;
if lram = 1 then
if LRAMCS_EN then
if taddr(31 downto 24) = LRAM_START then lramcs := '1'; else lramcs := '0'; end if;
else
lramcs := '1';
end if;
end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := write;
if cacheon = '0' then
twrite := '0'; vmask := (others => '0');
elsif (dco.icdiag.cctrl.ics = "01") then
twrite := twrite and r.hit;
vmask := icramo.tag(set)(ilinesize-1 downto 0) or vmaskraw;
else
if r.hit = '1' then vmask := r.valid or vmaskraw;
else vmask := vmaskraw; end if;
end if;
if (mcio.mexc or not mcio.cache) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then
v.valid := vmask; v.hit := '1';
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
if (ISETS > 1) and (irepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
-- cache write signals
if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if;
if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if;
-- diagnostic cache access
if diagen = '1' then
if (ISETS /= 1) then
if (dco.icdiag.ilramen = '1') and (lram = 1) then
v.diagset := conv_std_logic_vector(1, SETBITS);
else
v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW);
end if;
end if;
end if;
case ISETS is
when 1 =>
vdiagset := 0; rdiagset := 0;
when 3 =>
if conv_integer(v.diagset) < 3 then vdiagset := conv_integer(v.diagset); end if;
if conv_integer(r.diagset) < 3 then rdiagset := conv_integer(r.diagset); end if;
when others =>
vdiagset := conv_integer(v.diagset);
rdiagset := conv_integer(r.diagset);
end case;
diagdata := icramo.data(rdiagset);
if diagen = '1' then -- diagnostic or local ram access
taddr(TAG_HIGH downto LINE_LOW) := dco.icdiag.addr(TAG_HIGH downto LINE_LOW);
wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW);
wlrr := dci.maddress(CTAG_LRRPOS);
wlock := dci.maddress(CTAG_LOCKPOS);
if (dco.icdiag.ilramen = '1') and (lram = 1) then
ilramwr := not dco.icdiag.read;
elsif dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
ctwrite := (others => '0'); cdwrite := (others => '0');
ctwrite(vdiagset) := not dco.icdiag.read;
diagdata := icramo.tag(rdiagset);
else
dwrite := not dco.icdiag.read; twrite := '0';
cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read;
ctwrite := (others => '0');
end if;
vmask := dci.maddress(ilinesize -1 downto 0);
v.diagrdy := '1';
end if;
-- select data to return on read access
rdata := icramo.data;
case rdatasel is
when memory => rdata(0) := mcio.data; set := 0;
when others =>
end case;
-- cache flush
if ((ici.flush or dco.icdiag.flush) = '1') and (icen /= 0) then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
end if;
if (r.flush2 = '1') and (icen /= 0) then
twrite := '1'; ctwrite := (others => '1'); vmask := (others => '0');
v.faddr := r.faddr +1; taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := '0'; wlock := '0'; wtag := (others => '0'); v.lrr := '0';
if (r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1)) = '1' then
v.flush2 := '0';
end if;
end if;
-- reset
if rst = '0' then
v.istate := "00"; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0';
v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0');
v.diagset := (others => '0'); v.lock := '0'; v.flush3 := '1';
v.waddress := ici.fpc(31 downto 2); v.lrr := '0';
end if;
if r.flush3 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- Drive signals
c <= v; -- register inputs
cl <= vl; -- lru register inputs
-- tag ram inputs
enable := enable and not dco.icdiag.scanen;
for i in 0 to ISETS-1 loop
tag(i) := (others => '0');
tag(i)(ilinesize-1 downto 0) := vmask;
tag(i)(TAG_HIGH downto TAG_LOW) := wtag;
tag(i)(CTAG_LRRPOS) := wlrr;
tag(i)(CTAG_LOCKPOS) := wlock;
end loop;
icrami.tag <= tag;
icrami.tenable <= enable;
icrami.twrite <= ctwrite;
icrami.flush <= r.flush2;
icrami.dpar <= (others => '0');
icrami.tpar <= (others => (others => '0'));
icrami.ctx <= (others => '0');
-- data ram inputs
icrami.denable <= enable;
icrami.address <= taddr(19+LINE_LOW downto LINE_LOW);
icrami.data <= ddatain;
icrami.dwrite <= cdwrite;
-- local ram inputs
icrami.ldramin.enable <= (dco.icdiag.ilramen or lramcs or lramacc) and not dco.icdiag.scanen;
icrami.ldramin.read <= dco.icdiag.ilramen or lramacc;
icrami.ldramin.write <= ilramwr;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- IU data cache inputs
ico.data <= rdata;
ico.mexc <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
ico.set <= conv_std_logic_vector(set, 2);
ico.cfg <= icfg;
ico.idle <= sidle;
end process;
-- Local registers
regs1 : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
regs2 : if (ISETS > 1) and (irepl = lru) generate
regs2 : process(clk)
begin if rising_edge(clk) then rl <= cl; end if; end process;
end generate;
nolru : if (ISETS = 1) or (irepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((ISETS > 2) and (irepl = lrr)) report
"Wrong instruction cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: icache
-- File: icache.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Modified: Edvin Catovic - Gaisler Research
-- Description: This unit implements the instruction cache controller.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
library gaisler;
use gaisler.libiu.all;
use gaisler.libcache.all;
entity icache is
generic (
icen : integer range 0 to 1 := 0;
irepl : integer range 0 to 2 := 0;
isets : integer range 1 to 4 := 1;
ilinesize : integer range 4 to 8 := 4;
isetsize : integer range 1 to 256 := 1;
isetlock : integer range 0 to 1 := 0;
lram : integer range 0 to 1 := 0;
lramsize : integer range 1 to 512 := 1;
lramstart : integer range 0 to 255 := 16#8e#);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ici : in icache_in_type;
ico : out icache_out_type;
dci : in dcache_in_type;
dco : in dcache_out_type;
mcii : out memory_ic_in_type;
mcio : in memory_ic_out_type;
icrami : out icram_in_type;
icramo : in icram_out_type;
fpuholdn : in std_ulogic
);
end;
architecture rtl of icache is
constant ILINE_BITS : integer := log2(ilinesize);
constant IOFFSET_BITS : integer := 8 +log2(isetsize) - ILINE_BITS;
constant TAG_LOW : integer := IOFFSET_BITS + ILINE_BITS + 2;
constant OFFSET_HIGH : integer := TAG_LOW - 1;
constant OFFSET_LOW : integer := ILINE_BITS + 2;
constant LINE_HIGH : integer := OFFSET_LOW - 1;
constant LINE_LOW : integer := 2;
constant LRR_BIT : integer := TAG_HIGH + 1;
constant lline : std_logic_vector((ILINE_BITS -1) downto 0) := (others=>'1');
constant fline : std_logic_vector((ILINE_BITS -1) downto 0) := (others=>'0');
constant SETBITS : integer := log2x(ISETS);
constant ILRUBITS : integer := lru_table(ISETS);
constant LRAM_START : std_logic_vector(7 downto 0) := conv_std_logic_vector(lramstart, 8);
constant LRAM_BITS : integer := log2(lramsize) + 10;
constant LRAMCS_EN : boolean := false;
subtype lru_type is std_logic_vector(ILRUBITS-1 downto 0);
type lru_array is array (0 to 2**IOFFSET_BITS-1) of lru_type; -- lru registers
type rdatatype is (itag, idata, memory); -- sources during cache read
type lru_table_vector_type is array(0 to 3) of std_logic_vector(4 downto 0);
type lru_table_type is array (0 to 2**IOFFSET_BITS-1) of lru_table_vector_type;
subtype lock_type is std_logic_vector(0 to ISETS-1);
type par_type is array (0 to ISETS-1) of std_logic_vector(1 downto 0);
function lru_set (lru : lru_type; lock : lock_type) return std_logic_vector is
variable xlru : std_logic_vector(4 downto 0);
variable set : std_logic_vector(SETBITS-1 downto 0);
variable xset : std_logic_vector(1 downto 0);
variable unlocked : integer range 0 to ISETS-1;
begin
set := (others => '0'); xlru := (others => '0'); xset := (others => '0');
xlru(ILRUBITS-1 downto 0) := lru;
if isetlock = 1 then
unlocked := ISETS-1;
for i in ISETS-1 downto 0 loop
if lock(i) = '0' then unlocked := i; end if;
end loop;
end if;
case ISETS is
when 2 =>
if isetlock = 1 then
if lock(0) = '1' then xset(0) := '1'; else xset(0) := xlru(0); end if;
else xset(0) := xlru(0); end if;
when 3 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru3_repl_table(conv_integer(xlru)) (0), 2);
end if;
when 4 =>
if isetlock = 1 then
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (unlocked), 2);
else
xset := conv_std_logic_vector(lru4_repl_table(conv_integer(xlru)) (0), 2);
end if;
when others =>
end case;
set := xset(SETBITS-1 downto 0);
return(set);
end;
function lru_calc (lru : lru_type; set : integer) return lru_type is
variable new_lru : lru_type;
variable xnew_lru: std_logic_vector(4 downto 0);
variable xlru : std_logic_vector(4 downto 0);
begin
new_lru := (others => '0'); xnew_lru := (others => '0');
xlru := (others => '0'); xlru(ILRUBITS-1 downto 0) := lru;
case ISETS is
when 2 =>
if set = 0 then xnew_lru(0) := '1'; else xnew_lru(0) := '0'; end if;
when 3 =>
xnew_lru(2 downto 0) := lru_3set_table(conv_integer(lru))(set);
when 4 =>
xnew_lru(4 downto 0) := lru_4set_table(conv_integer(lru))(set);
when others =>
end case;
new_lru := xnew_lru(ILRUBITS-1 downto 0);
return(new_lru);
end;
type icache_control_type is record -- all registers
req, burst, holdn : std_ulogic;
overrun : std_ulogic; --
underrun : std_ulogic; --
istate : std_logic_vector(1 downto 0); -- FSM vector
waddress : std_logic_vector(31 downto 2); -- write address buffer
valid : std_logic_vector(ilinesize-1 downto 0); -- valid bits
hit : std_ulogic;
su : std_ulogic;
flush : std_ulogic; -- flush in progress
flush2 : std_ulogic; -- flush in progress
flush3 : std_ulogic; -- flush in progress
faddr : std_logic_vector(IOFFSET_BITS - 1 downto 0); -- flush address
diagrdy : std_ulogic;
rndcnt : std_logic_vector(log2x(ISETS)-1 downto 0); -- replace counter
lrr : std_ulogic;
setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
diagset : std_logic_vector(log2x(ISETS)-1 downto 0);
lock : std_ulogic;
end record;
type lru_reg_type is record
write : std_ulogic;
waddr : std_logic_vector(IOFFSET_BITS-1 downto 0);
set : std_logic_vector(SETBITS-1 downto 0); --integer range 0 to ISETS-1;
lru : lru_array;
end record;
signal r, c : icache_control_type; -- r is registers, c is combinational
signal rl, cl : lru_reg_type; -- rl is registers, cl is combinational
constant icfg : std_logic_vector(31 downto 0) :=
cache_cfg(irepl, isets, ilinesize, isetsize, isetlock, 0, lram, lramsize, lramstart, 0);
begin
ictrl : process(rst, r, rl, mcio, ici, dci, dco, icramo, fpuholdn)
variable rdatasel : rdatatype;
variable twrite, diagen, dwrite : std_ulogic;
variable taddr : std_logic_vector(TAG_HIGH downto LINE_LOW); -- tag address
variable wtag : std_logic_vector(TAG_HIGH downto TAG_LOW); -- write tag value
variable ddatain : std_logic_vector(31 downto 0);
variable rdata : cdatatype;
variable diagdata : std_logic_vector(31 downto 0);
variable vmaskraw, vmask : std_logic_vector((ilinesize -1) downto 0);
variable xaddr_inc : std_logic_vector((ILINE_BITS -1) downto 0);
variable lastline, nlastline, nnlastline : std_ulogic;
variable enable : std_ulogic;
variable error : std_ulogic;
variable whit, hit, valid : std_ulogic;
variable cacheon : std_ulogic;
variable v : icache_control_type;
variable branch : std_ulogic;
variable eholdn : std_ulogic;
variable mds, write : std_ulogic;
variable memaddr : std_logic_vector(31 downto 2);
variable set : integer range 0 to MAXSETS-1;
variable setrepl : std_logic_vector(log2x(ISETS)-1 downto 0); -- set to replace
variable ctwrite, cdwrite, validv : std_logic_vector(0 to MAXSETS-1);
variable wlrr : std_ulogic;
variable vl : lru_reg_type;
variable vdiagset, rdiagset : integer range 0 to ISETS-1;
variable lock : std_logic_vector(0 to ISETS-1);
variable wlock, sidle : std_ulogic;
variable tag : cdatatype; --std_logic_vector(31 downto 0);
variable lramacc, ilramwr, lramcs : std_ulogic;
begin
-- init local variables
v := r; vl := rl; vl.write := '0'; vl.set := r.setrepl;
vl.waddr := r.waddress(OFFSET_HIGH downto OFFSET_LOW);
mds := '1'; dwrite := '0'; twrite := '0'; diagen := '0'; error := '0';
write := mcio.ready; v.diagrdy := '0'; v.holdn := '1';
v.flush3 := r.flush2; sidle := '0';
if icen /= 0 then
cacheon := dco.icdiag.cctrl.ics(0) and not r.flush;
else cacheon := '0'; end if;
enable := '1'; branch := '0';
eholdn := dco.hold and fpuholdn;
rdatasel := idata; -- read data from cache as default
ddatain := mcio.data; -- load full word from memory
wtag(TAG_HIGH downto TAG_LOW) := r.waddress(TAG_HIGH downto TAG_LOW);
wlrr := r.lrr; wlock := r.lock;
set := 0; ctwrite := (others => '0'); cdwrite := (others => '0');
vdiagset := 0; rdiagset := 0; lock := (others => '0'); ilramwr := '0';
lramacc := '0'; lramcs := '0';
-- random replacement counter
if ISETS > 1 then
if conv_integer(r.rndcnt) = (ISETS - 1) then v.rndcnt := (others => '0');
else v.rndcnt := r.rndcnt + 1; end if;
end if;
-- generate lock bits
if isetlock = 1 then
for i in 0 to ISETS-1 loop lock(i) := icramo.tag(i)(CTAG_LOCKPOS); end loop;
end if;
--local ram access
if (lram = 1) and (ici.fpc(31 downto 24) = LRAM_START) then lramacc := '1'; end if;
-- generate cache hit and valid bits
hit := '0';
for i in ISETS-1 downto 0 loop
if (icramo.tag(i)(TAG_HIGH downto TAG_LOW) = ici.fpc(TAG_HIGH downto TAG_LOW))
then hit := not r.flush; set := i; end if;
validv(i) := genmux(ici.fpc(LINE_HIGH downto LINE_LOW),
icramo.tag(i)(ilinesize -1 downto 0));
end loop;
if (lramacc = '1') and (ISETS > 1) then set := 1; end if;
if ici.fpc(LINE_HIGH downto LINE_LOW) = lline then lastline := '1';
else lastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW) = lline((ILINE_BITS -1) downto 0) then
nlastline := '1';
else nlastline := '0'; end if;
if r.waddress(LINE_HIGH downto LINE_LOW+1) = lline((ILINE_BITS -1) downto 1) then
nnlastline := '1';
else nnlastline := '0'; end if;
valid := validv(set);
xaddr_inc := r.waddress(LINE_HIGH downto LINE_LOW) + 1;
if mcio.ready = '1' then
v.waddress(LINE_HIGH downto LINE_LOW) := xaddr_inc;
end if;
taddr := ici.rpc(TAG_HIGH downto LINE_LOW);
-- main state machine
case r.istate is
when "00" => -- main state and cache hit
v.valid := icramo.tag(set)(ilinesize-1 downto 0);
v.hit := hit; v.su := ici.su; sidle := '1';
-- if (ici.inull or eholdn) = '0' then
if eholdn = '0' then
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
v.burst := dco.icdiag.cctrl.burst and not lastline;
if (eholdn and not (ici.inull or lramacc)) = '1' then
if not (cacheon and hit and valid) = '1' then
v.istate := "01"; v.req := '1';
v.holdn := '0'; v.overrun := '1';
else
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
v.waddress := ici.fpc(31 downto 2);
end if;
if dco.icdiag.enable = '1' then
diagen := '1';
end if;
ddatain := dci.maddress;
if (ISETS > 1) then
if (irepl = lru) then
vl.set := conv_std_logic_vector(set, SETBITS);
vl.waddr := ici.fpc(OFFSET_HIGH downto OFFSET_LOW);
end if;
v.setrepl := conv_std_logic_vector(set, SETBITS);
if (((not hit) and (not r.flush)) = '1') then
case irepl is
when rnd =>
if isetlock = 1 then
if lock(conv_integer(r.rndcnt)) = '0' then v.setrepl := r.rndcnt;
else
v.setrepl := conv_std_logic_vector(ISETS-1, SETBITS);
for i in ISETS-1 downto 0 loop
if (lock(i) = '0') and (i>conv_integer(r.rndcnt)) then
v.setrepl := conv_std_logic_vector(i, SETBITS);
end if;
end loop;
end if;
else
v.setrepl := r.rndcnt;
end if;
when lru =>
v.setrepl := lru_set(rl.lru(conv_integer(ici.fpc(OFFSET_HIGH downto OFFSET_LOW))), lock(0 to ISETS-1));
when lrr =>
v.setrepl := (others => '0');
if isetlock = 1 then
if lock(0) = '1' then v.setrepl(0) := '1';
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
else
v.setrepl(0) := icramo.tag(0)(CTAG_LRRPOS) xor icramo.tag(1)(CTAG_LRRPOS);
end if;
if v.setrepl(0) = '0' then v.lrr := not icramo.tag(0)(CTAG_LRRPOS);
else v.lrr := icramo.tag(0)(CTAG_LRRPOS); end if;
end case;
end if;
if (isetlock = 1) then
if (hit and lock(set)) = '1' then v.lock := '1';
else v.lock := '0'; end if;
end if;
end if;
when "01" => -- streaming: update cache and send data to IU
rdatasel := memory;
taddr(TAG_HIGH downto LINE_LOW) := r.waddress(TAG_HIGH downto LINE_LOW);
branch := (ici.fbranch and r.overrun) or
(ici.rbranch and (not r.overrun));
v.underrun := r.underrun or
(write and ((ici.inull or not eholdn) and (mcio.ready and not (r.overrun and not r.underrun))));
v.overrun := (r.overrun or (eholdn and not ici.inull)) and
not (write or r.underrun);
if mcio.ready = '1' then
-- mds := not (v.overrun and not r.underrun);
mds := not (r.overrun and not r.underrun);
-- v.req := r.burst;
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
if mcio.grant = '1' then
v.req := dco.icdiag.cctrl.burst and r.burst and
(not (nnlastline and mcio.ready)) and (dco.icdiag.cctrl.burst or (not branch)) and
not (v.underrun and not cacheon);
v.burst := v.req and not (nnlastline and mcio.ready);
end if;
v.underrun := (v.underrun or branch) and not v.overrun;
v.holdn := not (v.overrun or v.underrun);
if (mcio.ready = '1') and (r.req = '0') then --(v.burst = '0') then
v.underrun := '0'; v.overrun := '0';
if (dco.icdiag.cctrl.ics(0) and not r.flush2) = '1' then
v.istate := "10"; v.holdn := '0';
else
v.istate := "00"; v.flush := r.flush2; v.holdn := '1';
if r.overrun = '1' then taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
else taddr := ici.rpc(TAG_HIGH downto LINE_LOW); end if;
end if;
end if;
when "10" => -- return to main
taddr := ici.fpc(TAG_HIGH downto LINE_LOW);
v.istate := "00"; v.flush := r.flush2;
when others => v.istate := "00";
end case;
if mcio.retry = '1' then v.req := '1'; end if;
if lram = 1 then
if LRAMCS_EN then
if taddr(31 downto 24) = LRAM_START then lramcs := '1'; else lramcs := '0'; end if;
else
lramcs := '1';
end if;
end if;
-- Generate new valid bits write strobe
vmaskraw := decode(r.waddress(LINE_HIGH downto LINE_LOW));
twrite := write;
if cacheon = '0' then
twrite := '0'; vmask := (others => '0');
elsif (dco.icdiag.cctrl.ics = "01") then
twrite := twrite and r.hit;
vmask := icramo.tag(set)(ilinesize-1 downto 0) or vmaskraw;
else
if r.hit = '1' then vmask := r.valid or vmaskraw;
else vmask := vmaskraw; end if;
end if;
if (mcio.mexc or not mcio.cache) = '1' then
twrite := '0'; dwrite := '0';
else dwrite := twrite; end if;
if twrite = '1' then
v.valid := vmask; v.hit := '1';
if (ISETS > 1) and (irepl = lru) then vl.write := '1'; end if;
end if;
if (ISETS > 1) and (irepl = lru) and (rl.write = '1') then
vl.lru(conv_integer(rl.waddr)) :=
lru_calc(rl.lru(conv_integer(rl.waddr)), conv_integer(rl.set));
end if;
-- cache write signals
if ISETS > 1 then setrepl := r.setrepl; else setrepl := (others => '0'); end if;
if twrite = '1' then ctwrite(conv_integer(setrepl)) := '1'; end if;
if dwrite = '1' then cdwrite(conv_integer(setrepl)) := '1'; end if;
-- diagnostic cache access
if diagen = '1' then
if (ISETS /= 1) then
if (dco.icdiag.ilramen = '1') and (lram = 1) then
v.diagset := conv_std_logic_vector(1, SETBITS);
else
v.diagset := dco.icdiag.addr(SETBITS -1 + TAG_LOW downto TAG_LOW);
end if;
end if;
end if;
case ISETS is
when 1 =>
vdiagset := 0; rdiagset := 0;
when 3 =>
if conv_integer(v.diagset) < 3 then vdiagset := conv_integer(v.diagset); end if;
if conv_integer(r.diagset) < 3 then rdiagset := conv_integer(r.diagset); end if;
when others =>
vdiagset := conv_integer(v.diagset);
rdiagset := conv_integer(r.diagset);
end case;
diagdata := icramo.data(rdiagset);
if diagen = '1' then -- diagnostic or local ram access
taddr(TAG_HIGH downto LINE_LOW) := dco.icdiag.addr(TAG_HIGH downto LINE_LOW);
wtag(TAG_HIGH downto TAG_LOW) := dci.maddress(TAG_HIGH downto TAG_LOW);
wlrr := dci.maddress(CTAG_LRRPOS);
wlock := dci.maddress(CTAG_LOCKPOS);
if (dco.icdiag.ilramen = '1') and (lram = 1) then
ilramwr := not dco.icdiag.read;
elsif dco.icdiag.tag = '1' then
twrite := not dco.icdiag.read; dwrite := '0';
ctwrite := (others => '0'); cdwrite := (others => '0');
ctwrite(vdiagset) := not dco.icdiag.read;
diagdata := icramo.tag(rdiagset);
else
dwrite := not dco.icdiag.read; twrite := '0';
cdwrite := (others => '0'); cdwrite(vdiagset) := not dco.icdiag.read;
ctwrite := (others => '0');
end if;
vmask := dci.maddress(ilinesize -1 downto 0);
v.diagrdy := '1';
end if;
-- select data to return on read access
rdata := icramo.data;
case rdatasel is
when memory => rdata(0) := mcio.data; set := 0;
when others =>
end case;
-- cache flush
if ((ici.flush or dco.icdiag.flush) = '1') and (icen /= 0) then
v.flush := '1'; v.flush2 := '1'; v.faddr := (others => '0');
end if;
if (r.flush2 = '1') and (icen /= 0) then
twrite := '1'; ctwrite := (others => '1'); vmask := (others => '0');
v.faddr := r.faddr +1; taddr(OFFSET_HIGH downto OFFSET_LOW) := r.faddr;
wlrr := '0'; wlock := '0'; wtag := (others => '0'); v.lrr := '0';
if (r.faddr(IOFFSET_BITS -1) and not v.faddr(IOFFSET_BITS -1)) = '1' then
v.flush2 := '0';
end if;
end if;
-- reset
if rst = '0' then
v.istate := "00"; v.req := '0'; v.burst := '0'; v.holdn := '1';
v.flush := '0'; v.flush2 := '0'; v.overrun := '0'; v.underrun := '0';
v.rndcnt := (others => '0'); v.lrr := '0'; v.setrepl := (others => '0');
v.diagset := (others => '0'); v.lock := '0'; v.flush3 := '1';
v.waddress := ici.fpc(31 downto 2); v.lrr := '0';
end if;
if r.flush3 = '1' then
vl.lru := (others => (others => '0'));
end if;
-- Drive signals
c <= v; -- register inputs
cl <= vl; -- lru register inputs
-- tag ram inputs
enable := enable and not dco.icdiag.scanen;
for i in 0 to ISETS-1 loop
tag(i) := (others => '0');
tag(i)(ilinesize-1 downto 0) := vmask;
tag(i)(TAG_HIGH downto TAG_LOW) := wtag;
tag(i)(CTAG_LRRPOS) := wlrr;
tag(i)(CTAG_LOCKPOS) := wlock;
end loop;
icrami.tag <= tag;
icrami.tenable <= enable;
icrami.twrite <= ctwrite;
icrami.flush <= r.flush2;
icrami.dpar <= (others => '0');
icrami.tpar <= (others => (others => '0'));
icrami.ctx <= (others => '0');
-- data ram inputs
icrami.denable <= enable;
icrami.address <= taddr(19+LINE_LOW downto LINE_LOW);
icrami.data <= ddatain;
icrami.dwrite <= cdwrite;
-- local ram inputs
icrami.ldramin.enable <= (dco.icdiag.ilramen or lramcs or lramacc) and not dco.icdiag.scanen;
icrami.ldramin.read <= dco.icdiag.ilramen or lramacc;
icrami.ldramin.write <= ilramwr;
-- memory controller inputs
mcii.address(31 downto 2) <= r.waddress(31 downto 2);
mcii.address(1 downto 0) <= "00";
mcii.su <= r.su;
mcii.burst <= r.burst;
mcii.req <= r.req;
mcii.flush <= r.flush;
-- IU data cache inputs
ico.data <= rdata;
ico.mexc <= mcio.mexc or error;
ico.hold <= r.holdn;
ico.mds <= mds;
ico.flush <= r.flush;
ico.diagdata <= diagdata;
ico.diagrdy <= r.diagrdy;
ico.set <= conv_std_logic_vector(set, 2);
ico.cfg <= icfg;
ico.idle <= sidle;
end process;
-- Local registers
regs1 : process(clk)
begin if rising_edge(clk) then r <= c; end if; end process;
regs2 : if (ISETS > 1) and (irepl = lru) generate
regs2 : process(clk)
begin if rising_edge(clk) then rl <= cl; end if; end process;
end generate;
nolru : if (ISETS = 1) or (irepl /= lru) generate
rl.write <= '0'; rl.waddr <= (others => '0');
rl.set <= (others => '0'); rl.lru <= (others => (others => '0'));
end generate;
-- pragma translate_off
chk : process
begin
assert not ((ISETS > 2) and (irepl = lrr)) report
"Wrong instruction cache configuration detected: LRR replacement requires 2 sets"
severity failure;
wait;
end process;
-- pragma translate_on
end ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2718.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p02n01i02718ent IS
END c13s04b02x00p02n01i02718ent;
ARCHITECTURE c13s04b02x00p02n01i02718arch OF c13s04b02x00p02n01i02718ent IS
BEGIN
TESTING: PROCESS
variable total_time : real := 5#1234.4321#E-10; --No_failure_here
BEGIN
wait for 5 ns;
assert NOT( total_time = 5#1234.4321#E-10 )
report "***PASSED TEST: c13s04b02x00p02n01i02718"
severity NOTE;
assert ( total_time = 5#1234.4321#E-10 )
report "***FAILED TEST: c13s04b02x00p02n01i02718 - Based literal literal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p02n01i02718arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2718.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p02n01i02718ent IS
END c13s04b02x00p02n01i02718ent;
ARCHITECTURE c13s04b02x00p02n01i02718arch OF c13s04b02x00p02n01i02718ent IS
BEGIN
TESTING: PROCESS
variable total_time : real := 5#1234.4321#E-10; --No_failure_here
BEGIN
wait for 5 ns;
assert NOT( total_time = 5#1234.4321#E-10 )
report "***PASSED TEST: c13s04b02x00p02n01i02718"
severity NOTE;
assert ( total_time = 5#1234.4321#E-10 )
report "***FAILED TEST: c13s04b02x00p02n01i02718 - Based literal literal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p02n01i02718arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2718.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b02x00p02n01i02718ent IS
END c13s04b02x00p02n01i02718ent;
ARCHITECTURE c13s04b02x00p02n01i02718arch OF c13s04b02x00p02n01i02718ent IS
BEGIN
TESTING: PROCESS
variable total_time : real := 5#1234.4321#E-10; --No_failure_here
BEGIN
wait for 5 ns;
assert NOT( total_time = 5#1234.4321#E-10 )
report "***PASSED TEST: c13s04b02x00p02n01i02718"
severity NOTE;
assert ( total_time = 5#1234.4321#E-10 )
report "***FAILED TEST: c13s04b02x00p02n01i02718 - Based literal literal test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b02x00p02n01i02718arch;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter signal encoder. Reads out samples from the ----
---- sample buffer, assembles frames and subframes and encodes ----
---- serial data as bi-phase mark code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_encoder is
generic (DATA_WIDTH: integer range 16 to 32 := 32);
port (
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack: out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic);
end tx_encoder;
architecture rtl of tx_encoder is
signal spdif_clk_en, spdif_out : std_logic;
signal clk_cnt : integer range 0 to 511;
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
signal bufctrl : buf_states;
signal cha_samp_ack, chb_samp_ack : std_logic;
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
signal framest : frame_states;
signal frame_cnt : integer range 0 to 191;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal inv_preamble, toggle, valid : std_logic;
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal par_vector : std_logic_vector(26 downto 0);
signal send_audio : std_logic;
signal cdc_sync_stage0_tick_counter : std_logic := '0';
signal cdc_sync_stage1_tick_counter : std_logic := '0';
signal cdc_sync_stage2_tick_counter : std_logic := '0';
signal cdc_sync_stage3_tick_counter : std_logic := '0';
signal tick_counter : std_logic;
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
function encode_bit (
signal bit_cnt : integer; -- sub-frame bit position
signal valid : std_logic; -- validity bit
signal frame_cnt : integer; -- frame counter
signal par_cnt : integer; -- parity counter
signal user_data : std_logic_vector(191 downto 0);
signal ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal toggle : std_logic;
signal prev_spdif : std_logic) -- prev. value of spdif signal
return std_logic is
variable spdif, next_bit : std_logic;
begin
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
next_bit := audio(bit_cnt - 4);
elsif bit_cnt = 28 then -- validity bit
next_bit := valid;
elsif bit_cnt = 29 then -- user data
next_bit := user_data(frame_cnt);
elsif bit_cnt = 30 then
next_bit := ch_status(frame_cnt); -- channel status
elsif bit_cnt = 31 then
if par_cnt mod 2 = 1 then
next_bit := '1';
else
next_bit := '0';
end if;
end if;
-- bi-phase mark encoding:
if next_bit = '0' then
if toggle = '0' then
spdif := not prev_spdif;
else
spdif := prev_spdif;
end if;
else
spdif := not prev_spdif;
end if;
return(spdif);
end encode_bit;
begin
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
-- determined by the conf_ratio value.
DCLK : process (data_clk)
begin
if rising_edge(data_clk) then
cdc_sync_stage0_tick_counter <= not cdc_sync_stage0_tick_counter;
end if;
end process DCLK;
process (up_clk) begin
if rising_edge(up_clk) then
cdc_sync_stage1_tick_counter <= cdc_sync_stage0_tick_counter;
cdc_sync_stage2_tick_counter <= cdc_sync_stage1_tick_counter;
cdc_sync_stage3_tick_counter <= cdc_sync_stage2_tick_counter;
end if;
end process;
tick_counter <= cdc_sync_stage3_tick_counter xor cdc_sync_stage2_tick_counter;
CGEN: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
clk_cnt <= 0;
spdif_clk_en <= '0';
else
spdif_clk_en <= '0';
if tick_counter = '1' then
if clk_cnt < to_integer(unsigned(conf_ratio)) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
spdif_clk_en <= '1';
end if;
end if;
end if;
end if;
end process CGEN;
SRD: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txdata = '0' then
bufctrl <= IDLE;
sample_data_ack <= '0';
channel <= '0';
else
case bufctrl is
when IDLE =>
sample_data_ack <= '0';
if conf_txdata = '1' then
bufctrl <= READ_CHA;
sample_data_ack <='1';
end if;
when READ_CHA =>
channel <= '0';
sample_data_ack <= '0';
bufctrl <= CHA_RDY;
when CHA_RDY =>
if cha_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHB;
end if;
when READ_CHB =>
channel <= '1';
sample_data_ack <= '0';
bufctrl <= CHB_RDY;
when CHB_RDY =>
if chb_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHA;
end if;
when others =>
bufctrl <= IDLE;
end case;
end if;
end if;
end process SRD;
TXSYNC: process (data_clk)
begin
if (rising_edge(data_clk)) then
spdif_tx_o <= spdif_out;
end if;
end process TXSYNC;
-- State machine that generates sub-frames and blocks
FRST: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
framest <= IDLE;
frame_cnt <= 0;
bit_cnt <= 0;
spdif_out <= '0';
inv_preamble <= '0';
toggle <= '0';
valid <= '1';
send_audio <= '0';
cha_samp_ack <= '0';
chb_samp_ack <= '0';
else
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
case framest is
when IDLE =>
bit_cnt <= 0;
frame_cnt <= 0;
inv_preamble <= '0';
toggle <= '0';
framest <= BLOCK_START;
when BLOCK_START => -- Start of channels status block/Ch. A
chb_samp_ack <= '0';
toggle <= not toggle; -- Each bit uses two clock enables,
if toggle = '1' then -- counted by the toggle bit.
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Block start uses preamble Z.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_A => -- Sub-frame: channel A.
chb_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Channel A uses preable X.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_B => -- Sub-frame: channel B.
cha_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
valid <= not conf_txdata;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
if send_audio = '1' then
chb_samp_ack <= '1';
end if;
if frame_cnt < 191 then -- One block is 192 frames
frame_cnt <= frame_cnt + 1;
framest <= CHANNEL_A;
else
frame_cnt <= 0;
framest <= BLOCK_START;
end if;
end if;
end if;
-- Channel B uses preable Y.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when others =>
framest <= IDLE;
end case;
end if;
end if;
end if;
end process FRST;
-- Audio data latching
DA32: if DATA_WIDTH = 32 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
case to_integer(unsigned(conf_mode)) is
when 0 => -- 16 bit audio
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
when 1 => -- 17 bit audio
audio(23 downto 7) <= sample_data(16 downto 0);
audio(6 downto 0) <= (others => '0');
when 2 => -- 18 bit audio
audio(23 downto 6) <= sample_data(17 downto 0);
audio(5 downto 0) <= (others => '0');
when 3 => -- 19 bit audio
audio(23 downto 5) <= sample_data(18 downto 0);
audio(4 downto 0) <= (others => '0');
when 4 => -- 20 bit audio
audio(23 downto 4) <= sample_data(19 downto 0);
audio(3 downto 0) <= (others => '0');
when 5 => -- 21 bit audio
audio(23 downto 3) <= sample_data(20 downto 0);
audio(2 downto 0) <= (others => '0');
when 6 => -- 22 bit audio
audio(23 downto 2) <= sample_data(21 downto 0);
audio(1 downto 0) <= (others => '0');
when 7 => -- 23 bit audio
audio(23 downto 1) <= sample_data(22 downto 0);
audio(0) <= '0';
when 8 => -- 24 bit audio
audio(23 downto 0) <= sample_data(23 downto 0);
when others => -- unsupported modes
audio(23 downto 0) <= (others => '0');
end case;
end if;
end if;
end process ALAT;
end generate DA32;
DA16: if DATA_WIDTH = 16 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
end if;
end if;
end process ALAT;
end generate DA16;
-- Parity vector. These bits are counted to generate even parity
par_vector(23 downto 0) <= audio(23 downto 0);
par_vector(24) <= valid;
par_vector(25) <= active_user_data(frame_cnt);
par_vector(26) <= active_ch_status(frame_cnt);
-- Channel status and user datat to be used if buffers are disabled.
-- User data is then all zero, while channel status bits are taken from
-- register TxChStat.
def_user_data(191 downto 0) <= (others => '0');
def_ch_status(0) <= '0'; -- consumer mode
def_ch_status(1) <= chstat_audio; -- audio bit
def_ch_status(2) <= chstat_copy; -- copy right
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
else "001"; -- pre-emphasis
def_ch_status(7 downto 6) <= "00";
def_ch_status(14 downto 8) <= (others => '0');
def_ch_status(15) <= chstat_gstat; -- generation status
def_ch_status(23 downto 16) <= (others => '0');
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
"0010" when chstat_freq = "01" else
"0011" when chstat_freq = "10" else
"0001";
def_ch_status(191 downto 28) <= (others => '0'); --191 28
-- Generate channel status vector based on configuration register setting.
active_ch_status <= def_ch_status;
-- Generate user data vector based on configuration register setting.
active_user_data <= def_user_data;
end rtl;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter signal encoder. Reads out samples from the ----
---- sample buffer, assembles frames and subframes and encodes ----
---- serial data as bi-phase mark code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_encoder is
generic (DATA_WIDTH: integer range 16 to 32 := 32);
port (
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack: out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic);
end tx_encoder;
architecture rtl of tx_encoder is
signal spdif_clk_en, spdif_out : std_logic;
signal clk_cnt : integer range 0 to 511;
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
signal bufctrl : buf_states;
signal cha_samp_ack, chb_samp_ack : std_logic;
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
signal framest : frame_states;
signal frame_cnt : integer range 0 to 191;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal inv_preamble, toggle, valid : std_logic;
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal par_vector : std_logic_vector(26 downto 0);
signal send_audio : std_logic;
signal cdc_sync_stage0_tick_counter : std_logic := '0';
signal cdc_sync_stage1_tick_counter : std_logic := '0';
signal cdc_sync_stage2_tick_counter : std_logic := '0';
signal cdc_sync_stage3_tick_counter : std_logic := '0';
signal tick_counter : std_logic;
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
function encode_bit (
signal bit_cnt : integer; -- sub-frame bit position
signal valid : std_logic; -- validity bit
signal frame_cnt : integer; -- frame counter
signal par_cnt : integer; -- parity counter
signal user_data : std_logic_vector(191 downto 0);
signal ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal toggle : std_logic;
signal prev_spdif : std_logic) -- prev. value of spdif signal
return std_logic is
variable spdif, next_bit : std_logic;
begin
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
next_bit := audio(bit_cnt - 4);
elsif bit_cnt = 28 then -- validity bit
next_bit := valid;
elsif bit_cnt = 29 then -- user data
next_bit := user_data(frame_cnt);
elsif bit_cnt = 30 then
next_bit := ch_status(frame_cnt); -- channel status
elsif bit_cnt = 31 then
if par_cnt mod 2 = 1 then
next_bit := '1';
else
next_bit := '0';
end if;
end if;
-- bi-phase mark encoding:
if next_bit = '0' then
if toggle = '0' then
spdif := not prev_spdif;
else
spdif := prev_spdif;
end if;
else
spdif := not prev_spdif;
end if;
return(spdif);
end encode_bit;
begin
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
-- determined by the conf_ratio value.
DCLK : process (data_clk)
begin
if rising_edge(data_clk) then
cdc_sync_stage0_tick_counter <= not cdc_sync_stage0_tick_counter;
end if;
end process DCLK;
process (up_clk) begin
if rising_edge(up_clk) then
cdc_sync_stage1_tick_counter <= cdc_sync_stage0_tick_counter;
cdc_sync_stage2_tick_counter <= cdc_sync_stage1_tick_counter;
cdc_sync_stage3_tick_counter <= cdc_sync_stage2_tick_counter;
end if;
end process;
tick_counter <= cdc_sync_stage3_tick_counter xor cdc_sync_stage2_tick_counter;
CGEN: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
clk_cnt <= 0;
spdif_clk_en <= '0';
else
spdif_clk_en <= '0';
if tick_counter = '1' then
if clk_cnt < to_integer(unsigned(conf_ratio)) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
spdif_clk_en <= '1';
end if;
end if;
end if;
end if;
end process CGEN;
SRD: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txdata = '0' then
bufctrl <= IDLE;
sample_data_ack <= '0';
channel <= '0';
else
case bufctrl is
when IDLE =>
sample_data_ack <= '0';
if conf_txdata = '1' then
bufctrl <= READ_CHA;
sample_data_ack <='1';
end if;
when READ_CHA =>
channel <= '0';
sample_data_ack <= '0';
bufctrl <= CHA_RDY;
when CHA_RDY =>
if cha_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHB;
end if;
when READ_CHB =>
channel <= '1';
sample_data_ack <= '0';
bufctrl <= CHB_RDY;
when CHB_RDY =>
if chb_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHA;
end if;
when others =>
bufctrl <= IDLE;
end case;
end if;
end if;
end process SRD;
TXSYNC: process (data_clk)
begin
if (rising_edge(data_clk)) then
spdif_tx_o <= spdif_out;
end if;
end process TXSYNC;
-- State machine that generates sub-frames and blocks
FRST: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
framest <= IDLE;
frame_cnt <= 0;
bit_cnt <= 0;
spdif_out <= '0';
inv_preamble <= '0';
toggle <= '0';
valid <= '1';
send_audio <= '0';
cha_samp_ack <= '0';
chb_samp_ack <= '0';
else
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
case framest is
when IDLE =>
bit_cnt <= 0;
frame_cnt <= 0;
inv_preamble <= '0';
toggle <= '0';
framest <= BLOCK_START;
when BLOCK_START => -- Start of channels status block/Ch. A
chb_samp_ack <= '0';
toggle <= not toggle; -- Each bit uses two clock enables,
if toggle = '1' then -- counted by the toggle bit.
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Block start uses preamble Z.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_A => -- Sub-frame: channel A.
chb_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Channel A uses preable X.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_B => -- Sub-frame: channel B.
cha_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
valid <= not conf_txdata;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
if send_audio = '1' then
chb_samp_ack <= '1';
end if;
if frame_cnt < 191 then -- One block is 192 frames
frame_cnt <= frame_cnt + 1;
framest <= CHANNEL_A;
else
frame_cnt <= 0;
framest <= BLOCK_START;
end if;
end if;
end if;
-- Channel B uses preable Y.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when others =>
framest <= IDLE;
end case;
end if;
end if;
end if;
end process FRST;
-- Audio data latching
DA32: if DATA_WIDTH = 32 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
case to_integer(unsigned(conf_mode)) is
when 0 => -- 16 bit audio
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
when 1 => -- 17 bit audio
audio(23 downto 7) <= sample_data(16 downto 0);
audio(6 downto 0) <= (others => '0');
when 2 => -- 18 bit audio
audio(23 downto 6) <= sample_data(17 downto 0);
audio(5 downto 0) <= (others => '0');
when 3 => -- 19 bit audio
audio(23 downto 5) <= sample_data(18 downto 0);
audio(4 downto 0) <= (others => '0');
when 4 => -- 20 bit audio
audio(23 downto 4) <= sample_data(19 downto 0);
audio(3 downto 0) <= (others => '0');
when 5 => -- 21 bit audio
audio(23 downto 3) <= sample_data(20 downto 0);
audio(2 downto 0) <= (others => '0');
when 6 => -- 22 bit audio
audio(23 downto 2) <= sample_data(21 downto 0);
audio(1 downto 0) <= (others => '0');
when 7 => -- 23 bit audio
audio(23 downto 1) <= sample_data(22 downto 0);
audio(0) <= '0';
when 8 => -- 24 bit audio
audio(23 downto 0) <= sample_data(23 downto 0);
when others => -- unsupported modes
audio(23 downto 0) <= (others => '0');
end case;
end if;
end if;
end process ALAT;
end generate DA32;
DA16: if DATA_WIDTH = 16 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
end if;
end if;
end process ALAT;
end generate DA16;
-- Parity vector. These bits are counted to generate even parity
par_vector(23 downto 0) <= audio(23 downto 0);
par_vector(24) <= valid;
par_vector(25) <= active_user_data(frame_cnt);
par_vector(26) <= active_ch_status(frame_cnt);
-- Channel status and user datat to be used if buffers are disabled.
-- User data is then all zero, while channel status bits are taken from
-- register TxChStat.
def_user_data(191 downto 0) <= (others => '0');
def_ch_status(0) <= '0'; -- consumer mode
def_ch_status(1) <= chstat_audio; -- audio bit
def_ch_status(2) <= chstat_copy; -- copy right
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
else "001"; -- pre-emphasis
def_ch_status(7 downto 6) <= "00";
def_ch_status(14 downto 8) <= (others => '0');
def_ch_status(15) <= chstat_gstat; -- generation status
def_ch_status(23 downto 16) <= (others => '0');
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
"0010" when chstat_freq = "01" else
"0011" when chstat_freq = "10" else
"0001";
def_ch_status(191 downto 28) <= (others => '0'); --191 28
-- Generate channel status vector based on configuration register setting.
active_ch_status <= def_ch_status;
-- Generate user data vector based on configuration register setting.
active_user_data <= def_user_data;
end rtl;
|
----------------------------------------------------------------------
---- ----
---- WISHBONE SPDIF IP Core ----
---- ----
---- This file is part of the SPDIF project ----
---- http://www.opencores.org/cores/spdif_interface/ ----
---- ----
---- Description ----
---- SPDIF transmitter signal encoder. Reads out samples from the ----
---- sample buffer, assembles frames and subframes and encodes ----
---- serial data as bi-phase mark code. ----
---- ----
---- To Do: ----
---- - ----
---- ----
---- Author(s): ----
---- - Geir Drange, [email protected] ----
---- ----
----------------------------------------------------------------------
---- ----
---- Copyright (C) 2004 Authors and OPENCORES.ORG ----
---- ----
---- This source file may be used and distributed without ----
---- restriction provided that this copyright statement is not ----
---- removed from the file and that any derivative work contains ----
---- the original copyright notice and the associated disclaimer. ----
---- ----
---- This source file is free software; you can redistribute it ----
---- and/or modify it under the terms of the GNU Lesser General ----
---- Public License as published by the Free Software Foundation; ----
---- either version 2.1 of the License, or (at your option) any ----
---- later version. ----
---- ----
---- This source is distributed in the hope that it will be ----
---- useful, but WITHOUT ANY WARRANTY; without even the implied ----
---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ----
---- PURPOSE. See the GNU Lesser General Public License for more ----
---- details. ----
---- ----
---- You should have received a copy of the GNU Lesser General ----
---- Public License along with this source; if not, download it ----
---- from http://www.opencores.org/lgpl.shtml ----
---- ----
----------------------------------------------------------------------
--
-- CVS Revision History
--
-- $Log: not supported by cvs2svn $
--
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity tx_encoder is
generic (DATA_WIDTH: integer range 16 to 32 := 32);
port (
up_clk: in std_logic; -- clock
data_clk : in std_logic; -- data clock
resetn : in std_logic; -- resetn
conf_mode: in std_logic_vector(3 downto 0); -- sample format
conf_ratio: in std_logic_vector(7 downto 0); -- clock divider
conf_txdata: in std_logic; -- sample data enable
conf_txen: in std_logic; -- spdif signal enable
chstat_freq: in std_logic_vector(1 downto 0); -- sample freq.
chstat_gstat: in std_logic; -- generation status
chstat_preem: in std_logic; -- preemphasis status
chstat_copy: in std_logic; -- copyright bit
chstat_audio: in std_logic; -- data format
sample_data: in std_logic_vector(DATA_WIDTH - 1 downto 0); -- audio data
sample_data_ack: out std_logic; -- sample buffer read
channel: out std_logic;
spdif_tx_o: out std_logic);
end tx_encoder;
architecture rtl of tx_encoder is
signal spdif_clk_en, spdif_out : std_logic;
signal clk_cnt : integer range 0 to 511;
type buf_states is (IDLE, READ_CHA, READ_CHB, CHA_RDY, CHB_RDY);
signal bufctrl : buf_states;
signal cha_samp_ack, chb_samp_ack : std_logic;
type frame_states is (IDLE, BLOCK_START, CHANNEL_A, CHANNEL_B);
signal framest : frame_states;
signal frame_cnt : integer range 0 to 191;
signal bit_cnt, par_cnt : integer range 0 to 31;
signal inv_preamble, toggle, valid : std_logic;
signal def_user_data, def_ch_status : std_logic_vector(191 downto 0);
signal active_user_data, active_ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal par_vector : std_logic_vector(26 downto 0);
signal send_audio : std_logic;
signal cdc_sync_stage0_tick_counter : std_logic := '0';
signal cdc_sync_stage1_tick_counter : std_logic := '0';
signal cdc_sync_stage2_tick_counter : std_logic := '0';
signal cdc_sync_stage3_tick_counter : std_logic := '0';
signal tick_counter : std_logic;
constant X_PREAMBLE : std_logic_vector(0 to 7) := "11100010";
constant Y_PREAMBLE : std_logic_vector(0 to 7) := "11100100";
constant Z_PREAMBLE : std_logic_vector(0 to 7) := "11101000";
function encode_bit (
signal bit_cnt : integer; -- sub-frame bit position
signal valid : std_logic; -- validity bit
signal frame_cnt : integer; -- frame counter
signal par_cnt : integer; -- parity counter
signal user_data : std_logic_vector(191 downto 0);
signal ch_status : std_logic_vector(191 downto 0);
signal audio : std_logic_vector(23 downto 0);
signal toggle : std_logic;
signal prev_spdif : std_logic) -- prev. value of spdif signal
return std_logic is
variable spdif, next_bit : std_logic;
begin
if bit_cnt > 3 and bit_cnt < 28 then -- audio part
next_bit := audio(bit_cnt - 4);
elsif bit_cnt = 28 then -- validity bit
next_bit := valid;
elsif bit_cnt = 29 then -- user data
next_bit := user_data(frame_cnt);
elsif bit_cnt = 30 then
next_bit := ch_status(frame_cnt); -- channel status
elsif bit_cnt = 31 then
if par_cnt mod 2 = 1 then
next_bit := '1';
else
next_bit := '0';
end if;
end if;
-- bi-phase mark encoding:
if next_bit = '0' then
if toggle = '0' then
spdif := not prev_spdif;
else
spdif := prev_spdif;
end if;
else
spdif := not prev_spdif;
end if;
return(spdif);
end encode_bit;
begin
-- SPDIF clock enable generation. The clock is a fraction of the data clock,
-- determined by the conf_ratio value.
DCLK : process (data_clk)
begin
if rising_edge(data_clk) then
cdc_sync_stage0_tick_counter <= not cdc_sync_stage0_tick_counter;
end if;
end process DCLK;
process (up_clk) begin
if rising_edge(up_clk) then
cdc_sync_stage1_tick_counter <= cdc_sync_stage0_tick_counter;
cdc_sync_stage2_tick_counter <= cdc_sync_stage1_tick_counter;
cdc_sync_stage3_tick_counter <= cdc_sync_stage2_tick_counter;
end if;
end process;
tick_counter <= cdc_sync_stage3_tick_counter xor cdc_sync_stage2_tick_counter;
CGEN: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
clk_cnt <= 0;
spdif_clk_en <= '0';
else
spdif_clk_en <= '0';
if tick_counter = '1' then
if clk_cnt < to_integer(unsigned(conf_ratio)) then
clk_cnt <= clk_cnt + 1;
else
clk_cnt <= 0;
spdif_clk_en <= '1';
end if;
end if;
end if;
end if;
end process CGEN;
SRD: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txdata = '0' then
bufctrl <= IDLE;
sample_data_ack <= '0';
channel <= '0';
else
case bufctrl is
when IDLE =>
sample_data_ack <= '0';
if conf_txdata = '1' then
bufctrl <= READ_CHA;
sample_data_ack <='1';
end if;
when READ_CHA =>
channel <= '0';
sample_data_ack <= '0';
bufctrl <= CHA_RDY;
when CHA_RDY =>
if cha_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHB;
end if;
when READ_CHB =>
channel <= '1';
sample_data_ack <= '0';
bufctrl <= CHB_RDY;
when CHB_RDY =>
if chb_samp_ack = '1' then
sample_data_ack <= '1';
bufctrl <= READ_CHA;
end if;
when others =>
bufctrl <= IDLE;
end case;
end if;
end if;
end process SRD;
TXSYNC: process (data_clk)
begin
if (rising_edge(data_clk)) then
spdif_tx_o <= spdif_out;
end if;
end process TXSYNC;
-- State machine that generates sub-frames and blocks
FRST: process (up_clk)
begin
if rising_edge(up_clk) then
if resetn = '0' or conf_txen = '0' then
framest <= IDLE;
frame_cnt <= 0;
bit_cnt <= 0;
spdif_out <= '0';
inv_preamble <= '0';
toggle <= '0';
valid <= '1';
send_audio <= '0';
cha_samp_ack <= '0';
chb_samp_ack <= '0';
else
if spdif_clk_en = '1' then -- SPDIF clock is twice the bit rate
case framest is
when IDLE =>
bit_cnt <= 0;
frame_cnt <= 0;
inv_preamble <= '0';
toggle <= '0';
framest <= BLOCK_START;
when BLOCK_START => -- Start of channels status block/Ch. A
chb_samp_ack <= '0';
toggle <= not toggle; -- Each bit uses two clock enables,
if toggle = '1' then -- counted by the toggle bit.
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Block start uses preamble Z.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Z_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Z_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_A => -- Sub-frame: channel A.
chb_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
if send_audio = '1' then
cha_samp_ack <= '1';
end if;
framest <= CHANNEL_B;
end if;
end if;
-- Channel A uses preable X.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= X_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= X_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when CHANNEL_B => -- Sub-frame: channel B.
cha_samp_ack <= '0';
toggle <= not toggle;
if toggle = '1' then
if bit_cnt < 31 then
bit_cnt <= bit_cnt + 1;
else
bit_cnt <= 0;
valid <= not conf_txdata;
if spdif_out = '1' then
inv_preamble <= '1';
else
inv_preamble <= '0';
end if;
send_audio <= conf_txdata; -- 1 if audio samples sohuld be sent
if send_audio = '1' then
chb_samp_ack <= '1';
end if;
if frame_cnt < 191 then -- One block is 192 frames
frame_cnt <= frame_cnt + 1;
framest <= CHANNEL_A;
else
frame_cnt <= 0;
framest <= BLOCK_START;
end if;
end if;
end if;
-- Channel B uses preable Y.
if bit_cnt < 4 then
if toggle = '0' then
spdif_out <= Y_PREAMBLE(2 * bit_cnt) xor inv_preamble;
else
spdif_out <= Y_PREAMBLE(2 * bit_cnt + 1) xor inv_preamble;
end if;
par_cnt <= 0;
elsif bit_cnt > 3 and bit_cnt <= 31 then
spdif_out <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
if bit_cnt = 31 then
inv_preamble <= encode_bit(bit_cnt, valid, frame_cnt,
par_cnt, active_user_data,
active_ch_status,
audio, toggle, spdif_out);
end if;
if toggle = '0' then
if bit_cnt > 3 and bit_cnt < 31 and
par_vector(bit_cnt - 4) = '1' then
par_cnt <= par_cnt + 1;
end if;
end if;
end if;
when others =>
framest <= IDLE;
end case;
end if;
end if;
end if;
end process FRST;
-- Audio data latching
DA32: if DATA_WIDTH = 32 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
case to_integer(unsigned(conf_mode)) is
when 0 => -- 16 bit audio
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
when 1 => -- 17 bit audio
audio(23 downto 7) <= sample_data(16 downto 0);
audio(6 downto 0) <= (others => '0');
when 2 => -- 18 bit audio
audio(23 downto 6) <= sample_data(17 downto 0);
audio(5 downto 0) <= (others => '0');
when 3 => -- 19 bit audio
audio(23 downto 5) <= sample_data(18 downto 0);
audio(4 downto 0) <= (others => '0');
when 4 => -- 20 bit audio
audio(23 downto 4) <= sample_data(19 downto 0);
audio(3 downto 0) <= (others => '0');
when 5 => -- 21 bit audio
audio(23 downto 3) <= sample_data(20 downto 0);
audio(2 downto 0) <= (others => '0');
when 6 => -- 22 bit audio
audio(23 downto 2) <= sample_data(21 downto 0);
audio(1 downto 0) <= (others => '0');
when 7 => -- 23 bit audio
audio(23 downto 1) <= sample_data(22 downto 0);
audio(0) <= '0';
when 8 => -- 24 bit audio
audio(23 downto 0) <= sample_data(23 downto 0);
when others => -- unsupported modes
audio(23 downto 0) <= (others => '0');
end case;
end if;
end if;
end process ALAT;
end generate DA32;
DA16: if DATA_WIDTH = 16 generate
ALAT: process (up_clk)
begin
if rising_edge(up_clk) then
if send_audio = '0' then
audio(23 downto 0) <= (others => '0');
else
audio(23 downto 8) <= sample_data(15 downto 0);
audio(7 downto 0) <= (others => '0');
end if;
end if;
end process ALAT;
end generate DA16;
-- Parity vector. These bits are counted to generate even parity
par_vector(23 downto 0) <= audio(23 downto 0);
par_vector(24) <= valid;
par_vector(25) <= active_user_data(frame_cnt);
par_vector(26) <= active_ch_status(frame_cnt);
-- Channel status and user datat to be used if buffers are disabled.
-- User data is then all zero, while channel status bits are taken from
-- register TxChStat.
def_user_data(191 downto 0) <= (others => '0');
def_ch_status(0) <= '0'; -- consumer mode
def_ch_status(1) <= chstat_audio; -- audio bit
def_ch_status(2) <= chstat_copy; -- copy right
def_ch_status(5 downto 3) <= "000" when chstat_preem = '0'
else "001"; -- pre-emphasis
def_ch_status(7 downto 6) <= "00";
def_ch_status(14 downto 8) <= (others => '0');
def_ch_status(15) <= chstat_gstat; -- generation status
def_ch_status(23 downto 16) <= (others => '0');
def_ch_status(27 downto 24) <= "0000" when chstat_freq = "00" else
"0010" when chstat_freq = "01" else
"0011" when chstat_freq = "10" else
"0001";
def_ch_status(191 downto 28) <= (others => '0'); --191 28
-- Generate channel status vector based on configuration register setting.
active_ch_status <= def_ch_status;
-- Generate user data vector based on configuration register setting.
active_user_data <= def_user_data;
end rtl;
|
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
-- Violation below
entity FIFO is
generic(
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
entity FIFO is
generic (
G_WIDTH : integer := 256;
G_DEPTH : integer := 32
);
end entity FIFO;
|
library verilog;
use verilog.vl_types.all;
entity Projeto2 is
port(
LEDG : out vl_logic_vector(1 downto 1);
SW : in vl_logic_vector(4 downto 1)
);
end Projeto2;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: road_exdes.vhd
--
-- Description:
-- This is the actual BMG core wrapper.
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY road_exdes IS
PORT (
--Inputs - Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END road_exdes;
ARCHITECTURE xilinx OF road_exdes IS
COMPONENT BUFG IS
PORT (
I : IN STD_ULOGIC;
O : OUT STD_ULOGIC
);
END COMPONENT;
COMPONENT road IS
PORT (
--Port A
ADDRA : IN STD_LOGIC_VECTOR(16 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
CLKA : IN STD_LOGIC
);
END COMPONENT;
SIGNAL CLKA_buf : STD_LOGIC;
SIGNAL CLKB_buf : STD_LOGIC;
SIGNAL S_ACLK_buf : STD_LOGIC;
BEGIN
bufg_A : BUFG
PORT MAP (
I => CLKA,
O => CLKA_buf
);
bmg0 : road
PORT MAP (
--Port A
ADDRA => ADDRA,
DOUTA => DOUTA,
CLKA => CLKA_buf
);
END xilinx;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package adder_types is
subtype word is integer;
end package adder_types;
use work.adder_types.all;
-- end not in book
entity adder is
port ( a, b : in word;
sum : out word );
end entity adder;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package adder_types is
subtype word is integer;
end package adder_types;
use work.adder_types.all;
-- end not in book
entity adder is
port ( a, b : in word;
sum : out word );
end entity adder;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package adder_types is
subtype word is integer;
end package adder_types;
use work.adder_types.all;
-- end not in book
entity adder is
port ( a, b : in word;
sum : out word );
end entity adder;
|
--------------------------------------------------------------------------------
-- Entity: generic_mixer
-- Date:2018-08-02
-- Author: gideon
--
-- Description: Audio mixer
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.audio_type_pkg.all;
use work.io_bus_pkg.all;
entity generic_mixer is
generic (
g_num_sources : natural := 8 );
port (
clock : in std_logic;
reset : in std_logic;
start : in std_logic;
sys_clock : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
-- audio
inputs : in t_audio_array(0 to g_num_sources-1);
out_L : out std_logic_vector(23 downto 0);
out_R : out std_logic_vector(23 downto 0)
);
end entity;
architecture arch of generic_mixer is
-- if 6dB per bit, then
-- (0)1.1111111 ~ 2 = +6dB
-- (0)1.0010000 ~ 1.13 = +1dB (0x90)
-- (0)1.0000000 = 1 = 0 dB (0x80)
-- (0)0.1110010 = .89 = -1dB (0x72)
-- (0)0.1000000 = .5 = -6dB (0x40)
-- (0)0.0100000 = .25 = -12dB
-- (0)0.0000001 = = -42dB
-- conclusion: one byte volume control is enough
-- Multiplication is such that 0dB yields the same value
type t_state is (idle, accumulate, collect, collect2, collect3);
signal state : t_state;
signal pointer : natural range 0 to 2*g_num_sources;
signal sys_en : std_logic;
signal sys_en_d : std_logic;
signal sys_rdata: std_logic_vector(7 downto 0);
signal ram_addr : unsigned(7 downto 0);
signal ram_rdata: std_logic_vector(7 downto 0);
signal clear : std_logic;
signal a : signed(17 downto 0);
signal b : signed(8 downto 0);
signal result : signed(31 downto 0);
function clip(inp : signed(31 downto 0)) return std_logic_vector is
variable result : std_logic_vector(23 downto 0);
begin
if inp(31 downto 24) = X"FF" or inp(31 downto 24) = X"00" then
result := std_logic_vector(inp(24 downto 1));
elsif inp(31) = '0' then
result := X"7FFFFF";
else
result := X"800000";
end if;
return result;
end function clip;
begin
b <= '0' & signed(ram_rdata);
ram_addr <= to_unsigned(pointer, 8);
i_ram: entity work.dpram
generic map (
g_width_bits => 8,
g_depth_bits => 8
)
port map(
a_clock => clock,
a_address => ram_addr,
a_rdata => ram_rdata,
a_wdata => X"00",
a_en => '1',
a_we => '0',
b_clock => sys_clock,
b_address => req.address(7 downto 0),
b_rdata => sys_rdata,
b_wdata => req.data,
b_en => sys_en,
b_we => req.write
);
sys_en <= req.write or req.read;
process(sys_clock)
begin
if rising_edge(sys_clock) then
sys_en_d <= sys_en;
resp <= c_io_resp_init;
if sys_en_d = '1' then
resp.data <= sys_rdata;
resp.ack <= '1';
end if;
end if;
end process;
process(clock)
begin
if rising_edge(clock) then
clear <= '0';
a <= inputs(pointer / 2);
case state is
when idle =>
pointer <= 0;
if start = '1' then
clear <= '1';
pointer <= 1;
state <= accumulate;
end if;
when accumulate =>
if pointer = (2*g_num_sources)-1 then
state <= collect;
else
pointer <= pointer + 1;
end if;
when collect =>
state <= collect2;
when collect2 =>
out_L <= clip(result);
state <= collect3;
when collect3 =>
out_R <= clip(result);
state <= idle;
end case;
if reset = '1' then
out_L <= (others => '0');
out_R <= (others => '0');
state <= idle;
end if;
end if;
end process;
i_muladd: entity work.mul_add
port map (
clock => clock,
clear => clear,
a => a,
b => b,
result => result
);
end architecture;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (lin64) Build 1733598 Wed Dec 14 22:35:42 MST 2016
--Date : Sat Apr 15 18:53:53 2017
--Host : work running 64-bit Ubuntu 16.04.2 LTS
--Command : generate_target sys_wrapper.bd
--Design : sys_wrapper
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity sys_wrapper is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC
);
end sys_wrapper;
architecture STRUCTURE of sys_wrapper is
component sys is
port (
DDR_cas_n : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC
);
end component sys;
begin
sys_i: component sys
port map (
DDR_addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_ba(2 downto 0) => DDR_ba(2 downto 0),
DDR_cas_n => DDR_cas_n,
DDR_ck_n => DDR_ck_n,
DDR_ck_p => DDR_ck_p,
DDR_cke => DDR_cke,
DDR_cs_n => DDR_cs_n,
DDR_dm(3 downto 0) => DDR_dm(3 downto 0),
DDR_dq(31 downto 0) => DDR_dq(31 downto 0),
DDR_dqs_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_dqs_p(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_odt => DDR_odt,
DDR_ras_n => DDR_ras_n,
DDR_reset_n => DDR_reset_n,
DDR_we_n => DDR_we_n,
FIXED_IO_ddr_vrn => FIXED_IO_ddr_vrn,
FIXED_IO_ddr_vrp => FIXED_IO_ddr_vrp,
FIXED_IO_mio(53 downto 0) => FIXED_IO_mio(53 downto 0),
FIXED_IO_ps_clk => FIXED_IO_ps_clk,
FIXED_IO_ps_porb => FIXED_IO_ps_porb,
FIXED_IO_ps_srstb => FIXED_IO_ps_srstb
);
end STRUCTURE;
|
--test bench written by alban bourge @ tima
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_tb is
--fsm state types
type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop);
--context descriptor
subtype context_t is std_logic_vector(1 downto 0);
--argument width and type of fsm instruction
constant ARG_WIDTH : integer := 8;
subtype argument_t is unsigned(ARG_WIDTH - 1 downto 0);
type instruction is
record
state : state_t;
context_uut : context_t;
arg : argument_t;
end record;
--reset instruction
constant instr_rst : instruction := (state => Rst, context_uut => (others =>'0'), arg => (others =>'0'));
--ram instruction
type ram_instruction is
record
sel : std_logic;
we : std_logic;
addr_up : std_logic;
addr_z : std_logic;
end record;
constant ram_instr_z : ram_instruction := (sel => '0', we => '0', addr_up => '0', addr_z => '0');
--assert unit instruction
type assert_instruction is
record
en_feed : std_logic;
en_check : std_logic;
end record;
constant assert_instr_z : assert_instruction := (en_feed => '0', en_check => '0');
--size of instruction table defined by PC_SIZE i.e. width of program counter
constant PC_SIZE : integer := 5;
type table_behavior is array (0 to 2**PC_SIZE - 1) of instruction;
--constraint fixed by unit under test (augh dependant)
--##CONSTRAINTS_START##--
subtype stdin_vector is std_logic_vector(31 downto 0);
subtype stdout_vector is std_logic_vector(31 downto 0);
subtype cp_vector is std_logic_vector(63 downto 0);
--##CONSTRAINTS_END##--
--assert_uut vector number counter size
constant VEC_NO_SIZE : integer := 20;
end pkg_tb;
|
--test bench written by alban bourge @ tima
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package pkg_tb is
--fsm state types
type state_t is (Rst,Sig_start,Ack_data,Running,Waitfor,Cp_search,Cp_save,Idle,Rst_uut,Rest_ini0,Rest_ini1,Rest,Stop);
--context descriptor
subtype context_t is std_logic_vector(1 downto 0);
--argument width and type of fsm instruction
constant ARG_WIDTH : integer := 8;
subtype argument_t is unsigned(ARG_WIDTH - 1 downto 0);
type instruction is
record
state : state_t;
context_uut : context_t;
arg : argument_t;
end record;
--reset instruction
constant instr_rst : instruction := (state => Rst, context_uut => (others =>'0'), arg => (others =>'0'));
--ram instruction
type ram_instruction is
record
sel : std_logic;
we : std_logic;
addr_up : std_logic;
addr_z : std_logic;
end record;
constant ram_instr_z : ram_instruction := (sel => '0', we => '0', addr_up => '0', addr_z => '0');
--assert unit instruction
type assert_instruction is
record
en_feed : std_logic;
en_check : std_logic;
end record;
constant assert_instr_z : assert_instruction := (en_feed => '0', en_check => '0');
--size of instruction table defined by PC_SIZE i.e. width of program counter
constant PC_SIZE : integer := 5;
type table_behavior is array (0 to 2**PC_SIZE - 1) of instruction;
--constraint fixed by unit under test (augh dependant)
--##CONSTRAINTS_START##--
subtype stdin_vector is std_logic_vector(31 downto 0);
subtype stdout_vector is std_logic_vector(31 downto 0);
subtype cp_vector is std_logic_vector(63 downto 0);
--##CONSTRAINTS_END##--
--assert_uut vector number counter size
constant VEC_NO_SIZE : integer := 20;
end pkg_tb;
|
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1_9.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1_9.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1_9.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_skid2mm_buf.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_skid2mm_buf.vhd
--
-- Description:
-- Implements the AXi Skid Buffer in the Option 2 (Registerd outputs) mode.
--
-- This Module also provides Write Data Bus Mirroring and WSTRB
-- Demuxing to match a narrow Stream to a wider MMap Write
-- Channel. By doing this in the skid buffer, the resource
-- utilization of the skid buffer can be minimized by only
-- having to buffer/mux the Stream data width, not the MMap
-- Data width.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_datamover_v5_1_9;
use axi_datamover_v5_1_9.axi_datamover_wr_demux;
-------------------------------------------------------------------------------
entity axi_datamover_skid2mm_buf is
generic (
C_MDATA_WIDTH : INTEGER range 32 to 1024 := 32 ;
-- Width of the MMap Write Data bus (in bits)
C_SDATA_WIDTH : INTEGER range 8 to 1024 := 32 ;
-- Width of the Stream Data bus (in bits)
C_ADDR_LSB_WIDTH : INTEGER range 1 to 8 := 5
-- Width of the LS address bus needed to Demux the WSTRB
);
port (
-- Clock and Reset Inputs -------------------------------------------
--
ACLK : In std_logic ; --
ARST : In std_logic ; --
---------------------------------------------------------------------
-- Slave Side (Wr Data Controller Input Side) -----------------------
--
S_ADDR_LSB : in std_logic_vector(C_ADDR_LSB_WIDTH-1 downto 0); --
S_VALID : In std_logic ; --
S_READY : Out std_logic ; --
S_DATA : In std_logic_vector(C_SDATA_WIDTH-1 downto 0); --
S_STRB : In std_logic_vector((C_SDATA_WIDTH/8)-1 downto 0); --
S_LAST : In std_logic ; --
---------------------------------------------------------------------
-- Master Side (MMap Write Data Output Side) ------------------------
M_VALID : Out std_logic ; --
M_READY : In std_logic ; --
M_DATA : Out std_logic_vector(C_MDATA_WIDTH-1 downto 0); --
M_STRB : Out std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0); --
M_LAST : Out std_logic --
---------------------------------------------------------------------
);
end entity axi_datamover_skid2mm_buf;
architecture implementation of axi_datamover_skid2mm_buf is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
Constant IN_DATA_WIDTH : integer := C_SDATA_WIDTH;
Constant MM2STRM_WIDTH_RATIO : integer := C_MDATA_WIDTH/C_SDATA_WIDTH;
-- Signals decalrations -------------------------
Signal sig_reset_reg : std_logic := '0';
signal sig_spcl_s_ready_set : std_logic := '0';
signal sig_data_skid_reg : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_reg : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_reg : std_logic := '0';
signal sig_skid_reg_en : std_logic := '0';
signal sig_data_skid_mux_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_skid_mux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_skid_mux_out : std_logic := '0';
signal sig_skid_mux_sel : std_logic := '0';
signal sig_data_reg_out : std_logic_vector(IN_DATA_WIDTH-1 downto 0) := (others => '0');
signal sig_strb_reg_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal sig_last_reg_out : std_logic := '0';
signal sig_data_reg_out_en : std_logic := '0';
signal sig_m_valid_out : std_logic := '0';
signal sig_m_valid_dup : std_logic := '0';
signal sig_m_valid_comb : std_logic := '0';
signal sig_s_ready_out : std_logic := '0';
signal sig_s_ready_dup : std_logic := '0';
signal sig_s_ready_comb : std_logic := '0';
signal sig_mirror_data_out : std_logic_vector(C_MDATA_WIDTH-1 downto 0) := (others => '0');
signal sig_wstrb_demux_out : std_logic_vector((C_MDATA_WIDTH/8)-1 downto 0) := (others => '0');
-- Register duplication attribute assignments to control fanout
-- on handshake output signals
Attribute KEEP : string; -- declaration
Attribute EQUIVALENT_REGISTER_REMOVAL : string; -- declaration
Attribute KEEP of sig_m_valid_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_m_valid_dup : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_out : signal is "TRUE"; -- definition
Attribute KEEP of sig_s_ready_dup : signal is "TRUE"; -- definition
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_m_valid_dup : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_out : signal is "no";
Attribute EQUIVALENT_REGISTER_REMOVAL of sig_s_ready_dup : signal is "no";
begin --(architecture implementation)
M_VALID <= sig_m_valid_out;
S_READY <= sig_s_ready_out;
M_STRB <= sig_strb_reg_out;
M_LAST <= sig_last_reg_out;
M_DATA <= sig_mirror_data_out;
-- Assign the special S_READY FLOP set signal
sig_spcl_s_ready_set <= sig_reset_reg;
-- Generate the ouput register load enable control
sig_data_reg_out_en <= M_READY or not(sig_m_valid_dup);
-- Generate the skid inpit register load enable control
sig_skid_reg_en <= sig_s_ready_dup;
-- Generate the skid mux select control
sig_skid_mux_sel <= not(sig_s_ready_dup);
-- Skid Mux
sig_data_skid_mux_out <= sig_data_skid_reg
When (sig_skid_mux_sel = '1')
Else S_DATA;
sig_strb_skid_mux_out <= sig_strb_skid_reg
When (sig_skid_mux_sel = '1')
--Else S_STRB;
Else sig_wstrb_demux_out;
sig_last_skid_mux_out <= sig_last_skid_reg
When (sig_skid_mux_sel = '1')
Else S_LAST;
-- m_valid combinational logic
sig_m_valid_comb <= S_VALID or
(sig_m_valid_dup and
(not(sig_s_ready_dup) or
not(M_READY)));
-- s_ready combinational logic
sig_s_ready_comb <= M_READY or
(sig_s_ready_dup and
(not(sig_m_valid_dup) or
not(S_VALID)));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_THE_RST
--
-- Process Description:
-- Register input reset
--
-------------------------------------------------------------
REG_THE_RST : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
sig_reset_reg <= ARST;
end if;
end process REG_THE_RST;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: S_READY_FLOP
--
-- Process Description:
-- Registers S_READY handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
S_READY_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_s_ready_out <= '0';
sig_s_ready_dup <= '0';
Elsif (sig_spcl_s_ready_set = '1') Then
sig_s_ready_out <= '1';
sig_s_ready_dup <= '1';
else
sig_s_ready_out <= sig_s_ready_comb;
sig_s_ready_dup <= sig_s_ready_comb;
end if;
end if;
end process S_READY_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: M_VALID_FLOP
--
-- Process Description:
-- Registers M_VALID handshake signals per Skid Buffer
-- Option 2 scheme
--
-------------------------------------------------------------
M_VALID_FLOP : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1' or
sig_spcl_s_ready_set = '1') then -- Fix from AXI DMA
sig_m_valid_out <= '0';
sig_m_valid_dup <= '0';
else
sig_m_valid_out <= sig_m_valid_comb;
sig_m_valid_dup <= sig_m_valid_comb;
end if;
end if;
end process M_VALID_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_DATA_REG
--
-- Process Description:
-- This process implements the Skid register for the
-- Skid Buffer Data signals.
--
-------------------------------------------------------------
SKID_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_skid_reg_en = '1') then
sig_data_skid_reg <= S_DATA;
else
null; -- hold current state
end if;
end if;
end process SKID_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SKID_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- Skid Buffer Control signals
--
-------------------------------------------------------------
SKID_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_skid_reg <= (others => '0');
sig_last_skid_reg <= '0';
elsif (sig_skid_reg_en = '1') then
sig_strb_skid_reg <= sig_wstrb_demux_out;
sig_last_skid_reg <= S_LAST;
else
null; -- hold current state
end if;
end if;
end process SKID_CNTL_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_DATA_REG
--
-- Process Description:
-- This process implements the Output register for the
-- Data signals.
--
-------------------------------------------------------------
OUTPUT_DATA_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (sig_data_reg_out_en = '1') then
sig_data_reg_out <= sig_data_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_DATA_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: OUTPUT_CNTL_REG
--
-- Process Description:
-- This process implements the Output registers for the
-- control signals.
--
-------------------------------------------------------------
OUTPUT_CNTL_REG : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARST = '1') then
sig_strb_reg_out <= (others => '0');
sig_last_reg_out <= '0';
elsif (sig_data_reg_out_en = '1') then
sig_strb_reg_out <= sig_strb_skid_mux_out;
sig_last_reg_out <= sig_last_skid_mux_out;
else
null; -- hold current state
end if;
end if;
end process OUTPUT_CNTL_REG;
-------------------------------------------------------------
-- Combinational Process
--
-- Label: DO_WR_DATA_MIRROR
--
-- Process Description:
-- Implement the Write Data Mirror structure
--
-- Note that it is required that the Stream Width be less than
-- or equal to the MMap WData width.
--
-------------------------------------------------------------
DO_WR_DATA_MIRROR : process (sig_data_reg_out)
begin
for slice_index in 0 to MM2STRM_WIDTH_RATIO-1 loop
sig_mirror_data_out(((C_SDATA_WIDTH*slice_index)+C_SDATA_WIDTH)-1
downto C_SDATA_WIDTH*slice_index)
<= sig_data_reg_out;
end loop;
end process DO_WR_DATA_MIRROR;
------------------------------------------------------------
-- Instance: I_WSTRB_DEMUX
--
-- Description:
-- Instance for the Write Strobe DeMux.
--
------------------------------------------------------------
I_WSTRB_DEMUX : entity axi_datamover_v5_1_9.axi_datamover_wr_demux
generic map (
C_SEL_ADDR_WIDTH => C_ADDR_LSB_WIDTH ,
C_MMAP_DWIDTH => C_MDATA_WIDTH ,
C_STREAM_DWIDTH => C_SDATA_WIDTH
)
port map (
wstrb_in => S_STRB ,
demux_wstrb_out => sig_wstrb_demux_out ,
debeat_saddr_lsb => S_ADDR_LSB
);
end implementation;
|
architecture rtl of fifo is
constant c_zeros : std_logic_vector(7 downto 0) := (others => '0');
constant c_one : std_logic_vector(7 downto 0) := (0 => '1', (others => '0'));
constant c_two : std_logic_vector(7 downto 0) := (1 => '1', (others => '0'));
constant c_stimulus : t_stimulus_array := ((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00"));
constant c_stimulus : t_stimulus_array := (
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
((name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"), (name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset", clk_in => "01", rst_in => "11", cnt_en_in => "00", cnt_out => "00"),
(name => "Not enabled", clk_in => "01", rst_in => "00", cnt_en_in => "00", cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00")
);
constant c_stimulus : t_stimulus_array :=
(
(
name => "Hold in reset",
clk_in => "01",
rst_in => "11",
cnt_en_in => "00",
cnt_out => "00"
),
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
)
);
constant c_stimulus : t_stimulus_array :=
(
name => "Not enabled",
clk_in => "01",
rst_in => "00",
cnt_en_in => "00",
cnt_out => "00"
); -- Comment
begin
end architecture rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- package: opcodes
-- File: opcodes.vhd
-- Author: Jiri Gaisler
-- Description: Instruction definitions according to the SPARC V8 manual.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package sparc is
-- op decoding (inst(31 downto 30))
subtype op_type is std_logic_vector(1 downto 0);
constant FMT2 : op_type := "00";
constant CALL : op_type := "01";
constant FMT3 : op_type := "10";
constant LDST : op_type := "11";
-- op2 decoding (inst(24 downto 22))
subtype op2_type is std_logic_vector(2 downto 0);
constant UNIMP : op2_type := "000";
constant BICC : op2_type := "010";
constant SETHI : op2_type := "100";
constant FBFCC : op2_type := "110";
constant CBCCC : op2_type := "111";
-- op3 decoding (inst(24 downto 19))
subtype op3_type is std_logic_vector(5 downto 0);
constant IADD : op3_type := "000000";
constant IAND : op3_type := "000001";
constant IOR : op3_type := "000010";
constant IXOR : op3_type := "000011";
constant ISUB : op3_type := "000100";
constant ANDN : op3_type := "000101";
constant ORN : op3_type := "000110";
constant IXNOR : op3_type := "000111";
constant ADDX : op3_type := "001000";
constant UMUL : op3_type := "001010";
constant SMUL : op3_type := "001011";
constant SUBX : op3_type := "001100";
constant UDIV : op3_type := "001110";
constant SDIV : op3_type := "001111";
constant ADDCC : op3_type := "010000";
constant ANDCC : op3_type := "010001";
constant ORCC : op3_type := "010010";
constant XORCC : op3_type := "010011";
constant SUBCC : op3_type := "010100";
constant ANDNCC : op3_type := "010101";
constant ORNCC : op3_type := "010110";
constant XNORCC : op3_type := "010111";
constant ADDXCC : op3_type := "011000";
constant UMULCC : op3_type := "011010";
constant SMULCC : op3_type := "011011";
constant SUBXCC : op3_type := "011100";
constant UDIVCC : op3_type := "011110";
constant SDIVCC : op3_type := "011111";
constant TADDCC : op3_type := "100000";
constant TSUBCC : op3_type := "100001";
constant TADDCCTV : op3_type := "100010";
constant TSUBCCTV : op3_type := "100011";
constant MULSCC : op3_type := "100100";
constant ISLL : op3_type := "100101";
constant ISRL : op3_type := "100110";
constant ISRA : op3_type := "100111";
constant RDY : op3_type := "101000";
constant RDPSR : op3_type := "101001";
constant RDWIM : op3_type := "101010";
constant RDTBR : op3_type := "101011";
constant WRY : op3_type := "110000";
constant WRPSR : op3_type := "110001";
constant WRWIM : op3_type := "110010";
constant WRTBR : op3_type := "110011";
constant FPOP1 : op3_type := "110100";
constant FPOP2 : op3_type := "110101";
constant CPOP1 : op3_type := "110110";
constant CPOP2 : op3_type := "110111";
constant JMPL : op3_type := "111000";
constant TICC : op3_type := "111010";
constant FLUSH : op3_type := "111011";
constant RETT : op3_type := "111001";
constant SAVE : op3_type := "111100";
constant RESTORE : op3_type := "111101";
constant UMAC : op3_type := "111110";
constant SMAC : op3_type := "111111";
constant LD : op3_type := "000000";
constant LDUB : op3_type := "000001";
constant LDUH : op3_type := "000010";
constant LDD : op3_type := "000011";
constant LDSB : op3_type := "001001";
constant LDSH : op3_type := "001010";
constant LDSTUB : op3_type := "001101";
constant SWAP : op3_type := "001111";
constant LDA : op3_type := "010000";
constant LDUBA : op3_type := "010001";
constant LDUHA : op3_type := "010010";
constant LDDA : op3_type := "010011";
constant LDSBA : op3_type := "011001";
constant LDSHA : op3_type := "011010";
constant LDSTUBA : op3_type := "011101";
constant SWAPA : op3_type := "011111";
constant LDF : op3_type := "100000";
constant LDFSR : op3_type := "100001";
constant LDDF : op3_type := "100011";
constant LDC : op3_type := "110000";
constant LDCSR : op3_type := "110001";
constant LDDC : op3_type := "110011";
constant ST : op3_type := "000100";
constant STB : op3_type := "000101";
constant STH : op3_type := "000110";
constant ISTD : op3_type := "000111";
constant STA : op3_type := "010100";
constant STBA : op3_type := "010101";
constant STHA : op3_type := "010110";
constant STDA : op3_type := "010111";
constant STF : op3_type := "100100";
constant STFSR : op3_type := "100101";
constant STDFQ : op3_type := "100110";
constant STDF : op3_type := "100111";
constant STC : op3_type := "110100";
constant STCSR : op3_type := "110101";
constant STDCQ : op3_type := "110110";
constant STDC : op3_type := "110111";
constant CASA : op3_type := "111100";
-- bicc decoding (inst(27 downto 25))
constant BA : std_logic_vector(3 downto 0) := "1000";
-- fpop1 decoding
subtype fpop_type is std_logic_vector(8 downto 0);
constant FITOS : fpop_type := "011000100";
constant FITOD : fpop_type := "011001000";
constant FSTOI : fpop_type := "011010001";
constant FDTOI : fpop_type := "011010010";
constant FSTOD : fpop_type := "011001001";
constant FDTOS : fpop_type := "011000110";
constant FMOVS : fpop_type := "000000001";
constant FNEGS : fpop_type := "000000101";
constant FABSS : fpop_type := "000001001";
constant FSQRTS : fpop_type := "000101001";
constant FSQRTD : fpop_type := "000101010";
constant FADDS : fpop_type := "001000001";
constant FADDD : fpop_type := "001000010";
constant FSUBS : fpop_type := "001000101";
constant FSUBD : fpop_type := "001000110";
constant FMULS : fpop_type := "001001001";
constant FMULD : fpop_type := "001001010";
constant FSMULD : fpop_type := "001101001";
constant FDIVS : fpop_type := "001001101";
constant FDIVD : fpop_type := "001001110";
-- fpop2 decoding
constant FCMPS : fpop_type := "001010001";
constant FCMPD : fpop_type := "001010010";
constant FCMPES : fpop_type := "001010101";
constant FCMPED : fpop_type := "001010110";
-- trap type decoding
subtype trap_type is std_logic_vector(5 downto 0);
constant TT_IAEX : trap_type := "000001";
constant TT_IINST : trap_type := "000010";
constant TT_PRIV : trap_type := "000011";
constant TT_FPDIS : trap_type := "000100";
constant TT_WINOF : trap_type := "000101";
constant TT_WINUF : trap_type := "000110";
constant TT_UNALA : trap_type := "000111";
constant TT_FPEXC : trap_type := "001000";
constant TT_DAEX : trap_type := "001001";
constant TT_TAG : trap_type := "001010";
constant TT_WATCH : trap_type := "001011";
constant TT_DSU : trap_type := "010000";
constant TT_PWD : trap_type := "010001";
constant TT_RFERR : trap_type := "100000";
constant TT_IAERR : trap_type := "100001";
constant TT_CPDIS : trap_type := "100100";
constant TT_CPEXC : trap_type := "101000";
constant TT_DIV : trap_type := "101010";
constant TT_DSEX : trap_type := "101011";
constant TT_TICC : trap_type := "111111";
constant TT_ICERR : trap_type := "110000"; -- icache correctable error
constant TT_DCERR : trap_type := "110100"; -- dcache correctable error
constant TT_RCERR : trap_type := "111000"; -- RF correctable error
-- Alternate address space identifiers (only 5 lsb bist are used)
subtype asi_type is std_logic_vector(4 downto 0);
constant ASI_SYSR : asi_type := "00010"; -- 0x02
constant ASI_UINST : asi_type := "01000"; -- 0x08
constant ASI_SINST : asi_type := "01001"; -- 0x09
constant ASI_UDATA : asi_type := "01010"; -- 0x0A
constant ASI_SDATA : asi_type := "01011"; -- 0x0B
constant ASI_ITAG : asi_type := "01100"; -- 0x0C
constant ASI_IDATA : asi_type := "01101"; -- 0x0D
constant ASI_DTAG : asi_type := "01110"; -- 0x0E
constant ASI_DDATA : asi_type := "01111"; -- 0x0F
constant ASI_IFLUSH : asi_type := "10000"; -- 0x10
constant ASI_DFLUSH : asi_type := "10001"; -- 0x11
constant ASI_FLUSH_PAGE : std_logic_vector(4 downto 0) := "10000"; -- 0x10 i/dcache flush page
constant ASI_FLUSH_CTX : std_logic_vector(4 downto 0) := "10011"; -- 0x13 i/dcache flush ctx
constant ASI_DCTX : std_logic_vector(4 downto 0) := "10100"; -- 0x14 dcache ctx
constant ASI_ICTX : std_logic_vector(4 downto 0) := "10101"; -- 0x15 icache ctx
constant ASI_MMUFLUSHPROBE : std_logic_vector(4 downto 0) := "11000"; -- 0x18 i/dtlb flush/(probe)
constant ASI_MMUREGS : std_logic_vector(4 downto 0) := "11001"; -- 0x19 mmu regs access
constant ASI_MMU_BP : std_logic_vector(4 downto 0) := "11100"; -- 0x1c mmu Bypass
constant ASI_MMU_DIAG : std_logic_vector(4 downto 0) := "11101"; -- 0x1d mmu diagnostic
--constant ASI_MMU_DSU : std_logic_vector(4 downto 0) := "11111"; -- 0x1f mmu diagnostic
constant ASI_MMUSNOOP_DTAG : std_logic_vector(4 downto 0) := "11110"; -- 0x1e mmusnoop physical dtag
-- ftt decoding
subtype ftt_type is std_logic_vector(2 downto 0);
constant FPIEEE_ERR : ftt_type := "001";
constant FPSEQ_ERR : ftt_type := "100";
constant FPHW_ERR : ftt_type := "101";
end;
|
architecture RTL of FIFO is
begin
BLOCK_LABEL : block is
begin
a <= b;
end block;
-- Violations below
BLOCK_LABEL : block is
begin
a <= b;
end block;
end architecture RTL;
|
--
-- UART receiver
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART receiver
entity uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end uart_receiver;
architecture rtl of uart_receiver is
-- Majority voting logic
component slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end component;
-- Counter
component slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end component;
-- FSM
type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
signal CState, NState : state_type;
-- Signals
signal iBaudCountClear : std_logic; -- Baud counter clear
signal iBaudStep : std_logic; -- Next symbol pulse
signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
signal iFilterClear : std_logic; -- Reset input filter
signal iFSIN : std_logic; -- Filtered SIN
signal iParity : std_logic; -- Data parity
signal iParityReceived : std_logic; -- Parity received
signal iDataCount : integer range 0 to 8; -- Data bit counter
signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
signal iDataCountFinish : std_logic; -- Data bit counter finished
signal iRXFinished : std_logic; -- Word received, output data valid
signal iFE : std_logic; -- Internal frame error
signal iBI : std_logic; -- Internal break interrupt
signal iNoStopReceived : std_logic; -- No valid stop bit received
signal iDOUT : std_logic_vector(7 downto 0); -- Data output
begin
-- Baudrate counter: RXCLK/16
RX_BRC: slib_counter generic map (
WIDTH => 4
) port map (
CLK => CLK,
RST => RST,
CLEAR => iBaudCountClear,
LOAD => '0',
ENABLE => RXCLK,
DOWN => '0',
D => x"0",
OVERFLOW => iBaudStep
);
-- Input filter
RX_MVF: slib_mv_filter generic map (
WIDTH => 4,
THRESHOLD => 10
) port map (
CLK => CLK,
RST => RST,
SAMPLE => RXCLK,
CLEAR => iFilterClear,
D => SIN,
Q => iFSIN
);
-- iBaudStepD
RX_IFC: process (CLK, RST)
begin
if (RST = '1') then
iBaudStepD <= '0';
elsif (CLK'event and CLK = '1') then
iBaudStepD <= iBaudStep;
end if;
end process;
iFilterClear <= iBaudStepD or iBaudCountClear;
-- Parity generation
RX_PAR: process (iDOUT, EPS)
begin
iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS;
end process;
-- Data bit capture
RX_DATACOUNT: process (CLK, RST)
begin
if (RST = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDataCountInit = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
else
if (iBaudStep = '1' and iDataCountFinish = '0') then
iDOUT(iDataCount) <= iFSIN;
iDataCount <= iDataCount + 1;
end if;
end if;
end if;
end process;
iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or
(WLS = "01" and iDataCount = 6) or
(WLS = "10" and iDataCount = 7) or
(WLS = "11" and iDataCount = 8) else '0';
-- FSM update process
RX_FSMUPDATE: process (CLK, RST)
begin
if (RST = '1') then
CState <= IDLE;
elsif (CLK'event and CLK = '1') then
CState <= NState;
end if;
end process;
-- RX FSM
RX_FSM: process (CState, SIN, iFSIN, iBaudStep, iDataCountFinish, PEN, WLS, STB)
begin
-- Defaults
NState <= IDLE;
iBaudCountClear <= '0';
iDataCountInit <= '0';
iRXFinished <= '0';
case CState is
when IDLE => if (SIN = '0') then -- Start detected
NState <= START;
end if;
iBaudCountClear <= '1';
iDataCountInit <= '1';
when START => iDataCountInit <= '1';
if (iBaudStep = '1') then -- Wait for start bit end
if (iFSIN = '0') then
NState <= DATA;
end if;
else
NState <= START;
end if;
when DATA => if (iDataCountFinish = '1') then -- Received all data bits
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
else
NState <= DATA;
end if;
when PAR => if (iBaudStep = '1') then -- Wait for parity bit
NState <= STOP;
else
NState <= PAR;
end if;
when STOP => if (iBaudStep = '1') then -- Wait for stop bit
if (iFSIN = '0') then -- No stop bit received
iRXFinished <= '1';
NState <= MWAIT;
else
iRXFinished <= '1';
NState <= IDLE; -- Stop bit end
end if;
else
NState <= STOP;
end if;
when MWAIT => if (SIN = '0') then -- Wait for mark
NState <= MWAIT;
end if;
when others => null;
end case;
end process;
-- Check parity
RX_PARCHECK: process (CLK, RST)
begin
if (RST = '1') then
PE <= '0';
iParityReceived <= '0';
elsif (CLK'event and CLK = '1') then
if (CState = PAR and iBaudStep = '1') then
iParityReceived <= iFSIN; -- Received parity bit
end if;
-- Check parity
if (PEN = '1') then -- Parity enabled
PE <= '0';
if (SP = '1') then -- Sticky parity
if ((EPS xor iParityReceived) = '0') then
PE <= '1'; -- Parity error
end if;
else
if (iParity /= iParityReceived) then
PE <= '1'; -- Parity error
end if;
end if;
else
PE <= '0'; -- Parity disabled
iParityReceived <= '0';
end if;
end if;
end process;
-- Framing error and break interrupt
iNoStopReceived <= '1' when iFSIN = '0' and (CState = STOP) else '0';
iBI <= '1' when iDOUT = "00000000" and
iParityReceived = '0' and
iNoStopReceived = '1' else '0';
iFE <= '1' when iNoStopReceived = '1' else '0';
-- Output signals
DOUT <= iDOUT;
BI <= iBI;
FE <= iFE;
RXFINISHED <= iRXFinished;
end rtl;
|
--
-- UART receiver
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART receiver
entity uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end uart_receiver;
architecture rtl of uart_receiver is
-- Majority voting logic
component slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end component;
-- Counter
component slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end component;
-- FSM
type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
signal CState, NState : state_type;
-- Signals
signal iBaudCountClear : std_logic; -- Baud counter clear
signal iBaudStep : std_logic; -- Next symbol pulse
signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
signal iFilterClear : std_logic; -- Reset input filter
signal iFSIN : std_logic; -- Filtered SIN
signal iParity : std_logic; -- Data parity
signal iParityReceived : std_logic; -- Parity received
signal iDataCount : integer range 0 to 8; -- Data bit counter
signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
signal iDataCountFinish : std_logic; -- Data bit counter finished
signal iRXFinished : std_logic; -- Word received, output data valid
signal iFE : std_logic; -- Internal frame error
signal iBI : std_logic; -- Internal break interrupt
signal iNoStopReceived : std_logic; -- No valid stop bit received
signal iDOUT : std_logic_vector(7 downto 0); -- Data output
begin
-- Baudrate counter: RXCLK/16
RX_BRC: slib_counter generic map (
WIDTH => 4
) port map (
CLK => CLK,
RST => RST,
CLEAR => iBaudCountClear,
LOAD => '0',
ENABLE => RXCLK,
DOWN => '0',
D => x"0",
OVERFLOW => iBaudStep
);
-- Input filter
RX_MVF: slib_mv_filter generic map (
WIDTH => 4,
THRESHOLD => 10
) port map (
CLK => CLK,
RST => RST,
SAMPLE => RXCLK,
CLEAR => iFilterClear,
D => SIN,
Q => iFSIN
);
-- iBaudStepD
RX_IFC: process (CLK, RST)
begin
if (RST = '1') then
iBaudStepD <= '0';
elsif (CLK'event and CLK = '1') then
iBaudStepD <= iBaudStep;
end if;
end process;
iFilterClear <= iBaudStepD or iBaudCountClear;
-- Parity generation
RX_PAR: process (iDOUT, EPS)
begin
iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS;
end process;
-- Data bit capture
RX_DATACOUNT: process (CLK, RST)
begin
if (RST = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDataCountInit = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
else
if (iBaudStep = '1' and iDataCountFinish = '0') then
iDOUT(iDataCount) <= iFSIN;
iDataCount <= iDataCount + 1;
end if;
end if;
end if;
end process;
iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or
(WLS = "01" and iDataCount = 6) or
(WLS = "10" and iDataCount = 7) or
(WLS = "11" and iDataCount = 8) else '0';
-- FSM update process
RX_FSMUPDATE: process (CLK, RST)
begin
if (RST = '1') then
CState <= IDLE;
elsif (CLK'event and CLK = '1') then
CState <= NState;
end if;
end process;
-- RX FSM
RX_FSM: process (CState, SIN, iFSIN, iBaudStep, iDataCountFinish, PEN, WLS, STB)
begin
-- Defaults
NState <= IDLE;
iBaudCountClear <= '0';
iDataCountInit <= '0';
iRXFinished <= '0';
case CState is
when IDLE => if (SIN = '0') then -- Start detected
NState <= START;
end if;
iBaudCountClear <= '1';
iDataCountInit <= '1';
when START => iDataCountInit <= '1';
if (iBaudStep = '1') then -- Wait for start bit end
if (iFSIN = '0') then
NState <= DATA;
end if;
else
NState <= START;
end if;
when DATA => if (iDataCountFinish = '1') then -- Received all data bits
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
else
NState <= DATA;
end if;
when PAR => if (iBaudStep = '1') then -- Wait for parity bit
NState <= STOP;
else
NState <= PAR;
end if;
when STOP => if (iBaudStep = '1') then -- Wait for stop bit
if (iFSIN = '0') then -- No stop bit received
iRXFinished <= '1';
NState <= MWAIT;
else
iRXFinished <= '1';
NState <= IDLE; -- Stop bit end
end if;
else
NState <= STOP;
end if;
when MWAIT => if (SIN = '0') then -- Wait for mark
NState <= MWAIT;
end if;
when others => null;
end case;
end process;
-- Check parity
RX_PARCHECK: process (CLK, RST)
begin
if (RST = '1') then
PE <= '0';
iParityReceived <= '0';
elsif (CLK'event and CLK = '1') then
if (CState = PAR and iBaudStep = '1') then
iParityReceived <= iFSIN; -- Received parity bit
end if;
-- Check parity
if (PEN = '1') then -- Parity enabled
PE <= '0';
if (SP = '1') then -- Sticky parity
if ((EPS xor iParityReceived) = '0') then
PE <= '1'; -- Parity error
end if;
else
if (iParity /= iParityReceived) then
PE <= '1'; -- Parity error
end if;
end if;
else
PE <= '0'; -- Parity disabled
iParityReceived <= '0';
end if;
end if;
end process;
-- Framing error and break interrupt
iNoStopReceived <= '1' when iFSIN = '0' and (CState = STOP) else '0';
iBI <= '1' when iDOUT = "00000000" and
iParityReceived = '0' and
iNoStopReceived = '1' else '0';
iFE <= '1' when iNoStopReceived = '1' else '0';
-- Output signals
DOUT <= iDOUT;
BI <= iBI;
FE <= iFE;
RXFINISHED <= iRXFinished;
end rtl;
|
--
-- UART receiver
--
-- Author: Sebastian Witt
-- Date: 27.01.2008
-- Version: 1.1
--
-- This code is free software; you can redistribute it and/or
-- modify it under the terms of the GNU Lesser General Public
-- License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
--
-- This code is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public
-- License along with this library; if not, write to the
-- Free Software Foundation, Inc., 59 Temple Place, Suite 330,
-- Boston, MA 02111-1307 USA
--
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
USE IEEE.numeric_std.all;
-- Serial UART receiver
entity uart_receiver is
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
RXCLK : in std_logic; -- Receiver clock (16x baudrate)
RXCLEAR : in std_logic; -- Reset receiver state
WLS : in std_logic_vector(1 downto 0); -- Word length select
STB : in std_logic; -- Number of stop bits
PEN : in std_logic; -- Parity enable
EPS : in std_logic; -- Even parity select
SP : in std_logic; -- Stick parity
SIN : in std_logic; -- Receiver input
PE : out std_logic; -- Parity error
FE : out std_logic; -- Framing error
BI : out std_logic; -- Break interrupt
DOUT : out std_logic_vector(7 downto 0); -- Output data
RXFINISHED : out std_logic -- Receiver operation finished
);
end uart_receiver;
architecture rtl of uart_receiver is
-- Majority voting logic
component slib_mv_filter is
generic (
WIDTH : natural := 4;
THRESHOLD : natural := 10
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
SAMPLE : in std_logic; -- Clock enable for sample process
CLEAR : in std_logic; -- Reset process
D : in std_logic; -- Signal input
Q : out std_logic -- Signal D was at least THRESHOLD samples high
);
end component;
-- Counter
component slib_counter is
generic (
WIDTH : natural := 4 -- Counter width
);
port (
CLK : in std_logic; -- Clock
RST : in std_logic; -- Reset
CLEAR : in std_logic; -- Clear counter register
LOAD : in std_logic; -- Load counter register
ENABLE : in std_logic; -- Enable count operation
DOWN : in std_logic; -- Count direction down
D : in std_logic_vector(WIDTH-1 downto 0); -- Load counter register input
Q : out std_logic_vector(WIDTH-1 downto 0); -- Shift register output
OVERFLOW : out std_logic -- Counter overflow
);
end component;
-- FSM
type state_type is (IDLE, START, DATA, PAR, STOP, MWAIT);
signal CState, NState : state_type;
-- Signals
signal iBaudCountClear : std_logic; -- Baud counter clear
signal iBaudStep : std_logic; -- Next symbol pulse
signal iBaudStepD : std_logic; -- Next symbol pulse delayed by one clock
signal iFilterClear : std_logic; -- Reset input filter
signal iFSIN : std_logic; -- Filtered SIN
signal iParity : std_logic; -- Data parity
signal iParityReceived : std_logic; -- Parity received
signal iDataCount : integer range 0 to 8; -- Data bit counter
signal iDataCountInit : std_logic; -- Initialize data bit counter to word length
signal iDataCountFinish : std_logic; -- Data bit counter finished
signal iRXFinished : std_logic; -- Word received, output data valid
signal iFE : std_logic; -- Internal frame error
signal iBI : std_logic; -- Internal break interrupt
signal iNoStopReceived : std_logic; -- No valid stop bit received
signal iDOUT : std_logic_vector(7 downto 0); -- Data output
begin
-- Baudrate counter: RXCLK/16
RX_BRC: slib_counter generic map (
WIDTH => 4
) port map (
CLK => CLK,
RST => RST,
CLEAR => iBaudCountClear,
LOAD => '0',
ENABLE => RXCLK,
DOWN => '0',
D => x"0",
OVERFLOW => iBaudStep
);
-- Input filter
RX_MVF: slib_mv_filter generic map (
WIDTH => 4,
THRESHOLD => 10
) port map (
CLK => CLK,
RST => RST,
SAMPLE => RXCLK,
CLEAR => iFilterClear,
D => SIN,
Q => iFSIN
);
-- iBaudStepD
RX_IFC: process (CLK, RST)
begin
if (RST = '1') then
iBaudStepD <= '0';
elsif (CLK'event and CLK = '1') then
iBaudStepD <= iBaudStep;
end if;
end process;
iFilterClear <= iBaudStepD or iBaudCountClear;
-- Parity generation
RX_PAR: process (iDOUT, EPS)
begin
iParity <= iDOUT(7) xor iDOUT(6) xor iDOUT(5) xor iDOUT(4) xor iDOUT(3) xor iDOUT(2) xor iDOUT(1) xor iDOUT(0) xor not EPS;
end process;
-- Data bit capture
RX_DATACOUNT: process (CLK, RST)
begin
if (RST = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
elsif (CLK'event and CLK = '1') then
if (iDataCountInit = '1') then
iDataCount <= 0;
iDOUT <= (others => '0');
else
if (iBaudStep = '1' and iDataCountFinish = '0') then
iDOUT(iDataCount) <= iFSIN;
iDataCount <= iDataCount + 1;
end if;
end if;
end if;
end process;
iDataCountFinish <= '1' when (WLS = "00" and iDataCount = 5) or
(WLS = "01" and iDataCount = 6) or
(WLS = "10" and iDataCount = 7) or
(WLS = "11" and iDataCount = 8) else '0';
-- FSM update process
RX_FSMUPDATE: process (CLK, RST)
begin
if (RST = '1') then
CState <= IDLE;
elsif (CLK'event and CLK = '1') then
CState <= NState;
end if;
end process;
-- RX FSM
RX_FSM: process (CState, SIN, iFSIN, iBaudStep, iDataCountFinish, PEN, WLS, STB)
begin
-- Defaults
NState <= IDLE;
iBaudCountClear <= '0';
iDataCountInit <= '0';
iRXFinished <= '0';
case CState is
when IDLE => if (SIN = '0') then -- Start detected
NState <= START;
end if;
iBaudCountClear <= '1';
iDataCountInit <= '1';
when START => iDataCountInit <= '1';
if (iBaudStep = '1') then -- Wait for start bit end
if (iFSIN = '0') then
NState <= DATA;
end if;
else
NState <= START;
end if;
when DATA => if (iDataCountFinish = '1') then -- Received all data bits
if (PEN = '1') then
NState <= PAR; -- Parity enabled
else
NState <= STOP; -- No parity
end if;
else
NState <= DATA;
end if;
when PAR => if (iBaudStep = '1') then -- Wait for parity bit
NState <= STOP;
else
NState <= PAR;
end if;
when STOP => if (iBaudStep = '1') then -- Wait for stop bit
if (iFSIN = '0') then -- No stop bit received
iRXFinished <= '1';
NState <= MWAIT;
else
iRXFinished <= '1';
NState <= IDLE; -- Stop bit end
end if;
else
NState <= STOP;
end if;
when MWAIT => if (SIN = '0') then -- Wait for mark
NState <= MWAIT;
end if;
when others => null;
end case;
end process;
-- Check parity
RX_PARCHECK: process (CLK, RST)
begin
if (RST = '1') then
PE <= '0';
iParityReceived <= '0';
elsif (CLK'event and CLK = '1') then
if (CState = PAR and iBaudStep = '1') then
iParityReceived <= iFSIN; -- Received parity bit
end if;
-- Check parity
if (PEN = '1') then -- Parity enabled
PE <= '0';
if (SP = '1') then -- Sticky parity
if ((EPS xor iParityReceived) = '0') then
PE <= '1'; -- Parity error
end if;
else
if (iParity /= iParityReceived) then
PE <= '1'; -- Parity error
end if;
end if;
else
PE <= '0'; -- Parity disabled
iParityReceived <= '0';
end if;
end if;
end process;
-- Framing error and break interrupt
iNoStopReceived <= '1' when iFSIN = '0' and (CState = STOP) else '0';
iBI <= '1' when iDOUT = "00000000" and
iParityReceived = '0' and
iNoStopReceived = '1' else '0';
iFE <= '1' when iNoStopReceived = '1' else '0';
-- Output signals
DOUT <= iDOUT;
BI <= iBI;
FE <= iFE;
RXFINISHED <= iRXFinished;
end rtl;
|
-- NEED RESULT: ENT00006: port clause not present in entity header passed
-- NEED RESULT: ENT00006_1: port clause present in entity header passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00006
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 1.1.1 (2)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00006(ARCH00006)
-- ENT00006_1(ARCH00006_1)
-- ENT00006_Test_Bench(ARCH00006_Test_Bench)
--
-- REVISION HISTORY:
--
-- 25-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00006 is
end ENT00006 ;
architecture ARCH00006 of ENT00006 is
begin
process
begin
test_report ( "ENT00006" ,
"port clause not present in entity header" ,
true ) ;
wait ;
end process ;
end ARCH00006 ;
use WORK.STANDARD_TYPES.all ;
entity ENT00006_1 is
port ( dummy : boolean := false) ;
end ENT00006_1 ;
architecture ARCH00006_1 of ENT00006_1 is
begin
process
begin
test_report ( "ENT00006_1" ,
"port clause present in entity header" ,
true ) ;
wait ;
end process ;
end ARCH00006_1 ;
entity ENT00006_Test_Bench is
end ENT00006_Test_Bench ;
architecture ARCH00006_Test_Bench of ENT00006_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00006 ( ARCH00006 ) ;
for CIS2 : UUT use entity WORK.ENT00006_1 ( ARCH00006_1 ) ;
begin
CIS1 : UUT ;
CIS2 : UUT ;
end block L1 ;
end ARCH00006_Test_Bench ;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library util;
use util.types_pkg.all;
use work.cpu_types_pkg.all;
use work.cpu_l1mem_inst_types_pkg.all;
package cpu_l1mem_inst_pass_pkg is
type cpu_l1mem_inst_pass_ctrl_in_type is record
request : cpu_l1mem_inst_request_code_type;
cacheen : std_ulogic;
mmuen : std_ulogic;
alloc : std_ulogic;
priv : std_ulogic;
direction : cpu_l1mem_inst_fetch_direction_type;
end record;
type cpu_l1mem_inst_pass_dp_in_type is record
vaddr : cpu_ivaddr_type;
end record;
type cpu_l1mem_inst_pass_ctrl_out_type is record
ready : std_ulogic;
result : cpu_l1mem_inst_result_code_type;
end record;
type cpu_l1mem_inst_pass_dp_out_type is record
paddr : cpu_ipaddr_type;
data : cpu_inst_type;
end record;
end package;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3035.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p01n02i03035ent IS
END c12s02b02x00p01n02i03035ent;
ARCHITECTURE c12s02b02x00p01n02i03035arch OF c12s02b02x00p01n02i03035ent IS
BEGIN
-- test for first element association
bl2: block
generic(i:integer:=10; r:real:=3.4; b:bit:='1');
generic map(i=>5);
begin
assert (i=5)
report "Generic map value for integer generic not correct"
severity failure;
assert (r=3.4)
report "Default value for real generic not correct"
severity failure;
assert (b='1')
report "Default value for bit generic not correct"
severity failure;
assert NOT( i=5 and r=3.4 and b='1')
report "***PASSED TEST: c12s02b02x00p01n02i03035"
severity NOTE;
assert ( i=5 and r=3.4 and b='1')
report "***FAILED TEST: c12s02b02x00p01n02i03035 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03035arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3035.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p01n02i03035ent IS
END c12s02b02x00p01n02i03035ent;
ARCHITECTURE c12s02b02x00p01n02i03035arch OF c12s02b02x00p01n02i03035ent IS
BEGIN
-- test for first element association
bl2: block
generic(i:integer:=10; r:real:=3.4; b:bit:='1');
generic map(i=>5);
begin
assert (i=5)
report "Generic map value for integer generic not correct"
severity failure;
assert (r=3.4)
report "Default value for real generic not correct"
severity failure;
assert (b='1')
report "Default value for bit generic not correct"
severity failure;
assert NOT( i=5 and r=3.4 and b='1')
report "***PASSED TEST: c12s02b02x00p01n02i03035"
severity NOTE;
assert ( i=5 and r=3.4 and b='1')
report "***FAILED TEST: c12s02b02x00p01n02i03035 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03035arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3035.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p01n02i03035ent IS
END c12s02b02x00p01n02i03035ent;
ARCHITECTURE c12s02b02x00p01n02i03035arch OF c12s02b02x00p01n02i03035ent IS
BEGIN
-- test for first element association
bl2: block
generic(i:integer:=10; r:real:=3.4; b:bit:='1');
generic map(i=>5);
begin
assert (i=5)
report "Generic map value for integer generic not correct"
severity failure;
assert (r=3.4)
report "Default value for real generic not correct"
severity failure;
assert (b='1')
report "Default value for bit generic not correct"
severity failure;
assert NOT( i=5 and r=3.4 and b='1')
report "***PASSED TEST: c12s02b02x00p01n02i03035"
severity NOTE;
assert ( i=5 and r=3.4 and b='1')
report "***FAILED TEST: c12s02b02x00p01n02i03035 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03035arch;
|
-------------------------------------------------------------------------------
-- Title : Accelerator Adapter
-- Project :
-------------------------------------------------------------------------------
-- File : asymmetric_dp_bank_v6.vhd
-- Author : rmg/jn
-- Company : Xilinx, Inc.
-- Created : 2012-09-05
-- Last update: 2013-10-25
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- (c) Copyright 2012 Xilinx, Inc. All rights reserved.
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2012-09-05 1.0 rmg/jn Created
-- 2013-10-25 2.0 pvk Added support for UltraScale primitives.
-------------------------------------------------------------------------------
-- ****************************************************************************
--
-- (c) Copyright 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- ****************************************************************************
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
library axis_accelerator_adapter_v2_1_6;
use axis_accelerator_adapter_v2_1_6.xd_adapter_pkg.all;
-- Assumption: Port A is always wider
entity asymmetric_dp_bank_v6 is
generic (
C_FAMILY : string;
C_BRAM_TYPE : string := "7_SERIES"; -- 7_SERIES = RAMB36E1. ULTRASCALE = RAMB36E2
C_PRINT_INFO : boolean := false;
C_BANK_AWIDTH_A : integer;
C_BANK_DWIDTH_A : integer;
C_BANK_AWIDTH_B : integer;
C_BANK_DWIDTH_B : integer);
port (
rst : in std_logic;
clk_a : in std_logic;
ce_a : in std_logic;
we_a : in std_logic;
addr_a : in std_logic_vector(C_BANK_AWIDTH_A-1 downto 0);
din_a : in std_logic_vector(C_BANK_DWIDTH_A-1 downto 0);
dout_a : out std_logic_vector(C_BANK_DWIDTH_A-1 downto 0);
clk_b : in std_logic;
ce_b : in std_logic;
we_b : in std_logic;
addr_b : in std_logic_vector(C_BANK_AWIDTH_B-1 downto 0);
din_b : in std_logic_vector(C_BANK_DWIDTH_B-1 downto 0);
dout_b : out std_logic_vector(C_BANK_DWIDTH_B-1 downto 0));
end asymmetric_dp_bank_v6;
architecture rtl of asymmetric_dp_bank_v6 is
constant MAX_BRAM_AWIDTH : integer := 15; -- 32Kx1
constant MIN_BRAM_AWIDTH : integer := 10; -- 1Kx32
constant MAX_BRAM_DWIDTH : integer := 32; -- 1Kx32
constant MIN_BRAM_DWIDTH : integer := 1; -- 32Kx1
constant DATA_RATIO : integer := C_BANK_DWIDTH_A/C_BANK_DWIDTH_B;
function calc_bram_dwidth(bank_awidth : natural; bank_dwidth : natural) return integer is
variable dwidth : integer;
begin
if(bank_awidth > MAX_BRAM_AWIDTH) then
-- If required address bitwidth is bigger than possible bitwidth, then we
-- have to increase depth. In this case, the BRAMs are configured x1.
dwidth := 1;
else
-- bitwidth for data bus is calculated using the following expression:
dwidth := 2**(MAX_BRAM_AWIDTH-bank_awidth);
-- assuming that we do not go above max possible bitwidth:
if(dwidth > MAX_BRAM_DWIDTH) then
dwidth := MAX_BRAM_DWIDTH;
end if;
-- But, if it goes above the width of the bank, we limit to such width
if(dwidth > bank_dwidth) then
dwidth := bank_dwidth;
end if;
if(dwidth*DATA_RATIO > MAX_BRAM_DWIDTH) then
dwidth := MAX_BRAM_DWIDTH/DATA_RATIO;
end if;
end if;
return dwidth;
end function calc_bram_dwidth;
-- Dimensioning of bank according to narrow port
constant BRAM_AWIDTH_B : integer := min_size(C_BANK_AWIDTH_B, MAX_BRAM_AWIDTH);
constant BRAM_DWIDTH_B : integer := calc_bram_dwidth(C_BANK_AWIDTH_B, C_BANK_DWIDTH_B);
constant N_BRAM : integer := div_round_up(C_BANK_DWIDTH_B, BRAM_DWIDTH_B);
constant BRAM_AWIDTH_A : integer := BRAM_AWIDTH_B-log2(DATA_RATIO);
constant BRAM_DWIDTH_A : integer := BRAM_DWIDTH_B*DATA_RATIO;
constant COL_SIZE : integer := 2**(C_BANK_AWIDTH_B-BRAM_AWIDTH_B);
begin
NO_DEPTH_EXPANSION_GEN : if (C_BANK_AWIDTH_B <= MAX_BRAM_AWIDTH) generate
signal bram_addr_a : std_logic_vector(15 downto 0);
signal bram_addr_b : std_logic_vector(15 downto 0);
begin
process(addr_a)
constant BRAM_ADDR_LSB : integer := log2(BRAM_DWIDTH_A);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+BRAM_AWIDTH_A-1;
begin
bram_addr_a <= (others => '0');
bram_addr_a(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_a;
end process;
process(addr_b)
constant BRAM_ADDR_LSB : integer := log2(BRAM_DWIDTH_B);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+BRAM_AWIDTH_B-1;
begin
bram_addr_b <= (others => '0');
bram_addr_b(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_b;
end process;
MEM_BANK_GEN : for i in 0 to N_BRAM-1 generate
signal bram_din_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_a : std_logic_vector(3 downto 0);
signal bram_din_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_b : std_logic_vector(7 downto 0);
begin
-- In the input dus (wide), BRAM i gives support to slice i of each of
-- the DATA_RATIO subwords.
process(din_a)
begin
bram_din_a <= (others => '1');
for k in 0 to DATA_RATIO-1 loop
-- from each subwordk, we take slice i
bram_din_a(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k) <=
din_a(BRAM_DWIDTH_B*(i+1)-1+C_BANK_DWIDTH_B*k downto BRAM_DWIDTH_B*i+C_BANK_DWIDTH_B*k);
end loop;
end process;
DOUT_A_GEN : for k in 0 to DATA_RATIO-1 generate
begin
dout_a(BRAM_DWIDTH_B*(i+1)-1+C_BANK_DWIDTH_B*k downto BRAM_DWIDTH_B*i+C_BANK_DWIDTH_B*k) <=
bram_dout_a(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k);
end generate DOUT_A_GEN;
-- narrow port (B), we group the slices:
process(din_b)
begin
bram_din_b <= (others => '0');
bram_din_b(BRAM_DWIDTH_B-1 downto 0) <= din_b(BRAM_DWIDTH_B*(i+1)-1 downto BRAM_DWIDTH_B*i);
end process;
dout_b(BRAM_DWIDTH_B*(i+1)-1 downto BRAM_DWIDTH_B*i) <= bram_dout_b(BRAM_DWIDTH_B-1 downto 0);
-- No support for byte-enable we signals
bram_we_a <= (others => we_a);
bram_we_b <= (others => we_b);
--------------------------
-- 7 Series BRAM Primitive
--------------------------
BRAM_7_SERIES : if (C_BRAM_TYPE = "7_SERIES") generate
begin
BRAM_I : RAMB36E1
generic map (
SIM_COLLISION_CHECK => "ALL", -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", -- "PERFORMANCE" or "DELAYED_WRITE"
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
EN_ECC_READ => false, -- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_WRITE => false,
INIT_A => x"000000000", -- INIT_A, INIT_B: Initial values on output ports
INIT_B => x"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RAM_EXTENSION_A => "NONE", -- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP", -- "SDP" or "TDP"
READ_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36
READ_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36
WRITE_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE", -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => x"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_B => x"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_B => "READ_FIRST")
port map (
-- ECC Signals: 1-bit (each) output Error Correction Circuitry ports
INJECTDBITERR => '0', -- 1-bit input Inject a double bit error
INJECTSBITERR => '0', -- 1-bit input Inject a single bit error
DBITERR => open, -- 1-bit output double bit error status output
ECCPARITY => open, -- 8-bit output generated error correction parity
RDADDRECC => open, -- 9-bit output ECC read address
SBITERR => open, -- 1-bit output Single bit error status output
CASCADEINA => '0', -- 1-bit input A port cascade input
CASCADEOUTA => open, -- 1-bit output A port cascade output
DIADI => bram_din_a, -- 32-bit input A port data/LSB data input
DIPADIP => x"0", -- 4-bit input A port parity/LSB parity input
DOADO => bram_dout_a, -- 32-bit output A port data/LSB data output
DOPADOP => open, -- 4-bit output A port parity/LSB parity output
ADDRARDADDR => bram_addr_a, -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a, -- 1-bit input A port clock/Read clock input
ENARDEN => ce_a, -- 1-bit input A port enable/Read enable input
REGCEAREGCE => '1', -- 1-bit input A port register enable/Register enable input
RSTRAMARSTRAM => rst, -- 1-bit input A port set/reset input
RSTREGARSTREG => '0', -- 1-bit input A port register set/reset input
WEA => bram_we_a, -- 4-bit input A port write enable input
CASCADEINB => '0', -- 1-bit input B port cascade input
CASCADEOUTB => open, -- 1-bit output B port cascade output
DIBDI => bram_din_b, -- 32-bit input B port data/MSB data input
DIPBDIP => x"0", -- 4-bit input B port parity/MSB parity input
DOBDO => bram_dout_b, -- 32-bit output B port data/MSB data output
DOPBDOP => open, -- 4-bit output B port parity/MSB parity output
ADDRBWRADDR => bram_addr_b, -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b, -- 1-bit input B port clock/Write clock input
ENBWREN => ce_b, -- 1-bit input B port enable/Write enable input
REGCEB => '1', -- 1-bit input B port register enable input
RSTRAMB => rst, -- Reset del latch de salida de la memoria (1 bit)
RSTREGB => '0', -- Reset del registro opcional de salida (1 bit)
--WEBWE => x"FF"); -- 8-bit input B port write enable/Write enable input
WEBWE => bram_we_b); -- 8-bit input B port write enable/Write enable input
end generate BRAM_7_SERIES;
--------------------------
-- 8 Series BRAM Primitive
--------------------------
BRAM_8_SERIES : if (C_BRAM_TYPE = "ULTRASCALE") generate
begin
BRAM_I: RAMB36E2
GENERIC MAP (
SIM_COLLISION_CHECK => "ALL",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
READ_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72,
WRITE_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36,
READ_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36,
WRITE_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SLEEP_ASYNC => "FALSE",
SRVAL_A => X"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output,
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"),
WRITE_MODE_B => "READ_FIRST"
)
PORT MAP (
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DBITERR => open,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
CASDOUTA => open,
CASDOUTB => open,
CASDOUTPA => open,
CASDOUTPB => open,
CASOUTDBITERR => open,
CASOUTSBITERR => open,
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDOMUXEN_A => '0',
CASDOMUXEN_B => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
CASDINA => (OTHERS => '0'),
CASDINB => (OTHERS => '0'),
CASDINPA => (OTHERS => '0'),
CASDINPB => (OTHERS => '0'),
CASDOMUXA => '0',
CASDOMUXB => '0',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
DINADIN => bram_din_a, -- 32-bit input A port data/LSB data input
DINPADINP => x"0", -- 4-bit input A port parity/LSB parity input,
DOUTADOUT => bram_dout_a, -- 32-bit output A port data/LSB data output
DOUTPADOUTP => open,
ADDRARDADDR => bram_addr_a(14 downto 0), -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a,
ENARDEN => ce_a, -- 1-bit input A port enable/Read enable input
ADDRENA => '0',
REGCEAREGCE => '1',
RSTRAMARSTRAM => rst,
RSTREGARSTREG => '0',
WEA => bram_we_a, -- 4-bit input A port write enable input
DINBDIN => bram_din_b, -- 32-bit input B port data/MSB data input
DINPBDINP => x"0", -- 4-bit input B port parity/MSB parity input
DOUTBDOUT => bram_dout_b, -- 32-bit output B port data/MSB data output
DOUTPBDOUTP => open,
ADDRBWRADDR => bram_addr_b(14 downto 0), -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b,
ENBWREN => ce_b, -- 1-bit input B port enable/Write enable input
ADDRENB => '0',
ECCPIPECE => '0',
REGCEB => '1',
RSTRAMB => rst,
RSTREGB => '0',
SLEEP => '0',
WEBWE => bram_we_b -- 8-bit input B port write enable/Write enable input
);
end generate BRAM_8_SERIES;
end generate MEM_BANK_GEN;
end generate NO_DEPTH_EXPANSION_GEN;
DEPTH_EXPANSION_GEN : if (C_BANK_AWIDTH_B > MAX_BRAM_AWIDTH) generate
signal bram_addr_a : std_logic_vector(15 downto 0);
signal bram_addr_b : std_logic_vector(15 downto 0);
constant WORD_AWIDTH : integer := log2(COL_SIZE);
constant BRAM_SEL_A_MSB : integer := C_BANK_AWIDTH_A-1;
constant BRAM_SEL_A_LSB : integer := BRAM_SEL_A_MSB-(WORD_AWIDTH-1);
constant BRAM_SEL_B_MSB : integer := C_BANK_AWIDTH_B-1;
constant BRAM_SEL_B_LSB : integer := BRAM_SEL_B_MSB-(WORD_AWIDTH-1);
signal bram_ce_a : std_logic_vector(COL_SIZE-1 downto 0);
signal bram_ce_b : std_logic_vector(COL_SIZE-1 downto 0);
signal bram_sel_addr_a : std_logic_vector(WORD_AWIDTH-1 downto 0);
signal bram_sel_addr_b : std_logic_vector(WORD_AWIDTH-1 downto 0);
begin
-- Use the WORD_AWIDTH MS bits to select the BRAM inside the column
process(addr_a, ce_a)
begin
bram_ce_a <= (others => '0');
if (ce_a = '1') then
for i in 0 to COL_SIZE-1 loop
if (unsigned(addr_a(BRAM_SEL_A_MSB downto BRAM_SEL_A_LSB)) = i) then
bram_ce_a(i) <= '1';
end if;
end loop;
end if;
end process;
process(addr_b, ce_b)
begin
bram_ce_b <= (others => '0');
if (ce_b = '1') then
for i in 0 to COL_SIZE-1 loop
if (unsigned(addr_b(BRAM_SEL_B_MSB downto BRAM_SEL_B_LSB)) = i) then
bram_ce_b(i) <= '1';
end if;
end loop;
end if;
end process;
-- this section of bits has to be registered to generate the selection
-- signal for the mux's of output datapath
process(clk_a)
begin
if (clk_a'event and clk_a = '1') then
if (ce_a = '1') then
bram_sel_addr_a <= addr_a(BRAM_SEL_A_MSB downto BRAM_SEL_A_LSB);
end if;
end if;
end process;
process(clk_b)
begin
if (clk_b'event and clk_b = '1') then
if (ce_b = '1') then
bram_sel_addr_b <= addr_b(BRAM_SEL_B_MSB downto BRAM_SEL_B_LSB);
end if;
end if;
end process;
-- In this case, given that it is depth increase we use all width of BRAM
-- address bus of wide port
process(addr_b)
constant BRAM_ADDR_LSB : integer := log2(BRAM_DWIDTH_B);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+BRAM_AWIDTH_B-1;
constant ADDR_LSB : integer := 0;
constant ADDR_MSB : integer := MAX_BRAM_AWIDTH-1;
begin
bram_addr_b <= (others => '0');
bram_addr_b(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_b(ADDR_MSB downto ADDR_LSB);
end process;
-- and, in the narrow port, it's the same but reducing the width log2(DATA_RATIO):
process(addr_a)
constant BRAM_ADDR_LSB : integer := log2(BRAM_DWIDTH_A);
constant BRAM_ADDR_MSB : integer := BRAM_ADDR_LSB+BRAM_AWIDTH_A-1;
-- same as wide port minus log2(DATA_RATIO):
constant ADDR_LSB : integer := 0;
constant ADDR_MSB : integer := (MAX_BRAM_AWIDTH-log2(DATA_RATIO))-1;
begin
bram_addr_a <= (others => '0');
bram_addr_a(BRAM_ADDR_MSB downto BRAM_ADDR_LSB) <= addr_a(ADDR_MSB downto ADDR_LSB);
end process;
MEM_BANK_GEN : for i in 0 to N_BRAM-1 generate
signal bram_din_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_a : std_logic_vector(3 downto 0);
signal bram_din_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_we_b : std_logic_vector(7 downto 0);
-- These superbusses represent group data busses at the output of BRAMs
-- in same column
signal col_dout_a : std_logic_vector(COL_SIZE*BRAM_DWIDTH_A-1 downto 0);
signal col_dout_b : std_logic_vector(COL_SIZE*BRAM_DWIDTH_B-1 downto 0);
-- this is for the output mux
signal mux_dout_a : std_logic_vector(BRAM_DWIDTH_A-1 downto 0);
signal mux_dout_b : std_logic_vector(BRAM_DWIDTH_B-1 downto 0);
signal bram_dout_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
begin
-- In the input port of wide bus, BRAM i gives support to slide i of each
-- of DATA_RATIO subwords
process(din_a)
begin
bram_din_a <= (others => '1');
for k in 0 to DATA_RATIO-1 loop
-- from each subword k, we take slice i
bram_din_a(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k) <=
din_a(BRAM_DWIDTH_B*(i+1)-1+C_BANK_DWIDTH_B*k downto BRAM_DWIDTH_B*i+C_BANK_DWIDTH_B*k);
end loop;
end process;
-- in the narrow port(B), we group the slices:
process(din_b)
begin
bram_din_b <= (others => '0');
bram_din_b(BRAM_DWIDTH_B-1 downto 0) <= din_b(BRAM_DWIDTH_B*(i+1)-1 downto BRAM_DWIDTH_B*i);
end process;
-- mux's in the output data busses in the same column
process(col_dout_a, bram_sel_addr_a)
begin
mux_dout_a <= (others => '0');
for k in 0 to COL_SIZE-1 loop
if (unsigned(bram_sel_addr_a) = k) then
mux_dout_a <= col_dout_a(BRAM_DWIDTH_A*(k+1)-1 downto BRAM_DWIDTH_A*k);
end if;
end loop;
end process;
process(col_dout_b, bram_sel_addr_b)
begin
mux_dout_b <= (others => '0');
for k in 0 to COL_SIZE-1 loop
if (unsigned(bram_sel_addr_b) = k) then
mux_dout_b <= col_dout_b(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k);
end if;
end loop;
end process;
-- For the output datapath, we apply the same criterio that in the input
-- datapath
-- For the wide port, we apply interleave with the output of the mux
DOUT_A_GEN : for k in 0 to DATA_RATIO-1 generate
begin
dout_a(BRAM_DWIDTH_B*(i+1)-1+C_BANK_DWIDTH_B*k downto BRAM_DWIDTH_B*i+C_BANK_DWIDTH_B*k) <=
mux_dout_a(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k);
end generate DOUT_A_GEN;
-- for the narrow port, we directly take the slice
dout_b(BRAM_DWIDTH_B*(i+1)-1 downto BRAM_DWIDTH_B*i) <= mux_dout_b(BRAM_DWIDTH_B-1 downto 0);
-- No byte-enable for we signals
bram_we_a <= (others => we_a);
bram_we_b <= (others => we_b);
BRAM_COL_GEN : for k in 0 to COL_SIZE-1 generate
signal bram_dout_a : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
signal bram_dout_b : std_logic_vector(MAX_BRAM_DWIDTH-1 downto 0);
begin
-- This superbus groups the output datapaths
col_dout_a(BRAM_DWIDTH_A*(k+1)-1 downto BRAM_DWIDTH_A*k) <= bram_dout_a(BRAM_DWIDTH_A-1 downto 0);
col_dout_b(BRAM_DWIDTH_B*(k+1)-1 downto BRAM_DWIDTH_B*k) <= bram_dout_b(BRAM_DWIDTH_B-1 downto 0);
--------------------------
-- 7 Series BRAM Primitive
--------------------------
BRAM_7_SERIES : if (C_BRAM_TYPE = "7_SERIES") generate
begin
BRAM_I : RAMB36E1
generic map (
SIM_COLLISION_CHECK => "ALL", -- Colision check: Values ("ALL", "WARNING_ONLY", "GENERATE_X_ONLY" or "NONE")
RDADDR_COLLISION_HWCONFIG => "DELAYED_WRITE", -- "PERFORMANCE" or "DELAYED_WRITE"
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
EN_ECC_READ => false, -- Error Correction Circuitry (ECC): Encoder/decoder enable (TRUE/FALSE)
EN_ECC_WRITE => false,
INIT_A => x"000000000", -- INIT_A, INIT_B: Initial values on output ports
INIT_B => x"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RAM_EXTENSION_A => "NONE", -- RAM_EXTENSION_A, RAM_EXTENSION_B: Selects cascade mode ("UPPER", "LOWER", or "NONE")
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP", -- "SDP" or "TDP"
READ_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72
WRITE_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36
READ_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36
WRITE_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE", -- RSTREG_PRIORITY_A, RSTREG_PRIORITY_B: Reset or enable priority ("RSTREG" or "REGCE")
RSTREG_PRIORITY_B => "REGCE",
SRVAL_A => x"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output
SRVAL_B => x"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE")
WRITE_MODE_B => "READ_FIRST")
port map (
-- ECC Signals: 1-bit (each) output Error Correction Circuitry ports
INJECTDBITERR => '0', -- 1-bit input Inject a double bit error
INJECTSBITERR => '0', -- 1-bit input Inject a single bit error
DBITERR => open, -- 1-bit output double bit error status output
ECCPARITY => open, -- 8-bit output generated error correction parity
RDADDRECC => open, -- 9-bit output ECC read address
SBITERR => open, -- 1-bit output Single bit error status output
CASCADEINA => '0', -- 1-bit input A port cascade input
CASCADEOUTA => open, -- 1-bit output A port cascade output
DIADI => bram_din_a, -- 32-bit input A port data/LSB data input
DIPADIP => x"0", -- 4-bit input A port parity/LSB parity input
DOADO => bram_dout_a, -- 32-bit output A port data/LSB data output
DOPADOP => open, -- 4-bit output A port parity/LSB parity output
ADDRARDADDR => bram_addr_a, -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a, -- 1-bit input A port clock/Read clock input
ENARDEN => bram_ce_a(k), -- 1-bit input A port enable/Read enable input
REGCEAREGCE => '1', -- 1-bit input A port register enable/Register enable input
RSTRAMARSTRAM => rst, -- 1-bit input A port set/reset input
RSTREGARSTREG => '0', -- 1-bit input A port register set/reset input
WEA => bram_we_a, -- 4-bit input A port write enable input
CASCADEINB => '0', -- 1-bit input B port cascade input
CASCADEOUTB => open, -- 1-bit output B port cascade output
DIBDI => bram_din_b, -- 32-bit input B port data/MSB data input
DIPBDIP => x"0", -- 4-bit input B port parity/MSB parity input
DOBDO => bram_dout_b, -- 32-bit output B port data/MSB data output
DOPBDOP => open, -- 4-bit output B port parity/MSB parity output
ADDRBWRADDR => bram_addr_b, -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b, -- 1-bit input B port clock/Write clock input
ENBWREN => bram_ce_b(k), -- 1-bit input B port enable/Write enable input
REGCEB => '1', -- 1-bit input B port register enable input
RSTRAMB => rst, -- Reset del latch de salida de la memoria (1 bit)
RSTREGB => '0', -- Reset del registro opcional de salida (1 bit)
--WEBWE => x"FF"); -- 8-bit input B port write enable/Write enable input
WEBWE => bram_we_b); -- 8-bit input B port write enable/Write enable input
end generate BRAM_7_SERIES;
--------------------------
-- 8 Series BRAM Primitive
--------------------------
BRAM_8_SERIES : if (C_BRAM_TYPE = "ULTRASCALE") generate
begin
BRAM_I: RAMB36E2
GENERIC MAP (
SIM_COLLISION_CHECK => "ALL",
CASCADE_ORDER_A => "NONE",
CASCADE_ORDER_B => "NONE",
CLOCK_DOMAINS => "INDEPENDENT",
DOA_REG => 0, -- DOA_REG, DOB_REG: Optional output register (0 or 1)
DOB_REG => 0,
ENADDRENA => "FALSE",
ENADDRENB => "FALSE",
EN_ECC_PIPE => "FALSE",
EN_ECC_READ => "FALSE",
EN_ECC_WRITE => "FALSE",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE", -- RAM initialization file
RDADDRCHANGEA => "FALSE",
RDADDRCHANGEB => "FALSE",
READ_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- READ_WIDTH_A: 0, 1, 2, 4, 9, 18, 36, 72,
WRITE_WIDTH_A => BRAM_DWIDTH_A+(BRAM_DWIDTH_A/8), -- WRITE_WIDTH_A: 0, 1, 2, 4, 9, 18, 36,
READ_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- READ_WIDTH_B: 0, 1, 2, 4, 9, 18, 36,
WRITE_WIDTH_B => BRAM_DWIDTH_B+(BRAM_DWIDTH_B/8), -- WRITE_WIDTH_B: 0, 1, 2, 4, 9, 18, 36, 72
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SLEEP_ASYNC => "FALSE",
SRVAL_A => X"000000000", -- SRVAL_A, SRVAL_B: Set/reset value for output,
SRVAL_B => X"000000000",
WRITE_MODE_A => "READ_FIRST", -- WriteMode: Value on output upon a write ("WRITE_FIRST", "READ_FIRST", or "NO_CHANGE"),
WRITE_MODE_B => "READ_FIRST"
)
PORT MAP (
INJECTDBITERR => '0',
INJECTSBITERR => '0',
DBITERR => open,
ECCPARITY => open,
RDADDRECC => open,
SBITERR => open,
CASDOUTA => open,
CASDOUTB => open,
CASDOUTPA => open,
CASDOUTPB => open,
CASOUTDBITERR => open,
CASOUTSBITERR => open,
CASDIMUXA => '0',
CASDIMUXB => '0',
CASDOMUXEN_A => '0',
CASDOMUXEN_B => '0',
CASOREGIMUXEN_A => '0',
CASOREGIMUXEN_B => '0',
CASDINA => (OTHERS => '0'),
CASDINB => (OTHERS => '0'),
CASDINPA => (OTHERS => '0'),
CASDINPB => (OTHERS => '0'),
CASDOMUXA => '0',
CASDOMUXB => '0',
CASINDBITERR => '0',
CASINSBITERR => '0',
CASOREGIMUXA => '0',
CASOREGIMUXB => '0',
DINADIN => bram_din_a, -- 32-bit input A port data/LSB data input
DINPADINP => x"0", -- 4-bit input A port parity/LSB parity input,
DOUTADOUT => bram_dout_a, -- 32-bit output A port data/LSB data output
DOUTPADOUTP => open,
ADDRARDADDR => bram_addr_a(14 downto 0), -- 16-bit input A port address/Read address input
CLKARDCLK => clk_a,
ENARDEN => bram_ce_a(k), -- 1-bit input A port enable/Read enable input
ADDRENA => '0',
REGCEAREGCE => '1',
RSTRAMARSTRAM => rst,
RSTREGARSTREG => '0',
WEA => bram_we_a, -- 4-bit input A port write enable input
DINBDIN => bram_din_b, -- 32-bit input B port data/MSB data input
DINPBDINP => x"0", -- 4-bit input B port parity/MSB parity input
DOUTBDOUT => bram_dout_b, -- 32-bit output B port data/MSB data output
DOUTPBDOUTP => open,
ADDRBWRADDR => bram_addr_b(14 downto 0), -- 16-bit input B port address/Write address input
CLKBWRCLK => clk_b,
ENBWREN => bram_ce_b(k), -- 1-bit input B port enable/Write enable input
ADDRENB => '0',
ECCPIPECE => '0',
REGCEB => '1',
RSTRAMB => rst,
RSTREGB => '0',
SLEEP => '0',
WEBWE => bram_we_b -- 8-bit input B port write enable/Write enable input
);
end generate BRAM_8_SERIES;
end generate BRAM_COL_GEN;
end generate MEM_BANK_GEN;
end generate DEPTH_EXPANSION_GEN;
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: devices
-- File: devices.vhd
-- Author: Aeroflex Gaisler AB
-- Description: Vendor and devices IDs for AMBA plug&play
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package devices is
-- Vendor codes
constant VENDOR_RESERVED : amba_vendor_type := 16#00#; -- Do not use!
constant VENDOR_GAISLER : amba_vendor_type := 16#01#;
constant VENDOR_PENDER : amba_vendor_type := 16#02#;
constant VENDOR_ESA : amba_vendor_type := 16#04#;
constant VENDOR_ASTRIUM : amba_vendor_type := 16#06#;
constant VENDOR_OPENCHIP : amba_vendor_type := 16#07#;
constant VENDOR_OPENCORES : amba_vendor_type := 16#08#;
constant VENDOR_CONTRIB : amba_vendor_type := 16#09#;
constant VENDOR_DLR : amba_vendor_type := 16#0A#;
constant VENDOR_EONIC : amba_vendor_type := 16#0B#;
constant VENDOR_TELECOMPT : amba_vendor_type := 16#0C#;
constant VENDOR_DTU : amba_vendor_type := 16#0D#;
constant VENDOR_BSC : amba_vendor_type := 16#0E#;
constant VENDOR_RADIONOR : amba_vendor_type := 16#0F#;
constant VENDOR_GLEICHMANN : amba_vendor_type := 16#10#;
constant VENDOR_MENTA : amba_vendor_type := 16#11#;
constant VENDOR_SUN : amba_vendor_type := 16#13#;
constant VENDOR_MOVIDIA : amba_vendor_type := 16#14#;
constant VENDOR_ORBITA : amba_vendor_type := 16#17#;
constant VENDOR_SYNOPSYS : amba_vendor_type := 16#21#;
constant VENDOR_NASA : amba_vendor_type := 16#22#;
constant VENDOR_S3 : amba_vendor_type := 16#31#;
constant VENDOR_ACTEL : amba_vendor_type := 16#AC#;
constant VENDOR_APPLECORE : amba_vendor_type := 16#AE#;
constant VENDOR_C3E : amba_vendor_type := 16#C3#;
constant VENDOR_CAL : amba_vendor_type := 16#CA#;
constant VENDOR_CETON : amba_vendor_type := 16#CB#;
constant VENDOR_EMBEDDIT : amba_vendor_type := 16#EA#;
-- Aeroflex Gaisler device ids
constant GAISLER_LEON2DSU : amba_device_type := 16#002#;
constant GAISLER_LEON3 : amba_device_type := 16#003#;
constant GAISLER_LEON3DSU : amba_device_type := 16#004#;
constant GAISLER_ETHAHB : amba_device_type := 16#005#;
constant GAISLER_APBMST : amba_device_type := 16#006#;
constant GAISLER_AHBUART : amba_device_type := 16#007#;
constant GAISLER_SRCTRL : amba_device_type := 16#008#;
constant GAISLER_SDCTRL : amba_device_type := 16#009#;
constant GAISLER_SSRCTRL : amba_device_type := 16#00A#;
constant GAISLER_I2C2AHB : amba_device_type := 16#00B#;
constant GAISLER_APBUART : amba_device_type := 16#00C#;
constant GAISLER_IRQMP : amba_device_type := 16#00D#;
constant GAISLER_AHBRAM : amba_device_type := 16#00E#;
constant GAISLER_AHBDPRAM : amba_device_type := 16#00F#;
constant GAISLER_GRIOMMU2 : amba_device_type := 16#010#;
constant GAISLER_GPTIMER : amba_device_type := 16#011#;
constant GAISLER_PCITRG : amba_device_type := 16#012#;
constant GAISLER_PCISBRG : amba_device_type := 16#013#;
constant GAISLER_PCIFBRG : amba_device_type := 16#014#;
constant GAISLER_PCITRACE : amba_device_type := 16#015#;
constant GAISLER_DMACTRL : amba_device_type := 16#016#;
constant GAISLER_AHBTRACE : amba_device_type := 16#017#;
constant GAISLER_DSUCTRL : amba_device_type := 16#018#;
constant GAISLER_CANAHB : amba_device_type := 16#019#;
constant GAISLER_GPIO : amba_device_type := 16#01A#;
constant GAISLER_AHBROM : amba_device_type := 16#01B#;
constant GAISLER_AHBJTAG : amba_device_type := 16#01C#;
constant GAISLER_ETHMAC : amba_device_type := 16#01D#;
constant GAISLER_SWNODE : amba_device_type := 16#01E#;
constant GAISLER_SPW : amba_device_type := 16#01F#;
constant GAISLER_AHB2AHB : amba_device_type := 16#020#;
constant GAISLER_USBDC : amba_device_type := 16#021#;
constant GAISLER_USB_DCL : amba_device_type := 16#022#;
constant GAISLER_DDRMP : amba_device_type := 16#023#;
constant GAISLER_ATACTRL : amba_device_type := 16#024#;
constant GAISLER_DDRSP : amba_device_type := 16#025#;
constant GAISLER_EHCI : amba_device_type := 16#026#;
constant GAISLER_UHCI : amba_device_type := 16#027#;
constant GAISLER_I2CMST : amba_device_type := 16#028#;
constant GAISLER_SPW2 : amba_device_type := 16#029#;
constant GAISLER_AHBDMA : amba_device_type := 16#02A#;
constant GAISLER_NUHOSP3 : amba_device_type := 16#02B#;
constant GAISLER_CLKGATE : amba_device_type := 16#02C#;
constant GAISLER_SPICTRL : amba_device_type := 16#02D#;
constant GAISLER_DDR2SP : amba_device_type := 16#02E#;
constant GAISLER_SLINK : amba_device_type := 16#02F#;
constant GAISLER_GRTM : amba_device_type := 16#030#;
constant GAISLER_GRTC : amba_device_type := 16#031#;
constant GAISLER_GRPW : amba_device_type := 16#032#;
constant GAISLER_GRCTM : amba_device_type := 16#033#;
constant GAISLER_GRHCAN : amba_device_type := 16#034#;
constant GAISLER_GRFIFO : amba_device_type := 16#035#;
constant GAISLER_GRADCDAC : amba_device_type := 16#036#;
constant GAISLER_GRPULSE : amba_device_type := 16#037#;
constant GAISLER_GRTIMER : amba_device_type := 16#038#;
constant GAISLER_AHB2PP : amba_device_type := 16#039#;
constant GAISLER_GRVERSION : amba_device_type := 16#03A#;
constant GAISLER_APB2PW : amba_device_type := 16#03B#;
constant GAISLER_PW2APB : amba_device_type := 16#03C#;
constant GAISLER_GRCAN : amba_device_type := 16#03D#;
constant GAISLER_I2CSLV : amba_device_type := 16#03E#;
constant GAISLER_U16550 : amba_device_type := 16#03F#;
constant GAISLER_AHBMST_EM : amba_device_type := 16#040#;
constant GAISLER_AHBSLV_EM : amba_device_type := 16#041#;
constant GAISLER_GRTESTMOD : amba_device_type := 16#042#;
constant GAISLER_ASCS : amba_device_type := 16#043#;
constant GAISLER_IPMVBCTRL : amba_device_type := 16#044#;
constant GAISLER_SPIMCTRL : amba_device_type := 16#045#;
constant GAISLER_L4STAT : amba_device_type := 16#047#;
constant GAISLER_LEON4 : amba_device_type := 16#048#;
constant GAISLER_LEON4DSU : amba_device_type := 16#049#;
constant GAISLER_PWM : amba_device_type := 16#04A#;
constant GAISLER_L2CACHE : amba_device_type := 16#04B#;
constant GAISLER_SDCTRL64 : amba_device_type := 16#04C#;
constant GAISLER_GR1553B : amba_device_type := 16#04D#;
constant GAISLER_1553TST : amba_device_type := 16#04E#;
constant GAISLER_GRIOMMU : amba_device_type := 16#04F#;
constant GAISLER_FTAHBRAM : amba_device_type := 16#050#;
constant GAISLER_FTSRCTRL : amba_device_type := 16#051#;
constant GAISLER_AHBSTAT : amba_device_type := 16#052#;
constant GAISLER_LEON3FT : amba_device_type := 16#053#;
constant GAISLER_FTMCTRL : amba_device_type := 16#054#;
constant GAISLER_FTSDCTRL : amba_device_type := 16#055#;
constant GAISLER_FTSRCTRL8 : amba_device_type := 16#056#;
constant GAISLER_MEMSCRUB : amba_device_type := 16#057#;
constant GAISLER_FTSDCTRL64: amba_device_type := 16#058#;
constant GAISLER_NANDFCTRL : amba_device_type := 16#059#;
constant GAISLER_N2DLLCTRL : amba_device_type := 16#05A#;
constant GAISLER_N2PLLCTRL : amba_device_type := 16#05B#;
constant GAISLER_SPI2AHB : amba_device_type := 16#05C#;
constant GAISLER_DDRSDMUX : amba_device_type := 16#05D#;
constant GAISLER_AHBFROM : amba_device_type := 16#05E#;
constant GAISLER_PCIEXP : amba_device_type := 16#05F#;
constant GAISLER_APBPS2 : amba_device_type := 16#060#;
constant GAISLER_VGACTRL : amba_device_type := 16#061#;
constant GAISLER_LOGAN : amba_device_type := 16#062#;
constant GAISLER_SVGACTRL : amba_device_type := 16#063#;
constant GAISLER_T1AHB : amba_device_type := 16#064#;
constant GAISLER_MP7WRAP : amba_device_type := 16#065#;
constant GAISLER_GRSYSMON : amba_device_type := 16#066#;
constant GAISLER_GRACECTRL : amba_device_type := 16#067#;
constant GAISLER_ATAHBSLV : amba_device_type := 16#068#;
constant GAISLER_ATAHBMST : amba_device_type := 16#069#;
constant GAISLER_ATAPBSLV : amba_device_type := 16#06A#;
constant GAISLER_MIGDDR2 : amba_device_type := 16#06B#;
constant GAISLER_LCDCTRL : amba_device_type := 16#06C#;
constant GAISLER_SWITCHOVER: amba_device_type := 16#06D#;
constant GAISLER_FIFOUART : amba_device_type := 16#06E#;
constant GAISLER_MUXCTRL : amba_device_type := 16#06F#;
constant GAISLER_B1553BC : amba_device_type := 16#070#;
constant GAISLER_B1553RT : amba_device_type := 16#071#;
constant GAISLER_B1553BRM : amba_device_type := 16#072#;
constant GAISLER_AES : amba_device_type := 16#073#;
constant GAISLER_ECC : amba_device_type := 16#074#;
constant GAISLER_PCIF : amba_device_type := 16#075#;
constant GAISLER_CLKMOD : amba_device_type := 16#076#;
constant GAISLER_HAPSTRAK : amba_device_type := 16#077#;
constant GAISLER_TEST_1X2 : amba_device_type := 16#078#;
constant GAISLER_WILD2AHB : amba_device_type := 16#079#;
constant GAISLER_BIO1 : amba_device_type := 16#07A#;
constant GAISLER_AESDMA : amba_device_type := 16#07B#;
constant GAISLER_GRPCI2 : amba_device_type := 16#07C#;
constant GAISLER_GRPCI2_DMA: amba_device_type := 16#07D#;
constant GAISLER_GRPCI2_TB : amba_device_type := 16#07E#;
constant GAISLER_MMA : amba_device_type := 16#07F#;
constant GAISLER_SATCAN : amba_device_type := 16#080#;
constant GAISLER_CANMUX : amba_device_type := 16#081#;
constant GAISLER_GRTMRX : amba_device_type := 16#082#;
constant GAISLER_GRTCTX : amba_device_type := 16#083#;
constant GAISLER_GRTMDESC : amba_device_type := 16#084#;
constant GAISLER_GRTMVC : amba_device_type := 16#085#;
constant GAISLER_GEFFE : amba_device_type := 16#086#;
constant GAISLER_GPREG : amba_device_type := 16#087#;
constant GAISLER_GRTMPAHB : amba_device_type := 16#088#;
constant GAISLER_SPWCUC : amba_device_type := 16#089#;
constant GAISLER_SPW2_DMA : amba_device_type := 16#08A#;
constant GAISLER_SPWROUTER : amba_device_type := 16#08B#;
constant GAISLER_EDCLMST : amba_device_type := 16#08C#;
constant GAISLER_GRPWTX : amba_device_type := 16#08D#;
constant GAISLER_GRPWRX : amba_device_type := 16#08E#;
constant GAISLER_GPREGBANK : amba_device_type := 16#08F#;
constant GAISLER_MIG_SERIES7 : amba_device_type := 16#090#;
constant GAISLER_GRSPW2_SIST : amba_device_type := 16#091#;
constant GAISLER_SGMII : amba_device_type := 16#092#;
constant GAISLER_RGMII : amba_device_type := 16#093#;
constant GAISLER_IRQGEN : amba_device_type := 16#094#;
constant GAISLER_GRDMAC : amba_device_type := 16#095#;
constant GAISLER_AHB2AVLA : amba_device_type := 16#096#;
constant GAISLER_SPWTDP : amba_device_type := 16#097#;
-- Sun Microsystems
constant SUN_T1 : amba_device_type := 16#001#;
constant SUN_S1 : amba_device_type := 16#011#;
-- Caltech
constant CAL_DDRCTRL : amba_device_type := 16#188#;
-- European Space Agency device ids
constant ESA_LEON2 : amba_device_type := 16#002#;
constant ESA_LEON2APB : amba_device_type := 16#003#;
constant ESA_IRQ : amba_device_type := 16#005#;
constant ESA_TIMER : amba_device_type := 16#006#;
constant ESA_UART : amba_device_type := 16#007#;
constant ESA_CFG : amba_device_type := 16#008#;
constant ESA_IO : amba_device_type := 16#009#;
constant ESA_MCTRL : amba_device_type := 16#00F#;
constant ESA_PCIARB : amba_device_type := 16#010#;
constant ESA_HURRICANE : amba_device_type := 16#011#;
constant ESA_SPW_RMAP : amba_device_type := 16#012#;
constant ESA_AHBUART : amba_device_type := 16#013#;
constant ESA_SPWA : amba_device_type := 16#014#;
constant ESA_BOSCHCAN : amba_device_type := 16#015#;
constant ESA_IRQ2 : amba_device_type := 16#016#;
constant ESA_AHBSTAT : amba_device_type := 16#017#;
constant ESA_WPROT : amba_device_type := 16#018#;
constant ESA_WPROT2 : amba_device_type := 16#019#;
constant ESA_PDEC3AMBA : amba_device_type := 16#020#;
constant ESA_PTME3AMBA : amba_device_type := 16#021#;
-- OpenChip IDs
constant OPENCHIP_APBGPIO : amba_device_type := 16#001#;
constant OPENCHIP_APBI2C : amba_device_type := 16#002#;
constant OPENCHIP_APBSPI : amba_device_type := 16#003#;
constant OPENCHIP_APBCHARLCD : amba_device_type := 16#004#;
constant OPENCHIP_APBPWM : amba_device_type := 16#005#;
constant OPENCHIP_APBPS2 : amba_device_type := 16#006#;
constant OPENCHIP_APBMMCSD : amba_device_type := 16#007#;
constant OPENCHIP_APBNAND : amba_device_type := 16#008#;
constant OPENCHIP_APBLPC : amba_device_type := 16#009#;
constant OPENCHIP_APBCF : amba_device_type := 16#00A#;
constant OPENCHIP_APBSYSACE : amba_device_type := 16#00B#;
constant OPENCHIP_APB1WIRE : amba_device_type := 16#00C#;
constant OPENCHIP_APBJTAG : amba_device_type := 16#00D#;
constant OPENCHIP_APBSUI : amba_device_type := 16#00E#;
-- Gleichmann's device ids
constant GLEICHMANN_CUSTOM : amba_device_type := 16#001#;
constant GLEICHMANN_GEOLCD01 : amba_device_type := 16#002#;
constant GLEICHMANN_DAC : amba_device_type := 16#003#;
constant GLEICHMANN_HPI : amba_device_type := 16#004#;
constant GLEICHMANN_SPI : amba_device_type := 16#005#;
constant GLEICHMANN_HIFC : amba_device_type := 16#006#;
constant GLEICHMANN_ADCDAC : amba_device_type := 16#007#;
constant GLEICHMANN_SPIOC : amba_device_type := 16#008#;
constant GLEICHMANN_AC97 : amba_device_type := 16#009#;
-- DTU device ids
constant DTU_IV : amba_device_type := 16#001#;
constant DTU_RBMMTRANS : amba_device_type := 16#002#;
constant DTU_FTMCTRL : amba_device_type := 16#054#;
-- BSC device ids
constant BSC_CORE1 : amba_device_type := 16#001#;
constant BSC_CORE2 : amba_device_type := 16#002#;
-- Orbita device ids
constant ORBITA_1553B : amba_device_type := 16#001#;
constant ORBITA_429 : amba_device_type := 16#002#;
constant ORBITA_SPI : amba_device_type := 16#003#;
constant ORBITA_I2C : amba_device_type := 16#004#;
constant ORBITA_SMARTCARD : amba_device_type := 16#064#;
constant ORBITA_SDCARD : amba_device_type := 16#065#;
constant ORBITA_UART16550 : amba_device_type := 16#066#;
constant ORBITA_CRYPTO : amba_device_type := 16#067#;
constant ORBITA_SYSIF : amba_device_type := 16#068#;
constant ORBITA_PIO : amba_device_type := 16#069#;
constant ORBITA_RTC : amba_device_type := 16#0C8#;
constant ORBITA_COLORLCD : amba_device_type := 16#12C#;
constant ORBITA_PCI : amba_device_type := 16#190#;
constant ORBITA_DSP : amba_device_type := 16#1F4#;
constant ORBITA_USBHOST : amba_device_type := 16#258#;
constant ORBITA_USBDEV : amba_device_type := 16#2BC#;
-- Actel device ids
constant ACTEL_COREMP7 : amba_device_type := 16#001#;
-- NASA device ids
constant NASA_EP32 : amba_device_type := 16#001#;
-- AppleCore device ids
constant APPLECORE_UTLEON3 : amba_device_type := 16#001#;
constant APPLECORE_UTLEON3DSU : amba_device_type := 16#002#;
constant APPLECORE_APBPERFCNT : amba_device_type := 16#003#;
-- Contribution library IDs
constant CONTRIB_CORE1 : amba_device_type := 16#001#;
constant CONTRIB_CORE2 : amba_device_type := 16#002#;
-- grlib system device ids
subtype system_device_type is integer range 0 to 16#ffff#;
constant LEON3_NEXTREME1 : system_device_type := 16#0101#;
constant LEON4_NEXTREME1 : system_device_type := 16#0102#;
constant LEON3_ACT_FUSION : system_device_type := 16#0105#;
constant LEON3_RTAX_CID6RSNETH: system_device_type := 16#0196#;
constant LEON3_RTAX_KARI : system_device_type := 16#0197#;
constant LEON3_RTAX_IAA : system_device_type := 16#0198#;
constant LEON3_RTAX_TECNOBIT : system_device_type := 16#0199#;
constant LEON3_RTAX_TDP8 : system_device_type := 16#0200#;
constant LEON3_RTAX_CID1 : system_device_type := 16#0201#;
constant LEON3_RTAX_CID2 : system_device_type := 16#0202#;
constant LEON3_RTAX_CID3 : system_device_type := 16#0203#;
constant LEON3_RTAX_CID4 : system_device_type := 16#0204#;
constant LEON3_RTAX_CID5 : system_device_type := 16#0205#;
constant LEON3_RTAX_CID6 : system_device_type := 16#0206#;
constant LEON3_RTAX_CID7 : system_device_type := 16#0207#;
constant LEON3_RTAX_CID8 : system_device_type := 16#0208#;
constant LEON3_IHP25RH1 : system_device_type := 16#0251#;
constant LEON3_PROXIMA : system_device_type := 16#0252#;
constant NGMP_PROTOTYPE : system_device_type := 16#0281#;
constant NGMP_PROTOTYPE2 : system_device_type := 16#0282#;
constant ALTERA_DE2 : system_device_type := 16#0302#;
constant ALTERA_DE4 : system_device_type := 16#0303#;
constant XILINX_ML401 : system_device_type := 16#0401#;
constant LEON3FT_GRXC4V : system_device_type := 16#0453#;
constant XILINX_ML501 : system_device_type := 16#0501#;
constant XILINX_ML505 : system_device_type := 16#0505#;
constant XILINX_ML506 : system_device_type := 16#0506#;
constant XILINX_ML507 : system_device_type := 16#0507#;
constant XILINX_ML509 : system_device_type := 16#0509#;
constant XILINX_ML510 : system_device_type := 16#0510#;
constant XILINX_SP601 : system_device_type := 16#0601#;
constant XILINX_ML605 : system_device_type := 16#0605#;
constant ORBITA_1 : system_device_type := 16#0631#;
constant ORBITA_OBTMP : system_device_type := 16#0632#;
constant AEROFLEX_UT699 : system_device_type := 16#0699#;
constant AEROFLEX_UT700 : system_device_type := 16#0700#;
constant GAISLER_GR701 : system_device_type := 16#0701#;
constant GAISLER_GR702 : system_device_type := 16#0702#;
constant GAISLER_GR703 : system_device_type := 16#0703#;
constant GAISLER_DARE1 : system_device_type := 16#0704#;
constant GAISLER_GR712RC : system_device_type := 16#0712#;
constant GAISLER_SPWRTRASIC : system_device_type := 16#0718#;
constant AEROFLEX_UT840 : system_device_type := 16#0840#;
-- pragma translate_off
constant GAISLER_DESC : vendor_description := "Aeroflex Gaisler ";
constant gaisler_device_table : device_table_type := (
GAISLER_LEON2DSU => "LEON2 Debug Support Unit ",
GAISLER_LEON3 => "LEON3 SPARC V8 Processor ",
GAISLER_LEON3DSU => "LEON3 Debug Support Unit ",
GAISLER_ETHAHB => "OC ethernet AHB interface ",
GAISLER_AHBRAM => "Single-port AHB SRAM module ",
GAISLER_AHBDPRAM => "Dual-port AHB SRAM module ",
GAISLER_APBMST => "AHB/APB Bridge ",
GAISLER_AHBUART => "AHB Debug UART ",
GAISLER_SRCTRL => "Simple SRAM Controller ",
GAISLER_SDCTRL => "PC133 SDRAM Controller ",
GAISLER_SSRCTRL => "Synchronous SRAM Controller ",
GAISLER_APBUART => "Generic UART ",
GAISLER_IRQMP => "Multi-processor Interrupt Ctrl.",
GAISLER_GPTIMER => "Modular Timer Unit ",
GAISLER_PCITRG => "Simple 32-bit PCI Target ",
GAISLER_PCISBRG => "Simple 32-bit PCI Bridge ",
GAISLER_PCIFBRG => "Fast 32-bit PCI Bridge ",
GAISLER_PCITRACE => "32-bit PCI Trace Buffer ",
GAISLER_DMACTRL => "PCI/AHB DMA controller ",
GAISLER_AHBTRACE => "AMBA Trace Buffer ",
GAISLER_DSUCTRL => "DSU/ETH controller ",
GAISLER_GRTM => "CCSDS Telemetry Encoder ",
GAISLER_GRTC => "CCSDS Telecommand Decoder ",
GAISLER_GRPW => "PacketWire to AMBA AHB I/F ",
GAISLER_GRCTM => "CCSDS Time Manager ",
GAISLER_GRHCAN => "ESA HurriCANe CAN with DMA ",
GAISLER_GRFIFO => "FIFO Controller ",
GAISLER_GRADCDAC => "ADC / DAC Interface ",
GAISLER_GRPULSE => "General Purpose I/O with Pulses",
GAISLER_GRTIMER => "Timer Unit with Latches ",
GAISLER_AHB2PP => "AMBA AHB to Packet Parallel I/F",
GAISLER_GRVERSION => "Version and Revision Register ",
GAISLER_APB2PW => "PacketWire Transmit Interface ",
GAISLER_PW2APB => "PacketWire Receive Interface ",
GAISLER_GRCAN => "CAN Controller with DMA ",
GAISLER_AHBMST_EM => "AMBA Master Emulator ",
GAISLER_AHBSLV_EM => "AMBA Slave Emulator ",
GAISLER_CANAHB => "OC CAN AHB interface ",
GAISLER_GPIO => "General Purpose I/O port ",
GAISLER_AHBROM => "Generic AHB ROM ",
GAISLER_AHB2AHB => "AHB-to-AHB Bridge ",
GAISLER_AHBDMA => "Simple AHB DMA controller ",
GAISLER_NUHOSP3 => "Nuhorizons Spartan3 IO I/F ",
GAISLER_CLKGATE => "Clock gating unit ",
GAISLER_FTAHBRAM => "Generic FT AHB SRAM module ",
GAISLER_FTSRCTRL => "Simple FT SRAM Controller ",
GAISLER_LEON3FT => "LEON3-FT SPARC V8 Processor ",
GAISLER_FTMCTRL => "Memory controller with EDAC ",
GAISLER_FTSDCTRL => "FT PC133 SDRAM Controller ",
GAISLER_FTSRCTRL8 => "FT 8-bit SRAM/16-bit IO Ctrl ",
GAISLER_FTSDCTRL64=> "64-bit FT SDRAM Controller ",
GAISLER_AHBSTAT => "AHB Status Register ",
GAISLER_AHBJTAG => "JTAG Debug Link ",
GAISLER_ETHMAC => "GR Ethernet MAC ",
GAISLER_SWNODE => "SpaceWire Node Interface ",
GAISLER_SPW => "SpaceWire Serial Link ",
GAISLER_VGACTRL => "VGA controller ",
GAISLER_APBPS2 => "PS2 interface ",
GAISLER_LOGAN => "On chip Logic Analyzer ",
GAISLER_SVGACTRL => "SVGA frame buffer ",
GAISLER_T1AHB => "Niagara T1 PCX/AHB bridge ",
GAISLER_B1553BC => "AMBA Wrapper for Core1553BBC ",
GAISLER_B1553RT => "AMBA Wrapper for Core1553BRT ",
GAISLER_B1553BRM => "AMBA Wrapper for Core1553BRM ",
GAISLER_SATCAN => "SatCAN controller ",
GAISLER_CANMUX => "CAN Bus multiplexer ",
GAISLER_GRTMRX => "CCSDS Telemetry Receiver ",
GAISLER_GRTCTX => "CCSDS Telecommand Transmitter ",
GAISLER_GRTMDESC => "CCSDS Telemetry Descriptor ",
GAISLER_GRTMVC => "CCSDS Telemetry VC Generator ",
GAISLER_GRTMPAHB => "CCSDS Telemetry VC AHB Input ",
GAISLER_GEFFE => "Geffe Generator ",
GAISLER_SPWCUC => "CCSDS CUC / SpaceWire I/F ",
GAISLER_GPREG => "General Purpose Register ",
GAISLER_AES => "Advanced Encryption Standard ",
GAISLER_AESDMA => "AES 256 DMA ",
GAISLER_GRPCI2 => "GRPCI2 PCI/AHB bridge ",
GAISLER_GRPCI2_DMA=> "GRPCI2 DMA interface ",
GAISLER_GRPCI2_TB => "GRPCI2 Trace buffer ",
GAISLER_MMA => "Memory Mapped AMBA ",
GAISLER_ECC => "Elliptic Curve Cryptography ",
GAISLER_PCIF => "AMBA Wrapper for CorePCIF ",
GAISLER_USBDC => "GR USB 2.0 Device Controller ",
GAISLER_USB_DCL => "USB Debug Communication Link ",
GAISLER_DDRMP => "Multi-port DDR controller ",
GAISLER_ATACTRL => "ATA controller ",
GAISLER_DDRSP => "Single-port DDR266 controller ",
GAISLER_EHCI => "USB Enhanced Host Controller ",
GAISLER_UHCI => "USB Universal Host Controller ",
GAISLER_I2CMST => "AMBA Wrapper for OC I2C-master ",
GAISLER_I2CSLV => "I2C Slave ",
GAISLER_U16550 => "Simple 16550 UART ",
GAISLER_SPICTRL => "SPI Controller ",
GAISLER_DDR2SP => "Single-port DDR2 controller ",
GAISLER_GRTESTMOD => "Test report module ",
GAISLER_CLKMOD => "CPU Clock Switching Ctrl module",
GAISLER_SLINK => "SLINK Master ",
GAISLER_HAPSTRAK => "HAPS HapsTrak I/O Port ",
GAISLER_TEST_1X2 => "HAPS TEST_1x2 interface ",
GAISLER_WILD2AHB => "WildCard CardBus interface ",
GAISLER_BIO1 => "Basic I/O board BIO1 ",
GAISLER_ASCS => "ASCS Master ",
GAISLER_SPW2 => "GRSPW2 SpaceWire Serial Link ",
GAISLER_IPMVBCTRL => "IPM-bus/MVBC memory controller ",
GAISLER_SPIMCTRL => "SPI Memory Controller ",
GAISLER_L4STAT => "LEON4 Statistics Unit ",
GAISLER_LEON4 => "LEON4 SPARC V8 Processor ",
GAISLER_LEON4DSU => "LEON4 Debug Support Unit ",
GAISLER_PWM => "PWM generator ",
GAISLER_L2CACHE => "L2-Cache Controller ",
GAISLER_SDCTRL64 => "64-bit PC133 SDRAM Controller ",
GAISLER_MP7WRAP => "CoreMP7 wrapper ",
GAISLER_GRSYSMON => "AMBA wrapper for System Monitor",
GAISLER_GRACECTRL => "System ACE I/F Controller ",
GAISLER_ATAHBSLV => "AMBA Test Framework AHB Slave ",
GAISLER_ATAHBMST => "AMBA Test Framework AHB Master ",
GAISLER_ATAPBSLV => "AMBA Test Framework APB Slave ",
GAISLER_MIGDDR2 => "Xilinx MIG DDR2 Controller ",
GAISLER_LCDCTRL => "LCD Controller ",
GAISLER_SWITCHOVER=> "Switchover Logic ",
GAISLER_FIFOUART => "UART with large FIFO ",
GAISLER_MUXCTRL => "Analogue multiplexer control ",
GAISLER_GR1553B => "MIL-STD-1553B Interface ",
GAISLER_1553TST => "MIL-STD-1553B Test Device ",
GAISLER_MEMSCRUB => "AHB Memory Scrubber ",
GAISLER_GRIOMMU => "IO Memory Management Unit ",
GAISLER_SPW2_DMA => "GRSPW Router DMA interface ",
GAISLER_SPWROUTER => "GRSPW Router ",
GAISLER_EDCLMST => "EDCL master interface ",
GAISLER_GRPWTX => "PacketWire Transmitter with DMA",
GAISLER_GRPWRX => "PacketWire Receiver with DMA ",
GAISLER_GRIOMMU2 => "IOMMU secondary master i/f ",
GAISLER_I2C2AHB => "I2C to AHB Bridge ",
GAISLER_NANDFCTRL => "NAND Flash Controller ",
GAISLER_N2PLLCTRL => "N2X PLL Dynamic Config. i/f ",
GAISLER_N2DLLCTRL => "N2X DLL Dynamic Config. i/f ",
GAISLER_GPREGBANK => "General Purpose Register Bank ",
GAISLER_SPI2AHB => "SPI to AHB Bridge ",
GAISLER_DDRSDMUX => "Muxed FT DDR/SDRAM controller ",
GAISLER_AHBFROM => "Flash ROM Memory ",
GAISLER_PCIEXP => "Xilinx PCI EXPRESS Wrapper ",
GAISLER_MIG_SERIES7 => "Xilinx MIG DDR3 Controller ",
GAISLER_GRSPW2_SIST => "GRSPW Router SIST ",
GAISLER_SGMII => "XILINX SGMII Interface ",
GAISLER_RGMII => "Gaisler RGMII Interface ",
GAISLER_IRQGEN => "Interrupt generator ",
GAISLER_GRDMAC => "DMA Controller with APB bridge ",
GAISLER_AHB2AVLA => "Avalon-MM memory controller ",
GAISLER_SPWTDP => "CCSDS TDP / SpaceWire I/F ",
others => "Unknown Device ");
constant gaisler_lib : vendor_library_type := (
vendorid => VENDOR_GAISLER,
vendordesc => GAISLER_DESC,
device_table => gaisler_device_table
);
constant ESA_DESC : vendor_description := "European Space Agency ";
constant esa_device_table : device_table_type := (
ESA_LEON2 => "LEON2 SPARC V8 Processor ",
ESA_LEON2APB => "LEON2 Peripheral Bus ",
ESA_IRQ => "LEON2 Interrupt Controller ",
ESA_TIMER => "LEON2 Timer ",
ESA_UART => "LEON2 UART ",
ESA_CFG => "LEON2 Configuration Register ",
ESA_IO => "LEON2 Input/Output ",
ESA_MCTRL => "LEON2 Memory Controller ",
ESA_PCIARB => "PCI Arbiter ",
ESA_HURRICANE => "HurriCANe/HurryAMBA CAN Ctrl ",
ESA_SPW_RMAP => "UoD/Saab SpaceWire/RMAP link ",
ESA_AHBUART => "LEON2 AHB Debug UART ",
ESA_SPWA => "ESA/ASTRIUM SpaceWire link ",
ESA_BOSCHCAN => "SSC/BOSCH CAN Ctrl ",
ESA_IRQ2 => "LEON2 Secondary Irq Controller ",
ESA_AHBSTAT => "LEON2 AHB Status Register ",
ESA_WPROT => "LEON2 Write Protection ",
ESA_WPROT2 => "LEON2 Extended Write Protection",
ESA_PDEC3AMBA => "ESA CCSDS PDEC3AMBA TC Decoder ",
ESA_PTME3AMBA => "ESA CCSDS PTME3AMBA TM Encoder ",
others => "Unknown Device ");
constant esa_lib : vendor_library_type := (
vendorid => VENDOR_ESA,
vendordesc => ESA_DESC,
device_table => esa_device_table
);
constant OPENCHIP_DESC : vendor_description := "OpenChip ";
constant openchip_device_table : device_table_type := (
OPENCHIP_APBGPIO => "APB General Purpose IO ",
OPENCHIP_APBI2C => "APB I2C Interface ",
OPENCHIP_APBSPI => "APB SPI Interface ",
OPENCHIP_APBCHARLCD => "APB Character LCD ",
OPENCHIP_APBPWM => "APB PWM ",
OPENCHIP_APBPS2 => "APB PS/2 Interface ",
OPENCHIP_APBMMCSD => "APB MMC/SD Card Interface ",
OPENCHIP_APBNAND => "APB NAND(SmartMedia) Interface ",
OPENCHIP_APBLPC => "APB LPC Interface ",
OPENCHIP_APBCF => "APB CompactFlash (IDE) ",
OPENCHIP_APBSYSACE => "APB SystemACE Interface ",
OPENCHIP_APB1WIRE => "APB 1-Wire Interface ",
OPENCHIP_APBJTAG => "APB JTAG TAP Master ",
OPENCHIP_APBSUI => "APB Simple User Interface ",
others => "Unknown Device ");
constant openchip_lib : vendor_library_type := (
vendorid => VENDOR_OPENCHIP,
vendordesc => OPENCHIP_DESC,
device_table => openchip_device_table
);
constant GLEICHMANN_DESC : vendor_description := "Gleichmann Electronics ";
constant gleichmann_device_table : device_table_type := (
GLEICHMANN_CUSTOM => "Custom device ",
GLEICHMANN_GEOLCD01 => "GEOLCD01 graphics system ",
GLEICHMANN_DAC => "Sigma delta DAC ",
GLEICHMANN_HPI => "AHB-to-HPI bridge ",
GLEICHMANN_SPI => "SPI master ",
GLEICHMANN_HIFC => "Human interface controller ",
GLEICHMANN_ADCDAC => "Sigma delta ADC/DAC ",
GLEICHMANN_SPIOC => "SPI master for SDCard IF ",
GLEICHMANN_AC97 => "AC97 Controller ",
others => "Unknown Device ");
constant gleichmann_lib : vendor_library_type := (
vendorid => VENDOR_GLEICHMANN,
vendordesc => GLEICHMANN_DESC,
device_table => gleichmann_device_table
);
constant CONTRIB_DESC : vendor_description := "Various contributions ";
constant contrib_device_table : device_table_type := (
CONTRIB_CORE1 => "Contributed core 1 ",
CONTRIB_CORE2 => "Contributed core 2 ",
others => "Unknown Device ");
constant contrib_lib : vendor_library_type := (
vendorid => VENDOR_CONTRIB,
vendordesc => CONTRIB_DESC,
device_table => contrib_device_table
);
constant MENTA_DESC : vendor_description := "Menta ";
constant menta_device_table : device_table_type := (
others => "Unknown Device ");
constant menta_lib : vendor_library_type := (
vendorid => VENDOR_MENTA,
vendordesc => MENTA_DESC,
device_table => menta_device_table
);
constant SUN_DESC : vendor_description := "Sun Microsystems ";
constant sun_device_table : device_table_type := (
SUN_T1 => "Niagara T1 SPARC V9 Processor ",
SUN_S1 => "Niagara S1 SPARC V9 Processor ",
others => "Unknown Device ");
constant sun_lib : vendor_library_type := (
vendorid => VENDOR_SUN,
vendordesc => SUN_DESC,
device_table => sun_device_table
);
constant OPENCORES_DESC : vendor_description := "OpenCores ";
constant opencores_device_table : device_table_type := (
others => "Unknown Device ");
constant opencores_lib : vendor_library_type := (
vendorid => VENDOR_OPENCORES,
vendordesc => OPENCORES_DESC,
device_table => opencores_device_table
);
constant CETON_DESC : vendor_description := "Ceton Corporation ";
constant ceton_device_table : device_table_type := (
others => "Unknown Device ");
constant ceton_lib : vendor_library_type := (
vendorid => VENDOR_CETON,
vendordesc => CETON_DESC,
device_table => ceton_device_table
);
constant SYNOPSYS_DESC : vendor_description := "Synopsys Inc. ";
constant synopsys_device_table : device_table_type := (
others => "Unknown Device ");
constant synopsys_lib : vendor_library_type := (
vendorid => VENDOR_SYNOPSYS,
vendordesc => SYNOPSYS_DESC,
device_table => synopsys_device_table
);
constant EMBEDDIT_DESC : vendor_description := "Embedd.it ";
constant embeddit_device_table : device_table_type := (
others => "Unknown Device ");
constant embeddit_lib : vendor_library_type := (
vendorid => VENDOR_EMBEDDIT,
vendordesc => EMBEDDIT_DESC,
device_table => embeddit_device_table
);
constant dlr_device_table : device_table_type := (
others => "Unknown Device ");
constant DLR_DESC : vendor_description := "German Aerospace Center ";
constant dlr_lib : vendor_library_type := (
vendorid => VENDOR_DLR,
vendordesc => DLR_DESC,
device_table => dlr_device_table
);
constant eonic_device_table : device_table_type := (
others => "Unknown Device ");
constant EONIC_DESC : vendor_description := "Eonic BV ";
constant eonic_lib : vendor_library_type := (
vendorid => VENDOR_EONIC,
vendordesc => EONIC_DESC,
device_table => eonic_device_table
);
constant telecompt_device_table : device_table_type := (
others => "Unknown Device ");
constant TELECOMPT_DESC : vendor_description := "Telecom ParisTech ";
constant telecompt_lib : vendor_library_type := (
vendorid => VENDOR_TELECOMPT,
vendordesc => TELECOMPT_DESC,
device_table => telecompt_device_table
);
constant radionor_device_table : device_table_type := (
others => "Unknown Device ");
constant RADIONOR_DESC : vendor_description := "Radionor Communications ";
constant radionor_lib : vendor_library_type := (
vendorid => VENDOR_RADIONOR,
vendordesc => RADIONOR_DESC,
device_table => radionor_device_table
);
constant bsc_device_table : device_table_type := (
BSC_CORE1 => "Core 1 ",
BSC_CORE2 => "Core 2 ",
others => "Unknown Device ");
constant BSC_DESC : vendor_description := "BSC ";
constant bsc_lib : vendor_library_type := (
vendorid => VENDOR_BSC,
vendordesc => BSC_DESC,
device_table => bsc_device_table
);
constant dtu_device_table : device_table_type := (
DTU_IV => "Instrument Virtualizer ",
DTU_RBMMTRANS => "RB/MM Transfer ",
DTU_FTMCTRL => "Memory controller with 8CS ",
others => "Unknown Device ");
constant DTU_DESC : vendor_description := "DTU Space ";
constant dtu_lib : vendor_library_type := (
vendorid => VENDOR_DTU,
vendordesc => DTU_DESC,
device_table => dtu_device_table
);
constant orbita_device_table : device_table_type := (
ORBITA_1553B => "MIL-STD-1553B Controller ",
ORBITA_429 => "429 Interface ",
ORBITA_SPI => "SPI Interface ",
ORBITA_I2C => "I2C Interface ",
ORBITA_SMARTCARD => "Smart Card Reader ",
ORBITA_SDCARD => "SD Card Reader ",
ORBITA_UART16550 => "16550 UART ",
ORBITA_CRYPTO => "Crypto Engine ",
ORBITA_SYSIF => "System Interface ",
ORBITA_PIO => "Programmable IO module ",
ORBITA_RTC => "Real-Time Clock ",
ORBITA_COLORLCD => "Color LCD Controller ",
ORBITA_PCI => "PCI Module ",
ORBITA_DSP => "DPS Co-Processor ",
ORBITA_USBHOST => "USB Host ",
ORBITA_USBDEV => "USB Device ",
others => "Unknown Device ");
constant ORBITA_DESC : vendor_description := "Orbita ";
constant orbita_lib : vendor_library_type := (
vendorid => VENDOR_ORBITA,
vendordesc => ORBITA_DESC,
device_table => orbita_device_table
);
constant ACTEL_DESC : vendor_description := "Actel Corporation ";
constant actel_device_table : device_table_type := (
ACTEL_COREMP7 => "CoreMP7 Processor ",
others => "Unknown Device ");
constant actel_lib : vendor_library_type := (
vendorid => VENDOR_ACTEL,
vendordesc => ACTEL_DESC,
device_table => actel_device_table
);
constant NASA_DESC : vendor_description := "NASA ";
constant nasa_device_table : device_table_type := (
NASA_EP32 => "EP32 Forth processor ",
others => "Unknown Device ");
constant nasa_lib : vendor_library_type := (
vendorid => VENDOR_NASA,
vendordesc => NASA_DESC,
device_table => nasa_device_table
);
constant S3_DESC : vendor_description := "S3 Group ";
constant s3_device_table : device_table_type := (
others => "Unknown Device ");
constant s3_lib : vendor_library_type := (
vendorid => VENDOR_S3,
vendordesc => S3_DESC,
device_table => s3_device_table
);
constant APPLECORE_DESC : vendor_description := "AppleCore ";
constant applecore_device_table : device_table_type := (
APPLECORE_UTLEON3 => "AppleCore uT-LEON3 Processor ",
APPLECORE_UTLEON3DSU => "AppleCore uT-LEON3 DSU ",
others => "Unknown Device ");
constant applecore_lib : vendor_library_type := (
vendorid => VENDOR_APPLECORE,
vendordesc => APPLECORE_DESC,
device_table => applecore_device_table
);
constant C3E_DESC : vendor_description := "TU Braunschweig C3E ";
constant c3e_device_table : device_table_type := (
others => "Unknown Device ");
constant c3e_lib : vendor_library_type := (
vendorid => VENDOR_C3E,
vendordesc => C3E_DESC,
device_table => c3e_device_table
);
constant UNKNOWN_DESC : vendor_description := "Unknown vendor ";
constant unknown_device_table : device_table_type := (
others => "Unknown Device ");
constant unknown_lib : vendor_library_type := (
vendorid => 0,
vendordesc => UNKNOWN_DESC,
device_table => unknown_device_table
);
constant iptable : device_array := (
VENDOR_GAISLER => gaisler_lib,
VENDOR_ESA => esa_lib,
VENDOR_OPENCHIP => openchip_lib,
VENDOR_OPENCORES => opencores_lib,
VENDOR_CONTRIB => contrib_lib,
VENDOR_DLR => dlr_lib,
VENDOR_EONIC => eonic_lib,
VENDOR_TELECOMPT => telecompt_lib,
VENDOR_GLEICHMANN => gleichmann_lib,
VENDOR_MENTA => menta_lib,
VENDOR_EMBEDDIT => embeddit_lib,
VENDOR_SUN => sun_lib,
VENDOR_RADIONOR => radionor_lib,
VENDOR_ORBITA => orbita_lib,
VENDOR_SYNOPSYS => synopsys_lib,
VENDOR_CETON => ceton_lib,
VENDOR_ACTEL => actel_lib,
VENDOR_NASA => nasa_lib,
VENDOR_S3 => s3_lib,
others => unknown_lib);
type system_table_type is array (0 to 4095) of device_description;
constant system_table : system_table_type := (
LEON3_NEXTREME1 => "LEON3 eASIC Nextreme controller",
LEON4_NEXTREME1 => "LEON4 eASIC Nextreme SoC ",
LEON3_ACT_FUSION => "LEON3 Actel Fusion Dev. board ",
LEON3_RTAX_CID2 => "LEON3FT RTAX Configuration 2 ",
LEON3_RTAX_CID5 => "LEON3FT RTAX Configuration 5 ",
LEON3_RTAX_CID6 => "LEON3FT RTAX Configuration 6 ",
LEON3_RTAX_CID7 => "LEON3FT RTAX Configuration 7 ",
LEON3_RTAX_CID8 => "LEON3FT RTAX Configuration 8 ",
LEON3_PROXIMA => "LEON3 PROXIMA FPGA design ",
ALTERA_DE2 => "Altera DE2 Development board ",
ALTERA_DE4 => "TerASIC DE4 Development board ",
XILINX_ML401 => "Xilinx ML401 Development board ",
XILINX_ML501 => "Xilinx ML501 Development board ",
XILINX_ML505 => "Xilinx ML505 Development board ",
XILINX_ML506 => "Xilinx ML506 Development board ",
XILINX_ML507 => "Xilinx ML507 Development board ",
XILINX_ML509 => "Xilinx ML509 Development board ",
XILINX_ML510 => "Xilinx ML510 Development board ",
XILINX_SP601 => "Xilinx SP601 Development board ",
XILINX_ML605 => "Xilinx ML605 Development board ",
AEROFLEX_UT699 => "Aeroflex UT699 Rad-Hard CPU ",
AEROFLEX_UT700 => "Aeroflex UT700 Rad-Hard CPU ",
GAISLER_DARE1 => "Gaisler DARE1 Rad-Hard CPU ",
GAISLER_GR712RC => "Gaisler GR712RC Rad-Hard CPU ",
NGMP_PROTOTYPE => "NGMP Prototype System-on-Chip ",
NGMP_PROTOTYPE2 => "NGMP Prototype System-on-Chip ",
ORBITA_OBTMP => "Orbita LEON4 prototype system ",
GAISLER_SPWRTRASIC => "Gaisler SpaceWire Router ASIC ",
others => "Unknown system ");
-- pragma translate_on
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2487.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p02n01i02487ent IS
END c07s03b03x00p02n01i02487ent;
ARCHITECTURE c07s03b03x00p02n01i02487arch OF c07s03b03x00p02n01i02487ent IS
BEGIN
TESTING: PROCESS
function typeconv (a1 : real) return integer is
begin
return 1;
end;
function func1 (a2 : integer) return integer is
begin
return 5;
end func1;
variable x: real := 1.2;
variable y: integer;
BEGIN
y := func1 (typeconv (x));
assert NOT(y=5)
report "***PASSED TEST: c07s03b03x00p02n01i02487"
severity NOTE;
assert (y=5)
report "***FAILED TEST: c07s03b03x00p02n01i02487 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p02n01i02487arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2487.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p02n01i02487ent IS
END c07s03b03x00p02n01i02487ent;
ARCHITECTURE c07s03b03x00p02n01i02487arch OF c07s03b03x00p02n01i02487ent IS
BEGIN
TESTING: PROCESS
function typeconv (a1 : real) return integer is
begin
return 1;
end;
function func1 (a2 : integer) return integer is
begin
return 5;
end func1;
variable x: real := 1.2;
variable y: integer;
BEGIN
y := func1 (typeconv (x));
assert NOT(y=5)
report "***PASSED TEST: c07s03b03x00p02n01i02487"
severity NOTE;
assert (y=5)
report "***FAILED TEST: c07s03b03x00p02n01i02487 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p02n01i02487arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2487.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p02n01i02487ent IS
END c07s03b03x00p02n01i02487ent;
ARCHITECTURE c07s03b03x00p02n01i02487arch OF c07s03b03x00p02n01i02487ent IS
BEGIN
TESTING: PROCESS
function typeconv (a1 : real) return integer is
begin
return 1;
end;
function func1 (a2 : integer) return integer is
begin
return 5;
end func1;
variable x: real := 1.2;
variable y: integer;
BEGIN
y := func1 (typeconv (x));
assert NOT(y=5)
report "***PASSED TEST: c07s03b03x00p02n01i02487"
severity NOTE;
assert (y=5)
report "***FAILED TEST: c07s03b03x00p02n01i02487 - The function call consists of a function name and (optionally) an actual parameter list enclosed with parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p02n01i02487arch;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fg_tb_pctrl.vhd
--
-- Description:
-- Used for protocol control on write and read interface stimulus and status generation
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.fg_tb_pkg.ALL;
ENTITY fg_tb_pctrl IS
GENERIC(
AXI_CHANNEL : STRING :="NONE";
C_APPLICATION_TYPE : INTEGER := 0;
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_WR_PNTR_WIDTH : INTEGER := 0;
C_RD_PNTR_WIDTH : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 2;
TB_SEED : INTEGER := 2
);
PORT(
RESET_WR : IN STD_LOGIC;
RESET_RD : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
FULL : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
ALMOST_FULL : IN STD_LOGIC;
ALMOST_EMPTY : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC_VECTOR(C_DIN_WIDTH-1 DOWNTO 0);
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
DOUT_CHK : IN STD_LOGIC;
PRC_WR_EN : OUT STD_LOGIC;
PRC_RD_EN : OUT STD_LOGIC;
RESET_EN : OUT STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE fg_pc_arch OF fg_tb_pctrl IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH,8);
CONSTANT D_WIDTH_DIFF : INTEGER := log2roundup(C_DIN_WIDTH/C_DOUT_WIDTH);
SIGNAL data_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL full_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL empty_chk_i : STD_LOGIC := if_then_else(C_CH_TYPE /= 2,'1','0');
SIGNAL status_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL status_d1_i : STD_LOGIC_VECTOR(4 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL rd_en_gen : STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_cntr : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL full_as_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL full_ds_timeout : STD_LOGIC_VECTOR(C_WR_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL rd_cntr : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH-2 DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_as_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0) := (OTHERS => '0');
SIGNAL empty_ds_timeout : STD_LOGIC_VECTOR(C_RD_PNTR_WIDTH DOWNTO 0):= (OTHERS => '0');
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL state : STD_LOGIC := '0';
SIGNAL wr_control : STD_LOGIC := '0';
SIGNAL rd_control : STD_LOGIC := '0';
SIGNAL stop_on_err : STD_LOGIC := '0';
SIGNAL sim_stop_cntr : STD_LOGIC_VECTOR(7 DOWNTO 0):= conv_std_logic_vector(if_then_else(C_CH_TYPE=2,64,TB_STOP_CNT),8);
SIGNAL sim_done_i : STD_LOGIC := '0';
SIGNAL rdw_gt_wrw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL wrw_gt_rdw : STD_LOGIC_VECTOR(D_WIDTH_DIFF-1 DOWNTO 0) := (OTHERS => '1');
SIGNAL rd_activ_cont : STD_LOGIC_VECTOR(25 downto 0):= (OTHERS => '0');
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL reset_en_i : STD_LOGIC := '0';
SIGNAL sim_done_d1 : STD_LOGIC := '0';
SIGNAL sim_done_wr1 : STD_LOGIC := '0';
SIGNAL sim_done_wr2 : STD_LOGIC := '0';
SIGNAL empty_d1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom1 : STD_LOGIC := '0';
SIGNAL state_d1 : STD_LOGIC := '0';
SIGNAL state_rd_dom1 : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '0';
SIGNAL rd_en_wr1 : STD_LOGIC := '0';
SIGNAL wr_en_d1 : STD_LOGIC := '0';
SIGNAL wr_en_rd1 : STD_LOGIC := '0';
SIGNAL full_chk_d1 : STD_LOGIC := '0';
SIGNAL full_chk_rd1 : STD_LOGIC := '0';
SIGNAL empty_wr_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom2 : STD_LOGIC := '0';
SIGNAL state_rd_dom3 : STD_LOGIC := '0';
SIGNAL rd_en_wr2 : STD_LOGIC := '0';
SIGNAL wr_en_rd2 : STD_LOGIC := '0';
SIGNAL full_chk_rd2 : STD_LOGIC := '0';
SIGNAL reset_en_d1 : STD_LOGIC := '0';
SIGNAL reset_en_rd1 : STD_LOGIC := '0';
SIGNAL reset_en_rd2 : STD_LOGIC := '0';
SIGNAL data_chk_wr_d1 : STD_LOGIC := '0';
SIGNAL data_chk_rd1 : STD_LOGIC := '0';
SIGNAL data_chk_rd2 : STD_LOGIC := '0';
SIGNAL post_rst_dly_wr : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
SIGNAL post_rst_dly_rd : STD_LOGIC_VECTOR(4 DOWNTO 0) := (OTHERS => '1');
BEGIN
status_i <= data_chk_i & full_chk_rd2 & empty_chk_i & '0' & '0';
STATUS <= status_d1_i & '0' & '0' & rd_activ_cont(rd_activ_cont'high);
prc_we_i <= wr_en_i WHEN sim_done_wr2 = '0' ELSE '0';
prc_re_i <= rd_en_i WHEN sim_done_i = '0' ELSE '0';
SIM_DONE <= sim_done_i;
rdw_gt_wrw <= (OTHERS => '1');
PROCESS(RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(prc_re_i = '1') THEN
rd_activ_cont <= rd_activ_cont + "1";
END IF;
END IF;
END PROCESS;
PROCESS(sim_done_i)
BEGIN
assert sim_done_i = '0'
report "Simulation Complete for:" & AXI_CHANNEL
severity note;
END PROCESS;
-----------------------------------------------------
-- SIM_DONE SIGNAL GENERATION
-----------------------------------------------------
PROCESS (RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
--sim_done_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF((OR_REDUCE(sim_stop_cntr) = '0' AND TB_STOP_CNT /= 0) OR stop_on_err = '1') THEN
sim_done_i <= '1';
END IF;
END IF;
END PROCESS;
-- TB Timeout/Stop
fifo_tb_stop_run:IF(TB_STOP_CNT /= 0) GENERATE
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0' AND state_rd_dom3 = '1') THEN
sim_stop_cntr <= sim_stop_cntr - "1";
END IF;
END IF;
END PROCESS;
END GENERATE fifo_tb_stop_run;
-- Stop when error found
PROCESS (RD_CLK)
BEGIN
IF (RD_CLK'event AND RD_CLK='1') THEN
IF(sim_done_i = '0') THEN
status_d1_i <= status_i OR status_d1_i;
END IF;
IF(FREEZEON_ERROR = 1 AND status_i /= "0") THEN
stop_on_err <= '1';
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-----------------------------------------------------
-- CHECKS FOR FIFO
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
post_rst_dly_rd <= (OTHERS => '1');
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
post_rst_dly_rd <= post_rst_dly_rd-post_rst_dly_rd(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
post_rst_dly_wr <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
post_rst_dly_wr <= post_rst_dly_wr-post_rst_dly_wr(4);
END IF;
END PROCESS;
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wrw_gt_rdw <= (OTHERS => '1');
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1') THEN
wrw_gt_rdw <= wrw_gt_rdw + '1';
END IF;
END IF;
END PROCESS;
-- FULL de-assert Counter
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_ds_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(rd_en_wr2 = '1' AND wr_en_i = '0' AND FULL = '1' AND AND_REDUCE(wrw_gt_rdw) = '1') THEN
full_ds_timeout <= full_ds_timeout + '1';
END IF;
ELSE
full_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- EMPTY deassert counter
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_ds_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state = '0') THEN
IF(wr_en_rd2 = '1' AND rd_en_i = '0' AND EMPTY = '1' AND AND_REDUCE(rdw_gt_wrw) = '1') THEN
empty_ds_timeout <= empty_ds_timeout + '1';
END IF;
ELSE
empty_ds_timeout <= (OTHERS => '0');
END IF;
END IF;
END PROCESS;
-- Full check signal generation
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
full_chk_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
full_chk_i <= '0';
ELSE
full_chk_i <= AND_REDUCE(full_as_timeout) OR
AND_REDUCE(full_ds_timeout);
END IF;
END IF;
END PROCESS;
-- Empty checks
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_chk_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(C_APPLICATION_TYPE = 1 AND (AXI_CHANNEL = "WACH" OR AXI_CHANNEL = "RACH" OR AXI_CHANNEL = "AXI4_Stream")) THEN
empty_chk_i <= '0';
ELSE
empty_chk_i <= AND_REDUCE(empty_as_timeout) OR
AND_REDUCE(empty_ds_timeout);
END IF;
END IF;
END PROCESS;
fifo_d_chk:IF(C_CH_TYPE /= 2) GENERATE
PRC_WR_EN <= prc_we_i AFTER 24 ns;
PRC_RD_EN <= prc_re_i AFTER 12 ns;
data_chk_i <= dout_chk;
END GENERATE fifo_d_chk;
-----------------------------------------------------
-----------------------------------------------------
-- SYNCHRONIZERS B/W WRITE AND READ DOMAINS
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
empty_wr_dom1 <= '1';
empty_wr_dom2 <= '1';
state_d1 <= '0';
wr_en_d1 <= '0';
rd_en_wr1 <= '0';
rd_en_wr2 <= '0';
full_chk_d1 <= '0';
reset_en_d1 <= '0';
sim_done_wr1 <= '0';
sim_done_wr2 <= '0';
ELSIF (WR_CLK'event AND WR_CLK='1') THEN
sim_done_wr1 <= sim_done_d1;
sim_done_wr2 <= sim_done_wr1;
reset_en_d1 <= reset_en_i;
state_d1 <= state;
empty_wr_dom1 <= empty_d1;
empty_wr_dom2 <= empty_wr_dom1;
wr_en_d1 <= wr_en_i;
rd_en_wr1 <= rd_en_d1;
rd_en_wr2 <= rd_en_wr1;
full_chk_d1 <= full_chk_i;
END IF;
END PROCESS;
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
empty_d1 <= '1';
state_rd_dom1 <= '0';
state_rd_dom2 <= '0';
state_rd_dom3 <= '0';
wr_en_rd1 <= '0';
wr_en_rd2 <= '0';
rd_en_d1 <= '0';
full_chk_rd1 <= '0';
full_chk_rd2 <= '0';
reset_en_rd1 <= '0';
reset_en_rd2 <= '0';
sim_done_d1 <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
sim_done_d1 <= sim_done_i;
reset_en_rd1 <= reset_en_d1;
reset_en_rd2 <= reset_en_rd1;
empty_d1 <= EMPTY;
rd_en_d1 <= rd_en_i;
state_rd_dom1 <= state_d1;
state_rd_dom2 <= state_rd_dom1;
state_rd_dom3 <= state_rd_dom2;
wr_en_rd1 <= wr_en_d1;
wr_en_rd2 <= wr_en_rd1;
full_chk_rd1 <= full_chk_d1;
full_chk_rd2 <= full_chk_rd1;
END IF;
END PROCESS;
RESET_EN <= reset_en_rd2;
data_fifo_en:IF(C_CH_TYPE /= 2) GENERATE
-----------------------------------------------------
-- WR_EN GENERATION
-----------------------------------------------------
gen_rand_wr_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+1
)
PORT MAP(
CLK => WR_CLK,
RESET => RESET_WR,
RANDOM_NUM => wr_en_gen,
ENABLE => '1'
);
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
wr_en_i <= wr_en_gen(0) AND wr_en_gen(7) AND wr_en_gen(2) AND wr_control;
ELSE
wr_en_i <= (wr_en_gen(3) OR wr_en_gen(4) OR wr_en_gen(2)) AND (NOT post_rst_dly_wr(4));
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- WR_EN CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
wr_cntr <= (OTHERS => '0');
wr_control <= '1';
full_as_timeout <= (OTHERS => '0');
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
IF(state = '1') THEN
IF(wr_en_i = '1') THEN
wr_cntr <= wr_cntr + "1";
END IF;
full_as_timeout <= (OTHERS => '0');
ELSE
wr_cntr <= (OTHERS => '0');
IF(rd_en_wr2 = '0') THEN
IF(wr_en_i = '1') THEN
full_as_timeout <= full_as_timeout + "1";
END IF;
ELSE
full_as_timeout <= (OTHERS => '0');
END IF;
END IF;
wr_control <= NOT wr_cntr(wr_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN GENERATION
-----------------------------------------------------
gen_rand_rd_en:fg_tb_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET_RD,
RANDOM_NUM => rd_en_gen,
ENABLE => '1'
);
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_en_i <= '0';
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
rd_en_i <= rd_en_gen(1) AND rd_en_gen(5) AND rd_en_gen(3) AND rd_control AND (NOT post_rst_dly_rd(4));
ELSE
rd_en_i <= rd_en_gen(0) OR rd_en_gen(6);
END IF;
END IF;
END PROCESS;
-----------------------------------------------------
-- RD_EN CONTROL
-----------------------------------------------------
PROCESS(RD_CLK,RESET_RD)
BEGIN
IF(RESET_RD = '1') THEN
rd_cntr <= (OTHERS => '0');
rd_control <= '1';
empty_as_timeout <= (OTHERS => '0');
ELSIF(RD_CLK'event AND RD_CLK='1') THEN
IF(state_rd_dom2 = '0') THEN
IF(rd_en_i = '1') THEN
rd_cntr <= rd_cntr + "1";
END IF;
empty_as_timeout <= (OTHERS => '0');
ELSE
rd_cntr <= (OTHERS => '0');
IF(wr_en_rd2 = '0') THEN
IF(rd_en_i = '1') THEN
empty_as_timeout <= empty_as_timeout + "1";
END IF;
ELSE
empty_as_timeout <= (OTHERS => '0');
END IF;
END IF;
rd_control <= NOT rd_cntr(rd_cntr'high);
END IF;
END PROCESS;
-----------------------------------------------------
-- STIMULUS CONTROL
-----------------------------------------------------
PROCESS(WR_CLK,RESET_WR)
BEGIN
IF(RESET_WR = '1') THEN
state <= '0';
reset_en_i <= '0';
ELSIF(WR_CLK'event AND WR_CLK='1') THEN
CASE state IS
WHEN '0' =>
IF(FULL = '1' AND empty_wr_dom2 = '0') THEN
state <= '1';
reset_en_i <= '0';
END IF;
WHEN '1' =>
IF(empty_wr_dom2 = '1' AND FULL = '0') THEN
state <= '0';
reset_en_i <= '1';
END IF;
WHEN OTHERS => state <= state;
END CASE;
END IF;
END PROCESS;
END GENERATE data_fifo_en;
END ARCHITECTURE;
|
-------------------------------------------------------------------------------
--
-- T410 ROM wrapper for lpm_rom.
--
-- $Id: t410_rom-lpm-c.vhd,v 1.1.1.1 2006-05-06 01:56:44 arniml Exp $
--
-- Copyright (c) 2006, Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-------------------------------------------------------------------------------
configuration t410_rom_struct_c0 of t410_rom is
for lpm
for rom_b: lpm_rom
use configuration work.lpm_rom_c0;
end for;
end for;
end t410_rom_struct_c0;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: i2c2ahb_gen
-- File: i2c2ahb_gen.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- Contact: [email protected]
-- Description: Generic wrapper for I2C-slave, see i2c2ahb.vhd
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library gaisler;
use gaisler.i2c.all;
entity i2c2ahb_gen is
generic (
ahbaddrh : integer := 0;
ahbaddrl : integer := 0;
ahbmaskh : integer := 0;
ahbmaskl : integer := 0;
-- I2C configuration
i2cslvaddr : integer range 0 to 127 := 0;
i2ccfgaddr : integer range 0 to 127 := 0;
oepol : integer range 0 to 1 := 0;
--
filter : integer range 2 to 512 := 2
);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- AHB master interface
ahbi_hgrant : in std_ulogic;
ahbi_hready : in std_ulogic;
ahbi_hresp : in std_logic_vector(1 downto 0);
ahbi_hrdata : in std_logic_vector(AHBDW-1 downto 0);
--ahbo : out ahb_mst_out_type;
ahbo_hbusreq : out std_ulogic;
ahbo_hlock : out std_ulogic;
ahbo_htrans : out std_logic_vector(1 downto 0);
ahbo_haddr : out std_logic_vector(31 downto 0);
ahbo_hwrite : out std_ulogic;
ahbo_hsize : out std_logic_vector(2 downto 0);
ahbo_hburst : out std_logic_vector(2 downto 0);
ahbo_hprot : out std_logic_vector(3 downto 0);
ahbo_hwdata : out std_logic_vector(AHBDW-1 downto 0);
-- I2C signals
--i2ci : in i2c_in_type;
i2ci_scl : in std_ulogic;
i2ci_sda : in std_ulogic;
--i2co : out i2c_out_type
i2co_scl : out std_ulogic;
i2co_scloen : out std_ulogic;
i2co_sda : out std_ulogic;
i2co_sdaoen : out std_ulogic;
i2co_enable : out std_ulogic
);
end entity i2c2ahb_gen;
architecture rtl of i2c2ahb_gen is
-- AHB signals
signal ahbi : ahb_mst_in_type;
signal ahbo : ahb_mst_out_type;
-- I2C signals
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
begin
ahbi.hgrant(0) <= ahbi_hgrant;
ahbi.hgrant(1 to NAHBMST-1) <= (others => '0');
ahbi.hready <= ahbi_hready;
ahbi.hresp <= ahbi_hresp;
ahbi.hrdata <= ahbi_hrdata;
ahbo_hbusreq <= ahbo.hbusreq;
ahbo_hlock <= ahbo.hlock;
ahbo_htrans <= ahbo.htrans;
ahbo_haddr <= ahbo.haddr;
ahbo_hwrite <= ahbo.hwrite;
ahbo_hsize <= ahbo.hsize;
ahbo_hburst <= ahbo.hburst;
ahbo_hprot <= ahbo.hprot;
ahbo_hwdata <= ahbo.hwdata;
i2ci.scl <= i2ci_scl;
i2ci.sda <= i2ci_sda;
i2co_scl <= i2co.scl;
i2co_scloen <= i2co.scloen;
i2co_sda <= i2co.sda;
i2co_sdaoen <= i2co.sdaoen;
i2co_enable <= i2co.enable;
i2c0 : i2c2ahb
generic map (
hindex => 0,
ahbaddrh => ahbaddrh, ahbaddrl => ahbaddrl,
ahbmaskh => ahbmaskh, ahbmaskl => ahbmaskl,
i2cslvaddr => i2cslvaddr, i2ccfgaddr => i2ccfgaddr,
oepol => oepol, filter => filter)
port map (rstn, clk, ahbi, ahbo, i2ci, i2co);
end architecture rtl;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_s2mm_omit_wrap.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_s2mm_omit_wrap.vhd
--
-- Description:
-- This file implements the DataMover MM2S Omit Wrapper.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
-------------------------------------------------------------------------------
entity axi_datamover_s2mm_omit_wrap is
generic (
C_INCLUDE_S2MM : Integer range 0 to 2 := 0;
-- Specifies the type of S2MM function to include
-- 0 = Omit S2MM functionality
-- 1 = Full S2MM Functionality
-- 2 = Lite S2MM functionality
C_S2MM_AWID : Integer range 0 to 255 := 9;
-- Specifies the constant value to output on
-- the ARID output port
C_S2MM_ID_WIDTH : Integer range 1 to 8 := 4;
-- Specifies the width of the S2MM ID port
C_S2MM_ADDR_WIDTH : Integer range 32 to 64 := 32;
-- Specifies the width of the MMap Read Address Channel
-- Address bus
C_S2MM_MDATA_WIDTH : Integer range 32 to 1024 := 32;
-- Specifies the width of the MMap Read Data Channel
-- data bus
C_S2MM_SDATA_WIDTH : Integer range 8 to 1024 := 32;
-- Specifies the width of the S2MM Master Stream Data
-- Channel data bus
C_INCLUDE_S2MM_STSFIFO : Integer range 0 to 1 := 0;
-- Specifies if a Status FIFO is to be implemented
-- 0 = Omit S2MM Status FIFO
-- 1 = Include S2MM Status FIFO
C_S2MM_STSCMD_FIFO_DEPTH : Integer range 1 to 16 := 4;
-- Specifies the depth of the S2MM Command FIFO and the
-- optional Status FIFO
-- Valid values are 1,4,8,16
C_S2MM_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0;
-- Specifies if the Status and Command interfaces need to
-- be asynchronous to the primary data path clocking
-- 0 = Use same clocking as data path
-- 1 = Use special Status/Command clock for the interfaces
C_INCLUDE_S2MM_DRE : Integer range 0 to 1 := 0;
-- Specifies if DRE is to be included in the S2MM function
-- 0 = Omit DRE
-- 1 = Include DRE
C_S2MM_BURST_SIZE : Integer range 2 to 256 := 16;
-- Specifies the max number of databeats to use for MMap
-- burst transfers by the S2MM function
C_S2MM_SUPPORT_INDET_BTT : Integer range 0 to 1 := 0;
-- Specifies if Store and Forward is enabled
C_S2MM_ADDR_PIPE_DEPTH : Integer range 1 to 30 := 1;
-- This parameter specifies the depth of the S2MM internal
-- address pipeline queues in the Write Address Controller
-- and the Write Data Controller. Increasing this value will
-- allow more Write Addresses to be issued to the AXI4 Write
-- Address Channel before transmission of the associated
-- write data on the Write Data Channel.
C_TAG_WIDTH : Integer range 1 to 8 := 4 ;
-- Width of the TAG field
C_ENABLE_CACHE_USER : Integer range 0 to 1 := 0;
C_FAMILY : String := "virtex7"
-- Specifies the target FPGA family type
);
port (
-- S2MM Primary Clock and reset inputs -----------------------
s2mm_aclk : in std_logic; --
-- Primary synchronization clock for the Master side --
-- interface and internal logic. It is also used --
-- for the User interface synchronization when --
-- C_STSCMD_IS_ASYNC = 0. --
--
-- S2MM Primary Reset input --
s2mm_aresetn : in std_logic; --
-- Reset used for the internal master logic --
--------------------------------------------------------------
-- S2MM Halt request input control ---------------------------
s2mm_halt : in std_logic; --
-- Active high soft shutdown request --
--
-- S2MM Halt Complete status flag --
s2mm_halt_cmplt : out std_logic; --
-- Active high soft shutdown complete status --
--------------------------------------------------------------
-- S2MM Error discrete output --------------------------------
s2mm_err : Out std_logic; --
-- Composite Error indication --
--------------------------------------------------------------
-- Optional S2MM Command/Status Clock and Reset Inputs -------
-- Only used if C_S2MM_STSCMD_IS_ASYNC = 1 --
s2mm_cmdsts_awclk : in std_logic; --
-- Secondary Clock input for async CMD/Status interface --
--
s2mm_cmdsts_aresetn : in std_logic; --
-- Secondary Reset input for async CMD/Status interface --
--------------------------------------------------------------
-- User Command Interface Ports (AXI Stream) -----------------------------------------------------
s2mm_cmd_wvalid : in std_logic; --
s2mm_cmd_wready : out std_logic; --
s2mm_cmd_wdata : in std_logic_vector((C_TAG_WIDTH+(8*C_ENABLE_CACHE_USER)+C_S2MM_ADDR_WIDTH+36)-1 downto 0); --
--------------------------------------------------------------------------------------------------
-- User Status Interface Ports (AXI Stream) --------------------------------------------------------
s2mm_sts_wvalid : out std_logic; --
s2mm_sts_wready : in std_logic; --
s2mm_sts_wdata : out std_logic_vector(((C_S2MM_SUPPORT_INDET_BTT*24)+8)-1 downto 0); --
s2mm_sts_wstrb : out std_logic_vector((((C_S2MM_SUPPORT_INDET_BTT*24)+8)/8)-1 downto 0); --
s2mm_sts_wlast : out std_logic; --
----------------------------------------------------------------------------------------------------
-- Address posting controls -----------------------------------------
s2mm_allow_addr_req : in std_logic; --
s2mm_addr_req_posted : out std_logic; --
s2mm_wr_xfer_cmplt : out std_logic; --
s2mm_ld_nxt_len : out std_logic; --
s2mm_wr_len : out std_logic_vector(7 downto 0); --
---------------------------------------------------------------------
-- S2MM AXI Address Channel I/O --------------------------------------
s2mm_awid : out std_logic_vector(C_S2MM_ID_WIDTH-1 downto 0); --
-- AXI Address Channel ID output --
--
s2mm_awaddr : out std_logic_vector(C_S2MM_ADDR_WIDTH-1 downto 0); --
-- AXI Address Channel Address output --
--
s2mm_awlen : out std_logic_vector(7 downto 0); --
-- AXI Address Channel LEN output --
-- Sized to support 256 data beat bursts --
--
s2mm_awsize : out std_logic_vector(2 downto 0); --
-- AXI Address Channel SIZE output --
--
s2mm_awburst : out std_logic_vector(1 downto 0); --
-- AXI Address Channel BURST output --
--
s2mm_awprot : out std_logic_vector(2 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awcache : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
s2mm_awuser : out std_logic_vector(3 downto 0); --
-- AXI Address Channel PROT output --
--
s2mm_awvalid : out std_logic; --
-- AXI Address Channel VALID output --
--
s2mm_awready : in std_logic; --
-- AXI Address Channel READY input --
-----------------------------------------------------------------------
-- Currently unsupported AXI Address Channel output signals -----------
-- s2mm__awlock : out std_logic_vector(2 downto 0); --
-- s2mm__awcache : out std_logic_vector(4 downto 0); --
-- s2mm__awqos : out std_logic_vector(3 downto 0); --
-- s2mm__awregion : out std_logic_vector(3 downto 0); --
-----------------------------------------------------------------------
-- S2MM AXI MMap Write Data Channel I/O ----------------------------------------------
s2mm_wdata : Out std_logic_vector(C_S2MM_MDATA_WIDTH-1 downto 0); --
s2mm_wstrb : Out std_logic_vector((C_S2MM_MDATA_WIDTH/8)-1 downto 0); --
s2mm_wlast : Out std_logic; --
s2mm_wvalid : Out std_logic; --
s2mm_wready : In std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI MMap Write response Channel I/O ------------------------------------------
s2mm_bresp : In std_logic_vector(1 downto 0); --
s2mm_bvalid : In std_logic; --
s2mm_bready : Out std_logic; --
---------------------------------------------------------------------------------------
-- S2MM AXI Master Stream Channel I/O ------------------------------------------------
s2mm_strm_wdata : In std_logic_vector(C_S2MM_SDATA_WIDTH-1 downto 0); --
s2mm_strm_wstrb : In std_logic_vector((C_S2MM_SDATA_WIDTH/8)-1 downto 0); --
s2mm_strm_wlast : In std_logic; --
s2mm_strm_wvalid : In std_logic; --
s2mm_strm_wready : Out std_logic; --
---------------------------------------------------------------------------------------
-- Testing Support I/O -----------------------------------------
s2mm_dbg_sel : in std_logic_vector( 3 downto 0); --
s2mm_dbg_data : out std_logic_vector(31 downto 0) --
----------------------------------------------------------------
);
end entity axi_datamover_s2mm_omit_wrap;
architecture implementation of axi_datamover_s2mm_omit_wrap is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
begin --(architecture implementation)
-- Just tie off output ports
s2mm_dbg_data <= X"CAFE0000" ; -- 32 bit Constant indicating S2MM OMIT type
s2mm_addr_req_posted <= '0' ;
s2mm_wr_xfer_cmplt <= '0' ;
s2mm_ld_nxt_len <= '0' ;
s2mm_wr_len <= (others => '0');
s2mm_halt_cmplt <= s2mm_halt ;
s2mm_err <= '0' ;
s2mm_cmd_wready <= '0' ;
s2mm_sts_wvalid <= '0' ;
s2mm_sts_wdata <= (others => '0');
s2mm_sts_wstrb <= (others => '0');
s2mm_sts_wlast <= '0' ;
s2mm_awid <= (others => '0');
s2mm_awaddr <= (others => '0');
s2mm_awlen <= (others => '0');
s2mm_awsize <= (others => '0');
s2mm_awburst <= (others => '0');
s2mm_awprot <= (others => '0');
s2mm_awcache <= (others => '0');
s2mm_awuser <= (others => '0');
s2mm_awvalid <= '0' ;
s2mm_wdata <= (others => '0');
s2mm_wstrb <= (others => '0');
s2mm_wlast <= '0' ;
s2mm_wvalid <= '0' ;
s2mm_bready <= '0' ;
s2mm_strm_wready <= '0' ;
-- Input ports are ignored
end implementation;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_ecc_e
--
-- Generated
-- by: wig
-- on: Mon Mar 22 13:27:43 2004
-- cmd: H:\work\mix_new\mix\mix_0.pl -strip -nodelta ../../mde_tests.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_ecc_e-e.vhd,v 1.1 2004/04/06 10:50:05 wig Exp $
-- $Date: 2004/04/06 10:50:05 $
-- $Log: inst_ecc_e-e.vhd,v $
-- Revision 1.1 2004/04/06 10:50:05 wig
-- Adding result/mde_tests
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.37 2003/12/23 13:25:21 abauer Exp
--
-- Generator: mix_0.pl Version: Revision: 1.26 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_ecc_e
--
entity inst_ecc_e is
-- Generics:
-- No Generated Generics for Entity inst_ecc_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_ecc_e
nreset : in std_ulogic;
nreset_s : in std_ulogic
-- End of Generated Port for Entity inst_ecc_e
);
end inst_ecc_e;
--
-- End of Generated Entity inst_ecc_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end generate;
end architecture;
|
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end generate;
end architecture;
|
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end generate;
end architecture;
|
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end generate;
end architecture;
|
entity ent is
generic (
config : string := "config0";
bits : bit_vector := "10101" );
end entity;
architecture a of ent is
signal sig : integer;
begin
gen_cfg1 : if config = "config1" generate
bad: sig <= 0;
end generate;
gen_cfg2 : if bits /= "00000" generate
good: sig <= 1;
end generate;
end architecture;
|
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab7_lib;
CONFIGURATION fetch_struct_config OF fetch IS
FOR struct
FOR ALL : Fetch_FSM
USE ENTITY lab7_lib.Fetch_FSM(FSM);
END FOR;
END FOR;
END fetch_struct_config;
|
-- Generation properties:
-- Format : hierarchical
-- Generic mappings : exclude
-- Leaf-level entities : direct binding
-- Regular libraries : use library name
-- View name : include
--
LIBRARY lab7_lib;
CONFIGURATION fetch_struct_config OF fetch IS
FOR struct
FOR ALL : Fetch_FSM
USE ENTITY lab7_lib.Fetch_FSM(FSM);
END FOR;
END FOR;
END fetch_struct_config;
|
when others =>
instrOutput <= X"0000_0000";
end case;
end if;
end process;
end architecture;
|
-- NEED RESULT: ARCH00109.P1: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00109.P2: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109.P3: Multi transport transactions occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00109: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS passed
-- NEED RESULT: ARCH00109: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109: One transport transaction occurred on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: ARCH00109: Old transactions were removed on signal asg with selected name prefixed by an indexed name on LHS failed
-- NEED RESULT: P3: Transport transactions entirely completed passed
-- NEED RESULT: P2: Transport transactions entirely completed passed
-- NEED RESULT: P1: Transport transactions entirely completed passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00109
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (2)
-- 8.3 (3)
-- 8.3 (5)
-- 8.3.1 (3)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00109(ARCH00109)
-- ENT00109_Test_Bench(ARCH00109_Test_Bench)
--
-- REVISION HISTORY:
--
-- 07-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00109 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns,
c_st_rec1_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00109.P1" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_2(highb).f2 after 10 ns ,
c_st_rec1_vector_1(highb).f2 after 20 ns ,
c_st_rec1_vector_2(highb).f2 after 30 ns ,
c_st_rec1_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector(lowb).f2 <= transport
c_st_rec1_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector(lowb).f2 =
c_st_rec1_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00109" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns,
c_st_rec2_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00109.P2" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_2(highb).f2 after 10 ns ,
c_st_rec2_vector_1(highb).f2 after 20 ns ,
c_st_rec2_vector_2(highb).f2 after 30 ns ,
c_st_rec2_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector(lowb).f2 <= transport
c_st_rec2_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector(lowb).f2 =
c_st_rec2_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00109" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns,
c_st_rec3_vector_1(highb).f2 after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00109.P3" ,
"Multi transport transactions occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_2(highb).f2 after 10 ns ,
c_st_rec3_vector_1(highb).f2 after 20 ns ,
c_st_rec3_vector_2(highb).f2 after 30 ns ,
c_st_rec3_vector_1(highb).f2 after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_2(highb).f2 and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector(lowb).f2 <= transport
c_st_rec3_vector_1(highb).f2 after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector(lowb).f2 =
c_st_rec3_vector_1(highb).f2 and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00109" ,
"One transport transaction occurred on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
correct ) ;
--
when others
=> -- No more transactions should have occurred
test_report ( "ARCH00109" ,
"Old transactions were removed on signal " &
"asg with selected name prefixed by an indexed name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
--
end ENT00109 ;
--
architecture ARCH00109 of ENT00109 is
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
--
begin
PGEN_CHKP_1 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Transport transactions entirely completed",
chk_st_rec1_vector = 4 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P1 :
process ( s_st_rec1_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
end process P1 ;
--
PGEN_CHKP_2 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Transport transactions entirely completed",
chk_st_rec2_vector = 4 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P2 :
process ( s_st_rec2_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
end process P2 ;
--
PGEN_CHKP_3 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Transport transactions entirely completed",
chk_st_rec3_vector = 4 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P3 :
process ( s_st_rec3_vector )
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
end process P3 ;
--
--
end ARCH00109 ;
--
entity ENT00109_Test_Bench is
end ENT00109_Test_Bench ;
--
architecture ARCH00109_Test_Bench of ENT00109_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00109 ( ARCH00109 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00109_Test_Bench ;
|
--!
--! Copyright (C) 2010 - 2012 Creonic GmbH
--!
--! This file is part of the Creonic Viterbi Decoder, which is distributed
--! under the terms of the GNU General Public License version 2.
--!
--! @file
--! @brief Generic single port RAM with a single read/write port
--! @author Matthias Alles
--! @date 2010/09/28
--!
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library dec_viterbi;
use dec_viterbi.pkg_helper.all;
entity generic_sp_ram is
generic(
DISTR_RAM : boolean := false;
WORDS : integer := 8;
BITWIDTH : integer := 8
);
port(
clk : in std_logic;
rst : in std_logic;
wen : in std_logic;
en : in std_logic;
a : in std_logic_vector(no_bits_natural(WORDS - 1) - 1 downto 0);
d : in std_logic_vector(BITWIDTH - 1 downto 0);
q : out std_logic_vector(BITWIDTH - 1 downto 0)
);
end generic_sp_ram;
architecture rtl of generic_sp_ram is
type t_ram is array(WORDS - 1 downto 0) of
std_logic_vector(BITWIDTH - 1 downto 0);
signal sp_ram : t_ram := (others => (others => '0'));
function get_ram_style_xilinx(dist_ram : in boolean) return string is
begin
if dist_ram then
return "pipe_distributed";
else
return "block";
end if;
end function;
function get_ram_style_altera(dist_ram : in boolean) return string is
begin
if dist_ram then
return "MLAB, no_rw_check";
else
return "AUTO";
end if;
end function;
attribute RAM_STYLE : string;
attribute RAM_STYLE of sp_ram : signal is get_ram_style_xilinx(DISTR_RAM);
attribute ramstyle : string;
attribute ramstyle of sp_ram : signal is get_ram_style_altera(DISTR_RAM);
begin
--
-- Do not register the address for reading, since the synthesis doesn't
-- recognize then that this is a single-port RAM.
--
pr_sp_ram_rw: process(clk)
begin
if rising_edge(clk) then
if en = '1' then
if wen = '1' then
sp_ram(conv_integer(a)) <= d;
else
q <= sp_ram(conv_integer(a));
end if;
end if;
end if;
end process pr_sp_ram_rw;
end rtl;
|
--
-- SineTable.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This entity represents a sine wave table which allow to choose one of
-- the normal sine or half sine wave. The table only contains quarter of
-- full wave to reduce hardware resources.
--
entity SineTable is
port (
clk : in std_logic;
wf : in std_logic;
addr : in integer range 0 to 2 ** (PGOUT_TYPE'high+1) - 1;
data : out SIGNED_DB_TYPE
);
end SineTable;
architecture RTL of SineTable is
constant TABLE_WIDTH : integer := (addr'high-addr'low+1)/4;
type sin_type is array (0 to TABLE_WIDTH-1) of DB_TYPE;
constant sin_data : sin_type := (
"1111111","1100101","1010101","1001100",
"1000101","1000000","0111100","0111000",
"0110101","0110011","0110000","0101110",
"0101100","0101010","0101000","0100111",
"0100101","0100100","0100011","0100001",
"0100000","0011111","0011110","0011101",
"0011100","0011011","0011010","0011010",
"0011001","0011000","0010111","0010110",
"0010110","0010101","0010100","0010100",
"0010011","0010011","0010010","0010001",
"0010001","0010000","0010000","0001111",
"0001111","0001110","0001110","0001110",
"0001101","0001101","0001100","0001100",
"0001011","0001011","0001011","0001010",
"0001010","0001010","0001001","0001001",
"0001001","0001000","0001000","0001000",
"0001000","0000111","0000111","0000111",
"0000110","0000110","0000110","0000110",
"0000101","0000101","0000101","0000101",
"0000101","0000100","0000100","0000100",
"0000100","0000100","0000011","0000011",
"0000011","0000011","0000011","0000011",
"0000010","0000010","0000010","0000010",
"0000010","0000010","0000010","0000001",
"0000001","0000001","0000001","0000001",
"0000001","0000001","0000001","0000001",
"0000001","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000"
);
begin
process (clk)
begin
if clk'event and clk = '1' then
if addr < TABLE_WIDTH then
data <= ( sign=>'0', value=>sin_data(addr) );
elsif addr < TABLE_WIDTH * 2 then
data <= ( sign=>'0', value=>sin_data(TABLE_WIDTH * 2 - 1 - addr) );
elsif addr < TABLE_WIDTH * 3 then
if wf = '0' then
data <= ( sign=>'1', value=>sin_data(addr - TABLE_WIDTH * 2));
else
data <= ( sign=>'1', value=>sin_data(0) );
end if ;
else
if wf = '0' then
data <= ( sign=>'1', value=>sin_data( TABLE_WIDTH * 4 - 1 - addr));
else
data <= ( sign=>'1', value=>sin_data(0) );
end if;
end if;
end if;
end process;
end RTL; |
--
-- SineTable.vhd
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use WORK.VM2413.ALL;
--
-- This entity represents a sine wave table which allow to choose one of
-- the normal sine or half sine wave. The table only contains quarter of
-- full wave to reduce hardware resources.
--
entity SineTable is
port (
clk : in std_logic;
wf : in std_logic;
addr : in integer range 0 to 2 ** (PGOUT_TYPE'high+1) - 1;
data : out SIGNED_DB_TYPE
);
end SineTable;
architecture RTL of SineTable is
constant TABLE_WIDTH : integer := (addr'high-addr'low+1)/4;
type sin_type is array (0 to TABLE_WIDTH-1) of DB_TYPE;
constant sin_data : sin_type := (
"1111111","1100101","1010101","1001100",
"1000101","1000000","0111100","0111000",
"0110101","0110011","0110000","0101110",
"0101100","0101010","0101000","0100111",
"0100101","0100100","0100011","0100001",
"0100000","0011111","0011110","0011101",
"0011100","0011011","0011010","0011010",
"0011001","0011000","0010111","0010110",
"0010110","0010101","0010100","0010100",
"0010011","0010011","0010010","0010001",
"0010001","0010000","0010000","0001111",
"0001111","0001110","0001110","0001110",
"0001101","0001101","0001100","0001100",
"0001011","0001011","0001011","0001010",
"0001010","0001010","0001001","0001001",
"0001001","0001000","0001000","0001000",
"0001000","0000111","0000111","0000111",
"0000110","0000110","0000110","0000110",
"0000101","0000101","0000101","0000101",
"0000101","0000100","0000100","0000100",
"0000100","0000100","0000011","0000011",
"0000011","0000011","0000011","0000011",
"0000010","0000010","0000010","0000010",
"0000010","0000010","0000010","0000001",
"0000001","0000001","0000001","0000001",
"0000001","0000001","0000001","0000001",
"0000001","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000",
"0000000","0000000","0000000","0000000"
);
begin
process (clk)
begin
if clk'event and clk = '1' then
if addr < TABLE_WIDTH then
data <= ( sign=>'0', value=>sin_data(addr) );
elsif addr < TABLE_WIDTH * 2 then
data <= ( sign=>'0', value=>sin_data(TABLE_WIDTH * 2 - 1 - addr) );
elsif addr < TABLE_WIDTH * 3 then
if wf = '0' then
data <= ( sign=>'1', value=>sin_data(addr - TABLE_WIDTH * 2));
else
data <= ( sign=>'1', value=>sin_data(0) );
end if ;
else
if wf = '0' then
data <= ( sign=>'1', value=>sin_data( TABLE_WIDTH * 4 - 1 - addr));
else
data <= ( sign=>'1', value=>sin_data(0) );
end if;
end if;
end if;
end process;
end RTL; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := spartan6;
constant CFG_MEMTECH : integer := spartan6;
constant CFG_PADTECH : integer := spartan6;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := spartan6;
constant CFG_CLKMUL : integer := (18);
constant CFG_CLKDIV : integer := (9);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 1;
constant CFG_NWP : integer := (0);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 1;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 1;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 0 + 0 + 0;
constant CFG_ETH_BUF : integer := 1;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0033#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000009#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 1;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDR2SP : integer := 0;
constant CFG_DDR2SP_INIT : integer := 0;
constant CFG_DDR2SP_FREQ : integer := 100;
constant CFG_DDR2SP_TRFC : integer := 130;
constant CFG_DDR2SP_DATAWIDTH : integer := 64;
constant CFG_DDR2SP_FTEN : integer := 0;
constant CFG_DDR2SP_FTWIDTH : integer := 0;
constant CFG_DDR2SP_COL : integer := 9;
constant CFG_DDR2SP_SIZE : integer := 8;
constant CFG_DDR2SP_DELAY0 : integer := 0;
constant CFG_DDR2SP_DELAY1 : integer := 0;
constant CFG_DDR2SP_DELAY2 : integer := 0;
constant CFG_DDR2SP_DELAY3 : integer := 0;
constant CFG_DDR2SP_DELAY4 : integer := 0;
constant CFG_DDR2SP_DELAY5 : integer := 0;
constant CFG_DDR2SP_DELAY6 : integer := 0;
constant CFG_DDR2SP_DELAY7 : integer := 0;
constant CFG_DDR2SP_NOSYNC : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#F00#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- SPI memory controller
constant CFG_SPIMCTRL : integer := 0;
constant CFG_SPIMCTRL_SDCARD : integer := 0;
constant CFG_SPIMCTRL_READCMD : integer := 16#0#;
constant CFG_SPIMCTRL_DUMMYBYTE : integer := 0;
constant CFG_SPIMCTRL_DUALOUTPUT : integer := 0;
constant CFG_SPIMCTRL_SCALER : integer := 1;
constant CFG_SPIMCTRL_ASCALER : integer := 1;
constant CFG_SPIMCTRL_PWRUPCNT : integer := 0;
constant CFG_SPIMCTRL_OFFSET : integer := 16#0#;
-- SPI controller
constant CFG_SPICTRL_ENABLE : integer := 0;
constant CFG_SPICTRL_NUM : integer := 1;
constant CFG_SPICTRL_SLVS : integer := 1;
constant CFG_SPICTRL_FIFO : integer := 1;
constant CFG_SPICTRL_SLVREG : integer := 0;
constant CFG_SPICTRL_ODMODE : integer := 0;
constant CFG_SPICTRL_AM : integer := 0;
constant CFG_SPICTRL_ASEL : integer := 0;
constant CFG_SPICTRL_TWEN : integer := 0;
constant CFG_SPICTRL_MAXWLEN : integer := 0;
constant CFG_SPICTRL_SYNCRAM : integer := 0;
constant CFG_SPICTRL_FT : integer := 0;
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
---------------------------------------------------------------------
--
-- File Name: TESTER_pkg.vhd
-- Project: LL FIFO
-- Version: 1.2
-- Date: 2005-06-29
--
-- Company: Xilinx, Inc.
-- Contributors: Wen Ying Wei, Davy Huang
--
-- Disclaimer: XILINX IS PROVIDING THIS DESIGN, CODE, OR
-- INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
-- PROGRAMS AND SOLUTIONS FOR XILINX DEVICES. BY
-- PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
-- ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
-- APPLICATION OR STANDARD, XILINX IS MAKING NO
-- REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
-- FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
-- RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
-- REQUIRE FOR YOUR IMPLEMENTATION. XILINX
-- EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
-- RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
-- INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
-- FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
-- OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE.
--
-- (c) Copyright 2005 Xilinx, Inc.
-- All rights reserved.
--
---------------------------------------------------------------------
--
-- Tester Package
-- Author: Davy Huang
--
-- Description:
-- This package file is created for mixed language simulation
-- using Aurora tester for LL FIFO.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package TESTER_pkg is
component OUTPUT_TESTER IS
GENERIC (
-- Parameter Declarations ********************************************
GLOBALDLY : integer := 1;
LL_DAT_BIT_WIDTH : integer := 16;
LL_REM_BIT_WIDTH : integer := 1;
FIFO_DEPTH : integer := 256);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
RX_D : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
RX_REM : IN std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
RX_SOF_N : IN std_logic;
RX_EOF_N : IN std_logic;
RX_SRC_RDY_N : IN std_logic;
UFC_RX_DATA : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
UFC_RX_REM : IN std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
UFC_RX_SOF_N : IN std_logic;
UFC_RX_EOF_N : IN std_logic;
UFC_RX_SRC_RDY_N : IN std_logic;
RX_SOF_N_REF : IN std_logic;
RX_EOF_N_REF : IN std_logic;
RX_REM_REF : IN std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
RX_DATA_REF : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
RX_SRC_RDY_N_REF : IN std_logic;
UFC_RX_DATA_REF : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
UFC_RX_REM_REF : IN std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
UFC_RX_SOF_N_REF : IN std_logic;
UFC_RX_EOF_N_REF : IN std_logic;
UFC_RX_SRC_RDY_N_REF : IN std_logic;
WORKING : OUT std_logic;
COMPARING : OUT std_logic;
OVERFLOW : OUT std_logic;
RESULT_GOOD : OUT std_logic;
RESULT_GOOD_PDU : OUT std_logic;
RESULT_GOOD_UFC : OUT std_logic);
END COMPONENT;
component OUTPUT_TESTER_8_BIT IS
GENERIC (
-- Parameter Declarations ********************************************
GLOBALDLY : integer := 1;
LL_DAT_BIT_WIDTH : integer := 8;
LL_REM_BIT_WIDTH : integer := 0;
FIFO_DEPTH : integer := 256);
PORT (
CLK : IN std_logic;
RST : IN std_logic;
RX_D : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
RX_REM : IN std_logic;
RX_SOF_N : IN std_logic;
RX_EOF_N : IN std_logic;
RX_SRC_RDY_N : IN std_logic;
UFC_RX_DATA : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
UFC_RX_REM : IN std_logic;
UFC_RX_SOF_N : IN std_logic;
UFC_RX_EOF_N : IN std_logic;
UFC_RX_SRC_RDY_N : IN std_logic;
RX_SOF_N_REF : IN std_logic;
RX_EOF_N_REF : IN std_logic;
RX_REM_REF : IN std_logic;
RX_DATA_REF : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
RX_SRC_RDY_N_REF : IN std_logic;
UFC_RX_DATA_REF : IN std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
UFC_RX_REM_REF : IN std_logic;
UFC_RX_SOF_N_REF : IN std_logic;
UFC_RX_EOF_N_REF : IN std_logic;
UFC_RX_SRC_RDY_N_REF : IN std_logic;
WORKING : OUT std_logic;
COMPARING : OUT std_logic;
OVERFLOW : OUT std_logic;
RESULT_GOOD : OUT std_logic;
RESULT_GOOD_PDU : OUT std_logic;
RESULT_GOOD_UFC : OUT std_logic);
END COMPONENT;
COMPONENT FILEREAD_TESTER IS
GENERIC (
-- Parameter Declarations ********************************************
GLOBALDLY : integer := 1;
TV_WIDTH : integer := 8;
CV_WIDTH : integer := 4;
LL_DAT_BIT_WIDTH : integer := 16;
LL_REM_BIT_WIDTH : integer := 1;
REM_VECTOR_WIDTH : integer := 3);
PORT (
CLK : IN std_logic;
TV : IN std_logic_vector(0 TO TV_WIDTH - 1);
TX_SOF_N : OUT std_logic;
TX_EOF_N : OUT std_logic;
TX_D : OUT std_logic_vector(0 TO LL_DAT_BIT_WIDTH - 1);
TX_REM : OUT std_logic_vector(0 TO LL_REM_BIT_WIDTH - 1);
TX_SRC_RDY_N : OUT std_logic;
NFC_NB : OUT std_logic_vector(0 TO 3);
NFC_REQ_N : OUT std_logic;
UFC_TX_REQ_N : OUT std_logic;
UFC_TX_MS : OUT std_logic_vector(0 TO 3);
CTRL : OUT std_logic_vector(0 TO CV_WIDTH -1));
END COMPONENT;
end TESTER_pkg;
------------------------------------------------------------------------
-- History:
-- DH 8/22/03 -- Initial design
------------------------------------------------------------------------
-- $Revision: 1.2 $
-- $Date: 2004/12/27 18:12:18 $
|
architecture RTL of FIFO is
begin
process
variable var1 : integer := 0;
file file1 : load_file_file open read_mode is load_file_name;
constant con1 : std_logic := '1';
alias alias1 is name;
alias alias1 : subtype_indicator is name;
begin
end process;
-- Violations below
process
variable var1 : integer := 0;
file file1: load_file_file open read_mode is load_file_name;
constant con1 : std_logic := '1';
alias alias1 is name;
alias alias1: subtype_indicator is name;
begin
end process;
process
procedure some_procedure (count : integer) is
variable v_count : std_logic_vector(SOME_CONSTANT - 1 downto 0);
begin
end procedure;
variable var1 : integer := 0;
file file1 : load_file_file open read_mode is load_file_name;
constant con1 : std_logic := '1';
alias alias1 is name;
alias alias1 : subtype_indicator is name;
begin end process;
end architecture RTL;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: memctrl
-- File: memctrl.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Memory controller package
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
library techmap;
use techmap.gencomp.all;
package memctrl is
type memory_in_type is record
data : std_logic_vector(31 downto 0); -- Data bus address
brdyn : std_logic;
bexcn : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bwidth : std_logic_vector(1 downto 0);
sd : std_logic_vector(63 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
edac : std_logic;
end record;
type memory_out_type is record
address : std_logic_vector(31 downto 0);
data : std_logic_vector(31 downto 0);
sddata : std_logic_vector(63 downto 0);
ramsn : std_logic_vector(7 downto 0);
ramoen : std_logic_vector(7 downto 0);
ramn : std_ulogic;
romn : std_ulogic;
mben : std_logic_vector(3 downto 0);
iosn : std_logic;
romsn : std_logic_vector(7 downto 0);
oen : std_logic;
writen : std_logic;
wrn : std_logic_vector(3 downto 0);
bdrive : std_logic_vector(3 downto 0);
vbdrive : std_logic_vector(31 downto 0); --vector bus drive
svbdrive : std_logic_vector(63 downto 0); --vector bus drive sdram
read : std_logic;
sa : std_logic_vector(14 downto 0);
cb : std_logic_vector(7 downto 0);
scb : std_logic_vector(7 downto 0);
vcdrive : std_logic_vector(7 downto 0); --vector bus drive cb
svcdrive : std_logic_vector(7 downto 0); --vector bus drive cb sdram
ce : std_ulogic;
end record;
type sdctrl_in_type is record
wprot : std_ulogic;
data : std_logic_vector (127 downto 0); -- data in
cb : std_logic_vector(15 downto 0);
end record;
type sdctrl_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 15 downto 0); -- data i/o mask
bdrive : std_ulogic; -- bus drive
qdrive : std_ulogic; -- bus drive
vbdrive : std_logic_vector(31 downto 0); -- vector bus drive
address : std_logic_vector (16 downto 2); -- address out
data : std_logic_vector (127 downto 0); -- data out
cb : std_logic_vector(15 downto 0);
ce : std_ulogic;
ba : std_logic_vector ( 1 downto 0); -- bank address
cal_en : std_logic_vector(7 downto 0); -- enable delay calibration
cal_inc : std_logic_vector(7 downto 0); -- inc/dec delay
cal_rst : std_logic; -- calibration reset
odt : std_logic_vector(1 downto 0);
end record;
type sdram_out_type is record
sdcke : std_logic_vector ( 1 downto 0); -- clk en
sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
sdwen : std_ulogic; -- write en
rasn : std_ulogic; -- row addr stb
casn : std_ulogic; -- col addr stb
dqm : std_logic_vector ( 7 downto 0); -- data i/o mask
end record;
component sdctrl
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ftsdctrl is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
pwron : integer := 0;
sdbits : integer := 32;
edacen : integer := 1;
errcnt : integer := 0;
cntbits : integer range 1 to 8 := 1;
oepol : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component srctrl
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
prom8en : integer := 0;
oepol : integer := 0;
srbanks : integer range 1 to 5 := 1;
banksz : integer range 0 to 13 := 13;
romasel : integer range 0 to 28 := 19
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ftsrctrl is
generic (
hindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
romws : integer := 2;
iows : integer := 2;
rmw : integer := 0;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
rombanks : integer range 1 to 8 := 1;
rombanksz : integer range 0 to 15 := 15;
rombankszdef : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 0;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0;
prom8en : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
type sdram_in_type is record
haddr : std_logic_vector(31 downto 0); -- memory address
rhaddr : std_logic_vector(31 downto 0); -- latched memory address
hready : std_ulogic;
hsize : std_logic_vector(1 downto 0);
hsel : std_ulogic;
hwrite : std_ulogic;
htrans : std_logic_vector(1 downto 0);
rhtrans : std_logic_vector(1 downto 0);
nhtrans : std_logic_vector(1 downto 0);
idle : std_ulogic;
enable : std_ulogic;
error : std_ulogic;
brmw : std_ulogic;
edac : std_ulogic;
srdis : std_logic;
end record;
type sdram_mctrl_out_type is record
address : std_logic_vector(16 downto 2);
busy : std_ulogic;
aload : std_ulogic;
bdrive : std_ulogic;
hready : std_ulogic;
hsel : std_ulogic;
bsel : std_ulogic;
hresp : std_logic_vector (1 downto 0);
vhready : std_ulogic;
prdata : std_logic_vector (31 downto 0);
end record;
type wprot_out_type is record
wprothit : std_ulogic;
end record;
component sdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftsdmctrl
generic (
pindex : integer := 0;
invclk : integer := 0;
fast : integer := 0;
wprot : integer := 0;
sdbits : integer := 32;
syncrst : integer := 0;
pageburst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
sdi : in sdram_in_type;
sdo : out sdram_out_type;
apbi : in apb_slv_in_type;
wpo : in wprot_out_type;
sdmo : out sdram_mctrl_out_type
);
end component;
component ftmctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 16#000#;
rommask : integer := 16#E00#;
ioaddr : integer := 16#200#;
iomask : integer := 16#E00#;
ramaddr : integer := 16#400#;
rammask : integer := 16#C00#;
paddr : integer := 0;
pmask : integer := 16#fff#;
wprot : integer := 0;
invclk : integer := 0;
fast : integer := 0;
romasel : integer := 28;
sdrasel : integer := 29;
srbanks : integer := 4;
ram8 : integer := 0;
ram16 : integer := 0;
sden : integer := 0;
sepbus : integer := 0;
sdbits : integer := 32;
sdlsb : integer := 2; -- set to 12 for the GE-HPE board
oepol : integer := 0;
edac : integer := 0;
syncrst : integer := 0;
pageburst : integer := 0;
scantest : integer := 0;
writefb : integer := 0;
netlist : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
memi : in memory_in_type;
memo : out memory_out_type;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
wpo : in wprot_out_type;
sdo : out sdram_out_type
);
end component;
component ssrctrl
generic (
hindex : integer := 0;
pindex : integer := 0;
romaddr : integer := 0;
rommask : integer := 16#ff0#;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
paddr : integer := 0;
pmask : integer := 16#fff#;
oepol : integer := 0;
bus16 : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
type ddrmem_in_type is record
cke : std_ulogic;
cs : std_logic_vector(1 downto 0);
control : std_logic_vector(2 downto 0); --RAS,CAS,WE
ba : std_logic_vector(1 downto 0);
adr : std_logic_vector(13 downto 0);
dq : std_logic_vector(63 downto 0);
dm : std_logic_vector(15 downto 0);
dqs : std_logic_vector(15 downto 0);
dq_oe : std_logic_vector(63 downto 0);
dqs_oe : std_logic_vector(15 downto 0);
end record;
type ddrmem_out_type is record
dq : std_logic_vector(63 downto 0);
dqs : std_logic_vector(15 downto 0);
end record;
component ddrctrl
generic (
hindex1 : integer := 0;
haddr1 : integer := 0;
hmask1 : integer := 16#f80#;
hindex2 : integer := 0;
haddr2 : integer := 0;
hmask2 : integer := 16#f80#;
pindex : integer := 3;
paddr : integer := 0;
numahb : integer := 1; -- Allowed: 1, 2
ahb1sepclk : integer := 0; -- Allowed: 0, 1
ahb2sepclk : integer := 0; -- Allowed: 0, 1
modbanks : integer := 1; -- Allowed: 1, 2
numchips : integer := 8; -- Allowed: 1, 2, 4, 8, 16
chipbits : integer := 8; -- Allowed: 4, 8, 16
chipsize : integer := 128; -- Allowed: 64, 128, 256, 512, 1024 (MB)
plldelay : integer := 0; -- Allowed: 0, 1 (Use 200us start up delay)
tech : integer := 0;
clkperiod : integer := 10); -- 100 Mhz
port (
rst : in std_ulogic;
clk0 : in std_ulogic;
clk90 : in std_ulogic;
clk180 : in std_ulogic;
clk270 : in std_ulogic;
hclk1 : in std_ulogic;
hclk2 : in std_ulogic;
pclk : in std_ulogic;
ahb1si : in ahb_slv_in_type;
ahb1so : out ahb_slv_out_type;
ahb2si : in ahb_slv_in_type;
ahb2so : out ahb_slv_out_type;
apbsi : in apb_slv_in_type;
apbso : out apb_slv_out_type;
-- dapbso : out apb_slv_out_type;
ddsi : out ddrmem_in_type;
ddso : in ddrmem_out_type);
end component;
component ftsrctrl_v1
generic (
hindex: Integer := 1;
romaddr: Integer := 16#000#;
rommask: Integer := 16#ff0#;
ramaddr: Integer := 16#400#;
rammask: Integer := 16#ff0#;
ioaddr: Integer := 16#200#;
iomask: Integer := 16#ff0#;
ramws: Integer := 0;
romws: Integer := 0;
iows: Integer := 0;
rmw: Integer := 1;
srbanks: Integer range 1 to 8 := 8;
banksz: Integer range 0 to 13 := 0;
rombanks: Integer range 1 to 8 := 8;
rombanksz: Integer range 0 to 13 := 0;
rombankszdef: Integer range 0 to 13 := 6;
romasel: Integer range 0 to 28 := 0;
pindex: Integer := 0;
paddr: Integer := 16#000#;
pmask: Integer := 16#fff#;
edacen: Integer range 0 to 1 := 1;
errcnt: Integer range 0 to 1 := 0;
cntbits: Integer range 1 to 8 := 1;
wsreg: Integer := 1;
oepol: Integer := 0);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbit : integer := 256;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp64a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp32a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrsp16a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkread : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddrspa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0); -- ddr data
hackVector : out std_logic_vector(7 downto 0)
);
end component;
component ddr2sp16a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2sp32a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2sp64a
generic (
memtech : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
col : integer := 9;
Mbyte : integer := 16;
fast : integer := 0;
pwron : integer := 0;
oepol : integer := 0;
readdly : integer := 1;
odten : integer := 0
);
port (
rst : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
sdi : in sdctrl_in_type;
sdo : out sdctrl_out_type
);
end component;
component ddr2spa
generic (
fabtech : integer := 0;
memtech : integer := 0;
rskew : integer := 0;
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#f00#;
ioaddr : integer := 16#000#;
iomask : integer := 16#fff#;
MHz : integer := 100;
clkmul : integer := 2;
clkdiv : integer := 2;
col : integer := 9;
Mbyte : integer := 16;
rstdel : integer := 200;
pwron : integer := 0;
oepol : integer := 0;
ddrbits : integer := 16;
ahbfreq : integer := 50;
readdly : integer := 1;
ddelayb0 : integer := 0;
ddelayb1 : integer := 0;
ddelayb2 : integer := 0;
ddelayb3 : integer := 0;
ddelayb4 : integer := 0;
ddelayb5 : integer := 0;
ddelayb6 : integer := 0;
ddelayb7 : integer := 0;
numidelctrl : integer := 4;
norefclk : integer := 0;
odten : integer := 0
);
port (
rst_ddr : in std_ulogic;
rst_ahb : in std_ulogic;
clk_ddr : in std_ulogic;
clk_ahb : in std_ulogic;
clkref200 : in std_ulogic;
lock : out std_ulogic; -- DCM locked
clkddro : out std_ulogic; -- DCM locked
clkddri : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
-- ddr_clk_fb_out : out std_logic;
-- ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (ddrbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (ddrbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (ddrbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0)
);
end component;
component ddr_phy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkread : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end component;
component ddr2_phy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref200 : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(1 downto 0);
sdi : out sdctrl_in_type;
sdo : in sdctrl_out_type);
end component;
component ftsrctrl8 is
generic (
hindex : integer := 0;
ramaddr : integer := 16#400#;
rammask : integer := 16#ff0#;
ioaddr : integer := 16#200#;
iomask : integer := 16#ff0#;
ramws : integer := 0;
iows : integer := 2;
srbanks : integer range 1 to 8 := 1;
banksz : integer range 0 to 15 := 15;
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
edacen : integer range 0 to 1 := 1;
errcnt : integer range 0 to 1 := 1;
cntbits : integer range 1 to 8 := 1;
wsreg : integer := 0;
oepol : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
sri : in memory_in_type;
sro : out memory_out_type
);
end component;
end;
|
--###############################
--# Project Name :
--# File :
--# Project :
--# Engineer :
--# Modification History
--###############################
library IEEE;
use IEEE.std_logic_1164.all;
entity TB_I2CSLAVE_READ is
end TB_I2CSLAVE_READ;
architecture stimulus of TB_I2CSLAVE_READ is
-- COMPONENTS --
component I2CSLAVE
port(
MCLK : in std_logic;
nRST : in std_logic;
SDA_IN : in std_logic;
SCL_IN : in std_logic;
SDA_OUT : out std_logic;
SCL_OUT : out std_logic;
ADDRESS : out std_logic_vector(7 downto 0);
DATA_OUT : out std_logic_vector(7 downto 0);
DATA_IN : in std_logic_vector(7 downto 0);
WR : out std_logic;
RD : out std_logic;
READ_DONE : out std_logic
);
end component;
--
-- SIGNALS --
signal MCLK : std_logic;
signal nRST : std_logic;
signal SDA_IN : std_logic;
signal SCL_IN : std_logic;
signal SDA_OUT : std_logic;
signal SCL_OUT : std_logic;
signal ADDRESS : std_logic_vector(7 downto 0);
signal DATA_OUT : std_logic_vector(7 downto 0);
signal DATA_IN : std_logic_vector(7 downto 0);
signal WR : std_logic;
signal RD : std_logic;
signal READ_DONE : std_logic;
--
signal RUNNING : std_logic := '1';
signal result : std_logic_vector(7 downto 0);
begin
-- PORT MAP --
I_I2CSLAVE_0 : I2CSLAVE
port map (
MCLK => MCLK,
nRST => nRST,
SDA_IN => SDA_IN,
SCL_IN => SCL_IN,
SDA_OUT => SDA_OUT,
SCL_OUT => SCL_OUT,
ADDRESS => ADDRESS,
DATA_OUT => DATA_OUT,
DATA_IN => DATA_IN,
WR => WR,
RD => RD,
READ_DONE => READ_DONE
);
--
CLOCK: process
begin
while (RUNNING = '1') loop
MCLK <= '1';
wait for 10 ns;
MCLK <= '0';
wait for 10 ns;
end loop;
wait;
end process CLOCK;
GO: process
procedure SendData(data : in std_logic_vector(7 downto 0)) is
variable d : std_logic_vector(7 downto 0);
begin
d := data;
SCL_IN <= '0';
for i in 0 to 7 loop
SDA_IN <= d(7);
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SCL_IN <= '0';
d(7 downto 1) := d(6 downto 0);
wait for 80 ns;
end loop;
SDA_IN <= '1';
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SCL_IN <= '0';
wait for 80 ns;
end SendData;
procedure ReadData(nack: in std_logic) is
variable d: std_logic_vector(7 downto 0);
begin
SCL_IN <= '0';
for i in 0 to 7 loop
d(7 downto 1) := d(6 downto 0);
wait for 80 ns;
SCL_IN <= '1';
d(0) := SDA_OUT;
wait for 80 ns;
SCL_IN <= '0';
wait for 80 ns;
end loop;
SDA_IN <= nack;
result <= d;
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SCL_IN <= '0';
wait for 80 ns;
SDA_IN <= '1';
end ReadData;
begin
result <= x"FF";
wait for 1 ns;
nRST <= '0';
SDA_IN <= '1';
SCL_IN <= '1';
wait for 1000 ns;
nRST <= '1';
SDA_IN <= '0'; -- start
wait for 80 ns;
SendData(x"70"); -- 38 < 1 + write
SendData(x"55"); -- address
SDA_IN <= '0'; -- prepare stop bit
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SDA_IN <= '1';
wait for 80 ns;
SDA_IN <= '0'; -- start2
wait for 80 ns;
SendData(x"71"); -- 38 < 1 + read
ReadData('0'); -- ack
ReadData('0'); -- ack
ReadData('1'); -- nack
SDA_IN <= '0'; -- prepare stop bit
wait for 80 ns;
SCL_IN <= '1';
wait for 80 ns;
SDA_IN <= '1'; -- stop
wait for 1000 ns;
RUNNING <= '0';
wait;
end process GO;
P_READ: process
begin
wait for 100 ns;
DATA_IN <= x"FF";
wait until RD'event and RD='0';
DATA_IN <= x"66";
wait until RD'event and RD='0';
DATA_IN <= x"77";
wait until RD'event and RD='0';
DATA_IN <= x"88";
wait;
end process P_READ;
end stimulus;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use ieee.std_logic_signed.all; -- never use this library!!!
use ieee.std_logic_misc.all; -- provides or_reduce
use work.core_defs.all;
use work.functions_and_types.all;
entity alu is
port(op1 : in std_logic_vector(data_bits-1 downto 0);
op2 : in std_logic_vector(data_bits-1 downto 0);
aluctl : in std_logic_vector(alu_op_bits-1 downto 0);
res : out std_logic_vector(data_bits-1 downto 0);
carry : out std_logic;
zero : out std_logic;
neg : out std_logic;
ovfl : out std_logic
);
end alu;
architecture alu_impl of alu is
signal tmp : std_logic_vector(data_bits downto 0);
signal op2in : std_logic_vector(data_bits-1 downto 0);
signal is_subtraction : std_logic;
begin
is_subtraction <= bitwise_cmp(aluctl,"0101");
op2in <= sign_extend(is_subtraction,op2in'length) xor op2;
res <= tmp(tmp'left-1 downto 0);
zero <= not(or_reduce(tmp(tmp'left-1 downto 0)));
--A "combinational process" must have a sensitivity list containing all
--the signals which it reads (inputs), and must always update the signals
--which it assigns (outputs).
operate : process (aluctl, op1, op2,op2in, is_subtraction)
begin
case aluctl is
when "0000" => tmp <= logic_extend(op1 and op2in,tmp'length);
when "0001" => tmp <= logic_extend(op1 or op2in,tmp'length);
when "0010" => tmp <= logic_extend(op1 xor op2in,tmp'length);
when "0011" | "0100" | "0101" => tmp <= full_adder(op1, op2in, is_subtraction);
when "0110" => tmp <= logic_extend(bitwise_cmp(op1,op2in),tmp'length);
when others => tmp <= sign_extend('0',tmp'length);
end case;
end process;
outputs : process(aluctl,op1,op2,op2in,tmp)
begin
case? aluctl is
when "0011" => ovfl <= ((tmp(op1'left) xor op1(op1'left)) and (tmp(op2in'left) xor op2in(op2in'left))); -- ADD INTEGER
carry <= (tmp(tmp'left));
neg <= tmp(data_bits-1);
when "0100" => ovfl <= (tmp(tmp'left)); -- ADD NATURAL
carry <= (tmp(tmp'left));
neg <= '0';
when "0101" => ovfl <= (((not (tmp(op2'left))) xor op2(op2'left)) and (op1(op1'left) xor op2(op2'left))); -- SUB
carry <= tmp(tmp'left);
neg <= tmp(tmp'left-1);
when others => ovfl <= '0';
carry <= '0';
neg <= '0';
end case?;
end process;
end alu_impl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- LUT/FF/S3S/BRAM: 260/111/136/1
library work;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity iec_processor_io is
generic (
g_mhz : natural := 50);
port (
clock : in std_logic;
reset : in std_logic;
req : in t_io_req;
resp : out t_io_resp;
irq : out std_logic;
clk_o : out std_logic;
clk_i : in std_logic;
data_o : out std_logic;
data_i : in std_logic;
atn_o : out std_logic;
atn_i : in std_logic;
srq_o : out std_logic;
srq_i : in std_logic );
end iec_processor_io;
architecture structural of iec_processor_io is
signal proc_reset : std_logic;
signal enable : std_logic;
-- irq
signal irq_event : std_logic;
signal irq_enable : std_logic;
signal irq_status : std_logic;
-- instruction ram interface
signal instr_addr : unsigned(8 downto 0);
signal instr_en : std_logic;
signal instr_data : std_logic_vector(31 downto 0);
-- software fifo interface
signal up_fifo_get : std_logic;
signal up_fifo_put : std_logic;
signal up_fifo_din : std_logic_vector(8 downto 0);
signal up_fifo_dout : std_logic_vector(8 downto 0);
signal up_fifo_empty : std_logic;
signal up_fifo_full : std_logic;
signal up_dav : std_logic;
signal up_space : std_logic;
signal down_fifo_flush : std_logic;
signal down_fifo_empty : std_logic;
signal down_fifo_full : std_logic;
signal down_fifo_get : std_logic;
signal down_fifo_put : std_logic;
signal down_fifo_din : std_logic_vector(8 downto 0);
signal down_fifo_dout : std_logic_vector(8 downto 0);
signal down_dav : std_logic;
signal down_space : std_logic;
signal ram_en : std_logic;
signal ram_rdata : std_logic_vector(7 downto 0);
signal ram_sel : std_logic;
signal reg_rdata : std_logic_vector(7 downto 0);
begin
i_proc: entity work.iec_processor
generic map (
g_mhz => g_mhz )
port map (
clock => clock,
reset => proc_reset,
-- instruction ram interface
instr_addr => instr_addr,
instr_en => instr_en,
instr_data => instr_data(29 downto 0),
-- software fifo interface
up_fifo_put => up_fifo_put,
up_fifo_din => up_fifo_din,
up_fifo_full => up_fifo_full,
down_fifo_empty => down_fifo_empty,
down_fifo_get => down_fifo_get,
down_fifo_dout => down_fifo_dout,
down_fifo_flush => down_fifo_flush,
irq_event => irq_event,
clk_o => clk_o,
clk_i => clk_i,
data_o => data_o,
data_i => data_i,
atn_o => atn_o,
atn_i => atn_i,
srq_o => srq_o,
srq_i => srq_i );
i_ram: RAMB16_S9_S36
generic map (
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST" )
port map (
DOA => ram_rdata,
ADDRA => std_logic_vector(req.address(10 downto 0)),
CLKA => clock,
DIA => req.data,
DIPA => "0",
ENA => ram_en,
SSRA => '0',
WEA => req.write,
DOB(31 downto 24) => instr_data(7 downto 0), -- CPU is big endian
DOB(23 downto 16) => instr_data(15 downto 8),
DOB(15 downto 8) => instr_data(23 downto 16),
DOB(7 downto 0) => instr_data(31 downto 24),
ADDRB => std_logic_vector(instr_addr),
CLKB => clock,
DIB => X"00000000",
DIPB => X"0",
ENB => instr_en,
SSRB => '0',
WEB => '0' );
-- i_up_fifo: entity work.srl_fifo
-- generic map (
-- Width => 9,
-- Depth => 15, -- 15 is the maximum
-- Threshold => 13 )
-- port map (
-- clock => clock,
-- reset => reset,
-- GetElement => up_fifo_get,
-- PutElement => up_fifo_put,
-- FlushFifo => '0',
-- DataIn => up_fifo_din,
-- DataOut => up_fifo_dout,
-- SpaceInFifo => up_space,
-- AlmostFull => open,
-- DataInFifo => up_dav);
--
-- up_fifo_empty <= not up_dav;
-- up_fifo_full <= not up_space;
i_up_fifo: entity work.sync_fifo
generic map (
g_depth => 2048,
g_data_width => 9,
g_threshold => 500,
g_storage => "blockram", -- can also be "blockram" or "distributed"
g_fall_through => true )
port map (
clock => clock,
reset => reset,
rd_en => up_fifo_get,
wr_en => up_fifo_put,
din => up_fifo_din,
dout => up_fifo_dout,
flush => '0',
full => up_fifo_full,
almost_full => open,
empty => up_fifo_empty,
count => open );
i_down_fifo: entity work.srl_fifo
generic map (
Width => 9,
Depth => 15, -- 15 is the maximum
Threshold => 13 )
port map (
clock => clock,
reset => reset,
GetElement => down_fifo_get,
PutElement => down_fifo_put,
FlushFifo => down_fifo_flush,
DataIn => down_fifo_din,
DataOut => down_fifo_dout,
SpaceInFifo => down_space,
AlmostFull => open,
DataInFifo => down_dav);
down_fifo_empty <= not down_dav;
down_fifo_full <= not down_space;
process(clock)
begin
if rising_edge(clock) then
ram_sel <= '0';
reg_rdata <= (others => '0');
proc_reset <= not enable;
resp.ack <= '0';
if req.read='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
ram_sel <= req.address(11);
case req.address(3 downto 0) is
when X"0" =>
reg_rdata <= X"23"; -- version
when X"1" =>
reg_rdata(0) <= down_fifo_empty;
reg_rdata(1) <= down_fifo_full;
when X"2" =>
reg_rdata(0) <= up_fifo_empty;
reg_rdata(1) <= up_fifo_full;
reg_rdata(7) <= up_fifo_dout(8);
when X"6"|X"8"|X"9"|X"A"|X"B" =>
reg_rdata <= up_fifo_dout(7 downto 0);
when X"7" =>
reg_rdata <= "0000000" & up_fifo_dout(8);
when X"C" =>
reg_rdata <= "0000000" & irq_status;
when others => null;
end case;
elsif req.write='1' then
resp.ack <= '1'; -- data handled outside clocked process if ram
if req.address(11)='0' then
case req.address(3 downto 0) is
when X"3" =>
proc_reset <= '1';
enable <= req.data(0);
when X"C" =>
irq_status <= '0';
irq_enable <= req.data(0);
when others =>
null;
end case;
end if;
end if;
if irq_event='1' then
irq_status <= '1';
end if;
irq <= irq_enable and irq_status;
if reset='1' then
proc_reset <= '1';
enable <= '0';
end if;
end if;
end process;
resp.data <= ram_rdata when ram_sel='1' else reg_rdata;
down_fifo_put <= '1' when req.write='1' and req.address(11)='0' and req.address(3 downto 1) = "10" else '0';
up_fifo_get <= '1' when req.read='1' and req.address(11)='0' and ((req.address(3 downto 0) = "0110") or (req.address(3 downto 2) = "10")) else '0';
down_fifo_din <= req.address(0) & req.data;
ram_en <= (req.write or req.read) and req.address(11);
end structural;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.