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--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity Q_reg is
port (
F : in MVL7_vector(3 downto 0);
clk : in clock;
I : in MVL7_vector(8 downto 0);
Q0, Q3 : in MVL7;
Q : inout MVL7_vector(3 downto 0)
);
end Q_reg;
architecture Q_reg of Q_reg is
begin
Q_reg1 : block ( (clk = '1') and (not clk'stable ) )
begin
-- WRITE TO Q REGISTER WITH/WITHOUT SHIFTING.
Q <= guarded F when (I(8 downto 6) = "000") else
Q3 & Q(3 downto 1) when (I(8 downto 6) = "100") else
Q(2 downto 0) & Q0 when (I(8 downto 6) = "110") else
Q;
end block Q_reg1;
end Q_reg;
---------------------------------------------
|
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity Q_reg is
port (
F : in MVL7_vector(3 downto 0);
clk : in clock;
I : in MVL7_vector(8 downto 0);
Q0, Q3 : in MVL7;
Q : inout MVL7_vector(3 downto 0)
);
end Q_reg;
architecture Q_reg of Q_reg is
begin
Q_reg1 : block ( (clk = '1') and (not clk'stable ) )
begin
-- WRITE TO Q REGISTER WITH/WITHOUT SHIFTING.
Q <= guarded F when (I(8 downto 6) = "000") else
Q3 & Q(3 downto 1) when (I(8 downto 6) = "100") else
Q(2 downto 0) & Q0 when (I(8 downto 6) = "110") else
Q;
end block Q_reg1;
end Q_reg;
---------------------------------------------
|
--------------------------------------------------------------------------------
--
-- AM2901 Benchmark
--
-- Source: AMD data book
--
-- VHDL Benchmark author Indraneel Ghosh
-- University Of California, Irvine, CA 92717
--
-- Developed on Jan 1, 1992
--
-- Verification Information:
--
-- Verified By whom? Date Simulator
-- -------- ------------ -------- ------------
-- Syntax yes Champaka Ramachandran Sept 17, 92 ZYCAD
-- Functionality yes Champaka Ramachandran Sept 17, 92 ZYCAD
--------------------------------------------------------------------------------
--library ZYCAD;
use work.TYPES.all;
use work.MVL7_functions.all;
use work.synthesis_types.all;
entity Q_reg is
port (
F : in MVL7_vector(3 downto 0);
clk : in clock;
I : in MVL7_vector(8 downto 0);
Q0, Q3 : in MVL7;
Q : inout MVL7_vector(3 downto 0)
);
end Q_reg;
architecture Q_reg of Q_reg is
begin
Q_reg1 : block ( (clk = '1') and (not clk'stable ) )
begin
-- WRITE TO Q REGISTER WITH/WITHOUT SHIFTING.
Q <= guarded F when (I(8 downto 6) = "000") else
Q3 & Q(3 downto 1) when (I(8 downto 6) = "100") else
Q(2 downto 0) & Q0 when (I(8 downto 6) = "110") else
Q;
end block Q_reg1;
end Q_reg;
---------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end icap;
architecture spartan_3a of icap is
type t_state is (idle, pulse, hold);
signal state : t_state;
signal icap_cen : std_logic := '1';
signal icap_data : std_logic_vector(0 to 7);
signal icap_clk : std_logic := '0';
function swap_bits(s : std_logic_vector) return std_logic_vector is
variable in_vec : std_logic_vector(s'length downto 1) := s;
variable out_vec : std_logic_vector(1 to s'length);
begin
for i in in_vec'range loop
out_vec(i) := in_vec(i);
end loop;
return out_vec;
end swap_bits;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
case io_req.address(3 downto 0) is
when c_icap_pulse =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '0';
state <= pulse;
when c_icap_write =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '1';
state <= pulse;
when others =>
io_resp.ack <= '1';
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_icap_fpga_type =>
io_resp.data <= g_fpga_type;
when others =>
null;
end case;
end if;
when pulse =>
icap_clk <= '1';
state <= hold;
when hold =>
icap_clk <= '0';
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
if reset='1' then
state <= idle;
icap_data <= X"00";
icap_cen <= '1';
icap_clk <= '0';
end if;
end if;
end process;
i_icap: ICAP_SPARTAN3A
port map (
CLK => icap_clk,
CE => icap_cen,
WRITE => icap_cen,
I => icap_data,
O => open,
BUSY => open );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end icap;
architecture spartan_3a of icap is
type t_state is (idle, pulse, hold);
signal state : t_state;
signal icap_cen : std_logic := '1';
signal icap_data : std_logic_vector(0 to 7);
signal icap_clk : std_logic := '0';
function swap_bits(s : std_logic_vector) return std_logic_vector is
variable in_vec : std_logic_vector(s'length downto 1) := s;
variable out_vec : std_logic_vector(1 to s'length);
begin
for i in in_vec'range loop
out_vec(i) := in_vec(i);
end loop;
return out_vec;
end swap_bits;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
case io_req.address(3 downto 0) is
when c_icap_pulse =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '0';
state <= pulse;
when c_icap_write =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '1';
state <= pulse;
when others =>
io_resp.ack <= '1';
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_icap_fpga_type =>
io_resp.data <= g_fpga_type;
when others =>
null;
end case;
end if;
when pulse =>
icap_clk <= '1';
state <= hold;
when hold =>
icap_clk <= '0';
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
if reset='1' then
state <= idle;
icap_data <= X"00";
icap_cen <= '1';
icap_clk <= '0';
end if;
end if;
end process;
i_icap: ICAP_SPARTAN3A
port map (
CLK => icap_clk,
CE => icap_cen,
WRITE => icap_cen,
I => icap_data,
O => open,
BUSY => open );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end icap;
architecture spartan_3a of icap is
type t_state is (idle, pulse, hold);
signal state : t_state;
signal icap_cen : std_logic := '1';
signal icap_data : std_logic_vector(0 to 7);
signal icap_clk : std_logic := '0';
function swap_bits(s : std_logic_vector) return std_logic_vector is
variable in_vec : std_logic_vector(s'length downto 1) := s;
variable out_vec : std_logic_vector(1 to s'length);
begin
for i in in_vec'range loop
out_vec(i) := in_vec(i);
end loop;
return out_vec;
end swap_bits;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
case io_req.address(3 downto 0) is
when c_icap_pulse =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '0';
state <= pulse;
when c_icap_write =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '1';
state <= pulse;
when others =>
io_resp.ack <= '1';
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_icap_fpga_type =>
io_resp.data <= g_fpga_type;
when others =>
null;
end case;
end if;
when pulse =>
icap_clk <= '1';
state <= hold;
when hold =>
icap_clk <= '0';
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
if reset='1' then
state <= idle;
icap_data <= X"00";
icap_cen <= '1';
icap_clk <= '0';
end if;
end if;
end process;
i_icap: ICAP_SPARTAN3A
port map (
CLK => icap_clk,
CE => icap_cen,
WRITE => icap_cen,
I => icap_data,
O => open,
BUSY => open );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end icap;
architecture spartan_3a of icap is
type t_state is (idle, pulse, hold);
signal state : t_state;
signal icap_cen : std_logic := '1';
signal icap_data : std_logic_vector(0 to 7);
signal icap_clk : std_logic := '0';
function swap_bits(s : std_logic_vector) return std_logic_vector is
variable in_vec : std_logic_vector(s'length downto 1) := s;
variable out_vec : std_logic_vector(1 to s'length);
begin
for i in in_vec'range loop
out_vec(i) := in_vec(i);
end loop;
return out_vec;
end swap_bits;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
case io_req.address(3 downto 0) is
when c_icap_pulse =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '0';
state <= pulse;
when c_icap_write =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '1';
state <= pulse;
when others =>
io_resp.ack <= '1';
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_icap_fpga_type =>
io_resp.data <= g_fpga_type;
when others =>
null;
end case;
end if;
when pulse =>
icap_clk <= '1';
state <= hold;
when hold =>
icap_clk <= '0';
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
if reset='1' then
state <= idle;
icap_data <= X"00";
icap_cen <= '1';
icap_clk <= '0';
end if;
end if;
end process;
i_icap: ICAP_SPARTAN3A
port map (
CLK => icap_clk,
CE => icap_cen,
WRITE => icap_cen,
I => icap_data,
O => open,
BUSY => open );
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.io_bus_pkg.all;
use work.icap_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity icap is
generic (
g_fpga_type : std_logic_vector(7 downto 0) := X"3A" );
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req;
io_resp : out t_io_resp );
end icap;
architecture spartan_3a of icap is
type t_state is (idle, pulse, hold);
signal state : t_state;
signal icap_cen : std_logic := '1';
signal icap_data : std_logic_vector(0 to 7);
signal icap_clk : std_logic := '0';
function swap_bits(s : std_logic_vector) return std_logic_vector is
variable in_vec : std_logic_vector(s'length downto 1) := s;
variable out_vec : std_logic_vector(1 to s'length);
begin
for i in in_vec'range loop
out_vec(i) := in_vec(i);
end loop;
return out_vec;
end swap_bits;
begin
process(clock)
begin
if rising_edge(clock) then
io_resp <= c_io_resp_init;
case state is
when idle =>
if io_req.write='1' then
case io_req.address(3 downto 0) is
when c_icap_pulse =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '0';
state <= pulse;
when c_icap_write =>
icap_data <= swap_bits(io_req.data);
icap_cen <= '1';
state <= pulse;
when others =>
io_resp.ack <= '1';
end case;
elsif io_req.read='1' then
io_resp.ack <= '1';
case io_req.address(3 downto 0) is
when c_icap_fpga_type =>
io_resp.data <= g_fpga_type;
when others =>
null;
end case;
end if;
when pulse =>
icap_clk <= '1';
state <= hold;
when hold =>
icap_clk <= '0';
io_resp.ack <= '1';
state <= idle;
when others =>
null;
end case;
if reset='1' then
state <= idle;
icap_data <= X"00";
icap_cen <= '1';
icap_clk <= '0';
end if;
end if;
end process;
i_icap: ICAP_SPARTAN3A
port map (
CLK => icap_clk,
CE => icap_cen,
WRITE => icap_cen,
I => icap_data,
O => open,
BUSY => open );
end architecture;
|
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
o => o,
i0 => i(0),
i1 => i(1),
i2 => i(2),
i3 => i(3) );
process is
begin
i <= "0000";
wait for 1 ns;
assert o = '1';
i <= "0001";
wait for 1 ns;
assert o = '0';
i <= "1111";
wait for 1 ns;
assert o = '1';
wait;
end process;
end architecture;
|
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
o => o,
i0 => i(0),
i1 => i(1),
i2 => i(2),
i3 => i(3) );
process is
begin
i <= "0000";
wait for 1 ns;
assert o = '1';
i <= "0001";
wait for 1 ns;
assert o = '0';
i <= "1111";
wait for 1 ns;
assert o = '1';
wait;
end process;
end architecture;
|
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
o => o,
i0 => i(0),
i1 => i(1),
i2 => i(2),
i3 => i(3) );
process is
begin
i <= "0000";
wait for 1 ns;
assert o = '1';
i <= "0001";
wait for 1 ns;
assert o = '0';
i <= "1111";
wait for 1 ns;
assert o = '1';
wait;
end process;
end architecture;
|
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
o => o,
i0 => i(0),
i1 => i(1),
i2 => i(2),
i3 => i(3) );
process is
begin
i <= "0000";
wait for 1 ns;
assert o = '1';
i <= "0001";
wait for 1 ns;
assert o = '0';
i <= "1111";
wait for 1 ns;
assert o = '1';
wait;
end process;
end architecture;
|
entity lut4_test is
end entity;
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
architecture test of lut4_test is
signal i : std_logic_vector(3 downto 0);
signal o : std_logic;
begin
uut: LUT4
generic map (
INIT => X"8001" )
port map (
o => o,
i0 => i(0),
i1 => i(1),
i2 => i(2),
i3 => i(3) );
process is
begin
i <= "0000";
wait for 1 ns;
assert o = '1';
i <= "0001";
wait for 1 ns;
assert o = '0';
i <= "1111";
wait for 1 ns;
assert o = '1';
wait;
end process;
end architecture;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:56:25 10/19/2014
-- Design Name:
-- Module Name: D:/Documents/Xilinx Projects/multi_cycle_cpu/src/reg_file_tb.vhd
-- Project Name: multi_cycle_cpu
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: reg_file
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use ieee.numeric_std.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY reg_file_tb IS
END reg_file_tb;
ARCHITECTURE behavior OF reg_file_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT reg_file
PORT(
clk : IN std_logic;
wr_en : IN std_logic;
rd_reg_num1 : IN std_logic_vector(4 downto 0);
rd_reg_num2 : IN std_logic_vector(4 downto 0);
wr_reg_num : IN std_logic_vector(4 downto 0);
wr_data : IN std_logic_vector(31 downto 0);
rd_data1 : OUT std_logic_vector(31 downto 0);
rd_data2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal wr_en : std_logic := '0';
signal rd_reg_num1 : std_logic_vector(4 downto 0) := (others => '0');
signal rd_reg_num2 : std_logic_vector(4 downto 0) := (others => '0');
signal wr_reg_num : std_logic_vector(4 downto 0) := (others => '0');
signal wr_data : std_logic_vector(31 downto 0) := (others => '0');
--Outputs
signal rd_data1 : std_logic_vector(31 downto 0);
signal rd_data2 : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: reg_file PORT MAP (
clk => clk,
wr_en => wr_en,
rd_reg_num1 => rd_reg_num1,
rd_reg_num2 => rd_reg_num2,
wr_reg_num => wr_reg_num,
wr_data => wr_data,
rd_data1 => rd_data1,
rd_data2 => rd_data2
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clk_period*10;
-- insert stimulus here
-- write some data
for i in 0 to 31 loop
wr_en <= '1';
wr_reg_num <= std_logic_vector(to_unsigned(i, 5));
wr_data <= std_logic_vector( X"ffffff00" + to_signed( i, 32));
wait for clk_period;
end loop;
wr_en <= '0';
-- test read from reg no.1
for i in 0 to 31 loop
rd_reg_num1 <= std_logic_vector(to_unsigned(i, 5));
wait for clk_period;
assert rd_data1 = std_logic_vector( X"ffffff00" + to_signed( i, 32)) report "reading test 1 failed" severity error;
end loop;
-- test read from reg no.2
for i in 0 to 31 loop
rd_reg_num2 <= std_logic_vector(to_unsigned(i, 5));
wait for clk_period;
assert rd_data2 = std_logic_vector( X"ffffff00" + to_signed( i, 32)) report "reading test 2 failed" severity error;
end loop;
assert false report "end of simulation" severity failure;
wait;
end process;
END;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Single-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating single-port RAM
--
-- - single clock, clock enable
-- - 1 read/write port
--
-- Written data is passed through the memory and output again as read-data 'q'.
-- This is the normal behaviour of a single-port RAM and also known as
-- write-first mode or read-through-write behaviour.
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_sp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end entity;
architecture rtl of ocram_sp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates single-port memory as expected.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
signal a_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
if we = '1' then
ram(to_integer(a)) <= d;
end if;
a_reg <= a;
end if;
end if;
end process;
q <= ram(to_integer(a_reg)); -- gets new data
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
signal a_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
if we = '1' then
ram(to_integer(a)) <= d;
end if;
a_reg <= a;
end if;
end if;
end process;
q <= ram(to_integer(a_reg)); -- gets new data
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_sp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0));
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_sp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk => clk,
ce => ce,
we => we,
a => a,
d => d,
q => q
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Martin Zabel
-- Patrick Lehmann
--
-- Module: Single-port memory.
--
-- Description:
-- ------------------------------------
-- Inferring / instantiating single-port RAM
--
-- - single clock, clock enable
-- - 1 read/write port
--
-- Written data is passed through the memory and output again as read-data 'q'.
-- This is the normal behaviour of a single-port RAM and also known as
-- write-first mode or read-through-write behaviour.
--
-- License:
-- ============================================================================
-- Copyright 2008-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library STD;
use STD.TextIO.all;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_textio.all;
library PoC;
use PoC.config.all;
use PoC.utils.all;
use PoC.strings.all;
entity ocram_sp is
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0)
);
end entity;
architecture rtl of ocram_sp is
constant DEPTH : positive := 2**A_BITS;
begin
gInfer: if VENDOR = VENDOR_XILINX generate
-- RAM can be inferred correctly
-- XST Advanced HDL Synthesis generates single-port memory as expected.
subtype word_t is std_logic_vector(D_BITS - 1 downto 0);
type ram_t is array(0 to DEPTH - 1) of word_t;
begin
genLoadFile : if (str_length(FileName) /= 0) generate
-- Read a *.mem or *.hex file
impure function ocram_ReadMemFile(FileName : STRING) return ram_t is
file FileHandle : TEXT open READ_MODE is FileName;
variable CurrentLine : LINE;
variable TempWord : STD_LOGIC_VECTOR((div_ceil(word_t'length, 4) * 4) - 1 downto 0);
variable Result : ram_t := (others => (others => '0'));
begin
-- discard the first line of a mem file
if (str_toLower(FileName(FileName'length - 3 to FileName'length)) = ".mem") then
readline(FileHandle, CurrentLine);
end if;
for i in 0 to DEPTH - 1 loop
exit when endfile(FileHandle);
readline(FileHandle, CurrentLine);
hread(CurrentLine, TempWord);
Result(i) := resize(TempWord, word_t'length);
end loop;
return Result;
end function;
signal ram : ram_t := ocram_ReadMemFile(FILENAME);
signal a_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
if we = '1' then
ram(to_integer(a)) <= d;
end if;
a_reg <= a;
end if;
end if;
end process;
q <= ram(to_integer(a_reg)); -- gets new data
end generate;
genNoLoadFile : if (str_length(FileName) = 0) generate
signal ram : ram_t;
signal a_reg : unsigned(A_BITS-1 downto 0);
begin
process (clk)
begin
if rising_edge(clk) then
if ce = '1' then
if we = '1' then
ram(to_integer(a)) <= d;
end if;
a_reg <= a;
end if;
end if;
end process;
q <= ram(to_integer(a_reg)); -- gets new data
end generate;
end generate gInfer;
gAltera: if VENDOR = VENDOR_ALTERA generate
component ocram_sp_altera
generic (
A_BITS : positive;
D_BITS : positive;
FILENAME : STRING := ""
);
port (
clk : in std_logic;
ce : in std_logic;
we : in std_logic;
a : in unsigned(A_BITS-1 downto 0);
d : in std_logic_vector(D_BITS-1 downto 0);
q : out std_logic_vector(D_BITS-1 downto 0));
end component;
begin
-- Direct instantiation of altsyncram (including component
-- declaration above) is not sufficient for ModelSim.
-- That requires also usage of altera_mf library.
i: ocram_sp_altera
generic map (
A_BITS => A_BITS,
D_BITS => D_BITS,
FILENAME => FILENAME
)
port map (
clk => clk,
ce => ce,
we => we,
a => a,
d => d,
q => q
);
end generate gAltera;
assert VENDOR = VENDOR_XILINX or VENDOR = VENDOR_ALTERA
report "Device not yet supported."
severity failure;
end rtl;
|
------------------------------------------------------------------------------
--! Copyright (C) 2009 , Olivier Girard
--
--! Redistribution and use in source and binary forms, with or without
--! modification, are permitted provided that the following conditions
--! are met:
--! * Redistributions of source code must retain the above copyright
--! notice, this list of conditions and the following disclaimer.
--! * Redistributions in binary form must reproduce the above copyright
--! notice, this list of conditions and the following disclaimer in the
--! documentation and/or other materials provided with the distribution.
--! * Neither the name of the authors nor the names of its contributors
--! may be used to endorse or promote products derived from this software
--! without specific prior written permission.
--
--! THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--! AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--! IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
--! ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
--! LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY,
--! OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
--! SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
--! INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
--! CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
--! ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
--! THE POSSIBILITY OF SUCH DAMAGE
--
------------------------------------------------------------------------------
--
--! @file fmsp_dbg_i2c.vhd
--!
--! @brief fpgaMSP430 Debug I2C Slave communication interface
--
--! @author Olivier Girard, [email protected]
--! @author Emmanuel Amadio, [email protected] (VHDL Rewrite)
--
------------------------------------------------------------------------------
--! @version 1
--! @date: 2017-04-21
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all; --! standard unresolved logic UX01ZWLH-
use ieee.numeric_std.all; --! for the signed, unsigned types and arithmetic ops
use work.fmsp_misc_package.all;
entity fmsp_dbg_i2c is
generic (
DBG_I2C_BROADCAST_EN : boolean := false --! Enable the I2C broadcast address
);
port (
dbg_clk : in std_logic; --! Debug unit clock
dbg_rst : in std_logic; --! Debug unit reset
--! INPUTs
dbg_dout : in std_logic_vector(15 downto 0); --! Debug register data output
dbg_i2c_addr : in std_logic_vector(6 downto 0); --! Debug interface: I2C ADDRESS
dbg_i2c_broadcast : in std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : in std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : in std_logic; --! Debug interface: I2C SDA IN
mem_burst : in std_logic; --! Burst on going
mem_burst_end : in std_logic; --! End TX/RX burst
mem_burst_rd : in std_logic; --! Start TX burst
mem_burst_wr : in std_logic; --! Start RX burst
mem_bw : in std_logic; --! Burst byte width
--! OUTPUTs
dbg_addr : out std_logic_vector(5 downto 0); --! Debug register address
dbg_din : out std_logic_vector(15 downto 0); --! Debug register data input
dbg_i2c_sda_out : out std_logic; --! Debug interface: I2C SDA OUT
dbg_rd : out std_logic; --! Debug register data read
dbg_wr : out std_logic --! Debug register data write
);
end entity fmsp_dbg_i2c;
architecture RTL of fmsp_dbg_i2c is
--! 3) I2C STATE MACHINE
--! State machine definition
-- constant RX_ADDR : integer := 0;
-- constant RX_ADDR_ACK : integer := 1;
-- constant RX_DATA : integer := 2;
-- constant RX_DATA_ACK : integer := 3;
-- constant TX_DATA : integer := 4;
-- constant TX_DATA_ACK : integer := 5;
type I2C_STATE_TYPE is ( RX_ADDR,
RX_ADDR_ACK,
RX_DATA,
RX_DATA_ACK,
TX_DATA,
TX_DATA_ACK
); --type of state machine.
--! 6) DEBUG INTERFACE STATE MACHINE
--! State machine definition
-- constant RX_CMD : integer := 0;
-- constant RX_BYTE_LO : integer := 1;
-- constant RX_BYTE_HI : integer := 2;
-- constant TX_BYTE_LO : integer := 3;
-- constant TX_BYTE_HI : integer := 4;
type DBG_STATE_TYPE is ( RX_CMD,
RX_BYTE_LO,
RX_BYTE_HI,
TX_BYTE_LO,
TX_BYTE_HI
); --type of state machine.
--! 7) REGISTER READ/WRITE ACCESS
constant MEM_DATA : std_logic_vector(5 downto 0) := "000110";
type fmsp_dbg_i2c_in_type is record
dbg_dout : std_logic_vector(15 downto 0); --! Debug register data output
dbg_i2c_addr : std_logic_vector(6 downto 0); --! Debug interface: I2C ADDRESS
dbg_i2c_broadcast : std_logic_vector(6 downto 0); --! Debug interface: I2C Broadcast Address (for multicore systems)
dbg_i2c_scl : std_logic; --! Debug interface: I2C SCL
dbg_i2c_sda_in : std_logic; --! Debug interface: I2C SDA IN
mem_burst : std_logic; --! Burst on going
mem_burst_end : std_logic; --! End TX/RX burst
mem_burst_rd : std_logic; --! Start TX burst
mem_burst_wr : std_logic; --! Start RX burst
mem_bw : std_logic; --! Burst byte width
scl_sync_n : std_logic;
sda_in_sync_n : std_logic;
end record;
type reg_type is record
scl_buf : std_logic_vector(1 downto 0); --! SCL/SDA input buffers
sda_in_buf : std_logic_vector(1 downto 0); --! SCL/SDA input buffers
sda_in_dly : std_logic; --! SDA Edge detection
scl_dly : std_logic; --! SCL Edge detection
scl_re_dly : std_logic_vector(1 downto 0); --! Delayed SCL Rising-Edge for SDA data sampling
i2c_active_seq : std_logic; --! I2C Slave Active
i2c_state : I2C_STATE_TYPE; --! State register/wires
-- i2c_state_nxt : I2C_STATE_TYPE; --! State register/wires
shift_buf : std_logic_vector(8 downto 0); --! Utility signals
dbg_rd : std_logic; --! Utility signals
dbg_i2c_sda_out : std_logic; --! 5) I2C TRANSMIT BUFFER
dbg_state : DBG_STATE_TYPE; --! State register/wires
dbg_addr : std_logic_vector(5 downto 0);
dbg_din_lo : std_logic_vector(7 downto 0);
dbg_din_hi : std_logic_vector(7 downto 0);
dbg_bw : std_logic; --! Utility signals
dbg_wr : std_logic; --! Debug register data write command
end record;
signal d : fmsp_dbg_i2c_in_type;
signal r : reg_type := ( scl_buf => "00", --! SCL/SDA input buffers
sda_in_buf => "00", --! SCL/SDA input buffers
sda_in_dly => '0', --! SDA Edge detection
scl_dly => '0', --! SCL Edge detection
scl_re_dly => "00", --! Delayed SCL Rising-Edge for SDA data sampling
i2c_active_seq => '0', --! I2C Slave Active
i2c_state => RX_ADDR, --! State register/wires
shift_buf => "000000000",--! Utility signals
dbg_rd => '0', --! Utility signals
dbg_i2c_sda_out => '0', --! I2C TRANSMIT BUFFER
dbg_state => RX_CMD, --! State register/wires
dbg_addr => "000000",
dbg_din_lo => "00000000",
dbg_din_hi => "00000000",
dbg_bw => '0', --! Utility signals
dbg_wr => '0' --! Debug register data write command
);
signal rin : reg_type;
begin
d.dbg_dout <= dbg_dout;
d.dbg_i2c_addr <= dbg_i2c_addr;
d.dbg_i2c_broadcast <= dbg_i2c_broadcast;
d.dbg_i2c_scl <= dbg_i2c_scl;
d.dbg_i2c_sda_in <= dbg_i2c_sda_in;
d.mem_burst <= mem_burst;
d.mem_burst_end <= mem_burst_end;
d.mem_burst_rd <= mem_burst_rd;
d.mem_burst_wr <= mem_burst_wr;
d.mem_bw <= mem_bw;
COMB : process (d, r)
variable v : reg_type;
--! 1) I2C RECEIVE LINE SYNCHRONIZTION & FILTERING
--! Synchronize SCL/SDA inputs
variable v_scl_sync_n : std_logic;
variable v_scl_sync : std_logic;
variable v_sda_in_sync_n : std_logic;
variable v_sda_in_sync : std_logic;
--! SCL/SDA Majority decision
variable v_scl : std_logic;
variable v_sda_in : std_logic;
--! SDA Edge detection
variable v_sda_in_fe : std_logic;
variable v_sda_in_re : std_logic;
-- variable v_sda_in_edge : std_logic;
--! SCL Edge detection
variable v_scl_fe : std_logic;
variable v_scl_re : std_logic;
-- variable v_scl_edge : std_logic;
--! Delayed SCL Rising-Edge for SDA data sampling
variable v_scl_sample : std_logic;
--! 2) I2C START & STOP CONDITION DETECTION
--! Start condition
variable v_start_detect : std_logic;
--! Stop condition
variable v_stop_detect : std_logic;
--! I2C Slave Active
variable v_i2c_addr_not_valid : std_logic;
variable v_i2c_active : std_logic;
variable v_i2c_init : std_logic;
--! State machine
variable v_i2c_state_nxt : I2C_STATE_TYPE;
--! 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
variable v_shift_rx_en : std_logic;
variable v_shift_tx_en : std_logic;
variable v_shift_tx_en_pre : std_logic;
variable v_shift_rx_done : std_logic;
variable v_shift_tx_done : std_logic;
variable v_shift_buf_rx_init : std_logic;
variable v_shift_buf_rx_en : std_logic;
variable v_shift_buf_tx_init : std_logic;
variable v_shift_buf_tx_en : std_logic;
variable v_shift_tx_val : std_logic_vector(7 downto 0);
variable v_shift_buf_nxt : std_logic_vector(8 downto 0);
variable v_shift_buf : std_logic;
--! Detect when the received I2C device address is not valid
-- variable v_i2c_addr_not_valid : std_logic;
variable UNUSED_dbg_i2c_broadcast : std_logic_vector(6 downto 0);
--! Utility signals
variable v_shift_rx_data_done : std_logic;
variable v_shift_tx_data_done : std_logic;
--! State machine
variable v_dbg_state_nxt : DBG_STATE_TYPE;
--! Utility signals
variable v_cmd_valid : std_logic;
variable v_rx_lo_valid : std_logic;
variable v_rx_hi_valid : std_logic;
--! Debug register address & bit width
variable v_dbg_addr : std_logic_vector(5 downto 0);
--! Debug register data input
variable v_dbg_din : std_logic_vector(15 downto 0);
--! Debug register data read command
-- variable v_dbg_rd : std_logic;
--! Debug register data read value
-- variable v_shift_tx_val : std_logic;
begin
--! default assignment
v := r;
--! overriding assignments
v_scl_sync := not(d.scl_sync_n);
v_sda_in_sync := not(d.sda_in_sync_n);
--! SCL/SDA input buffers
v.scl_buf := r.scl_buf(0) & v_scl_sync;
v.sda_in_buf := r.sda_in_buf(0) & v_sda_in_sync;
--! SCL/SDA Majority decision
v_scl := (v_scl_sync and r.scl_buf(0))
or (v_scl_sync and r.scl_buf(0))
or (r.scl_buf(0) and r.scl_buf(1));
v_sda_in := (v_sda_in_sync and r.sda_in_buf(0))
or (v_sda_in_sync and r.sda_in_buf(1))
or (r.sda_in_buf(0) and r.sda_in_buf(1));
--! SCL/SDA Edge detection
--------------------------------
--! SDA Edge detection
v.sda_in_dly := v_sda_in;
v_sda_in_fe := r.sda_in_dly and not( v_sda_in);
v_sda_in_re := not( r.sda_in_dly) and v_sda_in;
-- v_sda_in_edge := r.sda_in_dly xor v_sda_in;
--! SCL Edge detection
v.scl_dly := v_scl;
v_scl_fe := r.scl_dly and not( v_scl);
v_scl_re := not( r.scl_dly) and v_scl;
-- v_scl_edge := r.scl_dly xor v_scl;
--! Delayed SCL Rising-Edge for SDA data sampling
v.scl_re_dly := r.scl_re_dly(0) & v_scl_re;
v_scl_sample := r.scl_re_dly(1);
--=============================================================================
--! 4) I2C SHIFT REGISTER (FOR RECEIVING)
--=============================================================================
v_shift_rx_en := '0';
if ( (r.i2c_state = RX_ADDR)
or (r.i2c_state = RX_DATA)
or (r.i2c_state = RX_DATA_ACK)
) then
v_shift_rx_en := '1';
end if;
v_shift_rx_done := v_shift_rx_en and v_scl_fe and r.shift_buf(8);
v_shift_buf_rx_init := '0';
if ( (v_i2c_init = '1')
or ( (r.i2c_state = RX_ADDR_ACK)
and (v_scl_fe = '1')
and (not(r.shift_buf(8)) = '1')
)
or ( (r.i2c_state = RX_DATA_ACK)
and (v_scl_fe = '1')
)
) then
v_shift_buf_rx_init := '1';
end if;
v_shift_buf_rx_en := v_shift_rx_en and v_scl_sample;
--! Detect when the received I2C device address is not valid
v_i2c_addr_not_valid := '0';
if (DBG_I2C_BROADCAST_EN = true) then
if ( (r.i2c_state = RX_ADDR)
and (v_shift_rx_done = '1')
and (r.shift_buf(7 downto 1) /= d.dbg_i2c_broadcast(6 downto 0))
and (r.shift_buf(7 downto 1) /= d.dbg_i2c_addr(6 downto 0))
) then
v_i2c_addr_not_valid := '1';
end if;
else
if ( (r.i2c_state = RX_ADDR)
and (v_shift_rx_done = '1')
and (r.shift_buf(7 downto 1) /= d.dbg_i2c_addr(6 downto 0))
) then
v_i2c_addr_not_valid := '1';
end if;
end if;
--=============================================================================
--! 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
--=============================================================================
v_shift_tx_en := '0';
if ( (r.i2c_state = TX_DATA)
or (r.i2c_state = TX_DATA_ACK)
) then
v_shift_tx_en := '1';
end if;
if (r.shift_buf = "100000000") then
v_shift_tx_done := v_shift_tx_en and v_scl_fe;
else
v_shift_tx_done := '0';
end if;
--=============================================================================
--! 2) I2C START & STOP CONDITION DETECTION
--=============================================================================
--! Start condition
v_start_detect := v_sda_in_fe and v_scl;
--! Stop condition
v_stop_detect := v_sda_in_re and v_scl;
-------------------
--! I2C Slave Active
-------------------
--! The I2C logic will be activated whenever a start condition
--! is detected and will be disactivated if the slave address
--! doesn't match or if a stop condition is detected.
if (v_start_detect = '1') then
v.i2c_active_seq := '1';
elsif ((v_stop_detect = '1') or (v_i2c_addr_not_valid = '1')) then
v.i2c_active_seq := '0';
end if;
v_i2c_active := r.i2c_active_seq and not(v_stop_detect);
v_i2c_init := not(v_i2c_active) or v_start_detect;
--=============================================================================
--! 3) I2C STATE MACHINE
--=============================================================================
--! State transition
case (r.i2c_state) is
when RX_ADDR =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_shift_rx_done) = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_i2c_addr_not_valid) = '1') then
v_i2c_state_nxt := RX_ADDR;
else
v_i2c_state_nxt := RX_ADDR_ACK;
end if;
when RX_ADDR_ACK =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_scl_fe) = '1') then
v_i2c_state_nxt := RX_ADDR_ACK;
elsif (r.shift_buf(0) = '1') then
v_i2c_state_nxt := TX_DATA;
else
v_i2c_state_nxt := RX_DATA;
end if;
when RX_DATA =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_shift_rx_done) = '1') then
v_i2c_state_nxt := RX_DATA;
else
v_i2c_state_nxt := RX_DATA_ACK;
end if;
when RX_DATA_ACK =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_scl_fe) = '1') then
v_i2c_state_nxt := RX_DATA_ACK;
else
v_i2c_state_nxt := RX_DATA;
end if;
when TX_DATA =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_shift_tx_done) = '1') then
v_i2c_state_nxt := TX_DATA;
else
v_i2c_state_nxt := TX_DATA_ACK;
end if;
when TX_DATA_ACK =>
if (v_i2c_init = '1') then
v_i2c_state_nxt := RX_ADDR;
elsif (not(v_scl_fe) = '1') then
v_i2c_state_nxt := TX_DATA_ACK;
elsif (not(v_sda_in) = '1') then
v_i2c_state_nxt := TX_DATA;
else
v_i2c_state_nxt := RX_ADDR;
end if;
when Others =>
v_i2c_state_nxt := RX_ADDR;
end case;
--! State machine
v.i2c_state := v_i2c_state_nxt;
--=============================================================================
--! 4) I2C SHIFT REGISTER (FOR RECEIVING & TRANSMITING)
--=============================================================================
v_shift_tx_en_pre := '0';
if ( (v_i2c_state_nxt = TX_DATA)
or (v_i2c_state_nxt = TX_DATA_ACK)
) then
v_shift_tx_en_pre := '1';
end if;
v_shift_buf_tx_init := '0';
if ( ( (r.i2c_state = RX_ADDR_ACK)
and (v_scl_re = '1')
and (not(r.shift_buf(0)) = '1')
)
or ( (r.i2c_state = TX_DATA_ACK)
and (v_scl_re = '1')
)
) then
v_shift_buf_tx_init := '1';
end if;
if (r.shift_buf /= "100000000") then
v_shift_buf_tx_en := v_shift_tx_en_pre and v_scl_fe;
else
v_shift_buf_tx_en := '0';
end if;
--! Debug register data read value
if (r.dbg_state = TX_BYTE_HI) then
v_shift_tx_val := d.dbg_dout(15 downto 8);
else
v_shift_tx_val := d.dbg_dout(7 downto 0);
end if;
if (v_shift_buf_rx_init = '1') then --! RX Init
v_shift_buf_nxt := "000000001";
elsif (v_shift_buf_tx_init = '1') then --! TX Init
v_shift_buf_nxt := v_shift_tx_val & '1';
elsif (v_shift_buf_rx_en = '1') then --! RX Shift
v_shift_buf_nxt := r.shift_buf(7 downto 0) & v_sda_in;
elsif (v_shift_buf_tx_en = '1') then --! TX Shift
v_shift_buf_nxt := r.shift_buf(7 downto 0) & '0';
else --! Hold
v_shift_buf_nxt := r.shift_buf(8 downto 0);
end if;
v.shift_buf := v_shift_buf_nxt;
UNUSED_dbg_i2c_broadcast := d.dbg_i2c_broadcast;
--! Utility signals
v_shift_rx_data_done := '0';
if ( (r.i2c_state = RX_DATA)
and (v_shift_rx_done = '1')
) then
v_shift_rx_data_done := '1';
end if;
v_shift_tx_data_done := v_shift_tx_done;
--=============================================================================
--! 5) I2C TRANSMIT BUFFER
--=============================================================================
if (v_scl_fe) then
if ( (v_i2c_state_nxt = RX_ADDR_ACK)
or (v_i2c_state_nxt = RX_ADDR_ACK)
or ( (v_shift_buf_tx_en = '1')
and (not(r.shift_buf(8)) = '1')
)
) then
v.dbg_i2c_sda_out := '1';
else
v.dbg_i2c_sda_out := '1';
end if;
end if;
--=============================================================================
--! 6) DEBUG INTERFACE STATE MACHINE
--=============================================================================
--! State transition
case (r.dbg_state) is
when RX_CMD =>
if (d.mem_burst_wr = '1') then
v_dbg_state_nxt := RX_BYTE_LO;
elsif (d.mem_burst_rd = '1') then
v_dbg_state_nxt := TX_BYTE_LO;
elsif (not(v_shift_rx_data_done) = '1') then
v_dbg_state_nxt := RX_CMD;
elsif (r.shift_buf(7) = '1') then
v_dbg_state_nxt := RX_BYTE_LO;
else
v_dbg_state_nxt := TX_BYTE_LO;
end if;
when RX_BYTE_LO =>
if ( (d.mem_burst = '1') and (d.mem_burst_end = '1') ) then
v_dbg_state_nxt := RX_CMD;
elsif (not(v_shift_rx_data_done) = '1') then
v_dbg_state_nxt := RX_BYTE_LO;
elsif ( (d.mem_burst = '1') and (not(d.mem_burst_end) = '1') ) then
if (not(d.mem_bw) = '1') then
v_dbg_state_nxt := RX_BYTE_LO;
else
v_dbg_state_nxt := RX_BYTE_HI;
end if;
elsif (not(r.dbg_bw) = '1') then
v_dbg_state_nxt := RX_CMD;
else
v_dbg_state_nxt := RX_BYTE_HI;
end if;
when RX_BYTE_HI =>
if (not(v_shift_rx_data_done) = '1') then
v_dbg_state_nxt := RX_BYTE_HI;
elsif ( (d.mem_burst_wr = '1') and (not(d.mem_burst_end) = '1') ) then
v_dbg_state_nxt := RX_BYTE_LO;
else
v_dbg_state_nxt := RX_CMD;
end if;
when TX_BYTE_LO =>
if (not(v_shift_tx_data_done) = '1') then
v_dbg_state_nxt := TX_BYTE_LO;
elsif ( (d.mem_burst = '1') and (d.mem_bw = '1') ) then
v_dbg_state_nxt := TX_BYTE_LO;
elsif ( (d.mem_burst = '1') and (not(d.mem_bw) = '1') ) then
v_dbg_state_nxt := TX_BYTE_HI;
elsif (not(r.dbg_bw) = '1') then
v_dbg_state_nxt := TX_BYTE_HI;
else
v_dbg_state_nxt := RX_CMD;
end if;
when TX_BYTE_HI =>
if (not(v_shift_rx_data_done) = '1') then
v_dbg_state_nxt := TX_BYTE_HI;
elsif (d.mem_burst = '1') then
v_dbg_state_nxt := TX_BYTE_LO;
else
v_dbg_state_nxt := RX_CMD;
end if;
when Others =>
v_dbg_state_nxt := RX_CMD;
end case;
--! State machine
v.dbg_state := v_dbg_state_nxt;
--! Utility signals
if ( (r.dbg_state = RX_CMD)
and (v_shift_rx_data_done = '1')
) then
v_cmd_valid := '1';
else
v_cmd_valid := '0';
end if;
if ( (r.dbg_state = RX_BYTE_LO)
and (v_shift_rx_data_done = '1')
) then
v_rx_lo_valid := '1';
else
v_rx_lo_valid := '0';
end if;
if ( (r.dbg_state = RX_BYTE_HI)
and (v_shift_rx_data_done = '1')
) then
v_rx_hi_valid := '1';
else
v_rx_hi_valid := '0';
end if;
--=============================================================================
--! 7) REGISTER READ/WRITE ACCESS
--=============================================================================
if (v_cmd_valid = '1') then
v.dbg_bw := r.shift_buf(6);
v.dbg_addr := r.shift_buf(5 downto 0);
elsif (d.mem_burst = '1') then
v.dbg_bw := d.mem_bw;
v.dbg_addr := MEM_DATA;
end if;
--! Debug register data input
if (v_rx_lo_valid = '1') then
v.dbg_din_lo := r.shift_buf(7 downto 0);
end if;
if (v_rx_lo_valid = '1') then
v.dbg_din_hi := x"00";
elsif (v_rx_hi_valid = '1') then
v.dbg_din_hi := r.shift_buf(7 downto 0);
end if;
v_dbg_din := r.dbg_din_hi & r.dbg_din_lo;
--! Debug register data write command
if ((d.mem_burst and d.mem_bw) = '1') then
v.dbg_wr := v_rx_lo_valid;
elsif ((d.mem_burst and not(d.mem_bw)) = '1') then
v.dbg_wr := v_rx_hi_valid;
elsif (r.dbg_bw = '1') then
v.dbg_wr := v_rx_lo_valid;
else
v.dbg_wr := v_rx_hi_valid;
end if;
--! Debug register data read command
if ((d.mem_burst and d.mem_bw) = '1') then
if ( (r.dbg_state = TX_BYTE_LO)
and (v_shift_tx_data_done = '1')
) then
v.dbg_rd := '1';
else
v.dbg_rd := '0';
end if;
elsif ((d.mem_burst and not(d.mem_bw)) = '1') then
if ( (r.dbg_state = TX_BYTE_HI)
and (v_shift_tx_data_done = '1')
) then
v.dbg_rd := '1';
else
v.dbg_rd := '0';
end if;
elsif (v_cmd_valid = '1') then
v.dbg_rd := not(r.shift_buf(7));
else
v.dbg_rd := '0';
end if;
--! drive register inputs
rin <= v;
--! drive module outputs
dbg_addr <= r.dbg_addr; --! Debug register address
dbg_din <= v_dbg_din; --! Debug register data input
dbg_i2c_sda_out <= r.dbg_i2c_sda_out; --! Debug interface: I2C SDA OUT
dbg_rd <= r.dbg_rd; --! Debug register data read
dbg_wr <= r.dbg_wr; --! Debug register data write
end process COMB;
REGS : process (dbg_clk,dbg_rst)
begin
if (dbg_rst = '1') then
r <= ( scl_buf => "11", --! SCL input buffer
sda_in_buf => "11", --! SDA input buffer
sda_in_dly => '0', --! SDA Edge detection
scl_dly => '0', --! SCL Edge detection
scl_re_dly => "00", --! Delayed SCL Rising-Edge for SDA data sampling
i2c_active_seq => '0', --! I2C Slave Active
i2c_state => RX_ADDR, --! State register/wires
shift_buf => "000000000",--! Utility signals
dbg_rd => '0', --! Utility signals
dbg_i2c_sda_out => '0', --! I2C TRANSMIT BUFFER
dbg_state => RX_CMD, --! State register/wires
dbg_addr => "000000",
dbg_din_lo => "00000000",
dbg_din_hi => "00000000",
dbg_bw => '0', --! Utility signals
dbg_wr => '0' --! Debug register data write command
);
elsif rising_edge(dbg_clk) then
r <= rin;
end if;
end process REGS;
sync_cell_i2c_scl : fmsp_sync_cell
port map(
clk => dbg_clk,
rst => dbg_rst,
data_in => not(dbg_i2c_scl),
data_out => d.scl_sync_n
);
sync_cell_i2c_sda : fmsp_sync_cell
port map(
clk => dbg_clk,
rst => dbg_rst,
data_in => not(dbg_i2c_sda_in),
data_out => d.sda_in_sync_n
);
end RTL;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Mon Feb 13 12:47:50 2017
-- Host : WK117 running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- C:/Users/aholzer/Documents/new/Arty-BSD/src/bd/system/ip/system_axi_gpio_led_0/system_axi_gpio_led_0_sim_netlist.vhdl
-- Design : system_axi_gpio_led_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35ticsg324-1L
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_address_decoder is
port (
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_aclk : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
is_read : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
is_write_reg : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
\bus2ip_addr_i_reg[8]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC;
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
\Dual.gpio_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
rst_reg : in STD_LOGIC;
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
start2 : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_address_decoder : entity is "address_decoder";
end system_axi_gpio_led_0_address_decoder;
architecture STRUCTURE of system_axi_gpio_led_0_address_decoder is
signal \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\ : STD_LOGIC;
signal \^mem_decode_gen[0].cs_out_i_reg[0]_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[10]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[11]_i_1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[4]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[5]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[6]_i_1\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[7]_i_1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[8]_i_1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio2_Data_Out[9]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[0]_i_2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[2]_i_1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \Dual.gpio_Data_Out[3]_i_1\ : label is "soft_lutpair3";
begin
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ <= \^mem_decode_gen[0].cs_out_i_reg[0]_0\;
s_axi_arready <= \^s_axi_arready\;
s_axi_wready <= \^s_axi_wready\;
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i[20]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(11),
I1 => \Dual.gpio2_Data_In_reg[0]\(11),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(0)
);
\Dual.READ_REG2_GEN[10].GPIO2_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(1),
I1 => \Dual.gpio2_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(10)
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i[31]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => gpio_xferAck_Reg,
I2 => bus2ip_rnw_i_reg,
I3 => GPIO_xferAck_i,
O => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i[31]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(0),
I1 => \Dual.gpio2_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(11)
);
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i[21]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(10),
I1 => \Dual.gpio2_Data_In_reg[0]\(10),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(1)
);
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i[22]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(9),
I1 => \Dual.gpio2_Data_In_reg[0]\(9),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(2)
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i[23]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(8),
I1 => \Dual.gpio2_Data_In_reg[0]\(8),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(3)
);
\Dual.READ_REG2_GEN[4].GPIO2_DBus_i[24]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(7),
I1 => \Dual.gpio2_Data_In_reg[0]\(7),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(4)
);
\Dual.READ_REG2_GEN[5].GPIO2_DBus_i[25]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(6),
I1 => \Dual.gpio2_Data_In_reg[0]\(6),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(5)
);
\Dual.READ_REG2_GEN[6].GPIO2_DBus_i[26]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(5),
I1 => \Dual.gpio2_Data_In_reg[0]\(5),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(6)
);
\Dual.READ_REG2_GEN[7].GPIO2_DBus_i[27]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(4),
I1 => \Dual.gpio2_Data_In_reg[0]\(4),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(7)
);
\Dual.READ_REG2_GEN[8].GPIO2_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(3),
I1 => \Dual.gpio2_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(8)
);
\Dual.READ_REG2_GEN[9].GPIO2_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A0000000C000000"
)
port map (
I0 => gpio2_io_t(2),
I1 => \Dual.gpio2_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(1),
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg2_In(9)
);
\Dual.READ_REG_GEN[0].GPIO_DBus_i[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(3),
I1 => \Dual.gpio_Data_In_reg[0]\(3),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(0)
);
\Dual.READ_REG_GEN[1].GPIO_DBus_i[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(2),
I1 => \Dual.gpio_Data_In_reg[0]\(2),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(1)
);
\Dual.READ_REG_GEN[2].GPIO_DBus_i[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(1),
I1 => \Dual.gpio_Data_In_reg[0]\(1),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(2)
);
\Dual.READ_REG_GEN[3].GPIO_DBus_i[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"000A0000000C0000"
)
port map (
I0 => gpio_io_t(0),
I1 => \Dual.gpio_Data_In_reg[0]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => \bus2ip_addr_i_reg[8]\(0),
O => Read_Reg_In(3)
);
\Dual.gpio2_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00001000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio2_Data_Out_reg[0]\(0)
);
\Dual.gpio2_Data_Out[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(1),
O => D(1)
);
\Dual.gpio2_Data_Out[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(0),
O => D(0)
);
\Dual.gpio2_Data_Out[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(7),
O => D(7)
);
\Dual.gpio2_Data_Out[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(6),
O => D(6)
);
\Dual.gpio2_Data_Out[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(5),
O => D(5)
);
\Dual.gpio2_Data_Out[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(4),
O => D(4)
);
\Dual.gpio2_Data_Out[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(3),
O => D(3)
);
\Dual.gpio2_Data_Out[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"D0"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => s_axi_wdata(2),
O => D(2)
);
\Dual.gpio2_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF10000000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio2_OE_reg[0]\(0)
);
\Dual.gpio_Data_Out[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00000100"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => \bus2ip_addr_i_reg[8]\(0),
I5 => rst_reg,
O => \Dual.gpio_Data_Out_reg[0]\(0)
);
\Dual.gpio_Data_Out[0]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(11),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(3),
O => D(11)
);
\Dual.gpio_Data_Out[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(10),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(2),
O => D(10)
);
\Dual.gpio_Data_Out[2]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(9),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(1),
O => D(9)
);
\Dual.gpio_Data_Out[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"BA8A"
)
port map (
I0 => s_axi_wdata(8),
I1 => \bus2ip_addr_i_reg[8]\(1),
I2 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I3 => s_axi_wdata(0),
O => D(8)
);
\Dual.gpio_OE[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00040000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \bus2ip_addr_i_reg[8]\(0),
I2 => \bus2ip_addr_i_reg[8]\(2),
I3 => \bus2ip_addr_i_reg[8]\(1),
I4 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I5 => rst_reg,
O => E(0)
);
\MEM_DECODE_GEN[0].cs_out_i[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"000E0000"
)
port map (
I0 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I1 => start2,
I2 => \^s_axi_wready\,
I3 => \^s_axi_arready\,
I4 => s_axi_aresetn,
O => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\
);
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \MEM_DECODE_GEN[0].cs_out_i[0]_i_1_n_0\,
Q => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
R => '0'
);
\ip2bus_data_i_D1[20]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(11),
O => \ip2bus_data_i_D1_reg[20]\(11)
);
\ip2bus_data_i_D1[21]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(10),
O => \ip2bus_data_i_D1_reg[20]\(10)
);
\ip2bus_data_i_D1[22]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(9),
O => \ip2bus_data_i_D1_reg[20]\(9)
);
\ip2bus_data_i_D1[23]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(8),
O => \ip2bus_data_i_D1_reg[20]\(8)
);
\ip2bus_data_i_D1[24]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(7),
O => \ip2bus_data_i_D1_reg[20]\(7)
);
\ip2bus_data_i_D1[25]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(6),
O => \ip2bus_data_i_D1_reg[20]\(6)
);
\ip2bus_data_i_D1[26]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(5),
O => \ip2bus_data_i_D1_reg[20]\(5)
);
\ip2bus_data_i_D1[27]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFF70000"
)
port map (
I0 => bus2ip_rnw_i_reg,
I1 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \bus2ip_addr_i_reg[8]\(2),
I4 => GPIO2_DBus_i(4),
O => \ip2bus_data_i_D1_reg[20]\(4)
);
\ip2bus_data_i_D1[28]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(3),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(3),
O => \ip2bus_data_i_D1_reg[20]\(3)
);
\ip2bus_data_i_D1[29]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(2),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(2),
O => \ip2bus_data_i_D1_reg[20]\(2)
);
\ip2bus_data_i_D1[30]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(1),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(1),
O => \ip2bus_data_i_D1_reg[20]\(1)
);
\ip2bus_data_i_D1[31]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"ABAAAAAAA8AAAAAA"
)
port map (
I0 => GPIO2_DBus_i(0),
I1 => \bus2ip_addr_i_reg[8]\(2),
I2 => \bus2ip_addr_i_reg[8]\(1),
I3 => \^mem_decode_gen[0].cs_out_i_reg[0]_0\,
I4 => bus2ip_rnw_i_reg,
I5 => GPIO_DBus_i(0),
O => \ip2bus_data_i_D1_reg[20]\(0)
);
s_axi_arready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_read,
I5 => ip2bus_rdack_i_D1,
O => \^s_axi_arready\
);
s_axi_wready_INST_0: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00020000"
)
port map (
I0 => Q(3),
I1 => Q(2),
I2 => Q(1),
I3 => Q(0),
I4 => is_write_reg,
I5 => ip2bus_wrack_i_D1,
O => \^s_axi_wready\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_cdc_sync is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_cdc_sync : entity is "cdc_sync";
end system_axi_gpio_led_0_cdc_sync;
architecture STRUCTURE of system_axi_gpio_led_0_cdc_sync is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \system_axi_gpio_led_0_cdc_sync__parameterized0\ is
port (
scndry_vect_out : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \system_axi_gpio_led_0_cdc_sync__parameterized0\ : entity is "cdc_sync";
end \system_axi_gpio_led_0_cdc_sync__parameterized0\;
architecture STRUCTURE of \system_axi_gpio_led_0_cdc_sync__parameterized0\ is
signal s_level_out_bus_d1_cdc_to_0 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_1 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_10 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_11 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_2 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_3 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_4 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_5 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_6 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_7 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_8 : STD_LOGIC;
signal s_level_out_bus_d1_cdc_to_9 : STD_LOGIC;
signal s_level_out_bus_d2_0 : STD_LOGIC;
signal s_level_out_bus_d2_1 : STD_LOGIC;
signal s_level_out_bus_d2_10 : STD_LOGIC;
signal s_level_out_bus_d2_11 : STD_LOGIC;
signal s_level_out_bus_d2_2 : STD_LOGIC;
signal s_level_out_bus_d2_3 : STD_LOGIC;
signal s_level_out_bus_d2_4 : STD_LOGIC;
signal s_level_out_bus_d2_5 : STD_LOGIC;
signal s_level_out_bus_d2_6 : STD_LOGIC;
signal s_level_out_bus_d2_7 : STD_LOGIC;
signal s_level_out_bus_d2_8 : STD_LOGIC;
signal s_level_out_bus_d2_9 : STD_LOGIC;
signal s_level_out_bus_d3_0 : STD_LOGIC;
signal s_level_out_bus_d3_1 : STD_LOGIC;
signal s_level_out_bus_d3_10 : STD_LOGIC;
signal s_level_out_bus_d3_11 : STD_LOGIC;
signal s_level_out_bus_d3_2 : STD_LOGIC;
signal s_level_out_bus_d3_3 : STD_LOGIC;
signal s_level_out_bus_d3_4 : STD_LOGIC;
signal s_level_out_bus_d3_5 : STD_LOGIC;
signal s_level_out_bus_d3_6 : STD_LOGIC;
signal s_level_out_bus_d3_7 : STD_LOGIC;
signal s_level_out_bus_d3_8 : STD_LOGIC;
signal s_level_out_bus_d3_9 : STD_LOGIC;
attribute ASYNC_REG : boolean;
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM : string;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type : string;
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
attribute ASYNC_REG of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is std.standard.true;
attribute XILINX_LEGACY_PRIM of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "FDR";
attribute box_type of \GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\ : label is "PRIMITIVE";
begin
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_0,
Q => s_level_out_bus_d2_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_10,
Q => s_level_out_bus_d2_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_11,
Q => s_level_out_bus_d2_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_1,
Q => s_level_out_bus_d2_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_2,
Q => s_level_out_bus_d2_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_3,
Q => s_level_out_bus_d2_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_4,
Q => s_level_out_bus_d2_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_5,
Q => s_level_out_bus_d2_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_6,
Q => s_level_out_bus_d2_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_7,
Q => s_level_out_bus_d2_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_8,
Q => s_level_out_bus_d2_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d2[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d2\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d1_cdc_to_9,
Q => s_level_out_bus_d2_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_0,
Q => s_level_out_bus_d3_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_10,
Q => s_level_out_bus_d3_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_11,
Q => s_level_out_bus_d3_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_1,
Q => s_level_out_bus_d3_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_2,
Q => s_level_out_bus_d3_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_3,
Q => s_level_out_bus_d3_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_4,
Q => s_level_out_bus_d3_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_5,
Q => s_level_out_bus_d3_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_6,
Q => s_level_out_bus_d3_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_7,
Q => s_level_out_bus_d3_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_8,
Q => s_level_out_bus_d3_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d3[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d3\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d2_9,
Q => s_level_out_bus_d3_9,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[0].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_0,
Q => scndry_vect_out(0),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[10].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_10,
Q => scndry_vect_out(10),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[11].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_11,
Q => scndry_vect_out(11),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[1].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_1,
Q => scndry_vect_out(1),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[2].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_2,
Q => scndry_vect_out(2),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[3].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_3,
Q => scndry_vect_out(3),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[4].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_4,
Q => scndry_vect_out(4),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[5].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_5,
Q => scndry_vect_out(5),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[6].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_6,
Q => scndry_vect_out(6),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[7].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_7,
Q => scndry_vect_out(7),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[8].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_8,
Q => scndry_vect_out(8),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_CROSS_PLEVEL_IN2SCNDRY_bus_d4[9].CROSS2_PLEVEL_IN2SCNDRY_s_level_out_bus_d4\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_level_out_bus_d3_9,
Q => scndry_vect_out(9),
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[0].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(0),
Q => s_level_out_bus_d1_cdc_to_0,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[10].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(10),
Q => s_level_out_bus_d1_cdc_to_10,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[11].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(11),
Q => s_level_out_bus_d1_cdc_to_11,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[1].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(1),
Q => s_level_out_bus_d1_cdc_to_1,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[2].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(2),
Q => s_level_out_bus_d1_cdc_to_2,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[3].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(3),
Q => s_level_out_bus_d1_cdc_to_3,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[4].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(4),
Q => s_level_out_bus_d1_cdc_to_4,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[5].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(5),
Q => s_level_out_bus_d1_cdc_to_5,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[6].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(6),
Q => s_level_out_bus_d1_cdc_to_6,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[7].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(7),
Q => s_level_out_bus_d1_cdc_to_7,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[8].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(8),
Q => s_level_out_bus_d1_cdc_to_8,
R => '0'
);
\GENERATE_LEVEL_P_S_CDC.MULTI_BIT.FOR_IN_cdc_to[9].CROSS2_PLEVEL_IN2SCNDRY_IN_cdc_to\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i(9),
Q => s_level_out_bus_d1_cdc_to_9,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_GPIO_Core is
port (
GPIO2_DBus_i : out STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : out STD_LOGIC_VECTOR ( 3 downto 0 );
GPIO_xferAck_i : out STD_LOGIC;
gpio_xferAck_Reg : out STD_LOGIC;
ip2bus_rdack_i : out STD_LOGIC;
ip2bus_wrack_i_D1_reg : out STD_LOGIC;
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 );
Q : out STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
Read_Reg_Rst : in STD_LOGIC;
Read_Reg2_In : in STD_LOGIC_VECTOR ( 0 to 11 );
s_axi_aclk : in STD_LOGIC;
Read_Reg_In : in STD_LOGIC_VECTOR ( 0 to 3 );
SS : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw : in STD_LOGIC;
bus2ip_cs : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 11 downto 0 );
bus2ip_rnw_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_0 : in STD_LOGIC_VECTOR ( 0 to 0 );
bus2ip_rnw_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_GPIO_Core : entity is "GPIO_Core";
end system_axi_gpio_led_0_GPIO_Core;
architecture STRUCTURE of system_axi_gpio_led_0_GPIO_Core is
signal \^gpio_xferack_i\ : STD_LOGIC;
signal gpio2_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 11 );
signal gpio_io_i_d2 : STD_LOGIC_VECTOR ( 0 to 3 );
signal \^gpio_xferack_reg\ : STD_LOGIC;
signal iGPIO_xferAck : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of iGPIO_xferAck_i_1 : label is "soft_lutpair9";
attribute SOFT_HLUTNM of ip2bus_rdack_i_D1_i_1 : label is "soft_lutpair9";
begin
GPIO_xferAck_i <= \^gpio_xferack_i\;
gpio_xferAck_Reg <= \^gpio_xferack_reg\;
\Dual.INPUT_DOUBLE_REGS4\: entity work.system_axi_gpio_led_0_cdc_sync
port map (
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(3) => gpio_io_i_d2(0),
scndry_vect_out(2) => gpio_io_i_d2(1),
scndry_vect_out(1) => gpio_io_i_d2(2),
scndry_vect_out(0) => gpio_io_i_d2(3)
);
\Dual.INPUT_DOUBLE_REGS5\: entity work.\system_axi_gpio_led_0_cdc_sync__parameterized0\
port map (
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
s_axi_aclk => s_axi_aclk,
scndry_vect_out(11) => gpio2_io_i_d2(0),
scndry_vect_out(10) => gpio2_io_i_d2(1),
scndry_vect_out(9) => gpio2_io_i_d2(2),
scndry_vect_out(8) => gpio2_io_i_d2(3),
scndry_vect_out(7) => gpio2_io_i_d2(4),
scndry_vect_out(6) => gpio2_io_i_d2(5),
scndry_vect_out(5) => gpio2_io_i_d2(6),
scndry_vect_out(4) => gpio2_io_i_d2(7),
scndry_vect_out(3) => gpio2_io_i_d2(8),
scndry_vect_out(2) => gpio2_io_i_d2(9),
scndry_vect_out(1) => gpio2_io_i_d2(10),
scndry_vect_out(0) => gpio2_io_i_d2(11)
);
\Dual.READ_REG2_GEN[0].GPIO2_DBus_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(0),
Q => GPIO2_DBus_i(11),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[10].GPIO2_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(10),
Q => GPIO2_DBus_i(1),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[11].GPIO2_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(11),
Q => GPIO2_DBus_i(0),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[1].GPIO2_DBus_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(1),
Q => GPIO2_DBus_i(10),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[2].GPIO2_DBus_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(2),
Q => GPIO2_DBus_i(9),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[3].GPIO2_DBus_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(3),
Q => GPIO2_DBus_i(8),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[4].GPIO2_DBus_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(4),
Q => GPIO2_DBus_i(7),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[5].GPIO2_DBus_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(5),
Q => GPIO2_DBus_i(6),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[6].GPIO2_DBus_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(6),
Q => GPIO2_DBus_i(5),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[7].GPIO2_DBus_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(7),
Q => GPIO2_DBus_i(4),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[8].GPIO2_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(8),
Q => GPIO2_DBus_i(3),
R => Read_Reg_Rst
);
\Dual.READ_REG2_GEN[9].GPIO2_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg2_In(9),
Q => GPIO2_DBus_i(2),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(0),
Q => GPIO_DBus_i(3),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[1].GPIO_DBus_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(1),
Q => GPIO_DBus_i(2),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[2].GPIO_DBus_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(2),
Q => GPIO_DBus_i(1),
R => Read_Reg_Rst
);
\Dual.READ_REG_GEN[3].GPIO_DBus_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => Read_Reg_In(3),
Q => GPIO_DBus_i(0),
R => Read_Reg_Rst
);
\Dual.gpio2_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(0),
Q => Q(11),
R => '0'
);
\Dual.gpio2_Data_In_reg[10]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(10),
Q => Q(1),
R => '0'
);
\Dual.gpio2_Data_In_reg[11]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(11),
Q => Q(0),
R => '0'
);
\Dual.gpio2_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(1),
Q => Q(10),
R => '0'
);
\Dual.gpio2_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(2),
Q => Q(9),
R => '0'
);
\Dual.gpio2_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(3),
Q => Q(8),
R => '0'
);
\Dual.gpio2_Data_In_reg[4]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(4),
Q => Q(7),
R => '0'
);
\Dual.gpio2_Data_In_reg[5]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(5),
Q => Q(6),
R => '0'
);
\Dual.gpio2_Data_In_reg[6]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(6),
Q => Q(5),
R => '0'
);
\Dual.gpio2_Data_In_reg[7]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(7),
Q => Q(4),
R => '0'
);
\Dual.gpio2_Data_In_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(8),
Q => Q(3),
R => '0'
);
\Dual.gpio2_Data_In_reg[9]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio2_io_i_d2(9),
Q => Q(2),
R => '0'
);
\Dual.gpio2_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(11),
Q => gpio2_io_o(11),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(1),
Q => gpio2_io_o(1),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(0),
Q => gpio2_io_o(0),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(10),
Q => gpio2_io_o(10),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(9),
Q => gpio2_io_o(9),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(8),
Q => gpio2_io_o(8),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(7),
Q => gpio2_io_o(7),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(6),
Q => gpio2_io_o(6),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(5),
Q => gpio2_io_o(5),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(4),
Q => gpio2_io_o(4),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(3),
Q => gpio2_io_o(3),
R => SS(0)
);
\Dual.gpio2_Data_Out_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_0(0),
D => D(2),
Q => gpio2_io_o(2),
R => SS(0)
);
\Dual.gpio2_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(11),
Q => gpio2_io_t(11),
S => SS(0)
);
\Dual.gpio2_OE_reg[10]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(1),
Q => gpio2_io_t(1),
S => SS(0)
);
\Dual.gpio2_OE_reg[11]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(0),
Q => gpio2_io_t(0),
S => SS(0)
);
\Dual.gpio2_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(10),
Q => gpio2_io_t(10),
S => SS(0)
);
\Dual.gpio2_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(9),
Q => gpio2_io_t(9),
S => SS(0)
);
\Dual.gpio2_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(8),
Q => gpio2_io_t(8),
S => SS(0)
);
\Dual.gpio2_OE_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(7),
Q => gpio2_io_t(7),
S => SS(0)
);
\Dual.gpio2_OE_reg[5]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(6),
Q => gpio2_io_t(6),
S => SS(0)
);
\Dual.gpio2_OE_reg[6]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(5),
Q => gpio2_io_t(5),
S => SS(0)
);
\Dual.gpio2_OE_reg[7]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(4),
Q => gpio2_io_t(4),
S => SS(0)
);
\Dual.gpio2_OE_reg[8]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(3),
Q => gpio2_io_t(3),
S => SS(0)
);
\Dual.gpio2_OE_reg[9]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg_1(0),
D => D(2),
Q => gpio2_io_t(2),
S => SS(0)
);
\Dual.gpio_Data_In_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(0),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(3),
R => '0'
);
\Dual.gpio_Data_In_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(1),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(2),
R => '0'
);
\Dual.gpio_Data_In_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(2),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(1),
R => '0'
);
\Dual.gpio_Data_In_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_io_i_d2(3),
Q => \Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(0),
R => '0'
);
\Dual.gpio_Data_Out_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(11),
Q => gpio_io_o(3),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(10),
Q => gpio_io_o(2),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(9),
Q => gpio_io_o(1),
R => SS(0)
);
\Dual.gpio_Data_Out_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => E(0),
D => D(8),
Q => gpio_io_o(0),
R => SS(0)
);
\Dual.gpio_OE_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(11),
Q => gpio_io_t(3),
S => SS(0)
);
\Dual.gpio_OE_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(10),
Q => gpio_io_t(2),
S => SS(0)
);
\Dual.gpio_OE_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(9),
Q => gpio_io_t(1),
S => SS(0)
);
\Dual.gpio_OE_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => s_axi_aclk,
CE => bus2ip_rnw_i_reg(0),
D => D(8),
Q => gpio_io_t(0),
S => SS(0)
);
gpio_xferAck_Reg_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \^gpio_xferack_i\,
Q => \^gpio_xferack_reg\,
R => SS(0)
);
iGPIO_xferAck_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_cs,
I2 => \^gpio_xferack_reg\,
O => iGPIO_xferAck
);
iGPIO_xferAck_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => iGPIO_xferAck,
Q => \^gpio_xferack_i\,
R => SS(0)
);
ip2bus_rdack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_rdack_i
);
ip2bus_wrack_i_D1_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^gpio_xferack_i\,
I1 => bus2ip_rnw,
O => ip2bus_wrack_i_D1_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_slave_attachment is
port (
bus2ip_rnw_i_reg_0 : out STD_LOGIC;
\ip2bus_data_i_D1_reg[31]\ : out STD_LOGIC;
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[20]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_slave_attachment : entity is "slave_attachment";
end system_axi_gpio_led_0_slave_attachment;
architecture STRUCTURE of system_axi_gpio_led_0_slave_attachment is
signal \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal bus2ip_addr : STD_LOGIC_VECTOR ( 0 to 6 );
signal \bus2ip_addr_i[2]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[3]_i_1_n_0\ : STD_LOGIC;
signal \bus2ip_addr_i[8]_i_1_n_0\ : STD_LOGIC;
signal bus2ip_rnw_i06_out : STD_LOGIC;
signal \^bus2ip_rnw_i_reg_0\ : STD_LOGIC;
signal clear : STD_LOGIC;
signal \^ip2bus_data_i_d1_reg[31]\ : STD_LOGIC;
signal is_read : STD_LOGIC;
signal is_read_i_1_n_0 : STD_LOGIC;
signal is_write : STD_LOGIC;
signal is_write_i_1_n_0 : STD_LOGIC;
signal is_write_reg_n_0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_arready\ : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_axi_bvalid_i_i_1_n_0 : STD_LOGIC;
signal s_axi_rdata_i : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal s_axi_rvalid_i_i_1_n_0 : STD_LOGIC;
signal \^s_axi_wready\ : STD_LOGIC;
signal start2 : STD_LOGIC;
signal start2_i_1_n_0 : STD_LOGIC;
signal state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \state[0]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_1_n_0\ : STD_LOGIC;
signal \state[1]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \bus2ip_addr_i[3]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of bus2ip_rnw_i_i_1 : label is "soft_lutpair6";
begin
bus2ip_rnw_i_reg_0 <= \^bus2ip_rnw_i_reg_0\;
\ip2bus_data_i_D1_reg[31]\ <= \^ip2bus_data_i_d1_reg[31]\;
s_axi_arready <= \^s_axi_arready\;
s_axi_bvalid <= \^s_axi_bvalid\;
s_axi_rvalid <= \^s_axi_rvalid\;
s_axi_wready <= \^s_axi_wready\;
\INCLUDE_DPHASE_TIMER.dpto_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
O => plusOp(0)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
O => plusOp(1)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
O => plusOp(2)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => state(1),
I1 => state(0),
O => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
I1 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
I2 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
I3 => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
O => plusOp(3)
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(0),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(0),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(1),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(1),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(2),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(2),
R => clear
);
\INCLUDE_DPHASE_TIMER.dpto_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => plusOp(3),
Q => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3),
R => clear
);
I_DECODER: entity work.system_axi_gpio_led_0_address_decoder
port map (
D(11 downto 0) => D(11 downto 0),
\Dual.gpio2_Data_In_reg[0]\(11 downto 0) => \Dual.gpio2_Data_In_reg[0]\(11 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_Data_In_reg[0]\(3 downto 0) => Q(3 downto 0),
\Dual.gpio_Data_Out_reg[0]\(0) => \Dual.gpio_Data_Out_reg[0]\(0),
E(0) => E(0),
GPIO2_DBus_i(11 downto 0) => GPIO2_DBus_i(11 downto 0),
GPIO_DBus_i(3 downto 0) => GPIO_DBus_i(3 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]_0\ => \MEM_DECODE_GEN[0].cs_out_i_reg[0]\,
Q(3 downto 0) => \INCLUDE_DPHASE_TIMER.dpto_cnt_reg__0\(3 downto 0),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
\bus2ip_addr_i_reg[8]\(2) => bus2ip_addr(0),
\bus2ip_addr_i_reg[8]\(1) => bus2ip_addr(5),
\bus2ip_addr_i_reg[8]\(0) => bus2ip_addr(6),
bus2ip_rnw_i_reg => \^ip2bus_data_i_d1_reg[31]\,
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => \ip2bus_data_i_D1_reg[20]\(11 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
is_read => is_read,
is_write_reg => is_write_reg_n_0,
rst_reg => \^bus2ip_rnw_i_reg_0\,
s_axi_aclk => s_axi_aclk,
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => \^s_axi_arready\,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => \^s_axi_wready\,
start2 => start2
);
\bus2ip_addr_i[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(0),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(0),
O => \bus2ip_addr_i[2]_i_1_n_0\
);
\bus2ip_addr_i[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(1),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(1),
O => \bus2ip_addr_i[3]_i_1_n_0\
);
\bus2ip_addr_i[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"ABAAA8AA"
)
port map (
I0 => s_axi_awaddr(2),
I1 => state(1),
I2 => state(0),
I3 => s_axi_arvalid,
I4 => s_axi_araddr(2),
O => \bus2ip_addr_i[8]_i_1_n_0\
);
\bus2ip_addr_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[2]_i_1_n_0\,
Q => bus2ip_addr(6),
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[3]_i_1_n_0\,
Q => bus2ip_addr(5),
R => \^bus2ip_rnw_i_reg_0\
);
\bus2ip_addr_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => \bus2ip_addr_i[8]_i_1_n_0\,
Q => bus2ip_addr(0),
R => \^bus2ip_rnw_i_reg_0\
);
bus2ip_rnw_i_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => s_axi_arvalid,
I1 => state(0),
I2 => state(1),
O => bus2ip_rnw_i06_out
);
bus2ip_rnw_i_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => start2_i_1_n_0,
D => bus2ip_rnw_i06_out,
Q => \^ip2bus_data_i_d1_reg[31]\,
R => \^bus2ip_rnw_i_reg_0\
);
is_read_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"3FFA000A"
)
port map (
I0 => s_axi_arvalid,
I1 => \state[1]_i_2_n_0\,
I2 => state(1),
I3 => state(0),
I4 => is_read,
O => is_read_i_1_n_0
);
is_read_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_read_i_1_n_0,
Q => is_read,
R => \^bus2ip_rnw_i_reg_0\
);
is_write_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"1000FFFF10000000"
)
port map (
I0 => state(1),
I1 => s_axi_arvalid,
I2 => s_axi_wvalid,
I3 => s_axi_awvalid,
I4 => is_write,
I5 => is_write_reg_n_0,
O => is_write_i_1_n_0
);
is_write_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"F88800000000FFFF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
I4 => state(1),
I5 => state(0),
O => is_write
);
is_write_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => is_write_i_1_n_0,
Q => is_write_reg_n_0,
R => \^bus2ip_rnw_i_reg_0\
);
rst_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_axi_aresetn,
O => p_1_in
);
rst_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => p_1_in,
Q => \^bus2ip_rnw_i_reg_0\,
R => '0'
);
s_axi_bvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_wready\,
I1 => state(1),
I2 => state(0),
I3 => s_axi_bready,
I4 => \^s_axi_bvalid\,
O => s_axi_bvalid_i_i_1_n_0
);
s_axi_bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_bvalid_i_i_1_n_0,
Q => \^s_axi_bvalid\,
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i[11]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => state(0),
I1 => state(1),
O => s_axi_rdata_i
);
\s_axi_rdata_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(0),
Q => s_axi_rdata(0),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(10),
Q => s_axi_rdata(10),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(11),
Q => s_axi_rdata(11),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(1),
Q => s_axi_rdata(1),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(2),
Q => s_axi_rdata(2),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(3),
Q => s_axi_rdata(3),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(4),
Q => s_axi_rdata(4),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(5),
Q => s_axi_rdata(5),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(6),
Q => s_axi_rdata(6),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(7),
Q => s_axi_rdata(7),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(8),
Q => s_axi_rdata(8),
R => \^bus2ip_rnw_i_reg_0\
);
\s_axi_rdata_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => s_axi_rdata_i,
D => \ip2bus_data_i_D1_reg[20]_0\(9),
Q => s_axi_rdata(9),
R => \^bus2ip_rnw_i_reg_0\
);
s_axi_rvalid_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"08FF0808"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(0),
I2 => state(1),
I3 => s_axi_rready,
I4 => \^s_axi_rvalid\,
O => s_axi_rvalid_i_i_1_n_0
);
s_axi_rvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_axi_aclk,
CE => '1',
D => s_axi_rvalid_i_i_1_n_0,
Q => \^s_axi_rvalid\,
R => \^bus2ip_rnw_i_reg_0\
);
start2_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"000000F8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
I2 => s_axi_arvalid,
I3 => state(0),
I4 => state(1),
O => start2_i_1_n_0
);
start2_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => start2_i_1_n_0,
Q => start2,
R => \^bus2ip_rnw_i_reg_0\
);
\state[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"0FFFAACC"
)
port map (
I0 => \^s_axi_wready\,
I1 => s_axi_arvalid,
I2 => \state[1]_i_2_n_0\,
I3 => state(1),
I4 => state(0),
O => \state[0]_i_1_n_0\
);
\state[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"2E2E2E2ECCCCFFCC"
)
port map (
I0 => \^s_axi_arready\,
I1 => state(1),
I2 => \state[1]_i_2_n_0\,
I3 => \state[1]_i_3_n_0\,
I4 => s_axi_arvalid,
I5 => state(0),
O => \state[1]_i_1_n_0\
);
\state[1]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \state[1]_i_2_n_0\
);
\state[1]_i_3\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_awvalid,
I1 => s_axi_wvalid,
O => \state[1]_i_3_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[0]_i_1_n_0\,
Q => state(0),
R => \^bus2ip_rnw_i_reg_0\
);
\state_reg[1]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => \state[1]_i_1_n_0\,
Q => state(1),
R => \^bus2ip_rnw_i_reg_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_axi_lite_ipif is
port (
bus2ip_reset : out STD_LOGIC;
bus2ip_rnw : out STD_LOGIC;
bus2ip_cs : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 11 downto 0 );
\ip2bus_data_i_D1_reg[20]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
Read_Reg_In : out STD_LOGIC_VECTOR ( 0 to 3 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg2_In : out STD_LOGIC_VECTOR ( 0 to 11 );
\Dual.gpio2_OE_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\Dual.gpio2_Data_Out_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
Read_Reg_Rst : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aclk : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
ip2bus_rdack_i_D1 : in STD_LOGIC;
ip2bus_wrack_i_D1 : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO2_DBus_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
GPIO_DBus_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : in STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_t : in STD_LOGIC_VECTOR ( 11 downto 0 );
\Dual.gpio2_Data_In_reg[0]\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_aresetn : in STD_LOGIC;
gpio_xferAck_Reg : in STD_LOGIC;
GPIO_xferAck_i : in STD_LOGIC;
\ip2bus_data_i_D1_reg[20]_0\ : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_axi_lite_ipif : entity is "axi_lite_ipif";
end system_axi_gpio_led_0_axi_lite_ipif;
architecture STRUCTURE of system_axi_gpio_led_0_axi_lite_ipif is
begin
I_SLAVE_ATTACHMENT: entity work.system_axi_gpio_led_0_slave_attachment
port map (
D(11 downto 0) => D(11 downto 0),
\Dual.gpio2_Data_In_reg[0]\(11 downto 0) => \Dual.gpio2_Data_In_reg[0]\(11 downto 0),
\Dual.gpio2_Data_Out_reg[0]\(0) => \Dual.gpio2_Data_Out_reg[0]\(0),
\Dual.gpio2_OE_reg[0]\(0) => \Dual.gpio2_OE_reg[0]\(0),
\Dual.gpio_Data_Out_reg[0]\(0) => \Dual.gpio_Data_Out_reg[0]\(0),
E(0) => E(0),
GPIO2_DBus_i(11 downto 0) => GPIO2_DBus_i(11 downto 0),
GPIO_DBus_i(3 downto 0) => GPIO_DBus_i(3 downto 0),
GPIO_xferAck_i => GPIO_xferAck_i,
\MEM_DECODE_GEN[0].cs_out_i_reg[0]\ => bus2ip_cs,
Q(3 downto 0) => Q(3 downto 0),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_rnw_i_reg_0 => bus2ip_reset,
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => \ip2bus_data_i_D1_reg[20]\(11 downto 0),
\ip2bus_data_i_D1_reg[20]_0\(11 downto 0) => \ip2bus_data_i_D1_reg[20]_0\(11 downto 0),
\ip2bus_data_i_D1_reg[31]\ => bus2ip_rnw,
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2 downto 0) => s_axi_araddr(2 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2 downto 0) => s_axi_awaddr(2 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(11 downto 0) => s_axi_rdata(11 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0_axi_gpio is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
ip2intc_irpt : out STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of system_axi_gpio_led_0_axi_gpio : entity is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 12;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 4;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of system_axi_gpio_led_0_axi_gpio : entity is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of system_axi_gpio_led_0_axi_gpio : entity is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of system_axi_gpio_led_0_axi_gpio : entity is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of system_axi_gpio_led_0_axi_gpio : entity is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of system_axi_gpio_led_0_axi_gpio : entity is -1;
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of system_axi_gpio_led_0_axi_gpio : entity is "axi_gpio";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_led_0_axi_gpio : entity is "yes";
attribute ip_group : string;
attribute ip_group of system_axi_gpio_led_0_axi_gpio : entity is "LOGICORE";
end system_axi_gpio_led_0_axi_gpio;
architecture STRUCTURE of system_axi_gpio_led_0_axi_gpio is
signal \<const0>\ : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_11 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_12 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_13 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_14 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_15 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_16 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_17 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_18 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_35 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_36 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_49 : STD_LOGIC;
signal AXI_LITE_IPIF_I_n_50 : STD_LOGIC;
signal GPIO2_DBus_i : STD_LOGIC_VECTOR ( 20 to 31 );
signal GPIO_DBus : STD_LOGIC_VECTOR ( 11 downto 0 );
signal GPIO_DBus_i : STD_LOGIC_VECTOR ( 28 to 31 );
signal GPIO_xferAck_i : STD_LOGIC;
signal Read_Reg2_In : STD_LOGIC_VECTOR ( 0 to 11 );
signal Read_Reg_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal Read_Reg_Rst : STD_LOGIC;
signal bus2ip_cs : STD_LOGIC;
signal bus2ip_reset : STD_LOGIC;
signal bus2ip_rnw : STD_LOGIC;
signal gpio2_Data_In : STD_LOGIC_VECTOR ( 0 to 11 );
signal \^gpio2_io_t\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal gpio_Data_In : STD_LOGIC_VECTOR ( 0 to 3 );
signal gpio_core_1_n_19 : STD_LOGIC;
signal \^gpio_io_t\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal gpio_xferAck_Reg : STD_LOGIC;
signal ip2bus_data_i_D1 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal ip2bus_rdack_i : STD_LOGIC;
signal ip2bus_rdack_i_D1 : STD_LOGIC;
signal ip2bus_wrack_i_D1 : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_rdata\ : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \^s_axi_wready\ : STD_LOGIC;
begin
gpio2_io_t(11 downto 0) <= \^gpio2_io_t\(11 downto 0);
gpio_io_t(3 downto 0) <= \^gpio_io_t\(3 downto 0);
ip2intc_irpt <= \<const0>\;
s_axi_awready <= \^s_axi_wready\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_rdata(31) <= \<const0>\;
s_axi_rdata(30) <= \<const0>\;
s_axi_rdata(29) <= \<const0>\;
s_axi_rdata(28) <= \<const0>\;
s_axi_rdata(27) <= \<const0>\;
s_axi_rdata(26) <= \<const0>\;
s_axi_rdata(25) <= \<const0>\;
s_axi_rdata(24) <= \<const0>\;
s_axi_rdata(23) <= \<const0>\;
s_axi_rdata(22) <= \<const0>\;
s_axi_rdata(21) <= \<const0>\;
s_axi_rdata(20) <= \<const0>\;
s_axi_rdata(19) <= \<const0>\;
s_axi_rdata(18) <= \<const0>\;
s_axi_rdata(17) <= \<const0>\;
s_axi_rdata(16) <= \<const0>\;
s_axi_rdata(15) <= \<const0>\;
s_axi_rdata(14) <= \<const0>\;
s_axi_rdata(13) <= \<const0>\;
s_axi_rdata(12) <= \<const0>\;
s_axi_rdata(11 downto 0) <= \^s_axi_rdata\(11 downto 0);
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_wready <= \^s_axi_wready\;
AXI_LITE_IPIF_I: entity work.system_axi_gpio_led_0_axi_lite_ipif
port map (
D(11 downto 8) => p_0_out(3 downto 0),
D(7) => AXI_LITE_IPIF_I_n_11,
D(6) => AXI_LITE_IPIF_I_n_12,
D(5) => AXI_LITE_IPIF_I_n_13,
D(4) => AXI_LITE_IPIF_I_n_14,
D(3) => AXI_LITE_IPIF_I_n_15,
D(2) => AXI_LITE_IPIF_I_n_16,
D(1) => AXI_LITE_IPIF_I_n_17,
D(0) => AXI_LITE_IPIF_I_n_18,
\Dual.gpio2_Data_In_reg[0]\(11) => gpio2_Data_In(0),
\Dual.gpio2_Data_In_reg[0]\(10) => gpio2_Data_In(1),
\Dual.gpio2_Data_In_reg[0]\(9) => gpio2_Data_In(2),
\Dual.gpio2_Data_In_reg[0]\(8) => gpio2_Data_In(3),
\Dual.gpio2_Data_In_reg[0]\(7) => gpio2_Data_In(4),
\Dual.gpio2_Data_In_reg[0]\(6) => gpio2_Data_In(5),
\Dual.gpio2_Data_In_reg[0]\(5) => gpio2_Data_In(6),
\Dual.gpio2_Data_In_reg[0]\(4) => gpio2_Data_In(7),
\Dual.gpio2_Data_In_reg[0]\(3) => gpio2_Data_In(8),
\Dual.gpio2_Data_In_reg[0]\(2) => gpio2_Data_In(9),
\Dual.gpio2_Data_In_reg[0]\(1) => gpio2_Data_In(10),
\Dual.gpio2_Data_In_reg[0]\(0) => gpio2_Data_In(11),
\Dual.gpio2_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_50,
\Dual.gpio2_OE_reg[0]\(0) => AXI_LITE_IPIF_I_n_49,
\Dual.gpio_Data_Out_reg[0]\(0) => AXI_LITE_IPIF_I_n_36,
E(0) => AXI_LITE_IPIF_I_n_35,
GPIO2_DBus_i(11) => GPIO2_DBus_i(20),
GPIO2_DBus_i(10) => GPIO2_DBus_i(21),
GPIO2_DBus_i(9) => GPIO2_DBus_i(22),
GPIO2_DBus_i(8) => GPIO2_DBus_i(23),
GPIO2_DBus_i(7) => GPIO2_DBus_i(24),
GPIO2_DBus_i(6) => GPIO2_DBus_i(25),
GPIO2_DBus_i(5) => GPIO2_DBus_i(26),
GPIO2_DBus_i(4) => GPIO2_DBus_i(27),
GPIO2_DBus_i(3) => GPIO2_DBus_i(28),
GPIO2_DBus_i(2) => GPIO2_DBus_i(29),
GPIO2_DBus_i(1) => GPIO2_DBus_i(30),
GPIO2_DBus_i(0) => GPIO2_DBus_i(31),
GPIO_DBus_i(3) => GPIO_DBus_i(28),
GPIO_DBus_i(2) => GPIO_DBus_i(29),
GPIO_DBus_i(1) => GPIO_DBus_i(30),
GPIO_DBus_i(0) => GPIO_DBus_i(31),
GPIO_xferAck_i => GPIO_xferAck_i,
Q(3) => gpio_Data_In(0),
Q(2) => gpio_Data_In(1),
Q(1) => gpio_Data_In(2),
Q(0) => gpio_Data_In(3),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
bus2ip_cs => bus2ip_cs,
bus2ip_reset => bus2ip_reset,
bus2ip_rnw => bus2ip_rnw,
gpio2_io_t(11 downto 0) => \^gpio2_io_t\(11 downto 0),
gpio_io_t(3 downto 0) => \^gpio_io_t\(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
\ip2bus_data_i_D1_reg[20]\(11 downto 0) => GPIO_DBus(11 downto 0),
\ip2bus_data_i_D1_reg[20]_0\(11 downto 0) => ip2bus_data_i_D1(11 downto 0),
ip2bus_rdack_i_D1 => ip2bus_rdack_i_D1,
ip2bus_wrack_i_D1 => ip2bus_wrack_i_D1,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(2) => s_axi_araddr(8),
s_axi_araddr(1 downto 0) => s_axi_araddr(3 downto 2),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(2) => s_axi_awaddr(8),
s_axi_awaddr(1 downto 0) => s_axi_awaddr(3 downto 2),
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(11 downto 0) => \^s_axi_rdata\(11 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(11 downto 0) => s_axi_wdata(11 downto 0),
s_axi_wready => \^s_axi_wready\,
s_axi_wvalid => s_axi_wvalid
);
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
gpio_core_1: entity work.system_axi_gpio_led_0_GPIO_Core
port map (
D(11 downto 8) => p_0_out(3 downto 0),
D(7) => AXI_LITE_IPIF_I_n_11,
D(6) => AXI_LITE_IPIF_I_n_12,
D(5) => AXI_LITE_IPIF_I_n_13,
D(4) => AXI_LITE_IPIF_I_n_14,
D(3) => AXI_LITE_IPIF_I_n_15,
D(2) => AXI_LITE_IPIF_I_n_16,
D(1) => AXI_LITE_IPIF_I_n_17,
D(0) => AXI_LITE_IPIF_I_n_18,
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(3) => gpio_Data_In(0),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(2) => gpio_Data_In(1),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(1) => gpio_Data_In(2),
\Dual.READ_REG_GEN[0].GPIO_DBus_i_reg[28]_0\(0) => gpio_Data_In(3),
E(0) => AXI_LITE_IPIF_I_n_36,
GPIO2_DBus_i(11) => GPIO2_DBus_i(20),
GPIO2_DBus_i(10) => GPIO2_DBus_i(21),
GPIO2_DBus_i(9) => GPIO2_DBus_i(22),
GPIO2_DBus_i(8) => GPIO2_DBus_i(23),
GPIO2_DBus_i(7) => GPIO2_DBus_i(24),
GPIO2_DBus_i(6) => GPIO2_DBus_i(25),
GPIO2_DBus_i(5) => GPIO2_DBus_i(26),
GPIO2_DBus_i(4) => GPIO2_DBus_i(27),
GPIO2_DBus_i(3) => GPIO2_DBus_i(28),
GPIO2_DBus_i(2) => GPIO2_DBus_i(29),
GPIO2_DBus_i(1) => GPIO2_DBus_i(30),
GPIO2_DBus_i(0) => GPIO2_DBus_i(31),
GPIO_DBus_i(3) => GPIO_DBus_i(28),
GPIO_DBus_i(2) => GPIO_DBus_i(29),
GPIO_DBus_i(1) => GPIO_DBus_i(30),
GPIO_DBus_i(0) => GPIO_DBus_i(31),
GPIO_xferAck_i => GPIO_xferAck_i,
Q(11) => gpio2_Data_In(0),
Q(10) => gpio2_Data_In(1),
Q(9) => gpio2_Data_In(2),
Q(8) => gpio2_Data_In(3),
Q(7) => gpio2_Data_In(4),
Q(6) => gpio2_Data_In(5),
Q(5) => gpio2_Data_In(6),
Q(4) => gpio2_Data_In(7),
Q(3) => gpio2_Data_In(8),
Q(2) => gpio2_Data_In(9),
Q(1) => gpio2_Data_In(10),
Q(0) => gpio2_Data_In(11),
Read_Reg2_In(0 to 11) => Read_Reg2_In(0 to 11),
Read_Reg_In(0 to 3) => Read_Reg_In(0 to 3),
Read_Reg_Rst => Read_Reg_Rst,
SS(0) => bus2ip_reset,
bus2ip_cs => bus2ip_cs,
bus2ip_rnw => bus2ip_rnw,
bus2ip_rnw_i_reg(0) => AXI_LITE_IPIF_I_n_35,
bus2ip_rnw_i_reg_0(0) => AXI_LITE_IPIF_I_n_50,
bus2ip_rnw_i_reg_1(0) => AXI_LITE_IPIF_I_n_49,
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
gpio2_io_o(11 downto 0) => gpio2_io_o(11 downto 0),
gpio2_io_t(11 downto 0) => \^gpio2_io_t\(11 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
gpio_io_o(3 downto 0) => gpio_io_o(3 downto 0),
gpio_io_t(3 downto 0) => \^gpio_io_t\(3 downto 0),
gpio_xferAck_Reg => gpio_xferAck_Reg,
ip2bus_rdack_i => ip2bus_rdack_i,
ip2bus_wrack_i_D1_reg => gpio_core_1_n_19,
s_axi_aclk => s_axi_aclk
);
\ip2bus_data_i_D1_reg[20]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(11),
Q => ip2bus_data_i_D1(11),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[21]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(10),
Q => ip2bus_data_i_D1(10),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[22]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(9),
Q => ip2bus_data_i_D1(9),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[23]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(8),
Q => ip2bus_data_i_D1(8),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[24]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(7),
Q => ip2bus_data_i_D1(7),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[25]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(6),
Q => ip2bus_data_i_D1(6),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[26]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(5),
Q => ip2bus_data_i_D1(5),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[27]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(4),
Q => ip2bus_data_i_D1(4),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[28]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(3),
Q => ip2bus_data_i_D1(3),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[29]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(2),
Q => ip2bus_data_i_D1(2),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[30]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(1),
Q => ip2bus_data_i_D1(1),
R => bus2ip_reset
);
\ip2bus_data_i_D1_reg[31]\: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => GPIO_DBus(0),
Q => ip2bus_data_i_D1(0),
R => bus2ip_reset
);
ip2bus_rdack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => ip2bus_rdack_i,
Q => ip2bus_rdack_i_D1,
R => bus2ip_reset
);
ip2bus_wrack_i_D1_reg: unisim.vcomponents.FDRE
port map (
C => s_axi_aclk,
CE => '1',
D => gpio_core_1_n_19,
Q => ip2bus_wrack_i_D1,
R => bus2ip_reset
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system_axi_gpio_led_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_araddr : in STD_LOGIC_VECTOR ( 8 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
gpio_io_i : in STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_o : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio_io_t : out STD_LOGIC_VECTOR ( 3 downto 0 );
gpio2_io_i : in STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_o : out STD_LOGIC_VECTOR ( 11 downto 0 );
gpio2_io_t : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of system_axi_gpio_led_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of system_axi_gpio_led_0 : entity is "system_axi_gpio_led_0,axi_gpio,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of system_axi_gpio_led_0 : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of system_axi_gpio_led_0 : entity is "axi_gpio,Vivado 2016.4";
end system_axi_gpio_led_0;
architecture STRUCTURE of system_axi_gpio_led_0 is
signal NLW_U0_ip2intc_irpt_UNCONNECTED : STD_LOGIC;
attribute C_ALL_INPUTS : integer;
attribute C_ALL_INPUTS of U0 : label is 0;
attribute C_ALL_INPUTS_2 : integer;
attribute C_ALL_INPUTS_2 of U0 : label is 0;
attribute C_ALL_OUTPUTS : integer;
attribute C_ALL_OUTPUTS of U0 : label is 0;
attribute C_ALL_OUTPUTS_2 : integer;
attribute C_ALL_OUTPUTS_2 of U0 : label is 0;
attribute C_DOUT_DEFAULT : integer;
attribute C_DOUT_DEFAULT of U0 : label is 0;
attribute C_DOUT_DEFAULT_2 : integer;
attribute C_DOUT_DEFAULT_2 of U0 : label is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_GPIO2_WIDTH : integer;
attribute C_GPIO2_WIDTH of U0 : label is 12;
attribute C_GPIO_WIDTH : integer;
attribute C_GPIO_WIDTH of U0 : label is 4;
attribute C_INTERRUPT_PRESENT : integer;
attribute C_INTERRUPT_PRESENT of U0 : label is 0;
attribute C_IS_DUAL : integer;
attribute C_IS_DUAL of U0 : label is 1;
attribute C_S_AXI_ADDR_WIDTH : integer;
attribute C_S_AXI_ADDR_WIDTH of U0 : label is 9;
attribute C_S_AXI_DATA_WIDTH : integer;
attribute C_S_AXI_DATA_WIDTH of U0 : label is 32;
attribute C_TRI_DEFAULT : integer;
attribute C_TRI_DEFAULT of U0 : label is -1;
attribute C_TRI_DEFAULT_2 : integer;
attribute C_TRI_DEFAULT_2 of U0 : label is -1;
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
attribute ip_group : string;
attribute ip_group of U0 : label is "LOGICORE";
begin
U0: entity work.system_axi_gpio_led_0_axi_gpio
port map (
gpio2_io_i(11 downto 0) => gpio2_io_i(11 downto 0),
gpio2_io_o(11 downto 0) => gpio2_io_o(11 downto 0),
gpio2_io_t(11 downto 0) => gpio2_io_t(11 downto 0),
gpio_io_i(3 downto 0) => gpio_io_i(3 downto 0),
gpio_io_o(3 downto 0) => gpio_io_o(3 downto 0),
gpio_io_t(3 downto 0) => gpio_io_t(3 downto 0),
ip2intc_irpt => NLW_U0_ip2intc_irpt_UNCONNECTED,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(8 downto 0) => s_axi_araddr(8 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(8 downto 0) => s_axi_awaddr(8 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_stratixii
-- File: usbhc_stratixii.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: tech wrapper for stratixii/altera usbhc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library stratixii;
use stratixii.stratixii_components.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library techmap;
use techmap.usbhc_stratixiipkg.all;
entity usbhc_stratixii is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_stratixii;
architecture rtl of usbhc_stratixii is
begin
-----------------------------------------------------------------------------
-- Howto add netlist maps:
-- First check the different combination of generics below. If your
-- configuration is not available then add a new one named comb<X+1> (where
-- X is the value of the last combination defined below) by simply copy
-- pasting one exicisting combination and changing the generics and component
-- name. Then add a component decleration for that configuration in the file
-- usbhc_stratixiipkg.vhd by simply copy pasting the port decleration from
-- the entity above and replacing n_cc, uhcgen, and nports with their actual
-- values. Also add the combination of genercis as valid in the function
-- valid_comb at the bottom of the file usbhc_stratixiipkg.vhd
-----------------------------------------------------------------------------
comb0 : if nports = 1 and
ehcgen = 0 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb0
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb0;
comb1 : if nports = 1 and
ehcgen = 1 and
uhcgen = 0 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb1
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb1;
comb2 : if nports = 1 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb2
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb2;
comb3 : if nports = 2 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 2 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb3
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb3;
-- pragma translate_off
nomap : if not valid_comb(nports,ehcgen,uhcgen,n_cc,n_pcc,prr,portroute1,
portroute2,endian_conv,be_regs,be_desc,uhcblo,bwrd,
utm_type,vbusconf,ramtest,urst_time,oepol) generate
err : process
begin
assert false report "ERROR : Can't map a netlist for this combination" &
"of generics"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: usbhc_stratixii
-- File: usbhc_stratixii.vhd
-- Author: Jonas Ekergarn - Gaisler Research
-- Description: tech wrapper for stratixii/altera usbhc netlist
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library stratixii;
use stratixii.stratixii_components.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
library techmap;
use techmap.usbhc_stratixiipkg.all;
entity usbhc_stratixii is
generic (
nports : integer range 1 to 15 := 1;
ehcgen : integer range 0 to 1 := 1;
uhcgen : integer range 0 to 1 := 1;
n_cc : integer range 1 to 15 := 1;
n_pcc : integer range 1 to 15 := 1;
prr : integer range 0 to 1 := 0;
portroute1 : integer := 0;
portroute2 : integer := 0;
endian_conv : integer range 0 to 1 := 1;
be_regs : integer range 0 to 1 := 0;
be_desc : integer range 0 to 1 := 0;
uhcblo : integer range 0 to 255 := 2;
bwrd : integer range 1 to 256 := 16;
utm_type : integer range 0 to 2 := 2;
vbusconf : integer range 0 to 3 := 3;
ramtest : integer range 0 to 1 := 0;
urst_time : integer := 250;
oepol : integer range 0 to 1 := 0
);
port (
clk : in std_ulogic;
uclk : in std_ulogic;
rst : in std_ulogic;
ursti : in std_ulogic;
-- EHC apb_slv_in_type unwrapped
ehc_apbsi_psel : in std_ulogic;
ehc_apbsi_penable : in std_ulogic;
ehc_apbsi_paddr : in std_logic_vector(31 downto 0);
ehc_apbsi_pwrite : in std_ulogic;
ehc_apbsi_pwdata : in std_logic_vector(31 downto 0);
ehc_apbsi_testen : in std_ulogic;
ehc_apbsi_testrst : in std_ulogic;
ehc_apbsi_scanen : in std_ulogic;
-- EHC apb_slv_out_type unwrapped
ehc_apbso_prdata : out std_logic_vector(31 downto 0);
ehc_apbso_pirq : out std_ulogic;
-- EHC/UHC ahb_mst_in_type unwrapped
ahbmi_hgrant : in std_logic_vector(n_cc*uhcgen downto 0);
ahbmi_hready : in std_ulogic;
ahbmi_hresp : in std_logic_vector(1 downto 0);
ahbmi_hrdata : in std_logic_vector(31 downto 0);
ahbmi_hcache : in std_ulogic;
ahbmi_testen : in std_ulogic;
ahbmi_testrst : in std_ulogic;
ahbmi_scanen : in std_ulogic;
-- UHC ahb_slv_in_type unwrapped
uhc_ahbsi_hsel : in std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbsi_haddr : in std_logic_vector(31 downto 0);
uhc_ahbsi_hwrite : in std_ulogic;
uhc_ahbsi_htrans : in std_logic_vector(1 downto 0);
uhc_ahbsi_hsize : in std_logic_vector(2 downto 0);
uhc_ahbsi_hwdata : in std_logic_vector(31 downto 0);
uhc_ahbsi_hready : in std_ulogic;
uhc_ahbsi_testen : in std_ulogic;
uhc_ahbsi_testrst : in std_ulogic;
uhc_ahbsi_scanen : in std_ulogic;
-- EHC ahb_mst_out_type_unwrapped
ehc_ahbmo_hbusreq : out std_ulogic;
ehc_ahbmo_hlock : out std_ulogic;
ehc_ahbmo_htrans : out std_logic_vector(1 downto 0);
ehc_ahbmo_haddr : out std_logic_vector(31 downto 0);
ehc_ahbmo_hwrite : out std_ulogic;
ehc_ahbmo_hsize : out std_logic_vector(2 downto 0);
ehc_ahbmo_hburst : out std_logic_vector(2 downto 0);
ehc_ahbmo_hprot : out std_logic_vector(3 downto 0);
ehc_ahbmo_hwdata : out std_logic_vector(31 downto 0);
-- UHC ahb_mst_out_vector_type unwrapped
uhc_ahbmo_hbusreq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hlock : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_htrans : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbmo_haddr : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwrite : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbmo_hsize : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hburst : out std_logic_vector((n_cc*3)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hprot : out std_logic_vector((n_cc*4)*uhcgen downto 1*uhcgen);
uhc_ahbmo_hwdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
-- UHC ahb_slv_out_vector_type unwrapped
uhc_ahbso_hready : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hresp : out std_logic_vector((n_cc*2)*uhcgen downto 1*uhcgen);
uhc_ahbso_hrdata : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
uhc_ahbso_hsplit : out std_logic_vector((n_cc*16)*uhcgen downto 1*uhcgen);
uhc_ahbso_hcache : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
uhc_ahbso_hirq : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
-- usbhc_out_type_vector unwrapped
xcvrsel : out std_logic_vector(((nports*2)-1) downto 0);
termsel : out std_logic_vector((nports-1) downto 0);
suspendm : out std_logic_vector((nports-1) downto 0);
opmode : out std_logic_vector(((nports*2)-1) downto 0);
txvalid : out std_logic_vector((nports-1) downto 0);
drvvbus : out std_logic_vector((nports-1) downto 0);
dataho : out std_logic_vector(((nports*8)-1) downto 0);
validho : out std_logic_vector((nports-1) downto 0);
host : out std_logic_vector((nports-1) downto 0);
stp : out std_logic_vector((nports-1) downto 0);
datao : out std_logic_vector(((nports*8)-1) downto 0);
utm_rst : out std_logic_vector((nports-1) downto 0);
dctrlo : out std_logic_vector((nports-1) downto 0);
-- usbhc_in_type_vector unwrapped
linestate : in std_logic_vector(((nports*2)-1) downto 0);
txready : in std_logic_vector((nports-1) downto 0);
rxvalid : in std_logic_vector((nports-1) downto 0);
rxactive : in std_logic_vector((nports-1) downto 0);
rxerror : in std_logic_vector((nports-1) downto 0);
vbusvalid : in std_logic_vector((nports-1) downto 0);
datahi : in std_logic_vector(((nports*8)-1) downto 0);
validhi : in std_logic_vector((nports-1) downto 0);
hostdisc : in std_logic_vector((nports-1) downto 0);
nxt : in std_logic_vector((nports-1) downto 0);
dir : in std_logic_vector((nports-1) downto 0);
datai : in std_logic_vector(((nports*8)-1) downto 0);
-- EHC transaction buffer signals
mbc20_tb_addr : out std_logic_vector(8 downto 0);
mbc20_tb_data : out std_logic_vector(31 downto 0);
mbc20_tb_en : out std_ulogic;
mbc20_tb_wel : out std_ulogic;
mbc20_tb_weh : out std_ulogic;
tb_mbc20_data : in std_logic_vector(31 downto 0);
pe20_tb_addr : out std_logic_vector(8 downto 0);
pe20_tb_data : out std_logic_vector(31 downto 0);
pe20_tb_en : out std_ulogic;
pe20_tb_wel : out std_ulogic;
pe20_tb_weh : out std_ulogic;
tb_pe20_data : in std_logic_vector(31 downto 0);
-- EHC packet buffer signals
mbc20_pb_addr : out std_logic_vector(8 downto 0);
mbc20_pb_data : out std_logic_vector(31 downto 0);
mbc20_pb_en : out std_ulogic;
mbc20_pb_we : out std_ulogic;
pb_mbc20_data : in std_logic_vector(31 downto 0);
sie20_pb_addr : out std_logic_vector(8 downto 0);
sie20_pb_data : out std_logic_vector(31 downto 0);
sie20_pb_en : out std_ulogic;
sie20_pb_we : out std_ulogic;
pb_sie20_data : in std_logic_vector(31 downto 0);
-- UHC packet buffer signals
sie11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
sie11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
sie11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
sie11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_sie11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_addr : out std_logic_vector((n_cc*9)*uhcgen downto 1*uhcgen);
mbc11_pb_data : out std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
mbc11_pb_en : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
mbc11_pb_we : out std_logic_vector(n_cc*uhcgen downto 1*uhcgen);
pb_mbc11_data : in std_logic_vector((n_cc*32)*uhcgen downto 1*uhcgen);
bufsel : out std_ulogic);
end usbhc_stratixii;
architecture rtl of usbhc_stratixii is
begin
-----------------------------------------------------------------------------
-- Howto add netlist maps:
-- First check the different combination of generics below. If your
-- configuration is not available then add a new one named comb<X+1> (where
-- X is the value of the last combination defined below) by simply copy
-- pasting one exicisting combination and changing the generics and component
-- name. Then add a component decleration for that configuration in the file
-- usbhc_stratixiipkg.vhd by simply copy pasting the port decleration from
-- the entity above and replacing n_cc, uhcgen, and nports with their actual
-- values. Also add the combination of genercis as valid in the function
-- valid_comb at the bottom of the file usbhc_stratixiipkg.vhd
-----------------------------------------------------------------------------
comb0 : if nports = 1 and
ehcgen = 0 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb0
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb0;
comb1 : if nports = 1 and
ehcgen = 1 and
uhcgen = 0 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb1
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb1;
comb2 : if nports = 1 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 1 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb2
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb2;
comb3 : if nports = 2 and
ehcgen = 1 and
uhcgen = 1 and
n_cc = 1 and
n_pcc = 2 and
prr = 0 and
portroute1 = 0 and
portroute2 = 0 and
endian_conv = 1 and
be_regs = 0 and
be_desc = 0 and
uhcblo = 2 and
bwrd = 16 and
utm_type = 2 and
vbusconf = 3 and
ramtest = 0 and
urst_time = 250 and
oepol = 0 generate
usbhc0 : usbhc_stratixii_comb3
port map(
clk,uclk,rst,ursti,ehc_apbsi_psel,ehc_apbsi_penable,ehc_apbsi_paddr,
ehc_apbsi_pwrite,ehc_apbsi_pwdata,ehc_apbsi_testen,ehc_apbsi_testrst,
ehc_apbsi_scanen,ehc_apbso_prdata,ehc_apbso_pirq,ahbmi_hgrant,
ahbmi_hready,ahbmi_hresp,ahbmi_hrdata,ahbmi_hcache,ahbmi_testen,
ahbmi_testrst,ahbmi_scanen,uhc_ahbsi_hsel,uhc_ahbsi_haddr,
uhc_ahbsi_hwrite,uhc_ahbsi_htrans,uhc_ahbsi_hsize,uhc_ahbsi_hwdata,
uhc_ahbsi_hready,uhc_ahbsi_testen,uhc_ahbsi_testrst,uhc_ahbsi_scanen,
ehc_ahbmo_hbusreq,ehc_ahbmo_hlock,ehc_ahbmo_htrans,ehc_ahbmo_haddr,
ehc_ahbmo_hwrite,ehc_ahbmo_hsize,ehc_ahbmo_hburst,ehc_ahbmo_hprot,
ehc_ahbmo_hwdata,uhc_ahbmo_hbusreq,uhc_ahbmo_hlock,uhc_ahbmo_htrans,
uhc_ahbmo_haddr,uhc_ahbmo_hwrite,uhc_ahbmo_hsize,uhc_ahbmo_hburst,
uhc_ahbmo_hprot,uhc_ahbmo_hwdata,uhc_ahbso_hready,uhc_ahbso_hresp,
uhc_ahbso_hrdata,uhc_ahbso_hsplit,uhc_ahbso_hcache,uhc_ahbso_hirq,
xcvrsel,termsel,suspendm,opmode,txvalid,drvvbus,dataho,validho,host,
stp,datao,utm_rst,dctrlo,linestate,txready,rxvalid,rxactive,rxerror,
vbusvalid,datahi,validhi,hostdisc,nxt,dir,datai,mbc20_tb_addr,
mbc20_tb_data,mbc20_tb_en,mbc20_tb_wel,mbc20_tb_weh,tb_mbc20_data,
pe20_tb_addr,pe20_tb_data,pe20_tb_en,pe20_tb_wel,pe20_tb_weh,
tb_pe20_data,mbc20_pb_addr,mbc20_pb_data,mbc20_pb_en,mbc20_pb_we,
pb_mbc20_data,sie20_pb_addr,sie20_pb_data,sie20_pb_en,sie20_pb_we,
pb_sie20_data,sie11_pb_addr,sie11_pb_data,sie11_pb_en,sie11_pb_we,
pb_sie11_data,mbc11_pb_addr,mbc11_pb_data,mbc11_pb_en,mbc11_pb_we,
pb_mbc11_data,bufsel);
end generate comb3;
-- pragma translate_off
nomap : if not valid_comb(nports,ehcgen,uhcgen,n_cc,n_pcc,prr,portroute1,
portroute2,endian_conv,be_regs,be_desc,uhcblo,bwrd,
utm_type,vbusconf,ramtest,urst_time,oepol) generate
err : process
begin
assert false report "ERROR : Can't map a netlist for this combination" &
"of generics"
severity failure;
wait;
end process;
end generate;
-- pragma translate_on
end rtl;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_03 is
end entity ap_a_03;
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of ap_a_03 is
begin
b1 : block is
-- code from book
type unsigned is array ( natural range <> ) of std_logic;
type signed is array ( natural range <> ) of std_logic;
-- end code from book
begin
end block b1;
b2 : block is
-- code from book
signal a: integer := 0;
signal b: signed (4 downto 0 );
-- end code from book
begin
a <= 0, 5 after 10 ns, -5 after 20 ns, 8 after 30 ns;
-- code from book
b <= To_signed ( a, b'length );
-- end code from book
process (b) is
begin
-- code from book
if std_match ( b, "0-000" ) then
-- . . .
-- end code from book
report "b matches";
else
report "b does not match";
end if;
end process;
end block b2;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_03 is
end entity ap_a_03;
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of ap_a_03 is
begin
b1 : block is
-- code from book
type unsigned is array ( natural range <> ) of std_logic;
type signed is array ( natural range <> ) of std_logic;
-- end code from book
begin
end block b1;
b2 : block is
-- code from book
signal a: integer := 0;
signal b: signed (4 downto 0 );
-- end code from book
begin
a <= 0, 5 after 10 ns, -5 after 20 ns, 8 after 30 ns;
-- code from book
b <= To_signed ( a, b'length );
-- end code from book
process (b) is
begin
-- code from book
if std_match ( b, "0-000" ) then
-- . . .
-- end code from book
report "b matches";
else
report "b does not match";
end if;
end process;
end block b2;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ap_a_ap_a_03.vhd,v 1.2 2001-10-26 16:29:33 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
entity ap_a_03 is
end entity ap_a_03;
library ieee; use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture test of ap_a_03 is
begin
b1 : block is
-- code from book
type unsigned is array ( natural range <> ) of std_logic;
type signed is array ( natural range <> ) of std_logic;
-- end code from book
begin
end block b1;
b2 : block is
-- code from book
signal a: integer := 0;
signal b: signed (4 downto 0 );
-- end code from book
begin
a <= 0, 5 after 10 ns, -5 after 20 ns, 8 after 30 ns;
-- code from book
b <= To_signed ( a, b'length );
-- end code from book
process (b) is
begin
-- code from book
if std_match ( b, "0-000" ) then
-- . . .
-- end code from book
report "b matches";
else
report "b does not match";
end if;
end process;
end block b2;
end architecture test;
|
-- NEED RESULT: ARCH00683: Allocators with static scalar subtype indication passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00683
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.6 (2)
-- 7.3.6 (4)
-- 7.3.6 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00683)
-- ENT00683_Test_Bench(ARCH00683_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-SEP-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00683 of E00000 is
begin
process
variable correct : boolean := true ;
type a_boolean is access boolean ;
variable va_boolean_1, va_boolean_2 : a_boolean
:= new boolean ;
type a_bit is access bit ;
variable va_bit_1, va_bit_2 : a_bit
:= new bit ;
type a_severity_level is access severity_level ;
variable va_severity_level_1, va_severity_level_2 : a_severity_level
:= new severity_level ;
type a_character is access character ;
variable va_character_1, va_character_2 : a_character
:= new character ;
type a_t_enum1 is access t_enum1 ;
variable va_t_enum1_1, va_t_enum1_2 : a_t_enum1
:= new t_enum1 ;
type a_st_enum1 is access st_enum1 ;
variable va_st_enum1_1, va_st_enum1_2 : a_st_enum1
:= new st_enum1 ;
type a_integer is access integer ;
variable va_integer_1, va_integer_2 : a_integer
:= new integer ;
type a_t_int1 is access t_int1 ;
variable va_t_int1_1, va_t_int1_2 : a_t_int1
:= new t_int1 ;
type a_st_int1 is access st_int1 ;
variable va_st_int1_1, va_st_int1_2 : a_st_int1
:= new st_int1 ;
type a_time is access time ;
variable va_time_1, va_time_2 : a_time
:= new time ;
type a_t_phys1 is access t_phys1 ;
variable va_t_phys1_1, va_t_phys1_2 : a_t_phys1
:= new t_phys1 ;
type a_st_phys1 is access st_phys1 ;
variable va_st_phys1_1, va_st_phys1_2 : a_st_phys1
:= new st_phys1 ;
type a_real is access real ;
variable va_real_1, va_real_2 : a_real
:= new real ;
type a_t_real1 is access t_real1 ;
variable va_t_real1_1, va_t_real1_2 : a_t_real1
:= new t_real1 ;
type a_st_real1 is access st_real1 ;
variable va_st_real1_1, va_st_real1_2 : a_st_real1
:= new st_real1 ;
begin
correct := correct and
va_boolean_1.all = d_boolean ;
correct := correct and
va_bit_1.all = d_bit ;
correct := correct and
va_severity_level_1.all = d_severity_level ;
correct := correct and
va_character_1.all = d_character ;
correct := correct and
va_t_enum1_1.all = d_t_enum1 ;
correct := correct and
va_st_enum1_1.all = d_st_enum1 ;
correct := correct and
va_integer_1.all = d_integer ;
correct := correct and
va_t_int1_1.all = d_t_int1 ;
correct := correct and
va_st_int1_1.all = d_st_int1 ;
correct := correct and
va_time_1.all = d_time ;
correct := correct and
va_t_phys1_1.all = d_t_phys1 ;
correct := correct and
va_st_phys1_1.all = d_st_phys1 ;
correct := correct and
va_real_1.all = d_real ;
correct := correct and
va_t_real1_1.all = d_t_real1 ;
correct := correct and
va_st_real1_1.all = d_st_real1 ;
test_report ( "ARCH00683" ,
"Allocators with static scalar subtype indication" ,
correct) ;
wait ;
end process ;
end ARCH00683 ;
--
entity ENT00683_Test_Bench is
end ENT00683_Test_Bench ;
--
architecture ARCH00683_Test_Bench of ENT00683_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00683 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00683_Test_Bench ;
|
---------------------------------------------------------------------------
--
-- (c) Copyright 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
---------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the Divider Generator
-- LogiCORE module. The testbench has been generated by the Xilinx
-- CORE Generator software to accompany the netlist you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with the netlist created for your core.
--
-- See the Divider Generator datasheet for further information about
-- this core.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated Divider Generator core
-- named "div".
--
-- There are two versions of your core that you can use in this testbench:
-- the XilinxCoreLib behavioral model or the generated netlist.
--
-- 1. XilinxCoreLib behavioral model
-- Compile div.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
-- 2. Generated netlist
-- Execute the following command in the directory containing your CORE
-- Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl div.ngc div_netlist.vhd
--
-- Compile div_netlist.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_div is
end tb_div;
architecture tb of tb_div is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
constant TEST_CYCLES : integer := 3000;
constant PHASE_CYCLES : integer := 1000;
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Slave channel DIVIDEND inputs
signal s_axis_dividend_tvalid : std_logic := '0'; -- TVALID for channel A
signal s_axis_dividend_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel A
-- Slave channel DIVISOR inputs
signal s_axis_divisor_tvalid : std_logic := '0'; -- TVALID for channel B
signal s_axis_divisor_tdata : std_logic_vector(15 downto 0) := (others => 'X'); -- TDATA for channel B
-- Breakout signals. These signals are the application-specific operands which
-- become subfields of the TDATA fields.
signal dividend : std_logic_vector(12 downto 0) := (others => '0');
signal divisor : std_logic_vector(12 downto 0) := (others => '0');
signal quotient : std_logic_vector(12 downto 0) := (others => '0');
signal fractional : std_logic_vector(11 downto 0) := (others => '0');
-----------------------------------------------------------------------
-- DUT output signals
-----------------------------------------------------------------------
-- Master channel DOUT outputs
signal m_axis_dout_tvalid : std_logic := '0'; -- TVALID for channel DOUT
signal m_axis_dout_tdata : std_logic_vector(31 downto 0) := (others => '0'); -- TDATA for channel DOUT
-----------------------------------------------------------------------
-- Testbench signals
-----------------------------------------------------------------------
signal cycles : integer := 0; -- Clock cycle counter
-----------------------------------------------------------------------
-- Constants, types and functions to create input data
-- Feed the divider walking ones on the dividend and walking one's with the
-- LSB set so as to show simple results which will still use remainder and fraction,
-- e.g. 8/5.
-----------------------------------------------------------------------
constant IP_dividend_DEPTH : integer := 30;
constant IP_dividend_WIDTH : integer := 13;
constant IP_divisor_DEPTH : integer := 32;
constant IP_divisor_WIDTH : integer := 13;
subtype T_IP_dividend_ENTRY is std_logic_vector(IP_dividend_WIDTH-1 downto 0);
subtype T_IP_divisor_ENTRY is std_logic_vector(IP_divisor_WIDTH-1 downto 0);
type T_IP_dividend_TABLE is array (0 to IP_dividend_DEPTH-1) of T_IP_dividend_ENTRY;
type T_IP_divisor_TABLE is array (0 to IP_divisor_DEPTH-1) of T_IP_divisor_ENTRY;
-- Use separate functions to calculate channel dividend and divisor
-- waveforms as they return different widths in general
function create_ip_dividend_table return T_IP_dividend_TABLE is
variable result : T_IP_dividend_TABLE;
variable entry_int : signed(IP_dividend_WIDTH-1 downto 0) := (others => '0');
begin
for i in 0 to IP_dividend_DEPTH-1 loop
entry_int := (others => '0');
entry_int(i mod IP_dividend_WIDTH) := '1';
result(i) := std_logic_vector(entry_int);
end loop;
return result;
end function create_ip_dividend_table;
function create_ip_divisor_table return T_IP_divisor_TABLE is
variable result : T_IP_divisor_TABLE;
variable entry_int : signed(IP_divisor_WIDTH-1 downto 0) := (others => '0');
begin
for i in 0 to IP_divisor_DEPTH-1 loop
entry_int := (others => '0');
entry_int(0) := '1';
entry_int(i mod IP_divisor_WIDTH) := '1';
result(i) := std_logic_vector(entry_int);
end loop;
return result;
end function create_ip_divisor_table;
-- Call the functions to create the data
constant IP_dividend_DATA : T_IP_dividend_TABLE := create_ip_dividend_table;
constant IP_divisor_DATA : T_IP_divisor_TABLE := create_ip_divisor_table;
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.div
port map (
aclk => aclk,
s_axis_dividend_tvalid => s_axis_dividend_tvalid,
s_axis_dividend_tdata => s_axis_dividend_tdata,
s_axis_divisor_tvalid => s_axis_divisor_tvalid,
s_axis_divisor_tdata => s_axis_divisor_tdata,
m_axis_dout_tvalid => m_axis_dout_tvalid,
m_axis_dout_tdata => m_axis_dout_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
cycles <= cycles + 1;
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
if cycles >= TEST_CYCLES then
report "Not a real failure. Simulation finished successfully." severity failure;
wait;
end if;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
variable ip_dividend_index : integer := 0;
variable ip_divisor_index : integer := 0;
variable dividend_tvalid_nxt : std_logic := '0';
variable divisor_tvalid_nxt : std_logic := '0';
variable phase2_cycles : integer := 1;
variable phase2_count : integer := 0;
constant PHASE2_LIMIT : integer := 30;
begin
-- Test is stopped in clock_gen process, use endless loop here
loop
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Drive AXI TVALID signals to demonstrate different types of operation
case cycles is -- do different types of operation at different phases of the test
when 0 to PHASE_CYCLES * 1 - 1 =>
-- Phase 1: inputs always valid, no missing input data
dividend_tvalid_nxt := '1';
divisor_tvalid_nxt := '1';
when PHASE_CYCLES * 1 to PHASE_CYCLES * 2 - 1 =>
-- Phase 2: deprive channel A of valid transactions at an increasing rate
divisor_tvalid_nxt := '1';
if phase2_count < phase2_cycles then
dividend_tvalid_nxt := '0';
else
dividend_tvalid_nxt := '1';
end if;
phase2_count := phase2_count + 1;
if phase2_count >= PHASE2_LIMIT then
phase2_count := 0;
phase2_cycles := phase2_cycles + 1;
end if;
when PHASE_CYCLES * 2 to PHASE_CYCLES * 3 - 1 =>
-- Phase 3: deprive channel A of 1 out of 2 transactions, and channel B of 1 out of 3 transactions
if cycles mod 2 = 0 then
dividend_tvalid_nxt := '0';
else
dividend_tvalid_nxt := '1';
end if;
if cycles mod 3 = 0 then
divisor_tvalid_nxt := '0';
else
divisor_tvalid_nxt := '1';
end if;
when others =>
-- Test will stop imminently - do nothing
null;
end case;
-- Drive handshake signals with local variable values
s_axis_dividend_tvalid <= dividend_tvalid_nxt;
s_axis_divisor_tvalid <= divisor_tvalid_nxt;
-- Drive AXI slave channel A payload
-- Drive 'X's on payload signals when not valid
if dividend_tvalid_nxt /= '1' then
s_axis_dividend_tdata <= (others => 'X');
else
-- TDATA: This holds the dividend operand. It is 13 bits wide and byte-aligned with the operand in the LSBs
s_axis_dividend_tdata <= std_logic_vector(resize(signed(IP_dividend_DATA(ip_dividend_index)),16));
end if;
-- Drive AXI slave channel B payload
-- Drive 'X's on payload signals when not valid
if divisor_tvalid_nxt /= '1' then
s_axis_divisor_tdata <= (others => 'X');
else
-- TDATA: Holds the divisor operand. It is 13 bits wide and byte-aligned with the operand in the LSBs
s_axis_divisor_tdata <= std_logic_vector(resize(signed(IP_divisor_DATA(ip_divisor_index)),16));
end if;
-- Increment input data indices
if dividend_tvalid_nxt = '1' then
ip_dividend_index := ip_dividend_index + 1;
if ip_dividend_index = IP_dividend_DEPTH then
ip_dividend_index := 0;
end if;
end if;
if divisor_tvalid_nxt = '1' then
ip_divisor_index := ip_divisor_index + 1;
if ip_divisor_index = IP_divisor_DEPTH then
ip_divisor_index := 0;
end if;
end if;
end loop;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the DOUT channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_dout_tvalid = '1' then
if is_x(m_axis_dout_tdata) then
report "ERROR: m_axis_dout_tdata is invalid when m_axis_dout_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
divisor <= s_axis_divisor_tdata(12 downto 0);
dividend <= s_axis_dividend_tdata(12 downto 0);
fractional <= m_axis_dout_tdata(11 downto 0);
quotient <= m_axis_dout_tdata(24 downto 12);
end tb;
|
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2010 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: Dec 03, 2009
-- Design Name: IVK
-- Module Name: ivk_video_gen\colorbargen.vhd
-- Project Name: IVK
-- Target Devices: Spartan-6
-- Avnet Boards: IVK
--
-- Tool versions: ISE 11.4
--
-- Description: Color Bar Generator
--
-- Dependencies:
--
-- Revision: Dec 03, 2009: 1.00 Initial version
--
------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-- NOTES : Generate 8 color bars
--
-- R G B => Color
-- === === === ===========
-- 000 000 000 => K (black)
-- 000 000 255 => B (blue)
-- 000 255 000 => G (green)
-- 000 255 255 => C (cyan)
-- 255 000 000 => R (red)
-- 255 000 255 => M (magenta)
-- 255 255 000 => Y (yellow)
-- 255 255 255 => W (white)
--
-- Suggested Color Bar order : WYCGMRKB
--
entity ColorBarGen is
generic (
HWidth_g : integer := 16;
VWidth_g : integer := 16
);
port (
-- Global Reset
i_clk_p : in std_logic;
i_Reset_p : in std_logic;
-- Image Size
iv_HActive_p : in std_logic_vector(HWidth_g-1 downto 0);
iv_VActive_p : in std_logic_vector(VWidth_g-1 downto 0);
-- Data Request strobe (1 cycle in advance of synchronization signals)
iv_HCount_p : in std_logic_vector(HWidth_g-1 downto 0);
iv_VCount_p : in std_logic_vector(VWidth_g-1 downto 0);
i_PixelRequest_p : in std_logic;
-- Pixel Output
o_PixelValid_p : out std_logic;
ov8_RPixel_p : out std_logic_vector(7 downto 0);
ov8_GPixel_p : out std_logic_vector(7 downto 0);
ov8_BPixel_p : out std_logic_vector(7 downto 0)
);
end entity ColorBarGen;
architecture Rtl of ColorBarGen is
--
-- Intermediate signals for output ports
--
-- Pixel Output
signal PixelValid_s : std_logic;
signal v8_RPixel_s : std_logic_vector(7 downto 0);
signal v8_GPixel_s : std_logic_vector(7 downto 0);
signal v8_BPixel_s : std_logic_vector(7 downto 0);
--
-- Color Bar Generation
--
type ColorState_t is (
White_c,
Yellow_c,
Cyan_c,
Green_c,
Magenta_c,
Red_c,
Black_c,
Blue_c
);
signal ColorState_s : ColorState_t;
attribute fsm_encoding : string;
attribute fsm_encoding of ColorState_s
: signal is "sequential";
attribute safe_implementation : string;
attribute safe_implementation of ColorState_s
: signal is "yes";
alias v_HActiveDiv8_a : std_logic_vector(HWidth_g-4 downto 0) is iv_HActive_p(HWidth_g-1 downto 3);
begin
--
-- Output port assignments
--
-- Pixel Output
o_PixelValid_p <= PixelValid_s;
ov8_RPixel_p <= v8_RPixel_s;
ov8_GPixel_p <= v8_GPixel_s;
ov8_BPixel_p <= v8_BPixel_s;
--
-- Color Bar Generation
--
ColorBar_l : process( i_Clk_p, i_Reset_p )
begin
if ( i_Reset_p = '1' ) then
PixelValid_s <= '0';
v8_RPixel_s <= (others => '0');
v8_GPixel_s <= (others => '0');
v8_BPixel_s <= (others => '0');
ColorState_s <= White_c;
elsif rising_edge( i_Clk_p ) then
-- Default values
PixelValid_s <= '0';
v8_RPixel_s <= (others => '0');
v8_GPixel_s <= (others => '0');
v8_BPixel_s <= (others => '0');
-- Active Video
if ( i_PixelRequest_p = '1' ) then
PixelValid_s <= '1';
case ColorState_s is
when White_c =>
if unsigned(iv_HCount_p) >= (unsigned(v_HActiveDiv8_a)-1) then
ColorState_s <= Yellow_c;
end if;
v8_RPixel_s <= X"FF";
v8_GPixel_s <= X"FF";
v8_BPixel_s <= X"FF";
when Yellow_c =>
if unsigned(iv_HCount_p) >= (2*unsigned(v_HActiveDiv8_a)-1) then
ColorState_s <= Cyan_c;
end if;
v8_RPixel_s <= X"FF";
v8_GPixel_s <= X"FF";
v8_BPixel_s <= (others => '0');
when Cyan_c =>
if unsigned(iv_HCount_p) >= (3*unsigned(v_HActiveDiv8_a)-1) then
ColorState_s <= Green_c;
end if;
v8_RPixel_s <= (others => '0');
v8_GPixel_s <= X"FF";
v8_BPixel_s <= X"FF";
when Green_c =>
if unsigned(iv_HCount_p) >= (4*unsigned(v_HActiveDiv8_a)-1) then
ColorState_s <= Magenta_c;
end if;
v8_RPixel_s <= (others => '0');
v8_GPixel_s <= X"FF";
v8_BPixel_s <= (others => '0');
when Magenta_c =>
if unsigned(iv_HCount_p) >= (5*unsigned(v_HActiveDiv8_a)-1) then
ColorState_s <= Red_c;
end if;
v8_RPixel_s <= X"FF";
v8_GPixel_s <= (others => '0');
v8_BPixel_s <= X"FF";
when Red_c =>
if unsigned(iv_HCount_p) >= (6*unsigned(v_HActiveDiv8_a)-1) then
ColorState_s <= Black_c;
end if;
v8_RPixel_s <= X"FF";
v8_GPixel_s <= (others => '0');
v8_BPixel_s <= (others => '0');
when Black_c =>
if unsigned(iv_HCount_p) >= (7*unsigned(v_HActiveDiv8_a)-1) then
ColorState_s <= Blue_c;
end if;
v8_RPixel_s <= (others => '0');
v8_GPixel_s <= (others => '0');
v8_BPixel_s <= (others => '0');
when Blue_c =>
if unsigned(iv_HCount_p) >= (unsigned(iv_HActive_p)-1) then
ColorState_s <= White_c;
end if;
v8_RPixel_s <= (others => '0');
v8_GPixel_s <= (others => '0');
v8_BPixel_s <= X"FF";
when others =>
PixelValid_s <= '0';
v8_RPixel_s <= (others => '0');
v8_GPixel_s <= (others => '0');
v8_BPixel_s <= (others => '0');
ColorState_s <= White_c;
end case;
end if;
end if;
end process ColorBar_l;
end architecture Rtl; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity keyboard is
port(
CLK : in std_logic;
RESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
KEYB_DATA : out std_logic_vector(4 downto 0);
RESET_TICK : out std_logic);
end keyboard;
architecture rtl of keyboard is
signal CODE : std_logic_vector(7 downto 0); -- Scancode recieved from keyboard
signal DONE : std_logic; -- Current scancode valid
signal ERROR : std_logic; -- Current scancode corrupted
signal RELEASED_KEY : std_logic;
signal EXTENDED_KEY : std_logic;
signal KEYB_DATA_TEMP : std_logic_vector(4 downto 0);
begin
keyb_data <= KEYB_DATA_TEMP;
u_PS2 : entity work.ps2
port map(
CLK => CLK,
RESET => RESET,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
CODE => CODE,
DONE => DONE,
ERROR => ERROR );
main : process(CLK)
begin
if rising_edge(CLK) then
if RESET = '1' then
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
RESET_TICK <= '0';
KEYB_DATA_TEMP <= "00000";
else
RESET_TICK <= '0';
if ERROR = '1' then
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
elsif DONE = '1' then
if CODE = X"F0" then
RELEASED_KEY <= '1';
elsif CODE = X"E0" then
EXTENDED_KEY <= '1';
elsif CODE = X"07" and RELEASED_KEY = '1' then
RESET_TICK <= '1';
else
if EXTENDED_KEY = '1' then
if CODE = X"75" then
KEYB_DATA_TEMP(3) <= not RELEASED_KEY; -- up
elsif CODE = X"72" then
KEYB_DATA_TEMP(2) <= not RELEASED_KEY; -- down
elsif CODE = X"6B" then
KEYB_DATA_TEMP(1) <= not RELEASED_KEY; -- left
elsif CODE = X"74" then
KEYB_DATA_TEMP(0) <= not RELEASED_KEY; -- right
end if;
else
if CODE = X"29" or CODE = X"5A" then
KEYB_DATA_TEMP(4) <= not RELEASED_KEY; -- space/enter for fire
end if;
end if;
RELEASED_KEY <= '0';
EXTENDED_KEY <= '0';
end if;
end if;
end if;
end if;
end process;
end; |
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_10a is
end entity inline_10a;
----------------------------------------------------------------
architecture test of inline_10a is
-- code from book:
type stick_position is (down, center, up);
-- end of code from book
signal throttle : stick_position;
begin
process_3_a : process (throttle) is
variable speed : integer := 0;
constant decrement : integer := 1;
constant increment : integer := 1;
begin
-- code from book:
case throttle is
when down =>
speed := speed - decrement;
when up =>
speed := speed + increment;
when center =>
null; -- no change to speed
end case;
-- end of code from book
end process process_3_a;
stimulus : process is
begin
throttle <= down after 10 ns, center after 20 ns, up after 30 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_10a is
end entity inline_10a;
----------------------------------------------------------------
architecture test of inline_10a is
-- code from book:
type stick_position is (down, center, up);
-- end of code from book
signal throttle : stick_position;
begin
process_3_a : process (throttle) is
variable speed : integer := 0;
constant decrement : integer := 1;
constant increment : integer := 1;
begin
-- code from book:
case throttle is
when down =>
speed := speed - decrement;
when up =>
speed := speed + increment;
when center =>
null; -- no change to speed
end case;
-- end of code from book
end process process_3_a;
stimulus : process is
begin
throttle <= down after 10 ns, center after 20 ns, up after 30 ns;
wait;
end process stimulus;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_10a is
end entity inline_10a;
----------------------------------------------------------------
architecture test of inline_10a is
-- code from book:
type stick_position is (down, center, up);
-- end of code from book
signal throttle : stick_position;
begin
process_3_a : process (throttle) is
variable speed : integer := 0;
constant decrement : integer := 1;
constant increment : integer := 1;
begin
-- code from book:
case throttle is
when down =>
speed := speed - decrement;
when up =>
speed := speed + increment;
when center =>
null; -- no change to speed
end case;
-- end of code from book
end process process_3_a;
stimulus : process is
begin
throttle <= down after 10 ns, center after 20 ns, up after 30 ns;
wait;
end process stimulus;
end architecture test;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:blk_mem_gen:8.3
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY blk_mem_gen_v8_3_1;
USE blk_mem_gen_v8_3_1.blk_mem_gen_v8_3_1;
ENTITY FrameBuffer IS
PORT (
clka : IN STD_LOGIC;
ena : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END FrameBuffer;
ARCHITECTURE FrameBuffer_arch OF FrameBuffer IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF FrameBuffer_arch: ARCHITECTURE IS "yes";
COMPONENT blk_mem_gen_v8_3_1 IS
GENERIC (
C_FAMILY : STRING;
C_XDEVICEFAMILY : STRING;
C_ELABORATION_DIR : STRING;
C_INTERFACE_TYPE : INTEGER;
C_AXI_TYPE : INTEGER;
C_AXI_SLAVE_TYPE : INTEGER;
C_USE_BRAM_BLOCK : INTEGER;
C_ENABLE_32BIT_ADDRESS : INTEGER;
C_CTRL_ECC_ALGO : STRING;
C_HAS_AXI_ID : INTEGER;
C_AXI_ID_WIDTH : INTEGER;
C_MEM_TYPE : INTEGER;
C_BYTE_SIZE : INTEGER;
C_ALGORITHM : INTEGER;
C_PRIM_TYPE : INTEGER;
C_LOAD_INIT_FILE : INTEGER;
C_INIT_FILE_NAME : STRING;
C_INIT_FILE : STRING;
C_USE_DEFAULT_DATA : INTEGER;
C_DEFAULT_DATA : STRING;
C_HAS_RSTA : INTEGER;
C_RST_PRIORITY_A : STRING;
C_RSTRAM_A : INTEGER;
C_INITA_VAL : STRING;
C_HAS_ENA : INTEGER;
C_HAS_REGCEA : INTEGER;
C_USE_BYTE_WEA : INTEGER;
C_WEA_WIDTH : INTEGER;
C_WRITE_MODE_A : STRING;
C_WRITE_WIDTH_A : INTEGER;
C_READ_WIDTH_A : INTEGER;
C_WRITE_DEPTH_A : INTEGER;
C_READ_DEPTH_A : INTEGER;
C_ADDRA_WIDTH : INTEGER;
C_HAS_RSTB : INTEGER;
C_RST_PRIORITY_B : STRING;
C_RSTRAM_B : INTEGER;
C_INITB_VAL : STRING;
C_HAS_ENB : INTEGER;
C_HAS_REGCEB : INTEGER;
C_USE_BYTE_WEB : INTEGER;
C_WEB_WIDTH : INTEGER;
C_WRITE_MODE_B : STRING;
C_WRITE_WIDTH_B : INTEGER;
C_READ_WIDTH_B : INTEGER;
C_WRITE_DEPTH_B : INTEGER;
C_READ_DEPTH_B : INTEGER;
C_ADDRB_WIDTH : INTEGER;
C_HAS_MEM_OUTPUT_REGS_A : INTEGER;
C_HAS_MEM_OUTPUT_REGS_B : INTEGER;
C_HAS_MUX_OUTPUT_REGS_A : INTEGER;
C_HAS_MUX_OUTPUT_REGS_B : INTEGER;
C_MUX_PIPELINE_STAGES : INTEGER;
C_HAS_SOFTECC_INPUT_REGS_A : INTEGER;
C_HAS_SOFTECC_OUTPUT_REGS_B : INTEGER;
C_USE_SOFTECC : INTEGER;
C_USE_ECC : INTEGER;
C_EN_ECC_PIPE : INTEGER;
C_HAS_INJECTERR : INTEGER;
C_SIM_COLLISION_CHECK : STRING;
C_COMMON_CLK : INTEGER;
C_DISABLE_WARN_BHV_COLL : INTEGER;
C_EN_SLEEP_PIN : INTEGER;
C_USE_URAM : INTEGER;
C_EN_RDADDRA_CHG : INTEGER;
C_EN_RDADDRB_CHG : INTEGER;
C_EN_DEEPSLEEP_PIN : INTEGER;
C_EN_SHUTDOWN_PIN : INTEGER;
C_EN_SAFETY_CKT : INTEGER;
C_DISABLE_WARN_BHV_RANGE : INTEGER;
C_COUNT_36K_BRAM : STRING;
C_COUNT_18K_BRAM : STRING;
C_EST_POWER_SUMMARY : STRING
);
PORT (
clka : IN STD_LOGIC;
rsta : IN STD_LOGIC;
ena : IN STD_LOGIC;
regcea : IN STD_LOGIC;
wea : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addra : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dina : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
douta : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
clkb : IN STD_LOGIC;
rstb : IN STD_LOGIC;
enb : IN STD_LOGIC;
regceb : IN STD_LOGIC;
web : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
addrb : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
dinb : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
doutb : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
injectsbiterr : IN STD_LOGIC;
injectdbiterr : IN STD_LOGIC;
eccpipece : IN STD_LOGIC;
sbiterr : OUT STD_LOGIC;
dbiterr : OUT STD_LOGIC;
rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0);
sleep : IN STD_LOGIC;
deepsleep : IN STD_LOGIC;
shutdown : IN STD_LOGIC;
rsta_busy : OUT STD_LOGIC;
rstb_busy : OUT STD_LOGIC;
s_aclk : IN STD_LOGIC;
s_aresetn : IN STD_LOGIC;
s_axi_awid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_awaddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_awlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_awsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_awburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_awvalid : IN STD_LOGIC;
s_axi_awready : OUT STD_LOGIC;
s_axi_wdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_wstrb : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axi_wlast : IN STD_LOGIC;
s_axi_wvalid : IN STD_LOGIC;
s_axi_wready : OUT STD_LOGIC;
s_axi_bid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_bvalid : OUT STD_LOGIC;
s_axi_bready : IN STD_LOGIC;
s_axi_arid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_araddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axi_arlen : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_arsize : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s_axi_arburst : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_arvalid : IN STD_LOGIC;
s_axi_arready : OUT STD_LOGIC;
s_axi_rid : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
s_axi_rdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s_axi_rlast : OUT STD_LOGIC;
s_axi_rvalid : OUT STD_LOGIC;
s_axi_rready : IN STD_LOGIC;
s_axi_injectsbiterr : IN STD_LOGIC;
s_axi_injectdbiterr : IN STD_LOGIC;
s_axi_sbiterr : OUT STD_LOGIC;
s_axi_dbiterr : OUT STD_LOGIC;
s_axi_rdaddrecc : OUT STD_LOGIC_VECTOR(13 DOWNTO 0)
);
END COMPONENT blk_mem_gen_v8_3_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF FrameBuffer_arch: ARCHITECTURE IS "blk_mem_gen_v8_3_1,Vivado 2015.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF FrameBuffer_arch : ARCHITECTURE IS "FrameBuffer,blk_mem_gen_v8_3_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF FrameBuffer_arch: ARCHITECTURE IS "FrameBuffer,blk_mem_gen_v8_3_1,{x_ipProduct=Vivado 2015.4,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=blk_mem_gen,x_ipVersion=8.3,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_FAMILY=artix7,C_XDEVICEFAMILY=artix7,C_ELABORATION_DIR=./,C_INTERFACE_TYPE=0,C_AXI_TYPE=1,C_AXI_SLAVE_TYPE=0,C_USE_BRAM_BLOCK=0,C_ENABLE_32BIT_ADDRESS=0,C_CTRL_ECC_ALGO=NONE,C_HAS_AXI_ID=0,C_AXI_ID_WIDTH=4,C_MEM_TYPE=2,C_BYTE_SIZE=8,C_ALGORITHM=1,C_PRIM_TYPE=1,C_LOAD_INIT_FILE=1,C_INIT_FILE_NAME=FrameBuffer.mif,C_INIT_FILE=FrameBuffer.mem,C_USE_DEFAULT_DATA=0,C_DEFAULT_DATA=0,C_HAS_RSTA=0,C_RST_PRIORITY_A=CE,C_RSTRAM_A=0,C_INITA_VAL=0,C_HAS_ENA=1,C_HAS_REGCEA=0,C_USE_BYTE_WEA=1,C_WEA_WIDTH=1,C_WRITE_MODE_A=WRITE_FIRST,C_WRITE_WIDTH_A=8,C_READ_WIDTH_A=8,C_WRITE_DEPTH_A=10240,C_READ_DEPTH_A=10240,C_ADDRA_WIDTH=14,C_HAS_RSTB=0,C_RST_PRIORITY_B=CE,C_RSTRAM_B=0,C_INITB_VAL=0,C_HAS_ENB=0,C_HAS_REGCEB=0,C_USE_BYTE_WEB=1,C_WEB_WIDTH=1,C_WRITE_MODE_B=WRITE_FIRST,C_WRITE_WIDTH_B=8,C_READ_WIDTH_B=8,C_WRITE_DEPTH_B=10240,C_READ_DEPTH_B=10240,C_ADDRB_WIDTH=14,C_HAS_MEM_OUTPUT_REGS_A=0,C_HAS_MEM_OUTPUT_REGS_B=1,C_HAS_MUX_OUTPUT_REGS_A=0,C_HAS_MUX_OUTPUT_REGS_B=0,C_MUX_PIPELINE_STAGES=0,C_HAS_SOFTECC_INPUT_REGS_A=0,C_HAS_SOFTECC_OUTPUT_REGS_B=0,C_USE_SOFTECC=0,C_USE_ECC=0,C_EN_ECC_PIPE=0,C_HAS_INJECTERR=0,C_SIM_COLLISION_CHECK=ALL,C_COMMON_CLK=0,C_DISABLE_WARN_BHV_COLL=0,C_EN_SLEEP_PIN=0,C_USE_URAM=0,C_EN_RDADDRA_CHG=0,C_EN_RDADDRB_CHG=0,C_EN_DEEPSLEEP_PIN=0,C_EN_SHUTDOWN_PIN=0,C_EN_SAFETY_CKT=0,C_DISABLE_WARN_BHV_RANGE=0,C_COUNT_36K_BRAM=2,C_COUNT_18K_BRAM=1,C_EST_POWER_SUMMARY=Estimated Power for IP _ 4.61856 mW}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clka: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA CLK";
ATTRIBUTE X_INTERFACE_INFO OF ena: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA EN";
ATTRIBUTE X_INTERFACE_INFO OF wea: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA WE";
ATTRIBUTE X_INTERFACE_INFO OF addra: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dina: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DIN";
ATTRIBUTE X_INTERFACE_INFO OF douta: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTA DOUT";
ATTRIBUTE X_INTERFACE_INFO OF clkb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB CLK";
ATTRIBUTE X_INTERFACE_INFO OF web: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB WE";
ATTRIBUTE X_INTERFACE_INFO OF addrb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB ADDR";
ATTRIBUTE X_INTERFACE_INFO OF dinb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DIN";
ATTRIBUTE X_INTERFACE_INFO OF doutb: SIGNAL IS "xilinx.com:interface:bram:1.0 BRAM_PORTB DOUT";
BEGIN
U0 : blk_mem_gen_v8_3_1
GENERIC MAP (
C_FAMILY => "artix7",
C_XDEVICEFAMILY => "artix7",
C_ELABORATION_DIR => "./",
C_INTERFACE_TYPE => 0,
C_AXI_TYPE => 1,
C_AXI_SLAVE_TYPE => 0,
C_USE_BRAM_BLOCK => 0,
C_ENABLE_32BIT_ADDRESS => 0,
C_CTRL_ECC_ALGO => "NONE",
C_HAS_AXI_ID => 0,
C_AXI_ID_WIDTH => 4,
C_MEM_TYPE => 2,
C_BYTE_SIZE => 8,
C_ALGORITHM => 1,
C_PRIM_TYPE => 1,
C_LOAD_INIT_FILE => 1,
C_INIT_FILE_NAME => "FrameBuffer.mif",
C_INIT_FILE => "FrameBuffer.mem",
C_USE_DEFAULT_DATA => 0,
C_DEFAULT_DATA => "0",
C_HAS_RSTA => 0,
C_RST_PRIORITY_A => "CE",
C_RSTRAM_A => 0,
C_INITA_VAL => "0",
C_HAS_ENA => 1,
C_HAS_REGCEA => 0,
C_USE_BYTE_WEA => 1,
C_WEA_WIDTH => 1,
C_WRITE_MODE_A => "WRITE_FIRST",
C_WRITE_WIDTH_A => 8,
C_READ_WIDTH_A => 8,
C_WRITE_DEPTH_A => 10240,
C_READ_DEPTH_A => 10240,
C_ADDRA_WIDTH => 14,
C_HAS_RSTB => 0,
C_RST_PRIORITY_B => "CE",
C_RSTRAM_B => 0,
C_INITB_VAL => "0",
C_HAS_ENB => 0,
C_HAS_REGCEB => 0,
C_USE_BYTE_WEB => 1,
C_WEB_WIDTH => 1,
C_WRITE_MODE_B => "WRITE_FIRST",
C_WRITE_WIDTH_B => 8,
C_READ_WIDTH_B => 8,
C_WRITE_DEPTH_B => 10240,
C_READ_DEPTH_B => 10240,
C_ADDRB_WIDTH => 14,
C_HAS_MEM_OUTPUT_REGS_A => 0,
C_HAS_MEM_OUTPUT_REGS_B => 1,
C_HAS_MUX_OUTPUT_REGS_A => 0,
C_HAS_MUX_OUTPUT_REGS_B => 0,
C_MUX_PIPELINE_STAGES => 0,
C_HAS_SOFTECC_INPUT_REGS_A => 0,
C_HAS_SOFTECC_OUTPUT_REGS_B => 0,
C_USE_SOFTECC => 0,
C_USE_ECC => 0,
C_EN_ECC_PIPE => 0,
C_HAS_INJECTERR => 0,
C_SIM_COLLISION_CHECK => "ALL",
C_COMMON_CLK => 0,
C_DISABLE_WARN_BHV_COLL => 0,
C_EN_SLEEP_PIN => 0,
C_USE_URAM => 0,
C_EN_RDADDRA_CHG => 0,
C_EN_RDADDRB_CHG => 0,
C_EN_DEEPSLEEP_PIN => 0,
C_EN_SHUTDOWN_PIN => 0,
C_EN_SAFETY_CKT => 0,
C_DISABLE_WARN_BHV_RANGE => 0,
C_COUNT_36K_BRAM => "2",
C_COUNT_18K_BRAM => "1",
C_EST_POWER_SUMMARY => "Estimated Power for IP : 4.61856 mW"
)
PORT MAP (
clka => clka,
rsta => '0',
ena => ena,
regcea => '0',
wea => wea,
addra => addra,
dina => dina,
douta => douta,
clkb => clkb,
rstb => '0',
enb => '0',
regceb => '0',
web => web,
addrb => addrb,
dinb => dinb,
doutb => doutb,
injectsbiterr => '0',
injectdbiterr => '0',
eccpipece => '0',
sleep => '0',
deepsleep => '0',
shutdown => '0',
s_aclk => '0',
s_aresetn => '0',
s_axi_awid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_awaddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_awlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_awsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_awburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_awvalid => '0',
s_axi_wdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_wstrb => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axi_wlast => '0',
s_axi_wvalid => '0',
s_axi_bready => '0',
s_axi_arid => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
s_axi_araddr => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axi_arlen => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axi_arsize => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
s_axi_arburst => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
s_axi_arvalid => '0',
s_axi_rready => '0',
s_axi_injectsbiterr => '0',
s_axi_injectdbiterr => '0'
);
END FrameBuffer_arch;
|
architecture RTL of FIFO is
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
PROC_1 : process
procedure rst_procedure is
begin
a <= (others => '0');
b <= (others => '0');
c := d;
end procedure;
begin
if a = 1 then
a <= 2;
b := 1;
if b = 1 then
a <= 2;
b := 3;
if c = 1 then
a <= 3;
b := 10;
end if;
end if;
end if;
end process;
end architecture RTL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1260.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p05n01i01260ent IS
END c08s02b00x00p05n01i01260ent;
ARCHITECTURE c08s02b00x00p05n01i01260arch OF c08s02b00x00p05n01i01260ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
severity NOTE;
assert FALSE
report "***PASSED TEST: c08s02b00x00p05n01i01260 - This test needs manual check to make sure that default value for the message ""Assertion violation"" appears."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p05n01i01260arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1260.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p05n01i01260ent IS
END c08s02b00x00p05n01i01260ent;
ARCHITECTURE c08s02b00x00p05n01i01260arch OF c08s02b00x00p05n01i01260ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
severity NOTE;
assert FALSE
report "***PASSED TEST: c08s02b00x00p05n01i01260 - This test needs manual check to make sure that default value for the message ""Assertion violation"" appears."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p05n01i01260arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1260.vhd,v 1.2 2001-10-26 16:29:39 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p05n01i01260ent IS
END c08s02b00x00p05n01i01260ent;
ARCHITECTURE c08s02b00x00p05n01i01260arch OF c08s02b00x00p05n01i01260ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
severity NOTE;
assert FALSE
report "***PASSED TEST: c08s02b00x00p05n01i01260 - This test needs manual check to make sure that default value for the message ""Assertion violation"" appears."
severity NOTE;
wait;
END PROCESS TESTING;
END c08s02b00x00p05n01i01260arch;
|
-------------------------------------------------------------------------------
-- clock_generator_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library clock_generator_0_v4_03_a;
use clock_generator_0_v4_03_a.all;
library clock_generator_v4_03_a;
use clock_generator_v4_03_a.all;
entity clock_generator_0_wrapper is
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
attribute x_core_info : STRING;
attribute x_core_info of clock_generator_0_wrapper : entity is "clock_generator_v4_03_a";
end clock_generator_0_wrapper;
architecture STRUCTURE of clock_generator_0_wrapper is
component clock_generator is
generic (
C_FAMILY : STRING;
C_DEVICE : STRING;
C_PACKAGE : STRING;
C_SPEEDGRADE : STRING
);
port (
CLKIN : in std_logic;
CLKOUT0 : out std_logic;
CLKOUT1 : out std_logic;
CLKOUT2 : out std_logic;
CLKOUT3 : out std_logic;
CLKOUT4 : out std_logic;
CLKOUT5 : out std_logic;
CLKOUT6 : out std_logic;
CLKOUT7 : out std_logic;
CLKOUT8 : out std_logic;
CLKOUT9 : out std_logic;
CLKOUT10 : out std_logic;
CLKOUT11 : out std_logic;
CLKOUT12 : out std_logic;
CLKOUT13 : out std_logic;
CLKOUT14 : out std_logic;
CLKOUT15 : out std_logic;
CLKFBIN : in std_logic;
CLKFBOUT : out std_logic;
PSCLK : in std_logic;
PSEN : in std_logic;
PSINCDEC : in std_logic;
PSDONE : out std_logic;
RST : in std_logic;
LOCKED : out std_logic
);
end component;
begin
clock_generator_0 : clock_generator
generic map (
C_FAMILY => "spartan6",
C_DEVICE => "6slx150t",
C_PACKAGE => "fgg676",
C_SPEEDGRADE => "-3"
)
port map (
CLKIN => CLKIN,
CLKOUT0 => CLKOUT0,
CLKOUT1 => CLKOUT1,
CLKOUT2 => CLKOUT2,
CLKOUT3 => CLKOUT3,
CLKOUT4 => CLKOUT4,
CLKOUT5 => CLKOUT5,
CLKOUT6 => CLKOUT6,
CLKOUT7 => CLKOUT7,
CLKOUT8 => CLKOUT8,
CLKOUT9 => CLKOUT9,
CLKOUT10 => CLKOUT10,
CLKOUT11 => CLKOUT11,
CLKOUT12 => CLKOUT12,
CLKOUT13 => CLKOUT13,
CLKOUT14 => CLKOUT14,
CLKOUT15 => CLKOUT15,
CLKFBIN => CLKFBIN,
CLKFBOUT => CLKFBOUT,
PSCLK => PSCLK,
PSEN => PSEN,
PSINCDEC => PSINCDEC,
PSDONE => PSDONE,
RST => RST,
LOCKED => LOCKED
);
end architecture STRUCTURE;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex2;
constant CFG_MEMTECH : integer := virtex2;
constant CFG_PADTECH : integer := virtex2;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex2;
constant CFG_CLKMUL : integer := (4);
constant CFG_CLKDIV : integer := (4);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 2 + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 0;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 1;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 2;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#0034#;
constant CFG_ETH_ENM : integer := 16#020000#;
constant CFG_ETH_ENL : integer := 16#000006#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 0;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 1;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 1 + 0;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- PCI interface
constant CFG_PCI : integer := 0;
constant CFG_PCIVID : integer := 16#0#;
constant CFG_PCIDID : integer := 16#0#;
constant CFG_PCIDEPTH : integer := 8;
constant CFG_PCI_MTF : integer := 1;
-- PCI arbiter
constant CFG_PCI_ARB : integer := 0;
constant CFG_PCI_ARBAPB : integer := 0;
constant CFG_PCI_ARB_NGNT : integer := 4;
-- PCI trace buffer
constant CFG_PCITBUFEN: integer := 0;
constant CFG_PCITBUF : integer := 256;
-- Spacewire interface
constant CFG_SPW_EN : integer := 0;
constant CFG_SPW_NUM : integer := 1;
constant CFG_SPW_AHBFIFO : integer := 4;
constant CFG_SPW_RXFIFO : integer := 16;
constant CFG_SPW_RMAP : integer := 0;
constant CFG_SPW_RMAPBUF : integer := 4;
constant CFG_SPW_RMAPCRC : integer := 0;
constant CFG_SPW_NETLIST : integer := 0;
constant CFG_SPW_FT : integer := 0;
constant CFG_SPW_GRSPW : integer := 2;
constant CFG_SPW_RXUNAL : integer := 0;
constant CFG_SPW_DMACHAN : integer := 1;
constant CFG_SPW_PORTS : integer := 1;
constant CFG_SPW_INPUT : integer := 2;
constant CFG_SPW_OUTPUT : integer := 0;
constant CFG_SPW_RTSAME : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 4;
-- UART 2
constant CFG_UART2_ENABLE : integer := 1;
constant CFG_UART2_FIFO : integer := 4;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#00FE#;
constant CFG_GRGPIO_WIDTH : integer := (16);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- $Id: tb_serport_uart_rx.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tb_serport_uart_rx - sim
-- Description: Test bench for serport_uart_rx
--
-- Dependencies: simlib/simclk
-- simlib/simclkcnt
-- tbd_serport_uart_rx [UUT]
--
-- To test: serport_uart_rx
--
-- Target Devices: generic
--
-- Verified (with tb_serport_uart_rx_stim.dat):
-- Date Rev Code ghdl ise Target Comment
-- 2007-11-02 93 _tsim 0.26 8.2.03 I34 xc3s1000 d:ok
-- 2007-10-21 91 _ssim 0.26 8.1.03 I27 xc3s1000 c:ok (63488 cl 15.21s)
-- 2007-10-21 91 - 0.26 - - c:ok (63488 cl 7.12s)
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-23 444 1.1 use new simclk/simclkcnt
-- 2011-10-22 417 1.0.3 now numeric_std clean
-- 2010-04-24 281 1.0.2 use direct instatiation for tbd_
-- 2008-03-24 129 1.0.1 CLK_CYCLE now 31 bits
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.slvtypes.all;
use work.simlib.all;
use work.serportlib.all;
entity tb_serport_uart_rx is
end tb_serport_uart_rx;
architecture sim of tb_serport_uart_rx is
signal CLK : slbit := '0';
signal RESET : slbit := '0';
signal CLKDIV : slv5 := slv(to_unsigned(15, 5));
signal RXSD : slbit := '1';
signal RXDATA : slv8 := (others=>'0');
signal RXVAL : slbit := '0';
signal RXERR : slbit := '0';
signal RXACT : slbit := '0';
signal CLK_STOP : slbit := '0';
signal CLK_CYCLE : integer := 0;
signal N_MON_VAL : slbit := '0';
signal N_MON_ERR : slbit := '0';
signal N_MON_DAT : slv8 := (others=>'0');
signal R_MON_VAL_1 : slbit := '0';
signal R_MON_ERR_1 : slbit := '0';
signal R_MON_DAT_1 : slv8 := (others=>'0');
signal R_MON_VAL_2 : slbit := '0';
signal R_MON_ERR_2 : slbit := '0';
signal R_MON_DAT_2 : slv8 := (others=>'0');
constant clock_period : time := 20 ns;
constant clock_offset : time := 200 ns;
constant setup_time : time := 5 ns;
constant c2out_time : time := 10 ns;
begin
CLKGEN : simclk
generic map (
PERIOD => clock_period,
OFFSET => clock_offset)
port map (
CLK => CLK,
CLK_STOP => CLK_STOP
);
CLKCNT : simclkcnt port map (CLK => CLK, CLK_CYCLE => CLK_CYCLE);
UUT : entity work.tbd_serport_uart_rx
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT
);
proc_stim: process
file fstim : text open read_mode is "tb_serport_uart_rx_stim";
variable iline : line;
variable oline : line;
variable idelta : integer := 0;
variable itxdata : slv8 := (others=>'0');
variable irxval : slbit := '0';
variable irxerr : slbit := '0';
variable irxdata : slv8 := (others=>'0');
variable ok : boolean;
variable dname : string(1 to 6) := (others=>' ');
variable irate : integer := 16;
type bit_10_array_type is array (0 to 9) of slbit;
type int_10_array_type is array (0 to 9) of integer;
variable valpuls : bit_10_array_type := (others=>'0');
variable delpuls : int_10_array_type := (others=>0);
variable npuls : integer := 0;
begin
wait for clock_offset - setup_time;
file_loop: while not endfile(fstim) loop
readline (fstim, iline);
readcomment(iline, ok);
next file_loop when ok;
readword(iline, dname, ok);
if ok then
case dname is
when ".reset" => -- .reset
write(oline, string'(".reset"));
writeline(output, oline);
RESET <= '1';
wait for clock_period;
RESET <= '0';
wait for 9*clock_period;
when ".wait " => -- .wait
read_ea(iline, idelta);
wait for idelta*clock_period;
when ".rate " => -- .rate
idelta := 0;
while RXACT='1' loop -- ensure that uart isn't active
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
read_ea(iline, irate);
wait for 2*clock_period;
CLKDIV <= slv(to_unsigned(irate-1, CLKDIV'length));
wait for 2*clock_period;
when ".xrate" => -- .xrate
read_ea(iline, irate);
when "puls " => -- puls
writetimestamp(oline, CLK_CYCLE, ": puls ");
read_ea(iline, irxval);
read_ea(iline, irxerr);
read_ea(iline, irxdata);
npuls := 0;
for i in valpuls'range loop
testempty(iline, ok);
if ok then
exit;
end if;
read_ea(iline, valpuls(i));
read_ea(iline, delpuls(i));
assert delpuls(i)>0
report "assert puls length > 0" severity failure;
npuls := npuls + 1;
write(oline, valpuls(i), right, 3);
write(oline, delpuls(i), right, 3);
end loop; -- i
writeline(output, oline);
if npuls > 0 then
N_MON_VAL <= irxval;
N_MON_ERR <= irxerr;
N_MON_DAT <= irxdata;
for i in 0 to npuls-1 loop
RXSD <= valpuls(i);
wait for clock_period;
N_MON_VAL <= '0';
wait for (delpuls(i)-1)*clock_period;
end loop; -- i
end if;
when "send " => -- send
read_ea(iline, idelta);
read_ea(iline, itxdata);
RXSD <= '1';
wait for idelta*clock_period;
writetimestamp(oline, CLK_CYCLE, ": send ");
write(oline, itxdata, right, 10);
writeline(output, oline);
N_MON_VAL <= '1';
N_MON_ERR <= '0';
N_MON_DAT <= itxdata;
RXSD <= '0'; -- start bit
wait for clock_period;
N_MON_VAL <= '0';
wait for (irate-1)*clock_period;
RXSD <= '1';
for i in itxdata'reverse_range loop -- transmit lsb first
RXSD <= itxdata(i); -- data bit
wait for irate*clock_period;
end loop;
RXSD <= '1'; -- stop bit
wait for irate*clock_period;
when others => -- unknown command
write(oline, string'("?? unknown command: "));
write(oline, dname);
writeline(output, oline);
report "aborting" severity failure;
end case;
else
report "failed to find command" severity failure;
end if;
testempty_ea(iline);
end loop; -- file_loop:
idelta := 0;
while RXACT='1' loop
wait for clock_period;
idelta := idelta + 1;
exit when idelta>3000;
end loop;
writetimestamp(oline, CLK_CYCLE, ": DONE ");
writeline(output, oline);
wait for 12*irate*clock_period;
CLK_STOP <= '1';
wait; -- suspend proc_stim forever
-- clock is stopped, sim will end
end process proc_stim;
proc_moni: process
variable oline : line;
begin
loop
wait until rising_edge(CLK);
if R_MON_VAL_1 = '1' then
if R_MON_VAL_2 = '1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, string'(" FAIL MISSING ERR="));
write(oline, R_MON_ERR_2);
write(oline, string'(" DATA="));
write(oline, R_MON_DAT_2);
writeline(output, oline);
end if;
R_MON_VAL_2 <= R_MON_VAL_1;
R_MON_ERR_2 <= R_MON_ERR_1;
R_MON_DAT_2 <= R_MON_DAT_1;
end if;
R_MON_VAL_1 <= N_MON_VAL;
R_MON_ERR_1 <= N_MON_ERR;
R_MON_DAT_1 <= N_MON_DAT;
if RXVAL='1' or RXERR='1' then
writetimestamp(oline, CLK_CYCLE, ": moni ");
write(oline, RXDATA, right, 10);
if RXERR = '1' then
write(oline, string'(" RXERR=1"));
end if;
if R_MON_VAL_2 = '0' then
write(oline, string'(" FAIL UNEXPECTED"));
else
write(oline, string'(" CHECK"));
R_MON_VAL_2 <= '0';
if R_MON_ERR_2 = '0' then
if R_MON_DAT_2 = RXDATA and
RXERR='0' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL"));
end if;
else
if RXERR = '1' then
write(oline, string'(" OK"));
else
write(oline, string'(" FAIL, RXERR=1 expected"));
end if;
end if;
end if;
writeline(output, oline);
end if;
end loop;
end process proc_moni;
end sim;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:08:31 07/07/2016
-- Design Name:
-- Module Name: key2segments - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity key2segments is
Port ( scancode : in STD_LOGIC_VECTOR(7 downto 0);
segments : out STD_LOGIC_VECTOR (6 downto 0));
end key2segments;
architecture Behavioral of key2segments is
begin
process (scancode)
begin
case scancode is
when "00010110" => segments <= "1001111"; --1
when "00011110" => segments <= "0010010"; --2
when "00100110" => segments <= "0000110"; --3
when "00100101" => segments <= "1001100"; --4
when "00101110" => segments <= "0100100"; --5
when "00110110" => segments <= "0100000"; --6
when "00111101" => segments <= "0001111"; --7
when "00111110" => segments <= "0000000"; --8
when "01000110" => segments <= "0000100"; --9
when "01000101" => segments <= "0000001"; --0
when "00011100" => segments <= "0001000"; --A
when "00110010" => segments <= "1100000"; --b
when "00100001" => segments <= "0110001"; --c
when "00100011" => segments <= "1000010"; --d
when "00100100" => segments <= "0110000"; --E
when "00101011" => segments <= "0111000"; --F
when others => segments <= "1000001"; --u;
end case;
end process;
end Behavioral;
|
entity array10 is
end entity;
architecture test of array10 is
type int_vec is array (natural range <>) of integer;
type int_vec_ptr is access int_vec;
procedure do_stuff (variable p : inout int_vec_ptr;
variable r : inout integer) is
constant orig : int_vec(1 to p'length) := p.all;
constant len : integer := p'length;
begin
deallocate(p);
p := new int_vec'(1, 2, 3); -- Changes p'length
r := 0;
for i in 1 to len loop
r := r + orig(i);
end loop;
end procedure;
begin
p1: process is
variable p : int_vec_ptr;
variable r : integer;
begin
p := new int_vec'(1, 2, 3, 4, 5);
do_stuff(p, r);
assert r = 15;
assert p.all = (1, 2, 3);
wait;
end process;
end architecture;
|
LIBRARY Ieee;
USE ieee.std_logic_1164.all;
ENTITY CLAH16bits IS
PORT (
val1,val2: IN STD_LOGIC_VECTOR(15 DOWNTO 0);
CarryIn: IN STD_LOGIC;
CarryOut: OUT STD_LOGIC;
clk: IN STD_LOGIC;
rst: IN STD_LOGIC;
SomaResult:OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
);
END CLAH16bits;
ARCHITECTURE strc_CLAH16bits of CLAH16bits is
SIGNAL Cin_sig, Cout_sig: STD_LOGIC;
SIGNAL P0_sig, P1_sig, P2_sig, P3_sig: STD_LOGIC;
SIGNAL G0_sig, G1_sig, G2_sig, G3_sig: STD_LOGIC;
SIGNAL Cout1_temp_sig, Cout2_temp_sig, Cout3_temp_sig: STD_LOGIC;
SIGNAL A_sig, B_sig, Out_sig: STD_LOGIC_VECTOR(15 DOWNTO 0);
SIGNAL SomaT1,SomaT2,SomaT3,SomaT4:STD_LOGIC_VECTOR(3 DOWNTO 0);
Component CLA4bits
PORT (
val1,val2: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
SomaResult:OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
CarryIn: IN STD_LOGIC;
P, G: OUT STD_LOGIC
);
end component;
Component Reg1Bit
PORT (
valIn: in std_logic;
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic
);
end component;
Component Reg16Bit
PORT (
valIn: in std_logic_vector(15 downto 0);
clk: in std_logic;
rst: in std_logic;
valOut: out std_logic_vector(15 downto 0)
);
end component;
Component CLGB
PORT (
P0, P1, G0, G1, Cin: IN STD_LOGIC;
Cout1, Cout2: OUT STD_LOGIC
);
end component;
BEGIN
--registradores--
Reg_CarryIn: Reg1Bit PORT MAP (
valIn=>CarryIn,
clk=>clk,
rst=>rst,
valOut=>Cin_sig
);
Reg_A: Reg16Bit PORT MAP (
valIn=>val1,
clk=>clk,
rst=>rst,
valOut=>A_sig
);
Reg_B: Reg16Bit PORT MAP (
valIn=>val2,
clk=>clk,
rst=>rst,
valOut=>B_sig
);
Reg_CarryOut: Reg1Bit PORT MAP (
valIn=>Cout_sig,
clk=>clk,
rst=>rst,
valOut=>CarryOut
);
Reg_Ssoma: Reg16Bit PORT MAP (
valIn=>Out_sig,
clk=>clk,
rst=>rst,
valOut=>SomaResult
);
Som1: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(3 DOWNTO 0),
val2(3 DOWNTO 0) => B_sig(3 DOWNTO 0),
CarryIn=>Cin_sig,
P=>P0_sig,
G=>G0_sig,
SomaResult=>SomaT1
);
CLGB1: CLGB PORT MAP(
P0=>P0_sig,
G0=>G0_sig,
P1=>P1_sig,
G1=>G1_sig,
Cin=>Cin_sig,
Cout1=>Cout1_temp_sig,
Cout2=>Cout2_temp_sig
);
Som2: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(7 DOWNTO 4),
val2(3 DOWNTO 0) => B_sig(7 DOWNTO 4),
CarryIn=>Cout1_temp_sig,
P=>P1_sig,
G=>G1_sig,
SomaResult=>SomaT2
);
Som3: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(11 DOWNTO 8),
val2(3 DOWNTO 0) => B_sig(11 DOWNTO 8),
CarryIn=>Cout2_temp_sig,
P=>P2_sig,
G=>G2_sig,
SomaResult=>SomaT3
);
CLGB2: CLGB PORT MAP(
P0=>P2_sig,
G0=>G2_sig,
P1=>P3_sig,
G1=>G3_sig,
Cin=>Cout2_temp_sig,
Cout1=>Cout3_temp_sig,
Cout2=>Cout_sig
);
Som4: CLA4bits PORT MAP(
val1(3 DOWNTO 0) => A_sig(15 DOWNTO 12),
val2(3 DOWNTO 0) => B_sig(15 DOWNTO 12),
CarryIn=>Cout3_temp_sig,
P=>P3_sig,
G=>G3_sig,
SomaResult=>SomaT4
);
Out_sig <= SomaT4 & SomaT3 & SomaT2 & SomaT1;
END strc_CLAH16bits; |
--------------------------------------------------------------------------------
-- --
-- V H D L F I L E --
-- COPYRIGHT (C) 2006 --
-- --
--------------------------------------------------------------------------------
--
-- Title : CLKGEN
-- Design : MDCT Core
-- Author : Michal Krepa
--
--------------------------------------------------------------------------------
--
-- File : CLKGEN.VHD
-- Created : Sat Mar 12 2006
--
--------------------------------------------------------------------------------
--
-- Description : Clock generator for simulation
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.numeric_std.all;
library WORK;
use WORK.MDCTTB_PKG.all;
entity CLKGEN is
port (
clk : out STD_LOGIC
);
end CLKGEN;
--**************************************************************************--
architecture SIM of CLKGEN is
signal clk_s : STD_LOGIC;
begin
----------------------------------------------------------------------------
clk_gen_proc: -- clock generator
----------------------------------------------------------------------------
process
constant PERIOD : TIME := 1 us /(CLK_FREQ_C);
begin
clk_s <= '0';
wait for PERIOD/2;
clk_s <= '1';
wait for PERIOD/2;
end process;
----------------------------------------------------------------------------
clk_drv:
----------------------------------------------------------------------------
clk <= clk_s;
end SIM;
--**************************************************************************-- |
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity altera_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of altera_pll is
component altpll
generic (
operation_mode : string := "NORMAL" ;
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
extclk0_multiply_by : positive := 1;
extclk0_divide_by : positive := 1
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
extclkena : in std_logic_vector(3 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
extclk : out std_logic_vector(3 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (5 downto 0);
signal inclk : std_logic_vector (1 downto 0);
signal extclk : std_logic_vector (3 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 2) <= (others => '0');
noclk2xgen: if (clk2xen = 0) generate clkena(1 downto 0) <= "01"; end generate;
clk2xgen: if (clk2xen /= 0) generate clkena(1 downto 0) <= "11"; end generate;
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(1); e0 <= extclk(0);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
extclk0_multiply_by => clk_mul, extclk0_divide_by => clk_div,
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => CLK_MUL2X, clk1_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk, extclkena => clkena(3 downto 0),
clk => clkout, locked => locked, extclk => extclk);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_altera_mf is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_altera_mf is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
-- altera pll
component altera_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
e0 : out std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : altera_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_altera" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_altera" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
--
-- @file sig_pkg.vhd
-- @date December, 2013
-- @author G. Roggemans <[email protected]>
-- @copyright Copyright (c) GROG [https://grog.be] 2013, All Rights Reserved
--
-- This application is free software: you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or (at your
-- option) any later version.
--
-- This application is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License
-- for more details.
--
-- You should have received a copy of the GNU Lesser General Public License
-- along with this application. If not, see <http://www.gnu.org/licenses/>.
--
--
-- Package sig
--
-- Purpose: This package defines supplemental types, subtypes,
-- constants, and functions
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
package sig_pkg is
type core_register is array (0 to 11) of STD_LOGIC_VECTOR (3 downto 0);
end sig_pkg;
package body sig_pkg is
end sig_pkg;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := virtex4;
constant CFG_MEMTECH : integer := virtex4;
constant CFG_PADTECH : integer := virtex4;
constant CFG_TRANSTECH : integer := GTP0;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := virtex4;
constant CFG_CLKMUL : integer := (7);
constant CFG_CLKDIV : integer := (5);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 1;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 1*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 0 + 0*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 8;
constant CFG_TLB_TYPE : integer := 0 + 1*2;
constant CFG_TLB_REP : integer := 0;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2 + 64*0;
constant CFG_ATBSZ : integer := 2;
constant CFG_AHBPF : integer := 0;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
constant CFG_STAT_ENABLE : integer := 0;
constant CFG_STAT_CNT : integer := 1;
constant CFG_STAT_NMAX : integer := 0;
constant CFG_STAT_DSUEN : integer := 0;
constant CFG_NP_ASI : integer := 0;
constant CFG_WRPSR : integer := 0;
constant CFG_ALTWIN : integer := 0;
constant CFG_REX : integer := 0;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- Ethernet DSU
constant CFG_DSU_ETH : integer := 1 + 0 + 0;
constant CFG_ETH_BUF : integer := 4;
constant CFG_ETH_IPM : integer := 16#C0A8#;
constant CFG_ETH_IPL : integer := 16#010a#;
constant CFG_ETH_ENM : integer := 16#020060#;
constant CFG_ETH_ENL : integer := 16#000015#;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- DDR controller
constant CFG_DDRSP : integer := 0;
constant CFG_DDRSP_INIT : integer := 0;
constant CFG_DDRSP_FREQ : integer := 100;
constant CFG_DDRSP_COL : integer := 9;
constant CFG_DDRSP_SIZE : integer := 8;
constant CFG_DDRSP_RSKEW : integer := 0;
-- Xilinx MIG
constant CFG_MIG_DDR2 : integer := 1;
constant CFG_MIG_RANKS : integer := (1);
constant CFG_MIG_COLBITS : integer := (10);
constant CFG_MIG_ROWBITS : integer := (13);
constant CFG_MIG_BANKBITS: integer := (2);
constant CFG_MIG_HMASK : integer := 16#FE0#;
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- Gaisler Ethernet core
constant CFG_GRETH : integer := 1;
constant CFG_GRETH1G : integer := 0;
constant CFG_ETH_FIFO : integer := 32;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#0000#;
constant CFG_GRGPIO_WIDTH : integer := (8);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc259.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00259ent IS
END c03s01b02x00p08n01i00259ent;
ARCHITECTURE c03s01b02x00p08n01i00259arch OF c03s01b02x00p08n01i00259ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'HIGH;
variable R : REAL := 0.0;
BEGIN
R := 2.0 * REAL(V);
V := INTEGER(R);
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00259 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00259arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc259.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00259ent IS
END c03s01b02x00p08n01i00259ent;
ARCHITECTURE c03s01b02x00p08n01i00259arch OF c03s01b02x00p08n01i00259ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'HIGH;
variable R : REAL := 0.0;
BEGIN
R := 2.0 * REAL(V);
V := INTEGER(R);
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00259 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00259arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc259.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s01b02x00p08n01i00259ent IS
END c03s01b02x00p08n01i00259ent;
ARCHITECTURE c03s01b02x00p08n01i00259arch OF c03s01b02x00p08n01i00259ent IS
BEGIN
TESTING: PROCESS
variable V : INTEGER := INTEGER'HIGH;
variable R : REAL := 0.0;
BEGIN
R := 2.0 * REAL(V);
V := INTEGER(R);
assert FALSE
report "***FAILED TEST: c03s01b02x00p08n01i00259 - Number is out of integer bounds."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s01b02x00p08n01i00259arch;
|
entity somadornbits is
generic(n: integer := 32);
port(
a, b : in bit_vector(n-1 downto 0);
te : in bit;
s : out bit_vector(n-1 downto 0);
ts : out bit
);
end entity;
architecture estrutura of somadornbits is
signal t: bit_vector(n downto 0);
begin
process(a,b,t,te)
begin
t(0) <= te;
for i in 0 to n-1 loop
s(i) <= a(i) xor (b(i) xor t(i));
t(i+1) <= (a(i) and b(i)) or (a(i) and t(i)) or (b(i) and t(i));
end loop;
ts <= t(n);
--t(0) <= te;
--s(0) <= a(0) xor b(0) xor t(0);
--t(1) <= (a(0) and b(0)) or (a(0) and t(0)) or (b(0) and t(0));
--s(1) <= a(1) xor b(1) xor t(1);
--t(2) <= (a(1) and b(1)) or (a(1) and t(1)) or (b(1) and t(1));
--ts <= t(2);
end process;
end architecture;
|
library verilog;
use verilog.vl_types.all;
entity Controller_vlg_sample_tst is
port(
CLK : in vl_logic;
D7 : in vl_logic;
D711 : in vl_logic;
D2312 : in vl_logic;
Eq : in vl_logic;
Rb : in vl_logic;
Reset : in vl_logic;
sampler_tx : out vl_logic
);
end Controller_vlg_sample_tst;
|
--===========================================================================--
-- --
-- Synthesizable Hardware Breakpoint Trap --
-- --
--===========================================================================--
--
-- File name : trap.vhd
--
-- Entity name : trap
--
-- Purpose : Implements a 8 bit address and data hardware breakpoint comparator
-- which generates an interrupt output on qualified match conditions
--
-- Dependencies : ieee.Std_Logic_1164
-- ieee.std_logic_unsigned
--
-- Author : John E. Kent
--
-- Email : [email protected]
--
-- Web : http://opencores.org/project,system09
--
-- Description : Register Memory Map
--
-- Base + $00 - Address Comparitor High Byte
-- Base + $01 - Address Comparitor Low byte
-- Base + $02 - Data Comparitor
-- Base + $03 - Control Comparitor
-- Base + $04 - Address Qualifier High Byte
-- Base + $05 - Address Qualifier Low byte
-- Base + $06 - Data Qualifier
-- Base + $07 - Control Qualifier
--
-- Address, Data and Control signals
-- must match in the Comparitor registers
-- Matches are qualified by setting a bit
-- in the Qualifier registers
--
-- Control Comparitor / Control Qualify (write)
-- b0 - r/w 1=read 0=write
-- b1 - vma 1=valid 0=invalid
-- b7 - irq output 1=match 0=mismatch
--
-- Control Qualifier Read
-- b7 - match flag
--
-- Copyright (C) 2003 - 2010 John Kent
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--===========================================================================--
-- --
-- Revision History --
-- --
--===========================================================================--
-- Version Author Date Description
-- 0.1 John Kent 2003-05-05 Initial version
-- 0.2 John kent 2010-08-09 Updated header & GPL information
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity trap is
port (
clk : in std_logic;
rst : in std_logic;
cs : in std_logic;
rw : in std_logic;
vma : in std_logic;
addr : in std_logic_vector(15 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
irq : out std_logic
);
end;
architecture trap_arch of trap is
--
-- Trap registers
--
signal comp_addr_hi : std_logic_vector(7 downto 0);
signal comp_addr_lo : std_logic_vector(7 downto 0);
signal qual_addr_hi : std_logic_vector(7 downto 0);
signal qual_addr_lo : std_logic_vector(7 downto 0);
signal comp_data : std_logic_vector(7 downto 0);
signal qual_data : std_logic_vector(7 downto 0);
signal comp_ctrl : std_logic_vector(7 downto 0);
signal qual_ctrl : std_logic_vector(7 downto 0);
signal match_flag : std_logic;
begin
--------------------------------
--
-- write control registers
--
--------------------------------
trap_write : process( clk, rst, cs, rw, addr, data_in,
comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl )
begin
if clk'event and clk = '0' then
if rst = '1' then
comp_addr_hi <= "00000000";
comp_addr_lo <= "00000000";
comp_data <= "00000000";
comp_ctrl <= "00000000";
qual_addr_hi <= "00000000";
qual_addr_lo <= "00000000";
qual_data <= "00000000";
qual_ctrl <= "00000000";
elsif cs = '1' and rw = '0' then
case addr(2 downto 0) is
when "000" =>
comp_addr_hi <= data_in;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "001" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= data_in;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "010" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= data_in;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "011" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= data_in;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "100" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= data_in;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "101" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= data_in;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
when "110" =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= data_in;
qual_ctrl <= qual_ctrl;
-- when "111" =>
when others =>
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= data_in;
end case;
else
comp_addr_hi <= comp_addr_hi;
comp_addr_lo <= comp_addr_lo;
comp_data <= comp_data;
comp_ctrl <= comp_ctrl;
qual_addr_hi <= qual_addr_hi;
qual_addr_lo <= qual_addr_lo;
qual_data <= qual_data;
qual_ctrl <= qual_ctrl;
end if;
end if;
end process;
--
-- trap data output mux
--
trap_read : process( addr,
comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl,
match_flag )
begin
case addr(2 downto 0) is
when "000" =>
data_out <= comp_addr_hi;
when "001" =>
data_out <= comp_addr_lo;
when "010" =>
data_out <= comp_data;
when "011" =>
data_out <= comp_ctrl;
when "100" =>
data_out <= qual_addr_hi;
when "101" =>
data_out <= qual_addr_lo;
when "110" =>
data_out <= qual_data;
-- when "111" =>
when others =>
data_out(6 downto 0) <= qual_ctrl(6 downto 0);
data_out(7) <= match_flag;
end case;
end process;
--
-- Trap hardware
--
trap_match : process( Clk, rst, cs, rw, addr, vma, match_flag, data_in,
comp_addr_hi, comp_addr_lo, comp_data, comp_ctrl,
qual_addr_hi, qual_addr_lo, qual_data, qual_ctrl)
variable match : std_logic;
variable match_addr_hi : std_logic;
variable match_addr_lo : std_logic;
variable match_data : std_logic;
variable match_ctrl : std_logic;
begin
match_addr_hi :=
((comp_addr_hi(7) xor addr(15) ) and qual_addr_hi(7) ) or
((comp_addr_hi(6) xor addr(14) ) and qual_addr_hi(6) ) or
((comp_addr_hi(5) xor addr(13) ) and qual_addr_hi(5) ) or
((comp_addr_hi(4) xor addr(12) ) and qual_addr_hi(4) ) or
((comp_addr_hi(3) xor addr(11) ) and qual_addr_hi(3) ) or
((comp_addr_hi(2) xor addr(10) ) and qual_addr_hi(2) ) or
((comp_addr_hi(1) xor addr( 9) ) and qual_addr_hi(1) ) or
((comp_addr_hi(0) xor addr( 8) ) and qual_addr_hi(0) );
match_addr_lo :=
((comp_addr_lo(7) xor addr( 7) ) and qual_addr_lo(7) ) or
((comp_addr_lo(6) xor addr( 6) ) and qual_addr_lo(6) ) or
((comp_addr_lo(5) xor addr( 5) ) and qual_addr_lo(5) ) or
((comp_addr_lo(4) xor addr( 4) ) and qual_addr_lo(4) ) or
((comp_addr_lo(3) xor addr( 3) ) and qual_addr_lo(3) ) or
((comp_addr_lo(2) xor addr( 2) ) and qual_addr_lo(2) ) or
((comp_addr_lo(1) xor addr( 1) ) and qual_addr_lo(1) ) or
((comp_addr_lo(0) xor addr( 0) ) and qual_addr_lo(0) );
match_data :=
((comp_data(7) xor data_in(7)) and qual_data(7) ) or
((comp_data(6) xor data_in(6)) and qual_data(6) ) or
((comp_data(5) xor data_in(5)) and qual_data(5) ) or
((comp_data(4) xor data_in(4)) and qual_data(4) ) or
((comp_data(3) xor data_in(3)) and qual_data(3) ) or
((comp_data(2) xor data_in(2)) and qual_data(2) ) or
((comp_data(1) xor data_in(1)) and qual_data(1) ) or
((comp_data(0) xor data_in(0)) and qual_data(0) );
match_ctrl :=
((comp_ctrl(0) xor rw ) and qual_ctrl(0) ) or
((comp_ctrl(1) xor vma ) and qual_ctrl(1) );
match := not ( match_addr_hi or match_addr_lo or match_data or match_ctrl);
if rst = '1' then
match_flag <= '0';
elsif clk'event and clk = '0' then
if cs = '1' and rw = '0' then
match_flag <= '0';
else
if match = comp_ctrl(7) then
match_flag <= '1';
end if;
end if;
end if;
irq <= match_flag and qual_ctrl(7);
end process;
end trap_arch;
|
-------------------------------------------------------------------------------
--
-- (c) Copyright 2001, 2002, 2003, 2004, 2005, 2007, 2008, 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------
-- Project : Spartan-6 Integrated Block for PCI Express
-- File : pcie_app_s6.vhd
-- Description: PCI Express Endpoint sample application design.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity pcie_app_s6 is
port (
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
-- Tx
trn_tbuf_av : in std_logic_vector(5 downto 0);
trn_tcfg_req_n : in std_logic;
trn_terr_drop_n : in std_logic;
trn_tdst_rdy_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_terrfwd_n : out std_logic;
trn_tcfg_gnt_n : out std_logic;
trn_tstr_n : out std_logic;
-- Rx
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rerrfwd_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
trn_rnp_ok_n : out std_logic;
-- Flow Control
trn_fc_cpld : in std_logic_vector(11 downto 0);
trn_fc_cplh : in std_logic_vector(7 downto 0);
trn_fc_npd : in std_logic_vector(11 downto 0);
trn_fc_nph : in std_logic_vector(7 downto 0);
trn_fc_pd : in std_logic_vector(11 downto 0);
trn_fc_ph : in std_logic_vector(7 downto 0);
trn_fc_sel : out std_logic_vector(2 downto 0);
cfg_do : in std_logic_vector(31 downto 0);
cfg_rd_wr_done_n : in std_logic;
cfg_dwaddr : out std_logic_vector(9 downto 0);
cfg_rd_en_n : out std_logic;
cfg_err_cor_n : out std_logic;
cfg_err_ur_n : out std_logic;
cfg_err_ecrc_n : out std_logic;
cfg_err_cpl_timeout_n : out std_logic;
cfg_err_cpl_abort_n : out std_logic;
cfg_err_posted_n : out std_logic;
cfg_err_locked_n : out std_logic;
cfg_err_tlp_cpl_header : out std_logic_vector(47 downto 0);
cfg_err_cpl_rdy_n : in std_logic;
cfg_interrupt_n : out std_logic;
cfg_interrupt_rdy_n : in std_logic;
cfg_interrupt_assert_n : out std_logic;
cfg_interrupt_di : out std_logic_vector(7 downto 0);
cfg_interrupt_do : in std_logic_vector(7 downto 0);
cfg_interrupt_mmenable : in std_logic_vector(2 downto 0);
cfg_interrupt_msienable : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_trn_pending_n : out std_logic;
cfg_pm_wake_n : out std_logic;
cfg_bus_number : in std_logic_vector(7 downto 0);
cfg_device_number : in std_logic_vector(4 downto 0);
cfg_function_number : in std_logic_vector(2 downto 0);
cfg_status : in std_logic_vector(15 downto 0);
cfg_command : in std_logic_vector(15 downto 0);
cfg_dstatus : in std_logic_vector(15 downto 0);
cfg_dcommand : in std_logic_vector(15 downto 0);
cfg_lstatus : in std_logic_vector(15 downto 0);
cfg_lcommand : in std_logic_vector(15 downto 0);
cfg_pcie_link_state_n : in std_logic_vector(2 downto 0);
cfg_dsn : out std_logic_vector(63 downto 0)
);
end pcie_app_s6;
architecture rtl of pcie_app_s6 is
component PIO is
port (
trn_clk : in std_logic;
trn_reset_n : in std_logic;
trn_lnk_up_n : in std_logic;
trn_td : out std_logic_vector(31 downto 0);
trn_tsof_n : out std_logic;
trn_teof_n : out std_logic;
trn_tsrc_rdy_n : out std_logic;
trn_tsrc_dsc_n : out std_logic;
trn_tdst_rdy_n : in std_logic;
trn_tdst_dsc_n : in std_logic;
trn_rd : in std_logic_vector(31 downto 0);
trn_rsof_n : in std_logic;
trn_reof_n : in std_logic;
trn_rsrc_rdy_n : in std_logic;
trn_rsrc_dsc_n : in std_logic;
trn_rbar_hit_n : in std_logic_vector(6 downto 0);
trn_rdst_rdy_n : out std_logic;
cfg_to_turnoff_n : in std_logic;
cfg_turnoff_ok_n : out std_logic;
cfg_completer_id : in std_logic_vector(15 downto 0);
cfg_bus_mstr_enable : in std_logic
);
end component PIO;
constant PCI_EXP_EP_OUI : std_logic_vector(23 downto 0) := x"000A35";
constant PCI_EXP_EP_DSN_1 : std_logic_vector(31 downto 0) := x"01" & PCI_EXP_EP_OUI;
constant PCI_EXP_EP_DSN_2 : std_logic_vector(31 downto 0) := x"00000001";
signal cfg_completer_id : std_logic_vector(15 downto 0);
signal cfg_bus_mstr_enable : std_logic;
begin
--
-- Core input tie-offs
--
trn_fc_sel <= "000";
trn_rnp_ok_n <= '0';
trn_terrfwd_n <= '1';
trn_tcfg_gnt_n <= '0';
cfg_err_cor_n <= '1';
cfg_err_ur_n <= '1';
cfg_err_ecrc_n <= '1';
cfg_err_cpl_timeout_n <= '1';
cfg_err_cpl_abort_n <= '1';
cfg_err_posted_n <= '0';
cfg_err_locked_n <= '1';
cfg_pm_wake_n <= '1';
cfg_trn_pending_n <= '1';
trn_tstr_n <= '0';
cfg_interrupt_assert_n <= '1';
cfg_interrupt_n <= '1';
cfg_interrupt_di <= x"00";
cfg_err_tlp_cpl_header <= (OTHERS => '0');
cfg_dwaddr <= (OTHERS => '0');
cfg_rd_en_n <= '1';
cfg_dsn <= PCI_EXP_EP_DSN_2 & PCI_EXP_EP_DSN_1;
--
-- Programmed I/O Module
--
cfg_completer_id <= cfg_bus_number & cfg_device_number & cfg_function_number;
cfg_bus_mstr_enable <= cfg_command(2);
PIO_i : PIO
port map (
trn_clk => trn_clk, -- I
trn_reset_n => trn_reset_n, -- I
trn_lnk_up_n => trn_lnk_up_n, -- I
trn_td => trn_td, -- O [31:0]
trn_tsof_n => trn_tsof_n, -- O
trn_teof_n => trn_teof_n, -- O
trn_tsrc_rdy_n => trn_tsrc_rdy_n, -- O
trn_tsrc_dsc_n => trn_tsrc_dsc_n, -- O
trn_tdst_rdy_n => trn_tdst_rdy_n, -- I
trn_tdst_dsc_n => '1', -- I
trn_rd => trn_rd, -- I [31:0]
trn_rsof_n => trn_rsof_n, -- I
trn_reof_n => trn_reof_n, -- I
trn_rsrc_rdy_n => trn_rsrc_rdy_n, -- I
trn_rsrc_dsc_n => trn_rsrc_dsc_n, -- I
trn_rdst_rdy_n => trn_rdst_rdy_n, -- O
trn_rbar_hit_n => trn_rbar_hit_n, -- I [6:0]
cfg_to_turnoff_n => cfg_to_turnoff_n, -- I
cfg_turnoff_ok_n => cfg_turnoff_ok_n, -- O
cfg_completer_id => cfg_completer_id, -- I [15:0]
cfg_bus_mstr_enable => cfg_bus_mstr_enable -- I
);
end rtl;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: user.org:user:axi_nic:1.0
-- IP Revision: 11
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY sys_axi_nic_0_0 IS
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END sys_axi_nic_0_0;
ARCHITECTURE sys_axi_nic_0_0_arch OF sys_axi_nic_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF sys_axi_nic_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT nic_v1_0 IS
GENERIC (
C_S00_AXI_DATA_WIDTH : INTEGER;
C_S00_AXI_ADDR_WIDTH : INTEGER;
USE_1K_NOT_4K_FIFO_DEPTH : BOOLEAN
);
PORT (
RX_DATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
RX_VALID : IN STD_LOGIC;
RX_READY : OUT STD_LOGIC;
TX_DATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
TX_VALID : OUT STD_LOGIC;
TX_READY : IN STD_LOGIC;
s00_axi_aclk : IN STD_LOGIC;
s00_axi_aresetn : IN STD_LOGIC;
s00_axi_awaddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_awprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_awvalid : IN STD_LOGIC;
s00_axi_awready : OUT STD_LOGIC;
s00_axi_wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_wstrb : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
s00_axi_wvalid : IN STD_LOGIC;
s00_axi_wready : OUT STD_LOGIC;
s00_axi_bresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_bvalid : OUT STD_LOGIC;
s00_axi_bready : IN STD_LOGIC;
s00_axi_araddr : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
s00_axi_arprot : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
s00_axi_arvalid : IN STD_LOGIC;
s00_axi_arready : OUT STD_LOGIC;
s00_axi_rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
s00_axi_rresp : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
s00_axi_rvalid : OUT STD_LOGIC;
s00_axi_rready : IN STD_LOGIC
);
END COMPONENT nic_v1_0;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF sys_axi_nic_0_0_arch: ARCHITECTURE IS "nic_v1_0,Vivado 2016.4";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF sys_axi_nic_0_0_arch : ARCHITECTURE IS "sys_axi_nic_0_0,nic_v1_0,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF RX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF RX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF RX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 RX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF TX_DATA: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TDATA";
ATTRIBUTE X_INTERFACE_INFO OF TX_VALID: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TVALID";
ATTRIBUTE X_INTERFACE_INFO OF TX_READY: SIGNAL IS "xilinx.com:interface:axis:1.0 TX TREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 s00_axi_aclk CLK";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_aresetn: SIGNAL IS "xilinx.com:signal:reset:1.0 s00_axi_aresetn RST";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awaddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_awready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wstrb: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_wready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi WREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_bready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi BREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_araddr: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arprot: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_arready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rdata: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RDATA";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rresp: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RRESP";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rvalid: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RVALID";
ATTRIBUTE X_INTERFACE_INFO OF s00_axi_rready: SIGNAL IS "xilinx.com:interface:aximm:1.0 s00_axi RREADY";
BEGIN
U0 : nic_v1_0
GENERIC MAP (
C_S00_AXI_DATA_WIDTH => 32,
C_S00_AXI_ADDR_WIDTH => 5,
USE_1K_NOT_4K_FIFO_DEPTH => false
)
PORT MAP (
RX_DATA => RX_DATA,
RX_VALID => RX_VALID,
RX_READY => RX_READY,
TX_DATA => TX_DATA,
TX_VALID => TX_VALID,
TX_READY => TX_READY,
s00_axi_aclk => s00_axi_aclk,
s00_axi_aresetn => s00_axi_aresetn,
s00_axi_awaddr => s00_axi_awaddr,
s00_axi_awprot => s00_axi_awprot,
s00_axi_awvalid => s00_axi_awvalid,
s00_axi_awready => s00_axi_awready,
s00_axi_wdata => s00_axi_wdata,
s00_axi_wstrb => s00_axi_wstrb,
s00_axi_wvalid => s00_axi_wvalid,
s00_axi_wready => s00_axi_wready,
s00_axi_bresp => s00_axi_bresp,
s00_axi_bvalid => s00_axi_bvalid,
s00_axi_bready => s00_axi_bready,
s00_axi_araddr => s00_axi_araddr,
s00_axi_arprot => s00_axi_arprot,
s00_axi_arvalid => s00_axi_arvalid,
s00_axi_arready => s00_axi_arready,
s00_axi_rdata => s00_axi_rdata,
s00_axi_rresp => s00_axi_rresp,
s00_axi_rvalid => s00_axi_rvalid,
s00_axi_rready => s00_axi_rready
);
END sys_axi_nic_0_0_arch;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 22:35:46 07/17/2015
-- Design Name:
-- Module Name: C:/Users/rccoder/ALU/Lab3/ctrl_tb.vhd
-- Project Name: Lab3
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ctrl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ctrl_tb IS
END ctrl_tb;
ARCHITECTURE behavior OF ctrl_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ctrl
PORT(
d9 : IN std_logic;
d11 : IN std_logic;
sq7 : IN std_logic;
sq6 : IN std_logic;
rq : IN std_logic_vector(7 downto 0);
clrn : INOUT std_logic;
start : OUT std_logic;
serial : IN std_logic;
clk : IN std_logic;
csn : IN std_logic;
wrn : IN std_logic;
rdn : IN std_logic;
addr : IN std_logic_vector(1 downto 0);
data : INOUT std_logic_vector(7 downto 0);
intn : OUT std_logic
);
END COMPONENT;
--Inputs
signal d9 : std_logic := '0';
signal d11 : std_logic := '0';
signal sq7 : std_logic := '0';
signal sq6 : std_logic := '0';
signal rq : std_logic_vector(7 downto 0) := (others => '0');
signal serial : std_logic := '0';
signal clk : std_logic := '0';
signal csn : std_logic := '0';
signal wrn : std_logic := '0';
signal rdn : std_logic := '0';
signal addr : std_logic_vector(1 downto 0) := (others => '0');
--BiDirs
signal clrn : std_logic;
signal data : std_logic_vector(7 downto 0);
--Outputs
signal start : std_logic;
signal intn : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ctrl PORT MAP (
d9 => d9,
d11 => d11,
sq7 => sq7,
sq6 => sq6,
rq => rq,
clrn => clrn,
start => start,
serial => serial,
clk => clk,
csn => csn,
wrn => wrn,
rdn => rdn,
addr => addr,
data => data,
intn => intn
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wrn<='1';
addr<="00";
rq<="00001111";
d9<='1';
d11<='0';
sq6<='1';
sq7<='1';
rdn<='1';
wait for 50 ns;
rdn<='0';
wait for 50 ns;
addr<="01";
rdn<='0';
wrn<='1';
d11<='1';
wait for 50 ns;
wrn<='0';
d11<='0';
d9 <= '0';
wait for 50 ns;
d9<='1';
wait for 50 ns;
addr<="10";
wait for 50 ns;
addr<="01";
wrn<='1';
wait for 50 ns;
d11<='1';
wait for 50 ns;
wrn<='0';
addr<="00";
wait for 50 ns;
wrn<='1';
addr<="01";
wait for 50 ns;
wrn<='0';
addr<="11";
wait for 50 ns;
addr<="01";
-- insert stimulus here
wait;
end process;
END;
|
-- Testbench for Filters H_a1-4(z)
-- Uses a sine sweep as stimuli
--
-- This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation; either version 3 of the License, or (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program;
-- if not, see <http://www.gnu.org/licenses/>.
library ieee;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.analytic_filter_h_a1_pkg.all;
use work.analytic_filter_h_a2_pkg.all;
use work.analytic_filter_h_a3_pkg.all;
use work.analytic_filter_h_a4_pkg.all;
entity analytic_filter_tb is
generic(
clk_period : time := 10 ns;
input_data_width : integer := 16;
output_data_width : integer := 16;
filter_delay_in_clks : integer := 7; --delay of hilbert filter
data_width : integer := 16
);
end analytic_filter_tb;
architecture analytic_filter_tb_arch of analytic_filter_tb is
signal x : std_logic_vector(input_data_width-1 downto 0) := (others => '0'); --input
signal i,q : std_logic_vector(output_data_width-1 downto 0); --output
signal i_real,q_real : real;
signal x_real : real;
signal anal_data_i : std_logic_vector(input_data_width-1 downto 0);
signal clk : std_logic := '0';
signal rst : std_logic;
type filter_in_table is array (0 to 1034) of std_logic_vector(15 downto 0);
-- sine sweep
constant filter_in_force : filter_in_table :=
(
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F68"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F0D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D02"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A79"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78BC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"769F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7416"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7116"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6D93"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64D6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"598B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"52DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"434B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3A68"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"30CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2679"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B7F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FEC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"03D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F751"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA82"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DD8B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D098"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C3D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B781"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ABCC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0F5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"973D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8EE4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"882C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8353"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8092"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8220"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86B8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"97D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A450"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B334"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C445"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D731"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EB8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"00D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"167D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2BDA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"403C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"52ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6336"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7067"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79DF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F16"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B4F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7205"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"63F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5174"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B2D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"21F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EAFC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CFCB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B6A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FDB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"84A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8012"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8CA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9D8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B4AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D0C5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1110"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3124"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6620"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"76FA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E28"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7359"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F67"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"43A0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"220B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FD49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D863"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B68F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9AE7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"881B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"842D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9413"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AEA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D193"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F985"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"227F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4837"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6687"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7793"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"615E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3F93"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"15ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E947"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A66"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A483"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CB45"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F99D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2936"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"534A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"719F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F76"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B9C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AF3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D835"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8C4E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8010"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8940"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A6C3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D3EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"091C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D09"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"664B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D1B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CDD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6523"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"39FC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"035B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CBBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E1D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82C7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9B7C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C958"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"030C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3C71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"690F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EDA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"788B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"570B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"217E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E3E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC88"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8896"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8107"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"982E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0791"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"44AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"70AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E20"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3F3F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FF51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF3C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"906C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8006"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9319"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C4DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"489A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74CD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6387"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2A25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E3B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A59D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8327"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8789"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B1F6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F579"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3CB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"707C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"644F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2751"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DCBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9DDF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FB4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C665"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"11D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5729"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7596"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"427D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F660"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83C7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8977"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BD0F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0B04"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"54F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D62"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3B06"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA0E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A1D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"807A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9488"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D62B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"29ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5AED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0E39"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BAE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8655"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"88C0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C1B6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"179A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62D5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"60C0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1349"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BC47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85C6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AC6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"237F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C0A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E59"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5081"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F944"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"801F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9DF7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EFB7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A67"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"20DC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C29A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8602"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D4E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"352D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7775"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"755D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2F64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8916"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D217"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3543"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7890"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"72BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C26F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"843C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E6E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F00"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"61D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A4F2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8033"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"14EF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C4A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7AD7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3607"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CC1A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"859C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"93B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED52"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5449"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"50D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E7B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FD3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8906"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D8FC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"45C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F4C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A53"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9396"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"875D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D710"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4658"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F9B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E908"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DEF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8CD3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E756"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55CB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F6C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"41EF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE96"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"837D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9EE4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E0B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"750F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1948"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A7D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8172"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C7A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3EB0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F80"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"510B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CAA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0C6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"713E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"08E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9987"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"881F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E571"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5B9D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2872"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AE1B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"814B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A26"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"396C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BB15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8014"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C308"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4281"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8014"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C529"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"467D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3515"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B354"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8155"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D40C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5535"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A08C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8849"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F14F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6A71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FA75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B33"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9D15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1D08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CB8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5075"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C953"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C86D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5095"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"185B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"980F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0BEE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"791F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5727"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CD8B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8001"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CBEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"56B3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78B1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F50"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2883"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FB5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3825"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA56"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"87E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FCD2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"75EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"592F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8047"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DA9B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6570"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6C8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E5F2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"815A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C370"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7649"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F920"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"850B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B641"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02DA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8770"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B187"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47E9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7AD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02F3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86D6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B487"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4C8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7879"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F96B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFBB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"583C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7193"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E66D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"805A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D490"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6885"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CB18"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F458"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7872"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AAFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E89"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1E51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1DEF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8DD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADA0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4CEA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E69F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8006"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E264"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7383"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4DE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC86"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9022"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"26BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"84C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C6ED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6620"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5E5E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BBB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8978"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8A7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6948"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"582A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B19A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9051"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2DA6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CDD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F580"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8031"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E808"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"798A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"374F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9458"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AE34"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5814"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"666D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BF3C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B2B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1F6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8002"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F579"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E12"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2138"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"87AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA8F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FB2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9AE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5952"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6140"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B2EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"957C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"40F7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"718C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8951"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2ABE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A48"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DEC7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8351"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1905"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E31"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EDC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0CED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F6DD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"803D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F9D9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8029"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"06F8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F6AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"807B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0D35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81E1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"197B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DE3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85E6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2B5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"766B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C9EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8ED4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"41B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6A04"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B229"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"54A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA1C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"704A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3448"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"873C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E01A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E4E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0912"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8009"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0F96"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CD4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D6E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8BDF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4244"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6557"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A699"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFAA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CB1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3584"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EA13"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F357"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2FC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFC0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A999"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6AA8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3515"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8484"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FBB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E22C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46A6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C6E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"982B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C98F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BFD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8128"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"29B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA1E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B4B2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A57"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8001"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1CBE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7360"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B049"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B067"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73C5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A58"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"800E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"21F8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FA5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A825"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BB61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"79BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"827E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"389D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6017"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"951D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D895"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E231"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9084"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5B64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3C5B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82A4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0B25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"76D5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AFC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B863"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A9D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE23"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"86A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4BEA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4A80"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85DA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0232"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B0C1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA8E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C4F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F3DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8BDB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"599D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"37BB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6981"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"973D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E00E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C54C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB12"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7814"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FD49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8A0F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5A05"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"32A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8007"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2E47"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C87"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8AB6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE54"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7671"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A4BA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D1D7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FE3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C7A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADC3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B18"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ED78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9454"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BBC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"11A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8598"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"55D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3140"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8028"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3CF1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23F7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5E2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"886B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0CD6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6BDC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"91A0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F8BB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"74DB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9BB0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E834"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A50"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB63"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD34"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D22E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EC8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B2FF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CC64"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F62"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B630"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C9D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F88"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B696"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CA75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B429"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D555"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D33"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A7A1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DFEC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A16"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E73"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EE2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7478"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"946A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"001F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6B3F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8ACE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"157E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5D49"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8350"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2D85"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"499B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8004"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46BC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2FAE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8339"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5ED9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0FC9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8F2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"72B0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EB6B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A58F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C59B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C6CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A306"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F14F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"89AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"20F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E0A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4EC6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1EF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B44"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"71A3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E742"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AD7F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B180"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E35A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7293"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8B02"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"22E5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"480A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5C45"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"07A8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A08"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D32"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C20E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D464"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"772F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2019"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"46EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"815B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"62CB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F99C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A616"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC27"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F287"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6601"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81BE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"47BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1B05"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"931B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7C13"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFF8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DDA4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6FF0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"851A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3D78"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23B5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9022"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B5C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BFB9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E0E4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6CAC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4837"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1468"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9A6C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F5E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FC99"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5935"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6382"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EC3B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BA22"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7B91"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D72"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3010"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2A25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D89"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B13A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FA2E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5754"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80E2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6AF2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB11"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE14"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"718C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"82BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5063"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"004A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF76"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D0E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8D27"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3703"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1C2F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9CEB"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"98B7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"23F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2DDE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F7E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A0B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"197B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3607"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FCA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EF3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A2CF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1858"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3555"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"911C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F75"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9E73"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"209A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2BB7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"97C4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"94C8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"31B9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"186F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A5FA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"88F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"49EA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FAED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BEED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7243"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64DC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D485"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E527"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8411"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7A6D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AAC2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"17A9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2C5D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9C79"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EA2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"895A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E51"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EEF4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CF8D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"64D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8166"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7795"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADE6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1820"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A2DD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7BC1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8390"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5F8A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D3A2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EF30"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"49C9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E46"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FFF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8E15"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B11"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EBBA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D97E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58D8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"878B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"93C3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"43CA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F1BF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D64A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5955"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"883E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FA7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4C25"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E51D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E536"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4B71"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"912D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F38"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"85B6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"614C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C747"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0762"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2AC5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AA10"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78F4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9F7E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3A65"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F3AE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DCE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4D63"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9319"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DBF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"81F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6E35"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AF6B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2933"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"02E3"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D1BD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"53D2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"90A4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DFE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8197"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"70F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A899"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"34D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E456"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4142"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9FE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"755D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80AC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7D61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"58D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C5EE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"16A5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0E55"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"CE3E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"50D0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"96D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7928"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7CF5"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8EE9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5D5A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCA0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2524"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FB36"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"E481"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"39AD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AC0C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"68E0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8899"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7EED"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"80B8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"78B7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9429"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"5992"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BCF6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2987"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F19F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F2F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"278A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C016"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"553A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"9949"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"73D4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"83C2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7FD8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8148"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"791F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"908B"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"6240"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ADE6"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3FAC"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D45A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"16B4"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"FE83"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"EC9E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"275F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C5FF"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4AE2"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A64C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"663C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8FAD"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"77E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"8307"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7F94"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"802D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7DDE"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"861D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"7417"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"934E"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"63F1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"A5F0"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4F48"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"BC2C"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"37E8"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"D448"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1F6F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"ECCA"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0732"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0481"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"F038"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"1A8F"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"DB3A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"2E61"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"C8A7"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"3FA9"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"B8B1"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"4E4D"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"AB5A"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0),
to_stdlogicvector(bit_vector'(X"0000"))(15 DOWNTO 0));
begin
analytic_filter_inst : analytic_filter_h_a4 --change this to analytic_filter_h_ax to test other filters
generic map(
-- input_data_width => input_data_width, --uncomment this for analytic_filter_h_a1
-- output_data_width => output_data_width, --uncomment this for analytic_filter_h_a1
-- filter_delay_in_clks => filter_delay_in_clks --uncomment this for analytic_filter_h_a1
data_width => data_width --uncomment this for analytic_filter_h_a3-4
)
port map(
rst_i => rst,
clk_i => clk,
data_str_i => '1',
data_i => anal_data_i,
data_i_o => i,
data_q_o => q,
data_str_o => open
);
clk <= not clk after clk_period/2;
rst <= '1', '0' after 20 ns;
--choose scaling, not all filters have the full dynamic range
anal_data_i <= x;
-- anal_data_i <= std_logic_vector(shift_right(signed(x),1));
-- anal_data_i <= std_logic_vector(shift_right(signed(x),2));
x_real <= real(to_integer(signed(x)))/ 2.0**(input_data_width-1);
i_real <= real(to_integer(signed(i)))/ 2.0**(output_data_width-1);
q_real <= real(to_integer(signed(q)))/ 2.0**(output_data_width-1);
--choose imput stimuli:
-- x <= x"7FFF", x"0000" after 40 ns; --impulse response
-- x <= x"7FFF"; --step response
filter_in_gen: process
begin
x <= filter_in_force(0);
wait for clk_period*3;
x <= filter_in_force(1);
wait for clk_period;
for n in 0 to 1034 loop
if n + 2 <= 1034 then
x <= filter_in_force(n + 2);
end if;
wait for clk_period;
end loop;
assert false report "**** test complete. ****" severity note;
end process filter_in_gen;
end analytic_filter_tb_arch; |
-- This file is part of fsio, see <https://qu1x.org/fsio>.
--
-- Copyright (c) 2016 Rouven Spreckels <[email protected]>
--
-- fsio is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License version 3
-- as published by the Free Software Foundation on 19 November 2007.
--
-- fsio is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with fsio. If not, see <https://www.gnu.org/licenses>.
library ieee;
use ieee.std_logic_1164.all;
package fsio is
constant CAP: integer := 32;
constant LEN: integer := CAP;
component fsio_get is
generic (
-- Number of signals of all data maps
cap: integer := CAP;
-- Number of signals of all data maps actually being used
len: integer := LEN
);
port (
-- AXI core clock
clk: in std_logic;
-- AXI handshake input
hsi: in std_logic;
-- AXI handshake output as conditional feedback
hso: out std_logic;
-- AXI data input of all data maps
fsi: in std_logic_vector(cap - 1 downto 0);
-- AXI data output as feedback of all data maps
fso: out std_logic_vector(cap - 1 downto 0);
-- User data of all data maps to be read
dat: out std_logic_vector(len - 1 downto 0);
-- PS requests PL to read the data
-- Is set until acknowledged and the data has been fed back
req: out std_logic;
-- PL acknowledges when it has read the data
-- Must be kept set until request has been reset
ack: in std_logic
);
end component fsio_get;
component fsio_put is
generic (
-- Number of signals of all data maps
cap: integer := CAP;
-- Number of signals of all data maps actually being used
len: integer := LEN
);
port (
-- AXI core clock
clk: in std_logic;
-- AXI handshake input
hsi: in std_logic;
-- AXI handshake output as conditional feedback
hso: out std_logic;
-- AXI data input as feedback of all data maps
fsi: in std_logic_vector(cap - 1 downto 0);
-- AXI data output of all data maps
fso: out std_logic_vector(cap - 1 downto 0);
-- User data of all data maps to be written
dat: in std_logic_vector(len - 1 downto 0);
-- PS requests PL to write the data
-- Is set until acknowledged
req: out std_logic;
-- PL acknowledges when it has written the data
-- Must be set for exactly one clock cycle
ack: in std_logic
);
end component fsio_put;
end package;
|
entity 0test is end;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_mm_interconnect_0_rsp_demux_001 is
port(
sink_valid : in vl_logic_vector(0 downto 0);
sink_data : in vl_logic_vector(104 downto 0);
sink_channel : in vl_logic_vector(5 downto 0);
sink_startofpacket: in vl_logic;
sink_endofpacket: in vl_logic;
sink_ready : out vl_logic;
src0_valid : out vl_logic;
src0_data : out vl_logic_vector(104 downto 0);
src0_channel : out vl_logic_vector(5 downto 0);
src0_startofpacket: out vl_logic;
src0_endofpacket: out vl_logic;
src0_ready : in vl_logic;
src1_valid : out vl_logic;
src1_data : out vl_logic_vector(104 downto 0);
src1_channel : out vl_logic_vector(5 downto 0);
src1_startofpacket: out vl_logic;
src1_endofpacket: out vl_logic;
src1_ready : in vl_logic;
clk : in vl_logic;
reset : in vl_logic
);
end usb_system_mm_interconnect_0_rsp_demux_001;
|
-- Descp. Generate the table of all the possible pattern
--
-- entity name: g05_possibility_table
--
-- Version 1.0
-- Author: Felix Dube; [email protected] & Auguste Lalande; [email protected]
-- Date: November 2, 2015
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity g05_possibility_table is
port (
TC_EN : in std_logic; -- table counter enable
TC_RST : in std_logic; -- table counter reset
TM_IN : in std_logic; -- table memory input data
TM_EN : in std_logic; -- table memory write enable
CLK : in std_logic;
TC_LAST : out std_logic; -- last count flag
TM_ADDR : out std_logic_vector(11 downto 0);
TM_OUT : out std_logic -- table memory output
);
end g05_possibility_table;
architecture behavior of g05_possibility_table is
signal TC : std_logic_vector(11 downto 0);
signal MT : std_logic_vector(4195 downto 0);
begin
-- Table memory counter
process(CLK, TC_RST)
begin
if(TC_RST = '1') then
TC <= "000000000000";
TC_LAST <= '0';
elsif(rising_edge(CLK)) then
if(TC_EN = '1') then
if(TC(2 downto 0) = "101") then
if(TC(5 downto 3) = "101") then
if(TC(8 downto 6) = "101") then
if(TC(11 downto 9) = "101") then
TC_LAST <= '1';
TC <= "000000000000";
else
TC <= TC + 147;
end if;
else
TC <= TC + 19;
end if;
else
TC <= TC + 3;
end if;
else
TC <= TC + 1;
end if;
end if;
end if;
end process;
TM_ADDR <= TC;
-- Write in the memory table at a specific memory address
process(CLK)
begin
if(rising_edge(CLK)) then
if(TM_EN = '1') then
MT(to_integer(unsigned(TC))) <= TM_IN;
end if;
end if;
end process;
TM_OUT <= MT(to_integer(unsigned(TC)));
end behavior;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: gencomp
-- File: gencomp.vhd
-- Author: Jiri Gaisler et al. - Aeroflex Gaisler
-- Description: Declaration of portable memory modules, pads, e.t.c.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.config.grlib_config_array;
use grlib.config_types.grlib_techmap_testin_extra;
package gencomp is
---------------------------------------------------------------------------
-- BASIC DECLARATIONS
---------------------------------------------------------------------------
-- technologies and libraries
constant NTECH : integer := 54;
type tech_ability_type is array (0 to NTECH) of integer;
constant inferred : integer := 0;
constant virtex : integer := 1;
constant virtex2 : integer := 2;
constant memvirage : integer := 3;
constant axcel : integer := 4;
constant proasic : integer := 5;
constant atc18s : integer := 6;
constant altera : integer := 7;
constant umc : integer := 8;
constant rhumc : integer := 9;
constant apa3 : integer := 10;
constant spartan3 : integer := 11;
constant ihp25 : integer := 12;
constant rhlib18t : integer := 13;
constant virtex4 : integer := 14;
constant lattice : integer := 15;
constant ut25 : integer := 16;
constant spartan3e : integer := 17;
constant peregrine : integer := 18;
constant memartisan : integer := 19;
constant virtex5 : integer := 20;
constant custom1 : integer := 21;
constant ihp25rh : integer := 22;
constant stratix1 : integer := 23;
constant stratix2 : integer := 24;
constant eclipse : integer := 25;
constant stratix3 : integer := 26;
constant cyclone3 : integer := 27;
constant memvirage90 : integer := 28;
constant tsmc90 : integer := 29;
constant easic90 : integer := 30;
constant atc18rha : integer := 31;
constant smic013 : integer := 32;
constant tm65gplus : integer := 33;
constant axdsp : integer := 34;
constant spartan6 : integer := 35;
constant virtex6 : integer := 36;
constant actfus : integer := 37;
constant stratix4 : integer := 38;
constant st65lp : integer := 39;
constant st65gp : integer := 40;
constant easic45 : integer := 41;
constant cmos9sf : integer := 42;
constant apa3e : integer := 43;
constant apa3l : integer := 44;
constant ut130 : integer := 45;
constant ut90 : integer := 46;
constant gf65 : integer := 47;
constant virtex7 : integer := 48;
constant kintex7 : integer := 49;
constant artix7 : integer := 50;
constant zynq7000 : integer := 51;
constant rhlib13t : integer := 52;
constant saed32 : integer := 53;
constant dare : integer := 54;
constant DEFMEMTECH : integer := inferred;
constant DEFPADTECH : integer := inferred;
constant DEFFABTECH : integer := inferred;
constant is_fpga : tech_ability_type :=
(inferred => 1, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 1, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
constant infer_mul : tech_ability_type := is_fpga;
constant syncram_2p_write_through : tech_ability_type :=
(rhumc => 1, eclipse => 1, others => 0);
constant regfile_3p_write_through : tech_ability_type :=
(rhumc => 1, ihp25 => 1, ihp25rh => 1, eclipse => 1, others => 0);
constant regfile_3p_infer : tech_ability_type :=
(inferred => 1, rhumc => 1, ihp25 => 1, rhlib18t => 0, ut90 => 1,
peregrine => 1, ihp25rh => 1, umc => 1, custom1 => 0, others => 0);
constant syncram_2p_dest_rw_collision : tech_ability_type :=
(memartisan => 1, smic013 => 1, easic45 => 1, ut130 => 1, others => 0);
constant syncram_dp_dest_rw_collision : tech_ability_type :=
(memartisan => 1, smic013 => 1, easic45 => 1, others => 0);
constant syncram_has_customif : tech_ability_type := (others => 0);
constant syncram_customif_maxwidth: integer := 64; -- Expand as needed
constant has_sram : tech_ability_type :=
(atc18s => 0, others => 1);
constant has_2pram : tech_ability_type :=
( atc18s => 0, umc => 0, rhumc => 0, ihp25 => 0, others => 1);
constant has_dpram : tech_ability_type :=
(virtex => 1, virtex2 => 1, memvirage => 1, axcel => 0,
altera => 1, apa3 => 1, spartan3 => 1, virtex4 => 1,
lattice => 1, spartan3e => 1, memartisan => 1, virtex5 => 1,
custom1 => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
cyclone3 => 1, memvirage90 => 1, atc18rha => 1, smic013 => 1,
tm65gplus => 1, axdsp => 0, spartan6 => 1, virtex6 => 1,
actfus => 1, stratix4 => 1, easic45 => 1, apa3e => 1,
apa3l => 1, ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, dare => 1, others => 0);
constant has_sram64 : tech_ability_type :=
(inferred => 0, virtex2 => 1, spartan3 => 1, virtex4 => 1,
spartan3e => 1, memartisan => 1, virtex5 => 1, smic013 => 1,
spartan6 => 1, virtex6 => 1, easic45 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_sram128bw : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
altera => 1, cyclone3 => 1, stratix2 => 1, stratix3 => 1, stratix4 => 1,
ut90 => 1, others => 0);
constant has_sram128 : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
tm65gplus => 0, easic45 => 1, others => 0);
constant has_sram156bw : tech_ability_type := (
virtex2 => 0, virtex4 => 0, virtex5 => 0, spartan3 => 0,
spartan3e => 0, spartan6 => 0, virtex6 => 0, virtex7 => 0, kintex7 => 0,
altera => 0, cyclone3 => 0, stratix2 => 0, stratix3 => 0, stratix4 => 0,
tm65gplus => 0, custom1 => 1, ut90 => 1, others => 0);
constant has_sram256bw : tech_ability_type := (
virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1,
spartan3e => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
altera => 1, cyclone3 => 1, stratix2 => 1, stratix3 => 1, stratix4 => 1,
tm65gplus => 0, cmos9sf => 1, others => 0);
constant has_sram_2pbw : tech_ability_type := (
easic45 => 1, others => 0);
constant has_srambw : tech_ability_type := (easic45 => 1, others => 0);
constant has_2pfifo : tech_ability_type := (
altera => 1, stratix1 => 1, stratix2 => 1, stratix3 => 1,
stratix4 => 1, others => 0);
-- ram_raw_latency - describes how many edges on the write-port clock that
-- must pass before data is commited to memory. for example, if the write data
-- is commited to memory on the falling edge after a write cycle, and is
-- available to the read port after a short T_{raw} then ram_raw_latency
-- should be set to 1. If the data is available to the read port immediately
-- after the write-port clock rising edge that latches the write operation then
-- ram_raw_latency(tech) should return 0. If T_{raw} cannot be assumed to be
-- negligible (for instance, it is longer than a clock cycle on the read port)
-- then the ram_raw_latency value should be increased to cover also T_{raw}.
-- this value is important for cores that use DP or 2P memories in CDC.
constant ram_raw_latency : tech_ability_type := (easic45 => 1, others => 0);
constant padoen_polarity : tech_ability_type :=
(axcel => 1, proasic => 1, umc => 1, rhumc => 1, saed32 => 1, dare => 1, apa3 => 1,
ihp25 => 1, ut25 => 1, peregrine => 1, easic90 => 1, axdsp => 1,
actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, others => 0);
constant has_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 1, atc18s => 1, altera => 0,
umc => 1, rhumc => 1, saed32 => 1, dare => 1, apa3 => 1, spartan3 => 1,
ihp25 => 1, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, peregrine => 1, virtex5 => 1, axdsp => 1,
easic90 => 1, atc18rha => 1, spartan6 => 1, virtex6 => 1,
actfus => 1, apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_ds_pads : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, memvirage => 0,
axcel => 1, proasic => 0, atc18s => 0, altera => 0,
umc => 0, rhumc => 0, saed32 => 0, dare => 0, apa3 => 1, spartan3 => 1,
ihp25 => 0, rhlib18t => 1, virtex4 => 1, lattice => 0,
ut25 => 1, spartan3e => 1, virtex5 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1,
apa3e => 1, apa3l => 1, ut130 => 0, easic45 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_ds_combo : tech_ability_type :=
( rhumc => 1, ut25 => 1, ut130 => 1, others => 0);
constant has_clkand : tech_ability_type :=
( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1, virtex4 => 1,
virtex5 => 1, ut25 => 1, rhlib18t => 1,
spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, saed32 => 1, dare => 1, others => 0);
constant has_clkmux : tech_ability_type :=
( virtex => 1, virtex2 => 1, spartan3 => 1, spartan3e => 1,
virtex4 => 1, virtex5 => 1, rhlib18t => 1,
spartan6 => 1, virtex6 => 1, ut130 => 1, easic45 => 1,
ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, saed32 => 1, dare => 1, rhumc => 1, others => 0);
constant has_clkinv : tech_ability_type :=
( saed32 => 1, dare => 1, others => 0);
constant has_techbuf : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1, axcel => 1, ut25 => 1,
apa3 => 1, easic90 => 1, axdsp => 1, actfus => 1,
apa3e => 1, apa3l => 1, ut130 => 1, easic45 => 1,
ut90 => 1, spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant has_tapsel : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1,
spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1, others => 0);
constant tap_tck_gated : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1, spartan3 => 1, spartan3e => 1,
spartan6 => 0, others => 0);
constant need_extra_sync_reset : tech_ability_type :=
(axcel => 1, atc18s => 1, ut25 => 1, rhumc => 1, saed32 => 1, dare => 1, tsmc90 => 1,
rhlib18t => 1, atc18rha => 1, easic90 => 1, tm65gplus => 1,
axdsp => 1, cmos9sf => 1, apa3 => 1, apa3e => 1, apa3l => 1,
ut130 => 1, easic45 => 1, ut90 => 1, others => 0);
constant is_unisim : tech_ability_type :=
( virtex => 1, virtex2 => 1, virtex4 => 1, virtex5 => 1,
spartan3 => 1, spartan3e => 1,
spartan6 => 1, virtex6 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, others => 0);
constant has_tap : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, axcel => 0,
proasic => 0, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 0,
stratix3 => 1, cyclone3 => 1, axdsp => 0,
spartan6 => 1, virtex6 => 1, actfus => 1,
stratix4 => 1, easic45 => 0, apa3e => 1, apa3l => 1, virtex7 => 1, kintex7 => 1,
artix7 => 1, zynq7000 => 1,
others => 0);
constant has_clkgen : tech_ability_type :=
(inferred => 0, virtex => 1, virtex2 => 1, axcel => 1,
proasic => 1, altera => 1, apa3 => 1, spartan3 => 1,
virtex4 => 1, lattice => 0, spartan3e => 1, virtex5 => 1,
stratix1 => 1, stratix2 => 1, eclipse => 0, rhumc => 1, saed32 => 1, dare => 1,
stratix3 => 1, cyclone3 => 1, axdsp => 1,
spartan6 => 1, virtex6 => 1, actfus => 1, easic90 => 1,
stratix4 => 1, easic45 => 1, apa3e => 1, apa3l => 1,
rhlib18t => 1, ut130 => 1, ut90 => 1, virtex7 => 1, kintex7 => 1, artix7 => 1, zynq7000 => 1, others => 0);
constant has_ddr2phy: tech_ability_type :=
(inferred => 0, stratix2 => 1, stratix3 => 1, spartan3 => 1,
easic90 => 1, spartan6 => 1, easic45 => 1,
virtex4 => 1, virtex5 => 1, virtex6 => 1, others => 0);
constant ddr2phy_builtin_pads: tech_ability_type := (
-- Wrapped DDR2 IP cores with builtin pads
easic45 => 1,
-- Below techs have builtin pads for legacy reasons, can be converted if needed
easic90 => 1, spartan3 => 1, stratix3 => 1, stratix2 => 1,
others => 0);
constant ddr2phy_has_fbclk: tech_ability_type :=
(inferred => 1, others => 0);
constant ddrphy_has_fbclk: tech_ability_type :=
(others => 0);
constant ddr2phy_has_reg: tech_ability_type :=
(easic45 => 1, others => 0);
constant ddr2phy_has_custom: tech_ability_type :=
(easic45 => 1, others => 0);
constant ddr2phy_refclk_type: tech_ability_type :=
(virtex4 => 1, virtex5 => 1, virtex6 => 1, -- 1: 200 MHz reference
easic45 => 2, -- 2: 270 degree shifted clock
others => 0); -- 0: None
constant ddr2phy_has_datavalid: tech_ability_type :=
(easic45 => 1,
others => 0);
constant ddrphy_has_datavalid: tech_ability_type :=
(ut90 => 1, others => 0);
constant ddrphy_builtin_pads: tech_ability_type := (
inferred => 0,
-- Most techs have builtin pads for legacy reasons, can be converted if needed
others => 1);
constant ddrphy_latency: tech_ability_type := (
-- extra read latency, only used when not datavalid signal is available
inferred => 1,
others => 0
);
-- If the PHY passes through the control signals directly to the pads
-- and therefore needs them to be set asynchronously at reset
constant ddr2phy_ptctrl: tech_ability_type := (
inferred => 1, others => 0
);
constant ddrphy_ptctrl: tech_ability_type := (
inferred => 1, others => 0
);
constant has_syncreg: tech_ability_type := (
inferred => 0, others => 0);
-- pragma translate_off
subtype tech_description is string(1 to 10);
type tech_table_type is array (0 to NTECH) of tech_description;
-------------------------------------------------------------------------------
constant tech_table : tech_table_type := (
inferred => "inferred ", virtex => "virtex ",
virtex2 => "virtex2 ", memvirage => "virage ",
axcel => "axcel ", proasic => "proasic ",
atc18s => "atc18s ", altera => "altera ",
umc => "umc18 ", rhumc => "rhumc ",
apa3 => "proasic3 ", spartan3 => "spartan3 ",
ihp25 => "ihp25 ", rhlib18t => "rhlib18t ",
virtex4 => "virtex4 ", lattice => "lattice ",
ut25 => "ut025crh ", spartan3e => "spartan3e ",
peregrine => "peregrine ", memartisan => "artisan ",
virtex5 => "virtex5 ", custom1 => "custom1 ",
ihp25rh => "ihp25rh ", stratix1 => "stratix ",
stratix2 => "stratixii ", eclipse => "eclipse ",
stratix3 => "stratixiii", cyclone3 => "cycloneiii",
memvirage90 => "virage90 ", tsmc90 => "tsmc90 ",
easic90 => "nextreme ", atc18rha => "atc18rha ",
smic013 => "smic13 ", tm65gplus => "tm65gplus ",
axdsp => "axdsp ", spartan6 => "spartan6 ",
virtex6 => "virtex6 ", actfus => "fusion ",
stratix4 => "stratix4 ", st65lp => "st65lp ",
st65gp => "st65gp ", easic45 => "nextreme2 ",
cmos9sf => "cmos9sf ", apa3e => "proasic3e ",
apa3l => "proasic3l ", ut130 => "ut130hbd ",
ut90 => "ut90nhbd ", gf65 => "gf65g ",
virtex7 => "virtex7 ", kintex7 => "kintex7 ",
artix7 => "artix7 ", zynq7000 => "zynq7000 ",
rhlib13t => "rhlib13t ", saed32 => "saed32 ",
dare => "dare ");
-- pragma translate_on
-- input/output voltage
constant x12v : integer := 12;
constant x15v : integer := 15;
constant x18v : integer := 1;
constant x25v : integer := 2;
constant x33v : integer := 3;
constant x50v : integer := 5;
-- input/output levels
constant ttl : integer := 0;
constant cmos : integer := 1;
constant pci33 : integer := 2;
constant pci66 : integer := 3;
constant lvds : integer := 4;
constant sstl2_i : integer := 5;
constant sstl2_ii : integer := 6;
constant sstl3_i : integer := 7;
constant sstl3_ii : integer := 8;
constant sstl18_i : integer := 9;
constant sstl18_ii: integer := 10;
constant lvpecl : integer := 11;
constant sstl : integer := 12;
-- pad types
constant normal : integer := 0;
constant pullup : integer := 1;
constant pulldown : integer := 2;
constant opendrain: integer := 3;
constant schmitt : integer := 4;
constant dci : integer := 5;
---------------------------------------------------------------------------
-- MEMORY
---------------------------------------------------------------------------
-- testin vector is testen & scanen & (tech-dependent...)
constant TESTIN_WIDTH : integer := 4 + GRLIB_CONFIG_ARRAY(grlib_techmap_testin_extra);
constant testin_none : std_logic_vector(TESTIN_WIDTH-1 downto 0) := (others => '0');
-- synchronous single-port ram
component syncram
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
enable : in std_ulogic;
write : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous two-port ram (1 read, 1 write port)
component syncram_2p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous dual-port ram (2 read/write ports)
component syncram_dp
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk1 : in std_ulogic;
address1 : in std_logic_vector((abits -1) downto 0);
datain1 : in std_logic_vector((dbits -1) downto 0);
dataout1 : out std_logic_vector((dbits -1) downto 0);
enable1 : in std_ulogic;
write1 : in std_ulogic;
clk2 : in std_ulogic;
address2 : in std_logic_vector((abits -1) downto 0);
datain2 : in std_logic_vector((dbits -1) downto 0);
dataout2 : out std_logic_vector((dbits -1) downto 0);
enable2 : in std_ulogic;
write2 : in std_ulogic;
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(custombits-1 downto 0));
end component;
-- synchronous 3-port regfile (2 read, 1 write port)
component regfile_3p
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
wrfst : integer := 0; numregs : integer := 64; testen : integer := 0;
custombits : integer := 1);
port (
wclk : in std_ulogic;
waddr : in std_logic_vector((abits -1) downto 0);
wdata : in std_logic_vector((dbits -1) downto 0);
we : in std_ulogic;
rclk : in std_ulogic;
raddr1 : in std_logic_vector((abits -1) downto 0);
re1 : in std_ulogic;
rdata1 : out std_logic_vector((dbits -1) downto 0);
raddr2 : in std_logic_vector((abits -1) downto 0);
re2 : in std_ulogic;
rdata2 : out std_logic_vector((dbits -1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(2*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(2*custombits-1 downto 0));
end component;
-- 64-bit synchronous single-port ram with 32-bit write strobe
component syncram64
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (63+8*paren downto 0);
dataout : out std_logic_vector (63+8*paren downto 0);
enable : in std_logic_vector (1 downto 0);
write : in std_logic_vector (1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(2*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(2*custombits-1 downto 0));
end component;
-- 128-bit synchronous single-port ram with 32-bit write strobe
component syncram128
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0;
paren : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127+16*paren downto 0);
dataout : out std_logic_vector (127+16*paren downto 0);
enable : in std_logic_vector (3 downto 0);
write : in std_logic_vector (3 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(4*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(4*custombits-1 downto 0));
end component;
component syncramft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 3 := 0; testen : integer := 0; custombits : integer := 1 );
port (
clk : in std_ulogic;
address : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
write : in std_ulogic;
enable : in std_ulogic;
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector(((dbits + 7)/8)*2-1 downto 0) := (others => '0');
customclk: in std_ulogic := '0';
customin : in std_logic_vector(3*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(3*custombits-1 downto 0));
end component;
component syncram_2pft
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; ft : integer := 0;
testen : integer := 0; words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_ulogic;
raddress : in std_logic_vector((abits -1) downto 0);
dataout : out std_logic_vector((dbits -1) downto 0);
wclk : in std_ulogic;
write : in std_ulogic;
waddress : in std_logic_vector((abits -1) downto 0);
datain : in std_logic_vector((dbits -1) downto 0);
error : out std_logic_vector(((dbits + 7) / 8)-1 downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(3*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(3*custombits-1 downto 0));
end component;
component syncram128bw
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (127 downto 0);
dataout : out std_logic_vector (127 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(16*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(16*custombits-1 downto 0));
end component;
component syncram156bw
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(20*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(20*custombits-1 downto 0));
end component;
component syncram256bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (255 downto 0);
dataout : out std_logic_vector (255 downto 0);
enable : in std_logic_vector (31 downto 0);
write : in std_logic_vector (31 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(32*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(32*custombits-1 downto 0));
end component;
component syncrambw
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end component;
component syncram_2pbw
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
sepclk : integer := 0; wrfst : integer := 0; testen : integer := 0;
words : integer := 0; custombits : integer := 1);
port (
rclk : in std_ulogic;
renable : in std_logic_vector((dbits/8-1) downto 0);
raddress : in std_logic_vector((abits-1) downto 0);
dataout : out std_logic_vector((dbits-1) downto 0);
wclk : in std_ulogic;
write : in std_logic_vector((dbits/8-1) downto 0);
waddress : in std_logic_vector((abits-1) downto 0);
datain : in std_logic_vector((dbits-1) downto 0);
testin : in std_logic_vector(TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector((dbits/8)*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector((dbits/8)*custombits-1 downto 0));
end component;
component syncrambwft is
generic (tech : integer := 0; abits : integer := 6; dbits : integer := 8;
ft : integer range 0 to 3 := 0; testen : integer := 0; custombits : integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits-1 downto 0);
datain : in std_logic_vector (dbits-1 downto 0);
dataout : out std_logic_vector (dbits-1 downto 0);
enable : in std_logic_vector (dbits/8-1 downto 0);
write : in std_logic_vector (dbits/8-1 downto 0);
error : out std_logic_vector (dbits/8-1 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
errinj : in std_logic_vector((dbits/8)*2-1 downto 0) := (others => '0');
customclk : in std_ulogic := '0';
customin : in std_logic_vector(3*(dbits/8)*custombits-1 downto 0) := (others => '0');
customout : out std_logic_vector(3*(dbits/8)*custombits-1 downto 0));
end component;
component from is
generic (
timingcheckson: boolean := True;
instancepath: string := "*";
xon: boolean := False;
msgon: boolean := True;
data_x: integer := 1;
memoryfile: string := "";
progfile: string := "");
port (
clk: in std_ulogic;
addr: in std_logic_vector(6 downto 0);
data: out std_logic_vector(7 downto 0));
end component;
component syncfifo_2p is
generic (
tech : integer := 0;
abits : integer := 6;
dbits : integer := 8
);
port (
rclk : in std_logic;
renable : in std_logic;
rfull : out std_logic;
rempty : out std_logic;
rusedw : out std_logic_vector(abits-1 downto 0);
datain : in std_logic_vector(dbits-1 downto 0);
wclk : in std_logic;
write : in std_logic;
wfull : out std_logic;
wempty : out std_logic;
wusedw : out std_logic_vector(abits-1 downto 0);
dataout : out std_logic_vector(dbits-1 downto 0)
);
end component;
---------------------------------------------------------------------------
-- PADS
---------------------------------------------------------------------------
component inpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; filter : integer := 0;
strength : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic);
end component;
component inpadv
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; width : integer := 1;
filter : integer := 0; strength : integer := 0);
port (
pad : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; filter : integer := 0);
port (pad : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component iopadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0; filter : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000"
);
end component;
component iodpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i : in std_ulogic; o : out std_ulogic);
end component;
component iodpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi : in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component outpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component odpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component odpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : out std_ulogic; i, en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpadv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpadvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
pad : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
cfgi: in std_logic_vector(19 downto 0) := "00000000000000000000");
end component;
component toutpad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component toutpad_dsv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic);
end component;
component toutpad_dsvv is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0));
end component;
component skew_outpad
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end component;
component clkpad
generic (tech : integer := 0; level : integer := 0;
voltage : integer := x33v; arch : integer := 0;
hf : integer := 0; filter : integer := 0);
port (pad : in std_ulogic; o : out std_ulogic; rstn : std_ulogic := '1'; lock : out std_ulogic);
end component;
component inpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component clkpad_ds
generic (tech : integer := 0; level : integer := lvds; voltage : integer := x33v; term : integer := 0);
port (padp, padn : in std_ulogic; o : out std_ulogic);
end component;
component inpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; term : integer := 0);
port (
padp : in std_logic_vector(width-1 downto 0);
padn : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_ds
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0; term : integer := 0);
port (padp, padn : inout std_ulogic; i, en : in std_ulogic; o : out std_ulogic);
end component;
component iopad_dsv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_ulogic;
o : out std_logic_vector(width-1 downto 0));
end component;
component iopad_dsvv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (
padp, padn : inout std_logic_vector(width-1 downto 0);
i : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o : out std_logic_vector(width-1 downto 0));
end component;
component outpad_ds
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; oepol : integer := 0; slew : integer := 0);
port (padp, padn : out std_ulogic; i, en : in std_ulogic);
end component;
component outpad_dsv
generic (tech : integer := 0; level : integer := lvds;
voltage : integer := x33v; width : integer := 1; slew : integer := 0);
port (
padp : out std_logic_vector(width-1 downto 0);
padn : out std_logic_vector(width-1 downto 0);
i, en: in std_logic_vector(width-1 downto 0));
end component;
component lvds_combo is
generic (tech : integer := 0; voltage : integer := 0; width : integer := 1;
oepol : integer := 0; term : integer := 0);
port (odpadp, odpadn, ospadp, ospadn : out std_logic_vector(0 to width-1);
odval, osval, en : in std_logic_vector(0 to width-1);
idpadp, idpadn, ispadp, ispadn : in std_logic_vector(0 to width-1);
idval, isval : out std_logic_vector(0 to width-1);
powerdown : in std_logic_vector(0 to width-1) := (others => '0');
powerdownrx : in std_logic_vector(0 to width-1) := (others => '0');
lvdsref : in std_logic := '1'; lvdsrefo : out std_logic
);
end component;
-------------------------------------------------------------------------------
-- DDR PADS (bundles PAD and DDR register(s))
-------------------------------------------------------------------------------
component inpad_ddr
generic (tech : integer := 0; level : integer := 0; voltage : integer := x33v;
filter : integer := 0; strength : integer := 0 );
port (pad : in std_ulogic; o1, o2 : out std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component inpad_ddrv
generic (tech : integer := 0; level : integer := 0; voltage : integer := 0;
filter : integer := 0; strength : integer := 0; width : integer := 1);
port (pad : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r: in std_ulogic; s : in std_ulogic);
end component;
component outpad_ddr
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12);
port (pad : out std_ulogic; i1, i2 : in std_ulogic; c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component outpad_ddrv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := 0; strength : integer := 12;
width : integer := 1);
port (pad : out std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddr
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12;
oepol : integer := 0);
port (pad : inout std_ulogic; i1, i2 : in std_ulogic; en : in std_ulogic;
o1, o2 : out std_ulogic; c1, c2 : in std_ulogic; ce : in std_ulogic;
r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddrv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0); en : in std_ulogic;
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
component iopad_ddrvv
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; width : integer := 1;
oepol : integer := 0);
port (pad : inout std_logic_vector(width-1 downto 0);
i1, i2 : in std_logic_vector(width-1 downto 0);
en : in std_logic_vector(width-1 downto 0);
o1, o2 : out std_logic_vector(width-1 downto 0); c1, c2 : in std_ulogic;
ce : in std_ulogic; r : in std_ulogic; s : in std_ulogic);
end component;
---------------------------------------------------------------------------
-- BUFFERS
---------------------------------------------------------------------------
component techbuf is
generic(
buftype : integer range 0 to 6 := 0;
tech : integer range 0 to NTECH := inferred);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
---------------------------------------------------------------------------
-- CLOCK GENERATION
---------------------------------------------------------------------------
type clkgen_in_type is record
pllref : std_logic; -- optional reference for PLL
pllrst : std_logic; -- optional reset for PLL
pllctrl : std_logic_vector(1 downto 0); -- optional control for PLL
clksel : std_logic_vector(1 downto 0); -- optional clock select
end record;
type clkgen_out_type is record
clklock : std_logic;
pcilock : std_logic;
end record;
component clkgen
generic (
tech : integer := DEFFABTECH;
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
noclkfb : integer := 1;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
clksel : integer := 0; -- enable clock select
clk_odiv : integer := 1; -- Proasic3/Fusion output divider clkA
clkb_odiv: integer := 0; -- Proasic3/Fusion output divider clkB
clkc_odiv: integer := 0); -- Proasic3/Fusion output divider clkC
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- 2x clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type;
clk4x : out std_logic; -- 4x clock
clk1xu : out std_logic; -- unscaled 1X clock
clk2xu : out std_logic; -- unscaled 2X clock
clkb : out std_logic; -- Proasic3/Fusion clkB
clkc : out std_logic; -- Proasic3/Fusion clkC
clk8x : out std_logic); -- 8x clock
end component;
component clkand
generic( tech : integer := 0;
ren : integer range 0 to 1 := 0); -- registered enable
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
component clkmux
generic( tech : integer := 0;
rsel : integer range 0 to 1 := 0); -- registered sel
port(
i0, i1 : in std_ulogic;
sel : in std_ulogic;
o : out std_ulogic;
rst : in std_ulogic := '1'
);
end component;
component clkinv
generic( tech : integer := 0);
port(
i : in std_ulogic;
o : out std_ulogic
);
end component;
component clkrand is
generic( tech : integer := 0);
port(
i : in std_ulogic;
en : in std_ulogic;
o : out std_ulogic;
tsten : in std_ulogic := '0'
);
end component;
---------------------------------------------------------------------------
-- TAP controller and boundary scan
---------------------------------------------------------------------------
component tap
generic (
tech : integer := 0;
irlen : integer range 2 to 8 := 4;
idcode : integer range 0 to 255 := 9;
manf : integer range 0 to 2047 := 804;
part : integer range 0 to 65535 := 0;
ver : integer range 0 to 15 := 0;
trsten : integer range 0 to 1 := 1;
scantest : integer := 0;
oepol : integer := 1;
tcknen : integer := 0);
port (
trst : in std_ulogic;
tck : in std_ulogic;
tms : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
tapo_tck : out std_ulogic;
tapo_tdi : out std_ulogic;
tapo_inst : out std_logic_vector(7 downto 0);
tapo_rst : out std_ulogic;
tapo_capt : out std_ulogic;
tapo_shft : out std_ulogic;
tapo_upd : out std_ulogic;
tapo_xsel1 : out std_ulogic;
tapo_xsel2 : out std_ulogic;
tapi_en1 : in std_ulogic;
tapi_tdo1 : in std_ulogic;
tapi_tdo2 : in std_ulogic;
tapo_ninst : out std_logic_vector(7 downto 0);
tapo_iupd : out std_ulogic;
tapo_tckn : out std_ulogic;
testen : in std_ulogic := '0';
testrst : in std_ulogic := '1';
testoen : in std_ulogic := '0';
tdoen : out std_ulogic;
tckn : in std_ulogic := '0'
);
end component;
component scanregi
generic (
tech : integer := 0;
intesten: integer := 1
);
port (
pad : in std_ulogic;
core : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to core
bshighz : in std_ulogic
);
end component;
component scanrego
generic (
tech : integer := 0
);
port (
pad : out std_ulogic;
core : in std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupd : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic -- drive data reg to pad
);
end component;
component scanregto -- 2 scan registers: tdo<---output<--outputen<--tdi
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
samp : in std_ulogic; -- normally same as core unless outpad has feedback
coreo : in std_ulogic;
coreoen : in std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signal to scan reg on next tck edge
bsupdo : in std_ulogic; -- update data reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive data reg to pad
bshighz : in std_ulogic -- tri-state output
);
end component;
component scanregio -- 3 scan registers: tdo<--input<--output<--outputen<--tdi
generic (
tech : integer := 0;
hzsup: integer range 0 to 1 := 1;
oepol: integer range 0 to 1 := 1;
intesten: integer range 0 to 1 := 1
);
port (
pado : out std_ulogic;
padoen : out std_ulogic;
padi : in std_ulogic;
coreo : in std_ulogic;
coreoen : in std_ulogic;
corei : out std_ulogic;
tck : in std_ulogic;
tckn : in std_ulogic;
tdi : in std_ulogic;
tdo : out std_ulogic;
bsshft : in std_ulogic;
bscapt : in std_ulogic; -- capture signals to scan regs on next tck edge
bsupdi : in std_ulogic; -- update indata reg from scan reg on next tck edge
bsupdo : in std_ulogic; -- update outdata reg from scan reg on next tck edge
bsdrive : in std_ulogic; -- drive outdata regs to pad,
-- drive datareg(coreoen=0) or coreo(coreoen=1) to corei
bshighz : in std_ulogic -- tri-state output
);
end component;
---------------------------------------------------------------------------
-- DDR registers and PHY
---------------------------------------------------------------------------
component ddr_ireg is
generic ( tech : integer; arch : integer := 0);
port ( Q1 : out std_ulogic;
Q2 : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddr_oreg is generic (tech : integer; arch : integer := 0);
port
( Q : out std_ulogic;
C1 : in std_ulogic;
C2 : in std_ulogic;
CE : in std_ulogic;
D1 : in std_ulogic;
D2 : in std_ulogic;
R : in std_ulogic;
S : in std_ulogic);
end component;
component ddrphy
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2 ; clk_div : integer := 2;
rskew : integer :=0; mobile : integer := 0;
abits: integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkread : out std_ulogic; -- read clock
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(2 downto 0);
ddr_clkb : out std_logic_vector(2 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(1 downto 0);
ddr_csb : out std_logic_vector(1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (13 downto 0); -- data mask
ba : in std_logic_vector ( 1 downto 0); -- data mask
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(1 downto 0);
cke : in std_logic_vector(1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddrphy_wo_pads
generic (tech : integer := virtex2; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
rskew : integer := 0; mobile: integer := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
scantest : integer := 0; phyiconf : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkread : out std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (1 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
ck : in std_logic_vector(2 downto 0);
moben : in std_logic;
dqvalid : out std_ulogic;
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2phy
generic (
tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8 : integer := 0;
ddelayb9 : integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
ctrl2en: integer := 0; resync: integer := 0; custombits: integer := 8; extraio: integer := 0;
scantest : integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input reference clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock return
clkresync : in std_ulogic; -- resync clock (if resync/=0)
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (extraio+dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
-- Copy of control signals for 2nd DIMM
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2phy_wo_pads
generic (tech : integer := virtex5; MHz : integer := 100;
rstdelay : integer := 200; dbits : integer := 16;
clk_mul : integer := 2; clk_div : integer := 2;
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
ddelayb8: integer := 0;
ddelayb9: integer := 0; ddelayb10: integer := 0; ddelayb11: integer := 0;
numidelctrl : integer := 4; norefclk : integer := 0; rskew : integer := 0;
eightbanks : integer range 0 to 1 := 0; dqsse : integer range 0 to 1 := 0;
abits : integer := 14; nclk: integer := 3; ncs: integer := 2;
resync : integer := 0; custombits: integer := 8; scantest: integer := 0);
port (
rst : in std_ulogic;
clk : in std_logic; -- input clock
clkref : in std_logic; -- input 200MHz clock
clkout : out std_ulogic; -- system clock
clkoutret : in std_ulogic; -- system clock returned
clkresync : in std_ulogic;
lock : out std_ulogic; -- DCM locked
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector ( 2 downto 0);
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
oen : in std_ulogic;
noen : in std_ulogic;
dqs : in std_ulogic;
dqsoen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
cal_en : in std_logic_vector(dbits/8-1 downto 0);
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
cal_pll : in std_logic_vector(1 downto 0);
cal_rst : in std_logic;
odt : in std_logic_vector(ncs-1 downto 0);
oct : in std_logic;
read_pend : in std_logic_vector(7 downto 0);
regwdata : in std_logic_vector(63 downto 0);
regwrite : in std_logic_vector(1 downto 0);
regrdata : out std_logic_vector(63 downto 0);
dqin_valid : out std_ulogic;
customclk : in std_ulogic;
customdin : in std_logic_vector(custombits-1 downto 0);
customdout : out std_logic_vector(custombits-1 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component lpddr2phy_wo_pads
generic (
tech : integer := virtex5;
dbits : integer := 16;
nclk: integer := 3;
ncs: integer := 2;
clkratio: integer := 1;
scantest: integer := 0);
port (
rst : in std_ulogic;
clkin : in std_ulogic;
clkin2 : in std_ulogic;
clkout : out std_ulogic;
clkoutret : in std_ulogic; -- ckkout returned
clkout2 : out std_ulogic;
lock : out std_ulogic;
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_ca : out std_logic_vector(9 downto 0);
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs_in : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_out : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqs_oen : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dq_in : in std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_out : out std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_dq_oen : out std_logic_vector (dbits-1 downto 0); -- ddr data
ca : in std_logic_vector (10*2*clkratio-1 downto 0);
cke : in std_logic_vector (ncs*clkratio-1 downto 0);
csn : in std_logic_vector (ncs*clkratio-1 downto 0);
dqin : out std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr output data
dqout : in std_logic_vector (dbits*2*clkratio-1 downto 0); -- ddr input data
dm : in std_logic_vector (dbits/4*clkratio-1 downto 0); -- data mask
ckstop : in std_ulogic;
boot : in std_ulogic;
wrpend : in std_logic_vector(7 downto 0);
rdpend : in std_logic_vector(7 downto 0);
wrreq : out std_logic_vector(clkratio-1 downto 0);
rdvalid : out std_logic_vector(clkratio-1 downto 0);
refcal : in std_ulogic;
refcalwu : in std_ulogic;
refcaldone : out std_ulogic;
phycmd : in std_logic_vector(7 downto 0);
phycmden : in std_ulogic;
phycmdin : in std_logic_vector(31 downto 0);
phycmdout : out std_logic_vector(31 downto 0);
testen : in std_ulogic;
testrst : in std_ulogic;
scanen : in std_ulogic;
testoen : in std_ulogic);
end component;
component ddr2pads is
generic (tech: integer := virtex5;
dbits: integer := 16;
eightbanks: integer := 0;
dqsse: integer range 0 to 1 := 0;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
ddr_odt : out std_logic_vector(ncs-1 downto 0);
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1+eightbanks downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_odt : in std_logic_vector(ncs-1 downto 0)
);
end component;
component ddrpads is
generic (tech: integer := virtex5;
dbits: integer := 16;
abits: integer := 14;
nclk: integer := 3;
ncs: integer := 2;
ctrl2en: integer := 0);
port (
ddr_clk : out std_logic_vector(nclk-1 downto 0);
ddr_clkb : out std_logic_vector(nclk-1 downto 0);
ddr_clk_fb_out : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic_vector(ncs-1 downto 0);
ddr_csb : out std_logic_vector(ncs-1 downto 0);
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
-- Copy of control signals for 2nd DIMM (if ctrl2en /= 0)
ddr_web2 : out std_ulogic; -- ddr write enable
ddr_rasb2 : out std_ulogic; -- ddr ras
ddr_casb2 : out std_ulogic; -- ddr cas
ddr_ad2 : out std_logic_vector (abits-1 downto 0); -- ddr address
ddr_ba2 : out std_logic_vector (1 downto 0); -- ddr bank address
lddr_clk : in std_logic_vector(nclk-1 downto 0);
lddr_clkb : in std_logic_vector(nclk-1 downto 0);
lddr_clk_fb_out : in std_logic;
lddr_clk_fb : out std_logic;
lddr_cke : in std_logic_vector(ncs-1 downto 0);
lddr_csb : in std_logic_vector(ncs-1 downto 0);
lddr_web : in std_ulogic; -- ddr write enable
lddr_rasb : in std_ulogic; -- ddr ras
lddr_casb : in std_ulogic; -- ddr cas
lddr_dm : in std_logic_vector (dbits/8-1 downto 0); -- ddr dm
lddr_dqs_in : out std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_out : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_dqs_oen : in std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
lddr_ad : in std_logic_vector (abits-1 downto 0); -- ddr address
lddr_ba : in std_logic_vector (1 downto 0); -- ddr bank address
lddr_dq_in : out std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_out : in std_logic_vector (dbits-1 downto 0); -- ddr data
lddr_dq_oen : in std_logic_vector (dbits-1 downto 0) -- ddr data
);
end component;
component ddrphy_datapath is
generic (
regtech: integer := 0;
dbits: integer;
abits: integer;
bankbits: integer range 2 to 3 := 2;
ncs: integer;
nclk: integer;
resync: integer range 0 to 2 := 0
);
port (
clk0: in std_ulogic;
clk90: in std_ulogic;
clk180: in std_ulogic;
clk270: in std_ulogic;
clkresync: in std_ulogic;
ddr_clk: out std_logic_vector(nclk-1 downto 0);
ddr_clkb: out std_logic_vector(nclk-1 downto 0);
ddr_dq_in: in std_logic_vector(dbits-1 downto 0);
ddr_dq_out: out std_logic_vector(dbits-1 downto 0);
ddr_dq_oen: out std_logic_vector(dbits-1 downto 0);
ddr_dqs_in90: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_in90n: in std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_out: out std_logic_vector(dbits/8-1 downto 0);
ddr_dqs_oen: out std_logic_vector(dbits/8-1 downto 0);
ddr_cke: out std_logic_vector(ncs-1 downto 0);
ddr_csb: out std_logic_vector(ncs-1 downto 0);
ddr_web: out std_ulogic;
ddr_rasb: out std_ulogic;
ddr_casb: out std_ulogic;
ddr_ad: out std_logic_vector(abits-1 downto 0);
ddr_ba: out std_logic_vector(bankbits-1 downto 0);
ddr_dm: out std_logic_vector(dbits/8-1 downto 0);
ddr_odt: out std_logic_vector(ncs-1 downto 0);
dqin: out std_logic_vector(dbits*2-1 downto 0);
dqout: in std_logic_vector(dbits*2-1 downto 0);
addr : in std_logic_vector (abits-1 downto 0);
ba : in std_logic_vector (bankbits-1 downto 0);
dm : in std_logic_vector (dbits/4-1 downto 0);
oen : in std_ulogic;
rasn : in std_ulogic;
casn : in std_ulogic;
wen : in std_ulogic;
csn : in std_logic_vector(ncs-1 downto 0);
cke : in std_logic_vector(ncs-1 downto 0);
odt : in std_logic_vector(ncs-1 downto 0);
dqs_en : in std_ulogic;
dqs_oen : in std_ulogic;
ddrclk_en : in std_logic_vector(nclk-1 downto 0)
);
end component;
---------------------------------------------------------------------------
-- 61x61 Multiplier
---------------------------------------------------------------------------
component mul_61x61
generic (multech : integer := 0;
fabtech : integer := 0);
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
EN : in std_logic;
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end component;
---------------------------------------------------------------------------
-- Ring oscillator
---------------------------------------------------------------------------
component ringosc
generic (tech : integer := 0);
port (
roen : in Std_ULogic;
roout : out Std_ULogic);
end component;
---------------------------------------------------------------------------
-- System monitor
---------------------------------------------------------------------------
component system_monitor
generic (
-- GRLIB generics
tech : integer := DEFFABTECH;
-- Virtex 5 SYSMON generics
INIT_40 : bit_vector := X"0000";
INIT_41 : bit_vector := X"0000";
INIT_42 : bit_vector := X"0800";
INIT_43 : bit_vector := X"0000";
INIT_44 : bit_vector := X"0000";
INIT_45 : bit_vector := X"0000";
INIT_46 : bit_vector := X"0000";
INIT_47 : bit_vector := X"0000";
INIT_48 : bit_vector := X"0000";
INIT_49 : bit_vector := X"0000";
INIT_4A : bit_vector := X"0000";
INIT_4B : bit_vector := X"0000";
INIT_4C : bit_vector := X"0000";
INIT_4D : bit_vector := X"0000";
INIT_4E : bit_vector := X"0000";
INIT_4F : bit_vector := X"0000";
INIT_50 : bit_vector := X"0000";
INIT_51 : bit_vector := X"0000";
INIT_52 : bit_vector := X"0000";
INIT_53 : bit_vector := X"0000";
INIT_54 : bit_vector := X"0000";
INIT_55 : bit_vector := X"0000";
INIT_56 : bit_vector := X"0000";
INIT_57 : bit_vector := X"0000";
SIM_MONITOR_FILE : string := "design.txt");
port (
alm : out std_logic_vector(2 downto 0);
busy : out std_ulogic;
channel : out std_logic_vector(4 downto 0);
do : out std_logic_vector(15 downto 0);
drdy : out std_ulogic;
eoc : out std_ulogic;
eos : out std_ulogic;
jtagbusy : out std_ulogic;
jtaglocked : out std_ulogic;
jtagmodified : out std_ulogic;
ot : out std_ulogic;
convst : in std_ulogic;
convstclk : in std_ulogic;
daddr : in std_logic_vector(6 downto 0);
dclk : in std_ulogic;
den : in std_ulogic;
di : in std_logic_vector(15 downto 0);
dwe : in std_ulogic;
reset : in std_ulogic;
vauxn : in std_logic_vector(15 downto 0);
vauxp : in std_logic_vector(15 downto 0);
vn : in std_ulogic;
vp : in std_ulogic);
end component;
component nandtree
generic(
tech : integer := inferred;
width : integer := 2;
imp : integer := 0 );
port( i : in std_logic_vector(width-1 downto 0);
o : out std_ulogic;
en : in std_ulogic
);
end component;
component grmux2 is generic( tech : integer := inferred; imp : integer := 0);
port( ip0, ip1, sel : in std_logic; op : out std_ulogic); end component;
component grmux2v is generic( tech : integer := inferred; bits : integer := 2; imp : integer := 0);
port( ip0, ip1 : in std_logic_vector(bits-1 downto 0);
sel : in std_logic; op : out std_logic_vector(bits-1 downto 0));
end component;
component grdff is generic( tech : integer := inferred; imp : integer := 0);
port( clk, d : in std_ulogic; q : out std_ulogic); end component;
component gror2 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component grand12 is generic( tech : integer := inferred; imp : integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component grnand2 is generic (tech: integer := inferred; imp: integer := 0);
port( i0, i1 : in std_ulogic; q : out std_ulogic); end component;
component techmult
generic (
tech : integer := 0;
arch : integer := 0;
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end component;
component syncreg
generic (
tech : integer := 0;
stages : integer range 1 to 5 := 2
);
port (
clk : in std_ulogic;
d : in std_ulogic;
q : out std_ulogic
);
end component;
-------------------------------------------------------------------------------
-- SDRAM PHY
-------------------------------------------------------------------------------
component sdram_phy
generic (
tech : integer := spartan3;
oepol : integer := 0;
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end component;
-------------------------------------------------------------------------------
-- GIGABIT ETHERNET SERDES
-------------------------------------------------------------------------------
component serdes is
generic (
tech : integer
);
port (
clk_125 : in std_logic;
rst_125 : in std_logic;
rx_in : in std_logic; -- SER IN
rx_out : out std_logic_vector(9 downto 0); -- PAR OUT
rx_clk : out std_logic;
rx_rstn : out std_logic;
rx_pll_clk : out std_logic;
rx_pll_rstn : out std_logic;
tx_pll_clk : out std_logic;
tx_pll_rstn : out std_logic;
tx_in : in std_logic_vector(9 downto 0) ; -- PAR IN
tx_out : out std_logic; -- SER OUT
bitslip : in std_logic
);
end component;
end;
|
library verilog;
use verilog.vl_types.all;
entity usb_system_cpu_nios2_oci_fifo_wrptr_inc is
port(
ge2_free : in vl_logic;
ge3_free : in vl_logic;
input_tm_cnt : in vl_logic_vector(1 downto 0);
fifo_wrptr_inc : out vl_logic_vector(3 downto 0)
);
end usb_system_cpu_nios2_oci_fifo_wrptr_inc;
|
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reg_mux.vhd
-- Description: This entity is AXI VDMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdmantrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_regf.vhd
-- | |- axi_vdma_litef.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sgf.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdstsf.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sgf.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdstsf.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_reg_mux is
generic (
C_TOTAL_NUM_REGISTER : integer := 8 ;
-- Total number of defined registers for AXI VDMA. Used
-- to determine wrce and rdce vector widths.
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
-- Channel type for Read Mux
-- 0 = Channel is S2MM
-- 1 = Channel is MM2S
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1 ;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads
-- 1 = Enable Video Parameter Reads
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
-- AXI Lite interface address width
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Lite interface data width
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Scatter Gather engine Address Width
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
-- Master AXI Memory Map Address Width for MM2S Write Port
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
axi2ip_rdaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) ; --
axi2ip_rden : in std_logic ; --
ip2axi_rddata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ip2axi_rddata_valid : out std_logic ; --
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmacr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmasr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dma_irq_mask : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
linebuf_threshold : in std_logic_vector --
(THRESH_MSB_BIT downto 0) ; --
-- Register Direct Support --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_start_address1 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address2 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address3 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address4 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address5 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address6 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address7 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address8 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address9 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address10 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address11 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address12 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address13 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address14 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address15 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address16 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address17 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address18 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address19 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address20 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address21 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address22 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address23 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address24 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address25 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address26 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address27 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address28 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address29 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address30 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address31 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address32 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_reg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE DONT_TOUCH : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-VSIZE_DWIDTH;
constant VSIZE_PAD : std_logic_vector(VSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant HSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-HSIZE_DWIDTH;
constant HSIZE_PAD : std_logic_vector(HSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant FRMSTORE_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto FRMSTORE_MSB_BIT+1) := (others => '0');
constant THRESH_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto THRESH_MSB_BIT+1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal read_addr_ri : std_logic_vector(8 downto 0) := (others => '0');
signal read_addr : std_logic_vector(7 downto 0) := (others => '0');
signal read_addr_sg_1 : std_logic_vector(7 downto 0) := (others => '0');
signal ip2axi_rddata_int : std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ATTRIBUTE DONT_TOUCH OF ip2axi_rddata_int : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ip2axi_rddata <= ip2axi_rddata_int;
--*****************************************************************************
-- AXI LITE READ MUX
--*****************************************************************************
-- Register module is for MM2S Channel therefore look at
-- MM2S Register offsets
GEN_READ_MUX_FOR_MM2S : if C_CHANNEL_IS_MM2S = 1 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
curdesc_msb ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when MM2S_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_MM2S;
-- Register module is for S2MM Channel therefore look at
-- S2MM Register offsets
GEN_READ_MUX_FOR_S2MM : if C_CHANNEL_IS_MM2S = 0 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
dma_irq_mask ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when S2MM_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_SG =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 17 start addresses
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_S2MM;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reg_mux.vhd
-- Description: This entity is AXI VDMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdmantrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_regf.vhd
-- | |- axi_vdma_litef.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sgf.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdstsf.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sgf.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdstsf.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_reg_mux is
generic (
C_TOTAL_NUM_REGISTER : integer := 8 ;
-- Total number of defined registers for AXI VDMA. Used
-- to determine wrce and rdce vector widths.
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
-- Channel type for Read Mux
-- 0 = Channel is S2MM
-- 1 = Channel is MM2S
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1 ;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads
-- 1 = Enable Video Parameter Reads
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
-- AXI Lite interface address width
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Lite interface data width
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Scatter Gather engine Address Width
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
-- Master AXI Memory Map Address Width for MM2S Write Port
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
axi2ip_rdaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) ; --
axi2ip_rden : in std_logic ; --
ip2axi_rddata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ip2axi_rddata_valid : out std_logic ; --
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmacr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmasr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dma_irq_mask : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
linebuf_threshold : in std_logic_vector --
(THRESH_MSB_BIT downto 0) ; --
-- Register Direct Support --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_start_address1 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address2 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address3 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address4 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address5 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address6 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address7 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address8 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address9 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address10 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address11 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address12 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address13 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address14 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address15 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address16 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address17 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address18 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address19 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address20 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address21 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address22 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address23 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address24 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address25 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address26 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address27 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address28 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address29 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address30 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address31 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address32 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_reg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE DONT_TOUCH : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-VSIZE_DWIDTH;
constant VSIZE_PAD : std_logic_vector(VSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant HSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-HSIZE_DWIDTH;
constant HSIZE_PAD : std_logic_vector(HSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant FRMSTORE_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto FRMSTORE_MSB_BIT+1) := (others => '0');
constant THRESH_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto THRESH_MSB_BIT+1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal read_addr_ri : std_logic_vector(8 downto 0) := (others => '0');
signal read_addr : std_logic_vector(7 downto 0) := (others => '0');
signal read_addr_sg_1 : std_logic_vector(7 downto 0) := (others => '0');
signal ip2axi_rddata_int : std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ATTRIBUTE DONT_TOUCH OF ip2axi_rddata_int : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ip2axi_rddata <= ip2axi_rddata_int;
--*****************************************************************************
-- AXI LITE READ MUX
--*****************************************************************************
-- Register module is for MM2S Channel therefore look at
-- MM2S Register offsets
GEN_READ_MUX_FOR_MM2S : if C_CHANNEL_IS_MM2S = 1 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
curdesc_msb ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when MM2S_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_MM2S;
-- Register module is for S2MM Channel therefore look at
-- S2MM Register offsets
GEN_READ_MUX_FOR_S2MM : if C_CHANNEL_IS_MM2S = 0 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
dma_irq_mask ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when S2MM_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_SG =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 17 start addresses
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_S2MM;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reg_mux.vhd
-- Description: This entity is AXI VDMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdmantrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_regf.vhd
-- | |- axi_vdma_litef.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sgf.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdstsf.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sgf.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdstsf.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_reg_mux is
generic (
C_TOTAL_NUM_REGISTER : integer := 8 ;
-- Total number of defined registers for AXI VDMA. Used
-- to determine wrce and rdce vector widths.
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
-- Channel type for Read Mux
-- 0 = Channel is S2MM
-- 1 = Channel is MM2S
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1 ;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads
-- 1 = Enable Video Parameter Reads
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
-- AXI Lite interface address width
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Lite interface data width
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Scatter Gather engine Address Width
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
-- Master AXI Memory Map Address Width for MM2S Write Port
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
axi2ip_rdaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) ; --
axi2ip_rden : in std_logic ; --
ip2axi_rddata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ip2axi_rddata_valid : out std_logic ; --
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmacr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmasr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dma_irq_mask : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
linebuf_threshold : in std_logic_vector --
(THRESH_MSB_BIT downto 0) ; --
-- Register Direct Support --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_start_address1 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address2 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address3 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address4 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address5 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address6 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address7 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address8 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address9 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address10 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address11 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address12 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address13 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address14 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address15 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address16 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address17 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address18 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address19 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address20 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address21 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address22 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address23 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address24 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address25 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address26 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address27 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address28 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address29 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address30 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address31 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address32 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_reg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE DONT_TOUCH : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-VSIZE_DWIDTH;
constant VSIZE_PAD : std_logic_vector(VSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant HSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-HSIZE_DWIDTH;
constant HSIZE_PAD : std_logic_vector(HSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant FRMSTORE_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto FRMSTORE_MSB_BIT+1) := (others => '0');
constant THRESH_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto THRESH_MSB_BIT+1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal read_addr_ri : std_logic_vector(8 downto 0) := (others => '0');
signal read_addr : std_logic_vector(7 downto 0) := (others => '0');
signal read_addr_sg_1 : std_logic_vector(7 downto 0) := (others => '0');
signal ip2axi_rddata_int : std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ATTRIBUTE DONT_TOUCH OF ip2axi_rddata_int : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ip2axi_rddata <= ip2axi_rddata_int;
--*****************************************************************************
-- AXI LITE READ MUX
--*****************************************************************************
-- Register module is for MM2S Channel therefore look at
-- MM2S Register offsets
GEN_READ_MUX_FOR_MM2S : if C_CHANNEL_IS_MM2S = 1 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
curdesc_msb ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when MM2S_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_MM2S;
-- Register module is for S2MM Channel therefore look at
-- S2MM Register offsets
GEN_READ_MUX_FOR_S2MM : if C_CHANNEL_IS_MM2S = 0 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
dma_irq_mask ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when S2MM_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_SG =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 17 start addresses
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_S2MM;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_vdma_reg_mux
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011, 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_vdma_reg_mux.vhd
-- Description: This entity is AXI VDMA Register Module Top Level
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_vdma.vhd
-- |- axi_vdma_pkg.vhd
-- |- axi_vdmantrpt.vhd
-- |- axi_vdma_rst_module.vhd
-- | |- axi_vdma_reset.vhd (mm2s)
-- | | |- axi_vdma_cdc.vhd
-- | |- axi_vdma_reset.vhd (s2mm)
-- | | |- axi_vdma_cdc.vhd
-- |
-- |- axi_vdma_regf.vhd
-- | |- axi_vdma_litef.vhd
-- | |- axi_vdma_cdc.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_vdma_sg_cdc.vhd (mm2s)
-- |- axi_vdma_vid_cdc.vhd (mm2s)
-- |- axi_vdma_fsync_gen.vhd (mm2s)
-- |- axi_vdma_sof_gen.vhd (mm2s)
-- |- axi_vdma_reg_module.vhd (mm2s)
-- | |- axi_vdma_register.vhd (mm2s)
-- | |- axi_vdma_regdirect.vhd (mm2s)
-- |- axi_vdma_mngr.vhd (mm2s)
-- | |- axi_vdma_sgf.vhd (mm2s)
-- | |- axi_vdma_sm.vhd (mm2s)
-- | |- axi_vdma_cmdstsf.vhd (mm2s)
-- | |- axi_vdma_vidreg_module.vhd (mm2s)
-- | | |- axi_vdma_sgregister.vhd (mm2s)
-- | | |- axi_vdma_vregister.vhd (mm2s)
-- | | |- axi_vdma_vaddrreg_mux.vhd (mm2s)
-- | | |- axi_vdma_blkmem.vhd (mm2s)
-- | |- axi_vdma_genlock_mngr.vhd (mm2s)
-- | |- axi_vdma_genlock_mux.vhd (mm2s)
-- | |- axi_vdma_greycoder.vhd (mm2s)
-- |- axi_vdma_mm2s_linebuf.vhd (mm2s)
-- | |- axi_vdma_sfifo_autord.vhd (mm2s)
-- | |- axi_vdma_afifo_autord.vhd (mm2s)
-- | |- axi_vdma_skid_buf.vhd (mm2s)
-- | |- axi_vdma_cdc.vhd (mm2s)
-- |
-- |- axi_vdma_sg_cdc.vhd (s2mm)
-- |- axi_vdma_vid_cdc.vhd (s2mm)
-- |- axi_vdma_fsync_gen.vhd (s2mm)
-- |- axi_vdma_sof_gen.vhd (s2mm)
-- |- axi_vdma_reg_module.vhd (s2mm)
-- | |- axi_vdma_register.vhd (s2mm)
-- | |- axi_vdma_regdirect.vhd (s2mm)
-- |- axi_vdma_mngr.vhd (s2mm)
-- | |- axi_vdma_sgf.vhd (s2mm)
-- | |- axi_vdma_sm.vhd (s2mm)
-- | |- axi_vdma_cmdstsf.vhd (s2mm)
-- | |- axi_vdma_vidreg_module.vhd (s2mm)
-- | | |- axi_vdma_sgregister.vhd (s2mm)
-- | | |- axi_vdma_vregister.vhd (s2mm)
-- | | |- axi_vdma_vaddrreg_mux.vhd (s2mm)
-- | | |- axi_vdma_blkmem.vhd (s2mm)
-- | |- axi_vdma_genlock_mngr.vhd (s2mm)
-- | |- axi_vdma_genlock_mux.vhd (s2mm)
-- | |- axi_vdma_greycoder.vhd (s2mm)
-- |- axi_vdma_s2mm_linebuf.vhd (s2mm)
-- | |- axi_vdma_sfifo_autord.vhd (s2mm)
-- | |- axi_vdma_afifo_autord.vhd (s2mm)
-- | |- axi_vdma_skid_buf.vhd (s2mm)
-- | |- axi_vdma_cdc.vhd (s2mm)
-- |
-- |- axi_datamover_v3_00_a.axi_datamover.vhd (FULL)
-- |- axi_sg_v3_00_a.axi_sg.vhd
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2_8;
use axi_vdma_v6_2_8.axi_vdma_pkg.all;
-------------------------------------------------------------------------------
entity axi_vdma_reg_mux is
generic (
C_TOTAL_NUM_REGISTER : integer := 8 ;
-- Total number of defined registers for AXI VDMA. Used
-- to determine wrce and rdce vector widths.
C_INCLUDE_SG : integer range 0 to 1 := 1 ;
-- Include or Exclude Scatter Gather Engine
-- 0 = Exclude Scatter Gather Engine (Enables Register Direct Mode)
-- 1 = Include Scatter Gather Engine
C_CHANNEL_IS_MM2S : integer range 0 to 1 := 1 ;
-- Channel type for Read Mux
-- 0 = Channel is S2MM
-- 1 = Channel is MM2S
C_NUM_FSTORES : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_NUM_FSTORES_64 : integer range 1 to 32 := 3 ;
-- Number of Frame Stores
C_ENABLE_VIDPRMTR_READS : integer range 0 to 1 := 1 ;
-- Specifies whether video parameters are readable by axi_lite interface
-- when configure for Register Direct Mode
-- 0 = Disable Video Parameter Reads
-- 1 = Enable Video Parameter Reads
C_S_AXI_LITE_ADDR_WIDTH : integer range 9 to 9 := 9 ;
-- AXI Lite interface address width
C_S_AXI_LITE_DATA_WIDTH : integer range 32 to 32 := 32 ;
-- AXI Lite interface data width
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Scatter Gather engine Address Width
C_M_AXI_ADDR_WIDTH : integer range 32 to 32 := 32
-- Master AXI Memory Map Address Width for MM2S Write Port
);
port (
-----------------------------------------------------------------------
-- AXI Lite Control Interface
-----------------------------------------------------------------------
axi2ip_rdaddr : in std_logic_vector --
(C_S_AXI_LITE_ADDR_WIDTH-1 downto 0) ; --
axi2ip_rden : in std_logic ; --
ip2axi_rddata : out std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ip2axi_rddata_valid : out std_logic ; --
reg_index : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmacr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dmasr : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
dma_irq_mask : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
curdesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_lsb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
taildesc_msb : in std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
num_frame_store : in std_logic_vector --
(NUM_FRM_STORE_WIDTH-1 downto 0) ; --
linebuf_threshold : in std_logic_vector --
(THRESH_MSB_BIT downto 0) ; --
-- Register Direct Support --
reg_module_vsize : in std_logic_vector --
(VSIZE_DWIDTH-1 downto 0) ; --
reg_module_hsize : in std_logic_vector --
(HSIZE_DWIDTH-1 downto 0) ; --
reg_module_stride : in std_logic_vector --
(STRIDE_DWIDTH-1 downto 0) ; --
reg_module_frmdly : in std_logic_vector --
(FRMDLY_DWIDTH-1 downto 0) ; --
reg_module_start_address1 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address2 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address3 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address4 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address5 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address6 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address7 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address8 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address9 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address10 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address11 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address12 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address13 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address14 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address15 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address16 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address17 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address18 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address19 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address20 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address21 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address22 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address23 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address24 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address25 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address26 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address27 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address28 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address29 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address30 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address31 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) ; --
reg_module_start_address32 : in std_logic_vector --
(C_M_AXI_ADDR_WIDTH - 1 downto 0) --
);
end axi_vdma_reg_mux;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_vdma_reg_mux is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
ATTRIBUTE DONT_TOUCH : STRING;
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
constant VSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-VSIZE_DWIDTH;
constant VSIZE_PAD : std_logic_vector(VSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant HSIZE_PAD_WIDTH : integer := C_S_AXI_LITE_DATA_WIDTH-HSIZE_DWIDTH;
constant HSIZE_PAD : std_logic_vector(HSIZE_PAD_WIDTH-1 downto 0) := (others => '0');
constant FRMSTORE_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto FRMSTORE_MSB_BIT+1) := (others => '0');
constant THRESH_ZERO_PAD : std_logic_vector
(C_S_AXI_LITE_DATA_WIDTH - 1
downto THRESH_MSB_BIT+1) := (others => '0');
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal read_addr_ri : std_logic_vector(8 downto 0) := (others => '0');
signal read_addr : std_logic_vector(7 downto 0) := (others => '0');
signal read_addr_sg_1 : std_logic_vector(7 downto 0) := (others => '0');
signal ip2axi_rddata_int : std_logic_vector --
(C_S_AXI_LITE_DATA_WIDTH-1 downto 0) ; --
ATTRIBUTE DONT_TOUCH OF ip2axi_rddata_int : SIGNAL IS "true";
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
ip2axi_rddata <= ip2axi_rddata_int;
--*****************************************************************************
-- AXI LITE READ MUX
--*****************************************************************************
-- Register module is for MM2S Channel therefore look at
-- MM2S Register offsets
GEN_READ_MUX_FOR_MM2S : if C_CHANNEL_IS_MM2S = 1 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
curdesc_msb ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when MM2S_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_CURDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when MM2S_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when MM2S_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when MM2S_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_MM2S;
-- Register module is for S2MM Channel therefore look at
-- S2MM Register offsets
GEN_READ_MUX_FOR_S2MM : if C_CHANNEL_IS_MM2S = 0 generate
begin
-- Scatter Gather Mode Read MUX
GEN_READ_MUX_SG : if C_INCLUDE_SG = 1 generate
begin
--read_addr <= axi2ip_rdaddr(9 downto 0);
read_addr_sg_1 <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr_sg_1 ,
axi2ip_rden ,
dmacr ,
dmasr ,
curdesc_lsb ,
dma_irq_mask ,
taildesc_lsb ,
taildesc_msb ,
num_frame_store,
linebuf_threshold)
begin
case read_addr_sg_1 is
when S2MM_DMACR_OFFSET_SG =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_SG =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_CURDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= curdesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_SG =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_LSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_lsb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_TAILDESC_MSB_OFFSET_SG =>
ip2axi_rddata_int <= taildesc_msb;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_SG =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_SG =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_SG;
-- Register Direct Mode Read MUX
GEN_READ_MUX_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 1 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
read_addr_ri <= reg_index(0) & axi2ip_rdaddr(7 downto 0);
-- 17 start addresses
-- 1 start addresses
GEN_FSTORES_1 : if C_NUM_FSTORES = 1 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_1;
-- 2 start addresses
GEN_FSTORES_2 : if C_NUM_FSTORES = 2 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_2;
-- 3 start addresses
GEN_FSTORES_3 : if C_NUM_FSTORES = 3 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_3;
-- 4 start addresses
GEN_FSTORES_4 : if C_NUM_FSTORES = 4 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_4;
-- 5 start addresses
GEN_FSTORES_5 : if C_NUM_FSTORES = 5 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_5;
-- 6 start addresses
GEN_FSTORES_6 : if C_NUM_FSTORES = 6 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_6;
-- 7 start addresses
GEN_FSTORES_7 : if C_NUM_FSTORES = 7 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_7;
-- 8 start addresses
GEN_FSTORES_8 : if C_NUM_FSTORES = 8 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_8;
-- 9 start addresses
GEN_FSTORES_9 : if C_NUM_FSTORES = 9 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_9;
-- 10 start addresses
GEN_FSTORES_10 : if C_NUM_FSTORES = 10 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_10;
-- 11 start addresses
GEN_FSTORES_11 : if C_NUM_FSTORES = 11 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_11;
-- 12 start addresses
GEN_FSTORES_12 : if C_NUM_FSTORES = 12 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_12;
-- 13 start addresses
GEN_FSTORES_13 : if C_NUM_FSTORES = 13 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_13;
-- 14 start addresses
GEN_FSTORES_14 : if C_NUM_FSTORES = 14 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_14;
-- 15 start addresses
GEN_FSTORES_15 : if C_NUM_FSTORES = 15 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_15;
-- 16 start addresses
GEN_FSTORES_16 : if C_NUM_FSTORES = 16 generate
begin
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_8 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_8 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_8 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_8 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_16;
-- 17 start addresses
GEN_FSTORES_17 : if C_NUM_FSTORES = 17 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_17;
-- 18 start addresses
GEN_FSTORES_18 : if C_NUM_FSTORES = 18 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_18;
-- 19 start addresses
GEN_FSTORES_19 : if C_NUM_FSTORES = 19 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_19;
-- 20 start addresses
GEN_FSTORES_20 : if C_NUM_FSTORES = 20 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_20;
-- 21 start addresses
GEN_FSTORES_21 : if C_NUM_FSTORES = 21 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_21;
-- 22 start addresses
GEN_FSTORES_22 : if C_NUM_FSTORES = 22 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_22;
-- 23 start addresses
GEN_FSTORES_23 : if C_NUM_FSTORES = 23 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_23;
-- 24 start addresses
GEN_FSTORES_24 : if C_NUM_FSTORES = 24 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_24;
-- 25 start addresses
GEN_FSTORES_25 : if C_NUM_FSTORES = 25 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_25;
-- 26 start addresses
GEN_FSTORES_26 : if C_NUM_FSTORES = 26 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_26;
-- 27 start addresses
GEN_FSTORES_27 : if C_NUM_FSTORES = 27 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_27;
-- 28 start addresses
GEN_FSTORES_28 : if C_NUM_FSTORES = 28 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_28;
-- 29 start addresses
GEN_FSTORES_29 : if C_NUM_FSTORES = 29 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_29;
-- 30 start addresses
GEN_FSTORES_30 : if C_NUM_FSTORES = 30 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_30;
-- 31 start addresses
GEN_FSTORES_31 : if C_NUM_FSTORES = 31 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_31;
-- 32 start addresses
GEN_FSTORES_32 : if C_NUM_FSTORES = 32 generate
begin
AXI_LITE_READ_MUX : process(read_addr_ri ,
axi2ip_rden ,
dmacr ,
dmasr , reg_index ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold ,
reg_module_vsize ,
reg_module_hsize ,
reg_module_stride ,
reg_module_frmdly ,
reg_module_start_address1 ,
reg_module_start_address2 ,
reg_module_start_address3 ,
reg_module_start_address4 ,
reg_module_start_address5 ,
reg_module_start_address6 ,
reg_module_start_address7 ,
reg_module_start_address8 ,
reg_module_start_address9 ,
reg_module_start_address10 ,
reg_module_start_address11 ,
reg_module_start_address12 ,
reg_module_start_address13 ,
reg_module_start_address14 ,
reg_module_start_address15 ,
reg_module_start_address16 ,
reg_module_start_address17 ,
reg_module_start_address18 ,
reg_module_start_address19 ,
reg_module_start_address20 ,
reg_module_start_address21 ,
reg_module_start_address22 ,
reg_module_start_address23 ,
reg_module_start_address24 ,
reg_module_start_address25 ,
reg_module_start_address26 ,
reg_module_start_address27 ,
reg_module_start_address28 ,
reg_module_start_address29 ,
reg_module_start_address30 ,
reg_module_start_address31 ,
reg_module_start_address32)
begin
case read_addr_ri is
when S2MM_DMACR_OFFSET_90 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_90 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_90 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_90 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_90 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_90 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_90 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_90 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_90 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMACR_OFFSET_91 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_91 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_OFFSET_91 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_91 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_91 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_91 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_VSIZE_OFFSET_91 =>
ip2axi_rddata_int <= VSIZE_PAD & reg_module_vsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_HSIZE_OFFSET_91 =>
ip2axi_rddata_int <= HSIZE_PAD & reg_module_hsize;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DLYSTRD_OFFSET_91 =>
ip2axi_rddata_int <= RSVD_BITS_31TO29
& reg_module_frmdly
& RSVD_BITS_23TO16
& reg_module_stride;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR1_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address1;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR2_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address2;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR3_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address3;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR4_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address4;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR5_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address5;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR6_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address6;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR7_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address7;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR8_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address8;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR9_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address9;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR10_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address10;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR11_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address11;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR12_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address12;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR13_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address13;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR14_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address14;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR15_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address15;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR16_OFFSET_90 =>
ip2axi_rddata_int <= reg_module_start_address16;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR17_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address17;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR18_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address18;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR19_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address19;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR20_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address20;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR21_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address21;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR22_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address22;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR23_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address23;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR24_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address24;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR25_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address25;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR26_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address26;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR27_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address27;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR28_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address28;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR29_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address29;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR30_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address30;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR31_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address31;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_STARTADDR32_OFFSET_91 =>
ip2axi_rddata_int <= reg_module_start_address32;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_FSTORES_32;
end generate GEN_READ_MUX_REG_DIRECT;
-- Register Direct Mode Read MUX
GEN_READ_MUX_LITE_REG_DIRECT : if C_INCLUDE_SG = 0 and C_ENABLE_VIDPRMTR_READS = 0 generate
begin
read_addr <= axi2ip_rdaddr(7 downto 0);
AXI_LITE_READ_MUX : process(read_addr ,
axi2ip_rden ,
dmacr ,
reg_index ,
dmasr ,
dma_irq_mask ,
num_frame_store ,
linebuf_threshold)
begin
case read_addr is
when S2MM_DMACR_OFFSET_8 =>
ip2axi_rddata_int <= dmacr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMASR_OFFSET_8 =>
ip2axi_rddata_int <= dmasr;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_DMA_IRQ_MASK_8 =>
ip2axi_rddata_int <= dma_irq_mask;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_REG_INDEX_OFFSET_8 =>
ip2axi_rddata_int <= reg_index;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_FRAME_STORE_OFFSET_8 =>
ip2axi_rddata_int <= FRMSTORE_ZERO_PAD
& num_frame_store;
ip2axi_rddata_valid <= axi2ip_rden;
when S2MM_THRESHOLD_OFFSET_8 =>
ip2axi_rddata_int <= THRESH_ZERO_PAD
& linebuf_threshold;
ip2axi_rddata_valid <= axi2ip_rden;
when others =>
ip2axi_rddata_int <= (others => '0');
ip2axi_rddata_valid <= '0';
end case;
end process AXI_LITE_READ_MUX;
end generate GEN_READ_MUX_LITE_REG_DIRECT;
end generate GEN_READ_MUX_FOR_S2MM;
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
entity RF is
Port ( rs1 : in STD_LOGIC_VECTOR (4 downto 0);
rs2 : in STD_LOGIC_VECTOR (4 downto 0);
rd : in STD_LOGIC_VECTOR (4 downto 0);
DWR : in STD_LOGIC_VECTOR (31 downto 0);
rst : in STD_LOGIC;
Crs1 : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0');
Crs2 : out STD_LOGIC_VECTOR (31 downto 0):=(others=>'0'));
end RF;
architecture Behavioral of RF is
type ram_type is array (31 downto 0) of std_logic_vector (31 downto 0);
signal RAM: ram_type:=(others => "00000000000000000000000000000000");
--registro g0 siempre es cero
begin
process (rs1,rs2,rd,DWR,rst,RAM)
begin
if rst='0' then
if rd >"00000" then
RAM(conv_integer(rd)) <= DWR;
end if;
Crs1<=RAM(conv_integer(rs1));
Crs2<=RAM(conv_integer(rs2));
else
RAM<=(others => "00000000000000000000000000000000");
Crs1<=(others=>'0');
Crs2<=(others=>'0');
end if;
end process;
end Behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gleichmann;
use gleichmann.dac.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity adcdac is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer := 10 -- GPIO bits
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
adcdaci : in adcdac_in_type;
adcdaco : out adcdac_out_type
);
end;
architecture rtl of adcdac is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_ADCDAC, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is
record
dac_reg : std_logic_vector(nbits-1 downto 0);
adc_reg : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
-- ADC signals
signal valid : std_ulogic;
signal adc_out_par : std_logic_vector(nbits-1 downto 0);
signal rst_inv : std_ulogic;
begin
comb : process(adc_out_par, apbi, r, rst, valid)
variable readdata : std_logic_vector(31 downto 0);
variable v : registers;
begin
-- read registers
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" => readdata(nbits-1 downto 0) := r.dac_reg;
when "001" => readdata(nbits-1 downto 0) := r.adc_reg;
when others => null;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" => v.dac_reg := apbi.pwdata(nbits-1 downto 0);
when "001" => null;
when others => null;
end case;
end if;
-- update ADC value
if valid = '1' then
v.adc_reg := adc_out_par;
end if;
-- reset operation
if rst = '0' then
v.dac_reg := (others => '0');
v.adc_reg := (others => '0');
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= (others => '0');
end process comb;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
rst_inv <= not rst;
dac : sigdelt
generic map (
c_dacin_length => nbits)
port map (
reset => rst_inv,
clock => clk,
dac_in => r.dac_reg(nbits-1 downto 0),
dac_out => adcdaco.dac_out);
adc : adc_sigdelt
generic map (
c_adcin_length => nbits)
port map (
rstn => rst,
clk => clk,
valid => valid,
adc_fb => adcdaco.adc_fb,
adc_out => adc_out_par,
adc_in => adcdaci.adc_in);
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("adcdac" & tost(pindex) &
": " & tost(nbits) & "-bit ADC/DAC core rev " & tost(REVISION));
-- pragma translate_on
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gleichmann;
use gleichmann.dac.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity adcdac is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer := 10 -- GPIO bits
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
adcdaci : in adcdac_in_type;
adcdaco : out adcdac_out_type
);
end;
architecture rtl of adcdac is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GLEICHMANN, GLEICHMANN_ADCDAC, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is
record
dac_reg : std_logic_vector(nbits-1 downto 0);
adc_reg : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
-- ADC signals
signal valid : std_ulogic;
signal adc_out_par : std_logic_vector(nbits-1 downto 0);
signal rst_inv : std_ulogic;
begin
comb : process(adc_out_par, apbi, r, rst, valid)
variable readdata : std_logic_vector(31 downto 0);
variable v : registers;
begin
-- read registers
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" => readdata(nbits-1 downto 0) := r.dac_reg;
when "001" => readdata(nbits-1 downto 0) := r.adc_reg;
when others => null;
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" => v.dac_reg := apbi.pwdata(nbits-1 downto 0);
when "001" => null;
when others => null;
end case;
end if;
-- update ADC value
if valid = '1' then
v.adc_reg := adc_out_par;
end if;
-- reset operation
if rst = '0' then
v.dac_reg := (others => '0');
v.adc_reg := (others => '0');
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
apbo.pirq <= (others => '0');
end process comb;
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
rst_inv <= not rst;
dac : sigdelt
generic map (
c_dacin_length => nbits)
port map (
reset => rst_inv,
clock => clk,
dac_in => r.dac_reg(nbits-1 downto 0),
dac_out => adcdaco.dac_out);
adc : adc_sigdelt
generic map (
c_adcin_length => nbits)
port map (
rstn => rst,
clk => clk,
valid => valid,
adc_fb => adcdaco.adc_fb,
adc_out => adc_out_par,
adc_in => adcdaci.adc_in);
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("adcdac" & tost(pindex) &
": " & tost(nbits) & "-bit ADC/DAC core rev " & tost(REVISION));
-- pragma translate_on
end architecture rtl;
|
--------------------------------------------------------------------------------
-- system_xadc_wiz_0_0_family_support.vhd - package
--------------------------------------------------------------------------------
--
-- *************************************************************************
-- ** **
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This text/file contains proprietary, confidential **
-- ** information of Xilinx, Inc., is distributed under **
-- ** license from Xilinx, Inc., and may be used, copied **
-- ** and/or disclosed only pursuant to the terms of a valid **
-- ** license agreement with Xilinx, Inc. Xilinx hereby **
-- ** grants you a license to use this text/file solely for **
-- ** design, simulation, implementation and creation of **
-- ** design files limited to Xilinx devices or technologies. **
-- ** Use with non-Xilinx devices or technologies is expressly **
-- ** prohibited and immediately terminates your license unless **
-- ** covered by a separate agreement. **
-- ** **
-- ** Xilinx is providing this design, code, or information **
-- ** "as-is" solely for use in developing programs and **
-- ** solutions for Xilinx devices, with no obligation on the **
-- ** part of Xilinx to provide support. By providing this design, **
-- ** code, or information as one possible implementation of **
-- ** this feature, application or standard, Xilinx is making no **
-- ** representation that this implementation is free from any **
-- ** claims of infringement. You are responsible for obtaining **
-- ** any rights you may require for your implementation. **
-- ** Xilinx expressly disclaims any warranty whatsoever with **
-- ** respect to the adequacy of the implementation, including **
-- ** but not limited to any warranties or representations that this **
-- ** implementation is free from claims of infringement, implied **
-- ** warranties of merchantability or fitness for a particular **
-- ** purpose. **
-- ** **
-- ** Xilinx products are not intended for use in life support **
-- ** appliances, devices, or systems. Use in such applications is **
-- ** expressly prohibited. **
-- ** **
-- ** Any modifications that are made to the Source Code are **
-- ** done at the users sole risk and will be unsupported. **
-- ** The Xilinx Support Hotline does not have access to source **
-- ** code and therefore cannot answer specific questions related **
-- ** to source HDL. The Xilinx Hotline support of original source **
-- ** code IP shall only address issues and questions related **
-- ** to the standard Netlist version of the core (and thus **
-- ** indirectly, the original core source). **
-- ** **
-- ** Copyright (c) 2005-2010 Xilinx, Inc. All rights reserved. **
-- ** **
-- ** This copyright and support notice must be retained as part **
-- ** of this text at all times. **
-- ** **
-- *************************************************************************
--
--------------------------------------------------------------------------------
-- Filename: system_xadc_wiz_0_0_family_support.vhd
--
-- Description:
--
-- FAMILIES, PRIMITIVES and PRIMITIVE AVAILABILITY GUARDS
--
-- This package allows to determine whether a given primitive
-- or set of primitives is available in an FPGA family of interest.
--
-- The key element is the function, 'supported', which is
-- available in four variants (overloads). Here are examples
-- of each:
--
-- supported(virtex2, u_RAMB16_S2)
--
-- supported("Virtex2", u_RAMB16_S2)
--
-- supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
--
-- supported("spartan3", (u_MUXCY, u_XORCY, u_FD))
--
-- The 'supported' function returns true if and only
-- if all of the primitives being tested, as given in the
-- second argument, are available in the FPGA family that
-- is given in the first argument.
--
-- The first argument can be either one of the FPGA family
-- names from the enumeration type, 'families_type', or a
-- (case insensitive) string giving the same information.
-- The family name 'nofamily' is special and supports
-- none of the primitives.
--
-- The second argument is either a primitive or a list of
-- primitives. The set of primitive names that can be
-- tested is defined by the declaration of the
-- enumeration type, 'primitives_type'. The names are
-- the UNISIM-library names for the primitives, prefixed
-- by "u_". (The prefix avoids introducing a name that
-- conflicts with the component declaration for the primitive.)
--
-- The array type, 'primitive_array_type' is the basis for
-- forming lists of primitives. Typically, a fixed list
-- of primitves is expressed as a VHDL aggregate, a
-- comma separated list of primitives enclosed in
-- parentheses. (See the last two examples, above.)
--
-- The 'supported' function can be used as a guard
-- condition for a piece of code that depends on primitives
-- (primitive availability guard). Here is an example:
--
--
-- GEN : if supported(C_FAMILY, (u_MUXCY, u_XORCY)) generate
-- begin
-- ... Here, an implementation that depends on
-- ... MUXCY and XORCY.
-- end generate;
--
--
-- It can also be used in an assertion statement
-- to give warnings about problems that can arise from
-- attempting to implement into a family that does not
-- support all of the required primitives:
--
--
-- assert supported(C_FAMILY, <primtive list>)
-- report "This module cannot be implemnted " &
-- "into family, " & C_FAMILY &
-- ", because one or more of the primitives, " &
-- "<primitive_list>" & ", is not supported."
-- severity error;
--
--
-- A NOTE ON USAGE
--
-- It is probably best to take an exception to the coding
-- guidelines and make the names that are needed
-- from this package visible to a VHDL compilation unit by
--
-- library <libname>;
-- use <libname>.system_xadc_wiz_0_0_family_support.all;
--
-- rather than by calling out individual names in use clauses.
-- (VHDL tools do not have a common interpretation at present
-- on whether
--
-- use <libname>.system_xadc_wiz_0_0_family_support.primitives_type"
--
-- makes the enumeration literals visible.)
--
-- ADDITIONAL FEATURES
--
-- - A function, native_lut_size, is available to allow
-- the caller to query the largest sized LUT available in a given
-- FPGA family.
--
-- - A function, equalIgnoringCase, is available to compare strings
-- with case insensitivity. While this can be used to establish
-- whether the target family is some particular family, such
-- usage is discouraged and should be limited to legacy
-- situations or the rare situations where primitive
-- availability guards will not suffice.
--
--------------------------------------------------------------------------------
-- Author: FLO
-- History:
-- FLO 2005Mar24 - First Version
--
-- FLO 11/30/05
-- ^^^^^^
-- Virtex5 added.
-- ~~~~~~
-- TK 03/17/06 Corrected a Spartan3e issue in myimage
-- ~~~~~~
-- FLO 04/26/06
-- ^^^^^^
-- Added the native_lut_size function.
-- ~~~~~~
-- FLO 08/10/06
-- ^^^^^^
-- Added support for families virtex, spartan2 and spartan2e.
-- ~~~~~~
-- FLO 08/25/06
-- ^^^^^^
-- Enhanced the warning in function str2fam. Now when a string that is
-- passed in the call as a parameter does not correspond to a supported fpga
-- family, the string value of the passed string is mentioned in the warning
-- and it is explicitly stated that the returned value is 'nofamily'.
-- ~~~~~~
-- FLO 08/26/06
-- ^^^^^^
-- - Updated the virtex5 primitive set to a more recent list and
-- removed primitives (TEMAC, PCIE, etc.) that are not present
-- in all virtex5 family members.
-- - Added function equalIgnoringCase and an admonition to use it
-- as little as possible.
-- - Made some improvements to descriptions inside comments.
-- ~~~~~~
-- FLO 08/28/06
-- ^^^^^^
-- Added support for families spartan3a and spartan3an. These are initially
-- taken to have the same primitives as spartan3e.
-- ~~~~~~
-- FLO 10/28/06
-- ^^^^^^
-- Changed function str2fam so that it no longer depends on the VHDL
-- attribute, 'VAL. This is an XST workaround.
-- ~~~~~~
-- FLO 03/08/07
-- ^^^^^^
-- Updated spartan3a and sparan3an.
-- Added spartan3adsp.
-- ~~~~~~
-- FLO 08/31/07
-- ^^^^^^
-- A performance XST workaround was implemented to address slowness
-- associated with primitive availability guards. The workaround changes
-- the way that the fam_has_prim constant is initialized (aggregate
-- rather than a system of function and procedure calls).
-- ~~~~~~
-- FLO 04/11/08
-- ^^^^^^
-- Added these families: aspartan3e, aspartan3a, aspartan3an, aspartan3adsp
-- ~~~~~~
-- FLO 04/14/08
-- ^^^^^^
-- Removed family: aspartan3an
-- ~~~~~~
-- FLO 06/25/08
-- ^^^^^^
-- Added these families: qvirtex4, qrvirtex4
-- ~~~~~~
-- FLO 07/26/08
-- ^^^^^^
-- The BSCAN primitive for spartan3e is now BSCAN_SPARTAN3 instead
-- of BSCAN_SPARTAN3E.
-- ~~~~~~
-- FLO 09/02/06
-- ^^^^^^
-- Added an initial approximation of primitives for spartan6 and virtex6.
-- ~~~~~~
-- FLO 09/04/28
-- ^^^^^^
-- -Removed primitive u_BSCAN_SPARTAN3A from spartan6.
-- -Added the 5 and 6 LUTs to spartan6.
-- ~~~~~~
-- FLO 02/09/10 (back to MM/DD/YY)
-- ^^^^^^
-- -Removed primitive u_BSCAN_VIRTEX5 from virtex6.
-- -Added families spartan6l, qspartan6, aspartan6 and virtex6l.
-- ~~~~~~
-- FLO 04/26/10 (MM/DD/YY)
-- ^^^^^^
-- -Added families qspartan6l, qvirtex5 and qvirtex6.
-- ~~~~~~
-- FLO 06/21/10 (MM/DD/YY)
-- ^^^^^^
-- -Added family qrvirtex5.
-- ~~~~~~
--
-- DET 9/7/2010 For 12.4
-- ~~~~~~
-- -- Per CR573867
-- - Added the function get_root_family() as part of the derivative part
-- support improvements.
-- - Added the Virtex7 and Kintex7 device families
-- ^^^^^^
-- ~~~~~~
-- FLO 10/28/10 (MM/DD/YY)
-- ^^^^^^
-- -Added u_SRLC32E as supported for spartan6 (and its derivatives). (CR 575828)
-- ~~~~~~
-- FLO 12/15/10 (MM/DD/YY)
-- ^^^^^^
-- -Changed virtex6cx to be equal to virtex6 (instead of virtex5)
-- -Move kintex7 and virtex7 to the primitives in the Rodin unisim.btl file
-- -Added artix7 from the primitives in the Rodin unisim.btl file
-- ~~~~~~
--
-- DET 3/2/2011 EDk 13.2
-- ~~~~~~
-- -- Per CR595477
-- - Added zynq support in the get_root_family function.
-- ^^^^^^
--
-- DET 03/18/2011
-- ^^^^^^
-- Per CR602290
-- - Added u_RAMB16_S4_S36 for kintex7, virtex7, artix7 to grandfather axi_ethernetlite_v1_00_a.
-- - This change was lost from 13.1 O.40d to 13.2 branch.
-- - Copied the Virtex7 primitive info to zynq primitive entry (instead of the artix7 info)
-- ~~~~~~
--
-- DET 4/4/2011 EDK 13.2
-- ~~~~~~
-- -- Per CR604652
-- - Added kintex7l and virtex7l
-- ^^^^^^
--
--------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "clk", "clk_div#", "clk_#x"
-- reset signals: "rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinational signals: "*_cmb"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port: "*_i"
-- device pins: "*_pin"
-- ports:- Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
--------------------------------------------------------------------------------
package system_xadc_wiz_0_0_family_support is
type families_type is
(
nofamily
, virtex
, spartan2
, spartan2e
, virtexe
, virtex2
, qvirtex2 -- Taken to be identical to the virtex2 primitive set.
, qrvirtex2 -- Taken to be identical to the virtex2 primitive set.
, virtex2p
, spartan3
, aspartan3
, virtex4
, virtex4lx
, virtex4fx
, virtex4sx
, spartan3e
, virtex5
, spartan3a
, spartan3an
, spartan3adsp
, aspartan3e
, aspartan3a
, aspartan3adsp
, qvirtex4
, qrvirtex4
, spartan6
, virtex6
, spartan6l
, qspartan6
, aspartan6
, virtex6l
, qspartan6l
, qvirtex5
, qvirtex6
, qrvirtex5
, virtex5tx
, virtex5fx
, virtex6cx
, kintex7
, kintex7l
, qkintex7
, qkintex7l
, virtex7
, virtex7l
, qvirtex7
, qvirtex7l
, artix7
, aartix7
, artix7l
, qartix7
, zynq
, azynq
, qzynq
);
type primitives_type is range 0 to 798;
constant u_AND2: primitives_type := 0;
constant u_AND2B1L: primitives_type := u_AND2 + 1;
constant u_AND3: primitives_type := u_AND2B1L + 1;
constant u_AND4: primitives_type := u_AND3 + 1;
constant u_AUTOBUF: primitives_type := u_AND4 + 1;
constant u_BSCAN_SPARTAN2: primitives_type := u_AUTOBUF + 1;
constant u_BSCAN_SPARTAN3: primitives_type := u_BSCAN_SPARTAN2 + 1;
constant u_BSCAN_SPARTAN3A: primitives_type := u_BSCAN_SPARTAN3 + 1;
constant u_BSCAN_SPARTAN3E: primitives_type := u_BSCAN_SPARTAN3A + 1;
constant u_BSCAN_SPARTAN6: primitives_type := u_BSCAN_SPARTAN3E + 1;
constant u_BSCAN_VIRTEX: primitives_type := u_BSCAN_SPARTAN6 + 1;
constant u_BSCAN_VIRTEX2: primitives_type := u_BSCAN_VIRTEX + 1;
constant u_BSCAN_VIRTEX4: primitives_type := u_BSCAN_VIRTEX2 + 1;
constant u_BSCAN_VIRTEX5: primitives_type := u_BSCAN_VIRTEX4 + 1;
constant u_BSCAN_VIRTEX6: primitives_type := u_BSCAN_VIRTEX5 + 1;
constant u_BUF: primitives_type := u_BSCAN_VIRTEX6 + 1;
constant u_BUFCF: primitives_type := u_BUF + 1;
constant u_BUFE: primitives_type := u_BUFCF + 1;
constant u_BUFG: primitives_type := u_BUFE + 1;
constant u_BUFGCE: primitives_type := u_BUFG + 1;
constant u_BUFGCE_1: primitives_type := u_BUFGCE + 1;
constant u_BUFGCTRL: primitives_type := u_BUFGCE_1 + 1;
constant u_BUFGDLL: primitives_type := u_BUFGCTRL + 1;
constant u_BUFGMUX: primitives_type := u_BUFGDLL + 1;
constant u_BUFGMUX_1: primitives_type := u_BUFGMUX + 1;
constant u_BUFGMUX_CTRL: primitives_type := u_BUFGMUX_1 + 1;
constant u_BUFGMUX_VIRTEX4: primitives_type := u_BUFGMUX_CTRL + 1;
constant u_BUFGP: primitives_type := u_BUFGMUX_VIRTEX4 + 1;
constant u_BUFH: primitives_type := u_BUFGP + 1;
constant u_BUFHCE: primitives_type := u_BUFH + 1;
constant u_BUFIO: primitives_type := u_BUFHCE + 1;
constant u_BUFIO2: primitives_type := u_BUFIO + 1;
constant u_BUFIO2_2CLK: primitives_type := u_BUFIO2 + 1;
constant u_BUFIO2FB: primitives_type := u_BUFIO2_2CLK + 1;
constant u_BUFIO2FB_2CLK: primitives_type := u_BUFIO2FB + 1;
constant u_BUFIODQS: primitives_type := u_BUFIO2FB_2CLK + 1;
constant u_BUFPLL: primitives_type := u_BUFIODQS + 1;
constant u_BUFPLL_MCB: primitives_type := u_BUFPLL + 1;
constant u_BUFR: primitives_type := u_BUFPLL_MCB + 1;
constant u_BUFT: primitives_type := u_BUFR + 1;
constant u_CAPTURE_SPARTAN2: primitives_type := u_BUFT + 1;
constant u_CAPTURE_SPARTAN3: primitives_type := u_CAPTURE_SPARTAN2 + 1;
constant u_CAPTURE_SPARTAN3A: primitives_type := u_CAPTURE_SPARTAN3 + 1;
constant u_CAPTURE_SPARTAN3E: primitives_type := u_CAPTURE_SPARTAN3A + 1;
constant u_CAPTURE_VIRTEX: primitives_type := u_CAPTURE_SPARTAN3E + 1;
constant u_CAPTURE_VIRTEX2: primitives_type := u_CAPTURE_VIRTEX + 1;
constant u_CAPTURE_VIRTEX4: primitives_type := u_CAPTURE_VIRTEX2 + 1;
constant u_CAPTURE_VIRTEX5: primitives_type := u_CAPTURE_VIRTEX4 + 1;
constant u_CAPTURE_VIRTEX6: primitives_type := u_CAPTURE_VIRTEX5 + 1;
constant u_CARRY4: primitives_type := u_CAPTURE_VIRTEX6 + 1;
constant u_CFGLUT5: primitives_type := u_CARRY4 + 1;
constant u_CLKDLL: primitives_type := u_CFGLUT5 + 1;
constant u_CLKDLLE: primitives_type := u_CLKDLL + 1;
constant u_CLKDLLHF: primitives_type := u_CLKDLLE + 1;
constant u_CRC32: primitives_type := u_CLKDLLHF + 1;
constant u_CRC64: primitives_type := u_CRC32 + 1;
constant u_DCIRESET: primitives_type := u_CRC64 + 1;
constant u_DCM: primitives_type := u_DCIRESET + 1;
constant u_DCM_ADV: primitives_type := u_DCM + 1;
constant u_DCM_BASE: primitives_type := u_DCM_ADV + 1;
constant u_DCM_CLKGEN: primitives_type := u_DCM_BASE + 1;
constant u_DCM_PS: primitives_type := u_DCM_CLKGEN + 1;
constant u_DNA_PORT: primitives_type := u_DCM_PS + 1;
constant u_DSP48: primitives_type := u_DNA_PORT + 1;
constant u_DSP48A: primitives_type := u_DSP48 + 1;
constant u_DSP48A1: primitives_type := u_DSP48A + 1;
constant u_DSP48E: primitives_type := u_DSP48A1 + 1;
constant u_DSP48E1: primitives_type := u_DSP48E + 1;
constant u_DUMMY_INV: primitives_type := u_DSP48E1 + 1;
constant u_DUMMY_NOR2: primitives_type := u_DUMMY_INV + 1;
constant u_EFUSE_USR: primitives_type := u_DUMMY_NOR2 + 1;
constant u_EMAC: primitives_type := u_EFUSE_USR + 1;
constant u_FD: primitives_type := u_EMAC + 1;
constant u_FD_1: primitives_type := u_FD + 1;
constant u_FDC: primitives_type := u_FD_1 + 1;
constant u_FDC_1: primitives_type := u_FDC + 1;
constant u_FDCE: primitives_type := u_FDC_1 + 1;
constant u_FDCE_1: primitives_type := u_FDCE + 1;
constant u_FDCP: primitives_type := u_FDCE_1 + 1;
constant u_FDCP_1: primitives_type := u_FDCP + 1;
constant u_FDCPE: primitives_type := u_FDCP_1 + 1;
constant u_FDCPE_1: primitives_type := u_FDCPE + 1;
constant u_FDDRCPE: primitives_type := u_FDCPE_1 + 1;
constant u_FDDRRSE: primitives_type := u_FDDRCPE + 1;
constant u_FDE: primitives_type := u_FDDRRSE + 1;
constant u_FDE_1: primitives_type := u_FDE + 1;
constant u_FDP: primitives_type := u_FDE_1 + 1;
constant u_FDP_1: primitives_type := u_FDP + 1;
constant u_FDPE: primitives_type := u_FDP_1 + 1;
constant u_FDPE_1: primitives_type := u_FDPE + 1;
constant u_FDR: primitives_type := u_FDPE_1 + 1;
constant u_FDR_1: primitives_type := u_FDR + 1;
constant u_FDRE: primitives_type := u_FDR_1 + 1;
constant u_FDRE_1: primitives_type := u_FDRE + 1;
constant u_FDRS: primitives_type := u_FDRE_1 + 1;
constant u_FDRS_1: primitives_type := u_FDRS + 1;
constant u_FDRSE: primitives_type := u_FDRS_1 + 1;
constant u_FDRSE_1: primitives_type := u_FDRSE + 1;
constant u_FDS: primitives_type := u_FDRSE_1 + 1;
constant u_FDS_1: primitives_type := u_FDS + 1;
constant u_FDSE: primitives_type := u_FDS_1 + 1;
constant u_FDSE_1: primitives_type := u_FDSE + 1;
constant u_FIFO16: primitives_type := u_FDSE_1 + 1;
constant u_FIFO18: primitives_type := u_FIFO16 + 1;
constant u_FIFO18_36: primitives_type := u_FIFO18 + 1;
constant u_FIFO18E1: primitives_type := u_FIFO18_36 + 1;
constant u_FIFO36: primitives_type := u_FIFO18E1 + 1;
constant u_FIFO36_72: primitives_type := u_FIFO36 + 1;
constant u_FIFO36E1: primitives_type := u_FIFO36_72 + 1;
constant u_FMAP: primitives_type := u_FIFO36E1 + 1;
constant u_FRAME_ECC_VIRTEX4: primitives_type := u_FMAP + 1;
constant u_FRAME_ECC_VIRTEX5: primitives_type := u_FRAME_ECC_VIRTEX4 + 1;
constant u_FRAME_ECC_VIRTEX6: primitives_type := u_FRAME_ECC_VIRTEX5 + 1;
constant u_GND: primitives_type := u_FRAME_ECC_VIRTEX6 + 1;
constant u_GT10_10GE_4: primitives_type := u_GND + 1;
constant u_GT10_10GE_8: primitives_type := u_GT10_10GE_4 + 1;
constant u_GT10_10GFC_4: primitives_type := u_GT10_10GE_8 + 1;
constant u_GT10_10GFC_8: primitives_type := u_GT10_10GFC_4 + 1;
constant u_GT10_AURORA_1: primitives_type := u_GT10_10GFC_8 + 1;
constant u_GT10_AURORA_2: primitives_type := u_GT10_AURORA_1 + 1;
constant u_GT10_AURORA_4: primitives_type := u_GT10_AURORA_2 + 1;
constant u_GT10_AURORAX_4: primitives_type := u_GT10_AURORA_4 + 1;
constant u_GT10_AURORAX_8: primitives_type := u_GT10_AURORAX_4 + 1;
constant u_GT10_CUSTOM: primitives_type := u_GT10_AURORAX_8 + 1;
constant u_GT10_INFINIBAND_1: primitives_type := u_GT10_CUSTOM + 1;
constant u_GT10_INFINIBAND_2: primitives_type := u_GT10_INFINIBAND_1 + 1;
constant u_GT10_INFINIBAND_4: primitives_type := u_GT10_INFINIBAND_2 + 1;
constant u_GT10_OC192_4: primitives_type := u_GT10_INFINIBAND_4 + 1;
constant u_GT10_OC192_8: primitives_type := u_GT10_OC192_4 + 1;
constant u_GT10_OC48_1: primitives_type := u_GT10_OC192_8 + 1;
constant u_GT10_OC48_2: primitives_type := u_GT10_OC48_1 + 1;
constant u_GT10_OC48_4: primitives_type := u_GT10_OC48_2 + 1;
constant u_GT10_PCI_EXPRESS_1: primitives_type := u_GT10_OC48_4 + 1;
constant u_GT10_PCI_EXPRESS_2: primitives_type := u_GT10_PCI_EXPRESS_1 + 1;
constant u_GT10_PCI_EXPRESS_4: primitives_type := u_GT10_PCI_EXPRESS_2 + 1;
constant u_GT10_XAUI_1: primitives_type := u_GT10_PCI_EXPRESS_4 + 1;
constant u_GT10_XAUI_2: primitives_type := u_GT10_XAUI_1 + 1;
constant u_GT10_XAUI_4: primitives_type := u_GT10_XAUI_2 + 1;
constant u_GT11CLK: primitives_type := u_GT10_XAUI_4 + 1;
constant u_GT11CLK_MGT: primitives_type := u_GT11CLK + 1;
constant u_GT11_CUSTOM: primitives_type := u_GT11CLK_MGT + 1;
constant u_GT_AURORA_1: primitives_type := u_GT11_CUSTOM + 1;
constant u_GT_AURORA_2: primitives_type := u_GT_AURORA_1 + 1;
constant u_GT_AURORA_4: primitives_type := u_GT_AURORA_2 + 1;
constant u_GT_CUSTOM: primitives_type := u_GT_AURORA_4 + 1;
constant u_GT_ETHERNET_1: primitives_type := u_GT_CUSTOM + 1;
constant u_GT_ETHERNET_2: primitives_type := u_GT_ETHERNET_1 + 1;
constant u_GT_ETHERNET_4: primitives_type := u_GT_ETHERNET_2 + 1;
constant u_GT_FIBRE_CHAN_1: primitives_type := u_GT_ETHERNET_4 + 1;
constant u_GT_FIBRE_CHAN_2: primitives_type := u_GT_FIBRE_CHAN_1 + 1;
constant u_GT_FIBRE_CHAN_4: primitives_type := u_GT_FIBRE_CHAN_2 + 1;
constant u_GT_INFINIBAND_1: primitives_type := u_GT_FIBRE_CHAN_4 + 1;
constant u_GT_INFINIBAND_2: primitives_type := u_GT_INFINIBAND_1 + 1;
constant u_GT_INFINIBAND_4: primitives_type := u_GT_INFINIBAND_2 + 1;
constant u_GTPA1_DUAL: primitives_type := u_GT_INFINIBAND_4 + 1;
constant u_GT_XAUI_1: primitives_type := u_GTPA1_DUAL + 1;
constant u_GT_XAUI_2: primitives_type := u_GT_XAUI_1 + 1;
constant u_GT_XAUI_4: primitives_type := u_GT_XAUI_2 + 1;
constant u_GTXE1: primitives_type := u_GT_XAUI_4 + 1;
constant u_IBUF: primitives_type := u_GTXE1 + 1;
constant u_IBUF_AGP: primitives_type := u_IBUF + 1;
constant u_IBUF_CTT: primitives_type := u_IBUF_AGP + 1;
constant u_IBUF_DLY_ADJ: primitives_type := u_IBUF_CTT + 1;
constant u_IBUFDS: primitives_type := u_IBUF_DLY_ADJ + 1;
constant u_IBUFDS_DIFF_OUT: primitives_type := u_IBUFDS + 1;
constant u_IBUFDS_DLY_ADJ: primitives_type := u_IBUFDS_DIFF_OUT + 1;
constant u_IBUFDS_GTXE1: primitives_type := u_IBUFDS_DLY_ADJ + 1;
constant u_IBUFG: primitives_type := u_IBUFDS_GTXE1 + 1;
constant u_IBUFG_AGP: primitives_type := u_IBUFG + 1;
constant u_IBUFG_CTT: primitives_type := u_IBUFG_AGP + 1;
constant u_IBUFGDS: primitives_type := u_IBUFG_CTT + 1;
constant u_IBUFGDS_DIFF_OUT: primitives_type := u_IBUFGDS + 1;
constant u_IBUFG_GTL: primitives_type := u_IBUFGDS_DIFF_OUT + 1;
constant u_IBUFG_GTLP: primitives_type := u_IBUFG_GTL + 1;
constant u_IBUFG_HSTL_I: primitives_type := u_IBUFG_GTLP + 1;
constant u_IBUFG_HSTL_III: primitives_type := u_IBUFG_HSTL_I + 1;
constant u_IBUFG_HSTL_IV: primitives_type := u_IBUFG_HSTL_III + 1;
constant u_IBUFG_LVCMOS18: primitives_type := u_IBUFG_HSTL_IV + 1;
constant u_IBUFG_LVCMOS2: primitives_type := u_IBUFG_LVCMOS18 + 1;
constant u_IBUFG_LVDS: primitives_type := u_IBUFG_LVCMOS2 + 1;
constant u_IBUFG_LVPECL: primitives_type := u_IBUFG_LVDS + 1;
constant u_IBUFG_PCI33_3: primitives_type := u_IBUFG_LVPECL + 1;
constant u_IBUFG_PCI33_5: primitives_type := u_IBUFG_PCI33_3 + 1;
constant u_IBUFG_PCI66_3: primitives_type := u_IBUFG_PCI33_5 + 1;
constant u_IBUFG_PCIX66_3: primitives_type := u_IBUFG_PCI66_3 + 1;
constant u_IBUFG_SSTL2_I: primitives_type := u_IBUFG_PCIX66_3 + 1;
constant u_IBUFG_SSTL2_II: primitives_type := u_IBUFG_SSTL2_I + 1;
constant u_IBUFG_SSTL3_I: primitives_type := u_IBUFG_SSTL2_II + 1;
constant u_IBUFG_SSTL3_II: primitives_type := u_IBUFG_SSTL3_I + 1;
constant u_IBUF_GTL: primitives_type := u_IBUFG_SSTL3_II + 1;
constant u_IBUF_GTLP: primitives_type := u_IBUF_GTL + 1;
constant u_IBUF_HSTL_I: primitives_type := u_IBUF_GTLP + 1;
constant u_IBUF_HSTL_III: primitives_type := u_IBUF_HSTL_I + 1;
constant u_IBUF_HSTL_IV: primitives_type := u_IBUF_HSTL_III + 1;
constant u_IBUF_LVCMOS18: primitives_type := u_IBUF_HSTL_IV + 1;
constant u_IBUF_LVCMOS2: primitives_type := u_IBUF_LVCMOS18 + 1;
constant u_IBUF_LVDS: primitives_type := u_IBUF_LVCMOS2 + 1;
constant u_IBUF_LVPECL: primitives_type := u_IBUF_LVDS + 1;
constant u_IBUF_PCI33_3: primitives_type := u_IBUF_LVPECL + 1;
constant u_IBUF_PCI33_5: primitives_type := u_IBUF_PCI33_3 + 1;
constant u_IBUF_PCI66_3: primitives_type := u_IBUF_PCI33_5 + 1;
constant u_IBUF_PCIX66_3: primitives_type := u_IBUF_PCI66_3 + 1;
constant u_IBUF_SSTL2_I: primitives_type := u_IBUF_PCIX66_3 + 1;
constant u_IBUF_SSTL2_II: primitives_type := u_IBUF_SSTL2_I + 1;
constant u_IBUF_SSTL3_I: primitives_type := u_IBUF_SSTL2_II + 1;
constant u_IBUF_SSTL3_II: primitives_type := u_IBUF_SSTL3_I + 1;
constant u_ICAP_SPARTAN3A: primitives_type := u_IBUF_SSTL3_II + 1;
constant u_ICAP_SPARTAN6: primitives_type := u_ICAP_SPARTAN3A + 1;
constant u_ICAP_VIRTEX2: primitives_type := u_ICAP_SPARTAN6 + 1;
constant u_ICAP_VIRTEX4: primitives_type := u_ICAP_VIRTEX2 + 1;
constant u_ICAP_VIRTEX5: primitives_type := u_ICAP_VIRTEX4 + 1;
constant u_ICAP_VIRTEX6: primitives_type := u_ICAP_VIRTEX5 + 1;
constant u_IDDR: primitives_type := u_ICAP_VIRTEX6 + 1;
constant u_IDDR2: primitives_type := u_IDDR + 1;
constant u_IDDR_2CLK: primitives_type := u_IDDR2 + 1;
constant u_IDELAY: primitives_type := u_IDDR_2CLK + 1;
constant u_IDELAYCTRL: primitives_type := u_IDELAY + 1;
constant u_IFDDRCPE: primitives_type := u_IDELAYCTRL + 1;
constant u_IFDDRRSE: primitives_type := u_IFDDRCPE + 1;
constant u_INV: primitives_type := u_IFDDRRSE + 1;
constant u_IOBUF: primitives_type := u_INV + 1;
constant u_IOBUF_AGP: primitives_type := u_IOBUF + 1;
constant u_IOBUF_CTT: primitives_type := u_IOBUF_AGP + 1;
constant u_IOBUFDS: primitives_type := u_IOBUF_CTT + 1;
constant u_IOBUFDS_DIFF_OUT: primitives_type := u_IOBUFDS + 1;
constant u_IOBUF_F_12: primitives_type := u_IOBUFDS_DIFF_OUT + 1;
constant u_IOBUF_F_16: primitives_type := u_IOBUF_F_12 + 1;
constant u_IOBUF_F_2: primitives_type := u_IOBUF_F_16 + 1;
constant u_IOBUF_F_24: primitives_type := u_IOBUF_F_2 + 1;
constant u_IOBUF_F_4: primitives_type := u_IOBUF_F_24 + 1;
constant u_IOBUF_F_6: primitives_type := u_IOBUF_F_4 + 1;
constant u_IOBUF_F_8: primitives_type := u_IOBUF_F_6 + 1;
constant u_IOBUF_GTL: primitives_type := u_IOBUF_F_8 + 1;
constant u_IOBUF_GTLP: primitives_type := u_IOBUF_GTL + 1;
constant u_IOBUF_HSTL_I: primitives_type := u_IOBUF_GTLP + 1;
constant u_IOBUF_HSTL_III: primitives_type := u_IOBUF_HSTL_I + 1;
constant u_IOBUF_HSTL_IV: primitives_type := u_IOBUF_HSTL_III + 1;
constant u_IOBUF_LVCMOS18: primitives_type := u_IOBUF_HSTL_IV + 1;
constant u_IOBUF_LVCMOS2: primitives_type := u_IOBUF_LVCMOS18 + 1;
constant u_IOBUF_LVDS: primitives_type := u_IOBUF_LVCMOS2 + 1;
constant u_IOBUF_LVPECL: primitives_type := u_IOBUF_LVDS + 1;
constant u_IOBUF_PCI33_3: primitives_type := u_IOBUF_LVPECL + 1;
constant u_IOBUF_PCI33_5: primitives_type := u_IOBUF_PCI33_3 + 1;
constant u_IOBUF_PCI66_3: primitives_type := u_IOBUF_PCI33_5 + 1;
constant u_IOBUF_PCIX66_3: primitives_type := u_IOBUF_PCI66_3 + 1;
constant u_IOBUF_S_12: primitives_type := u_IOBUF_PCIX66_3 + 1;
constant u_IOBUF_S_16: primitives_type := u_IOBUF_S_12 + 1;
constant u_IOBUF_S_2: primitives_type := u_IOBUF_S_16 + 1;
constant u_IOBUF_S_24: primitives_type := u_IOBUF_S_2 + 1;
constant u_IOBUF_S_4: primitives_type := u_IOBUF_S_24 + 1;
constant u_IOBUF_S_6: primitives_type := u_IOBUF_S_4 + 1;
constant u_IOBUF_S_8: primitives_type := u_IOBUF_S_6 + 1;
constant u_IOBUF_SSTL2_I: primitives_type := u_IOBUF_S_8 + 1;
constant u_IOBUF_SSTL2_II: primitives_type := u_IOBUF_SSTL2_I + 1;
constant u_IOBUF_SSTL3_I: primitives_type := u_IOBUF_SSTL2_II + 1;
constant u_IOBUF_SSTL3_II: primitives_type := u_IOBUF_SSTL3_I + 1;
constant u_IODELAY: primitives_type := u_IOBUF_SSTL3_II + 1;
constant u_IODELAY2: primitives_type := u_IODELAY + 1;
constant u_IODELAYE1: primitives_type := u_IODELAY2 + 1;
constant u_IODRP2: primitives_type := u_IODELAYE1 + 1;
constant u_IODRP2_MCB: primitives_type := u_IODRP2 + 1;
constant u_ISERDES: primitives_type := u_IODRP2_MCB + 1;
constant u_ISERDES2: primitives_type := u_ISERDES + 1;
constant u_ISERDESE1: primitives_type := u_ISERDES2 + 1;
constant u_ISERDES_NODELAY: primitives_type := u_ISERDESE1 + 1;
constant u_JTAGPPC: primitives_type := u_ISERDES_NODELAY + 1;
constant u_JTAG_SIM_SPARTAN6: primitives_type := u_JTAGPPC + 1;
constant u_JTAG_SIM_VIRTEX6: primitives_type := u_JTAG_SIM_SPARTAN6 + 1;
constant u_KEEPER: primitives_type := u_JTAG_SIM_VIRTEX6 + 1;
constant u_KEY_CLEAR: primitives_type := u_KEEPER + 1;
constant u_LD: primitives_type := u_KEY_CLEAR + 1;
constant u_LD_1: primitives_type := u_LD + 1;
constant u_LDC: primitives_type := u_LD_1 + 1;
constant u_LDC_1: primitives_type := u_LDC + 1;
constant u_LDCE: primitives_type := u_LDC_1 + 1;
constant u_LDCE_1: primitives_type := u_LDCE + 1;
constant u_LDCP: primitives_type := u_LDCE_1 + 1;
constant u_LDCP_1: primitives_type := u_LDCP + 1;
constant u_LDCPE: primitives_type := u_LDCP_1 + 1;
constant u_LDCPE_1: primitives_type := u_LDCPE + 1;
constant u_LDE: primitives_type := u_LDCPE_1 + 1;
constant u_LDE_1: primitives_type := u_LDE + 1;
constant u_LDP: primitives_type := u_LDE_1 + 1;
constant u_LDP_1: primitives_type := u_LDP + 1;
constant u_LDPE: primitives_type := u_LDP_1 + 1;
constant u_LDPE_1: primitives_type := u_LDPE + 1;
constant u_LUT1: primitives_type := u_LDPE_1 + 1;
constant u_LUT1_D: primitives_type := u_LUT1 + 1;
constant u_LUT1_L: primitives_type := u_LUT1_D + 1;
constant u_LUT2: primitives_type := u_LUT1_L + 1;
constant u_LUT2_D: primitives_type := u_LUT2 + 1;
constant u_LUT2_L: primitives_type := u_LUT2_D + 1;
constant u_LUT3: primitives_type := u_LUT2_L + 1;
constant u_LUT3_D: primitives_type := u_LUT3 + 1;
constant u_LUT3_L: primitives_type := u_LUT3_D + 1;
constant u_LUT4: primitives_type := u_LUT3_L + 1;
constant u_LUT4_D: primitives_type := u_LUT4 + 1;
constant u_LUT4_L: primitives_type := u_LUT4_D + 1;
constant u_LUT5: primitives_type := u_LUT4_L + 1;
constant u_LUT5_D: primitives_type := u_LUT5 + 1;
constant u_LUT5_L: primitives_type := u_LUT5_D + 1;
constant u_LUT6: primitives_type := u_LUT5_L + 1;
constant u_LUT6_D: primitives_type := u_LUT6 + 1;
constant u_LUT6_L: primitives_type := u_LUT6_D + 1;
constant u_MCB: primitives_type := u_LUT6_L + 1;
constant u_MMCM_ADV: primitives_type := u_MCB + 1;
constant u_MMCM_BASE: primitives_type := u_MMCM_ADV + 1;
constant u_MULT18X18: primitives_type := u_MMCM_BASE + 1;
constant u_MULT18X18S: primitives_type := u_MULT18X18 + 1;
constant u_MULT18X18SIO: primitives_type := u_MULT18X18S + 1;
constant u_MULT_AND: primitives_type := u_MULT18X18SIO + 1;
constant u_MUXCY: primitives_type := u_MULT_AND + 1;
constant u_MUXCY_D: primitives_type := u_MUXCY + 1;
constant u_MUXCY_L: primitives_type := u_MUXCY_D + 1;
constant u_MUXF5: primitives_type := u_MUXCY_L + 1;
constant u_MUXF5_D: primitives_type := u_MUXF5 + 1;
constant u_MUXF5_L: primitives_type := u_MUXF5_D + 1;
constant u_MUXF6: primitives_type := u_MUXF5_L + 1;
constant u_MUXF6_D: primitives_type := u_MUXF6 + 1;
constant u_MUXF6_L: primitives_type := u_MUXF6_D + 1;
constant u_MUXF7: primitives_type := u_MUXF6_L + 1;
constant u_MUXF7_D: primitives_type := u_MUXF7 + 1;
constant u_MUXF7_L: primitives_type := u_MUXF7_D + 1;
constant u_MUXF8: primitives_type := u_MUXF7_L + 1;
constant u_MUXF8_D: primitives_type := u_MUXF8 + 1;
constant u_MUXF8_L: primitives_type := u_MUXF8_D + 1;
constant u_NAND2: primitives_type := u_MUXF8_L + 1;
constant u_NAND3: primitives_type := u_NAND2 + 1;
constant u_NAND4: primitives_type := u_NAND3 + 1;
constant u_NOR2: primitives_type := u_NAND4 + 1;
constant u_NOR3: primitives_type := u_NOR2 + 1;
constant u_NOR4: primitives_type := u_NOR3 + 1;
constant u_OBUF: primitives_type := u_NOR4 + 1;
constant u_OBUF_AGP: primitives_type := u_OBUF + 1;
constant u_OBUF_CTT: primitives_type := u_OBUF_AGP + 1;
constant u_OBUFDS: primitives_type := u_OBUF_CTT + 1;
constant u_OBUF_F_12: primitives_type := u_OBUFDS + 1;
constant u_OBUF_F_16: primitives_type := u_OBUF_F_12 + 1;
constant u_OBUF_F_2: primitives_type := u_OBUF_F_16 + 1;
constant u_OBUF_F_24: primitives_type := u_OBUF_F_2 + 1;
constant u_OBUF_F_4: primitives_type := u_OBUF_F_24 + 1;
constant u_OBUF_F_6: primitives_type := u_OBUF_F_4 + 1;
constant u_OBUF_F_8: primitives_type := u_OBUF_F_6 + 1;
constant u_OBUF_GTL: primitives_type := u_OBUF_F_8 + 1;
constant u_OBUF_GTLP: primitives_type := u_OBUF_GTL + 1;
constant u_OBUF_HSTL_I: primitives_type := u_OBUF_GTLP + 1;
constant u_OBUF_HSTL_III: primitives_type := u_OBUF_HSTL_I + 1;
constant u_OBUF_HSTL_IV: primitives_type := u_OBUF_HSTL_III + 1;
constant u_OBUF_LVCMOS18: primitives_type := u_OBUF_HSTL_IV + 1;
constant u_OBUF_LVCMOS2: primitives_type := u_OBUF_LVCMOS18 + 1;
constant u_OBUF_LVDS: primitives_type := u_OBUF_LVCMOS2 + 1;
constant u_OBUF_LVPECL: primitives_type := u_OBUF_LVDS + 1;
constant u_OBUF_PCI33_3: primitives_type := u_OBUF_LVPECL + 1;
constant u_OBUF_PCI33_5: primitives_type := u_OBUF_PCI33_3 + 1;
constant u_OBUF_PCI66_3: primitives_type := u_OBUF_PCI33_5 + 1;
constant u_OBUF_PCIX66_3: primitives_type := u_OBUF_PCI66_3 + 1;
constant u_OBUF_S_12: primitives_type := u_OBUF_PCIX66_3 + 1;
constant u_OBUF_S_16: primitives_type := u_OBUF_S_12 + 1;
constant u_OBUF_S_2: primitives_type := u_OBUF_S_16 + 1;
constant u_OBUF_S_24: primitives_type := u_OBUF_S_2 + 1;
constant u_OBUF_S_4: primitives_type := u_OBUF_S_24 + 1;
constant u_OBUF_S_6: primitives_type := u_OBUF_S_4 + 1;
constant u_OBUF_S_8: primitives_type := u_OBUF_S_6 + 1;
constant u_OBUF_SSTL2_I: primitives_type := u_OBUF_S_8 + 1;
constant u_OBUF_SSTL2_II: primitives_type := u_OBUF_SSTL2_I + 1;
constant u_OBUF_SSTL3_I: primitives_type := u_OBUF_SSTL2_II + 1;
constant u_OBUF_SSTL3_II: primitives_type := u_OBUF_SSTL3_I + 1;
constant u_OBUFT: primitives_type := u_OBUF_SSTL3_II + 1;
constant u_OBUFT_AGP: primitives_type := u_OBUFT + 1;
constant u_OBUFT_CTT: primitives_type := u_OBUFT_AGP + 1;
constant u_OBUFTDS: primitives_type := u_OBUFT_CTT + 1;
constant u_OBUFT_F_12: primitives_type := u_OBUFTDS + 1;
constant u_OBUFT_F_16: primitives_type := u_OBUFT_F_12 + 1;
constant u_OBUFT_F_2: primitives_type := u_OBUFT_F_16 + 1;
constant u_OBUFT_F_24: primitives_type := u_OBUFT_F_2 + 1;
constant u_OBUFT_F_4: primitives_type := u_OBUFT_F_24 + 1;
constant u_OBUFT_F_6: primitives_type := u_OBUFT_F_4 + 1;
constant u_OBUFT_F_8: primitives_type := u_OBUFT_F_6 + 1;
constant u_OBUFT_GTL: primitives_type := u_OBUFT_F_8 + 1;
constant u_OBUFT_GTLP: primitives_type := u_OBUFT_GTL + 1;
constant u_OBUFT_HSTL_I: primitives_type := u_OBUFT_GTLP + 1;
constant u_OBUFT_HSTL_III: primitives_type := u_OBUFT_HSTL_I + 1;
constant u_OBUFT_HSTL_IV: primitives_type := u_OBUFT_HSTL_III + 1;
constant u_OBUFT_LVCMOS18: primitives_type := u_OBUFT_HSTL_IV + 1;
constant u_OBUFT_LVCMOS2: primitives_type := u_OBUFT_LVCMOS18 + 1;
constant u_OBUFT_LVDS: primitives_type := u_OBUFT_LVCMOS2 + 1;
constant u_OBUFT_LVPECL: primitives_type := u_OBUFT_LVDS + 1;
constant u_OBUFT_PCI33_3: primitives_type := u_OBUFT_LVPECL + 1;
constant u_OBUFT_PCI33_5: primitives_type := u_OBUFT_PCI33_3 + 1;
constant u_OBUFT_PCI66_3: primitives_type := u_OBUFT_PCI33_5 + 1;
constant u_OBUFT_PCIX66_3: primitives_type := u_OBUFT_PCI66_3 + 1;
constant u_OBUFT_S_12: primitives_type := u_OBUFT_PCIX66_3 + 1;
constant u_OBUFT_S_16: primitives_type := u_OBUFT_S_12 + 1;
constant u_OBUFT_S_2: primitives_type := u_OBUFT_S_16 + 1;
constant u_OBUFT_S_24: primitives_type := u_OBUFT_S_2 + 1;
constant u_OBUFT_S_4: primitives_type := u_OBUFT_S_24 + 1;
constant u_OBUFT_S_6: primitives_type := u_OBUFT_S_4 + 1;
constant u_OBUFT_S_8: primitives_type := u_OBUFT_S_6 + 1;
constant u_OBUFT_SSTL2_I: primitives_type := u_OBUFT_S_8 + 1;
constant u_OBUFT_SSTL2_II: primitives_type := u_OBUFT_SSTL2_I + 1;
constant u_OBUFT_SSTL3_I: primitives_type := u_OBUFT_SSTL2_II + 1;
constant u_OBUFT_SSTL3_II: primitives_type := u_OBUFT_SSTL3_I + 1;
constant u_OCT_CALIBRATE: primitives_type := u_OBUFT_SSTL3_II + 1;
constant u_ODDR: primitives_type := u_OCT_CALIBRATE + 1;
constant u_ODDR2: primitives_type := u_ODDR + 1;
constant u_OFDDRCPE: primitives_type := u_ODDR2 + 1;
constant u_OFDDRRSE: primitives_type := u_OFDDRCPE + 1;
constant u_OFDDRTCPE: primitives_type := u_OFDDRRSE + 1;
constant u_OFDDRTRSE: primitives_type := u_OFDDRTCPE + 1;
constant u_OR2: primitives_type := u_OFDDRTRSE + 1;
constant u_OR2L: primitives_type := u_OR2 + 1;
constant u_OR3: primitives_type := u_OR2L + 1;
constant u_OR4: primitives_type := u_OR3 + 1;
constant u_ORCY: primitives_type := u_OR4 + 1;
constant u_OSERDES: primitives_type := u_ORCY + 1;
constant u_OSERDES2: primitives_type := u_OSERDES + 1;
constant u_OSERDESE1: primitives_type := u_OSERDES2 + 1;
constant u_PCIE_2_0: primitives_type := u_OSERDESE1 + 1;
constant u_PCIE_A1: primitives_type := u_PCIE_2_0 + 1;
constant u_PLL_ADV: primitives_type := u_PCIE_A1 + 1;
constant u_PLL_BASE: primitives_type := u_PLL_ADV + 1;
constant u_PMCD: primitives_type := u_PLL_BASE + 1;
constant u_POST_CRC_INTERNAL: primitives_type := u_PMCD + 1;
constant u_PPC405: primitives_type := u_POST_CRC_INTERNAL + 1;
constant u_PPC405_ADV: primitives_type := u_PPC405 + 1;
constant u_PPR_FRAME: primitives_type := u_PPC405_ADV + 1;
constant u_PULLDOWN: primitives_type := u_PPR_FRAME + 1;
constant u_PULLUP: primitives_type := u_PULLDOWN + 1;
constant u_RAM128X1D: primitives_type := u_PULLUP + 1;
constant u_RAM128X1S: primitives_type := u_RAM128X1D + 1;
constant u_RAM128X1S_1: primitives_type := u_RAM128X1S + 1;
constant u_RAM16X1D: primitives_type := u_RAM128X1S_1 + 1;
constant u_RAM16X1D_1: primitives_type := u_RAM16X1D + 1;
constant u_RAM16X1S: primitives_type := u_RAM16X1D_1 + 1;
constant u_RAM16X1S_1: primitives_type := u_RAM16X1S + 1;
constant u_RAM16X2S: primitives_type := u_RAM16X1S_1 + 1;
constant u_RAM16X4S: primitives_type := u_RAM16X2S + 1;
constant u_RAM16X8S: primitives_type := u_RAM16X4S + 1;
constant u_RAM256X1S: primitives_type := u_RAM16X8S + 1;
constant u_RAM32M: primitives_type := u_RAM256X1S + 1;
constant u_RAM32X1D: primitives_type := u_RAM32M + 1;
constant u_RAM32X1D_1: primitives_type := u_RAM32X1D + 1;
constant u_RAM32X1S: primitives_type := u_RAM32X1D_1 + 1;
constant u_RAM32X1S_1: primitives_type := u_RAM32X1S + 1;
constant u_RAM32X2S: primitives_type := u_RAM32X1S_1 + 1;
constant u_RAM32X4S: primitives_type := u_RAM32X2S + 1;
constant u_RAM32X8S: primitives_type := u_RAM32X4S + 1;
constant u_RAM64M: primitives_type := u_RAM32X8S + 1;
constant u_RAM64X1D: primitives_type := u_RAM64M + 1;
constant u_RAM64X1D_1: primitives_type := u_RAM64X1D + 1;
constant u_RAM64X1S: primitives_type := u_RAM64X1D_1 + 1;
constant u_RAM64X1S_1: primitives_type := u_RAM64X1S + 1;
constant u_RAM64X2S: primitives_type := u_RAM64X1S_1 + 1;
constant u_RAMB16: primitives_type := u_RAM64X2S + 1;
constant u_RAMB16BWE: primitives_type := u_RAMB16 + 1;
constant u_RAMB16BWER: primitives_type := u_RAMB16BWE + 1;
constant u_RAMB16BWE_S18: primitives_type := u_RAMB16BWER + 1;
constant u_RAMB16BWE_S18_S18: primitives_type := u_RAMB16BWE_S18 + 1;
constant u_RAMB16BWE_S18_S9: primitives_type := u_RAMB16BWE_S18_S18 + 1;
constant u_RAMB16BWE_S36: primitives_type := u_RAMB16BWE_S18_S9 + 1;
constant u_RAMB16BWE_S36_S18: primitives_type := u_RAMB16BWE_S36 + 1;
constant u_RAMB16BWE_S36_S36: primitives_type := u_RAMB16BWE_S36_S18 + 1;
constant u_RAMB16BWE_S36_S9: primitives_type := u_RAMB16BWE_S36_S36 + 1;
constant u_RAMB16_S1: primitives_type := u_RAMB16BWE_S36_S9 + 1;
constant u_RAMB16_S18: primitives_type := u_RAMB16_S1 + 1;
constant u_RAMB16_S18_S18: primitives_type := u_RAMB16_S18 + 1;
constant u_RAMB16_S18_S36: primitives_type := u_RAMB16_S18_S18 + 1;
constant u_RAMB16_S1_S1: primitives_type := u_RAMB16_S18_S36 + 1;
constant u_RAMB16_S1_S18: primitives_type := u_RAMB16_S1_S1 + 1;
constant u_RAMB16_S1_S2: primitives_type := u_RAMB16_S1_S18 + 1;
constant u_RAMB16_S1_S36: primitives_type := u_RAMB16_S1_S2 + 1;
constant u_RAMB16_S1_S4: primitives_type := u_RAMB16_S1_S36 + 1;
constant u_RAMB16_S1_S9: primitives_type := u_RAMB16_S1_S4 + 1;
constant u_RAMB16_S2: primitives_type := u_RAMB16_S1_S9 + 1;
constant u_RAMB16_S2_S18: primitives_type := u_RAMB16_S2 + 1;
constant u_RAMB16_S2_S2: primitives_type := u_RAMB16_S2_S18 + 1;
constant u_RAMB16_S2_S36: primitives_type := u_RAMB16_S2_S2 + 1;
constant u_RAMB16_S2_S4: primitives_type := u_RAMB16_S2_S36 + 1;
constant u_RAMB16_S2_S9: primitives_type := u_RAMB16_S2_S4 + 1;
constant u_RAMB16_S36: primitives_type := u_RAMB16_S2_S9 + 1;
constant u_RAMB16_S36_S36: primitives_type := u_RAMB16_S36 + 1;
constant u_RAMB16_S4: primitives_type := u_RAMB16_S36_S36 + 1;
constant u_RAMB16_S4_S18: primitives_type := u_RAMB16_S4 + 1;
constant u_RAMB16_S4_S36: primitives_type := u_RAMB16_S4_S18 + 1;
constant u_RAMB16_S4_S4: primitives_type := u_RAMB16_S4_S36 + 1;
constant u_RAMB16_S4_S9: primitives_type := u_RAMB16_S4_S4 + 1;
constant u_RAMB16_S9: primitives_type := u_RAMB16_S4_S9 + 1;
constant u_RAMB16_S9_S18: primitives_type := u_RAMB16_S9 + 1;
constant u_RAMB16_S9_S36: primitives_type := u_RAMB16_S9_S18 + 1;
constant u_RAMB16_S9_S9: primitives_type := u_RAMB16_S9_S36 + 1;
constant u_RAMB18: primitives_type := u_RAMB16_S9_S9 + 1;
constant u_RAMB18E1: primitives_type := u_RAMB18 + 1;
constant u_RAMB18SDP: primitives_type := u_RAMB18E1 + 1;
constant u_RAMB32_S64_ECC: primitives_type := u_RAMB18SDP + 1;
constant u_RAMB36: primitives_type := u_RAMB32_S64_ECC + 1;
constant u_RAMB36E1: primitives_type := u_RAMB36 + 1;
constant u_RAMB36_EXP: primitives_type := u_RAMB36E1 + 1;
constant u_RAMB36SDP: primitives_type := u_RAMB36_EXP + 1;
constant u_RAMB36SDP_EXP: primitives_type := u_RAMB36SDP + 1;
constant u_RAMB4_S1: primitives_type := u_RAMB36SDP_EXP + 1;
constant u_RAMB4_S16: primitives_type := u_RAMB4_S1 + 1;
constant u_RAMB4_S16_S16: primitives_type := u_RAMB4_S16 + 1;
constant u_RAMB4_S1_S1: primitives_type := u_RAMB4_S16_S16 + 1;
constant u_RAMB4_S1_S16: primitives_type := u_RAMB4_S1_S1 + 1;
constant u_RAMB4_S1_S2: primitives_type := u_RAMB4_S1_S16 + 1;
constant u_RAMB4_S1_S4: primitives_type := u_RAMB4_S1_S2 + 1;
constant u_RAMB4_S1_S8: primitives_type := u_RAMB4_S1_S4 + 1;
constant u_RAMB4_S2: primitives_type := u_RAMB4_S1_S8 + 1;
constant u_RAMB4_S2_S16: primitives_type := u_RAMB4_S2 + 1;
constant u_RAMB4_S2_S2: primitives_type := u_RAMB4_S2_S16 + 1;
constant u_RAMB4_S2_S4: primitives_type := u_RAMB4_S2_S2 + 1;
constant u_RAMB4_S2_S8: primitives_type := u_RAMB4_S2_S4 + 1;
constant u_RAMB4_S4: primitives_type := u_RAMB4_S2_S8 + 1;
constant u_RAMB4_S4_S16: primitives_type := u_RAMB4_S4 + 1;
constant u_RAMB4_S4_S4: primitives_type := u_RAMB4_S4_S16 + 1;
constant u_RAMB4_S4_S8: primitives_type := u_RAMB4_S4_S4 + 1;
constant u_RAMB4_S8: primitives_type := u_RAMB4_S4_S8 + 1;
constant u_RAMB4_S8_S16: primitives_type := u_RAMB4_S8 + 1;
constant u_RAMB4_S8_S8: primitives_type := u_RAMB4_S8_S16 + 1;
constant u_RAMB8BWER: primitives_type := u_RAMB4_S8_S8 + 1;
constant u_ROM128X1: primitives_type := u_RAMB8BWER + 1;
constant u_ROM16X1: primitives_type := u_ROM128X1 + 1;
constant u_ROM256X1: primitives_type := u_ROM16X1 + 1;
constant u_ROM32X1: primitives_type := u_ROM256X1 + 1;
constant u_ROM64X1: primitives_type := u_ROM32X1 + 1;
constant u_SLAVE_SPI: primitives_type := u_ROM64X1 + 1;
constant u_SPI_ACCESS: primitives_type := u_SLAVE_SPI + 1;
constant u_SRL16: primitives_type := u_SPI_ACCESS + 1;
constant u_SRL16_1: primitives_type := u_SRL16 + 1;
constant u_SRL16E: primitives_type := u_SRL16_1 + 1;
constant u_SRL16E_1: primitives_type := u_SRL16E + 1;
constant u_SRLC16: primitives_type := u_SRL16E_1 + 1;
constant u_SRLC16_1: primitives_type := u_SRLC16 + 1;
constant u_SRLC16E: primitives_type := u_SRLC16_1 + 1;
constant u_SRLC16E_1: primitives_type := u_SRLC16E + 1;
constant u_SRLC32E: primitives_type := u_SRLC16E_1 + 1;
constant u_STARTBUF_SPARTAN2: primitives_type := u_SRLC32E + 1;
constant u_STARTBUF_SPARTAN3: primitives_type := u_STARTBUF_SPARTAN2 + 1;
constant u_STARTBUF_SPARTAN3E: primitives_type := u_STARTBUF_SPARTAN3 + 1;
constant u_STARTBUF_VIRTEX: primitives_type := u_STARTBUF_SPARTAN3E + 1;
constant u_STARTBUF_VIRTEX2: primitives_type := u_STARTBUF_VIRTEX + 1;
constant u_STARTBUF_VIRTEX4: primitives_type := u_STARTBUF_VIRTEX2 + 1;
constant u_STARTUP_SPARTAN2: primitives_type := u_STARTBUF_VIRTEX4 + 1;
constant u_STARTUP_SPARTAN3: primitives_type := u_STARTUP_SPARTAN2 + 1;
constant u_STARTUP_SPARTAN3A: primitives_type := u_STARTUP_SPARTAN3 + 1;
constant u_STARTUP_SPARTAN3E: primitives_type := u_STARTUP_SPARTAN3A + 1;
constant u_STARTUP_SPARTAN6: primitives_type := u_STARTUP_SPARTAN3E + 1;
constant u_STARTUP_VIRTEX: primitives_type := u_STARTUP_SPARTAN6 + 1;
constant u_STARTUP_VIRTEX2: primitives_type := u_STARTUP_VIRTEX + 1;
constant u_STARTUP_VIRTEX4: primitives_type := u_STARTUP_VIRTEX2 + 1;
constant u_STARTUP_VIRTEX5: primitives_type := u_STARTUP_VIRTEX4 + 1;
constant u_STARTUP_VIRTEX6: primitives_type := u_STARTUP_VIRTEX5 + 1;
constant u_SUSPEND_SYNC: primitives_type := u_STARTUP_VIRTEX6 + 1;
constant u_SYSMON: primitives_type := u_SUSPEND_SYNC + 1;
constant u_TEMAC_SINGLE: primitives_type := u_SYSMON + 1;
constant u_TOC: primitives_type := u_TEMAC_SINGLE + 1;
constant u_TOCBUF: primitives_type := u_TOC + 1;
constant u_USR_ACCESS_VIRTEX4: primitives_type := u_TOCBUF + 1;
constant u_USR_ACCESS_VIRTEX5: primitives_type := u_USR_ACCESS_VIRTEX4 + 1;
constant u_USR_ACCESS_VIRTEX6: primitives_type := u_USR_ACCESS_VIRTEX5 + 1;
constant u_VCC: primitives_type := u_USR_ACCESS_VIRTEX6 + 1;
constant u_XNOR2: primitives_type := u_VCC + 1;
constant u_XNOR3: primitives_type := u_XNOR2 + 1;
constant u_XNOR4: primitives_type := u_XNOR3 + 1;
constant u_XOR2: primitives_type := u_XNOR4 + 1;
constant u_XOR3: primitives_type := u_XOR2 + 1;
constant u_XOR4: primitives_type := u_XOR3 + 1;
constant u_XORCY: primitives_type := u_XOR4 + 1;
constant u_XORCY_D: primitives_type := u_XORCY + 1;
constant u_XORCY_L: primitives_type := u_XORCY_D + 1;
-- Primitives added for artix7, kintex6, virtex7, and zynq
constant u_AND2B1: primitives_type := u_XORCY_L + 1;
constant u_AND2B2: primitives_type := u_AND2B1 + 1;
constant u_AND3B1: primitives_type := u_AND2B2 + 1;
constant u_AND3B2: primitives_type := u_AND3B1 + 1;
constant u_AND3B3: primitives_type := u_AND3B2 + 1;
constant u_AND4B1: primitives_type := u_AND3B3 + 1;
constant u_AND4B2: primitives_type := u_AND4B1 + 1;
constant u_AND4B3: primitives_type := u_AND4B2 + 1;
constant u_AND4B4: primitives_type := u_AND4B3 + 1;
constant u_AND5: primitives_type := u_AND4B4 + 1;
constant u_AND5B1: primitives_type := u_AND5 + 1;
constant u_AND5B2: primitives_type := u_AND5B1 + 1;
constant u_AND5B3: primitives_type := u_AND5B2 + 1;
constant u_AND5B4: primitives_type := u_AND5B3 + 1;
constant u_AND5B5: primitives_type := u_AND5B4 + 1;
constant u_BSCANE2: primitives_type := u_AND5B5 + 1;
constant u_BUFMR: primitives_type := u_BSCANE2 + 1;
constant u_BUFMRCE: primitives_type := u_BUFMR + 1;
constant u_CAPTUREE2: primitives_type := u_BUFMRCE + 1;
constant u_CFG_IO_ACCESS: primitives_type := u_CAPTUREE2 + 1;
constant u_FRAME_ECCE2: primitives_type := u_CFG_IO_ACCESS + 1;
constant u_GTXE2_CHANNEL: primitives_type := u_FRAME_ECCE2 + 1;
constant u_GTXE2_COMMON: primitives_type := u_GTXE2_CHANNEL + 1;
constant u_IBUF_DCIEN: primitives_type := u_GTXE2_COMMON + 1;
constant u_IBUFDS_BLVDS_25: primitives_type := u_IBUF_DCIEN + 1;
constant u_IBUFDS_DCIEN: primitives_type := u_IBUFDS_BLVDS_25 + 1;
constant u_IBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IBUFDS_DCIEN + 1;
constant u_IBUFDS_GTE2: primitives_type := u_IBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IBUFDS_LVDS_25: primitives_type := u_IBUFDS_GTE2 + 1;
constant u_IBUFGDS_BLVDS_25: primitives_type := u_IBUFDS_LVDS_25 + 1;
constant u_IBUFGDS_LVDS_25: primitives_type := u_IBUFGDS_BLVDS_25 + 1;
constant u_IBUFG_HSTL_I_18: primitives_type := u_IBUFGDS_LVDS_25 + 1;
constant u_IBUFG_HSTL_I_DCI: primitives_type := u_IBUFG_HSTL_I_18 + 1;
constant u_IBUFG_HSTL_I_DCI_18: primitives_type := u_IBUFG_HSTL_I_DCI + 1;
constant u_IBUFG_HSTL_II: primitives_type := u_IBUFG_HSTL_I_DCI_18 + 1;
constant u_IBUFG_HSTL_II_18: primitives_type := u_IBUFG_HSTL_II + 1;
constant u_IBUFG_HSTL_II_DCI: primitives_type := u_IBUFG_HSTL_II_18 + 1;
constant u_IBUFG_HSTL_II_DCI_18: primitives_type := u_IBUFG_HSTL_II_DCI + 1;
constant u_IBUFG_HSTL_III_18: primitives_type := u_IBUFG_HSTL_II_DCI_18 + 1;
constant u_IBUFG_HSTL_III_DCI: primitives_type := u_IBUFG_HSTL_III_18 + 1;
constant u_IBUFG_HSTL_III_DCI_18: primitives_type := u_IBUFG_HSTL_III_DCI + 1;
constant u_IBUFG_LVCMOS12: primitives_type := u_IBUFG_HSTL_III_DCI_18 + 1;
constant u_IBUFG_LVCMOS15: primitives_type := u_IBUFG_LVCMOS12 + 1;
constant u_IBUFG_LVCMOS25: primitives_type := u_IBUFG_LVCMOS15 + 1;
constant u_IBUFG_LVCMOS33: primitives_type := u_IBUFG_LVCMOS25 + 1;
constant u_IBUFG_LVDCI_15: primitives_type := u_IBUFG_LVCMOS33 + 1;
constant u_IBUFG_LVDCI_18: primitives_type := u_IBUFG_LVDCI_15 + 1;
constant u_IBUFG_LVDCI_DV2_15: primitives_type := u_IBUFG_LVDCI_18 + 1;
constant u_IBUFG_LVDCI_DV2_18: primitives_type := u_IBUFG_LVDCI_DV2_15 + 1;
constant u_IBUFG_LVTTL: primitives_type := u_IBUFG_LVDCI_DV2_18 + 1;
constant u_IBUFG_SSTL18_I: primitives_type := u_IBUFG_LVTTL + 1;
constant u_IBUFG_SSTL18_I_DCI: primitives_type := u_IBUFG_SSTL18_I + 1;
constant u_IBUFG_SSTL18_II: primitives_type := u_IBUFG_SSTL18_I_DCI + 1;
constant u_IBUFG_SSTL18_II_DCI: primitives_type := u_IBUFG_SSTL18_II + 1;
constant u_IBUF_HSTL_I_18: primitives_type := u_IBUFG_SSTL18_II_DCI + 1;
constant u_IBUF_HSTL_I_DCI: primitives_type := u_IBUF_HSTL_I_18 + 1;
constant u_IBUF_HSTL_I_DCI_18: primitives_type := u_IBUF_HSTL_I_DCI + 1;
constant u_IBUF_HSTL_II: primitives_type := u_IBUF_HSTL_I_DCI_18 + 1;
constant u_IBUF_HSTL_II_18: primitives_type := u_IBUF_HSTL_II + 1;
constant u_IBUF_HSTL_II_DCI: primitives_type := u_IBUF_HSTL_II_18 + 1;
constant u_IBUF_HSTL_II_DCI_18: primitives_type := u_IBUF_HSTL_II_DCI + 1;
constant u_IBUF_HSTL_III_18: primitives_type := u_IBUF_HSTL_II_DCI_18 + 1;
constant u_IBUF_HSTL_III_DCI: primitives_type := u_IBUF_HSTL_III_18 + 1;
constant u_IBUF_HSTL_III_DCI_18: primitives_type := u_IBUF_HSTL_III_DCI + 1;
constant u_IBUF_LVCMOS12: primitives_type := u_IBUF_HSTL_III_DCI_18 + 1;
constant u_IBUF_LVCMOS15: primitives_type := u_IBUF_LVCMOS12 + 1;
constant u_IBUF_LVCMOS25: primitives_type := u_IBUF_LVCMOS15 + 1;
constant u_IBUF_LVCMOS33: primitives_type := u_IBUF_LVCMOS25 + 1;
constant u_IBUF_LVDCI_15: primitives_type := u_IBUF_LVCMOS33 + 1;
constant u_IBUF_LVDCI_18: primitives_type := u_IBUF_LVDCI_15 + 1;
constant u_IBUF_LVDCI_DV2_15: primitives_type := u_IBUF_LVDCI_18 + 1;
constant u_IBUF_LVDCI_DV2_18: primitives_type := u_IBUF_LVDCI_DV2_15 + 1;
constant u_IBUF_LVTTL: primitives_type := u_IBUF_LVDCI_DV2_18 + 1;
constant u_IBUF_SSTL18_I: primitives_type := u_IBUF_LVTTL + 1;
constant u_IBUF_SSTL18_I_DCI: primitives_type := u_IBUF_SSTL18_I + 1;
constant u_IBUF_SSTL18_II: primitives_type := u_IBUF_SSTL18_I_DCI + 1;
constant u_IBUF_SSTL18_II_DCI: primitives_type := u_IBUF_SSTL18_II + 1;
constant u_ICAPE2: primitives_type := u_IBUF_SSTL18_II_DCI + 1;
constant u_IDELAYE2: primitives_type := u_ICAPE2 + 1;
constant u_IN_FIFO: primitives_type := u_IDELAYE2 + 1;
constant u_IOBUFDS_BLVDS_25: primitives_type := u_IN_FIFO + 1;
constant u_IOBUFDS_DIFF_OUT_DCIEN: primitives_type := u_IOBUFDS_BLVDS_25 + 1;
constant u_IOBUF_HSTL_I_18: primitives_type := u_IOBUFDS_DIFF_OUT_DCIEN + 1;
constant u_IOBUF_HSTL_II: primitives_type := u_IOBUF_HSTL_I_18 + 1;
constant u_IOBUF_HSTL_II_18: primitives_type := u_IOBUF_HSTL_II + 1;
constant u_IOBUF_HSTL_II_DCI: primitives_type := u_IOBUF_HSTL_II_18 + 1;
constant u_IOBUF_HSTL_II_DCI_18: primitives_type := u_IOBUF_HSTL_II_DCI + 1;
constant u_IOBUF_HSTL_III_18: primitives_type := u_IOBUF_HSTL_II_DCI_18 + 1;
constant u_IOBUF_LVCMOS12: primitives_type := u_IOBUF_HSTL_III_18 + 1;
constant u_IOBUF_LVCMOS15: primitives_type := u_IOBUF_LVCMOS12 + 1;
constant u_IOBUF_LVCMOS25: primitives_type := u_IOBUF_LVCMOS15 + 1;
constant u_IOBUF_LVCMOS33: primitives_type := u_IOBUF_LVCMOS25 + 1;
constant u_IOBUF_LVDCI_15: primitives_type := u_IOBUF_LVCMOS33 + 1;
constant u_IOBUF_LVDCI_18: primitives_type := u_IOBUF_LVDCI_15 + 1;
constant u_IOBUF_LVDCI_DV2_15: primitives_type := u_IOBUF_LVDCI_18 + 1;
constant u_IOBUF_LVDCI_DV2_18: primitives_type := u_IOBUF_LVDCI_DV2_15 + 1;
constant u_IOBUF_LVTTL: primitives_type := u_IOBUF_LVDCI_DV2_18 + 1;
constant u_IOBUF_SSTL18_I: primitives_type := u_IOBUF_LVTTL + 1;
constant u_IOBUF_SSTL18_II: primitives_type := u_IOBUF_SSTL18_I + 1;
constant u_IOBUF_SSTL18_II_DCI: primitives_type := u_IOBUF_SSTL18_II + 1;
constant u_ISERDESE2: primitives_type := u_IOBUF_SSTL18_II_DCI + 1;
constant u_JTAG_SIME2: primitives_type := u_ISERDESE2 + 1;
constant u_LUT6_2: primitives_type := u_JTAG_SIME2 + 1;
constant u_MMCME2_ADV: primitives_type := u_LUT6_2 + 1;
constant u_MMCME2_BASE: primitives_type := u_MMCME2_ADV + 1;
constant u_NAND2B1: primitives_type := u_MMCME2_BASE + 1;
constant u_NAND2B2: primitives_type := u_NAND2B1 + 1;
constant u_NAND3B1: primitives_type := u_NAND2B2 + 1;
constant u_NAND3B2: primitives_type := u_NAND3B1 + 1;
constant u_NAND3B3: primitives_type := u_NAND3B2 + 1;
constant u_NAND4B1: primitives_type := u_NAND3B3 + 1;
constant u_NAND4B2: primitives_type := u_NAND4B1 + 1;
constant u_NAND4B3: primitives_type := u_NAND4B2 + 1;
constant u_NAND4B4: primitives_type := u_NAND4B3 + 1;
constant u_NAND5: primitives_type := u_NAND4B4 + 1;
constant u_NAND5B1: primitives_type := u_NAND5 + 1;
constant u_NAND5B2: primitives_type := u_NAND5B1 + 1;
constant u_NAND5B3: primitives_type := u_NAND5B2 + 1;
constant u_NAND5B4: primitives_type := u_NAND5B3 + 1;
constant u_NAND5B5: primitives_type := u_NAND5B4 + 1;
constant u_NOR2B1: primitives_type := u_NAND5B5 + 1;
constant u_NOR2B2: primitives_type := u_NOR2B1 + 1;
constant u_NOR3B1: primitives_type := u_NOR2B2 + 1;
constant u_NOR3B2: primitives_type := u_NOR3B1 + 1;
constant u_NOR3B3: primitives_type := u_NOR3B2 + 1;
constant u_NOR4B1: primitives_type := u_NOR3B3 + 1;
constant u_NOR4B2: primitives_type := u_NOR4B1 + 1;
constant u_NOR4B3: primitives_type := u_NOR4B2 + 1;
constant u_NOR4B4: primitives_type := u_NOR4B3 + 1;
constant u_NOR5: primitives_type := u_NOR4B4 + 1;
constant u_NOR5B1: primitives_type := u_NOR5 + 1;
constant u_NOR5B2: primitives_type := u_NOR5B1 + 1;
constant u_NOR5B3: primitives_type := u_NOR5B2 + 1;
constant u_NOR5B4: primitives_type := u_NOR5B3 + 1;
constant u_NOR5B5: primitives_type := u_NOR5B4 + 1;
constant u_OBUFDS_BLVDS_25: primitives_type := u_NOR5B5 + 1;
constant u_OBUFDS_DUAL_BUF: primitives_type := u_OBUFDS_BLVDS_25 + 1;
constant u_OBUFDS_LVDS_25: primitives_type := u_OBUFDS_DUAL_BUF + 1;
constant u_OBUF_HSTL_I_18: primitives_type := u_OBUFDS_LVDS_25 + 1;
constant u_OBUF_HSTL_I_DCI: primitives_type := u_OBUF_HSTL_I_18 + 1;
constant u_OBUF_HSTL_I_DCI_18: primitives_type := u_OBUF_HSTL_I_DCI + 1;
constant u_OBUF_HSTL_II: primitives_type := u_OBUF_HSTL_I_DCI_18 + 1;
constant u_OBUF_HSTL_II_18: primitives_type := u_OBUF_HSTL_II + 1;
constant u_OBUF_HSTL_II_DCI: primitives_type := u_OBUF_HSTL_II_18 + 1;
constant u_OBUF_HSTL_II_DCI_18: primitives_type := u_OBUF_HSTL_II_DCI + 1;
constant u_OBUF_HSTL_III_18: primitives_type := u_OBUF_HSTL_II_DCI_18 + 1;
constant u_OBUF_HSTL_III_DCI: primitives_type := u_OBUF_HSTL_III_18 + 1;
constant u_OBUF_HSTL_III_DCI_18: primitives_type := u_OBUF_HSTL_III_DCI + 1;
constant u_OBUF_LVCMOS12: primitives_type := u_OBUF_HSTL_III_DCI_18 + 1;
constant u_OBUF_LVCMOS15: primitives_type := u_OBUF_LVCMOS12 + 1;
constant u_OBUF_LVCMOS25: primitives_type := u_OBUF_LVCMOS15 + 1;
constant u_OBUF_LVCMOS33: primitives_type := u_OBUF_LVCMOS25 + 1;
constant u_OBUF_LVDCI_15: primitives_type := u_OBUF_LVCMOS33 + 1;
constant u_OBUF_LVDCI_18: primitives_type := u_OBUF_LVDCI_15 + 1;
constant u_OBUF_LVDCI_DV2_15: primitives_type := u_OBUF_LVDCI_18 + 1;
constant u_OBUF_LVDCI_DV2_18: primitives_type := u_OBUF_LVDCI_DV2_15 + 1;
constant u_OBUF_LVTTL: primitives_type := u_OBUF_LVDCI_DV2_18 + 1;
constant u_OBUF_SSTL18_I: primitives_type := u_OBUF_LVTTL + 1;
constant u_OBUF_SSTL18_I_DCI: primitives_type := u_OBUF_SSTL18_I + 1;
constant u_OBUF_SSTL18_II: primitives_type := u_OBUF_SSTL18_I_DCI + 1;
constant u_OBUF_SSTL18_II_DCI: primitives_type := u_OBUF_SSTL18_II + 1;
constant u_OBUFT_DCIEN: primitives_type := u_OBUF_SSTL18_II_DCI + 1;
constant u_OBUFTDS_BLVDS_25: primitives_type := u_OBUFT_DCIEN + 1;
constant u_OBUFTDS_DCIEN: primitives_type := u_OBUFTDS_BLVDS_25 + 1;
constant u_OBUFTDS_DCIEN_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN + 1;
constant u_OBUFTDS_DUAL_BUF: primitives_type := u_OBUFTDS_DCIEN_DUAL_BUF + 1;
constant u_OBUFTDS_LVDS_25: primitives_type := u_OBUFTDS_DUAL_BUF + 1;
constant u_OBUFT_HSTL_I_18: primitives_type := u_OBUFTDS_LVDS_25 + 1;
constant u_OBUFT_HSTL_I_DCI: primitives_type := u_OBUFT_HSTL_I_18 + 1;
constant u_OBUFT_HSTL_I_DCI_18: primitives_type := u_OBUFT_HSTL_I_DCI + 1;
constant u_OBUFT_HSTL_II: primitives_type := u_OBUFT_HSTL_I_DCI_18 + 1;
constant u_OBUFT_HSTL_II_18: primitives_type := u_OBUFT_HSTL_II + 1;
constant u_OBUFT_HSTL_II_DCI: primitives_type := u_OBUFT_HSTL_II_18 + 1;
constant u_OBUFT_HSTL_II_DCI_18: primitives_type := u_OBUFT_HSTL_II_DCI + 1;
constant u_OBUFT_HSTL_III_18: primitives_type := u_OBUFT_HSTL_II_DCI_18 + 1;
constant u_OBUFT_HSTL_III_DCI: primitives_type := u_OBUFT_HSTL_III_18 + 1;
constant u_OBUFT_HSTL_III_DCI_18: primitives_type := u_OBUFT_HSTL_III_DCI + 1;
constant u_OBUFT_LVCMOS12: primitives_type := u_OBUFT_HSTL_III_DCI_18 + 1;
constant u_OBUFT_LVCMOS15: primitives_type := u_OBUFT_LVCMOS12 + 1;
constant u_OBUFT_LVCMOS25: primitives_type := u_OBUFT_LVCMOS15 + 1;
constant u_OBUFT_LVCMOS33: primitives_type := u_OBUFT_LVCMOS25 + 1;
constant u_OBUFT_LVDCI_15: primitives_type := u_OBUFT_LVCMOS33 + 1;
constant u_OBUFT_LVDCI_18: primitives_type := u_OBUFT_LVDCI_15 + 1;
constant u_OBUFT_LVDCI_DV2_15: primitives_type := u_OBUFT_LVDCI_18 + 1;
constant u_OBUFT_LVDCI_DV2_18: primitives_type := u_OBUFT_LVDCI_DV2_15 + 1;
constant u_OBUFT_LVTTL: primitives_type := u_OBUFT_LVDCI_DV2_18 + 1;
constant u_OBUFT_SSTL18_I: primitives_type := u_OBUFT_LVTTL + 1;
constant u_OBUFT_SSTL18_I_DCI: primitives_type := u_OBUFT_SSTL18_I + 1;
constant u_OBUFT_SSTL18_II: primitives_type := u_OBUFT_SSTL18_I_DCI + 1;
constant u_OBUFT_SSTL18_II_DCI: primitives_type := u_OBUFT_SSTL18_II + 1;
constant u_ODELAYE2: primitives_type := u_OBUFT_SSTL18_II_DCI + 1;
constant u_OR2B1: primitives_type := u_ODELAYE2 + 1;
constant u_OR2B2: primitives_type := u_OR2B1 + 1;
constant u_OR3B1: primitives_type := u_OR2B2 + 1;
constant u_OR3B2: primitives_type := u_OR3B1 + 1;
constant u_OR3B3: primitives_type := u_OR3B2 + 1;
constant u_OR4B1: primitives_type := u_OR3B3 + 1;
constant u_OR4B2: primitives_type := u_OR4B1 + 1;
constant u_OR4B3: primitives_type := u_OR4B2 + 1;
constant u_OR4B4: primitives_type := u_OR4B3 + 1;
constant u_OR5: primitives_type := u_OR4B4 + 1;
constant u_OR5B1: primitives_type := u_OR5 + 1;
constant u_OR5B2: primitives_type := u_OR5B1 + 1;
constant u_OR5B3: primitives_type := u_OR5B2 + 1;
constant u_OR5B4: primitives_type := u_OR5B3 + 1;
constant u_OR5B5: primitives_type := u_OR5B4 + 1;
constant u_OSERDESE2: primitives_type := u_OR5B5 + 1;
constant u_OUT_FIFO: primitives_type := u_OSERDESE2 + 1;
constant u_PCIE_2_1: primitives_type := u_OUT_FIFO + 1;
constant u_PHASER_IN: primitives_type := u_PCIE_2_1 + 1;
constant u_PHASER_IN_PHY: primitives_type := u_PHASER_IN + 1;
constant u_PHASER_OUT: primitives_type := u_PHASER_IN_PHY + 1;
constant u_PHASER_OUT_PHY: primitives_type := u_PHASER_OUT + 1;
constant u_PHASER_REF: primitives_type := u_PHASER_OUT_PHY + 1;
constant u_PHY_CONTROL: primitives_type := u_PHASER_REF + 1;
constant u_PLLE2_ADV: primitives_type := u_PHY_CONTROL + 1;
constant u_PLLE2_BASE: primitives_type := u_PLLE2_ADV + 1;
constant u_PSS: primitives_type := u_PLLE2_BASE + 1;
constant u_RAMD32: primitives_type := u_PSS + 1;
constant u_RAMD64E: primitives_type := u_RAMD32 + 1;
constant u_RAMS32: primitives_type := u_RAMD64E + 1;
constant u_RAMS64E: primitives_type := u_RAMS32 + 1;
constant u_SIM_CONFIGE2: primitives_type := u_RAMS64E + 1;
constant u_STARTUPE2: primitives_type := u_SIM_CONFIGE2 + 1;
constant u_USR_ACCESSE2: primitives_type := u_STARTUPE2 + 1;
constant u_XADC: primitives_type := u_USR_ACCESSE2 + 1;
constant u_XNOR5: primitives_type := u_XADC + 1;
constant u_XOR5: primitives_type := u_XNOR5 + 1;
constant u_ZHOLD_DELAY: primitives_type := u_XOR5 + 1;
type primitive_array_type is array (natural range <>) of primitives_type;
----------------------------------------------------------------------------
-- Returns true if primitive is available in family.
--
-- Examples:
--
-- supported(virtex2, u_RAMB16_S2) returns true because the RAMB16_S2
-- primitive is available in the
-- virtex2 family.
--
-- supported(spartan3, u_RAM4B_S4) returns false because the RAMB4_S4
-- primitive is not available in the
-- spartan3 family.
----------------------------------------------------------------------------
function supported( family : families_type;
primitive : primitives_type
) return boolean;
----------------------------------------------------------------------------
-- This is an overload of function 'supported' (see above). It allows a list
-- of primitives to be tested.
--
-- Returns true if all of primitives in the list are available in family.
--
-- Example: supported(spartan3, (u_MUXCY, u_XORCY, u_FD))
-- is
-- equivalent to: supported(spartan3, u_MUXCY) and
-- supported(spartan3, u_XORCY) and
-- supported(spartan3, u_FD);
----------------------------------------------------------------------------
function supported( family : families_type;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Below, are overloads of function 'supported' that allow the family
-- parameter to be passed as a string. These correspond to the above two
-- functions otherwise.
----------------------------------------------------------------------------
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type;
function fam2str( fam : families_type ) return string;
----------------------------------------------------------------------------
-- Function: native_lut_size
--
-- Returns the largest LUT size available in FPGA family, fam.
-- If no LUT is available in fam, then returns zero by default, unless
-- the call specifies a no_lut_return_val, in which case this value
-- is returned.
--
-- The function is available in two overload versions, one for each
-- way of passing the fam argument.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type. This is used for derivative part
-- aliasing to the root family.
----------------------------------------------------------------------------
function get_root_family( family_in : string ) return string;
end package system_xadc_wiz_0_0_family_support;
package body system_xadc_wiz_0_0_family_support is
type prim_status_type is (
n -- no
, y -- yes
, u -- unknown, not used. However, we use
-- an enumeration to allow for
-- possible future enhancement.
);
type fam_prim_status is array (primitives_type) of prim_status_type;
type fam_has_prim_type is array (families_type) of fam_prim_status;
-- Performance workaround (XST procedure and function handling).
-- The fam_has_prim constant is initialized by an aggregate rather than by the
-- following function. A version of this file with this function not
-- commented was employed in building the aggregate. So, what is below still
-- defines the family-primitive matirix.
--# ----------------------------------------------------------------------------
--# -- This function is used to populate the matrix of family/primitive values.
--# ----------------------------------------------------------------------------
--# ---(
--# function prim_population return fam_has_prim_type is
--# variable pp : fam_has_prim_type := (others => (others => n));
--#
--# procedure set_to( stat : prim_status_type
--# ; fam : families_type
--# ; prim_list : primitive_array_type
--# ) is
--# begin
--# for i in prim_list'range loop
--# pp(fam)(prim_list(i)) := stat;
--# end loop;
--# end set_to;
--#
--# begin
--# set_to(y, virtex, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI33_5
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS2
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI33_5
--# , u_IBUF_PCI66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI33_5
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI33_5
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS2
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI33_5
--# , u_OBUF_PCI66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, spartan2e, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_SPARTAN2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_IBUFG_AGP
--# , u_IBUFG_CTT
--# , u_IBUFG_GTL
--# , u_IBUFG_GTLP
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_IV
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS2
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL2_I
--# , u_IBUFG_SSTL2_II
--# , u_IBUFG_SSTL3_I
--# , u_IBUFG_SSTL3_II
--# , u_IBUF_AGP
--# , u_IBUF_CTT
--# , u_IBUF_GTL
--# , u_IBUF_GTLP
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_IV
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS2
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL2_I
--# , u_IBUF_SSTL2_II
--# , u_IBUF_SSTL3_I
--# , u_IBUF_SSTL3_II
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF_AGP
--# , u_IOBUF_CTT
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_GTL
--# , u_IOBUF_GTLP
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_IV
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS2
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_SSTL2_I
--# , u_IOBUF_SSTL2_II
--# , u_IOBUF_SSTL3_I
--# , u_IOBUF_SSTL3_II
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OBUFT_AGP
--# , u_OBUFT_CTT
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_GTL
--# , u_OBUFT_GTLP
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_IV
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS2
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_SSTL2_I
--# , u_OBUFT_SSTL2_II
--# , u_OBUFT_SSTL3_I
--# , u_OBUFT_SSTL3_II
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUF_AGP
--# , u_OBUF_CTT
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_GTL
--# , u_OBUF_GTLP
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_IV
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS2
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_SSTL2_I
--# , u_OBUF_SSTL2_II
--# , u_OBUF_SSTL3_I
--# , u_OBUF_SSTL3_II
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_SPARTAN2
--# , u_STARTUP_SPARTAN2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# set_to(y, virtexe, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGDLL
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFG
--# , u_INV
--# , u_IOBUF
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFT
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAMB4_S1
--# , u_RAMB4_S16
--# , u_RAMB4_S16_S16
--# , u_RAMB4_S1_S1
--# , u_RAMB4_S1_S16
--# , u_RAMB4_S1_S2
--# , u_RAMB4_S1_S4
--# , u_RAMB4_S1_S8
--# , u_RAMB4_S2
--# , u_RAMB4_S2_S16
--# , u_RAMB4_S2_S2
--# , u_RAMB4_S2_S4
--# , u_RAMB4_S2_S8
--# , u_RAMB4_S4
--# , u_RAMB4_S4_S16
--# , u_RAMB4_S4_S4
--# , u_RAMB4_S4_S8
--# , u_RAMB4_S8
--# , u_RAMB4_S8_S16
--# , u_RAMB4_S8_S8
--# , u_ROM16X1
--# , u_ROM32X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_STARTBUF_VIRTEX
--# , u_STARTUP_VIRTEX
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, virtex2, (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(qvirtex2) := pp(virtex2);
--# --
--# pp(qrvirtex2) := pp(virtex2);
--# --
--# set_to(y, virtex2p,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFE
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFT
--# , u_CAPTURE_VIRTEX2
--# , u_CLKDLL
--# , u_CLKDLLE
--# , u_CLKDLLHF
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_GT10_10GE_4
--# , u_GT10_10GE_8
--# , u_GT10_10GFC_4
--# , u_GT10_10GFC_8
--# , u_GT10_AURORAX_4
--# , u_GT10_AURORAX_8
--# , u_GT10_AURORA_1
--# , u_GT10_AURORA_2
--# , u_GT10_AURORA_4
--# , u_GT10_CUSTOM
--# , u_GT10_INFINIBAND_1
--# , u_GT10_INFINIBAND_2
--# , u_GT10_INFINIBAND_4
--# , u_GT10_OC192_4
--# , u_GT10_OC192_8
--# , u_GT10_OC48_1
--# , u_GT10_OC48_2
--# , u_GT10_OC48_4
--# , u_GT10_PCI_EXPRESS_1
--# , u_GT10_PCI_EXPRESS_2
--# , u_GT10_PCI_EXPRESS_4
--# , u_GT10_XAUI_1
--# , u_GT10_XAUI_2
--# , u_GT10_XAUI_4
--# , u_GT_AURORA_1
--# , u_GT_AURORA_2
--# , u_GT_AURORA_4
--# , u_GT_CUSTOM
--# , u_GT_ETHERNET_1
--# , u_GT_ETHERNET_2
--# , u_GT_ETHERNET_4
--# , u_GT_FIBRE_CHAN_1
--# , u_GT_FIBRE_CHAN_2
--# , u_GT_FIBRE_CHAN_4
--# , u_GT_INFINIBAND_1
--# , u_GT_INFINIBAND_2
--# , u_GT_INFINIBAND_4
--# , u_GT_XAUI_1
--# , u_GT_XAUI_2
--# , u_GT_XAUI_4
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PPC405
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX2
--# , u_STARTUP_VIRTEX2
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# set_to(y, spartan3,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3
--# , u_STARTUP_SPARTAN3
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3) := pp(spartan3);
--# --
--# set_to(y, spartan3e,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_SPARTAN3
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_CAPTURE_SPARTAN3E
--# , u_DCM
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FMAP
--# , u_GND
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(aspartan3e) := pp(spartan3e);
--# --
--# set_to(y, virtex4fx,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX4
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_VIRTEX4
--# , u_BUFGP
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX4
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX4
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX4
--# , u_IDDR
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_ISERDES
--# , u_JTAGPPC
--# , u_KEEPER
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PMCD
--# , u_PPC405
--# , u_PPC405_ADV
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB32_S64_ECC
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_STARTBUF_VIRTEX4
--# , u_STARTUP_VIRTEX4
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX4
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(virtex4sx) := pp(virtex4fx);
--# --
--# pp(virtex4lx) := pp(virtex4fx);
--# set_to(n, virtex4lx, (u_EMAC,
--# u_GT11CLK, u_GT11CLK_MGT, u_GT11_CUSTOM,
--# u_JTAGPPC, u_PPC405, u_PPC405_ADV
--# ) );
--# --
--# pp(virtex4) := pp(virtex4lx); -- virtex4 is defined as the largest set
--# -- of primitives that EVERY virtex4
--# -- device supports, i.e.. a design that uses
--# -- the virtex4 subset of primitives
--# -- is compatible with any variant of
--# -- the virtex4 family.
--# --
--# pp(qvirtex4) := pp(virtex4);
--# --
--# pp(qrvirtex4) := pp(virtex4);
--# --
--# set_to(y, virtex5,
--# (
--# u_AND2
--# , u_AND3
--# , u_AND4
--# , u_BSCAN_VIRTEX5
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFIO
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_EMAC
--# , u_FD
--# , u_FDC
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDCP_1
--# , u_FDC_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDP_1
--# , u_FDR
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDRS_1
--# , u_FDR_1
--# , u_FDS
--# , u_FDSE
--# , u_FDSE_1
--# , u_FDS_1
--# , u_FD_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY
--# , u_ISERDES
--# , u_ISERDES_NODELAY
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LDC
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDCP_1
--# , u_LDC_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDPE
--# , u_LDPE_1
--# , u_LDP_1
--# , u_LD_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_RAMB36_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRL16_1
--# , u_SRLC16
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC16_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_SYSMON
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# )
--# );
--# --
--# pp(spartan3a) := pp(spartan3e); -- Populate spartan3a by taking
--# -- differences from spartan3e.
--# set_to(n, spartan3a, (
--# u_BSCAN_SPARTAN3
--# , u_CAPTURE_SPARTAN3E
--# , u_DUMMY_INV
--# , u_DUMMY_NOR2
--# , u_STARTBUF_SPARTAN3E
--# , u_STARTUP_SPARTAN3E
--# ) );
--# set_to(y, spartan3a, (
--# u_BSCAN_SPARTAN3A
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS_DLY_ADJ
--# , u_ICAP_SPARTAN3A
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_SPI_ACCESS
--# , u_STARTUP_SPARTAN3A
--# ) );
--#
--# --
--# pp(aspartan3a) := pp(spartan3a);
--# --
--# pp(spartan3an) := pp(spartan3a);
--# --
--# pp(spartan3adsp) := pp(spartan3a);
--# set_to(y, spartan3adsp, (
--# u_DSP48A
--# , u_RAMB16BWER
--# ) );
--# --
--# pp(aspartan3adsp) := pp(spartan3adsp);
--# --
--# set_to(y, spartan6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_SPARTAN6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGDLL
--# , u_BUFGMUX
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFIO2
--# , u_BUFIO2_2CLK
--# , u_BUFIO2FB
--# , u_BUFIO2FB_2CLK
--# , u_BUFPLL
--# , u_BUFPLL_MCB
--# , u_CAPTURE_SPARTAN3A
--# , u_DCM
--# , u_DCM_CLKGEN
--# , u_DCM_PS
--# , u_DNA_PORT
--# , u_DSP48A1
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FMAP
--# , u_GND
--# , u_GTPA1_DUAL
--# , u_IBUF
--# , u_IBUF_DLY_ADJ
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DLY_ADJ
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_SPARTAN3A
--# , u_ICAP_SPARTAN6
--# , u_IDDR2
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IODELAY2
--# , u_IODRP2
--# , u_IODRP2_MCB
--# , u_ISERDES2
--# , u_JTAG_SIM_SPARTAN6
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MCB
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT18X18SIO
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_OCT_CALIBRATE
--# , u_ODDR2
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_ORCY
--# , u_OSERDES2
--# , u_PCIE_A1
--# , u_PLL_ADV
--# , u_POST_CRC_INTERNAL
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAMB16BWE
--# , u_RAMB16BWE_S18
--# , u_RAMB16BWE_S18_S18
--# , u_RAMB16BWE_S18_S9
--# , u_RAMB16BWE_S36
--# , u_RAMB16BWE_S36_S18
--# , u_RAMB16BWE_S36_S36
--# , u_RAMB16BWE_S36_S9
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB8BWER
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SLAVE_SPI
--# , u_SPI_ACCESS
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_SPARTAN3A
--# , u_STARTUP_SPARTAN6
--# , u_SUSPEND_SYNC
--# , u_TOC
--# , u_TOCBUF
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# --
--# set_to(y, virtex6, (
--# u_AND2
--# , u_AND2B1L
--# , u_AND3
--# , u_AND4
--# , u_AUTOBUF
--# , u_BSCAN_VIRTEX6
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGMUX_CTRL
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFIODQS
--# , u_BUFR
--# , u_CAPTURE_VIRTEX5
--# , u_CAPTURE_VIRTEX6
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_CRC32
--# , u_CRC64
--# , u_DCIRESET
--# , u_DCIRESET
--# , u_DCM
--# , u_DCM_ADV
--# , u_DCM_BASE
--# , u_DCM_PS
--# , u_DSP48
--# , u_DSP48E
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_EMAC
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDDRCPE
--# , u_FDDRRSE
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO16
--# , u_FIFO18
--# , u_FIFO18_36
--# , u_FIFO18E1
--# , u_FIFO36
--# , u_FIFO36_72
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECC_VIRTEX5
--# , u_FRAME_ECC_VIRTEX6
--# , u_GND
--# , u_GT11CLK
--# , u_GT11CLK_MGT
--# , u_GT11_CUSTOM
--# , u_GTXE1
--# , u_IBUF
--# , u_IBUF
--# , u_IBUFDS
--# , u_IBUFDS
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_GTXE1
--# , u_IBUFG
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_ICAP_VIRTEX5
--# , u_ICAP_VIRTEX6
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IFDDRCPE
--# , u_IFDDRRSE
--# , u_INV
--# , u_IOBUF
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDES
--# , u_ISERDESE1
--# , u_ISERDES_NODELAY
--# , u_JTAG_SIM_VIRTEX6
--# , u_KEEPER
--# , u_KEY_CLEAR
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCM_ADV
--# , u_MMCM_BASE
--# , u_MULT18X18
--# , u_MULT18X18S
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND3
--# , u_NAND4
--# , u_NOR2
--# , u_NOR3
--# , u_NOR4
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFT
--# , u_OBUFTDS
--# , u_ODDR
--# , u_OFDDRCPE
--# , u_OFDDRRSE
--# , u_OFDDRTCPE
--# , u_OFDDRTRSE
--# , u_OR2
--# , u_OR2L
--# , u_OR3
--# , u_OR4
--# , u_OSERDES
--# , u_OSERDESE1
--# , u_PCIE_2_0
--# , u_PLL_ADV
--# , u_PLL_BASE
--# , u_PMCD
--# , u_PPR_FRAME
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16
--# , u_RAMB16_S1
--# , u_RAMB16_S18
--# , u_RAMB16_S18_S18
--# , u_RAMB16_S18_S36
--# , u_RAMB16_S1_S1
--# , u_RAMB16_S1_S18
--# , u_RAMB16_S1_S2
--# , u_RAMB16_S1_S36
--# , u_RAMB16_S1_S4
--# , u_RAMB16_S1_S9
--# , u_RAMB16_S2
--# , u_RAMB16_S2_S18
--# , u_RAMB16_S2_S2
--# , u_RAMB16_S2_S36
--# , u_RAMB16_S2_S4
--# , u_RAMB16_S2_S9
--# , u_RAMB16_S36
--# , u_RAMB16_S36_S36
--# , u_RAMB16_S4
--# , u_RAMB16_S4_S18
--# , u_RAMB16_S4_S36
--# , u_RAMB16_S4_S4
--# , u_RAMB16_S4_S9
--# , u_RAMB16_S9
--# , u_RAMB16_S9_S18
--# , u_RAMB16_S9_S36
--# , u_RAMB16_S9_S9
--# , u_RAMB18
--# , u_RAMB18E1
--# , u_RAMB18SDP
--# , u_RAMB32_S64_ECC
--# , u_RAMB36
--# , u_RAMB36E1
--# , u_RAMB36_EXP
--# , u_RAMB36SDP
--# , u_RAMB36SDP_EXP
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUP_VIRTEX5
--# , u_STARTUP_VIRTEX6
--# , u_SYSMON
--# , u_SYSMON
--# , u_TEMAC_SINGLE
--# , u_TOC
--# , u_TOCBUF
--# , u_USR_ACCESS_VIRTEX5
--# , u_USR_ACCESS_VIRTEX6
--# , u_VCC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# ) );
--# --
--# pp(spartan6l) := pp(spartan6);
--# --
--# pp(qspartan6) := pp(spartan6);
--# --
--# pp(aspartan6) := pp(spartan6);
--# --
--# pp(virtex6l) := pp(virtex6);
--# --
--# pp(qspartan6l) := pp(spartan6);
--# --
--# pp(qvirtex5) := pp(virtex5);
--# --
--# pp(qvirtex6) := pp(virtex6);
--# --
--# pp(qrvirtex5) := pp(virtex5);
--# --
--# pp(virtex5tx) := pp(virtex5);
--# --
--# pp(virtex5fx) := pp(virtex5);
--# --
--# pp(virtex6cx) := pp(virtex6);
--# --
--# set_to(y, kintex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, virtex7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFG_IO_ACCESS
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_GTXE2_CHANNEL
--# , u_GTXE2_COMMON
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_BLVDS_25
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFDS_LVDS_25
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_BLVDS_25
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFGDS_LVDS_25
--# , u_IBUFG_HSTL_I
--# , u_IBUFG_HSTL_I_18
--# , u_IBUFG_HSTL_I_DCI
--# , u_IBUFG_HSTL_I_DCI_18
--# , u_IBUFG_HSTL_II
--# , u_IBUFG_HSTL_II_18
--# , u_IBUFG_HSTL_II_DCI
--# , u_IBUFG_HSTL_II_DCI_18
--# , u_IBUFG_HSTL_III
--# , u_IBUFG_HSTL_III_18
--# , u_IBUFG_HSTL_III_DCI
--# , u_IBUFG_HSTL_III_DCI_18
--# , u_IBUFG_LVCMOS12
--# , u_IBUFG_LVCMOS15
--# , u_IBUFG_LVCMOS18
--# , u_IBUFG_LVCMOS25
--# , u_IBUFG_LVCMOS33
--# , u_IBUFG_LVDCI_15
--# , u_IBUFG_LVDCI_18
--# , u_IBUFG_LVDCI_DV2_15
--# , u_IBUFG_LVDCI_DV2_18
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_LVTTL
--# , u_IBUFG_PCI33_3
--# , u_IBUFG_PCI66_3
--# , u_IBUFG_PCIX66_3
--# , u_IBUFG_SSTL18_I
--# , u_IBUFG_SSTL18_I_DCI
--# , u_IBUFG_SSTL18_II
--# , u_IBUFG_SSTL18_II_DCI
--# , u_IBUF_HSTL_I
--# , u_IBUF_HSTL_I_18
--# , u_IBUF_HSTL_I_DCI
--# , u_IBUF_HSTL_I_DCI_18
--# , u_IBUF_HSTL_II
--# , u_IBUF_HSTL_II_18
--# , u_IBUF_HSTL_II_DCI
--# , u_IBUF_HSTL_II_DCI_18
--# , u_IBUF_HSTL_III
--# , u_IBUF_HSTL_III_18
--# , u_IBUF_HSTL_III_DCI
--# , u_IBUF_HSTL_III_DCI_18
--# , u_IBUF_LVCMOS12
--# , u_IBUF_LVCMOS15
--# , u_IBUF_LVCMOS18
--# , u_IBUF_LVCMOS25
--# , u_IBUF_LVCMOS33
--# , u_IBUF_LVDCI_15
--# , u_IBUF_LVDCI_18
--# , u_IBUF_LVDCI_DV2_15
--# , u_IBUF_LVDCI_DV2_18
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_LVTTL
--# , u_IBUF_PCI33_3
--# , u_IBUF_PCI66_3
--# , u_IBUF_PCIX66_3
--# , u_IBUF_SSTL18_I
--# , u_IBUF_SSTL18_I_DCI
--# , u_IBUF_SSTL18_II
--# , u_IBUF_SSTL18_II_DCI
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_BLVDS_25
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_HSTL_I
--# , u_IOBUF_HSTL_I_18
--# , u_IOBUF_HSTL_II
--# , u_IOBUF_HSTL_II_18
--# , u_IOBUF_HSTL_II_DCI
--# , u_IOBUF_HSTL_II_DCI_18
--# , u_IOBUF_HSTL_III
--# , u_IOBUF_HSTL_III_18
--# , u_IOBUF_LVCMOS12
--# , u_IOBUF_LVCMOS15
--# , u_IOBUF_LVCMOS18
--# , u_IOBUF_LVCMOS25
--# , u_IOBUF_LVCMOS33
--# , u_IOBUF_LVDCI_15
--# , u_IOBUF_LVDCI_18
--# , u_IOBUF_LVDCI_DV2_15
--# , u_IOBUF_LVDCI_DV2_18
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_LVTTL
--# , u_IOBUF_PCI33_3
--# , u_IOBUF_PCI66_3
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IOBUF_SSTL18_I
--# , u_IOBUF_SSTL18_II
--# , u_IOBUF_SSTL18_II_DCI
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_BLVDS_25
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUFDS_LVDS_25
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_HSTL_I
--# , u_OBUF_HSTL_I_18
--# , u_OBUF_HSTL_I_DCI
--# , u_OBUF_HSTL_I_DCI_18
--# , u_OBUF_HSTL_II
--# , u_OBUF_HSTL_II_18
--# , u_OBUF_HSTL_II_DCI
--# , u_OBUF_HSTL_II_DCI_18
--# , u_OBUF_HSTL_III
--# , u_OBUF_HSTL_III_18
--# , u_OBUF_HSTL_III_DCI
--# , u_OBUF_HSTL_III_DCI_18
--# , u_OBUF_LVCMOS12
--# , u_OBUF_LVCMOS15
--# , u_OBUF_LVCMOS18
--# , u_OBUF_LVCMOS25
--# , u_OBUF_LVCMOS33
--# , u_OBUF_LVDCI_15
--# , u_OBUF_LVDCI_18
--# , u_OBUF_LVDCI_DV2_15
--# , u_OBUF_LVDCI_DV2_18
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_LVTTL
--# , u_OBUF_PCI33_3
--# , u_OBUF_PCI66_3
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUF_SSTL18_I
--# , u_OBUF_SSTL18_I_DCI
--# , u_OBUF_SSTL18_II
--# , u_OBUF_SSTL18_II_DCI
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_BLVDS_25
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFTDS_LVDS_25
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_HSTL_I
--# , u_OBUFT_HSTL_I_18
--# , u_OBUFT_HSTL_I_DCI
--# , u_OBUFT_HSTL_I_DCI_18
--# , u_OBUFT_HSTL_II
--# , u_OBUFT_HSTL_II_18
--# , u_OBUFT_HSTL_II_DCI
--# , u_OBUFT_HSTL_II_DCI_18
--# , u_OBUFT_HSTL_III
--# , u_OBUFT_HSTL_III_18
--# , u_OBUFT_HSTL_III_DCI
--# , u_OBUFT_HSTL_III_DCI_18
--# , u_OBUFT_LVCMOS12
--# , u_OBUFT_LVCMOS15
--# , u_OBUFT_LVCMOS18
--# , u_OBUFT_LVCMOS25
--# , u_OBUFT_LVCMOS33
--# , u_OBUFT_LVDCI_15
--# , u_OBUFT_LVDCI_18
--# , u_OBUFT_LVDCI_DV2_15
--# , u_OBUFT_LVDCI_DV2_18
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_LVTTL
--# , u_OBUFT_PCI33_3
--# , u_OBUFT_PCI66_3
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_OBUFT_SSTL18_I
--# , u_OBUFT_SSTL18_I_DCI
--# , u_OBUFT_SSTL18_II
--# , u_OBUFT_SSTL18_II_DCI
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB36E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# set_to(y, artix7, (
--# u_AND2
--# , u_AND2B1
--# , u_AND2B1L
--# , u_AND2B2
--# , u_AND3
--# , u_AND3B1
--# , u_AND3B2
--# , u_AND3B3
--# , u_AND4
--# , u_AND4B1
--# , u_AND4B2
--# , u_AND4B3
--# , u_AND4B4
--# , u_AND5
--# , u_AND5B1
--# , u_AND5B2
--# , u_AND5B3
--# , u_AND5B4
--# , u_AND5B5
--# , u_AUTOBUF
--# , u_BSCANE2
--# , u_BUF
--# , u_BUFCF
--# , u_BUFG
--# , u_BUFGCE
--# , u_BUFGCE_1
--# , u_BUFGCTRL
--# , u_BUFGMUX
--# , u_BUFGMUX_1
--# , u_BUFGP
--# , u_BUFH
--# , u_BUFHCE
--# , u_BUFIO
--# , u_BUFMR
--# , u_BUFMRCE
--# , u_BUFR
--# , u_BUFT
--# , u_CAPTUREE2
--# , u_CARRY4
--# , u_CFGLUT5
--# , u_DCIRESET
--# , u_DNA_PORT
--# , u_DSP48E1
--# , u_EFUSE_USR
--# , u_FD
--# , u_FD_1
--# , u_FDC
--# , u_FDC_1
--# , u_FDCE
--# , u_FDCE_1
--# , u_FDCP
--# , u_FDCP_1
--# , u_FDCPE
--# , u_FDCPE_1
--# , u_FDE
--# , u_FDE_1
--# , u_FDP
--# , u_FDP_1
--# , u_FDPE
--# , u_FDPE_1
--# , u_FDR
--# , u_FDR_1
--# , u_FDRE
--# , u_FDRE_1
--# , u_FDRS
--# , u_FDRS_1
--# , u_FDRSE
--# , u_FDRSE_1
--# , u_FDS
--# , u_FDS_1
--# , u_FDSE
--# , u_FDSE_1
--# , u_FIFO18E1
--# , u_FIFO36E1
--# , u_FMAP
--# , u_FRAME_ECCE2
--# , u_GND
--# , u_IBUF
--# , u_IBUF_DCIEN
--# , u_IBUFDS
--# , u_IBUFDS_DCIEN
--# , u_IBUFDS_DIFF_OUT
--# , u_IBUFDS_DIFF_OUT_DCIEN
--# , u_IBUFDS_GTE2
--# , u_IBUFG
--# , u_IBUFGDS
--# , u_IBUFGDS_DIFF_OUT
--# , u_IBUFG_LVDS
--# , u_IBUFG_LVPECL
--# , u_IBUFG_PCIX66_3
--# , u_IBUF_LVDS
--# , u_IBUF_LVPECL
--# , u_IBUF_PCIX66_3
--# , u_ICAPE2
--# , u_IDDR
--# , u_IDDR_2CLK
--# , u_IDELAY
--# , u_IDELAYCTRL
--# , u_IDELAYE2
--# , u_IN_FIFO
--# , u_INV
--# , u_IOBUF
--# , u_IOBUFDS
--# , u_IOBUFDS_DIFF_OUT
--# , u_IOBUFDS_DIFF_OUT_DCIEN
--# , u_IOBUF_F_12
--# , u_IOBUF_F_16
--# , u_IOBUF_F_2
--# , u_IOBUF_F_24
--# , u_IOBUF_F_4
--# , u_IOBUF_F_6
--# , u_IOBUF_F_8
--# , u_IOBUF_LVDS
--# , u_IOBUF_LVPECL
--# , u_IOBUF_PCIX66_3
--# , u_IOBUF_S_12
--# , u_IOBUF_S_16
--# , u_IOBUF_S_2
--# , u_IOBUF_S_24
--# , u_IOBUF_S_4
--# , u_IOBUF_S_6
--# , u_IOBUF_S_8
--# , u_IODELAY
--# , u_IODELAYE1
--# , u_ISERDESE2
--# , u_JTAG_SIME2
--# , u_KEEPER
--# , u_LD
--# , u_LD_1
--# , u_LDC
--# , u_LDC_1
--# , u_LDCE
--# , u_LDCE_1
--# , u_LDCP
--# , u_LDCP_1
--# , u_LDCPE
--# , u_LDCPE_1
--# , u_LDE
--# , u_LDE_1
--# , u_LDP
--# , u_LDP_1
--# , u_LDPE
--# , u_LDPE_1
--# , u_LUT1
--# , u_LUT1_D
--# , u_LUT1_L
--# , u_LUT2
--# , u_LUT2_D
--# , u_LUT2_L
--# , u_LUT3
--# , u_LUT3_D
--# , u_LUT3_L
--# , u_LUT4
--# , u_LUT4_D
--# , u_LUT4_L
--# , u_LUT5
--# , u_LUT5_D
--# , u_LUT5_L
--# , u_LUT6
--# , u_LUT6_2
--# , u_LUT6_D
--# , u_LUT6_L
--# , u_MMCME2_ADV
--# , u_MMCME2_BASE
--# , u_MULT_AND
--# , u_MUXCY
--# , u_MUXCY_D
--# , u_MUXCY_L
--# , u_MUXF5
--# , u_MUXF5_D
--# , u_MUXF5_L
--# , u_MUXF6
--# , u_MUXF6_D
--# , u_MUXF6_L
--# , u_MUXF7
--# , u_MUXF7_D
--# , u_MUXF7_L
--# , u_MUXF8
--# , u_MUXF8_D
--# , u_MUXF8_L
--# , u_NAND2
--# , u_NAND2B1
--# , u_NAND2B2
--# , u_NAND3
--# , u_NAND3B1
--# , u_NAND3B2
--# , u_NAND3B3
--# , u_NAND4
--# , u_NAND4B1
--# , u_NAND4B2
--# , u_NAND4B3
--# , u_NAND4B4
--# , u_NAND5
--# , u_NAND5B1
--# , u_NAND5B2
--# , u_NAND5B3
--# , u_NAND5B4
--# , u_NAND5B5
--# , u_NOR2
--# , u_NOR2B1
--# , u_NOR2B2
--# , u_NOR3
--# , u_NOR3B1
--# , u_NOR3B2
--# , u_NOR3B3
--# , u_NOR4
--# , u_NOR4B1
--# , u_NOR4B2
--# , u_NOR4B3
--# , u_NOR4B4
--# , u_NOR5
--# , u_NOR5B1
--# , u_NOR5B2
--# , u_NOR5B3
--# , u_NOR5B4
--# , u_NOR5B5
--# , u_OBUF
--# , u_OBUFDS
--# , u_OBUFDS_DUAL_BUF
--# , u_OBUF_F_12
--# , u_OBUF_F_16
--# , u_OBUF_F_2
--# , u_OBUF_F_24
--# , u_OBUF_F_4
--# , u_OBUF_F_6
--# , u_OBUF_F_8
--# , u_OBUF_LVDS
--# , u_OBUF_LVPECL
--# , u_OBUF_PCIX66_3
--# , u_OBUF_S_12
--# , u_OBUF_S_16
--# , u_OBUF_S_2
--# , u_OBUF_S_24
--# , u_OBUF_S_4
--# , u_OBUF_S_6
--# , u_OBUF_S_8
--# , u_OBUFT
--# , u_OBUFT_DCIEN
--# , u_OBUFTDS
--# , u_OBUFTDS_DCIEN
--# , u_OBUFTDS_DCIEN_DUAL_BUF
--# , u_OBUFTDS_DUAL_BUF
--# , u_OBUFT_F_12
--# , u_OBUFT_F_16
--# , u_OBUFT_F_2
--# , u_OBUFT_F_24
--# , u_OBUFT_F_4
--# , u_OBUFT_F_6
--# , u_OBUFT_F_8
--# , u_OBUFT_LVDS
--# , u_OBUFT_LVPECL
--# , u_OBUFT_PCIX66_3
--# , u_OBUFT_S_12
--# , u_OBUFT_S_16
--# , u_OBUFT_S_2
--# , u_OBUFT_S_24
--# , u_OBUFT_S_4
--# , u_OBUFT_S_6
--# , u_OBUFT_S_8
--# , u_ODDR
--# , u_ODELAYE2
--# , u_OR2
--# , u_OR2B1
--# , u_OR2B2
--# , u_OR2L
--# , u_OR3
--# , u_OR3B1
--# , u_OR3B2
--# , u_OR3B3
--# , u_OR4
--# , u_OR4B1
--# , u_OR4B2
--# , u_OR4B3
--# , u_OR4B4
--# , u_OR5
--# , u_OR5B1
--# , u_OR5B2
--# , u_OR5B3
--# , u_OR5B4
--# , u_OR5B5
--# , u_OSERDESE2
--# , u_OUT_FIFO
--# , u_PCIE_2_1
--# , u_PHASER_IN
--# , u_PHASER_IN_PHY
--# , u_PHASER_OUT
--# , u_PHASER_OUT_PHY
--# , u_PHASER_REF
--# , u_PHY_CONTROL
--# , u_PLLE2_ADV
--# , u_PLLE2_BASE
--# , u_PSS
--# , u_PULLDOWN
--# , u_PULLUP
--# , u_RAM128X1D
--# , u_RAM128X1S
--# , u_RAM128X1S_1
--# , u_RAM16X1D
--# , u_RAM16X1D_1
--# , u_RAM16X1S
--# , u_RAM16X1S_1
--# , u_RAM16X2S
--# , u_RAM16X4S
--# , u_RAM16X8S
--# , u_RAM256X1S
--# , u_RAM32M
--# , u_RAM32X1D
--# , u_RAM32X1D_1
--# , u_RAM32X1S
--# , u_RAM32X1S_1
--# , u_RAM32X2S
--# , u_RAM32X4S
--# , u_RAM32X8S
--# , u_RAM64M
--# , u_RAM64X1D
--# , u_RAM64X1D_1
--# , u_RAM64X1S
--# , u_RAM64X1S_1
--# , u_RAM64X2S
--# , u_RAMB16_S4_S36
--# , u_RAMB18E1
--# , u_RAMB36E1
--# , u_RAMD32
--# , u_RAMD64E
--# , u_RAMS32
--# , u_RAMS64E
--# , u_ROM128X1
--# , u_ROM16X1
--# , u_ROM256X1
--# , u_ROM32X1
--# , u_ROM64X1
--# , u_SIM_CONFIGE2
--# , u_SRL16
--# , u_SRL16_1
--# , u_SRL16E
--# , u_SRL16E_1
--# , u_SRLC16
--# , u_SRLC16_1
--# , u_SRLC16E
--# , u_SRLC16E_1
--# , u_SRLC32E
--# , u_STARTUPE2
--# , u_USR_ACCESSE2
--# , u_VCC
--# , u_XADC
--# , u_XNOR2
--# , u_XNOR3
--# , u_XNOR4
--# , u_XNOR5
--# , u_XOR2
--# , u_XOR3
--# , u_XOR4
--# , u_XOR5
--# , u_XORCY
--# , u_XORCY_D
--# , u_XORCY_L
--# , u_ZHOLD_DELAY
--# ) );
--# --
--# return pp;
--# end prim_population;
--# ---)
--#
--#constant fam_has_prim : fam_has_prim_type := prim_population;
constant fam_has_prim : fam_has_prim_type :=
(
nofamily => (
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2 => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan2e => (
y, n, y, y, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtexe => (
y, n, y, y, n, n, n, n, n, n, y, n, n, n, n, y, y, y, y, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex2 => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex2p => (
y, n, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3 => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4lx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4fx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex4sx => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, y, y, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3an => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3e => (
y, n, y, y, n, n, y, n, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3a => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan3adsp => (
y, n, y, y, n, n, n, y, n, n, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, y, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex4 => (
y, n, y, y, n, n, n, n, n, n, n, n, y, n, n, y, y, n, y, y, y, y, n, y, y, n, y, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, n, y, y, y, y, n, y, n, y, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, y, y, n, n, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, y, n, y, y, n, y, n, n, n, n, n, n, y, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, n, n, n, n, y, y, y, y, y, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
spartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
aspartan6 => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex6l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qspartan6l => (
y, y, y, y, y, n, n, n, n, y, n, n, n, n, n, y, y, n, y, y, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, n, y, y, n, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, y, y, n, n, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, y, y, y, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, n, n, n, y, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, y, n, n, y, n, n, n, y, y, n, n, n, y, y, y, y, y, y, n, n, n, n, n, y, y, y, n, n, n, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, y, n, y, n, n, n, n, n, y, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qvirtex6 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, n, y, y, y, n, y, y, y, y, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, y, y, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, y, n, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, y, y, y, y, y, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, n, y, n, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, n, y, n, y, y, n, y, y, y, n, n, n, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
qrvirtex5 => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5tx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
virtex5fx => (
y, n, y, y, n, n, n, n, n, n, n, n, n, y, n, y, y, n, y, y, y, y, n, y, y, y, n, y, n, n, y, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, n, y, n, y, y, n, n, n, y, y, y, y, y, y, n, y, n, y, n, n, y, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, n, y, n, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, n, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, n, y, y, n, y, n, n, n, n, y, y, y, n, n, n, n, y, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, n, y, y, y, y, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, y, n, y, y, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n,
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virtex6cx => (
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n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n),
kintex7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
kintex7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qkintex7 => (
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y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qkintex7l => (
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artix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
aartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
artix7l => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qartix7 => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n,
n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
zynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
azynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y),
qzynq => (
y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, y, y, n, y, y, y, y, n, y, y, n, n, y, y, y, y, n, n, n, n, n, n, n, y, y, n, n, n, n, n, n, n, n, n, y, y, n, n, n, n, n, y, n, n, n, n, n, y, n, n, n, n, y, n, n, y, n, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, y, n, n, y, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, y, y, n, n, y, n, n, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, y, y, n, y, n, y, y, y, n, y, y, n, n, n, n, n, n, n, n, n, n, y, n, y, y, y, n, n, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, y, n, n, n, n, n, n, n, n, n, y, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, y, n, n, y, y, y, y, y, y, y, y, n, n, y, y, n, y, n, y, y, y, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, y, n, n, n, n, n, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, n, n, n, n, n, n, n, y, n, n, n, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, n, n, y, y, y, y, y, y, y, y, y, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, n, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y,
y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y, y)
);
function supported( family : families_type;
primitive : primitives_type
) return boolean is
begin
return fam_has_prim(family)(primitive) = y;
end supported;
function supported( family : families_type;
primitives : primitive_array_type
) return boolean is
begin
for i in primitives'range loop
if fam_has_prim(family)(primitives(i)) /= y then
return false;
end if;
end loop;
return true;
end supported;
----------------------------------------------------------------------------
-- This function is used as alternative to the 'IMAGE attribute, which
-- is not correctly interpretted by some vhdl tools.
----------------------------------------------------------------------------
function myimage (fam_type : families_type) return string is
variable temp : families_type :=fam_type;
begin
case temp is
when nofamily => return "nofamily" ;
when virtex => return "virtex" ;
when spartan2 => return "spartan2" ;
when spartan2e => return "spartan2e" ;
when virtexe => return "virtexe" ;
when virtex2 => return "virtex2" ;
when qvirtex2 => return "qvirtex2" ;
when qrvirtex2 => return "qrvirtex2" ;
when virtex2p => return "virtex2p" ;
when spartan3 => return "spartan3" ;
when aspartan3 => return "aspartan3" ;
when spartan3e => return "spartan3e" ;
when virtex4 => return "virtex4" ;
when virtex4lx => return "virtex4lx" ;
when virtex4fx => return "virtex4fx" ;
when virtex4sx => return "virtex4sx" ;
when virtex5 => return "virtex5" ;
when spartan3a => return "spartan3a" ;
when spartan3an => return "spartan3an" ;
when spartan3adsp => return "spartan3adsp" ;
when aspartan3e => return "aspartan3e" ;
when aspartan3a => return "aspartan3a" ;
when aspartan3adsp => return "aspartan3adsp";
when qvirtex4 => return "qvirtex4" ;
when qrvirtex4 => return "qrvirtex4" ;
when spartan6 => return "spartan6" ;
when virtex6 => return "virtex6" ;
when spartan6l => return "spartan6l" ;
when qspartan6 => return "qspartan6" ;
when aspartan6 => return "aspartan6" ;
when virtex6l => return "virtex6l" ;
when qspartan6l => return "qspartan6l" ;
when qvirtex5 => return "qvirtex5" ;
when qvirtex6 => return "qvirtex6" ;
when qrvirtex5 => return "qrvirtex5" ;
when virtex5tx => return "virtex5tx" ;
when virtex5fx => return "virtex5fx" ;
when virtex6cx => return "virtex6cx" ;
when virtex7 => return "virtex7" ;
when virtex7l => return "virtex7l" ;
when qvirtex7 => return "qvirtex7" ;
when qvirtex7l => return "qvirtex7l" ;
when kintex7 => return "kintex7" ;
when kintex7l => return "kintex7l" ;
when qkintex7 => return "qkintex7" ;
when qkintex7l => return "qkintex7l" ;
when artix7 => return "artix7" ;
when aartix7 => return "aartix7" ;
when artix7l => return "artix7l" ;
when qartix7 => return "qartix7" ;
when zynq => return "zynq" ;
when azynq => return "azynq" ;
when qzynq => return "qzynq" ;
end case;
end myimage;
----------------------------------------------------------------------------
-- Function: get_root_family
--
-- This function takes in the string for the desired FPGA family type and
-- returns the root FPGA family type string. This is used for derivative part
-- aliasing to the root family. This is primarily for fifo_generator and
-- blk_mem_gen calls that need the root family passed to the call.
----------------------------------------------------------------------------
function get_root_family(family_in : string) return string is
begin
-- spartan3 Root family
if (equalIgnoringCase(family_in, "spartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3an" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3a" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3adsp" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "spartan3e" )) Then return "spartan3" ;
Elsif (equalIgnoringCase(family_in, "aspartan3e" )) Then return "spartan3" ;
-- virtex4 Root family
Elsif (equalIgnoringCase(family_in, "virtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4lx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4fx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "virtex4sx" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qvirtex4" )) Then return "virtex4" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex4" )) Then return "virtex4" ;
-- virtex5 Root family
Elsif (equalIgnoringCase(family_in, "virtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "qrvirtex5" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5tx" )) Then return "virtex5" ;
Elsif (equalIgnoringCase(family_in, "virtex5fx" )) Then return "virtex5" ;
-- virtex6 Root family
Elsif (equalIgnoringCase(family_in, "virtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6l" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "qvirtex6" )) Then return "virtex6" ;
Elsif (equalIgnoringCase(family_in, "virtex6cx" )) Then return "virtex6" ;
-- spartan6 Root family
Elsif (equalIgnoringCase(family_in, "spartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "spartan6l" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "aspartan6" )) Then return "spartan6" ;
Elsif (equalIgnoringCase(family_in, "qspartan6l" )) Then return "spartan6" ;
-- Virtex7 Root family
Elsif (equalIgnoringCase(family_in, "virtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "virtex7l" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7" )) Then return "virtex7" ;
Elsif (equalIgnoringCase(family_in, "qvirtex7l" )) Then return "virtex7" ;
-- Kintex7 Root family
Elsif (equalIgnoringCase(family_in, "kintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "kintex7l" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7" )) Then return "kintex7" ;
Elsif (equalIgnoringCase(family_in, "qkintex7l" )) Then return "kintex7" ;
-- artix7 Root family
Elsif (equalIgnoringCase(family_in, "artix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "aartix7" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "artix7l" )) Then return "artix7" ;
Elsif (equalIgnoringCase(family_in, "qartix7" )) Then return "artix7" ;
-- zynq Root family
Elsif (equalIgnoringCase(family_in, "zynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "azynq" )) Then return "zynq" ;
Elsif (equalIgnoringCase(family_in, "qzynq" )) Then return "zynq" ;
-- No Match to supported families and derivatives
Else return "nofamily";
End if;
end get_root_family;
function toLowerCaseChar( char : character ) return character is
begin
-- If char is not an upper case letter then return char
if char < 'A' OR char > 'Z' then
return char;
end if;
-- Otherwise map char to its corresponding lower case character and
-- return that
case char is
when 'A' => return 'a';
when 'B' => return 'b';
when 'C' => return 'c';
when 'D' => return 'd';
when 'E' => return 'e';
when 'F' => return 'f';
when 'G' => return 'g';
when 'H' => return 'h';
when 'I' => return 'i';
when 'J' => return 'j';
when 'K' => return 'k';
when 'L' => return 'l';
when 'M' => return 'm';
when 'N' => return 'n';
when 'O' => return 'o';
when 'P' => return 'p';
when 'Q' => return 'q';
when 'R' => return 'r';
when 'S' => return 's';
when 'T' => return 't';
when 'U' => return 'u';
when 'V' => return 'v';
when 'W' => return 'w';
when 'X' => return 'x';
when 'Y' => return 'y';
when 'Z' => return 'z';
when others => return char;
end case;
end toLowerCaseChar;
----------------------------------------------------------------------------
-- Function: equalIgnoringCase
--
-- Compare one string against another for equality with case insensitivity.
-- Can be used to test see if a family, C_FAMILY, is equal to some
-- family. However such usage is discouraged. Use instead availability
-- primitive guards based on the function, 'supported', wherever possible.
----------------------------------------------------------------------------
function equalIgnoringCase( str1, str2 : string ) return boolean is
constant LEN1 : integer := str1'length;
constant LEN2 : integer := str2'length;
variable equal : boolean := TRUE;
begin
if not (LEN1 = LEN2) then
equal := FALSE;
else
for i in str1'range loop
if not (toLowerCaseChar(str1(i)) = toLowerCaseChar(str2(i))) then
equal := FALSE;
end if;
end loop;
end if;
return equal;
end equalIgnoringCase;
----------------------------------------------------------------------------
-- Conversions from/to STRING to/from families_type.
-- These are convenience functions that are not normally needed when
-- using the 'supported' functions.
----------------------------------------------------------------------------
function str2fam( fam_as_string : string ) return families_type is
--
variable fas : string(1 to fam_as_string'length) := fam_as_string;
variable fam : families_type;
--
begin
-- Search for and return the corresponding family.
for fam in families_type'low to families_type'high loop
if equalIgnoringCase(fas, myimage(fam)) then return fam; end if;
end loop;
-- If there is no matching family, report a warning and return nofamily.
assert false
report "Package system_xadc_wiz_0_0_family_support: Function str2fam called" &
" with string parameter, " & fam_as_string &
", that does not correspond" &
" to a supported family. Returning nofamily."
severity warning;
return nofamily;
end str2fam;
function fam2str( fam : families_type) return string is
begin
--return families_type'IMAGE(fam);
return myimage(fam);
end fam2str;
function supported( fam_as_str : string;
primitive : primitives_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitive);
end supported;
function supported( fam_as_str : string;
primitives : primitive_array_type
) return boolean is
begin
return supported(str2fam(fam_as_str), primitives);
end supported;
----------------------------------------------------------------------------
-- Function: native_lut_size, two overloads.
----------------------------------------------------------------------------
function native_lut_size( fam : families_type;
no_lut_return_val : natural := 0
) return natural is
begin
if supported(fam, u_LUT6) then return 6;
elsif supported(fam, u_LUT5) then return 5;
elsif supported(fam, u_LUT4) then return 4;
elsif supported(fam, u_LUT3) then return 3;
elsif supported(fam, u_LUT2) then return 2;
elsif supported(fam, u_LUT1) then return 1;
else return no_lut_return_val;
end if;
end;
function native_lut_size( fam_as_string : string;
no_lut_return_val : natural := 0
) return natural is
begin
return native_lut_size( fam => str2fam(fam_as_string),
no_lut_return_val => no_lut_return_val
);
end;
end package body system_xadc_wiz_0_0_family_support;
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity lookup is
generic (TABLE: ctl_lut_t
);
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;X: in ctl_signal
;Y: in ctl_signal
;Z: out ctl_signal
);
end entity;
architecture lookup_impl of lookup is
attribute ram_style: string;
signal rom: ctl_lut_t := TABLE;
attribute ram_style of rom: signal is "block";
signal s1_left_ref: ctl_signal := (others => '0');
signal s1_right_ref: ctl_signal := (others => '0');
signal s1_y: ctl_signal := (others => '0');
signal s2_left_mult: unsigned(12 downto 0) := (others => '0');
signal s2_right_mult: unsigned(12 downto 0) := (others => '0');
signal s3_z_buf: ctl_signal := (others => '0');
begin
process(CLK_EVEN)
variable x_ix: integer range 0 to 255;
variable y_ix: integer range 0 to 15;
begin
if EN = '1' and rising_edge(CLK_EVEN) then
x_ix := to_integer(X);
y_ix := to_integer(Y(7 downto 4));
s1_left_ref <= rom(x_ix, y_ix);
end if;
end process;
process(CLK_EVEN)
variable y_plusone: unsigned(4 downto 0);
variable x_ix: integer range 0 to 255;
variable y_ix: integer range 1 to 16;
begin
if EN = '1' and rising_edge(CLK_EVEN) then
y_plusone := ("0" & Y(7 downto 4)) + 1;
x_ix := to_integer(X);
y_ix := to_integer(y_plusone);
s1_right_ref <= rom(x_ix, y_ix);
end if;
end process;
process(CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s1_y <= Y;
end if;
end process;
process(CLK_ODD)
variable s1_y_recip: unsigned(4 downto 0);
begin
if EN = '1' and rising_edge(CLK_ODD) then
s1_y_recip := "10000" - s1_y(3 downto 0);
s2_left_mult <= s1_y_recip * s1_left_ref;
end if;
end process;
process(CLK_ODD)
variable s1_y_fact: unsigned(4 downto 0);
begin
if EN = '1' and rising_edge(CLK_ODD) then
s1_y_fact := "0" & s1_y(3 downto 0);
s2_right_mult <= s1_y_fact * s1_right_ref;
end if;
end process;
process(CLK_EVEN)
variable s2_z_wide: unsigned(12 downto 0);
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s2_z_wide := s2_left_mult + s2_right_mult;
s3_z_buf <= s2_z_wide(11 downto 4);
end if;
end process;
Z <= s3_z_buf;
end architecture;
|
--
-- Knobs Galore - a free phase distortion synthesizer
-- Copyright (C) 2015 Ilmo Euro
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.common.all;
entity lookup is
generic (TABLE: ctl_lut_t
);
port (EN: in std_logic
;CLK_EVEN: in std_logic
;CLK_ODD: in std_logic
;X: in ctl_signal
;Y: in ctl_signal
;Z: out ctl_signal
);
end entity;
architecture lookup_impl of lookup is
attribute ram_style: string;
signal rom: ctl_lut_t := TABLE;
attribute ram_style of rom: signal is "block";
signal s1_left_ref: ctl_signal := (others => '0');
signal s1_right_ref: ctl_signal := (others => '0');
signal s1_y: ctl_signal := (others => '0');
signal s2_left_mult: unsigned(12 downto 0) := (others => '0');
signal s2_right_mult: unsigned(12 downto 0) := (others => '0');
signal s3_z_buf: ctl_signal := (others => '0');
begin
process(CLK_EVEN)
variable x_ix: integer range 0 to 255;
variable y_ix: integer range 0 to 15;
begin
if EN = '1' and rising_edge(CLK_EVEN) then
x_ix := to_integer(X);
y_ix := to_integer(Y(7 downto 4));
s1_left_ref <= rom(x_ix, y_ix);
end if;
end process;
process(CLK_EVEN)
variable y_plusone: unsigned(4 downto 0);
variable x_ix: integer range 0 to 255;
variable y_ix: integer range 1 to 16;
begin
if EN = '1' and rising_edge(CLK_EVEN) then
y_plusone := ("0" & Y(7 downto 4)) + 1;
x_ix := to_integer(X);
y_ix := to_integer(y_plusone);
s1_right_ref <= rom(x_ix, y_ix);
end if;
end process;
process(CLK_EVEN)
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s1_y <= Y;
end if;
end process;
process(CLK_ODD)
variable s1_y_recip: unsigned(4 downto 0);
begin
if EN = '1' and rising_edge(CLK_ODD) then
s1_y_recip := "10000" - s1_y(3 downto 0);
s2_left_mult <= s1_y_recip * s1_left_ref;
end if;
end process;
process(CLK_ODD)
variable s1_y_fact: unsigned(4 downto 0);
begin
if EN = '1' and rising_edge(CLK_ODD) then
s1_y_fact := "0" & s1_y(3 downto 0);
s2_right_mult <= s1_y_fact * s1_right_ref;
end if;
end process;
process(CLK_EVEN)
variable s2_z_wide: unsigned(12 downto 0);
begin
if EN = '1' and rising_edge(CLK_EVEN) then
s2_z_wide := s2_left_mult + s2_right_mult;
s3_z_buf <= s2_z_wide(11 downto 4);
end if;
end process;
Z <= s3_z_buf;
end architecture;
|
-- multiple1902 <[email protected]>
-- Released under GNU GPL v3, or later.
library ieee;
use ieee.std_logic_1164.all;
entity fourstep_tb is
end fourstep_tb;
architecture behav of fourstep_tb is
component fourstep
port (
clk : in std_logic;
step : out std_logic_vector(3 downto 0) -- no semicolon here!
);
end component;
for fourstep_0: fourstep use entity work.fourstep;
signal clk : std_logic;
signal step : std_logic_vector(3 downto 0);
begin
fourstep_0: fourstep port map (
clk => clk,
step => step
);
process
begin
for i in 0 to 20 loop
clk<='0';
wait for 10 ms;
clk<='1';
wait for 10 ms;
end loop;
assert false report "have a nice day!" severity note;
wait;
end process;
end behav;
|
-------------------------------------------------------------------------------
-- FT2232H Sync FIFO Interface
--
-- This component is designed to interface an FT2232H USB chip with two
-- dual-port FIFOs in first-word-fall-through (zero read latency) mode. The
-- FIFOs are used for buffering and (de)serializing data words and for
-- crossing the USB and FPGA clock domains.
-------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ft2232fifo is
port (
-- ftdi interface
usb_clk: in std_logic;
usb_oe_n: out std_logic;
usb_rd_n: out std_logic;
usb_wr_n: out std_logic;
usb_rxf_n: in std_logic;
usb_txe_n: in std_logic;
usb_d: inout std_logic_vector(7 downto 0);
-- application/fifo interface
rst: in std_logic;
fifo_in_wr_en: out std_logic;
fifo_in_full: in std_logic;
fifo_in_data: out std_logic_vector(7 downto 0);
fifo_out_rd_en: out std_logic;
fifo_out_empty: in std_logic;
fifo_out_data: in std_logic_vector(7 downto 0)
);
end ft2232fifo;
architecture ft2232fifo_arch of ft2232fifo is
-- registers for signals from or to ftdi
signal qusb_rxf_n: std_logic := '1';
signal qusb_txe_n: std_logic := '1';
signal usb_rxf, usb_txe: std_logic;
signal usb_rd_en: std_logic := '0';
signal usb_wr_en: std_logic := '0';
signal usb_rd_en_at_ftdi: std_logic := '0';
signal usb_wr_en_at_ftdi: std_logic := '0';
signal usb_d_out, usb_d_in: std_logic_vector(7 downto 0) := (others => '-');
signal int_rd_en, int_wr_en, int_oe: std_logic;
signal int_d_out: std_logic_vector(7 downto 0);
signal drive_usb_d: boolean;
signal fifo_in_wr_en_i, fifo_out_rd_en_i: std_logic;
type byte_array_t is array(integer range <>) of std_logic_vector(7 downto 0);
-- data read buffer
signal rx_data_ring: byte_array_t(3 downto 0) := (others => (others => '-'));
signal rx_index_rd: unsigned(1 downto 0) := (others => '0');
signal rx_index_wr: unsigned(1 downto 0) := (others => '0');
signal rx_count: integer range 0 to rx_data_ring'high := 0;
-- data write buffer
signal tx_data_ring: byte_array_t(3 downto 0) := (others => (others => '-'));
signal tx_index_rd: unsigned(1 downto 0) := (others => '0');
signal tx_index_wr: unsigned(1 downto 0) := (others => '0');
signal tx_count: integer range 0 to tx_data_ring'high := 0;
-- state register
type state_t is (
s_reset, s_idle,
s_switch_to_read, s_read, s_end_read,
s_write
);
signal state, next_state: state_t := s_reset;
attribute iob: string;
--attribute iob of usb_rxf_n: signal is "FORCE";
--attribute iob of usb_txe_n: signal is "FORCE";
attribute iob of usb_wr_n: signal is "FORCE";
attribute iob of usb_rd_n: signal is "FORCE";
attribute iob of usb_oe_n: signal is "FORCE";
--attribute iob of usb_d: signal is "FORCE";
--attribute iob of usb_d_out: signal is "FORCE"; -- TODO: drive_usb_d must be registered for moving usb_d to iob
--attribute iob of usb_d_in: signal is "FORCE";
begin
usb_d <= usb_d_out when drive_usb_d else (others => 'Z');
sync_input: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
qusb_rxf_n <= '1';
qusb_txe_n <= '1';
usb_d_in <= (others => '-');
else
qusb_rxf_n <= usb_rxf_n;
qusb_txe_n <= usb_txe_n;
usb_d_in <= usb_d;
end if;
end if;
end process;
usb_rxf <= not qusb_rxf_n;
usb_txe <= not qusb_txe_n;
sync_state: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
state <= s_reset;
else
state <= next_state;
end if;
end if;
end process;
sync_receive_data: process(usb_clk)
variable byte_delta: integer range -1 to 1;
begin
if rising_edge(usb_clk) then
if rst = '1' then
rx_count <= 0;
rx_index_rd <= (others => '0');
rx_index_wr <= (others => '0');
rx_data_ring <= (others => (others => '-'));
else
byte_delta := 0;
-- add byte from usb to ring if valid
if (usb_rd_en_at_ftdi = '1') and (usb_rxf = '1') then
rx_data_ring(to_integer(rx_index_wr)) <= usb_d_in;
rx_index_wr <= rx_index_wr + 1;
byte_delta := byte_delta + 1;
end if;
-- remove byte from ring if read from interface
if (fifo_in_wr_en_i = '1') and (fifo_in_full = '0') then
rx_index_rd <= rx_index_rd + 1;
byte_delta := byte_delta - 1;
end if;
rx_count <= rx_count + byte_delta;
end if;
end if;
end process;
fifo_in_data <= rx_data_ring(to_integer(rx_index_rd)) when rx_count /= 0 else (others => '-');
fifo_in_wr_en_i <= '1' when rx_count /= 0 else '0';
fifo_in_wr_en <= fifo_in_wr_en_i;
sync_transmit_data: process(usb_clk)
variable byte_delta: integer range -1 to 1;
begin
if rising_edge(usb_clk) then
if rst = '1' then
tx_count <= 0;
tx_index_rd <= (others => '0');
tx_index_wr <= (others => '0');
tx_data_ring <= (others => (others => '-'));
else
byte_delta := 0;
-- add byte from interface
if (fifo_out_rd_en_i = '1') and (fifo_out_empty = '0') then
tx_data_ring(to_integer(tx_index_wr)) <= fifo_out_data;
tx_index_wr <= tx_index_wr + 1;
byte_delta := byte_delta + 1;
end if;
-- advance data pointer at each write
if int_wr_en = '1' then
tx_index_rd <= tx_index_rd + 1;
byte_delta := byte_delta - 1;
end if;
-- recover byte from ring if write was not accepted
if (usb_wr_en_at_ftdi = '1') and (usb_txe = '0') then
tx_index_rd <= tx_index_rd - 1;
byte_delta := byte_delta + 1;
end if;
tx_count <= tx_count + byte_delta;
end if;
end if;
end process;
comb_state: process(state,
fifo_in_full, usb_rxf, rx_count,
fifo_out_empty, usb_txe, tx_count)
variable could_wr, could_rd: boolean;
begin
-- next state
next_state <= state;
-- output defaults
drive_usb_d <= false;
int_oe <= '0';
int_rd_en <= '0';
int_wr_en <= '0';
-- internal defaults
fifo_out_rd_en_i <= '0';
could_wr := (usb_txe = '1') and ((tx_count > 0) or (fifo_out_empty = '0'));
could_rd := (fifo_in_full = '0') and (usb_rxf = '1') and (rx_count <= 1);
case state is
when s_reset =>
next_state <= s_idle;
when s_idle =>
-- switch to write or read mode
if could_wr then
next_state <= s_write;
elsif could_rd then
next_state <= s_switch_to_read;
end if;
when s_switch_to_read =>
-- disable our outputs and enable usb outputs
int_oe <= '1';
next_state <= s_read;
when s_read =>
-- read data from usb
int_oe <= '1';
int_rd_en <= '1';
-- end reading if there is nothing to read or interface won't accpet more data
if not could_rd then
int_rd_en <= '0';
next_state <= s_end_read;
end if;
when s_end_read =>
-- wait until last read command passed
if could_wr then
next_state <= s_write;
else
next_state <= s_idle;
end if;
when s_write =>
drive_usb_d <= true;
if could_wr then
-- write valid data to usb
if tx_count > 0 then
int_wr_en <= '1';
end if;
-- fetch data from interface if there is enough space for failed writes
if tx_count <= 1 then
fifo_out_rd_en_i <= '1';
end if;
else
-- end writing if there is nothing to write or usb won't accept more data
if could_rd then
next_state <= s_switch_to_read;
else
next_state <= s_idle;
end if;
end if;
when others =>
null;
end case;
end process;
int_d_out <= tx_data_ring(to_integer(tx_index_rd));
fifo_out_rd_en <= fifo_out_rd_en_i;
sync_output_internal: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
usb_rd_en <= '0';
usb_wr_en <= '0';
usb_rd_en_at_ftdi <= '0';
usb_wr_en_at_ftdi <= '0';
else
usb_rd_en <= int_rd_en;
usb_wr_en <= int_wr_en;
usb_rd_en_at_ftdi <= usb_rd_en;
usb_wr_en_at_ftdi <= usb_wr_en;
end if;
end if;
end process;
sync_output: process(usb_clk)
begin
if rising_edge(usb_clk) then
if rst = '1' then
usb_d_out <= (others => '-');
usb_oe_n <= '1';
usb_rd_n <= '1';
usb_wr_n <= '1';
else
usb_d_out <= int_d_out;
usb_oe_n <= not int_oe;
usb_rd_n <= not int_rd_en;
usb_wr_n <= not int_wr_en;
end if;
end if;
end process;
end ft2232fifo_arch;
|
------------------------------------------------------------------------------
-- Copyright (c) 2014, Pascal Trotta - Testgroup (Politecnico di Torino)
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright notice, this
-- list of conditions and the following disclaimer in the documentation and/or other
-- materials provided with the distribution.
--
-- THIS SOURCE CODE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY
-- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
-- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-- ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
-- OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
-----------------------------------------------------------------------------
-- Entity: dprc_pkg
-- File: dprc_pkg.vhd
-- Author: Pascal Trotta (TestGroup research group - Politecnico di Torino)
-- Contacts: [email protected] www.testgroup.polito.it
-- Description: dprc package including types definitions, procedures and components declarations
-- Last revision: 29/09/2014
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.devices.all;
use grlib.DMA2AHB_Package.all;
library techmap;
use techmap.gencomp.all;
package dprc_pkg is
-------------------------------------------------------------------------------
-- Types
-------------------------------------------------------------------------------
-- ICAP I/O signals
type icap_in_type is record
idata : std_logic_vector(31 downto 0);
wen : std_ulogic;
cen : std_ulogic;
end record;
type icap_out_type is record
odata : std_logic_vector(31 downto 0);
busy : std_ulogic;
end record;
-- read-only APB registers
type dprc_apbregout_type is record
status : std_logic_vector(31 downto 0);
timer : std_logic_vector(31 downto 0);
end record;
-- control signals for APB registers
type dprc_apbcontrol_type is record
status_value : std_logic_vector(31 downto 0);
control_clr : std_ulogic;
status_en : std_ulogic;
status_clr : std_ulogic;
timer_en : std_ulogic;
timer_clear : std_ulogic;
end record;
-- write/read APB registers
type dprc_apbregin_type is record
control : std_logic_vector(31 downto 0);
address : std_logic_vector(31 downto 0);
rm_reset : std_logic_vector(31 downto 0);
end record;
-------------------------------------------------------------------------------
-- Functions & Procedures
-------------------------------------------------------------------------------
procedure icapbyteswap(signal idata : in std_logic_vector(31 downto 0); signal odata : out std_logic_vector(31 downto 0));
procedure crc(signal idata : in std_logic_vector(31 downto 0); signal q : in std_logic_vector(31 downto 0); variable d : out std_logic_vector(31 downto 0));
procedure gray_encoder(variable idata : in std_logic_vector; variable odata : out std_logic_vector);
procedure gray_decoder(signal idata : in std_logic_vector; constant size : integer; variable odata : out std_logic_vector);
-------------------------------------------------------------------------------
-- Components
-------------------------------------------------------------------------------
component dprc is
generic (
cfg_clkmul : integer := 2; -- clkraw multiplier
cfg_clkdiv : integer := 1; -- clkraw divisor
raw_freq : integer := 50000; -- Board frequency in KHz
clk_sel : integer := 0; -- Select between clkraw and clk100 for ICAP domain clk when configured in async or d2prc mode
hindex : integer := 2; -- AMBA AHB master index
vendorid : integer := VENDOR_CONTRIB; -- Vendor ID
deviceid : integer := CONTRIB_CORE1; -- Device ID
version : integer := 1; -- Device version
pindex : integer := 13; -- AMBA APB slave index
paddr : integer := 13; -- Address for APB I/O BAR
pmask : integer := 16#fff#; -- Mask for APB I/O BAR
technology : integer := virtex4; -- FPGA target technology
crc_en : integer := 0; -- Bitstream verification enable (d2prc mode)
words_block : integer := 10; -- Number of 32-bit words in a CRC-block
fifo_dcm_inst : integer := 1; -- Instantiate clock generator and fifo (async/sync mode)
fifo_depth : integer := 9); -- Number of addressing bits for the FIFO (true FIFO depth = 2**fifo_depth)
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clkraw : in std_ulogic; -- Raw Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
ahbmi : in ahb_mst_in_type; -- AHB master input
ahbmo : out ahb_mst_out_type; -- AHB master output
apbi : in apb_slv_in_type; -- APB slave input
apbo : out apb_slv_out_type; -- APB slave output
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition)
end component;
component d2prc is
generic (
technology : integer := virtex4; -- FPGA target technology
fifo_depth : integer := 9; -- true FIFO depth = 2**fifo_depth
crc_block : integer := 10); -- Number of 32-bit words in a CRC-block
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition));
end component;
component async_dprc is
generic (
technology : integer := virtex4; -- Target technology
fifo_depth : integer := 9); -- true FIFO depth = 2**fifo_depth
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
clk100 : in std_ulogic; -- 100 MHz Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition));
end component;
component sync_dprc is
port (
rstn : in std_ulogic; -- Asynchronous Reset input (active low)
clkm : in std_ulogic; -- Clock input
dmai : out DMA_In_Type; -- dma signals input
dmao : in DMA_Out_Type; -- dma signals output
icapi : out icap_in_type; -- icap input signals
icapo : in icap_out_type; -- icap output signals
apbregi : in dprc_apbregin_type; -- values from apb registers (control, address, rm_reset)
apbcontrol : out dprc_apbcontrol_type; -- control signals for apb register
rm_reset : out std_logic_vector(31 downto 0)); -- Reconfigurable modules reset (1 bit for each different reconfigurable partition));
end component;
end package;
package body dprc_pkg is
procedure icapbyteswap(signal idata : in std_logic_vector(31 downto 0); signal odata : out std_logic_vector(31 downto 0)) is
begin
for i in 0 to 3 loop
for j in 0+i*8 to 7+i*8 loop
odata(j)<=idata(7+i*8-(j-i*8));
end loop;
end loop;
end icapbyteswap;
procedure crc(signal idata : in std_logic_vector(31 downto 0); signal q : in std_logic_vector(31 downto 0); variable d : out std_logic_vector(31 downto 0)) is
-------------------------------------------------------------------------------
-- Copyright (C) 2009 OutputLogic.com
-- This source file may be used and distributed without restriction
-- provided that this copyright statement is not removed from the file
-- and that any derivative work contains the original copyright notice
-- and the associated disclaimer.
--
-- THIS SOURCE FILE IS PROVIDED "AS IS" AND WITHOUT ANY EXPRESS
-- OR IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
-- WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
-------------------------------------------------------------------------------
variable dv : std_logic_vector(31 downto 0);
begin
d(0) := q(0) xor q(3) xor q(6) xor q(9) xor q(12) xor q(14) xor q(15) xor q(20) xor q(21) xor q(26) xor q(27) xor q(28) xor q(29) xor q(31) xor idata(0) xor idata(3) xor idata(6) xor idata(9) xor idata(12) xor idata(14) xor idata(15) xor idata(20) xor idata(21) xor idata(26) xor idata(27) xor idata(28) xor idata(29) xor idata(31);
d(1) := q(1) xor q(4) xor q(7) xor q(10) xor q(13) xor q(15) xor q(16) xor q(21) xor q(22) xor q(27) xor q(28) xor q(29) xor q(30) xor idata(1) xor idata(4) xor idata(7) xor idata(10) xor idata(13) xor idata(15) xor idata(16) xor idata(21) xor idata(22) xor idata(27) xor idata(28) xor idata(29) xor idata(30);
d(2) := q(2) xor q(5) xor q(8) xor q(11) xor q(14) xor q(16) xor q(17) xor q(22) xor q(23) xor q(28) xor q(29) xor q(30) xor q(31) xor idata(2) xor idata(5) xor idata(8) xor idata(11) xor idata(14) xor idata(16) xor idata(17) xor idata(22) xor idata(23) xor idata(28) xor idata(29) xor idata(30) xor idata(31);
d(3) := q(0) xor q(14) xor q(17) xor q(18) xor q(20) xor q(21) xor q(23) xor q(24) xor q(26) xor q(27) xor q(28) xor q(30) xor idata(0) xor idata(14) xor idata(17) xor idata(18) xor idata(20) xor idata(21) xor idata(23) xor idata(24) xor idata(26) xor idata(27) xor idata(28) xor idata(30);
d(4) := q(1) xor q(15) xor q(18) xor q(19) xor q(21) xor q(22) xor q(24) xor q(25) xor q(27) xor q(28) xor q(29) xor q(31) xor idata(1) xor idata(15) xor idata(18) xor idata(19) xor idata(21) xor idata(22) xor idata(24) xor idata(25) xor idata(27) xor idata(28) xor idata(29) xor idata(31);
d(5) := q(2) xor q(16) xor q(19) xor q(20) xor q(22) xor q(23) xor q(25) xor q(26) xor q(28) xor q(29) xor q(30) xor idata(2) xor idata(16) xor idata(19) xor idata(20) xor idata(22) xor idata(23) xor idata(25) xor idata(26) xor idata(28) xor idata(29) xor idata(30);
d(6) := q(3) xor q(17) xor q(20) xor q(21) xor q(23) xor q(24) xor q(26) xor q(27) xor q(29) xor q(30) xor q(31) xor idata(3) xor idata(17) xor idata(20) xor idata(21) xor idata(23) xor idata(24) xor idata(26) xor idata(27) xor idata(29) xor idata(30) xor idata(31);
d(7) := q(4) xor q(18) xor q(21) xor q(22) xor q(24) xor q(25) xor q(27) xor q(28) xor q(30) xor q(31) xor idata(4) xor idata(18) xor idata(21) xor idata(22) xor idata(24) xor idata(25) xor idata(27) xor idata(28) xor idata(30) xor idata(31);
d(8) := q(5) xor q(19) xor q(22) xor q(23) xor q(25) xor q(26) xor q(28) xor q(29) xor q(31) xor idata(5) xor idata(19) xor idata(22) xor idata(23) xor idata(25) xor idata(26) xor idata(28) xor idata(29) xor idata(31);
d(9) := q(6) xor q(20) xor q(23) xor q(24) xor q(26) xor q(27) xor q(29) xor q(30) xor idata(6) xor idata(20) xor idata(23) xor idata(24) xor idata(26) xor idata(27) xor idata(29) xor idata(30);
d(10) := q(7) xor q(21) xor q(24) xor q(25) xor q(27) xor q(28) xor q(30) xor q(31) xor idata(7) xor idata(21) xor idata(24) xor idata(25) xor idata(27) xor idata(28) xor idata(30) xor idata(31);
d(11) := q(8) xor q(22) xor q(25) xor q(26) xor q(28) xor q(29) xor q(31) xor idata(8) xor idata(22) xor idata(25) xor idata(26) xor idata(28) xor idata(29) xor idata(31);
d(12) := q(9) xor q(23) xor q(26) xor q(27) xor q(29) xor q(30) xor idata(9) xor idata(23) xor idata(26) xor idata(27) xor idata(29) xor idata(30);
d(13) := q(10) xor q(24) xor q(27) xor q(28) xor q(30) xor q(31) xor idata(10) xor idata(24) xor idata(27) xor idata(28) xor idata(30) xor idata(31);
d(14) := q(0) xor q(3) xor q(6) xor q(9) xor q(11) xor q(12) xor q(14) xor q(15) xor q(20) xor q(21) xor q(25) xor q(26) xor q(27) xor idata(0) xor idata(3) xor idata(6) xor idata(9) xor idata(11) xor idata(12) xor idata(14) xor idata(15) xor idata(20) xor idata(21) xor idata(25) xor idata(26) xor idata(27);
d(15) := q(1) xor q(4) xor q(7) xor q(10) xor q(12) xor q(13) xor q(15) xor q(16) xor q(21) xor q(22) xor q(26) xor q(27) xor q(28) xor idata(1) xor idata(4) xor idata(7) xor idata(10) xor idata(12) xor idata(13) xor idata(15) xor idata(16) xor idata(21) xor idata(22) xor idata(26) xor idata(27) xor idata(28);
d(16) := q(2) xor q(5) xor q(8) xor q(11) xor q(13) xor q(14) xor q(16) xor q(17) xor q(22) xor q(23) xor q(27) xor q(28) xor q(29) xor idata(2) xor idata(5) xor idata(8) xor idata(11) xor idata(13) xor idata(14) xor idata(16) xor idata(17) xor idata(22) xor idata(23) xor idata(27) xor idata(28) xor idata(29);
d(17) := q(3) xor q(6) xor q(9) xor q(12) xor q(14) xor q(15) xor q(17) xor q(18) xor q(23) xor q(24) xor q(28) xor q(29) xor q(30) xor idata(3) xor idata(6) xor idata(9) xor idata(12) xor idata(14) xor idata(15) xor idata(17) xor idata(18) xor idata(23) xor idata(24) xor idata(28) xor idata(29) xor idata(30);
d(18) := q(0) xor q(3) xor q(4) xor q(6) xor q(7) xor q(9) xor q(10) xor q(12) xor q(13) xor q(14) xor q(16) xor q(18) xor q(19) xor q(20) xor q(21) xor q(24) xor q(25) xor q(26) xor q(27) xor q(28) xor q(30) xor idata(0) xor idata(3) xor idata(4) xor idata(6) xor idata(7) xor idata(9) xor idata(10) xor idata(12) xor idata(13) xor idata(14) xor idata(16) xor idata(18) xor idata(19) xor idata(20) xor idata(21) xor idata(24) xor idata(25) xor idata(26) xor idata(27) xor idata(28) xor idata(30);
d(19) := q(1) xor q(4) xor q(5) xor q(7) xor q(8) xor q(10) xor q(11) xor q(13) xor q(14) xor q(15) xor q(17) xor q(19) xor q(20) xor q(21) xor q(22) xor q(25) xor q(26) xor q(27) xor q(28) xor q(29) xor q(31) xor idata(1) xor idata(4) xor idata(5) xor idata(7) xor idata(8) xor idata(10) xor idata(11) xor idata(13) xor idata(14) xor idata(15) xor idata(17) xor idata(19) xor idata(20) xor idata(21) xor idata(22) xor idata(25) xor idata(26) xor idata(27) xor idata(28) xor idata(29) xor idata(31);
d(20) := q(2) xor q(5) xor q(6) xor q(8) xor q(9) xor q(11) xor q(12) xor q(14) xor q(15) xor q(16) xor q(18) xor q(20) xor q(21) xor q(22) xor q(23) xor q(26) xor q(27) xor q(28) xor q(29) xor q(30) xor idata(2) xor idata(5) xor idata(6) xor idata(8) xor idata(9) xor idata(11) xor idata(12) xor idata(14) xor idata(15) xor idata(16) xor idata(18) xor idata(20) xor idata(21) xor idata(22) xor idata(23) xor idata(26) xor idata(27) xor idata(28) xor idata(29) xor idata(30);
d(21) := q(3) xor q(6) xor q(7) xor q(9) xor q(10) xor q(12) xor q(13) xor q(15) xor q(16) xor q(17) xor q(19) xor q(21) xor q(22) xor q(23) xor q(24) xor q(27) xor q(28) xor q(29) xor q(30) xor q(31) xor idata(3) xor idata(6) xor idata(7) xor idata(9) xor idata(10) xor idata(12) xor idata(13) xor idata(15) xor idata(16) xor idata(17) xor idata(19) xor idata(21) xor idata(22) xor idata(23) xor idata(24) xor idata(27) xor idata(28) xor idata(29) xor idata(30) xor idata(31);
d(22) := q(4) xor q(7) xor q(8) xor q(10) xor q(11) xor q(13) xor q(14) xor q(16) xor q(17) xor q(18) xor q(20) xor q(22) xor q(23) xor q(24) xor q(25) xor q(28) xor q(29) xor q(30) xor q(31) xor idata(4) xor idata(7) xor idata(8) xor idata(10) xor idata(11) xor idata(13) xor idata(14) xor idata(16) xor idata(17) xor idata(18) xor idata(20) xor idata(22) xor idata(23) xor idata(24) xor idata(25) xor idata(28) xor idata(29) xor idata(30) xor idata(31);
d(23) := q(5) xor q(8) xor q(9) xor q(11) xor q(12) xor q(14) xor q(15) xor q(17) xor q(18) xor q(19) xor q(21) xor q(23) xor q(24) xor q(25) xor q(26) xor q(29) xor q(30) xor q(31) xor idata(5) xor idata(8) xor idata(9) xor idata(11) xor idata(12) xor idata(14) xor idata(15) xor idata(17) xor idata(18) xor idata(19) xor idata(21) xor idata(23) xor idata(24) xor idata(25) xor idata(26) xor idata(29) xor idata(30) xor idata(31);
d(24) := q(6) xor q(9) xor q(10) xor q(12) xor q(13) xor q(15) xor q(16) xor q(18) xor q(19) xor q(20) xor q(22) xor q(24) xor q(25) xor q(26) xor q(27) xor q(30) xor q(31) xor idata(6) xor idata(9) xor idata(10) xor idata(12) xor idata(13) xor idata(15) xor idata(16) xor idata(18) xor idata(19) xor idata(20) xor idata(22) xor idata(24) xor idata(25) xor idata(26) xor idata(27) xor idata(30) xor idata(31);
d(25) := q(7) xor q(10) xor q(11) xor q(13) xor q(14) xor q(16) xor q(17) xor q(19) xor q(20) xor q(21) xor q(23) xor q(25) xor q(26) xor q(27) xor q(28) xor q(31) xor idata(7) xor idata(10) xor idata(11) xor idata(13) xor idata(14) xor idata(16) xor idata(17) xor idata(19) xor idata(20) xor idata(21) xor idata(23) xor idata(25) xor idata(26) xor idata(27) xor idata(28) xor idata(31);
d(26) := q(8) xor q(11) xor q(12) xor q(14) xor q(15) xor q(17) xor q(18) xor q(20) xor q(21) xor q(22) xor q(24) xor q(26) xor q(27) xor q(28) xor q(29) xor idata(8) xor idata(11) xor idata(12) xor idata(14) xor idata(15) xor idata(17) xor idata(18) xor idata(20) xor idata(21) xor idata(22) xor idata(24) xor idata(26) xor idata(27) xor idata(28) xor idata(29);
d(27) := q(9) xor q(12) xor q(13) xor q(15) xor q(16) xor q(18) xor q(19) xor q(21) xor q(22) xor q(23) xor q(25) xor q(27) xor q(28) xor q(29) xor q(30) xor idata(9) xor idata(12) xor idata(13) xor idata(15) xor idata(16) xor idata(18) xor idata(19) xor idata(21) xor idata(22) xor idata(23) xor idata(25) xor idata(27) xor idata(28) xor idata(29) xor idata(30);
d(28) := q(10) xor q(13) xor q(14) xor q(16) xor q(17) xor q(19) xor q(20) xor q(22) xor q(23) xor q(24) xor q(26) xor q(28) xor q(29) xor q(30) xor q(31) xor idata(10) xor idata(13) xor idata(14) xor idata(16) xor idata(17) xor idata(19) xor idata(20) xor idata(22) xor idata(23) xor idata(24) xor idata(26) xor idata(28) xor idata(29) xor idata(30) xor idata(31);
d(29) := q(0) xor q(3) xor q(6) xor q(9) xor q(11) xor q(12) xor q(17) xor q(18) xor q(23) xor q(24) xor q(25) xor q(26) xor q(28) xor q(30) xor idata(0) xor idata(3) xor idata(6) xor idata(9) xor idata(11) xor idata(12) xor idata(17) xor idata(18) xor idata(23) xor idata(24) xor idata(25) xor idata(26) xor idata(28) xor idata(30);
d(30) := q(1) xor q(4) xor q(7) xor q(10) xor q(12) xor q(13) xor q(18) xor q(19) xor q(24) xor q(25) xor q(26) xor q(27) xor q(29) xor q(31) xor idata(1) xor idata(4) xor idata(7) xor idata(10) xor idata(12) xor idata(13) xor idata(18) xor idata(19) xor idata(24) xor idata(25) xor idata(26) xor idata(27) xor idata(29) xor idata(31);
d(31) := q(2) xor q(5) xor q(8) xor q(11) xor q(13) xor q(14) xor q(19) xor q(20) xor q(25) xor q(26) xor q(27) xor q(28) xor q(30) xor idata(2) xor idata(5) xor idata(8) xor idata(11) xor idata(13) xor idata(14) xor idata(19) xor idata(20) xor idata(25) xor idata(26) xor idata(27) xor idata(28) xor idata(30);
end crc;
procedure gray_encoder(variable idata : in std_logic_vector; variable odata : out std_logic_vector) is
begin
for i in 0 to (idata'left)-1 loop
odata(i) := idata(i) xor idata(i+1);
end loop;
odata(odata'left) := idata(idata'left);
end gray_encoder;
procedure gray_decoder(signal idata : in std_logic_vector; constant size : integer; variable odata : out std_logic_vector) is
variable vdata : std_logic_vector(size downto 0);
begin
vdata(vdata'left) := idata(idata'left);
for i in (idata'left)-1 downto 0 loop
vdata(i) := idata(i) xor vdata(i+1);
end loop;
odata := vdata;
end gray_decoder;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1878.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01878ent IS
END c07s01b00x00p08n01i01878ent;
ARCHITECTURE c07s01b00x00p08n01i01878arch OF c07s01b00x00p08n01i01878ent IS
type small_int is range 0 to 7;
signal bool : boolean;
BEGIN
sig : bool <= true after 5 ns;
TESTING : PROCESS
variable car : small_int;
BEGIN
car := sig; --signal assignment labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01878 - Signal assignment labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01878arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1878.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01878ent IS
END c07s01b00x00p08n01i01878ent;
ARCHITECTURE c07s01b00x00p08n01i01878arch OF c07s01b00x00p08n01i01878ent IS
type small_int is range 0 to 7;
signal bool : boolean;
BEGIN
sig : bool <= true after 5 ns;
TESTING : PROCESS
variable car : small_int;
BEGIN
car := sig; --signal assignment labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01878 - Signal assignment labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01878arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1878.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s01b00x00p08n01i01878ent IS
END c07s01b00x00p08n01i01878ent;
ARCHITECTURE c07s01b00x00p08n01i01878arch OF c07s01b00x00p08n01i01878ent IS
type small_int is range 0 to 7;
signal bool : boolean;
BEGIN
sig : bool <= true after 5 ns;
TESTING : PROCESS
variable car : small_int;
BEGIN
car := sig; --signal assignment labels illegal here
wait for 5 ns;
assert FALSE
report "***FAILED TEST: c07s01b00x00p08n01i01878 - Signal assignment labels are not permitted as primaries in a variable assignment expression."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s01b00x00p08n01i01878arch;
|
---------------------------------------------------
-- School: University of Massachusetts Dartmouth
-- Department: Computer and Electrical Engineering
-- Engineer: Daniel Noyes
--
-- Create Date: SPRING 2015
-- Module Name: VGA_COLOR_TB
-- Project Name: VGA_COLOR
-- Target Devices: Spartan-3E
-- Tool versions: Xilinx ISE 14.7
-- Description: VGA_COLOR Test Bench
---------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.all;
USE ieee.numeric_std.ALL;
ENTITY VGA_TOPLEVEL_tb_vhd IS
END VGA_TOPLEVEL_tb_vhd;
ARCHITECTURE behavior OF VGA_TOPLEVEL_tb_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT VGA_TOPLEVEL
Port ( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
--SW : in STD_LOGIC_VECTOR (7 downto 0);
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
HSYNC : out STD_LOGIC;
VSYNC : out STD_LOGIC;
VGARED : out STD_LOGIC_VECTOR (2 downto 0);
VGAGRN : out STD_LOGIC_VECTOR (2 downto 0);
VGABLU : out STD_LOGIC_VECTOR (1 downto 0));
END COMPONENT;
SIGNAL CLK : STD_LOGIC := '0';
SIGNAL RST : STD_LOGIC := '0';
SIGNAL PS2_CLK : STD_LOGIC := '1';
SIGNAL PS2_DATA: STD_LOGIC := '1';
SIGNAL HSYNC : STD_LOGIC := '0';
SIGNAL VSYNC : STD_LOGIC := '0';
SIGNAL VGARED : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
SIGNAL VGAGRN : STD_LOGIC_VECTOR(2 downto 0) := (others=>'0');
SIGNAL VGABLU : STD_LOGIC_VECTOR(1 downto 0) := (others=>'0');
--SIGNAL SW : STD_LOGIC_VECTOR(7 downto 0);
-- Constants
-- constant period : time := 20 ns; -- 25 MHz =(1/20E-9)/2
constant period : time := 10 ns; -- 50 MHz =(1/10E-9)/2
-- constant period : time := 5 ns; -- 100 MHz =(1/10E-9)/2
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: VGA_TOPLEVEL PORT MAP( CLK => CLK,
RST => RST,
--SW => SW,
PS2_CLK => PS2_CLK,
PS2_DATA=> PS2_DATA,
HSYNC => HSYNC,
VSYNC => VSYNC,
VGARED => VGARED,
VGAGRN => VGAGRN,
VGABLU => VGABLU);
-- Generate clock
gen_Clock: process
begin
CLK <= '0'; wait for period;
CLK <= '1'; wait for period;
end process gen_Clock;
tb : PROCESS
BEGIN
-- Wait 100 ns for global reset to finish
wait for 100 ns;
report "Start VGA_Controller Test Bench" severity NOTE;
--Simulate Pressing A
--Sending the Break Code X"F0"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
--Sending the Key Code X"1C"
--Start bit '0'
PS2_DATA <= '0';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 7 LSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 6
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 5
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 4
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- 3
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 2
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 1
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '0'; -- 0 MSB
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Odd Parity Bit
PS2_DATA <= '0';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
-- Stop Bit '1'
PS2_DATA <= '1';
PS2_CLK <= '1';
wait for 30 us;
PS2_CLK <= '0';
wait for 30 us;
PS2_DATA <= '1'; -- END Transmission
PS2_CLK <= '1';
wait for 100 us;
wait; -- will wait forever
END PROCESS;
END;
|
------------------------------------------------------------------------
-- vga_controller_640_60.vhd
------------------------------------------------------------------------
-- Author : Ulrich Zoltán
-- Copyright 2006 Digilent, Inc.
------------------------------------------------------------------------
-- Software version : Xilinx ISE 7.1.04i
-- WebPack
-- Device : 3s200ft256-4
------------------------------------------------------------------------
-- This file contains the logic to generate the synchronization signals,
-- horizontal and vertical pixel counter and video disable signal
-- for the 640x480@60Hz resolution.
------------------------------------------------------------------------
-- Behavioral description
------------------------------------------------------------------------
-- Please read the following article on the web regarding the
-- vga video timings:
-- http://www.epanorama.net/documents/pc/vga_timing.html
-- This module generates the video synch pulses for the monitor to
-- enter 640x480@60Hz resolution state. It also provides horizontal
-- and vertical counters for the currently displayed pixel and a blank
-- signal that is active when the pixel is not inside the visible screen
-- and the color outputs should be reset to 0.
-- timing diagram for the horizontal synch signal (HS)
-- 0 648 744 800 (pixels)
-- -------------------------|______|-----------------
-- timing diagram for the vertical synch signal (VS)
-- 0 482 484 525 (lines)
-- -----------------------------------|______|-------
-- The blank signal is delayed one pixel clock period (40ns) from where
-- the pixel leaves the visible screen, according to the counters, to
-- account for the pixel pipeline delay. This delay happens because
-- it takes time from when the counters indicate current pixel should
-- be displayed to when the color data actually arrives at the monitor
-- pins (memory read delays, synchronization delays).
------------------------------------------------------------------------
-- Port definitions
------------------------------------------------------------------------
-- rst - global reset signal
-- pixel_clk - input pin, from dcm_25MHz
-- - the clock signal generated by a DCM that has
-- - a frequency of 25MHz.
-- HS - output pin, to monitor
-- - horizontal synch pulse
-- VS - output pin, to monitor
-- - vertical synch pulse
-- hcount - output pin, 11 bits, to clients
-- - horizontal count of the currently displayed
-- - pixel (even if not in visible area)
-- vcount - output pin, 11 bits, to clients
-- - vertical count of the currently active video
-- - line (even if not in visible area)
-- blank - output pin, to clients
-- - active when pixel is not in visible area.
------------------------------------------------------------------------
-- Revision History:
-- 09/18/2006(UlrichZ): created
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- simulation library
library UNISIM;
use UNISIM.VComponents.all;
-- the vga_controller_640_60 entity declaration
-- read above for behavioral description and port definitions.
entity vga_controller_640_60 is
port(
rst : in std_logic;
pixel_clk : in std_logic;
HS : out std_logic;
VS : out std_logic;
hcount : out std_logic_vector(10 downto 0);
vcount : out std_logic_vector(10 downto 0);
hchar : out std_logic_vector(10 downto 0);
vchar : out std_logic_vector(10 downto 0);
hpixel : out std_logic_vector(5 downto 0);
vpixel : out std_logic_vector(5 downto 0);
blank : out std_logic
);
end vga_controller_640_60;
architecture Behavioral of vga_controller_640_60 is
------------------------------------------------------------------------
-- CONSTANTS
------------------------------------------------------------------------
-- number of horizontal pixels per character
constant HPIX : std_logic_vector(5 downto 0) := "010011"; -- 19
-- number of vertical pixels per character
constant VPIX : std_logic_vector(5 downto 0) := "010011"; -- 19
-- maximum value for the horizontal pixel counter
constant HMAX : std_logic_vector(10 downto 0) := "01100100000"; -- 800
-- maximum value for the vertical pixel counter
constant VMAX : std_logic_vector(10 downto 0) := "01000001101"; -- 525
-- total number of visible columns
constant HLINES: std_logic_vector(10 downto 0) := "01010000000"; -- 640
-- value for the horizontal counter where front porch ends
constant HFP : std_logic_vector(10 downto 0) := "01010001000"; -- 648
-- value for the horizontal counter where the synch pulse ends
constant HSP : std_logic_vector(10 downto 0) := "01011101000"; -- 744
-- total number of visible lines
constant VLINES: std_logic_vector(10 downto 0) := "00111100000"; -- 480
-- value for the vertical counter where the front porch ends
constant VFP : std_logic_vector(10 downto 0) := "00111100010"; -- 482
-- value for the vertical counter where the synch pulse ends
constant VSP : std_logic_vector(10 downto 0) := "00111100100"; -- 484
-- polarity of the horizontal and vertical synch pulse
-- only one polarity used, because for this resolution they coincide.
constant SPP : std_logic := '0';
------------------------------------------------------------------------
-- SIGNALS
------------------------------------------------------------------------
-- horizontal and vertical counters
signal hcounter : std_logic_vector(10 downto 0) := (others => '0');
signal vcounter : std_logic_vector(10 downto 0) := (others => '0');
signal hch : std_logic_vector(10 downto 0) := (others => '0');
signal vch : std_logic_vector(10 downto 0) := (others => '0');
signal hpx : std_logic_vector(5 downto 0) := (others => '0');
signal vpx : std_logic_vector(5 downto 0) := (others => '0');
-- active when inside visible screen area.
signal video_enable: std_logic;
begin
-- output horizontal and vertical counters
hcount <= hcounter;
vcount <= vcounter;
hpixel <= hpx;
vpixel <= vpx;
hchar <= hch;
vchar <= vch;
-- blank is active when outside screen visible area
-- color output should be blacked (put on 0) when blank in active
-- blank is delayed one pixel clock period from the video_enable
-- signal to account for the pixel pipeline delay.
blank <= not video_enable when rising_edge(pixel_clk);
-- increment horizontal counter at pixel_clk rate
-- until HMAX is reached, then reset and keep counting
h_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
hcounter <= (others => '0');
hch <= (others => '0');
hpx <= (others => '0');
elsif(hcounter = HMAX) then
hcounter <= (others => '0');
hch <= (others => '0');
hpx <= (others => '0');
else
hcounter <= hcounter + 1;
if(hpx=HPIX) then
hpx <= (others => '0');
hch <= hch + 1;
else
hpx <= hpx + 1;
end if;
end if;
end if;
end process h_count;
-- increment vertical counter when one line is finished
-- (horizontal counter reached HMAX)
-- until VMAX is reached, then reset and keep counting
v_count: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(rst = '1') then
vcounter <= (others => '0');
vch <= (others => '0');
vpx <= (others => '0');
elsif(hcounter = HMAX) then
if(vcounter = VMAX) then
vcounter <= (others => '0');
vch <= (others => '0');
vpx <= (others => '0');
else
vcounter <= vcounter + 1;
if(vpx=VPIX) then
vpx <= (others => '0');
vch <= vch + 1;
else
vpx <= vpx + 1;
end if;
end if;
end if;
end if;
end process v_count;
-- generate horizontal synch pulse
-- when horizontal counter is between where the
-- front porch ends and the synch pulse ends.
-- The HS is active (with polarity SPP) for a total of 96 pixels.
do_hs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(hcounter >= HFP and hcounter < HSP) then
HS <= SPP;
else
HS <= not SPP;
end if;
end if;
end process do_hs;
-- generate vertical synch pulse
-- when vertical counter is between where the
-- front porch ends and the synch pulse ends.
-- The VS is active (with polarity SPP) for a total of 2 video lines
-- = 2*HMAX = 1600 pixels.
do_vs: process(pixel_clk)
begin
if(rising_edge(pixel_clk)) then
if(vcounter >= VFP and vcounter < VSP) then
VS <= SPP;
else
VS <= not SPP;
end if;
end if;
end process do_vs;
-- enable video output when pixel is in visible area
video_enable <= '1' when (hcounter < HLINES and vcounter < VLINES) else '0';
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
entity ent is
end;
architecture a of ent is
function count_ones(vec : std_logic_vector) return natural is
variable temp : natural := 0;
begin
for i in vec'range loop
if vec(i) then
temp := temp + 1;
end if;
end loop;
return temp;
end count_ones;
constant test : natural := count_ones("10101");
begin
end;
|
library ieee;
use ieee.std_logic_1164.all;
entity ent is
port (
o : out std_logic
);
end;
architecture a of ent is
begin
gen: if false generate
o <= '1';
else generate
o <= '0';
end generate;
end;
|
entity tb_anon01 is
end tb_anon01;
architecture behav of tb_anon01 is
signal i, o : bit_vector(6 downto 0);
begin
dut: entity work.anon01
port map (i, o);
process
begin
i <= b"000_0000";
wait for 1 ns;
assert o = b"010_0101" severity failure;
i <= b"111_1111";
wait for 1 ns;
assert o = b"101_1010" severity failure;
wait;
end process;
end behav;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2.1 (win64) Build 1957588 Wed Aug 9 16:32:24 MDT 2017
-- Date : Fri Sep 22 14:40:47 2017
-- Host : EffulgentTome running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ zqynq_lab_1_design_auto_pc_2_sim_netlist.vhdl
-- Design : zqynq_lab_1_design_auto_pc_2
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
axaddr_incr_reg : out STD_LOGIC_VECTOR ( 7 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
\axlen_cnt_reg[4]_0\ : out STD_LOGIC;
\m_axi_awaddr[1]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 9 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr[4]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5_n_0\ : STD_LOGIC;
signal \^axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1_n_7\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_4_n_0\ : STD_LOGIC;
signal \^axlen_cnt_reg[7]_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 7 downto 2 );
signal \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2\ : label is "soft_lutpair113";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_3\ : label is "soft_lutpair113";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
axaddr_incr_reg(7 downto 0) <= \^axaddr_incr_reg\(7 downto 0);
\axaddr_incr_reg[11]_0\ <= \^axaddr_incr_reg[11]_0\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axlen_cnt_reg[7]_0\ <= \^axlen_cnt_reg[7]_0\;
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"559AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000AAAA559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000559AAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(4),
I5 => \m_payload_i_reg[51]\(5),
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"000000000000559A"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \state_reg[1]\(0),
I2 => \state_reg[1]\(1),
I3 => \state_reg[0]_rep\,
I4 => \m_payload_i_reg[51]\(5),
I5 => \m_payload_i_reg[51]\(4),
O => S(0)
);
\axaddr_incr[4]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(3),
O => \axaddr_incr[4]_i_2_n_0\
);
\axaddr_incr[4]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(2),
O => \axaddr_incr[4]_i_3_n_0\
);
\axaddr_incr[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(1),
O => \axaddr_incr[4]_i_4_n_0\
);
\axaddr_incr[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(0),
O => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr[8]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(7),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(7),
O => \axaddr_incr[8]_i_2_n_0\
);
\axaddr_incr[8]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(6),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(6),
O => \axaddr_incr[8]_i_3_n_0\
);
\axaddr_incr[8]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(5),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(5),
O => \axaddr_incr[8]_i_4_n_0\
);
\axaddr_incr[8]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(4),
I1 => \^axaddr_incr_reg[11]_0\,
I2 => \^axaddr_incr_reg\(4),
O => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_5\,
Q => \^axaddr_incr_reg\(6),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_4\,
Q => \^axaddr_incr_reg\(7),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_7\,
Q => \^axaddr_incr_reg\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1_n_7\,
S(3) => \axaddr_incr[4]_i_2_n_0\,
S(2) => \axaddr_incr[4]_i_3_n_0\,
S(1) => \axaddr_incr[4]_i_4_n_0\,
S(0) => \axaddr_incr[4]_i_5_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_6\,
Q => \^axaddr_incr_reg\(1),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_5\,
Q => \^axaddr_incr_reg\(2),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1_n_4\,
Q => \^axaddr_incr_reg\(3),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_7\,
Q => \^axaddr_incr_reg\(4),
R => '0'
);
\axaddr_incr_reg[8]_i_1\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1_n_7\,
S(3) => \axaddr_incr[8]_i_2_n_0\,
S(2) => \axaddr_incr[8]_i_3_n_0\,
S(1) => \axaddr_incr[8]_i_4_n_0\,
S(0) => \axaddr_incr[8]_i_5_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1_n_6\,
Q => \^axaddr_incr_reg\(5),
R => '0'
);
\axlen_cnt[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(7),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => p_1_in(2)
);
\axlen_cnt[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1_n_0\
);
\axlen_cnt[4]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt_reg[4]_0\
);
\axlen_cnt[6]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \^q\(3),
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(8),
O => p_1_in(6)
);
\axlen_cnt[7]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA900A900A900"
)
port map (
I0 => \axlen_cnt_reg_n_0_[7]\,
I1 => \^axlen_cnt_reg[7]_0\,
I2 => \axlen_cnt[7]_i_4_n_0\,
I3 => \state_reg[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[51]\(9),
O => p_1_in(7)
);
\axlen_cnt[7]_i_3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^q\(2),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \^axlen_cnt_reg[7]_0\
);
\axlen_cnt[7]_i_4\: unisim.vcomponents.LUT2
generic map(
INIT => X"E"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \^q\(3),
O => \axlen_cnt[7]_i_4_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(2),
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(2),
Q => \^q\(2),
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(3),
Q => \^q\(3),
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(6),
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => p_1_in(7),
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_awaddr[1]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_0\,
I1 => \^axaddr_incr_reg[3]_0\(1),
I2 => \m_payload_i_reg[51]\(6),
I3 => \m_payload_i_reg[51]\(1),
O => \m_axi_awaddr[1]\
);
next_pending_r_i_3: unisim.vcomponents.LUT6
generic map(
INIT => X"0000000000000001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[7]\,
I2 => \^q\(2),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \^q\(1),
I5 => \axlen_cnt[7]_i_4_n_0\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_0\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
port (
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_incr_reg[11]_1\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_1 : out STD_LOGIC;
\m_axi_araddr[5]\ : out STD_LOGIC;
\m_axi_araddr[2]\ : out STD_LOGIC;
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_0 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_1 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 : entity is "axi_protocol_converter_v2_1_13_b2s_incr_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2 is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \axaddr_incr[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_5__0_n_0\ : STD_LOGIC;
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 5 to 5 );
signal \^axaddr_incr_reg[11]_0\ : STD_LOGIC_VECTOR ( 6 downto 0 );
signal \^axaddr_incr_reg[11]_1\ : STD_LOGIC;
signal \^axaddr_incr_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_1__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_1__0_n_7\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__1_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[4]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[5]_i_2_n_0\ : STD_LOGIC;
signal \axlen_cnt[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[4]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[5]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[6]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[7]\ : STD_LOGIC;
signal \next_pending_r_i_4__0_n_0\ : STD_LOGIC;
signal \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axlen_cnt[4]_i_2__0\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \axlen_cnt[5]_i_2\ : label is "soft_lutpair4";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_incr_reg[11]_0\(6 downto 0) <= \^axaddr_incr_reg[11]_0\(6 downto 0);
\axaddr_incr_reg[11]_1\ <= \^axaddr_incr_reg[11]_1\;
\axaddr_incr_reg[3]_0\(3 downto 0) <= \^axaddr_incr_reg[3]_0\(3 downto 0);
\axaddr_incr[0]_i_15\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA6AAAAAAAAAAAAA"
)
port map (
I0 => \m_payload_i_reg[51]\(3),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(3)
);
\axaddr_incr[0]_i_16\: unisim.vcomponents.LUT6
generic map(
INIT => X"2A262A2A2A2A2A2A"
)
port map (
I0 => \m_payload_i_reg[51]\(2),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(2)
);
\axaddr_incr[0]_i_17\: unisim.vcomponents.LUT6
generic map(
INIT => X"0A060A0A0A0A0A0A"
)
port map (
I0 => \m_payload_i_reg[51]\(1),
I1 => \m_payload_i_reg[51]\(5),
I2 => \m_payload_i_reg[51]\(6),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(1)
);
\axaddr_incr[0]_i_18\: unisim.vcomponents.LUT6
generic map(
INIT => X"0201020202020202"
)
port map (
I0 => \m_payload_i_reg[51]\(0),
I1 => \m_payload_i_reg[51]\(6),
I2 => \m_payload_i_reg[51]\(5),
I3 => \state_reg[1]\(1),
I4 => \state_reg[1]\(0),
I5 => m_axi_arready,
O => S(0)
);
\axaddr_incr[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(2),
O => \axaddr_incr[4]_i_2__0_n_0\
);
\axaddr_incr[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(1),
O => \axaddr_incr[4]_i_3__0_n_0\
);
\axaddr_incr[4]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => axaddr_incr_reg(5),
O => \axaddr_incr[4]_i_4__0_n_0\
);
\axaddr_incr[4]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[3]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(0),
O => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr[8]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(3),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(6),
O => \axaddr_incr[8]_i_2__0_n_0\
);
\axaddr_incr[8]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(2),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(5),
O => \axaddr_incr[8]_i_3__0_n_0\
);
\axaddr_incr[8]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(1),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(4),
O => \axaddr_incr[8]_i_4__0_n_0\
);
\axaddr_incr[8]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \m_payload_i_reg[11]\(0),
I1 => \^axaddr_incr_reg[11]_1\,
I2 => \^axaddr_incr_reg[11]_0\(3),
O => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(0),
Q => \^axaddr_incr_reg[3]_0\(0),
R => '0'
);
\axaddr_incr_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(5),
R => '0'
);
\axaddr_incr_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(6),
R => '0'
);
\axaddr_incr_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(1),
Q => \^axaddr_incr_reg[3]_0\(1),
R => '0'
);
\axaddr_incr_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(2),
Q => \^axaddr_incr_reg[3]_0\(2),
R => '0'
);
\axaddr_incr_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => O(3),
Q => \^axaddr_incr_reg[3]_0\(3),
R => '0'
);
\axaddr_incr_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(0),
R => '0'
);
\axaddr_incr_reg[4]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => CO(0),
CO(3) => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[4]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[4]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[4]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[4]_i_1__0_n_7\,
S(3) => \axaddr_incr[4]_i_2__0_n_0\,
S(2) => \axaddr_incr[4]_i_3__0_n_0\,
S(1) => \axaddr_incr[4]_i_4__0_n_0\,
S(0) => \axaddr_incr[4]_i_5__0_n_0\
);
\axaddr_incr_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_6\,
Q => axaddr_incr_reg(5),
R => '0'
);
\axaddr_incr_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_5\,
Q => \^axaddr_incr_reg[11]_0\(1),
R => '0'
);
\axaddr_incr_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[4]_i_1__0_n_4\,
Q => \^axaddr_incr_reg[11]_0\(2),
R => '0'
);
\axaddr_incr_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_7\,
Q => \^axaddr_incr_reg[11]_0\(3),
R => '0'
);
\axaddr_incr_reg[8]_i_1__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_1__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_1__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_1__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_1__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_1__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_incr_reg[8]_i_1__0_n_4\,
O(2) => \axaddr_incr_reg[8]_i_1__0_n_5\,
O(1) => \axaddr_incr_reg[8]_i_1__0_n_6\,
O(0) => \axaddr_incr_reg[8]_i_1__0_n_7\,
S(3) => \axaddr_incr[8]_i_2__0_n_0\,
S(2) => \axaddr_incr[8]_i_3__0_n_0\,
S(1) => \axaddr_incr[8]_i_4__0_n_0\,
S(0) => \axaddr_incr[8]_i_5__0_n_0\
);
\axaddr_incr_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => sel_first_reg_0,
D => \axaddr_incr_reg[8]_i_1__0_n_6\,
Q => \^axaddr_incr_reg[11]_0\(4),
R => '0'
);
\axlen_cnt[2]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(8),
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => \^q\(0),
I4 => \^q\(1),
I5 => \state_reg[0]\,
O => \axlen_cnt[2]_i_1__1_n_0\
);
\axlen_cnt[3]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAA90000FFFFFFFF"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => \state_reg[0]\,
I5 => \m_payload_i_reg[47]\,
O => \axlen_cnt[3]_i_1__1_n_0\
);
\axlen_cnt[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt[4]_i_2__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(9),
O => \axlen_cnt[4]_i_1__0_n_0\
);
\axlen_cnt[4]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[4]_i_2__0_n_0\
);
\axlen_cnt[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt[5]_i_2_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(10),
O => \axlen_cnt[5]_i_1__0_n_0\
);
\axlen_cnt[5]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \^q\(0),
I3 => \^q\(1),
I4 => \axlen_cnt_reg_n_0_[3]\,
O => \axlen_cnt[5]_i_2_n_0\
);
\axlen_cnt[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF909090"
)
port map (
I0 => \axlen_cnt_reg_n_0_[6]\,
I1 => \axlen_cnt[7]_i_3__0_n_0\,
I2 => \state_reg[0]\,
I3 => E(0),
I4 => \m_payload_i_reg[51]\(11),
O => \axlen_cnt[6]_i_1__0_n_0\
);
\axlen_cnt[7]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F8F8F88F88888888"
)
port map (
I0 => E(0),
I1 => \m_payload_i_reg[51]\(12),
I2 => \axlen_cnt_reg_n_0_[7]\,
I3 => \axlen_cnt[7]_i_3__0_n_0\,
I4 => \axlen_cnt_reg_n_0_[6]\,
I5 => \state_reg[0]\,
O => \axlen_cnt[7]_i_2__0_n_0\
);
\axlen_cnt[7]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFFE"
)
port map (
I0 => \axlen_cnt_reg_n_0_[5]\,
I1 => \axlen_cnt_reg_n_0_[3]\,
I2 => \^q\(1),
I3 => \^q\(0),
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[4]\,
O => \axlen_cnt[7]_i_3__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(0),
Q => \^q\(0),
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => D(1),
Q => \^q\(1),
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__1_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\axlen_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[4]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[4]\,
R => '0'
);
\axlen_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[5]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[5]\,
R => '0'
);
\axlen_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[6]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[6]\,
R => '0'
);
\axlen_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[7]_i_2__0_n_0\,
Q => \axlen_cnt_reg_n_0_[7]\,
R => '0'
);
\m_axi_araddr[2]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => \^axaddr_incr_reg[3]_0\(2),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(2),
O => \m_axi_araddr[2]\
);
\m_axi_araddr[5]_INST_0_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EF40"
)
port map (
I0 => \^axaddr_incr_reg[11]_1\,
I1 => axaddr_incr_reg(5),
I2 => \m_payload_i_reg[51]\(7),
I3 => \m_payload_i_reg[51]\(4),
O => \m_axi_araddr[5]\
);
\next_pending_r_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \axlen_cnt_reg_n_0_[4]\,
I1 => \axlen_cnt_reg_n_0_[5]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \next_pending_r_i_4__0_n_0\,
O => next_pending_r_reg_1
);
\next_pending_r_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(1),
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[6]\,
I3 => \axlen_cnt_reg_n_0_[7]\,
O => \next_pending_r_i_4__0_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => incr_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^axaddr_incr_reg[11]_1\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
port (
\axlen_cnt_reg[1]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
r_push_r_reg : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
\axlen_cnt_reg[1]_0\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\axaddr_wrap_reg[11]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_payload_i_reg[0]_1\ : out STD_LOGIC_VECTOR ( 0 to 0 );
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\axlen_cnt_reg[4]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[1]_1\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_second_len_r_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_next_pending : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[1]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first_i\ : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1__0\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__0\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of r_push_r_i_1 : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \s_axburst_eq0_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \s_axburst_eq1_i_1__0\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \state[1]_i_1\ : label is "soft_lutpair0";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1__0\ : label is "soft_lutpair2";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[1]\ <= \^axlen_cnt_reg[1]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first_i <= \^sel_first_i\;
wrap_second_len(0) <= \^wrap_second_len\(0);
\axaddr_incr[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AAEA"
)
port map (
I0 => sel_first_reg_2,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[47]\(3),
I2 => \^m_payload_i_reg[0]_0\,
I3 => si_rs_arvalid,
I4 => \^m_payload_i_reg[0]\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_arvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[47]\(1),
I4 => \axlen_cnt_reg[1]_1\(0),
I5 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(0)
);
\axlen_cnt[1]_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[47]\(2),
I2 => \axlen_cnt_reg[1]_1\(1),
I3 => \axlen_cnt_reg[1]_1\(0),
I4 => \^axlen_cnt_reg[1]\,
O => \axlen_cnt_reg[1]_0\(1)
);
\axlen_cnt[7]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00CA"
)
port map (
I0 => si_rs_arvalid,
I1 => m_axi_arready,
I2 => \^m_payload_i_reg[0]_0\,
I3 => \^m_payload_i_reg[0]\,
O => \axaddr_wrap_reg[11]\(0)
);
\axlen_cnt[7]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_arvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[4]\,
O => \^axlen_cnt_reg[1]\
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^m_payload_i_reg[0]_0\,
I1 => \^m_payload_i_reg[0]\,
O => m_axi_arvalid
);
\m_payload_i[31]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"D5"
)
port map (
I0 => si_rs_arvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^m_payload_i_reg[0]_0\,
O => \m_payload_i_reg[0]_1\(0)
);
\next_pending_r_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[51]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[4]\,
I3 => \^r_push_r_reg\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
r_push_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"40"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \^m_payload_i_reg[0]_0\,
I2 => m_axi_arready,
O => \^r_push_r_reg\
);
\s_axburst_eq0_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
\s_axburst_eq1_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => wrap_next_pending,
I1 => \m_payload_i_reg[47]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
\sel_first_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FCFFFFFFCCCECCCE"
)
port map (
I0 => si_rs_arvalid,
I1 => areset_d1,
I2 => \^m_payload_i_reg[0]\,
I3 => \^m_payload_i_reg[0]_0\,
I4 => m_axi_arready,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__4\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFC4C4CFCC"
)
port map (
I0 => m_axi_arready,
I1 => sel_first_reg_3,
I2 => \^q\(1),
I3 => si_rs_arvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"003030303E3E3E3E"
)
port map (
I0 => si_rs_arvalid,
I1 => \^q\(1),
I2 => \^q\(0),
I3 => m_axi_arready,
I4 => s_axburst_eq1_reg_0,
I5 => \cnt_read_reg[2]_rep__0\,
O => next_state(0)
);
\state[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"00AAB000"
)
port map (
I0 => \cnt_read_reg[2]_rep__0\,
I1 => s_axburst_eq1_reg_0,
I2 => m_axi_arready,
I3 => \^m_payload_i_reg[0]_0\,
I4 => \^m_payload_i_reg[0]\,
O => next_state(1)
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^m_payload_i_reg[0]_0\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(1),
Q => \^m_payload_i_reg[0]\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_arvalid,
I2 => \^m_payload_i_reg[0]_0\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]\(0),
I1 => axaddr_offset(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => axaddr_offset(0),
I4 => axaddr_offset(1),
I5 => \^e\(0),
O => \^wrap_second_len\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
port (
\cnt_read_reg[0]_rep__0_0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1_0\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[0]_0\ : out STD_LOGIC;
sel : out STD_LOGIC;
SR : out STD_LOGIC_VECTOR ( 0 to 0 );
bvalid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
b_push : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
\bresp_cnt_reg[7]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
mhandshake_r : in STD_LOGIC;
bvalid_i_reg_0 : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo is
signal bvalid_i_i_2_n_0 : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[0]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_0\ : STD_LOGIC;
signal \^cnt_read_reg[0]_rep__0_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[1]_rep__1_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_3_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_4_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_5_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_i_6_n_0\ : STD_LOGIC;
signal \memory_reg[3][0]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][1]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][2]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][3]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][4]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][5]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][6]_srl4_n_0\ : STD_LOGIC;
signal \memory_reg[3][7]_srl4_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_1\ : label is "soft_lutpair115";
attribute SOFT_HLUTNM of bvalid_i_i_1 : label is "soft_lutpair115";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1\ : label is "soft_lutpair117";
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__2\ : label is "soft_lutpair116";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1\ : label is "soft_lutpair116";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][0]_srl4 ";
attribute SOFT_HLUTNM of \memory_reg[3][0]_srl4_i_1__0\ : label is "soft_lutpair117";
attribute srl_bus_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][10]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][10]_srl4 ";
attribute srl_bus_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][11]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][11]_srl4 ";
attribute srl_bus_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][12]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][12]_srl4 ";
attribute srl_bus_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][13]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][13]_srl4 ";
attribute srl_bus_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][14]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][14]_srl4 ";
attribute srl_bus_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][15]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][15]_srl4 ";
attribute srl_bus_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][16]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][16]_srl4 ";
attribute srl_bus_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][17]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][17]_srl4 ";
attribute srl_bus_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][18]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][18]_srl4 ";
attribute srl_bus_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][19]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][19]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][1]_srl4 ";
attribute srl_bus_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][2]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][2]_srl4 ";
attribute srl_bus_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][3]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][3]_srl4 ";
attribute srl_bus_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][4]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][4]_srl4 ";
attribute srl_bus_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][5]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][5]_srl4 ";
attribute srl_bus_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][6]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][6]_srl4 ";
attribute srl_bus_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][7]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][7]_srl4 ";
attribute srl_bus_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][8]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][8]_srl4 ";
attribute srl_bus_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][9]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bid_fifo_0/memory_reg[3][9]_srl4 ";
begin
\cnt_read_reg[0]_0\ <= \^cnt_read_reg[0]_0\;
\cnt_read_reg[0]_rep__0_0\ <= \^cnt_read_reg[0]_rep__0_0\;
\cnt_read_reg[1]_rep__1_0\ <= \^cnt_read_reg[1]_rep__1_0\;
\bresp_cnt[7]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => areset_d1,
I1 => \^cnt_read_reg[0]_0\,
O => SR(0)
);
bvalid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"002A"
)
port map (
I0 => bvalid_i_i_2_n_0,
I1 => bvalid_i_reg_0,
I2 => si_rs_bready,
I3 => areset_d1,
O => bvalid_i_reg
);
bvalid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF00070707"
)
port map (
I0 => \^cnt_read_reg[1]_rep__1_0\,
I1 => \^cnt_read_reg[0]_rep__0_0\,
I2 => shandshake_r,
I3 => Q(1),
I4 => Q(0),
I5 => bvalid_i_reg_0,
O => bvalid_i_i_2_n_0
);
\cnt_read[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"69"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
I1 => shandshake_r,
I2 => Q(0),
O => D(0)
);
\cnt_read[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
O => \cnt_read[0]_i_1__2_n_0\
);
\cnt_read[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"E718"
)
port map (
I0 => \^cnt_read_reg[0]_rep__0_0\,
I1 => b_push,
I2 => shandshake_r,
I3 => \^cnt_read_reg[1]_rep__1_0\,
O => \cnt_read[1]_i_1_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__2_n_0\,
Q => \^cnt_read_reg[0]_rep__0_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1_n_0\,
Q => \^cnt_read_reg[1]_rep__1_0\,
S => areset_d1
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(0),
Q => \memory_reg[3][0]_srl4_n_0\
);
\memory_reg[3][0]_srl4_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^cnt_read_reg[0]_0\,
O => sel
);
\memory_reg[3][0]_srl4_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFEFFFFFFFFFFFE"
)
port map (
I0 => \memory_reg[3][0]_srl4_i_3_n_0\,
I1 => \memory_reg[3][0]_srl4_i_4_n_0\,
I2 => \memory_reg[3][0]_srl4_i_5_n_0\,
I3 => \memory_reg[3][0]_srl4_i_6_n_0\,
I4 => \bresp_cnt_reg[7]\(3),
I5 => \memory_reg[3][3]_srl4_n_0\,
O => \^cnt_read_reg[0]_0\
);
\memory_reg[3][0]_srl4_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"22F2FFFFFFFF22F2"
)
port map (
I0 => \memory_reg[3][0]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(0),
I2 => \memory_reg[3][2]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(2),
I4 => \memory_reg[3][1]_srl4_n_0\,
I5 => \bresp_cnt_reg[7]\(1),
O => \memory_reg[3][0]_srl4_i_3_n_0\
);
\memory_reg[3][0]_srl4_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"F222FFFFFFFFF222"
)
port map (
I0 => \bresp_cnt_reg[7]\(5),
I1 => \memory_reg[3][5]_srl4_n_0\,
I2 => \^cnt_read_reg[1]_rep__1_0\,
I3 => \^cnt_read_reg[0]_rep__0_0\,
I4 => \bresp_cnt_reg[7]\(7),
I5 => \memory_reg[3][7]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_4_n_0\
);
\memory_reg[3][0]_srl4_i_5\: unisim.vcomponents.LUT6
generic map(
INIT => X"2FF22FF2FFFF2FF2"
)
port map (
I0 => \bresp_cnt_reg[7]\(2),
I1 => \memory_reg[3][2]_srl4_n_0\,
I2 => \memory_reg[3][4]_srl4_n_0\,
I3 => \bresp_cnt_reg[7]\(4),
I4 => \bresp_cnt_reg[7]\(0),
I5 => \memory_reg[3][0]_srl4_n_0\,
O => \memory_reg[3][0]_srl4_i_5_n_0\
);
\memory_reg[3][0]_srl4_i_6\: unisim.vcomponents.LUT5
generic map(
INIT => X"6F6FFF6F"
)
port map (
I0 => \memory_reg[3][6]_srl4_n_0\,
I1 => \bresp_cnt_reg[7]\(6),
I2 => mhandshake_r,
I3 => \memory_reg[3][5]_srl4_n_0\,
I4 => \bresp_cnt_reg[7]\(5),
O => \memory_reg[3][0]_srl4_i_6_n_0\
);
\memory_reg[3][10]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(10),
Q => \out\(2)
);
\memory_reg[3][11]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(11),
Q => \out\(3)
);
\memory_reg[3][12]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(12),
Q => \out\(4)
);
\memory_reg[3][13]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(13),
Q => \out\(5)
);
\memory_reg[3][14]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(14),
Q => \out\(6)
);
\memory_reg[3][15]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(15),
Q => \out\(7)
);
\memory_reg[3][16]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(16),
Q => \out\(8)
);
\memory_reg[3][17]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(17),
Q => \out\(9)
);
\memory_reg[3][18]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(18),
Q => \out\(10)
);
\memory_reg[3][19]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => cnt_read(0),
A1 => cnt_read(1),
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(19),
Q => \out\(11)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(1),
Q => \memory_reg[3][1]_srl4_n_0\
);
\memory_reg[3][2]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(2),
Q => \memory_reg[3][2]_srl4_n_0\
);
\memory_reg[3][3]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(3),
Q => \memory_reg[3][3]_srl4_n_0\
);
\memory_reg[3][4]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(4),
Q => \memory_reg[3][4]_srl4_n_0\
);
\memory_reg[3][5]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep__0_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(5),
Q => \memory_reg[3][5]_srl4_n_0\
);
\memory_reg[3][6]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(6),
Q => \memory_reg[3][6]_srl4_n_0\
);
\memory_reg[3][7]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(7),
Q => \memory_reg[3][7]_srl4_n_0\
);
\memory_reg[3][8]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(8),
Q => \out\(0)
);
\memory_reg[3][9]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \cnt_read_reg[0]_rep_n_0\,
A1 => \cnt_read_reg[1]_rep_n_0\,
A2 => '0',
A3 => '0',
CE => b_push,
CLK => aclk,
D => \in\(9),
Q => \out\(1)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
port (
mhandshake : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bready : out STD_LOGIC;
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
mhandshake_r : in STD_LOGIC;
shandshake_r : in STD_LOGIC;
\bresp_cnt_reg[3]\ : in STD_LOGIC;
sel : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\ is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \cnt_read[1]_i_1__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__0\ : label is "soft_lutpair118";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute SOFT_HLUTNM of m_axi_bready_INST_0 : label is "soft_lutpair118";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[3][0]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][0]_srl4 ";
attribute srl_bus_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3] ";
attribute srl_name of \memory_reg[3][1]_srl4\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/WR.b_channel_0/bresp_fifo_0/memory_reg[3][1]_srl4 ";
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\cnt_read[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \^q\(1),
I1 => shandshake_r,
I2 => \^q\(0),
I3 => \bresp_cnt_reg[3]\,
O => \cnt_read[1]_i_1__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => D(0),
Q => \^q\(0),
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__0_n_0\,
Q => \^q\(1),
S => areset_d1
);
m_axi_bready_INST_0: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => mhandshake_r,
O => m_axi_bready
);
\memory_reg[3][0]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[1]\(0)
);
\memory_reg[3][1]_srl4\: unisim.vcomponents.SRL16E
generic map(
INIT => X"0000"
)
port map (
A0 => \^q\(0),
A1 => \^q\(1),
A2 => '0',
A3 => '0',
CE => sel,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[1]\(1)
);
mhandshake_r_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"2000"
)
port map (
I0 => m_axi_bvalid,
I1 => mhandshake_r,
I2 => \^q\(0),
I3 => \^q\(1),
O => mhandshake
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
port (
\cnt_read_reg[3]_rep__2_0\ : out STD_LOGIC;
wr_en0 : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2_1\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
s_ready_i_reg : in STD_LOGIC;
s_ready_i_reg_0 : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
\cnt_read_reg[4]_rep__0_0\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__2_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__1_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__2_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[3]_rep__2_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__1_n_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_0\ : STD_LOGIC;
signal \^cnt_read_reg[4]_rep__2_1\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^wr_en0\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__0\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \cnt_read[4]_i_5\ : label is "soft_lutpair9";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__1\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__2\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__1\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__2\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__1\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__2\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__1\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__2\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__1\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__1\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__1\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__2\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__2\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__2\ : label is "cnt_read_reg[4]";
attribute SOFT_HLUTNM of m_axi_rready_INST_0 : label is "soft_lutpair7";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][13]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][13]_srl32 ";
attribute srl_bus_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][14]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][14]_srl32 ";
attribute srl_bus_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][15]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][15]_srl32 ";
attribute srl_bus_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][16]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][16]_srl32 ";
attribute srl_bus_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][17]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][17]_srl32 ";
attribute srl_bus_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][18]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][18]_srl32 ";
attribute srl_bus_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][19]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][19]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][20]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][20]_srl32 ";
attribute srl_bus_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][21]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][21]_srl32 ";
attribute srl_bus_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][22]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][22]_srl32 ";
attribute srl_bus_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][23]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][23]_srl32 ";
attribute srl_bus_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][24]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][24]_srl32 ";
attribute srl_bus_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][25]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][25]_srl32 ";
attribute srl_bus_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][26]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][26]_srl32 ";
attribute srl_bus_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][27]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][27]_srl32 ";
attribute srl_bus_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][28]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][28]_srl32 ";
attribute srl_bus_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][29]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][29]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][30]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][30]_srl32 ";
attribute srl_bus_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][31]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][31]_srl32 ";
attribute srl_bus_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][32]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][32]_srl32 ";
attribute srl_bus_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][33]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][33]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/rd_data_fifo_0/memory_reg[31][9]_srl32 ";
attribute SOFT_HLUTNM of \state[1]_i_4\ : label is "soft_lutpair7";
begin
\cnt_read_reg[3]_rep__2_0\ <= \^cnt_read_reg[3]_rep__2_0\;
\cnt_read_reg[4]_rep__2_0\ <= \^cnt_read_reg[4]_rep__2_0\;
\cnt_read_reg[4]_rep__2_1\ <= \^cnt_read_reg[4]_rep__2_1\;
wr_en0 <= \^wr_en0\;
\cnt_read[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => s_ready_i_reg,
I2 => \^wr_en0\,
O => \cnt_read[0]_i_1__0_n_0\
);
\cnt_read[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"A96A"
)
port map (
I0 => \cnt_read_reg[1]_rep__2_n_0\,
I1 => \cnt_read_reg[0]_rep__2_n_0\,
I2 => \^wr_en0\,
I3 => s_ready_i_reg,
O => \cnt_read[1]_i_1__2_n_0\
);
\cnt_read[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"A6AAAA9A"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => s_ready_i_reg,
I3 => \^wr_en0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => \cnt_read[2]_i_1_n_0\
);
\cnt_read[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAAAA96AAAAAAA"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[0]_rep__2_n_0\,
I4 => \^wr_en0\,
I5 => s_ready_i_reg,
O => \cnt_read[3]_i_1_n_0\
);
\cnt_read[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA55AAA6A6AAA6AA"
)
port map (
I0 => \^cnt_read_reg[4]_rep__2_0\,
I1 => \cnt_read[4]_i_2_n_0\,
I2 => \cnt_read[4]_i_3_n_0\,
I3 => s_ready_i_reg_0,
I4 => \^cnt_read_reg[4]_rep__2_1\,
I5 => \^cnt_read_reg[3]_rep__2_0\,
O => \cnt_read[4]_i_1_n_0\
);
\cnt_read[4]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[2]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
O => \cnt_read[4]_i_2_n_0\
);
\cnt_read[4]_i_3\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => si_rs_rready,
I2 => \cnt_read_reg[4]_rep__0_0\,
I3 => \^wr_en0\,
O => \cnt_read[4]_i_3_n_0\
);
\cnt_read[4]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[1]_rep__2_n_0\,
I2 => \cnt_read_reg[2]_rep__2_n_0\,
O => \^cnt_read_reg[4]_rep__2_1\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__0_n_0\,
Q => \cnt_read_reg[0]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__2_n_0\,
Q => \cnt_read_reg[1]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1_n_0\,
Q => \cnt_read_reg[2]_rep__2_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \cnt_read_reg[3]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1_n_0\,
Q => \^cnt_read_reg[3]_rep__2_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__1\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \cnt_read_reg[4]_rep__1_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__2\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1_n_0\,
Q => \^cnt_read_reg[4]_rep__2_0\,
S => areset_d1
);
m_axi_rready_INST_0: unisim.vcomponents.LUT5
generic map(
INIT => X"F77F777F"
)
port map (
I0 => \^cnt_read_reg[3]_rep__2_0\,
I1 => \^cnt_read_reg[4]_rep__2_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \cnt_read_reg[2]_rep__2_n_0\,
I4 => \cnt_read_reg[0]_rep__2_n_0\,
O => m_axi_rready
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(0),
Q => \out\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][0]_srl32_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AA2A2AAA2A2A2AAA"
)
port map (
I0 => m_axi_rvalid,
I1 => \^cnt_read_reg[3]_rep__2_0\,
I2 => \^cnt_read_reg[4]_rep__2_0\,
I3 => \cnt_read_reg[1]_rep__2_n_0\,
I4 => \cnt_read_reg[2]_rep__2_n_0\,
I5 => \cnt_read_reg[0]_rep__2_n_0\,
O => \^wr_en0\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(10),
Q => \out\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(11),
Q => \out\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(12),
Q => \out\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][13]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(13),
Q => \out\(13),
Q31 => \NLW_memory_reg[31][13]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][14]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(14),
Q => \out\(14),
Q31 => \NLW_memory_reg[31][14]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][15]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(15),
Q => \out\(15),
Q31 => \NLW_memory_reg[31][15]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][16]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(16),
Q => \out\(16),
Q31 => \NLW_memory_reg[31][16]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][17]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(17),
Q => \out\(17),
Q31 => \NLW_memory_reg[31][17]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][18]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(18),
Q => \out\(18),
Q31 => \NLW_memory_reg[31][18]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][19]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(19),
Q => \out\(19),
Q31 => \NLW_memory_reg[31][19]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(1),
Q => \out\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][20]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(20),
Q => \out\(20),
Q31 => \NLW_memory_reg[31][20]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][21]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(21),
Q => \out\(21),
Q31 => \NLW_memory_reg[31][21]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][22]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(22),
Q => \out\(22),
Q31 => \NLW_memory_reg[31][22]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][23]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(23),
Q => \out\(23),
Q31 => \NLW_memory_reg[31][23]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][24]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(24),
Q => \out\(24),
Q31 => \NLW_memory_reg[31][24]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][25]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(25),
Q => \out\(25),
Q31 => \NLW_memory_reg[31][25]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][26]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(26),
Q => \out\(26),
Q31 => \NLW_memory_reg[31][26]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][27]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(27),
Q => \out\(27),
Q31 => \NLW_memory_reg[31][27]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][28]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(28),
Q => \out\(28),
Q31 => \NLW_memory_reg[31][28]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][29]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(29),
Q => \out\(29),
Q31 => \NLW_memory_reg[31][29]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(2),
Q => \out\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][30]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(30),
Q => \out\(30),
Q31 => \NLW_memory_reg[31][30]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][31]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(31),
Q => \out\(31),
Q31 => \NLW_memory_reg[31][31]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][32]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(32),
Q => \out\(32),
Q31 => \NLW_memory_reg[31][32]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][33]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => \^wr_en0\,
CLK => aclk,
D => \in\(33),
Q => \out\(33),
Q31 => \NLW_memory_reg[31][33]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(3),
Q => \out\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(4),
Q => \out\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(5),
Q => \out\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__1_n_0\,
A(3) => \cnt_read_reg[3]_rep__1_n_0\,
A(2) => \cnt_read_reg[2]_rep__1_n_0\,
A(1) => \cnt_read_reg[1]_rep__1_n_0\,
A(0) => \cnt_read_reg[0]_rep__1_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(6),
Q => \out\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(7),
Q => \out\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(8),
Q => \out\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep__0_n_0\,
A(3) => \cnt_read_reg[3]_rep__0_n_0\,
A(2) => \cnt_read_reg[2]_rep__0_n_0\,
A(1) => \cnt_read_reg[1]_rep__0_n_0\,
A(0) => \cnt_read_reg[0]_rep__0_n_0\,
CE => \^wr_en0\,
CLK => aclk,
D => \in\(9),
Q => \out\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_4\: unisim.vcomponents.LUT5
generic map(
INIT => X"7C000000"
)
port map (
I0 => \cnt_read_reg[0]_rep__2_n_0\,
I1 => \cnt_read_reg[2]_rep__2_n_0\,
I2 => \cnt_read_reg[1]_rep__2_n_0\,
I3 => \^cnt_read_reg[4]_rep__2_0\,
I4 => \^cnt_read_reg[3]_rep__2_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
\cnt_read_reg[4]_rep__2\ : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
r_push_r : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
\cnt_read_reg[0]_rep__2\ : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
wr_en0 : in STD_LOGIC;
\cnt_read_reg[4]_rep__2_0\ : in STD_LOGIC;
\cnt_read_reg[3]_rep__2\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__2_0\ : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 12 downto 0 );
aclk : in STD_LOGIC;
areset_d1 : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ : entity is "axi_protocol_converter_v2_1_13_b2s_simple_fifo";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\ is
signal cnt_read : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \cnt_read[0]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[1]_i_1__1_n_0\ : STD_LOGIC;
signal \cnt_read[2]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[3]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_1__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_2__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_3__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_4__0_n_0\ : STD_LOGIC;
signal \cnt_read[4]_i_5__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[0]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[1]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[2]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[3]_rep_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep__0_n_0\ : STD_LOGIC;
signal \cnt_read_reg[4]_rep_n_0\ : STD_LOGIC;
signal \^m_valid_i_reg\ : STD_LOGIC;
signal \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
signal \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[0]_i_1__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[1]_i_1__1\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[2]_i_1__0\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \cnt_read[4]_i_2__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \cnt_read[4]_i_3__0\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \cnt_read[4]_i_4__0\ : label is "soft_lutpair11";
attribute KEEP : string;
attribute KEEP of \cnt_read_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \cnt_read_reg[0]\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep\ : label is "cnt_read_reg[0]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[0]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[0]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[0]_rep__0\ : label is "cnt_read_reg[0]";
attribute KEEP of \cnt_read_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep\ : label is "cnt_read_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[1]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[1]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[1]_rep__0\ : label is "cnt_read_reg[1]";
attribute KEEP of \cnt_read_reg[2]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep\ : label is "cnt_read_reg[2]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[2]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[2]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[2]_rep__0\ : label is "cnt_read_reg[2]";
attribute KEEP of \cnt_read_reg[3]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep\ : label is "cnt_read_reg[3]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[3]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[3]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[3]_rep__0\ : label is "cnt_read_reg[3]";
attribute KEEP of \cnt_read_reg[4]\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep\ : label is "cnt_read_reg[4]";
attribute IS_FANOUT_CONSTRAINED of \cnt_read_reg[4]_rep__0\ : label is 1;
attribute KEEP of \cnt_read_reg[4]_rep__0\ : label is "yes";
attribute ORIG_CELL_NAME of \cnt_read_reg[4]_rep__0\ : label is "cnt_read_reg[4]";
attribute srl_bus_name : string;
attribute srl_bus_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name : string;
attribute srl_name of \memory_reg[31][0]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][0]_srl32 ";
attribute srl_bus_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][10]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][10]_srl32 ";
attribute srl_bus_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][11]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][11]_srl32 ";
attribute srl_bus_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][12]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][12]_srl32 ";
attribute srl_bus_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][1]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][1]_srl32 ";
attribute srl_bus_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][2]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][2]_srl32 ";
attribute srl_bus_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][3]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][3]_srl32 ";
attribute srl_bus_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][4]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][4]_srl32 ";
attribute srl_bus_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][5]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][5]_srl32 ";
attribute srl_bus_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][6]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][6]_srl32 ";
attribute srl_bus_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][7]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][7]_srl32 ";
attribute srl_bus_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][8]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][8]_srl32 ";
attribute srl_bus_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31] ";
attribute srl_name of \memory_reg[31][9]_srl32\ : label is "inst/\gen_axilite.gen_b2s_conv.axilite_b2s/RD.r_channel_0/transaction_fifo_0/memory_reg[31][9]_srl32 ";
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\cnt_read[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => s_ready_i_reg,
I2 => r_push_r,
O => \cnt_read[0]_i_1__1_n_0\
);
\cnt_read[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A69A"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[0]_rep__0_n_0\,
I2 => s_ready_i_reg,
I3 => r_push_r,
O => \cnt_read[1]_i_1__1_n_0\
);
\cnt_read[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AA6AA9AA"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => r_push_r,
I3 => s_ready_i_reg,
I4 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[2]_i_1__0_n_0\
);
\cnt_read[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAA6AAAAAA9AAAA"
)
port map (
I0 => \cnt_read_reg[3]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => r_push_r,
I4 => s_ready_i_reg,
I5 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[3]_i_1__0_n_0\
);
\cnt_read[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6A666A6AAA99AAAA"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read[4]_i_2__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read[4]_i_4__0_n_0\,
I4 => \cnt_read[4]_i_5__0_n_0\,
I5 => \cnt_read_reg[3]_rep__0_n_0\,
O => \cnt_read[4]_i_1__0_n_0\
);
\cnt_read[4]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"8A"
)
port map (
I0 => r_push_r,
I1 => \^m_valid_i_reg\,
I2 => si_rs_rready,
O => \cnt_read[4]_i_2__0_n_0\
);
\cnt_read[4]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"80"
)
port map (
I0 => \cnt_read_reg[2]_rep__0_n_0\,
I1 => \cnt_read_reg[1]_rep__0_n_0\,
I2 => \cnt_read_reg[0]_rep__0_n_0\,
O => \cnt_read[4]_i_3__0_n_0\
);
\cnt_read[4]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"4F"
)
port map (
I0 => \^m_valid_i_reg\,
I1 => si_rs_rready,
I2 => wr_en0,
O => \cnt_read_reg[4]_rep__2\
);
\cnt_read[4]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFB"
)
port map (
I0 => \cnt_read_reg[0]_rep__0_n_0\,
I1 => si_rs_rready,
I2 => \^m_valid_i_reg\,
I3 => r_push_r,
O => \cnt_read[4]_i_4__0_n_0\
);
\cnt_read[4]_i_5__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"1"
)
port map (
I0 => \cnt_read_reg[1]_rep__0_n_0\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
O => \cnt_read[4]_i_5__0_n_0\
);
\cnt_read_reg[0]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => cnt_read(0),
S => areset_d1
);
\cnt_read_reg[0]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[0]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[0]_i_1__1_n_0\,
Q => \cnt_read_reg[0]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[1]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => cnt_read(1),
S => areset_d1
);
\cnt_read_reg[1]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[1]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[1]_i_1__1_n_0\,
Q => \cnt_read_reg[1]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[2]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => cnt_read(2),
S => areset_d1
);
\cnt_read_reg[2]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[2]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[2]_i_1__0_n_0\,
Q => \cnt_read_reg[2]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[3]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => cnt_read(3),
S => areset_d1
);
\cnt_read_reg[3]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[3]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[3]_i_1__0_n_0\,
Q => \cnt_read_reg[3]_rep__0_n_0\,
S => areset_d1
);
\cnt_read_reg[4]\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => cnt_read(4),
S => areset_d1
);
\cnt_read_reg[4]_rep\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep_n_0\,
S => areset_d1
);
\cnt_read_reg[4]_rep__0\: unisim.vcomponents.FDSE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \cnt_read[4]_i_1__0_n_0\,
Q => \cnt_read_reg[4]_rep__0_n_0\,
S => areset_d1
);
m_valid_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"FF80808080808080"
)
port map (
I0 => \cnt_read_reg[4]_rep__0_n_0\,
I1 => \cnt_read_reg[3]_rep__0_n_0\,
I2 => \cnt_read[4]_i_3__0_n_0\,
I3 => \cnt_read_reg[4]_rep__2_0\,
I4 => \cnt_read_reg[3]_rep__2\,
I5 => \cnt_read_reg[0]_rep__2_0\,
O => \^m_valid_i_reg\
);
\memory_reg[31][0]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(0),
Q => \skid_buffer_reg[46]\(0),
Q31 => \NLW_memory_reg[31][0]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][10]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(10),
Q => \skid_buffer_reg[46]\(10),
Q31 => \NLW_memory_reg[31][10]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][11]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(11),
Q => \skid_buffer_reg[46]\(11),
Q31 => \NLW_memory_reg[31][11]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][12]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(12),
Q => \skid_buffer_reg[46]\(12),
Q31 => \NLW_memory_reg[31][12]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][1]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(1),
Q => \skid_buffer_reg[46]\(1),
Q31 => \NLW_memory_reg[31][1]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][2]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(2),
Q => \skid_buffer_reg[46]\(2),
Q31 => \NLW_memory_reg[31][2]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][3]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(3),
Q => \skid_buffer_reg[46]\(3),
Q31 => \NLW_memory_reg[31][3]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][4]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(4),
Q => \skid_buffer_reg[46]\(4),
Q31 => \NLW_memory_reg[31][4]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][5]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4) => \cnt_read_reg[4]_rep_n_0\,
A(3) => \cnt_read_reg[3]_rep_n_0\,
A(2) => \cnt_read_reg[2]_rep_n_0\,
A(1) => \cnt_read_reg[1]_rep_n_0\,
A(0) => \cnt_read_reg[0]_rep_n_0\,
CE => r_push_r,
CLK => aclk,
D => \in\(5),
Q => \skid_buffer_reg[46]\(5),
Q31 => \NLW_memory_reg[31][5]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][6]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(6),
Q => \skid_buffer_reg[46]\(6),
Q31 => \NLW_memory_reg[31][6]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][7]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(7),
Q => \skid_buffer_reg[46]\(7),
Q31 => \NLW_memory_reg[31][7]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][8]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(8),
Q => \skid_buffer_reg[46]\(8),
Q31 => \NLW_memory_reg[31][8]_srl32_Q31_UNCONNECTED\
);
\memory_reg[31][9]_srl32\: unisim.vcomponents.SRLC32E
generic map(
INIT => X"00000000"
)
port map (
A(4 downto 0) => cnt_read(4 downto 0),
CE => r_push_r,
CLK => aclk,
D => \in\(9),
Q => \skid_buffer_reg[46]\(9),
Q31 => \NLW_memory_reg[31][9]_srl32_Q31_UNCONNECTED\
);
\state[1]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"BEFEAAAAAAAAAAAA"
)
port map (
I0 => \cnt_read_reg[0]_rep__2\,
I1 => \cnt_read_reg[2]_rep__0_n_0\,
I2 => \cnt_read_reg[1]_rep__0_n_0\,
I3 => \cnt_read_reg[0]_rep__0_n_0\,
I4 => \cnt_read_reg[3]_rep__0_n_0\,
I5 => \cnt_read_reg[4]_rep__0_n_0\,
O => \state_reg[1]_rep\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
port (
\axlen_cnt_reg[4]\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[1]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : out STD_LOGIC;
\state_reg[1]_rep_1\ : out STD_LOGIC;
\axlen_cnt_reg[5]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axburst_eq0_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_i : out STD_LOGIC;
incr_next_pending : out STD_LOGIC;
s_axburst_eq1_reg : out STD_LOGIC;
\next\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\axaddr_wrap_reg[0]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
sel_first_reg : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\axlen_cnt_reg[3]\ : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
s_axburst_eq1_reg_0 : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
\m_payload_i_reg[49]\ : in STD_LOGIC_VECTOR ( 5 downto 0 );
\axlen_cnt_reg[5]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[3]_0\ : in STD_LOGIC;
\axlen_cnt_reg[4]_0\ : in STD_LOGIC;
\wrap_second_len_r_reg[1]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
next_pending_r_reg : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\axlen_cnt_reg[2]\ : in STD_LOGIC;
next_pending_r_reg_0 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
\sel_first__0\ : in STD_LOGIC;
aclk : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axlen_cnt_reg[4]\ : STD_LOGIC;
signal \^incr_next_pending\ : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^next\ : STD_LOGIC;
signal next_state : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^sel_first_i\ : STD_LOGIC;
signal \state[0]_i_2_n_0\ : STD_LOGIC;
signal \state[1]_i_1__0_n_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_0\ : STD_LOGIC;
signal \^state_reg[1]_rep_1\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[1]\ : STD_LOGIC_VECTOR ( 0 to 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_incr[0]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_1\ : label is "soft_lutpair110";
attribute SOFT_HLUTNM of \axlen_cnt[7]_i_5\ : label is "soft_lutpair111";
attribute SOFT_HLUTNM of m_axi_awvalid_INST_0 : label is "soft_lutpair112";
attribute SOFT_HLUTNM of s_axburst_eq0_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of s_axburst_eq1_i_1 : label is "soft_lutpair109";
attribute SOFT_HLUTNM of \state[0]_i_1\ : label is "soft_lutpair111";
attribute KEEP : string;
attribute KEEP of \state_reg[0]\ : label is "yes";
attribute ORIG_CELL_NAME : string;
attribute ORIG_CELL_NAME of \state_reg[0]\ : label is "state_reg[0]";
attribute IS_FANOUT_CONSTRAINED : integer;
attribute IS_FANOUT_CONSTRAINED of \state_reg[0]_rep\ : label is 1;
attribute KEEP of \state_reg[0]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[0]_rep\ : label is "state_reg[0]";
attribute KEEP of \state_reg[1]\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]\ : label is "state_reg[1]";
attribute IS_FANOUT_CONSTRAINED of \state_reg[1]_rep\ : label is 1;
attribute KEEP of \state_reg[1]_rep\ : label is "yes";
attribute ORIG_CELL_NAME of \state_reg[1]_rep\ : label is "state_reg[1]";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[11]_i_1\ : label is "soft_lutpair112";
begin
E(0) <= \^e\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axlen_cnt_reg[4]\ <= \^axlen_cnt_reg[4]\;
incr_next_pending <= \^incr_next_pending\;
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\next\ <= \^next\;
sel_first_i <= \^sel_first_i\;
\state_reg[1]_rep_0\ <= \^state_reg[1]_rep_0\;
\state_reg[1]_rep_1\ <= \^state_reg[1]_rep_1\;
wrap_next_pending <= \^wrap_next_pending\;
\wrap_second_len_r_reg[1]\(0) <= \^wrap_second_len_r_reg[1]\(0);
\axaddr_incr[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"EEFE"
)
port map (
I0 => sel_first_reg_2,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_incr_reg[11]\
);
\axaddr_offset_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAACAAAAAAA0AA"
)
port map (
I0 => \axaddr_offset_r_reg[3]_0\(0),
I1 => \m_payload_i_reg[49]\(3),
I2 => \^state_reg[1]_rep_1\,
I3 => si_rs_awvalid,
I4 => \^state_reg[1]_rep_0\,
I5 => \m_payload_i_reg[6]\,
O => \^axaddr_offset_r_reg[3]\(0)
);
\axlen_cnt[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0400FFFF04000400"
)
port map (
I0 => \^q\(1),
I1 => si_rs_awvalid,
I2 => \^q\(0),
I3 => \m_payload_i_reg[49]\(1),
I4 => \axlen_cnt_reg[5]_0\(0),
I5 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(0)
);
\axlen_cnt[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(2),
I2 => \axlen_cnt_reg[5]_0\(1),
I3 => \axlen_cnt_reg[5]_0\(0),
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(1)
);
\axlen_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(4),
I2 => \axlen_cnt_reg[5]_0\(2),
I3 => \axlen_cnt_reg[3]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(2)
);
\axlen_cnt[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"F88F8888"
)
port map (
I0 => \^e\(0),
I1 => \m_payload_i_reg[49]\(5),
I2 => \axlen_cnt_reg[5]_0\(3),
I3 => \axlen_cnt_reg[4]_0\,
I4 => \^axlen_cnt_reg[4]\,
O => \axlen_cnt_reg[5]\(3)
);
\axlen_cnt[7]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"CCFE"
)
port map (
I0 => si_rs_awvalid,
I1 => \^m_payload_i_reg[0]\,
I2 => \^state_reg[1]_rep_0\,
I3 => \^state_reg[1]_rep_1\,
O => \axaddr_wrap_reg[0]\(0)
);
\axlen_cnt[7]_i_5\: unisim.vcomponents.LUT4
generic map(
INIT => X"00FB"
)
port map (
I0 => \^q\(0),
I1 => si_rs_awvalid,
I2 => \^q\(1),
I3 => \axlen_cnt_reg[3]\,
O => \^axlen_cnt_reg[4]\
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
O => m_axi_awvalid
);
\m_payload_i[31]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => si_rs_awvalid,
O => \m_payload_i_reg[0]_0\(0)
);
\memory_reg[3][0]_srl4_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"88008888A800A8A8"
)
port map (
I0 => \^state_reg[1]_rep_1\,
I1 => \^state_reg[1]_rep_0\,
I2 => m_axi_awready,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => s_axburst_eq1_reg_0,
O => \^m_payload_i_reg[0]\
);
next_pending_r_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[48]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[3]\,
I3 => \^next\,
I4 => next_pending_r_reg,
O => \^incr_next_pending\
);
\next_pending_r_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8BBB8B88"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => \^e\(0),
I2 => \axlen_cnt_reg[2]\,
I3 => \^next\,
I4 => next_pending_r_reg_0,
O => \^wrap_next_pending\
);
next_pending_r_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"F3F35100FFFF0000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \^next\
);
s_axburst_eq0_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"FB08"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq0_reg
);
s_axburst_eq1_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"ABA8"
)
port map (
I0 => \^wrap_next_pending\,
I1 => \m_payload_i_reg[49]\(0),
I2 => \^sel_first_i\,
I3 => \^incr_next_pending\,
O => s_axburst_eq1_reg
);
sel_first_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"CCCEFCFFCCCECCCE"
)
port map (
I0 => si_rs_awvalid,
I1 => areset_d1,
I2 => \^state_reg[1]_rep_1\,
I3 => \^state_reg[1]_rep_0\,
I4 => \^m_payload_i_reg[0]\,
I5 => sel_first_reg_1,
O => \^sel_first_i\
);
\sel_first_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => sel_first_reg_2,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg
);
\sel_first_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFF44440F04"
)
port map (
I0 => \^m_payload_i_reg[0]\,
I1 => \sel_first__0\,
I2 => \^q\(1),
I3 => si_rs_awvalid,
I4 => \^q\(0),
I5 => areset_d1,
O => sel_first_reg_0
);
\state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"2F"
)
port map (
I0 => si_rs_awvalid,
I1 => \^q\(0),
I2 => \state[0]_i_2_n_0\,
O => next_state(0)
);
\state[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FA08FAFA0F0F0F0F"
)
port map (
I0 => m_axi_awready,
I1 => s_axburst_eq1_reg_0,
I2 => \^state_reg[1]_rep_0\,
I3 => \cnt_read_reg[0]_rep__0\,
I4 => \cnt_read_reg[1]_rep__1\,
I5 => \^state_reg[1]_rep_1\,
O => \state[0]_i_2_n_0\
);
\state[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0C0CAE0000000000"
)
port map (
I0 => s_axburst_eq1_reg_0,
I1 => \cnt_read_reg[1]_rep__1\,
I2 => \cnt_read_reg[0]_rep__0\,
I3 => m_axi_awready,
I4 => \^state_reg[1]_rep_0\,
I5 => \^state_reg[1]_rep_1\,
O => \state[1]_i_1__0_n_0\
);
\state_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^q\(0),
R => areset_d1
);
\state_reg[0]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => next_state(0),
Q => \^state_reg[1]_rep_1\,
R => areset_d1
);
\state_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^q\(1),
R => areset_d1
);
\state_reg[1]_rep\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \state[1]_i_1__0_n_0\,
Q => \^state_reg[1]_rep_0\,
R => areset_d1
);
\wrap_boundary_axaddr_r[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^state_reg[1]_rep_0\,
I1 => si_rs_awvalid,
I2 => \^state_reg[1]_rep_1\,
O => \^e\(0)
);
\wrap_cnt_r[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"9"
)
port map (
I0 => \^wrap_second_len_r_reg[1]\(0),
I1 => \m_payload_i_reg[44]\,
O => D(0)
);
\wrap_second_len_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FF0000FCAAAAAAAA"
)
port map (
I0 => \wrap_second_len_r_reg[1]_0\(0),
I1 => \m_payload_i_reg[35]\(2),
I2 => \^axaddr_offset_r_reg[3]\(0),
I3 => \m_payload_i_reg[35]\(0),
I4 => \m_payload_i_reg[35]\(1),
I5 => \^e\(0),
O => \^wrap_second_len_r_reg[1]\(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
port (
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
wrap_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\next\ : in STD_LOGIC;
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd is
signal axaddr_wrap : STD_LOGIC_VECTOR ( 11 downto 0 );
signal axaddr_wrap0 : STD_LOGIC_VECTOR ( 11 downto 0 );
signal \axaddr_wrap[0]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2_n_3\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal wrap_boundary_axaddr_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal wrap_cnt_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_wrap[11]_i_2\ : label is "soft_lutpair114";
attribute SOFT_HLUTNM of \next_pending_r_i_3__0\ : label is "soft_lutpair114";
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(0),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(0),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1_n_0\
);
\axaddr_wrap[10]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(10),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(10),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1_n_0\
);
\axaddr_wrap[11]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(11),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(11),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1_n_0\
);
\axaddr_wrap[11]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4_n_0\,
I1 => wrap_cnt_r(3),
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2_n_0\
);
\axaddr_wrap[11]_i_4\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => wrap_cnt_r(0),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[2]\,
I3 => wrap_cnt_r(2),
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => wrap_cnt_r(1),
O => \axaddr_wrap[11]_i_4_n_0\
);
\axaddr_wrap[11]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(11),
O => \axaddr_wrap[11]_i_5_n_0\
);
\axaddr_wrap[11]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(10),
O => \axaddr_wrap[11]_i_6_n_0\
);
\axaddr_wrap[11]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(9),
O => \axaddr_wrap[11]_i_7_n_0\
);
\axaddr_wrap[11]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(8),
O => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(1),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(1),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1_n_0\
);
\axaddr_wrap[2]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(2),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(2),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1_n_0\
);
\axaddr_wrap[3]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(3),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(3),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => axaddr_wrap(3),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(2),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => axaddr_wrap(1),
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => axaddr_wrap(0),
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(4),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(4),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1_n_0\
);
\axaddr_wrap[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(5),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(5),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1_n_0\
);
\axaddr_wrap[6]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(6),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(6),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1_n_0\
);
\axaddr_wrap[7]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(7),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(7),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1_n_0\
);
\axaddr_wrap[7]_i_3\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(7),
O => \axaddr_wrap[7]_i_3_n_0\
);
\axaddr_wrap[7]_i_4\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(6),
O => \axaddr_wrap[7]_i_4_n_0\
);
\axaddr_wrap[7]_i_5\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(5),
O => \axaddr_wrap[7]_i_5_n_0\
);
\axaddr_wrap[7]_i_6\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => axaddr_wrap(4),
O => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap[8]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(8),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(8),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1_n_0\
);
\axaddr_wrap[9]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => wrap_boundary_axaddr_r(9),
I1 => \axaddr_wrap[11]_i_2_n_0\,
I2 => axaddr_wrap0(9),
I3 => \next\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1_n_0\,
Q => axaddr_wrap(0),
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1_n_0\,
Q => axaddr_wrap(10),
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1_n_0\,
Q => axaddr_wrap(11),
R => '0'
);
\axaddr_wrap_reg[11]_i_3\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(11 downto 8),
S(3) => \axaddr_wrap[11]_i_5_n_0\,
S(2) => \axaddr_wrap[11]_i_6_n_0\,
S(1) => \axaddr_wrap[11]_i_7_n_0\,
S(0) => \axaddr_wrap[11]_i_8_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1_n_0\,
Q => axaddr_wrap(1),
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1_n_0\,
Q => axaddr_wrap(2),
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1_n_0\,
Q => axaddr_wrap(3),
R => '0'
);
\axaddr_wrap_reg[3]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => axaddr_wrap(3 downto 0),
O(3 downto 0) => axaddr_wrap0(3 downto 0),
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1_n_0\,
Q => axaddr_wrap(4),
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1_n_0\,
Q => axaddr_wrap(5),
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1_n_0\,
Q => axaddr_wrap(6),
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1_n_0\,
Q => axaddr_wrap(7),
R => '0'
);
\axaddr_wrap_reg[7]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => axaddr_wrap0(7 downto 4),
S(3) => \axaddr_wrap[7]_i_3_n_0\,
S(2) => \axaddr_wrap[7]_i_4_n_0\,
S(1) => \axaddr_wrap[7]_i_5_n_0\,
S(0) => \axaddr_wrap[7]_i_6_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1_n_0\,
Q => axaddr_wrap(8),
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1_n_0\,
Q => axaddr_wrap(9),
R => '0'
);
\axlen_cnt[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[1]\,
I5 => \axlen_cnt_reg_n_0_[2]\,
O => \axlen_cnt[0]_i_1__0_n_0\
);
\axlen_cnt[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__0_n_0\
);
\axlen_cnt[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__0_n_0\
);
\axlen_cnt[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__0_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__0_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_awaddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(0),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_awaddr(0)
);
\m_axi_awaddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(10),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_awaddr(10)
);
\m_axi_awaddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(11),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(7),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_awaddr(11)
);
\m_axi_awaddr[1]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(1),
I1 => \^sel_first_reg_0\,
I2 => axaddr_wrap(1),
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_awaddr(1)
);
\m_axi_awaddr[2]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(2),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(2),
O => m_axi_awaddr(2)
);
\m_axi_awaddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(3),
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_awaddr(3)
);
\m_axi_awaddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(4),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_awaddr(4)
);
\m_axi_awaddr[5]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(5),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(5),
O => m_axi_awaddr(5)
);
\m_axi_awaddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(6),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_awaddr(6)
);
\m_axi_awaddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(7),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_awaddr(7)
);
\m_axi_awaddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(8),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_awaddr(8)
);
\m_axi_awaddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => axaddr_wrap(9),
I2 => \m_payload_i_reg[47]\(14),
I3 => axaddr_incr_reg(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_awaddr(9)
);
\next_pending_r_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[1]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => next_pending_r_reg_1
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => wrap_next_pending,
Q => next_pending_r_reg_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => wrap_boundary_axaddr_r(0),
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => wrap_boundary_axaddr_r(10),
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => wrap_boundary_axaddr_r(11),
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => wrap_boundary_axaddr_r(1),
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => wrap_boundary_axaddr_r(2),
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => wrap_boundary_axaddr_r(3),
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => wrap_boundary_axaddr_r(4),
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => wrap_boundary_axaddr_r(5),
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => wrap_boundary_axaddr_r(6),
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => wrap_boundary_axaddr_r(7),
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => wrap_boundary_axaddr_r(8),
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => wrap_boundary_axaddr_r(9),
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => wrap_cnt_r(0),
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => wrap_cnt_r(1),
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => wrap_cnt_r(2),
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => wrap_cnt_r(3),
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
port (
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC_VECTOR ( 18 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_incr_reg[11]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\axaddr_incr_reg[3]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 : entity is "axi_protocol_converter_v2_1_13_b2s_wrap_cmd";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3 is
signal \axaddr_wrap[0]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[10]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[11]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[1]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[2]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_wrap[3]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_wrap[4]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[5]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[6]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[7]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[8]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap[9]_i_1__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[11]_i_3__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[3]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_4\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_5\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_6\ : STD_LOGIC;
signal \axaddr_wrap_reg[7]_i_2__0_n_7\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[10]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[11]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[1]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[2]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[3]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[4]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[5]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[6]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[7]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[8]\ : STD_LOGIC;
signal \axaddr_wrap_reg_n_0_[9]\ : STD_LOGIC;
signal \axlen_cnt[0]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[1]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[2]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt[3]_i_1__2_n_0\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[0]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[1]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[2]\ : STD_LOGIC;
signal \axlen_cnt_reg_n_0_[3]\ : STD_LOGIC;
signal \next_pending_r_i_3__2_n_0\ : STD_LOGIC;
signal next_pending_r_reg_n_0 : STD_LOGIC;
signal \^sel_first_reg_0\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[10]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[11]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[3]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[4]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[5]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[6]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[7]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[8]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[0]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[1]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[2]\ : STD_LOGIC;
signal \wrap_cnt_r_reg_n_0_[3]\ : STD_LOGIC;
signal \^wrap_next_pending\ : STD_LOGIC;
signal \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
begin
sel_first_reg_0 <= \^sel_first_reg_0\;
wrap_next_pending <= \^wrap_next_pending\;
\axaddr_offset_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(0),
Q => \axaddr_offset_r_reg[3]_0\(0),
R => '0'
);
\axaddr_offset_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(1),
Q => \axaddr_offset_r_reg[3]_0\(1),
R => '0'
);
\axaddr_offset_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(2),
Q => \axaddr_offset_r_reg[3]_0\(2),
R => '0'
);
\axaddr_offset_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \axaddr_offset_r_reg[3]_1\(3),
Q => \axaddr_offset_r_reg[3]_0\(3),
R => '0'
);
\axaddr_wrap[0]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(0),
O => \axaddr_wrap[0]_i_1__0_n_0\
);
\axaddr_wrap[10]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(10),
O => \axaddr_wrap[10]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(11),
O => \axaddr_wrap[11]_i_1__0_n_0\
);
\axaddr_wrap[11]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"41"
)
port map (
I0 => \axaddr_wrap[11]_i_4__0_n_0\,
I1 => \wrap_cnt_r_reg_n_0_[3]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
O => \axaddr_wrap[11]_i_2__0_n_0\
);
\axaddr_wrap[11]_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"6FF6FFFFFFFF6FF6"
)
port map (
I0 => \wrap_cnt_r_reg_n_0_[0]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \wrap_cnt_r_reg_n_0_[1]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \wrap_cnt_r_reg_n_0_[2]\,
O => \axaddr_wrap[11]_i_4__0_n_0\
);
\axaddr_wrap[11]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[11]\,
O => \axaddr_wrap[11]_i_5__0_n_0\
);
\axaddr_wrap[11]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[10]\,
O => \axaddr_wrap[11]_i_6__0_n_0\
);
\axaddr_wrap[11]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[9]\,
O => \axaddr_wrap[11]_i_7__0_n_0\
);
\axaddr_wrap[11]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[8]\,
O => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(1),
O => \axaddr_wrap[1]_i_1__0_n_0\
);
\axaddr_wrap[2]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(2),
O => \axaddr_wrap[2]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[3]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(3),
O => \axaddr_wrap[3]_i_1__0_n_0\
);
\axaddr_wrap[3]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[3]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_3_n_0\
);
\axaddr_wrap[3]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[2]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_4_n_0\
);
\axaddr_wrap[3]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[1]\,
I1 => \m_payload_i_reg[47]\(13),
I2 => \m_payload_i_reg[47]\(12),
O => \axaddr_wrap[3]_i_5_n_0\
);
\axaddr_wrap[3]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"A9"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[0]\,
I1 => \m_payload_i_reg[47]\(12),
I2 => \m_payload_i_reg[47]\(13),
O => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap[4]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(4),
O => \axaddr_wrap[4]_i_1__0_n_0\
);
\axaddr_wrap[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(5),
O => \axaddr_wrap[5]_i_1__0_n_0\
);
\axaddr_wrap[6]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_5\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(6),
O => \axaddr_wrap[6]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[7]_i_2__0_n_4\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(7),
O => \axaddr_wrap[7]_i_1__0_n_0\
);
\axaddr_wrap[7]_i_3__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[7]\,
O => \axaddr_wrap[7]_i_3__0_n_0\
);
\axaddr_wrap[7]_i_4__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[6]\,
O => \axaddr_wrap[7]_i_4__0_n_0\
);
\axaddr_wrap[7]_i_5__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[5]\,
O => \axaddr_wrap[7]_i_5__0_n_0\
);
\axaddr_wrap[7]_i_6__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \axaddr_wrap_reg_n_0_[4]\,
O => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap[8]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_7\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(8),
O => \axaddr_wrap[8]_i_1__0_n_0\
);
\axaddr_wrap[9]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
I1 => \axaddr_wrap[11]_i_2__0_n_0\,
I2 => \axaddr_wrap_reg[11]_i_3__0_n_6\,
I3 => \state_reg[1]_rep_0\,
I4 => \m_payload_i_reg[47]\(9),
O => \axaddr_wrap[9]_i_1__0_n_0\
);
\axaddr_wrap_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[0]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[0]\,
R => '0'
);
\axaddr_wrap_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[10]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[10]\,
R => '0'
);
\axaddr_wrap_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[11]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[11]\,
R => '0'
);
\axaddr_wrap_reg[11]_i_3__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(3) => \NLW_axaddr_wrap_reg[11]_i_3__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_wrap_reg[11]_i_3__0_n_1\,
CO(1) => \axaddr_wrap_reg[11]_i_3__0_n_2\,
CO(0) => \axaddr_wrap_reg[11]_i_3__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[11]_i_3__0_n_4\,
O(2) => \axaddr_wrap_reg[11]_i_3__0_n_5\,
O(1) => \axaddr_wrap_reg[11]_i_3__0_n_6\,
O(0) => \axaddr_wrap_reg[11]_i_3__0_n_7\,
S(3) => \axaddr_wrap[11]_i_5__0_n_0\,
S(2) => \axaddr_wrap[11]_i_6__0_n_0\,
S(1) => \axaddr_wrap[11]_i_7__0_n_0\,
S(0) => \axaddr_wrap[11]_i_8__0_n_0\
);
\axaddr_wrap_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[1]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[1]\,
R => '0'
);
\axaddr_wrap_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[2]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[2]\,
R => '0'
);
\axaddr_wrap_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[3]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[3]\,
R => '0'
);
\axaddr_wrap_reg[3]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[3]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[3]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[3]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_wrap_reg_n_0_[3]\,
DI(2) => \axaddr_wrap_reg_n_0_[2]\,
DI(1) => \axaddr_wrap_reg_n_0_[1]\,
DI(0) => \axaddr_wrap_reg_n_0_[0]\,
O(3) => \axaddr_wrap_reg[3]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[3]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[3]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[3]_i_2__0_n_7\,
S(3) => \axaddr_wrap[3]_i_3_n_0\,
S(2) => \axaddr_wrap[3]_i_4_n_0\,
S(1) => \axaddr_wrap[3]_i_5_n_0\,
S(0) => \axaddr_wrap[3]_i_6_n_0\
);
\axaddr_wrap_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[4]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[4]\,
R => '0'
);
\axaddr_wrap_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[5]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[5]\,
R => '0'
);
\axaddr_wrap_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[6]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[6]\,
R => '0'
);
\axaddr_wrap_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[7]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[7]\,
R => '0'
);
\axaddr_wrap_reg[7]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_wrap_reg[3]_i_2__0_n_0\,
CO(3) => \axaddr_wrap_reg[7]_i_2__0_n_0\,
CO(2) => \axaddr_wrap_reg[7]_i_2__0_n_1\,
CO(1) => \axaddr_wrap_reg[7]_i_2__0_n_2\,
CO(0) => \axaddr_wrap_reg[7]_i_2__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3) => \axaddr_wrap_reg[7]_i_2__0_n_4\,
O(2) => \axaddr_wrap_reg[7]_i_2__0_n_5\,
O(1) => \axaddr_wrap_reg[7]_i_2__0_n_6\,
O(0) => \axaddr_wrap_reg[7]_i_2__0_n_7\,
S(3) => \axaddr_wrap[7]_i_3__0_n_0\,
S(2) => \axaddr_wrap[7]_i_4__0_n_0\,
S(1) => \axaddr_wrap[7]_i_5__0_n_0\,
S(0) => \axaddr_wrap[7]_i_6__0_n_0\
);
\axaddr_wrap_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[8]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[8]\,
R => '0'
);
\axaddr_wrap_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axaddr_wrap[9]_i_1__0_n_0\,
Q => \axaddr_wrap_reg_n_0_[9]\,
R => '0'
);
\axlen_cnt[0]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"A3A3A3A3A3A3A3A0"
)
port map (
I0 => \m_payload_i_reg[47]\(15),
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => E(0),
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \axlen_cnt[0]_i_1__2_n_0\
);
\axlen_cnt[1]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFF999800009998"
)
port map (
I0 => \axlen_cnt_reg_n_0_[1]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[3]\,
I3 => \axlen_cnt_reg_n_0_[2]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(16),
O => \axlen_cnt[1]_i_1__2_n_0\
);
\axlen_cnt[2]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFA9A80000A9A8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[2]\,
I1 => \axlen_cnt_reg_n_0_[0]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(17),
O => \axlen_cnt[2]_i_1__2_n_0\
);
\axlen_cnt[3]_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFAAA80000AAA8"
)
port map (
I0 => \axlen_cnt_reg_n_0_[3]\,
I1 => \axlen_cnt_reg_n_0_[2]\,
I2 => \axlen_cnt_reg_n_0_[1]\,
I3 => \axlen_cnt_reg_n_0_[0]\,
I4 => E(0),
I5 => \m_payload_i_reg[47]\(18),
O => \axlen_cnt[3]_i_1__2_n_0\
);
\axlen_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[0]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[0]\,
R => '0'
);
\axlen_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[1]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[1]\,
R => '0'
);
\axlen_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[2]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[2]\,
R => '0'
);
\axlen_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg(0),
D => \axlen_cnt[3]_i_1__2_n_0\,
Q => \axlen_cnt_reg_n_0_[3]\,
R => '0'
);
\m_axi_araddr[0]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[0]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(0),
O => m_axi_araddr(0)
);
\m_axi_araddr[10]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[10]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(5),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(10),
O => m_axi_araddr(10)
);
\m_axi_araddr[11]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[11]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(6),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(11),
O => m_axi_araddr(11)
);
\m_axi_araddr[1]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[1]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(1),
O => m_axi_araddr(1)
);
\m_axi_araddr[2]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(2),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[2]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_3,
O => m_axi_araddr(2)
);
\m_axi_araddr[3]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[3]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[3]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(3),
O => m_axi_araddr(3)
);
\m_axi_araddr[4]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[4]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(0),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(4),
O => m_axi_araddr(4)
);
\m_axi_araddr[5]_INST_0\: unisim.vcomponents.LUT5
generic map(
INIT => X"B8FFB800"
)
port map (
I0 => \m_payload_i_reg[47]\(5),
I1 => \^sel_first_reg_0\,
I2 => \axaddr_wrap_reg_n_0_[5]\,
I3 => \m_payload_i_reg[47]\(14),
I4 => sel_first_reg_2,
O => m_axi_araddr(5)
);
\m_axi_araddr[6]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[6]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(1),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(6),
O => m_axi_araddr(6)
);
\m_axi_araddr[7]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[7]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(2),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(7),
O => m_axi_araddr(7)
);
\m_axi_araddr[8]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[8]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(3),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(8),
O => m_axi_araddr(8)
);
\m_axi_araddr[9]_INST_0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EFE0EFEF4F404040"
)
port map (
I0 => \^sel_first_reg_0\,
I1 => \axaddr_wrap_reg_n_0_[9]\,
I2 => \m_payload_i_reg[47]\(14),
I3 => \axaddr_incr_reg[11]\(4),
I4 => \m_payload_i_reg[38]\,
I5 => \m_payload_i_reg[47]\(9),
O => m_axi_araddr(9)
);
\next_pending_r_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FD55FC0C"
)
port map (
I0 => \m_payload_i_reg[46]\,
I1 => next_pending_r_reg_n_0,
I2 => \state_reg[1]_rep_0\,
I3 => \next_pending_r_i_3__2_n_0\,
I4 => E(0),
O => \^wrap_next_pending\
);
\next_pending_r_i_3__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"FBFBFBFBFBFBFB00"
)
port map (
I0 => \state_reg[0]_rep\,
I1 => si_rs_arvalid,
I2 => \state_reg[1]_rep\,
I3 => \axlen_cnt_reg_n_0_[3]\,
I4 => \axlen_cnt_reg_n_0_[2]\,
I5 => \axlen_cnt_reg_n_0_[1]\,
O => \next_pending_r_i_3__2_n_0\
);
next_pending_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \^wrap_next_pending\,
Q => next_pending_r_reg_n_0,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_reg_1,
Q => \^sel_first_reg_0\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(0),
Q => \wrap_boundary_axaddr_r_reg_n_0_[0]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(10),
Q => \wrap_boundary_axaddr_r_reg_n_0_[10]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(11),
Q => \wrap_boundary_axaddr_r_reg_n_0_[11]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(1),
Q => \wrap_boundary_axaddr_r_reg_n_0_[1]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(2),
Q => \wrap_boundary_axaddr_r_reg_n_0_[2]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(3),
Q => \wrap_boundary_axaddr_r_reg_n_0_[3]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(4),
Q => \wrap_boundary_axaddr_r_reg_n_0_[4]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(5),
Q => \wrap_boundary_axaddr_r_reg_n_0_[5]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[6]\(6),
Q => \wrap_boundary_axaddr_r_reg_n_0_[6]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(7),
Q => \wrap_boundary_axaddr_r_reg_n_0_[7]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(8),
Q => \wrap_boundary_axaddr_r_reg_n_0_[8]\,
R => '0'
);
\wrap_boundary_axaddr_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => \m_payload_i_reg[47]\(9),
Q => \wrap_boundary_axaddr_r_reg_n_0_[9]\,
R => '0'
);
\wrap_cnt_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(0),
Q => \wrap_cnt_r_reg_n_0_[0]\,
R => '0'
);
\wrap_cnt_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(1),
Q => \wrap_cnt_r_reg_n_0_[1]\,
R => '0'
);
\wrap_cnt_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(2),
Q => \wrap_cnt_r_reg_n_0_[2]\,
R => '0'
);
\wrap_cnt_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_2\(3),
Q => \wrap_cnt_r_reg_n_0_[3]\,
R => '0'
);
\wrap_second_len_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(0),
Q => \wrap_second_len_r_reg[3]_0\(0),
R => '0'
);
\wrap_second_len_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(1),
Q => \wrap_second_len_r_reg[3]_0\(1),
R => '0'
);
\wrap_second_len_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(2),
Q => \wrap_second_len_r_reg[3]_0\(2),
R => '0'
);
\wrap_second_len_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \wrap_second_len_r_reg[3]_1\(3),
Q => \wrap_second_len_r_reg[3]_0\(3),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
port (
s_axi_arready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_araddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]_0\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\m_payload_i_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_valid_i_reg_1 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice is
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \axaddr_incr[0]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8__0_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_4\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_5\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_6\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11__0_n_7\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6__0_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2__0_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3__0_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal \m_payload_i[0]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_2__0_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[47]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[48]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[49]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[50]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[51]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[53]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[54]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[55]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[56]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[57]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[58]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[59]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[60]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[61]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[62]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[63]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[64]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__0_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__0_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_arready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3__0_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4__0_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2__0_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[1]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2__0\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__0\ : label is "soft_lutpair39";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__1\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__0\ : label is "soft_lutpair38";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__0\ : label is "soft_lutpair37";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__0\ : label is "soft_lutpair36";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__0\ : label is "soft_lutpair35";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__0\ : label is "soft_lutpair34";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__0\ : label is "soft_lutpair33";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__0\ : label is "soft_lutpair32";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__0\ : label is "soft_lutpair31";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__0\ : label is "soft_lutpair44";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__0\ : label is "soft_lutpair30";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__0\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__0\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__0\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__0\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__0\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1__0\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1__0\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__0\ : label is "soft_lutpair43";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1__0\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1__0\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1__0\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1__0\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__0\ : label is "soft_lutpair42";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__0\ : label is "soft_lutpair41";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__0\ : label is "soft_lutpair40";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1__0\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1__0\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1__0\ : label is "soft_lutpair14";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_arready <= \^s_axi_arready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]_0\ <= \^wrap_cnt_r_reg[3]_0\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d_reg[1]_inv\: unisim.vcomponents.FDRE
generic map(
INIT => '1'
)
port map (
C => aclk,
CE => '1',
D => \aresetn_d_reg[0]_0\,
Q => \^m_valid_i_reg_0\,
R => '0'
);
\axaddr_incr[0]_i_10__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(0),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_7\,
O => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr[0]_i_12__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12__0_n_0\
);
\axaddr_incr[0]_i_13__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13__0_n_0\
);
\axaddr_incr[0]_i_14__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14__0_n_0\
);
\axaddr_incr[0]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_3__0_n_0\
);
\axaddr_incr[0]_i_4__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_4__0_n_0\
);
\axaddr_incr[0]_i_5__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_5__0_n_0\
);
\axaddr_incr[0]_i_6__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first_2,
O => \axaddr_incr[0]_i_6__0_n_0\
);
\axaddr_incr[0]_i_7__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(3),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_4\,
O => \axaddr_incr[0]_i_7__0_n_0\
);
\axaddr_incr[0]_i_8__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => \axaddr_incr_reg[3]_0\(2),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_5\,
O => \axaddr_incr[0]_i_8__0_n_0\
);
\axaddr_incr[0]_i_9__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => \axaddr_incr_reg[3]_0\(1),
I3 => sel_first_2,
I4 => \axaddr_incr_reg[0]_i_11__0_n_6\,
O => \axaddr_incr[0]_i_9__0_n_0\
);
\axaddr_incr[4]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr[4]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7__0_n_0\
);
\axaddr_incr[4]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8__0_n_0\
);
\axaddr_incr[4]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9__0_n_0\
);
\axaddr_incr[8]_i_10__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_incr[8]_i_7__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7__0_n_0\
);
\axaddr_incr[8]_i_8__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8__0_n_0\
);
\axaddr_incr[8]_i_9__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9__0_n_0\
);
\axaddr_incr_reg[0]_i_11__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11__0_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12__0_n_0\,
DI(1) => \axaddr_incr[0]_i_13__0_n_0\,
DI(0) => \axaddr_incr[0]_i_14__0_n_0\,
O(3) => \axaddr_incr_reg[0]_i_11__0_n_4\,
O(2) => \axaddr_incr_reg[0]_i_11__0_n_5\,
O(1) => \axaddr_incr_reg[0]_i_11__0_n_6\,
O(0) => \axaddr_incr_reg[0]_i_11__0_n_7\,
S(3 downto 0) => \m_payload_i_reg[3]_0\(3 downto 0)
);
\axaddr_incr_reg[0]_i_2__0\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[7]_0\(0),
CO(2) => \axaddr_incr_reg[0]_i_2__0_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2__0_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2__0_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3__0_n_0\,
DI(2) => \axaddr_incr[0]_i_4__0_n_0\,
DI(1) => \axaddr_incr[0]_i_5__0_n_0\,
DI(0) => \axaddr_incr[0]_i_6__0_n_0\,
O(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
S(3) => \axaddr_incr[0]_i_7__0_n_0\,
S(2) => \axaddr_incr[0]_i_8__0_n_0\,
S(1) => \axaddr_incr[0]_i_9__0_n_0\,
S(0) => \axaddr_incr[0]_i_10__0_n_0\
);
\axaddr_incr_reg[4]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11__0_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7__0_n_0\,
S(2) => \axaddr_incr[4]_i_8__0_n_0\,
S(1) => \axaddr_incr[4]_i_9__0_n_0\,
S(0) => \axaddr_incr[4]_i_10__0_n_0\
);
\axaddr_incr_reg[8]_i_6__0\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6__0_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6__0_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6__0_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6__0_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6__0_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[8]_i_7__0_n_0\,
S(2) => \axaddr_incr[8]_i_8__0_n_0\,
S(1) => \axaddr_incr[8]_i_9__0_n_0\,
S(0) => \axaddr_incr[8]_i_10__0_n_0\
);
\axaddr_offset_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2__0_n_0\
);
\axaddr_offset_r[1]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3__0_n_0\,
I1 => \axaddr_offset_r[1]_i_2__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \axaddr_offset_r[2]_i_3__0_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2__0_n_0\
);
\axaddr_offset_r[2]_i_3__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3__0_n_0\
);
\axaddr_offset_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]_rep_0\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_araddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first_2,
O => \m_axi_araddr[10]\
);
\m_payload_i[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__0_n_0\
);
\m_payload_i[10]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__0_n_0\
);
\m_payload_i[11]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__0_n_0\
);
\m_payload_i[12]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(12),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__0_n_0\
);
\m_payload_i[13]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(13),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__1_n_0\
);
\m_payload_i[14]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(14),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__0_n_0\
);
\m_payload_i[15]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(15),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__0_n_0\
);
\m_payload_i[16]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(16),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__0_n_0\
);
\m_payload_i[17]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(17),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__0_n_0\
);
\m_payload_i[18]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(18),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__0_n_0\
);
\m_payload_i[19]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(19),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__0_n_0\
);
\m_payload_i[1]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__0_n_0\
);
\m_payload_i[20]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(20),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__0_n_0\
);
\m_payload_i[21]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(21),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__0_n_0\
);
\m_payload_i[22]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(22),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__0_n_0\
);
\m_payload_i[23]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(23),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__0_n_0\
);
\m_payload_i[24]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(24),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__0_n_0\
);
\m_payload_i[25]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(25),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__0_n_0\
);
\m_payload_i[26]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(26),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__0_n_0\
);
\m_payload_i[27]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(27),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__0_n_0\
);
\m_payload_i[28]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(28),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__0_n_0\
);
\m_payload_i[29]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(29),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__0_n_0\
);
\m_payload_i[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__0_n_0\
);
\m_payload_i[30]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(30),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__0_n_0\
);
\m_payload_i[31]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(31),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_2__0_n_0\
);
\m_payload_i[32]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__0_n_0\
);
\m_payload_i[33]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__0_n_0\
);
\m_payload_i[34]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arprot(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__0_n_0\
);
\m_payload_i[35]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__0_n_0\
);
\m_payload_i[36]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arsize(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__0_n_0\
);
\m_payload_i[38]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__0_n_0\
);
\m_payload_i[39]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arburst(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__0_n_0\
);
\m_payload_i[3]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__0_n_0\
);
\m_payload_i[44]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__0_n_0\
);
\m_payload_i[45]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__0_n_0\
);
\m_payload_i[46]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_1__1_n_0\
);
\m_payload_i[47]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => \m_payload_i[47]_i_1__0_n_0\
);
\m_payload_i[48]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => \m_payload_i[48]_i_1__0_n_0\
);
\m_payload_i[49]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => \m_payload_i[49]_i_1__0_n_0\
);
\m_payload_i[4]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__0_n_0\
);
\m_payload_i[50]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => \m_payload_i[50]_i_1__0_n_0\
);
\m_payload_i[51]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arlen(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => \m_payload_i[51]_i_1__0_n_0\
);
\m_payload_i[53]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(0),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => \m_payload_i[53]_i_1__0_n_0\
);
\m_payload_i[54]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(1),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => \m_payload_i[54]_i_1__0_n_0\
);
\m_payload_i[55]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(2),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => \m_payload_i[55]_i_1__0_n_0\
);
\m_payload_i[56]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(3),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => \m_payload_i[56]_i_1__0_n_0\
);
\m_payload_i[57]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(4),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => \m_payload_i[57]_i_1__0_n_0\
);
\m_payload_i[58]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => \m_payload_i[58]_i_1__0_n_0\
);
\m_payload_i[59]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => \m_payload_i[59]_i_1__0_n_0\
);
\m_payload_i[5]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(5),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__0_n_0\
);
\m_payload_i[60]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => \m_payload_i[60]_i_1__0_n_0\
);
\m_payload_i[61]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => \m_payload_i[61]_i_1__0_n_0\
);
\m_payload_i[62]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => \m_payload_i[62]_i_1__0_n_0\
);
\m_payload_i[63]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(10),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => \m_payload_i[63]_i_1__0_n_0\
);
\m_payload_i[64]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_arid(11),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => \m_payload_i[64]_i_1__0_n_0\
);
\m_payload_i[6]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(6),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__0_n_0\
);
\m_payload_i[7]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(7),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__0_n_0\
);
\m_payload_i[8]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(8),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__0_n_0\
);
\m_payload_i[9]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_araddr(9),
I1 => \^s_axi_arready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__0_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[0]_i_1__0_n_0\,
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[10]_i_1__0_n_0\,
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[11]_i_1__0_n_0\,
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[12]_i_1__0_n_0\,
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[13]_i_1__1_n_0\,
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[14]_i_1__0_n_0\,
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[15]_i_1__0_n_0\,
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[16]_i_1__0_n_0\,
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[17]_i_1__0_n_0\,
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[18]_i_1__0_n_0\,
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[19]_i_1__0_n_0\,
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[1]_i_1__0_n_0\,
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[20]_i_1__0_n_0\,
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[21]_i_1__0_n_0\,
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[22]_i_1__0_n_0\,
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[23]_i_1__0_n_0\,
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[24]_i_1__0_n_0\,
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[25]_i_1__0_n_0\,
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[26]_i_1__0_n_0\,
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[27]_i_1__0_n_0\,
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[28]_i_1__0_n_0\,
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[29]_i_1__0_n_0\,
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[2]_i_1__0_n_0\,
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[30]_i_1__0_n_0\,
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[31]_i_2__0_n_0\,
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[32]_i_1__0_n_0\,
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[33]_i_1__0_n_0\,
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[34]_i_1__0_n_0\,
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[35]_i_1__0_n_0\,
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[36]_i_1__0_n_0\,
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[38]_i_1__0_n_0\,
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[39]_i_1__0_n_0\,
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[3]_i_1__0_n_0\,
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[44]_i_1__0_n_0\,
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[45]_i_1__0_n_0\,
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[46]_i_1__1_n_0\,
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[47]_i_1__0_n_0\,
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[48]_i_1__0_n_0\,
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[49]_i_1__0_n_0\,
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[4]_i_1__0_n_0\,
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[50]_i_1__0_n_0\,
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[51]_i_1__0_n_0\,
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[53]_i_1__0_n_0\,
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[54]_i_1__0_n_0\,
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[55]_i_1__0_n_0\,
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[56]_i_1__0_n_0\,
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[57]_i_1__0_n_0\,
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[58]_i_1__0_n_0\,
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[59]_i_1__0_n_0\,
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[5]_i_1__0_n_0\,
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[60]_i_1__0_n_0\,
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[61]_i_1__0_n_0\,
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[62]_i_1__0_n_0\,
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[63]_i_1__0_n_0\,
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[64]_i_1__0_n_0\,
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[6]_i_1__0_n_0\,
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[7]_i_1__0_n_0\,
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[8]_i_1__0_n_0\,
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => m_valid_i_reg_1(0),
D => \m_payload_i[9]_i_1__0_n_0\,
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"BFFFBBBB"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_ready_i_reg_0\,
R => \^m_valid_i_reg_0\
);
\next_pending_r_i_2__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFD"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(46),
I2 => \^q\(44),
I3 => \^q\(45),
I4 => \^q\(43),
O => next_pending_r_reg
);
\next_pending_r_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"0001"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"F444FFFF"
)
port map (
I0 => s_axi_arvalid,
I1 => \^s_axi_arready\,
I2 => \state_reg[0]_rep\,
I3 => \state_reg[1]_rep_0\,
I4 => \^s_ready_i_reg_0\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_arready\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_arid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_arready\,
D => s_axi_araddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2__0_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \wrap_cnt_r_reg[3]\(0)
);
\wrap_cnt_r[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]_0\,
I2 => wrap_second_len_1(0),
O => \wrap_cnt_r_reg[3]\(1)
);
\wrap_cnt_r[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len_1(0),
I2 => \^wrap_cnt_r_reg[3]_0\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => \wrap_cnt_r_reg[3]\(2)
);
\wrap_cnt_r[3]_i_2__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3__0_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]_0\
);
\wrap_cnt_r[3]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2__0_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^s_ready_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2__0_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^s_ready_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4__0_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2__0_n_0\,
O => \wrap_second_len_r[0]_i_2__0_n_0\
);
\wrap_second_len_r[0]_i_3__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2__0_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3__0_n_0\
);
\wrap_second_len_r[0]_i_4__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[1]\(0),
I2 => \^s_ready_i_reg_0\,
I3 => \state_reg[1]\(1),
O => \wrap_second_len_r[0]_i_4__0_n_0\
);
\wrap_second_len_r[2]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2__0_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2__0_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
port (
s_axi_awready : out STD_LOGIC;
s_ready_i_reg_0 : out STD_LOGIC;
m_valid_i_reg_0 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
\axaddr_offset_r_reg[1]\ : out STD_LOGIC;
\axaddr_offset_r_reg[0]\ : out STD_LOGIC;
\axaddr_offset_r_reg[2]\ : out STD_LOGIC;
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\aresetn_d_reg[1]_inv\ : out STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[1]_inv_0\ : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0 is
signal C : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 58 downto 0 );
signal \aresetn_d_reg_n_0_[0]\ : STD_LOGIC;
signal \axaddr_incr[0]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_12_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_13_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_14_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_3_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_4_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_5_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[0]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[4]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_10_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_7_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_8_n_0\ : STD_LOGIC;
signal \axaddr_incr[8]_i_9_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_11_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[0]_i_2_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_0\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[4]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_1\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_2\ : STD_LOGIC;
signal \axaddr_incr_reg[8]_i_6_n_3\ : STD_LOGIC;
signal \axaddr_offset_r[0]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[1]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_2_n_0\ : STD_LOGIC;
signal \axaddr_offset_r[2]_i_3_n_0\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[0]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[1]\ : STD_LOGIC;
signal \^axaddr_offset_r_reg[2]\ : STD_LOGIC;
signal \^axlen_cnt_reg[3]\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal \^m_valid_i_reg_0\ : STD_LOGIC;
signal \^next_pending_r_reg_0\ : STD_LOGIC;
signal \^s_axi_awready\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^s_ready_i_reg_0\ : STD_LOGIC;
signal skid_buffer : STD_LOGIC_VECTOR ( 64 downto 0 );
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[47]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[48]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[49]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[50]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[51]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[53]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[54]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[55]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[56]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[57]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[58]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[59]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[60]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[61]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[62]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[63]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[64]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
signal \wrap_boundary_axaddr_r[3]_i_2_n_0\ : STD_LOGIC;
signal \wrap_cnt_r[3]_i_3_n_0\ : STD_LOGIC;
signal \^wrap_cnt_r_reg[3]\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_2_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_3_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[0]_i_4_n_0\ : STD_LOGIC;
signal \wrap_second_len_r[3]_i_2_n_0\ : STD_LOGIC;
signal \^wrap_second_len_r_reg[3]\ : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 to 3 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_2\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axaddr_offset_r[2]_i_3\ : label is "soft_lutpair48";
attribute SOFT_HLUTNM of \axlen_cnt[3]_i_2\ : label is "soft_lutpair46";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1\ : label is "soft_lutpair72";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__0\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1\ : label is "soft_lutpair71";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1\ : label is "soft_lutpair70";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1\ : label is "soft_lutpair69";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1\ : label is "soft_lutpair68";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1\ : label is "soft_lutpair67";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1\ : label is "soft_lutpair66";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1\ : label is "soft_lutpair65";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1\ : label is "soft_lutpair64";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1\ : label is "soft_lutpair77";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1\ : label is "soft_lutpair63";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_2\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1\ : label is "soft_lutpair62";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1\ : label is "soft_lutpair61";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1\ : label is "soft_lutpair60";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1\ : label is "soft_lutpair59";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1\ : label is "soft_lutpair58";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_1__0\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[47]_i_1\ : label is "soft_lutpair57";
attribute SOFT_HLUTNM of \m_payload_i[48]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[49]_i_1\ : label is "soft_lutpair56";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1\ : label is "soft_lutpair76";
attribute SOFT_HLUTNM of \m_payload_i[50]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[51]_i_1\ : label is "soft_lutpair55";
attribute SOFT_HLUTNM of \m_payload_i[53]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[54]_i_1\ : label is "soft_lutpair54";
attribute SOFT_HLUTNM of \m_payload_i[55]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[56]_i_1\ : label is "soft_lutpair53";
attribute SOFT_HLUTNM of \m_payload_i[57]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[58]_i_1\ : label is "soft_lutpair52";
attribute SOFT_HLUTNM of \m_payload_i[59]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[60]_i_1\ : label is "soft_lutpair51";
attribute SOFT_HLUTNM of \m_payload_i[61]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[62]_i_1\ : label is "soft_lutpair50";
attribute SOFT_HLUTNM of \m_payload_i[63]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[64]_i_1\ : label is "soft_lutpair49";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1\ : label is "soft_lutpair75";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1\ : label is "soft_lutpair74";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1\ : label is "soft_lutpair73";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[3]_i_2\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_boundary_axaddr_r[5]_i_1\ : label is "soft_lutpair45";
attribute SOFT_HLUTNM of \wrap_cnt_r[2]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_cnt_r[3]_i_1\ : label is "soft_lutpair47";
attribute SOFT_HLUTNM of \wrap_second_len_r[0]_i_4\ : label is "soft_lutpair46";
begin
Q(58 downto 0) <= \^q\(58 downto 0);
\axaddr_offset_r_reg[0]\ <= \^axaddr_offset_r_reg[0]\;
\axaddr_offset_r_reg[1]\ <= \^axaddr_offset_r_reg[1]\;
\axaddr_offset_r_reg[2]\ <= \^axaddr_offset_r_reg[2]\;
\axlen_cnt_reg[3]\ <= \^axlen_cnt_reg[3]\;
m_valid_i_reg_0 <= \^m_valid_i_reg_0\;
next_pending_r_reg_0 <= \^next_pending_r_reg_0\;
s_axi_awready <= \^s_axi_awready\;
s_ready_i_reg_0 <= \^s_ready_i_reg_0\;
\wrap_cnt_r_reg[3]\ <= \^wrap_cnt_r_reg[3]\;
\wrap_second_len_r_reg[3]\(2 downto 0) <= \^wrap_second_len_r_reg[3]\(2 downto 0);
\aresetn_d[1]_inv_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"7"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
I1 => aresetn,
O => \aresetn_d_reg[1]_inv\
);
\aresetn_d_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => aresetn,
Q => \aresetn_d_reg_n_0_[0]\,
R => '0'
);
\axaddr_incr[0]_i_10\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFE100E1"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(0),
I3 => sel_first,
I4 => C(0),
O => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr[0]_i_12\: unisim.vcomponents.LUT3
generic map(
INIT => X"2A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_12_n_0\
);
\axaddr_incr[0]_i_13\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
O => \axaddr_incr[0]_i_13_n_0\
);
\axaddr_incr[0]_i_14\: unisim.vcomponents.LUT3
generic map(
INIT => X"02"
)
port map (
I0 => \^q\(0),
I1 => \^q\(35),
I2 => \^q\(36),
O => \axaddr_incr[0]_i_14_n_0\
);
\axaddr_incr[0]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"08"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_3_n_0\
);
\axaddr_incr[0]_i_4\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_4_n_0\
);
\axaddr_incr[0]_i_5\: unisim.vcomponents.LUT3
generic map(
INIT => X"04"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => sel_first,
O => \axaddr_incr[0]_i_5_n_0\
);
\axaddr_incr[0]_i_6\: unisim.vcomponents.LUT3
generic map(
INIT => X"01"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => sel_first,
O => \axaddr_incr[0]_i_6_n_0\
);
\axaddr_incr[0]_i_7\: unisim.vcomponents.LUT5
generic map(
INIT => X"FF780078"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(3),
I3 => sel_first,
I4 => C(3),
O => \axaddr_incr[0]_i_7_n_0\
);
\axaddr_incr[0]_i_8\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(36),
I1 => \^q\(35),
I2 => axaddr_incr_reg(2),
I3 => sel_first,
I4 => C(2),
O => \axaddr_incr[0]_i_8_n_0\
);
\axaddr_incr[0]_i_9\: unisim.vcomponents.LUT5
generic map(
INIT => X"FFD200D2"
)
port map (
I0 => \^q\(35),
I1 => \^q\(36),
I2 => axaddr_incr_reg(1),
I3 => sel_first,
I4 => C(1),
O => \axaddr_incr[0]_i_9_n_0\
);
\axaddr_incr[4]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(4),
O => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr[4]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(7),
O => \axaddr_incr[4]_i_7_n_0\
);
\axaddr_incr[4]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(6),
O => \axaddr_incr[4]_i_8_n_0\
);
\axaddr_incr[4]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(5),
O => \axaddr_incr[4]_i_9_n_0\
);
\axaddr_incr[8]_i_10\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(8),
O => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_incr[8]_i_7\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(11),
O => \axaddr_incr[8]_i_7_n_0\
);
\axaddr_incr[8]_i_8\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(10),
O => \axaddr_incr[8]_i_8_n_0\
);
\axaddr_incr[8]_i_9\: unisim.vcomponents.LUT1
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(9),
O => \axaddr_incr[8]_i_9_n_0\
);
\axaddr_incr_reg[0]_i_11\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => \axaddr_incr_reg[0]_i_11_n_0\,
CO(2) => \axaddr_incr_reg[0]_i_11_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_11_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_11_n_3\,
CYINIT => '0',
DI(3) => \^q\(3),
DI(2) => \axaddr_incr[0]_i_12_n_0\,
DI(1) => \axaddr_incr[0]_i_13_n_0\,
DI(0) => \axaddr_incr[0]_i_14_n_0\,
O(3 downto 0) => C(3 downto 0),
S(3 downto 0) => S(3 downto 0)
);
\axaddr_incr_reg[0]_i_2\: unisim.vcomponents.CARRY4
port map (
CI => '0',
CO(3) => CO(0),
CO(2) => \axaddr_incr_reg[0]_i_2_n_1\,
CO(1) => \axaddr_incr_reg[0]_i_2_n_2\,
CO(0) => \axaddr_incr_reg[0]_i_2_n_3\,
CYINIT => '0',
DI(3) => \axaddr_incr[0]_i_3_n_0\,
DI(2) => \axaddr_incr[0]_i_4_n_0\,
DI(1) => \axaddr_incr[0]_i_5_n_0\,
DI(0) => \axaddr_incr[0]_i_6_n_0\,
O(3 downto 0) => O(3 downto 0),
S(3) => \axaddr_incr[0]_i_7_n_0\,
S(2) => \axaddr_incr[0]_i_8_n_0\,
S(1) => \axaddr_incr[0]_i_9_n_0\,
S(0) => \axaddr_incr[0]_i_10_n_0\
);
\axaddr_incr_reg[4]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[0]_i_11_n_0\,
CO(3) => \axaddr_incr_reg[4]_i_6_n_0\,
CO(2) => \axaddr_incr_reg[4]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[4]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[4]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(3 downto 0),
S(3) => \axaddr_incr[4]_i_7_n_0\,
S(2) => \axaddr_incr[4]_i_8_n_0\,
S(1) => \axaddr_incr[4]_i_9_n_0\,
S(0) => \axaddr_incr[4]_i_10_n_0\
);
\axaddr_incr_reg[8]_i_6\: unisim.vcomponents.CARRY4
port map (
CI => \axaddr_incr_reg[4]_i_6_n_0\,
CO(3) => \NLW_axaddr_incr_reg[8]_i_6_CO_UNCONNECTED\(3),
CO(2) => \axaddr_incr_reg[8]_i_6_n_1\,
CO(1) => \axaddr_incr_reg[8]_i_6_n_2\,
CO(0) => \axaddr_incr_reg[8]_i_6_n_3\,
CYINIT => '0',
DI(3 downto 0) => B"0000",
O(3 downto 0) => \axaddr_incr_reg[11]\(7 downto 4),
S(3) => \axaddr_incr[8]_i_7_n_0\,
S(2) => \axaddr_incr[8]_i_8_n_0\,
S(1) => \axaddr_incr[8]_i_9_n_0\,
S(0) => \axaddr_incr[8]_i_10_n_0\
);
\axaddr_offset_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"F0F0F0F0F088F0F0"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \axaddr_offset_r_reg[3]_1\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \^axaddr_offset_r_reg[0]\
);
\axaddr_offset_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(3),
I1 => \^q\(1),
I2 => \^q\(35),
I3 => \^q\(2),
I4 => \^q\(36),
I5 => \^q\(0),
O => \axaddr_offset_r[0]_i_2_n_0\
);
\axaddr_offset_r[1]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_3_n_0\,
I1 => \axaddr_offset_r[1]_i_2_n_0\,
I2 => \^q\(35),
I3 => \^q\(40),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(1),
O => \^axaddr_offset_r_reg[1]\
);
\axaddr_offset_r[1]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(3),
I1 => \^q\(36),
I2 => \^q\(1),
O => \axaddr_offset_r[1]_i_2_n_0\
);
\axaddr_offset_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"AC00FFFFAC000000"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \axaddr_offset_r[2]_i_3_n_0\,
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \state_reg[1]_rep_0\,
I5 => \axaddr_offset_r_reg[3]_1\(2),
O => \^axaddr_offset_r_reg[2]\
);
\axaddr_offset_r[2]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(3),
O => \axaddr_offset_r[2]_i_2_n_0\
);
\axaddr_offset_r[2]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(4),
I1 => \^q\(36),
I2 => \^q\(2),
O => \axaddr_offset_r[2]_i_3_n_0\
);
\axaddr_offset_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AFA0CFCFAFA0C0C0"
)
port map (
I0 => \^q\(6),
I1 => \^q\(4),
I2 => \^q\(35),
I3 => \^q\(5),
I4 => \^q\(36),
I5 => \^q\(3),
O => \axaddr_offset_r_reg[3]\
);
\axlen_cnt[3]_i_2\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFDF"
)
port map (
I0 => \^q\(42),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \^axlen_cnt_reg[3]\
);
\m_axi_awaddr[11]_INST_0_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^q\(37),
I1 => sel_first,
O => \m_axi_awaddr[10]\
);
\m_payload_i[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => skid_buffer(0)
);
\m_payload_i[10]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => skid_buffer(10)
);
\m_payload_i[11]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => skid_buffer(11)
);
\m_payload_i[12]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(12),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => skid_buffer(12)
);
\m_payload_i[13]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(13),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => skid_buffer(13)
);
\m_payload_i[14]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(14),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => skid_buffer(14)
);
\m_payload_i[15]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(15),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => skid_buffer(15)
);
\m_payload_i[16]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(16),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => skid_buffer(16)
);
\m_payload_i[17]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(17),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => skid_buffer(17)
);
\m_payload_i[18]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(18),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => skid_buffer(18)
);
\m_payload_i[19]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(19),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => skid_buffer(19)
);
\m_payload_i[1]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => skid_buffer(1)
);
\m_payload_i[20]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(20),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => skid_buffer(20)
);
\m_payload_i[21]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(21),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => skid_buffer(21)
);
\m_payload_i[22]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(22),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => skid_buffer(22)
);
\m_payload_i[23]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(23),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => skid_buffer(23)
);
\m_payload_i[24]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(24),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => skid_buffer(24)
);
\m_payload_i[25]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(25),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => skid_buffer(25)
);
\m_payload_i[26]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(26),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => skid_buffer(26)
);
\m_payload_i[27]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(27),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => skid_buffer(27)
);
\m_payload_i[28]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(28),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => skid_buffer(28)
);
\m_payload_i[29]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(29),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => skid_buffer(29)
);
\m_payload_i[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => skid_buffer(2)
);
\m_payload_i[30]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(30),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => skid_buffer(30)
);
\m_payload_i[31]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(31),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => skid_buffer(31)
);
\m_payload_i[32]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => skid_buffer(32)
);
\m_payload_i[33]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => skid_buffer(33)
);
\m_payload_i[34]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awprot(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => skid_buffer(34)
);
\m_payload_i[35]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => skid_buffer(35)
);
\m_payload_i[36]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awsize(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => skid_buffer(36)
);
\m_payload_i[38]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => skid_buffer(38)
);
\m_payload_i[39]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awburst(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => skid_buffer(39)
);
\m_payload_i[3]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => skid_buffer(3)
);
\m_payload_i[44]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => skid_buffer(44)
);
\m_payload_i[45]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => skid_buffer(45)
);
\m_payload_i[46]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => skid_buffer(46)
);
\m_payload_i[47]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[47]\,
O => skid_buffer(47)
);
\m_payload_i[48]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[48]\,
O => skid_buffer(48)
);
\m_payload_i[49]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[49]\,
O => skid_buffer(49)
);
\m_payload_i[4]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => skid_buffer(4)
);
\m_payload_i[50]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[50]\,
O => skid_buffer(50)
);
\m_payload_i[51]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awlen(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[51]\,
O => skid_buffer(51)
);
\m_payload_i[53]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(0),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[53]\,
O => skid_buffer(53)
);
\m_payload_i[54]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(1),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[54]\,
O => skid_buffer(54)
);
\m_payload_i[55]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(2),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[55]\,
O => skid_buffer(55)
);
\m_payload_i[56]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(3),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[56]\,
O => skid_buffer(56)
);
\m_payload_i[57]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(4),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[57]\,
O => skid_buffer(57)
);
\m_payload_i[58]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[58]\,
O => skid_buffer(58)
);
\m_payload_i[59]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[59]\,
O => skid_buffer(59)
);
\m_payload_i[5]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(5),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => skid_buffer(5)
);
\m_payload_i[60]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[60]\,
O => skid_buffer(60)
);
\m_payload_i[61]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[61]\,
O => skid_buffer(61)
);
\m_payload_i[62]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[62]\,
O => skid_buffer(62)
);
\m_payload_i[63]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(10),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[63]\,
O => skid_buffer(63)
);
\m_payload_i[64]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awid(11),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[64]\,
O => skid_buffer(64)
);
\m_payload_i[6]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(6),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => skid_buffer(6)
);
\m_payload_i[7]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(7),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => skid_buffer(7)
);
\m_payload_i[8]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(8),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => skid_buffer(8)
);
\m_payload_i[9]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axi_awaddr(9),
I1 => \^s_axi_awready\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => skid_buffer(9)
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(0),
Q => \^q\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(10),
Q => \^q\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(11),
Q => \^q\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(12),
Q => \^q\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(13),
Q => \^q\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(14),
Q => \^q\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(15),
Q => \^q\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(16),
Q => \^q\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(17),
Q => \^q\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(18),
Q => \^q\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(19),
Q => \^q\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(1),
Q => \^q\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(20),
Q => \^q\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(21),
Q => \^q\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(22),
Q => \^q\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(23),
Q => \^q\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(24),
Q => \^q\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(25),
Q => \^q\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(26),
Q => \^q\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(27),
Q => \^q\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(28),
Q => \^q\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(29),
Q => \^q\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(2),
Q => \^q\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(30),
Q => \^q\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(31),
Q => \^q\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(32),
Q => \^q\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(33),
Q => \^q\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(34),
Q => \^q\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(35),
Q => \^q\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(36),
Q => \^q\(36),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(38),
Q => \^q\(37),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(39),
Q => \^q\(38),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(3),
Q => \^q\(3),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(44),
Q => \^q\(39),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(45),
Q => \^q\(40),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(46),
Q => \^q\(41),
R => '0'
);
\m_payload_i_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(47),
Q => \^q\(42),
R => '0'
);
\m_payload_i_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(48),
Q => \^q\(43),
R => '0'
);
\m_payload_i_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(49),
Q => \^q\(44),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(4),
Q => \^q\(4),
R => '0'
);
\m_payload_i_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(50),
Q => \^q\(45),
R => '0'
);
\m_payload_i_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(51),
Q => \^q\(46),
R => '0'
);
\m_payload_i_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(53),
Q => \^q\(47),
R => '0'
);
\m_payload_i_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(54),
Q => \^q\(48),
R => '0'
);
\m_payload_i_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(55),
Q => \^q\(49),
R => '0'
);
\m_payload_i_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(56),
Q => \^q\(50),
R => '0'
);
\m_payload_i_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(57),
Q => \^q\(51),
R => '0'
);
\m_payload_i_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(58),
Q => \^q\(52),
R => '0'
);
\m_payload_i_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(59),
Q => \^q\(53),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(5),
Q => \^q\(5),
R => '0'
);
\m_payload_i_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(60),
Q => \^q\(54),
R => '0'
);
\m_payload_i_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(61),
Q => \^q\(55),
R => '0'
);
\m_payload_i_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(62),
Q => \^q\(56),
R => '0'
);
\m_payload_i_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(63),
Q => \^q\(57),
R => '0'
);
\m_payload_i_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(64),
Q => \^q\(58),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(6),
Q => \^q\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(7),
Q => \^q\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(8),
Q => \^q\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => E(0),
D => skid_buffer(9),
Q => \^q\(9),
R => '0'
);
\m_valid_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^m_valid_i_reg_0\,
R => \aresetn_d_reg[1]_inv_0\
);
next_pending_r_i_2: unisim.vcomponents.LUT5
generic map(
INIT => X"FFFFFFFE"
)
port map (
I0 => \^next_pending_r_reg_0\,
I1 => \^q\(43),
I2 => \^q\(44),
I3 => \^q\(46),
I4 => \^q\(45),
O => next_pending_r_reg
);
\next_pending_r_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"FFFE"
)
port map (
I0 => \^q\(41),
I1 => \^q\(39),
I2 => \^q\(40),
I3 => \^q\(42),
O => \^next_pending_r_reg_0\
);
\s_ready_i_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \aresetn_d_reg_n_0_[0]\,
O => \^s_ready_i_reg_0\
);
s_ready_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"BFBB"
)
port map (
I0 => b_push,
I1 => \^m_valid_i_reg_0\,
I2 => s_axi_awvalid,
I3 => \^s_axi_awready\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^s_axi_awready\,
R => \^s_ready_i_reg_0\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(0),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(1),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awprot(2),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(0),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awsize(1),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(0),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awburst(1),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(0),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(1),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(2),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[47]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(3),
Q => \skid_buffer_reg_n_0_[47]\,
R => '0'
);
\skid_buffer_reg[48]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(4),
Q => \skid_buffer_reg_n_0_[48]\,
R => '0'
);
\skid_buffer_reg[49]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(5),
Q => \skid_buffer_reg_n_0_[49]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[50]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(6),
Q => \skid_buffer_reg_n_0_[50]\,
R => '0'
);
\skid_buffer_reg[51]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awlen(7),
Q => \skid_buffer_reg_n_0_[51]\,
R => '0'
);
\skid_buffer_reg[53]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(0),
Q => \skid_buffer_reg_n_0_[53]\,
R => '0'
);
\skid_buffer_reg[54]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(1),
Q => \skid_buffer_reg_n_0_[54]\,
R => '0'
);
\skid_buffer_reg[55]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(2),
Q => \skid_buffer_reg_n_0_[55]\,
R => '0'
);
\skid_buffer_reg[56]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(3),
Q => \skid_buffer_reg_n_0_[56]\,
R => '0'
);
\skid_buffer_reg[57]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(4),
Q => \skid_buffer_reg_n_0_[57]\,
R => '0'
);
\skid_buffer_reg[58]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(5),
Q => \skid_buffer_reg_n_0_[58]\,
R => '0'
);
\skid_buffer_reg[59]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(6),
Q => \skid_buffer_reg_n_0_[59]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[60]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(7),
Q => \skid_buffer_reg_n_0_[60]\,
R => '0'
);
\skid_buffer_reg[61]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(8),
Q => \skid_buffer_reg_n_0_[61]\,
R => '0'
);
\skid_buffer_reg[62]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(9),
Q => \skid_buffer_reg_n_0_[62]\,
R => '0'
);
\skid_buffer_reg[63]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(10),
Q => \skid_buffer_reg_n_0_[63]\,
R => '0'
);
\skid_buffer_reg[64]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awid(11),
Q => \skid_buffer_reg_n_0_[64]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^s_axi_awready\,
D => s_axi_awaddr(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
\wrap_boundary_axaddr_r[0]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"AA8A"
)
port map (
I0 => \^q\(0),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(0)
);
\wrap_boundary_axaddr_r[1]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"8A888AAA"
)
port map (
I0 => \^q\(1),
I1 => \^q\(36),
I2 => \^q\(39),
I3 => \^q\(35),
I4 => \^q\(40),
O => \wrap_boundary_axaddr_r_reg[6]\(1)
);
\wrap_boundary_axaddr_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"A0A0202AAAAA202A"
)
port map (
I0 => \^q\(2),
I1 => \^q\(40),
I2 => \^q\(35),
I3 => \^q\(41),
I4 => \^q\(36),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(2)
);
\wrap_boundary_axaddr_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"020202A2A2A202A2"
)
port map (
I0 => \^q\(3),
I1 => \wrap_boundary_axaddr_r[3]_i_2_n_0\,
I2 => \^q\(36),
I3 => \^q\(40),
I4 => \^q\(35),
I5 => \^q\(39),
O => \wrap_boundary_axaddr_r_reg[6]\(3)
);
\wrap_boundary_axaddr_r[3]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \^q\(41),
I1 => \^q\(35),
I2 => \^q\(42),
O => \wrap_boundary_axaddr_r[3]_i_2_n_0\
);
\wrap_boundary_axaddr_r[4]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"002A882A222AAA2A"
)
port map (
I0 => \^q\(4),
I1 => \^q\(35),
I2 => \^q\(42),
I3 => \^q\(36),
I4 => \^q\(40),
I5 => \^q\(41),
O => \wrap_boundary_axaddr_r_reg[6]\(4)
);
\wrap_boundary_axaddr_r[5]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"2A222AAA"
)
port map (
I0 => \^q\(5),
I1 => \^q\(36),
I2 => \^q\(41),
I3 => \^q\(35),
I4 => \^q\(42),
O => \wrap_boundary_axaddr_r_reg[6]\(5)
);
\wrap_boundary_axaddr_r[6]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"2AAA"
)
port map (
I0 => \^q\(6),
I1 => \^q\(36),
I2 => \^q\(42),
I3 => \^q\(35),
O => \wrap_boundary_axaddr_r_reg[6]\(6)
);
\wrap_cnt_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"BBBBBABBCCCCC0CC"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => D(0)
);
\wrap_cnt_r[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"9A"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(1),
I1 => \^wrap_cnt_r_reg[3]\,
I2 => wrap_second_len(0),
O => D(1)
);
\wrap_cnt_r[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"A6AA"
)
port map (
I0 => \^wrap_second_len_r_reg[3]\(2),
I1 => wrap_second_len(0),
I2 => \^wrap_cnt_r_reg[3]\,
I3 => \^wrap_second_len_r_reg[3]\(1),
O => D(2)
);
\wrap_cnt_r[3]_i_2\: unisim.vcomponents.LUT5
generic map(
INIT => X"AAAAAAAB"
)
port map (
I0 => \wrap_cnt_r[3]_i_3_n_0\,
I1 => \^axaddr_offset_r_reg[1]\,
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \axaddr_offset_r_reg[3]_0\(0),
I4 => \^axaddr_offset_r_reg[2]\,
O => \^wrap_cnt_r_reg[3]\
);
\wrap_cnt_r[3]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0F0F0F0F0F880F0F"
)
port map (
I0 => \axaddr_offset_r[0]_i_2_n_0\,
I1 => \^q\(39),
I2 => \wrap_second_len_r_reg[3]_0\(0),
I3 => \state_reg[1]\(1),
I4 => \^m_valid_i_reg_0\,
I5 => \state_reg[1]\(0),
O => \wrap_cnt_r[3]_i_3_n_0\
);
\wrap_second_len_r[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"4444454444444044"
)
port map (
I0 => \wrap_second_len_r[0]_i_2_n_0\,
I1 => \wrap_second_len_r_reg[3]_0\(0),
I2 => \state_reg[1]\(0),
I3 => \^m_valid_i_reg_0\,
I4 => \state_reg[1]\(1),
I5 => \wrap_second_len_r[0]_i_3_n_0\,
O => \^wrap_second_len_r_reg[3]\(0)
);
\wrap_second_len_r[0]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"AAAAA8080000A808"
)
port map (
I0 => \wrap_second_len_r[0]_i_4_n_0\,
I1 => \^q\(0),
I2 => \^q\(36),
I3 => \^q\(2),
I4 => \^q\(35),
I5 => \axaddr_offset_r[1]_i_2_n_0\,
O => \wrap_second_len_r[0]_i_2_n_0\
);
\wrap_second_len_r[0]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFFFFFFFFFBA"
)
port map (
I0 => \^axaddr_offset_r_reg[2]\,
I1 => \state_reg[1]_rep_0\,
I2 => \axaddr_offset_r_reg[3]_1\(3),
I3 => \wrap_second_len_r[3]_i_2_n_0\,
I4 => \^axaddr_offset_r_reg[0]\,
I5 => \^axaddr_offset_r_reg[1]\,
O => \wrap_second_len_r[0]_i_3_n_0\
);
\wrap_second_len_r[0]_i_4\: unisim.vcomponents.LUT4
generic map(
INIT => X"0020"
)
port map (
I0 => \^q\(39),
I1 => \state_reg[0]_rep\,
I2 => \^m_valid_i_reg_0\,
I3 => \state_reg[1]_rep\,
O => \wrap_second_len_r[0]_i_4_n_0\
);
\wrap_second_len_r[2]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"EE10FFFFEE100000"
)
port map (
I0 => \^axaddr_offset_r_reg[1]\,
I1 => \^axaddr_offset_r_reg[0]\,
I2 => \axaddr_offset_r_reg[3]_0\(0),
I3 => \^axaddr_offset_r_reg[2]\,
I4 => \state_reg[1]_rep_0\,
I5 => \wrap_second_len_r_reg[3]_0\(1),
O => \^wrap_second_len_r_reg[3]\(1)
);
\wrap_second_len_r[3]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"FFFFFFF444444444"
)
port map (
I0 => \state_reg[1]_rep_0\,
I1 => \wrap_second_len_r_reg[3]_0\(2),
I2 => \^axaddr_offset_r_reg[0]\,
I3 => \^axaddr_offset_r_reg[1]\,
I4 => \^axaddr_offset_r_reg[2]\,
I5 => \wrap_second_len_r[3]_i_2_n_0\,
O => \^wrap_second_len_r_reg[3]\(2)
);
\wrap_second_len_r[3]_i_2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EEE222E2"
)
port map (
I0 => \axaddr_offset_r[2]_i_2_n_0\,
I1 => \^q\(35),
I2 => \^q\(4),
I3 => \^q\(36),
I4 => \^q\(6),
I5 => \^axlen_cnt_reg[3]\,
O => \wrap_second_len_r[3]_i_2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\ is
signal \m_payload_i[0]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__1_n_0\ : STD_LOGIC;
signal m_valid_i0 : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_bvalid\ : STD_LOGIC;
signal s_ready_i0 : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \m_payload_i[0]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__1\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__1\ : label is "soft_lutpair79";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_2\ : label is "soft_lutpair78";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__1\ : label is "soft_lutpair84";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__1\ : label is "soft_lutpair83";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__1\ : label is "soft_lutpair82";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__1\ : label is "soft_lutpair81";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__1\ : label is "soft_lutpair80";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__1\ : label is "soft_lutpair80";
begin
s_axi_bvalid <= \^s_axi_bvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\m_payload_i[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__1_n_0\
);
\m_payload_i[10]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__1_n_0\
);
\m_payload_i[11]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__1_n_0\
);
\m_payload_i[12]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__1_n_0\
);
\m_payload_i[13]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
O => p_1_in
);
\m_payload_i[13]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_2_n_0\
);
\m_payload_i[1]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \s_bresp_acc_reg[1]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__1_n_0\
);
\m_payload_i[4]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__1_n_0\
);
\m_payload_i[5]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__1_n_0\
);
\m_payload_i[6]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__1_n_0\
);
\m_payload_i[7]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__1_n_0\
);
\m_payload_i[8]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__1_n_0\
);
\m_payload_i[9]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \out\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__1_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_2_n_0\,
Q => \s_axi_bid[11]\(13),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(1),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(2),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(3),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__1_n_0\,
Q => \s_axi_bid[11]\(9),
R => '0'
);
m_valid_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => s_axi_bready,
I1 => \^s_axi_bvalid\,
I2 => si_rs_bvalid,
I3 => \^skid_buffer_reg[0]_0\,
O => m_valid_i0
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => m_valid_i0,
Q => \^s_axi_bvalid\,
R => \aresetn_d_reg[1]_inv\
);
s_ready_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F4FF"
)
port map (
I0 => si_rs_bvalid,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_bready,
I3 => \^s_axi_bvalid\,
O => s_ready_i0
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => s_ready_i0,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(8),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(9),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(10),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(11),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \s_bresp_acc_reg[1]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(0),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(1),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(2),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(3),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(4),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(5),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(6),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \out\(7),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
port (
s_axi_rvalid : out STD_LOGIC;
\skid_buffer_reg[0]_0\ : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
\aresetn_d_reg[1]_inv\ : in STD_LOGIC;
aclk : in STD_LOGIC;
\aresetn_d_reg[0]\ : in STD_LOGIC;
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ : entity is "axi_register_slice_v2_1_13_axic_register_slice";
end \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\;
architecture STRUCTURE of \decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\ is
signal \m_payload_i[0]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[10]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[11]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[12]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[13]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[14]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[15]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[16]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[17]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[18]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[19]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[1]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[20]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[21]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[22]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[23]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[24]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[25]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[26]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[27]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[28]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[29]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[2]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[30]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[31]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[32]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[33]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[34]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[35]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[36]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[37]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[38]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[39]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[3]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[40]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[41]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[42]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[43]_i_1_n_0\ : STD_LOGIC;
signal \m_payload_i[44]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[45]_i_1__1_n_0\ : STD_LOGIC;
signal \m_payload_i[46]_i_2_n_0\ : STD_LOGIC;
signal \m_payload_i[4]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[5]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[6]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[7]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[8]_i_1__2_n_0\ : STD_LOGIC;
signal \m_payload_i[9]_i_1__2_n_0\ : STD_LOGIC;
signal \m_valid_i_i_1__1_n_0\ : STD_LOGIC;
signal p_1_in : STD_LOGIC;
signal \^s_axi_rvalid\ : STD_LOGIC;
signal \s_ready_i_i_1__2_n_0\ : STD_LOGIC;
signal \^skid_buffer_reg[0]_0\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[0]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[10]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[11]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[12]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[13]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[14]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[15]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[16]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[17]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[18]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[19]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[1]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[20]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[21]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[22]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[23]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[24]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[25]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[26]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[27]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[28]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[29]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[2]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[30]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[31]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[32]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[33]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[34]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[35]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[36]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[37]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[38]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[39]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[3]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[40]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[41]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[42]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[43]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[44]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[45]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[46]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[4]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[5]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[6]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[7]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[8]\ : STD_LOGIC;
signal \skid_buffer_reg_n_0_[9]\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \cnt_read[3]_i_2\ : label is "soft_lutpair85";
attribute SOFT_HLUTNM of \m_payload_i[10]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_payload_i[11]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[12]_i_1__2\ : label is "soft_lutpair103";
attribute SOFT_HLUTNM of \m_payload_i[13]_i_1__2\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[14]_i_1__1\ : label is "soft_lutpair102";
attribute SOFT_HLUTNM of \m_payload_i[15]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[16]_i_1__1\ : label is "soft_lutpair101";
attribute SOFT_HLUTNM of \m_payload_i[17]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[18]_i_1__1\ : label is "soft_lutpair100";
attribute SOFT_HLUTNM of \m_payload_i[19]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[1]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[20]_i_1__1\ : label is "soft_lutpair99";
attribute SOFT_HLUTNM of \m_payload_i[21]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[22]_i_1__1\ : label is "soft_lutpair98";
attribute SOFT_HLUTNM of \m_payload_i[23]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[24]_i_1__1\ : label is "soft_lutpair97";
attribute SOFT_HLUTNM of \m_payload_i[25]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[26]_i_1__1\ : label is "soft_lutpair96";
attribute SOFT_HLUTNM of \m_payload_i[27]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[28]_i_1__1\ : label is "soft_lutpair95";
attribute SOFT_HLUTNM of \m_payload_i[29]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[2]_i_1__2\ : label is "soft_lutpair108";
attribute SOFT_HLUTNM of \m_payload_i[30]_i_1__1\ : label is "soft_lutpair94";
attribute SOFT_HLUTNM of \m_payload_i[31]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[32]_i_1__1\ : label is "soft_lutpair93";
attribute SOFT_HLUTNM of \m_payload_i[33]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[34]_i_1__1\ : label is "soft_lutpair92";
attribute SOFT_HLUTNM of \m_payload_i[35]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[36]_i_1__1\ : label is "soft_lutpair91";
attribute SOFT_HLUTNM of \m_payload_i[37]_i_1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[38]_i_1__1\ : label is "soft_lutpair90";
attribute SOFT_HLUTNM of \m_payload_i[39]_i_1__1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[3]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[40]_i_1\ : label is "soft_lutpair89";
attribute SOFT_HLUTNM of \m_payload_i[41]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[42]_i_1\ : label is "soft_lutpair88";
attribute SOFT_HLUTNM of \m_payload_i[43]_i_1\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[44]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[45]_i_1__1\ : label is "soft_lutpair87";
attribute SOFT_HLUTNM of \m_payload_i[46]_i_2\ : label is "soft_lutpair86";
attribute SOFT_HLUTNM of \m_payload_i[4]_i_1__2\ : label is "soft_lutpair107";
attribute SOFT_HLUTNM of \m_payload_i[5]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[6]_i_1__2\ : label is "soft_lutpair106";
attribute SOFT_HLUTNM of \m_payload_i[7]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[8]_i_1__2\ : label is "soft_lutpair105";
attribute SOFT_HLUTNM of \m_payload_i[9]_i_1__2\ : label is "soft_lutpair104";
attribute SOFT_HLUTNM of \m_valid_i_i_1__1\ : label is "soft_lutpair85";
begin
s_axi_rvalid <= \^s_axi_rvalid\;
\skid_buffer_reg[0]_0\ <= \^skid_buffer_reg[0]_0\;
\cnt_read[3]_i_2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => \^skid_buffer_reg[0]_0\,
I1 => \cnt_read_reg[4]_rep__0\,
O => \cnt_read_reg[3]_rep__0\
);
\m_payload_i[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[0]\,
O => \m_payload_i[0]_i_1__2_n_0\
);
\m_payload_i[10]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[10]\,
O => \m_payload_i[10]_i_1__2_n_0\
);
\m_payload_i[11]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[11]\,
O => \m_payload_i[11]_i_1__2_n_0\
);
\m_payload_i[12]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[12]\,
O => \m_payload_i[12]_i_1__2_n_0\
);
\m_payload_i[13]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(13),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[13]\,
O => \m_payload_i[13]_i_1__2_n_0\
);
\m_payload_i[14]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(14),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[14]\,
O => \m_payload_i[14]_i_1__1_n_0\
);
\m_payload_i[15]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(15),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[15]\,
O => \m_payload_i[15]_i_1__1_n_0\
);
\m_payload_i[16]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(16),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[16]\,
O => \m_payload_i[16]_i_1__1_n_0\
);
\m_payload_i[17]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(17),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[17]\,
O => \m_payload_i[17]_i_1__1_n_0\
);
\m_payload_i[18]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(18),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[18]\,
O => \m_payload_i[18]_i_1__1_n_0\
);
\m_payload_i[19]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(19),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[19]\,
O => \m_payload_i[19]_i_1__1_n_0\
);
\m_payload_i[1]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[1]\,
O => \m_payload_i[1]_i_1__2_n_0\
);
\m_payload_i[20]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(20),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[20]\,
O => \m_payload_i[20]_i_1__1_n_0\
);
\m_payload_i[21]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(21),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[21]\,
O => \m_payload_i[21]_i_1__1_n_0\
);
\m_payload_i[22]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(22),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[22]\,
O => \m_payload_i[22]_i_1__1_n_0\
);
\m_payload_i[23]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(23),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[23]\,
O => \m_payload_i[23]_i_1__1_n_0\
);
\m_payload_i[24]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(24),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[24]\,
O => \m_payload_i[24]_i_1__1_n_0\
);
\m_payload_i[25]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(25),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[25]\,
O => \m_payload_i[25]_i_1__1_n_0\
);
\m_payload_i[26]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(26),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[26]\,
O => \m_payload_i[26]_i_1__1_n_0\
);
\m_payload_i[27]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(27),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[27]\,
O => \m_payload_i[27]_i_1__1_n_0\
);
\m_payload_i[28]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(28),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[28]\,
O => \m_payload_i[28]_i_1__1_n_0\
);
\m_payload_i[29]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(29),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[29]\,
O => \m_payload_i[29]_i_1__1_n_0\
);
\m_payload_i[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[2]\,
O => \m_payload_i[2]_i_1__2_n_0\
);
\m_payload_i[30]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(30),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[30]\,
O => \m_payload_i[30]_i_1__1_n_0\
);
\m_payload_i[31]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(31),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[31]\,
O => \m_payload_i[31]_i_1__1_n_0\
);
\m_payload_i[32]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(32),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[32]\,
O => \m_payload_i[32]_i_1__1_n_0\
);
\m_payload_i[33]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(33),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[33]\,
O => \m_payload_i[33]_i_1__1_n_0\
);
\m_payload_i[34]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(0),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[34]\,
O => \m_payload_i[34]_i_1__1_n_0\
);
\m_payload_i[35]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(1),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[35]\,
O => \m_payload_i[35]_i_1__1_n_0\
);
\m_payload_i[36]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(2),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[36]\,
O => \m_payload_i[36]_i_1__1_n_0\
);
\m_payload_i[37]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[37]\,
O => \m_payload_i[37]_i_1_n_0\
);
\m_payload_i[38]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[38]\,
O => \m_payload_i[38]_i_1__1_n_0\
);
\m_payload_i[39]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[39]\,
O => \m_payload_i[39]_i_1__1_n_0\
);
\m_payload_i[3]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(3),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[3]\,
O => \m_payload_i[3]_i_1__2_n_0\
);
\m_payload_i[40]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[40]\,
O => \m_payload_i[40]_i_1_n_0\
);
\m_payload_i[41]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[41]\,
O => \m_payload_i[41]_i_1_n_0\
);
\m_payload_i[42]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[42]\,
O => \m_payload_i[42]_i_1_n_0\
);
\m_payload_i[43]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[43]\,
O => \m_payload_i[43]_i_1_n_0\
);
\m_payload_i[44]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(10),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[44]\,
O => \m_payload_i[44]_i_1__1_n_0\
);
\m_payload_i[45]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(11),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[45]\,
O => \m_payload_i[45]_i_1__1_n_0\
);
\m_payload_i[46]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"B"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
O => p_1_in
);
\m_payload_i[46]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => r_push_r_reg(12),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[46]\,
O => \m_payload_i[46]_i_2_n_0\
);
\m_payload_i[4]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(4),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[4]\,
O => \m_payload_i[4]_i_1__2_n_0\
);
\m_payload_i[5]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(5),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[5]\,
O => \m_payload_i[5]_i_1__2_n_0\
);
\m_payload_i[6]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(6),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[6]\,
O => \m_payload_i[6]_i_1__2_n_0\
);
\m_payload_i[7]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(7),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[7]\,
O => \m_payload_i[7]_i_1__2_n_0\
);
\m_payload_i[8]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(8),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[8]\,
O => \m_payload_i[8]_i_1__2_n_0\
);
\m_payload_i[9]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => \cnt_read_reg[4]\(9),
I1 => \^skid_buffer_reg[0]_0\,
I2 => \skid_buffer_reg_n_0_[9]\,
O => \m_payload_i[9]_i_1__2_n_0\
);
\m_payload_i_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[0]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(0),
R => '0'
);
\m_payload_i_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[10]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(10),
R => '0'
);
\m_payload_i_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[11]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(11),
R => '0'
);
\m_payload_i_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[12]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(12),
R => '0'
);
\m_payload_i_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[13]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(13),
R => '0'
);
\m_payload_i_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[14]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(14),
R => '0'
);
\m_payload_i_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[15]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(15),
R => '0'
);
\m_payload_i_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[16]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(16),
R => '0'
);
\m_payload_i_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[17]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(17),
R => '0'
);
\m_payload_i_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[18]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(18),
R => '0'
);
\m_payload_i_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[19]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(19),
R => '0'
);
\m_payload_i_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[1]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(1),
R => '0'
);
\m_payload_i_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[20]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(20),
R => '0'
);
\m_payload_i_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[21]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(21),
R => '0'
);
\m_payload_i_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[22]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(22),
R => '0'
);
\m_payload_i_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[23]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(23),
R => '0'
);
\m_payload_i_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[24]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(24),
R => '0'
);
\m_payload_i_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[25]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(25),
R => '0'
);
\m_payload_i_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[26]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(26),
R => '0'
);
\m_payload_i_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[27]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(27),
R => '0'
);
\m_payload_i_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[28]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(28),
R => '0'
);
\m_payload_i_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[29]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(29),
R => '0'
);
\m_payload_i_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[2]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(2),
R => '0'
);
\m_payload_i_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[30]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(30),
R => '0'
);
\m_payload_i_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[31]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(31),
R => '0'
);
\m_payload_i_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[32]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(32),
R => '0'
);
\m_payload_i_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[33]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(33),
R => '0'
);
\m_payload_i_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[34]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(34),
R => '0'
);
\m_payload_i_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[35]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(35),
R => '0'
);
\m_payload_i_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[36]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(36),
R => '0'
);
\m_payload_i_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[37]_i_1_n_0\,
Q => \s_axi_rid[11]\(37),
R => '0'
);
\m_payload_i_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[38]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(38),
R => '0'
);
\m_payload_i_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[39]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(39),
R => '0'
);
\m_payload_i_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[3]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(3),
R => '0'
);
\m_payload_i_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[40]_i_1_n_0\,
Q => \s_axi_rid[11]\(40),
R => '0'
);
\m_payload_i_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[41]_i_1_n_0\,
Q => \s_axi_rid[11]\(41),
R => '0'
);
\m_payload_i_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[42]_i_1_n_0\,
Q => \s_axi_rid[11]\(42),
R => '0'
);
\m_payload_i_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[43]_i_1_n_0\,
Q => \s_axi_rid[11]\(43),
R => '0'
);
\m_payload_i_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[44]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(44),
R => '0'
);
\m_payload_i_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[45]_i_1__1_n_0\,
Q => \s_axi_rid[11]\(45),
R => '0'
);
\m_payload_i_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[46]_i_2_n_0\,
Q => \s_axi_rid[11]\(46),
R => '0'
);
\m_payload_i_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[4]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(4),
R => '0'
);
\m_payload_i_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[5]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(5),
R => '0'
);
\m_payload_i_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[6]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(6),
R => '0'
);
\m_payload_i_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[7]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(7),
R => '0'
);
\m_payload_i_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[8]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(8),
R => '0'
);
\m_payload_i_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => p_1_in,
D => \m_payload_i[9]_i_1__2_n_0\,
Q => \s_axi_rid[11]\(9),
R => '0'
);
\m_valid_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4FFF"
)
port map (
I0 => s_axi_rready,
I1 => \^s_axi_rvalid\,
I2 => \cnt_read_reg[4]_rep__0\,
I3 => \^skid_buffer_reg[0]_0\,
O => \m_valid_i_i_1__1_n_0\
);
m_valid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \m_valid_i_i_1__1_n_0\,
Q => \^s_axi_rvalid\,
R => \aresetn_d_reg[1]_inv\
);
\s_ready_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F8FF"
)
port map (
I0 => \cnt_read_reg[4]_rep__0\,
I1 => \^skid_buffer_reg[0]_0\,
I2 => s_axi_rready,
I3 => \^s_axi_rvalid\,
O => \s_ready_i_i_1__2_n_0\
);
s_ready_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => \s_ready_i_i_1__2_n_0\,
Q => \^skid_buffer_reg[0]_0\,
R => \aresetn_d_reg[0]\
);
\skid_buffer_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(0),
Q => \skid_buffer_reg_n_0_[0]\,
R => '0'
);
\skid_buffer_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(10),
Q => \skid_buffer_reg_n_0_[10]\,
R => '0'
);
\skid_buffer_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(11),
Q => \skid_buffer_reg_n_0_[11]\,
R => '0'
);
\skid_buffer_reg[12]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(12),
Q => \skid_buffer_reg_n_0_[12]\,
R => '0'
);
\skid_buffer_reg[13]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(13),
Q => \skid_buffer_reg_n_0_[13]\,
R => '0'
);
\skid_buffer_reg[14]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(14),
Q => \skid_buffer_reg_n_0_[14]\,
R => '0'
);
\skid_buffer_reg[15]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(15),
Q => \skid_buffer_reg_n_0_[15]\,
R => '0'
);
\skid_buffer_reg[16]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(16),
Q => \skid_buffer_reg_n_0_[16]\,
R => '0'
);
\skid_buffer_reg[17]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(17),
Q => \skid_buffer_reg_n_0_[17]\,
R => '0'
);
\skid_buffer_reg[18]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(18),
Q => \skid_buffer_reg_n_0_[18]\,
R => '0'
);
\skid_buffer_reg[19]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(19),
Q => \skid_buffer_reg_n_0_[19]\,
R => '0'
);
\skid_buffer_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(1),
Q => \skid_buffer_reg_n_0_[1]\,
R => '0'
);
\skid_buffer_reg[20]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(20),
Q => \skid_buffer_reg_n_0_[20]\,
R => '0'
);
\skid_buffer_reg[21]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(21),
Q => \skid_buffer_reg_n_0_[21]\,
R => '0'
);
\skid_buffer_reg[22]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(22),
Q => \skid_buffer_reg_n_0_[22]\,
R => '0'
);
\skid_buffer_reg[23]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(23),
Q => \skid_buffer_reg_n_0_[23]\,
R => '0'
);
\skid_buffer_reg[24]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(24),
Q => \skid_buffer_reg_n_0_[24]\,
R => '0'
);
\skid_buffer_reg[25]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(25),
Q => \skid_buffer_reg_n_0_[25]\,
R => '0'
);
\skid_buffer_reg[26]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(26),
Q => \skid_buffer_reg_n_0_[26]\,
R => '0'
);
\skid_buffer_reg[27]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(27),
Q => \skid_buffer_reg_n_0_[27]\,
R => '0'
);
\skid_buffer_reg[28]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(28),
Q => \skid_buffer_reg_n_0_[28]\,
R => '0'
);
\skid_buffer_reg[29]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(29),
Q => \skid_buffer_reg_n_0_[29]\,
R => '0'
);
\skid_buffer_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(2),
Q => \skid_buffer_reg_n_0_[2]\,
R => '0'
);
\skid_buffer_reg[30]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(30),
Q => \skid_buffer_reg_n_0_[30]\,
R => '0'
);
\skid_buffer_reg[31]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(31),
Q => \skid_buffer_reg_n_0_[31]\,
R => '0'
);
\skid_buffer_reg[32]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(32),
Q => \skid_buffer_reg_n_0_[32]\,
R => '0'
);
\skid_buffer_reg[33]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(33),
Q => \skid_buffer_reg_n_0_[33]\,
R => '0'
);
\skid_buffer_reg[34]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(0),
Q => \skid_buffer_reg_n_0_[34]\,
R => '0'
);
\skid_buffer_reg[35]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(1),
Q => \skid_buffer_reg_n_0_[35]\,
R => '0'
);
\skid_buffer_reg[36]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(2),
Q => \skid_buffer_reg_n_0_[36]\,
R => '0'
);
\skid_buffer_reg[37]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(3),
Q => \skid_buffer_reg_n_0_[37]\,
R => '0'
);
\skid_buffer_reg[38]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(4),
Q => \skid_buffer_reg_n_0_[38]\,
R => '0'
);
\skid_buffer_reg[39]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(5),
Q => \skid_buffer_reg_n_0_[39]\,
R => '0'
);
\skid_buffer_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(3),
Q => \skid_buffer_reg_n_0_[3]\,
R => '0'
);
\skid_buffer_reg[40]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(6),
Q => \skid_buffer_reg_n_0_[40]\,
R => '0'
);
\skid_buffer_reg[41]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(7),
Q => \skid_buffer_reg_n_0_[41]\,
R => '0'
);
\skid_buffer_reg[42]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(8),
Q => \skid_buffer_reg_n_0_[42]\,
R => '0'
);
\skid_buffer_reg[43]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(9),
Q => \skid_buffer_reg_n_0_[43]\,
R => '0'
);
\skid_buffer_reg[44]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(10),
Q => \skid_buffer_reg_n_0_[44]\,
R => '0'
);
\skid_buffer_reg[45]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(11),
Q => \skid_buffer_reg_n_0_[45]\,
R => '0'
);
\skid_buffer_reg[46]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => r_push_r_reg(12),
Q => \skid_buffer_reg_n_0_[46]\,
R => '0'
);
\skid_buffer_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(4),
Q => \skid_buffer_reg_n_0_[4]\,
R => '0'
);
\skid_buffer_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(5),
Q => \skid_buffer_reg_n_0_[5]\,
R => '0'
);
\skid_buffer_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(6),
Q => \skid_buffer_reg_n_0_[6]\,
R => '0'
);
\skid_buffer_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(7),
Q => \skid_buffer_reg_n_0_[7]\,
R => '0'
);
\skid_buffer_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(8),
Q => \skid_buffer_reg_n_0_[8]\,
R => '0'
);
\skid_buffer_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => \^skid_buffer_reg[0]_0\,
D => \cnt_read_reg[4]\(9),
Q => \skid_buffer_reg_n_0_[9]\,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
port (
si_rs_bvalid : out STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : out STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
\skid_buffer_reg[1]\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
areset_d1 : in STD_LOGIC;
aclk : in STD_LOGIC;
b_push : in STD_LOGIC;
si_rs_bready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 19 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel is
signal bid_fifo_0_n_2 : STD_LOGIC;
signal bid_fifo_0_n_3 : STD_LOGIC;
signal bid_fifo_0_n_6 : STD_LOGIC;
signal \bresp_cnt[7]_i_3_n_0\ : STD_LOGIC;
signal \bresp_cnt_reg__0\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal bresp_push : STD_LOGIC;
signal cnt_read : STD_LOGIC_VECTOR ( 1 downto 0 );
signal mhandshake : STD_LOGIC;
signal mhandshake_r : STD_LOGIC;
signal p_0_in : STD_LOGIC_VECTOR ( 7 downto 0 );
signal s_bresp_acc0 : STD_LOGIC;
signal \s_bresp_acc[0]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc[1]_i_1_n_0\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[0]\ : STD_LOGIC;
signal \s_bresp_acc_reg_n_0_[1]\ : STD_LOGIC;
signal shandshake : STD_LOGIC;
signal shandshake_r : STD_LOGIC;
signal \^si_rs_bvalid\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \bresp_cnt[1]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[2]_i_1\ : label is "soft_lutpair121";
attribute SOFT_HLUTNM of \bresp_cnt[3]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[4]_i_1\ : label is "soft_lutpair119";
attribute SOFT_HLUTNM of \bresp_cnt[6]_i_1\ : label is "soft_lutpair120";
attribute SOFT_HLUTNM of \bresp_cnt[7]_i_2\ : label is "soft_lutpair120";
begin
si_rs_bvalid <= \^si_rs_bvalid\;
bid_fifo_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
SR(0) => s_bresp_acc0,
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\bresp_cnt_reg[7]\(7 downto 0) => \bresp_cnt_reg__0\(7 downto 0),
bvalid_i_reg => bid_fifo_0_n_6,
bvalid_i_reg_0 => \^si_rs_bvalid\,
\cnt_read_reg[0]_0\ => bid_fifo_0_n_3,
\cnt_read_reg[0]_rep__0_0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1_0\ => \cnt_read_reg[1]_rep__1\,
\in\(19 downto 0) => \in\(19 downto 0),
mhandshake_r => mhandshake_r,
\out\(11 downto 0) => \out\(11 downto 0),
sel => bresp_push,
shandshake_r => shandshake_r,
si_rs_bready => si_rs_bready
);
\bresp_cnt[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \bresp_cnt_reg__0\(0),
O => p_0_in(0)
);
\bresp_cnt[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(1),
I1 => \bresp_cnt_reg__0\(0),
O => p_0_in(1)
);
\bresp_cnt[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(2),
I1 => \bresp_cnt_reg__0\(0),
I2 => \bresp_cnt_reg__0\(1),
O => p_0_in(2)
);
\bresp_cnt[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6AAA"
)
port map (
I0 => \bresp_cnt_reg__0\(3),
I1 => \bresp_cnt_reg__0\(1),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(2),
O => p_0_in(3)
);
\bresp_cnt[4]_i_1\: unisim.vcomponents.LUT5
generic map(
INIT => X"6AAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(4),
I1 => \bresp_cnt_reg__0\(2),
I2 => \bresp_cnt_reg__0\(0),
I3 => \bresp_cnt_reg__0\(1),
I4 => \bresp_cnt_reg__0\(3),
O => p_0_in(4)
);
\bresp_cnt[5]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"6AAAAAAAAAAAAAAA"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => p_0_in(5)
);
\bresp_cnt[6]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \bresp_cnt_reg__0\(6),
I1 => \bresp_cnt[7]_i_3_n_0\,
O => p_0_in(6)
);
\bresp_cnt[7]_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"6A"
)
port map (
I0 => \bresp_cnt_reg__0\(7),
I1 => \bresp_cnt[7]_i_3_n_0\,
I2 => \bresp_cnt_reg__0\(6),
O => p_0_in(7)
);
\bresp_cnt[7]_i_3\: unisim.vcomponents.LUT6
generic map(
INIT => X"8000000000000000"
)
port map (
I0 => \bresp_cnt_reg__0\(5),
I1 => \bresp_cnt_reg__0\(3),
I2 => \bresp_cnt_reg__0\(1),
I3 => \bresp_cnt_reg__0\(0),
I4 => \bresp_cnt_reg__0\(2),
I5 => \bresp_cnt_reg__0\(4),
O => \bresp_cnt[7]_i_3_n_0\
);
\bresp_cnt_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(0),
Q => \bresp_cnt_reg__0\(0),
R => s_bresp_acc0
);
\bresp_cnt_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(1),
Q => \bresp_cnt_reg__0\(1),
R => s_bresp_acc0
);
\bresp_cnt_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(2),
Q => \bresp_cnt_reg__0\(2),
R => s_bresp_acc0
);
\bresp_cnt_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(3),
Q => \bresp_cnt_reg__0\(3),
R => s_bresp_acc0
);
\bresp_cnt_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(4),
Q => \bresp_cnt_reg__0\(4),
R => s_bresp_acc0
);
\bresp_cnt_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(5),
Q => \bresp_cnt_reg__0\(5),
R => s_bresp_acc0
);
\bresp_cnt_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(6),
Q => \bresp_cnt_reg__0\(6),
R => s_bresp_acc0
);
\bresp_cnt_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => mhandshake_r,
D => p_0_in(7),
Q => \bresp_cnt_reg__0\(7),
R => s_bresp_acc0
);
bresp_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized0\
port map (
D(0) => bid_fifo_0_n_2,
Q(1 downto 0) => cnt_read(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\bresp_cnt_reg[3]\ => bid_fifo_0_n_3,
\in\(1) => \s_bresp_acc_reg_n_0_[1]\,
\in\(0) => \s_bresp_acc_reg_n_0_[0]\,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
mhandshake => mhandshake,
mhandshake_r => mhandshake_r,
sel => bresp_push,
shandshake_r => shandshake_r,
\skid_buffer_reg[1]\(1 downto 0) => \skid_buffer_reg[1]\(1 downto 0)
);
bvalid_i_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => bid_fifo_0_n_6,
Q => \^si_rs_bvalid\,
R => '0'
);
mhandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => mhandshake,
Q => mhandshake_r,
R => areset_d1
);
\s_bresp_acc[0]_i_1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00000000EACEAAAA"
)
port map (
I0 => \s_bresp_acc_reg_n_0_[0]\,
I1 => m_axi_bresp(0),
I2 => m_axi_bresp(1),
I3 => \s_bresp_acc_reg_n_0_[1]\,
I4 => mhandshake,
I5 => s_bresp_acc0,
O => \s_bresp_acc[0]_i_1_n_0\
);
\s_bresp_acc[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00EC"
)
port map (
I0 => m_axi_bresp(1),
I1 => \s_bresp_acc_reg_n_0_[1]\,
I2 => mhandshake,
I3 => s_bresp_acc0,
O => \s_bresp_acc[1]_i_1_n_0\
);
\s_bresp_acc_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[0]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[0]\,
R => '0'
);
\s_bresp_acc_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \s_bresp_acc[1]_i_1_n_0\,
Q => \s_bresp_acc_reg_n_0_[1]\,
R => '0'
);
shandshake_r_i_1: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => \^si_rs_bvalid\,
I1 => si_rs_bready,
O => shandshake
);
shandshake_r_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => shandshake,
Q => shandshake_r,
R => areset_d1
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
port (
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
\sel_first__0\ : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axlen_cnt_reg[7]\ : out STD_LOGIC;
\state_reg[1]_rep\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\axlen_cnt_reg[4]\ : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
wrap_next_pending : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_1 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_2 : in STD_LOGIC;
sel_first_reg_3 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 21 downto 0 );
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 3 downto 0 );
\next\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\state_reg[0]_rep\ : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_21 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd
port map (
CO(0) => CO(0),
D(3 downto 0) => D(3 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(3 downto 0) => Q(3 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[11]_0\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
\axlen_cnt_reg[4]_0\ => \axlen_cnt_reg[4]\,
\axlen_cnt_reg[7]_0\ => \axlen_cnt_reg[7]\,
incr_next_pending => incr_next_pending,
\m_axi_awaddr[1]\ => incr_cmd_0_n_21,
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(9 downto 8) => \m_payload_i_reg[51]\(21 downto 20),
\m_payload_i_reg[51]\(7) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(6 downto 4) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_1,
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_2,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
\memory_reg[3][0]_srl4_i_2\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[1]_rep\
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd
port map (
E(0) => E(0),
aclk => aclk,
axaddr_incr_reg(7 downto 0) => axaddr_incr_reg(11 downto 4),
\axaddr_incr_reg[3]\(2 downto 1) => \^axaddr_incr_reg[3]\(3 downto 2),
\axaddr_incr_reg[3]\(0) => \^axaddr_incr_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
\next\ => \next\,
next_pending_r_reg_0 => next_pending_r_reg_0,
next_pending_r_reg_1 => next_pending_r_reg_2,
sel_first_reg_0 => \sel_first__0\,
sel_first_reg_1 => sel_first_reg_3,
sel_first_reg_2 => incr_cmd_0_n_21,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
port (
next_pending_r_reg : out STD_LOGIC;
wrap_next_pending : out STD_LOGIC;
sel_first_reg_0 : out STD_LOGIC;
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC;
sel_first_reg_1 : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
next_pending_r_reg_0 : out STD_LOGIC;
r_rlast : out STD_LOGIC;
\state_reg[0]_rep\ : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
incr_next_pending : in STD_LOGIC;
aclk : in STD_LOGIC;
sel_first_i : in STD_LOGIC;
\m_payload_i_reg[39]\ : in STD_LOGIC;
\m_payload_i_reg[39]_0\ : in STD_LOGIC;
sel_first_reg_2 : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first_reg_3 : in STD_LOGIC;
sel_first_reg_4 : in STD_LOGIC;
\state_reg[0]\ : in STD_LOGIC;
\m_payload_i_reg[47]\ : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[51]\ : in STD_LOGIC_VECTOR ( 23 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\state_reg[1]_rep_0\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 1 downto 0 );
\axaddr_offset_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[6]\ : in STD_LOGIC_VECTOR ( 6 downto 0 );
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 : entity is "axi_protocol_converter_v2_1_13_b2s_cmd_translator";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1 is
signal axaddr_incr_reg : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \^axaddr_incr_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \axaddr_incr_reg_11__s_net_1\ : STD_LOGIC;
signal incr_cmd_0_n_16 : STD_LOGIC;
signal incr_cmd_0_n_17 : STD_LOGIC;
signal s_axburst_eq0 : STD_LOGIC;
signal s_axburst_eq1 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of r_rlast_r_i_1 : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \state[1]_i_3\ : label is "soft_lutpair5";
begin
\axaddr_incr_reg[11]\ <= \axaddr_incr_reg_11__s_net_1\;
\axaddr_incr_reg[3]\(3 downto 0) <= \^axaddr_incr_reg[3]\(3 downto 0);
incr_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_incr_cmd_2
port map (
CO(0) => CO(0),
D(1 downto 0) => D(1 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(1 downto 0) => Q(1 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]_0\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]_0\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[11]_1\ => \axaddr_incr_reg_11__s_net_1\,
\axaddr_incr_reg[3]_0\(3 downto 0) => \^axaddr_incr_reg[3]\(3 downto 0),
incr_next_pending => incr_next_pending,
\m_axi_araddr[2]\ => incr_cmd_0_n_17,
\m_axi_araddr[5]\ => incr_cmd_0_n_16,
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(12 downto 9) => \m_payload_i_reg[51]\(23 downto 20),
\m_payload_i_reg[51]\(8) => \m_payload_i_reg[51]\(18),
\m_payload_i_reg[51]\(7 downto 5) => \m_payload_i_reg[51]\(14 downto 12),
\m_payload_i_reg[51]\(4) => \m_payload_i_reg[51]\(5),
\m_payload_i_reg[51]\(3 downto 0) => \m_payload_i_reg[51]\(3 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
next_pending_r_reg_0 => next_pending_r_reg,
next_pending_r_reg_1 => next_pending_r_reg_0,
sel_first_reg_0 => sel_first_reg_2,
sel_first_reg_1 => sel_first_reg_3,
\state_reg[0]\ => \state_reg[0]\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0)
);
r_rlast_r_i_1: unisim.vcomponents.LUT3
generic map(
INIT => X"1D"
)
port map (
I0 => s_axburst_eq0,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq1,
O => r_rlast
);
s_axburst_eq0_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]\,
Q => s_axburst_eq0,
R => '0'
);
s_axburst_eq1_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[39]_0\,
Q => s_axburst_eq1,
R => '0'
);
sel_first_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => sel_first_i,
Q => sel_first_reg_0,
R => '0'
);
\state[1]_i_3\: unisim.vcomponents.LUT3
generic map(
INIT => X"B8"
)
port map (
I0 => s_axburst_eq1,
I1 => \m_payload_i_reg[51]\(15),
I2 => s_axburst_eq0,
O => \state_reg[0]_rep\
);
wrap_cmd_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wrap_cmd_3
port map (
E(0) => E(0),
aclk => aclk,
\axaddr_incr_reg[11]\(6 downto 1) => axaddr_incr_reg(11 downto 6),
\axaddr_incr_reg[11]\(0) => axaddr_incr_reg(4),
\axaddr_incr_reg[3]\(2) => \^axaddr_incr_reg[3]\(3),
\axaddr_incr_reg[3]\(1 downto 0) => \^axaddr_incr_reg[3]\(1 downto 0),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \axaddr_offset_r_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_0\(3 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\(18 downto 14) => \m_payload_i_reg[51]\(19 downto 15),
\m_payload_i_reg[47]\(13 downto 0) => \m_payload_i_reg[51]\(13 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]\(6 downto 0),
m_valid_i_reg(0) => m_valid_i_reg(0),
sel_first_reg_0 => sel_first_reg_1,
sel_first_reg_1 => sel_first_reg_4,
sel_first_reg_2 => incr_cmd_0_n_16,
sel_first_reg_3 => incr_cmd_0_n_17,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]_0\(3 downto 0) => \wrap_second_len_r_reg[3]\(3 downto 0),
\wrap_second_len_r_reg[3]_1\(3 downto 0) => \wrap_second_len_r_reg[3]_0\(3 downto 0),
\wrap_second_len_r_reg[3]_2\(3 downto 0) => \wrap_second_len_r_reg[3]_1\(3 downto 0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
port (
\state_reg[1]_rep\ : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_valid_i_reg : out STD_LOGIC;
\out\ : out STD_LOGIC_VECTOR ( 33 downto 0 );
\skid_buffer_reg[46]\ : out STD_LOGIC_VECTOR ( 12 downto 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
aclk : in STD_LOGIC;
r_rlast : in STD_LOGIC;
s_ready_i_reg : in STD_LOGIC;
si_rs_rready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
areset_d1 : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 11 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel is
signal \^m_valid_i_reg\ : STD_LOGIC;
signal r_push_r : STD_LOGIC;
signal rd_data_fifo_0_n_0 : STD_LOGIC;
signal rd_data_fifo_0_n_2 : STD_LOGIC;
signal rd_data_fifo_0_n_3 : STD_LOGIC;
signal rd_data_fifo_0_n_5 : STD_LOGIC;
signal trans_in : STD_LOGIC_VECTOR ( 12 downto 0 );
signal transaction_fifo_0_n_1 : STD_LOGIC;
signal wr_en0 : STD_LOGIC;
begin
m_valid_i_reg <= \^m_valid_i_reg\;
\r_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(0),
Q => trans_in(1),
R => '0'
);
\r_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(10),
Q => trans_in(11),
R => '0'
);
\r_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(11),
Q => trans_in(12),
R => '0'
);
\r_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(1),
Q => trans_in(2),
R => '0'
);
\r_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(2),
Q => trans_in(3),
R => '0'
);
\r_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(3),
Q => trans_in(4),
R => '0'
);
\r_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(4),
Q => trans_in(5),
R => '0'
);
\r_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(5),
Q => trans_in(6),
R => '0'
);
\r_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(6),
Q => trans_in(7),
R => '0'
);
\r_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(7),
Q => trans_in(8),
R => '0'
);
\r_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(8),
Q => trans_in(9),
R => '0'
);
\r_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => D(9),
Q => trans_in(10),
R => '0'
);
r_push_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \state_reg[1]_rep_0\,
Q => r_push_r,
R => '0'
);
r_rlast_r_reg: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => r_rlast,
Q => trans_in(0),
R => '0'
);
rd_data_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized1\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[3]_rep__2_0\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__0_0\ => \^m_valid_i_reg\,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\cnt_read_reg[4]_rep__2_1\ => rd_data_fifo_0_n_3,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\(33 downto 0) => \out\(33 downto 0),
s_ready_i_reg => s_ready_i_reg,
s_ready_i_reg_0 => transaction_fifo_0_n_1,
si_rs_rready => si_rs_rready,
\state_reg[1]_rep\ => rd_data_fifo_0_n_5,
wr_en0 => wr_en0
);
transaction_fifo_0: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_simple_fifo__parameterized2\
port map (
aclk => aclk,
areset_d1 => areset_d1,
\cnt_read_reg[0]_rep__2\ => rd_data_fifo_0_n_5,
\cnt_read_reg[0]_rep__2_0\ => rd_data_fifo_0_n_3,
\cnt_read_reg[3]_rep__2\ => rd_data_fifo_0_n_0,
\cnt_read_reg[4]_rep__2\ => transaction_fifo_0_n_1,
\cnt_read_reg[4]_rep__2_0\ => rd_data_fifo_0_n_2,
\in\(12 downto 0) => trans_in(12 downto 0),
m_valid_i_reg => \^m_valid_i_reg\,
r_push_r => r_push_r,
s_ready_i_reg => s_ready_i_reg,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 0) => \skid_buffer_reg[46]\(12 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
wr_en0 => wr_en0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
port (
s_axi_awready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
si_rs_awvalid : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
si_rs_bready : out STD_LOGIC;
si_rs_arvalid : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
si_rs_rready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 58 downto 0 );
\s_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 58 downto 0 );
\axaddr_incr_reg[11]\ : out STD_LOGIC_VECTOR ( 7 downto 0 );
CO : out STD_LOGIC_VECTOR ( 0 to 0 );
O : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[11]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[7]_0\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]\ : out STD_LOGIC;
axaddr_offset : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]\ : out STD_LOGIC;
next_pending_r_reg : out STD_LOGIC;
next_pending_r_reg_0 : out STD_LOGIC;
\wrap_cnt_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_cnt_r_reg[3]_1\ : out STD_LOGIC;
axaddr_offset_0 : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axlen_cnt_reg[3]_0\ : out STD_LOGIC;
next_pending_r_reg_1 : out STD_LOGIC;
next_pending_r_reg_2 : out STD_LOGIC;
\cnt_read_reg[3]_rep__0\ : out STD_LOGIC;
\axaddr_offset_r_reg[3]\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC;
\wrap_boundary_axaddr_r_reg[6]_0\ : out STD_LOGIC_VECTOR ( 6 downto 0 );
\m_axi_awaddr[10]\ : out STD_LOGIC;
\m_axi_araddr[10]\ : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
\state_reg[0]_rep\ : in STD_LOGIC;
\state_reg[1]_rep\ : in STD_LOGIC;
\state_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
\cnt_read_reg[4]_rep__0\ : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
b_push : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
S : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\state_reg[1]_0\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_0\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\wrap_second_len_r_reg[3]_2\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
wrap_second_len_1 : in STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_3\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep_1\ : in STD_LOGIC;
\axaddr_offset_r_reg[3]_4\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\state_reg[0]_rep_0\ : in STD_LOGIC;
\state_reg[1]_rep_2\ : in STD_LOGIC;
sel_first : in STD_LOGIC;
sel_first_2 : in STD_LOGIC;
si_rs_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
\out\ : in STD_LOGIC_VECTOR ( 11 downto 0 );
\s_bresp_acc_reg[1]\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
r_push_r_reg : in STD_LOGIC_VECTOR ( 12 downto 0 );
\cnt_read_reg[4]\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
axaddr_incr_reg : in STD_LOGIC_VECTOR ( 3 downto 0 );
\axaddr_incr_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_valid_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice is
signal ar_pipe_n_2 : STD_LOGIC;
signal aw_pipe_n_1 : STD_LOGIC;
signal aw_pipe_n_97 : STD_LOGIC;
begin
ar_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice
port map (
Q(58 downto 0) => \s_arid_r_reg[11]\(58 downto 0),
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[0]_0\ => aw_pipe_n_97,
\axaddr_incr_reg[11]\(3 downto 0) => \axaddr_incr_reg[11]_0\(3 downto 0),
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_incr_reg[3]_0\(3 downto 0) => \axaddr_incr_reg[3]_0\(3 downto 0),
\axaddr_incr_reg[7]\(3 downto 0) => \axaddr_incr_reg[7]\(3 downto 0),
\axaddr_incr_reg[7]_0\(0) => \axaddr_incr_reg[7]_0\(0),
\axaddr_offset_r_reg[0]\ => axaddr_offset_0(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset_0(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset_0(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]_0\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_3\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_4\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]_0\,
\m_axi_araddr[10]\ => \m_axi_araddr[10]\,
\m_payload_i_reg[3]_0\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
m_valid_i_reg_0 => ar_pipe_n_2,
m_valid_i_reg_1(0) => m_valid_i_reg(0),
next_pending_r_reg => next_pending_r_reg_1,
next_pending_r_reg_0 => next_pending_r_reg_2,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_ready_i_reg_0 => si_rs_arvalid,
sel_first_2 => sel_first_2,
\state_reg[0]_rep\ => \state_reg[0]_rep_0\,
\state_reg[1]\(1 downto 0) => \state_reg[1]\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep_1\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_2\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]_0\(6 downto 0),
\wrap_cnt_r_reg[3]\(2 downto 0) => \wrap_cnt_r_reg[3]_0\(2 downto 0),
\wrap_cnt_r_reg[3]_0\ => \wrap_cnt_r_reg[3]_1\,
wrap_second_len_1(0) => wrap_second_len_1(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]_0\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_2\(2 downto 0)
);
aw_pipe: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice_0
port map (
CO(0) => CO(0),
D(2 downto 0) => D(2 downto 0),
E(0) => E(0),
O(3 downto 0) => O(3 downto 0),
Q(58 downto 0) => Q(58 downto 0),
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
aresetn => aresetn,
\aresetn_d_reg[1]_inv\ => aw_pipe_n_97,
\aresetn_d_reg[1]_inv_0\ => ar_pipe_n_2,
axaddr_incr_reg(3 downto 0) => axaddr_incr_reg(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => \axaddr_incr_reg[11]\(7 downto 0),
\axaddr_offset_r_reg[0]\ => axaddr_offset(0),
\axaddr_offset_r_reg[1]\ => axaddr_offset(1),
\axaddr_offset_r_reg[2]\ => axaddr_offset(2),
\axaddr_offset_r_reg[3]\ => \axaddr_offset_r_reg[3]\,
\axaddr_offset_r_reg[3]_0\(0) => \axaddr_offset_r_reg[3]_1\(0),
\axaddr_offset_r_reg[3]_1\(3 downto 0) => \axaddr_offset_r_reg[3]_2\(3 downto 0),
\axlen_cnt_reg[3]\ => \axlen_cnt_reg[3]\,
b_push => b_push,
\m_axi_awaddr[10]\ => \m_axi_awaddr[10]\,
m_valid_i_reg_0 => si_rs_awvalid,
next_pending_r_reg => next_pending_r_reg,
next_pending_r_reg_0 => next_pending_r_reg_0,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
s_ready_i_reg_0 => aw_pipe_n_1,
sel_first => sel_first,
\state_reg[0]_rep\ => \state_reg[0]_rep\,
\state_reg[1]\(1 downto 0) => \state_reg[1]_0\(1 downto 0),
\state_reg[1]_rep\ => \state_reg[1]_rep\,
\state_reg[1]_rep_0\ => \state_reg[1]_rep_0\,
\wrap_boundary_axaddr_r_reg[6]\(6 downto 0) => \wrap_boundary_axaddr_r_reg[6]\(6 downto 0),
\wrap_cnt_r_reg[3]\ => \wrap_cnt_r_reg[3]\,
wrap_second_len(0) => wrap_second_len(0),
\wrap_second_len_r_reg[3]\(2 downto 0) => \wrap_second_len_r_reg[3]\(2 downto 0),
\wrap_second_len_r_reg[3]_0\(2 downto 0) => \wrap_second_len_r_reg[3]_1\(2 downto 0)
);
b_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized1\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\out\(11 downto 0) => \out\(11 downto 0),
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => \s_bresp_acc_reg[1]\(1 downto 0),
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[0]_0\ => si_rs_bready
);
r_pipe: entity work.\decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axic_register_slice__parameterized2\
port map (
aclk => aclk,
\aresetn_d_reg[0]\ => aw_pipe_n_1,
\aresetn_d_reg[1]_inv\ => ar_pipe_n_2,
\cnt_read_reg[3]_rep__0\ => \cnt_read_reg[3]_rep__0\,
\cnt_read_reg[4]\(33 downto 0) => \cnt_read_reg[4]\(33 downto 0),
\cnt_read_reg[4]_rep__0\ => \cnt_read_reg[4]_rep__0\,
r_push_r_reg(12 downto 0) => r_push_r_reg(12 downto 0),
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\skid_buffer_reg[0]_0\ => si_rs_rready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
wrap_second_len : out STD_LOGIC_VECTOR ( 0 to 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
\m_payload_i_reg[0]\ : out STD_LOGIC;
\m_payload_i_reg[0]_0\ : out STD_LOGIC;
r_push_r_reg : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
r_rlast : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\r_arid_r_reg[11]\ : out STD_LOGIC_VECTOR ( 11 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_arvalid : in STD_LOGIC;
\m_payload_i_reg[44]\ : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
m_axi_arready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\cnt_read_reg[2]_rep__0\ : in STD_LOGIC;
axaddr_offset : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[51]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel is
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal ar_cmd_fsm_0_n_0 : STD_LOGIC;
signal ar_cmd_fsm_0_n_12 : STD_LOGIC;
signal ar_cmd_fsm_0_n_15 : STD_LOGIC;
signal ar_cmd_fsm_0_n_16 : STD_LOGIC;
signal ar_cmd_fsm_0_n_17 : STD_LOGIC;
signal ar_cmd_fsm_0_n_20 : STD_LOGIC;
signal ar_cmd_fsm_0_n_21 : STD_LOGIC;
signal ar_cmd_fsm_0_n_3 : STD_LOGIC;
signal ar_cmd_fsm_0_n_8 : STD_LOGIC;
signal ar_cmd_fsm_0_n_9 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_8 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \^m_payload_i_reg[0]\ : STD_LOGIC;
signal \^m_payload_i_reg[0]_0\ : STD_LOGIC;
signal \^r_push_r_reg\ : STD_LOGIC;
signal \^sel_first\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
signal \^wrap_second_len\ : STD_LOGIC_VECTOR ( 0 to 0 );
begin
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
\m_payload_i_reg[0]\ <= \^m_payload_i_reg[0]\;
\m_payload_i_reg[0]_0\ <= \^m_payload_i_reg[0]_0\;
r_push_r_reg <= \^r_push_r_reg\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
wrap_second_len(0) <= \^wrap_second_len\(0);
ar_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_rd_cmd_fsm
port map (
D(0) => ar_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => ar_cmd_fsm_0_n_17,
axaddr_offset(2 downto 0) => axaddr_offset(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[11]\(0) => ar_cmd_fsm_0_n_16,
\axlen_cnt_reg[1]\ => ar_cmd_fsm_0_n_0,
\axlen_cnt_reg[1]_0\(1) => ar_cmd_fsm_0_n_8,
\axlen_cnt_reg[1]_0\(0) => ar_cmd_fsm_0_n_9,
\axlen_cnt_reg[1]_1\(1) => cmd_translator_0_n_9,
\axlen_cnt_reg[1]_1\(0) => cmd_translator_0_n_10,
\axlen_cnt_reg[4]\ => cmd_translator_0_n_11,
\cnt_read_reg[2]_rep__0\ => \cnt_read_reg[2]_rep__0\,
incr_next_pending => incr_next_pending,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \^m_payload_i_reg[0]_0\,
\m_payload_i_reg[0]_0\ => \^m_payload_i_reg[0]\,
\m_payload_i_reg[0]_1\(0) => E(0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[47]\(3) => \m_payload_i_reg[64]\(19),
\m_payload_i_reg[47]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[51]\ => \m_payload_i_reg[51]\,
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
next_pending_r_reg => cmd_translator_0_n_0,
r_push_r_reg => \^r_push_r_reg\,
s_axburst_eq0_reg => ar_cmd_fsm_0_n_12,
s_axburst_eq1_reg => ar_cmd_fsm_0_n_15,
s_axburst_eq1_reg_0 => cmd_translator_0_n_13,
sel_first_i => sel_first_i,
sel_first_reg => ar_cmd_fsm_0_n_20,
sel_first_reg_0 => ar_cmd_fsm_0_n_21,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
sel_first_reg_3 => cmd_translator_0_n_8,
si_rs_arvalid => si_rs_arvalid,
wrap_next_pending => wrap_next_pending,
wrap_second_len(0) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[1]\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator_1
port map (
CO(0) => CO(0),
D(1) => ar_cmd_fsm_0_n_8,
D(0) => ar_cmd_fsm_0_n_9,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(1) => cmd_translator_0_n_9,
Q(0) => cmd_translator_0_n_10,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => axaddr_offset(2 downto 0),
incr_next_pending => incr_next_pending,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
\m_payload_i_reg[11]\(3 downto 0) => \m_payload_i_reg[11]\(3 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => ar_cmd_fsm_0_n_12,
\m_payload_i_reg[39]_0\ => ar_cmd_fsm_0_n_15,
\m_payload_i_reg[3]\(3 downto 0) => \m_payload_i_reg[3]\(3 downto 0),
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(23 downto 0) => \m_payload_i_reg[64]\(23 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => ar_cmd_fsm_0_n_16,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_11,
r_rlast => r_rlast,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => cmd_translator_0_n_8,
sel_first_reg_2 => ar_cmd_fsm_0_n_17,
sel_first_reg_3 => ar_cmd_fsm_0_n_20,
sel_first_reg_4 => ar_cmd_fsm_0_n_21,
si_rs_arvalid => si_rs_arvalid,
\state_reg[0]\ => ar_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => cmd_translator_0_n_13,
\state_reg[0]_rep_0\ => \^m_payload_i_reg[0]\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => \^m_payload_i_reg[0]_0\,
\state_reg[1]_rep_0\ => \^r_push_r_reg\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => D(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^wrap_second_len\(0),
\wrap_second_len_r_reg[3]_0\(0) => D(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => ar_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_0\(0)
);
\s_arid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \r_arid_r_reg[11]\(0),
R => '0'
);
\s_arid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \r_arid_r_reg[11]\(10),
R => '0'
);
\s_arid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \r_arid_r_reg[11]\(11),
R => '0'
);
\s_arid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \r_arid_r_reg[11]\(1),
R => '0'
);
\s_arid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \r_arid_r_reg[11]\(2),
R => '0'
);
\s_arid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \r_arid_r_reg[11]\(3),
R => '0'
);
\s_arid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \r_arid_r_reg[11]\(4),
R => '0'
);
\s_arid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \r_arid_r_reg[11]\(5),
R => '0'
);
\s_arid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \r_arid_r_reg[11]\(6),
R => '0'
);
\s_arid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \r_arid_r_reg[11]\(7),
R => '0'
);
\s_arid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \r_arid_r_reg[11]\(8),
R => '0'
);
\s_arid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \r_arid_r_reg[11]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
port (
\axaddr_incr_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
sel_first : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 1 downto 0 );
\wrap_boundary_axaddr_r_reg[11]\ : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\state_reg[1]_rep\ : out STD_LOGIC;
\state_reg[1]_rep_0\ : out STD_LOGIC;
\wrap_second_len_r_reg[3]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\axaddr_offset_r_reg[3]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
b_push : out STD_LOGIC;
\axaddr_offset_r_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
\in\ : out STD_LOGIC_VECTOR ( 19 downto 0 );
S : out STD_LOGIC_VECTOR ( 3 downto 0 );
aclk : in STD_LOGIC;
O : in STD_LOGIC_VECTOR ( 3 downto 0 );
\m_payload_i_reg[47]\ : in STD_LOGIC;
si_rs_awvalid : in STD_LOGIC;
\m_payload_i_reg[64]\ : in STD_LOGIC_VECTOR ( 35 downto 0 );
\m_payload_i_reg[44]\ : in STD_LOGIC;
\cnt_read_reg[1]_rep__1\ : in STD_LOGIC;
\cnt_read_reg[0]_rep__0\ : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
CO : in STD_LOGIC_VECTOR ( 0 to 0 );
\m_payload_i_reg[35]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[48]\ : in STD_LOGIC;
areset_d1 : in STD_LOGIC;
\m_payload_i_reg[46]\ : in STD_LOGIC;
\m_payload_i_reg[6]\ : in STD_LOGIC;
\m_payload_i_reg[11]\ : in STD_LOGIC_VECTOR ( 7 downto 0 );
\m_payload_i_reg[38]\ : in STD_LOGIC;
\wrap_second_len_r_reg[3]_0\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\wrap_second_len_r_reg[3]_1\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\m_payload_i_reg[6]_0\ : in STD_LOGIC_VECTOR ( 6 downto 0 )
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel is
signal \^d\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^q\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal aw_cmd_fsm_0_n_0 : STD_LOGIC;
signal aw_cmd_fsm_0_n_13 : STD_LOGIC;
signal aw_cmd_fsm_0_n_17 : STD_LOGIC;
signal aw_cmd_fsm_0_n_20 : STD_LOGIC;
signal aw_cmd_fsm_0_n_21 : STD_LOGIC;
signal aw_cmd_fsm_0_n_24 : STD_LOGIC;
signal aw_cmd_fsm_0_n_25 : STD_LOGIC;
signal aw_cmd_fsm_0_n_3 : STD_LOGIC;
signal \^axaddr_offset_r_reg[3]\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \^axaddr_offset_r_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^b_push\ : STD_LOGIC;
signal cmd_translator_0_n_0 : STD_LOGIC;
signal cmd_translator_0_n_1 : STD_LOGIC;
signal cmd_translator_0_n_10 : STD_LOGIC;
signal cmd_translator_0_n_11 : STD_LOGIC;
signal cmd_translator_0_n_12 : STD_LOGIC;
signal cmd_translator_0_n_13 : STD_LOGIC;
signal cmd_translator_0_n_14 : STD_LOGIC;
signal cmd_translator_0_n_15 : STD_LOGIC;
signal cmd_translator_0_n_16 : STD_LOGIC;
signal cmd_translator_0_n_17 : STD_LOGIC;
signal cmd_translator_0_n_2 : STD_LOGIC;
signal cmd_translator_0_n_9 : STD_LOGIC;
signal incr_next_pending : STD_LOGIC;
signal \next\ : STD_LOGIC;
signal p_1_in : STD_LOGIC_VECTOR ( 5 downto 0 );
signal \^sel_first\ : STD_LOGIC;
signal \sel_first__0\ : STD_LOGIC;
signal sel_first_i : STD_LOGIC;
signal \^wrap_boundary_axaddr_r_reg[11]\ : STD_LOGIC;
signal \wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 1 to 1 );
signal wrap_next_pending : STD_LOGIC;
begin
D(0) <= \^d\(0);
Q(1 downto 0) <= \^q\(1 downto 0);
\axaddr_offset_r_reg[3]\(0) <= \^axaddr_offset_r_reg[3]\(0);
\axaddr_offset_r_reg[3]_0\(3 downto 0) <= \^axaddr_offset_r_reg[3]_0\(3 downto 0);
b_push <= \^b_push\;
sel_first <= \^sel_first\;
\wrap_boundary_axaddr_r_reg[11]\ <= \^wrap_boundary_axaddr_r_reg[11]\;
aw_cmd_fsm_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_wr_cmd_fsm
port map (
D(0) => aw_cmd_fsm_0_n_3,
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
Q(1 downto 0) => \^q\(1 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[11]\ => aw_cmd_fsm_0_n_21,
\axaddr_offset_r_reg[3]\(0) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(0) => \^axaddr_offset_r_reg[3]_0\(3),
\axaddr_wrap_reg[0]\(0) => aw_cmd_fsm_0_n_20,
\axlen_cnt_reg[2]\ => cmd_translator_0_n_16,
\axlen_cnt_reg[3]\ => cmd_translator_0_n_15,
\axlen_cnt_reg[3]_0\ => cmd_translator_0_n_17,
\axlen_cnt_reg[4]\ => aw_cmd_fsm_0_n_0,
\axlen_cnt_reg[4]_0\ => cmd_translator_0_n_13,
\axlen_cnt_reg[5]\(3 downto 2) => p_1_in(5 downto 4),
\axlen_cnt_reg[5]\(1 downto 0) => p_1_in(1 downto 0),
\axlen_cnt_reg[5]_0\(3) => cmd_translator_0_n_9,
\axlen_cnt_reg[5]_0\(2) => cmd_translator_0_n_10,
\axlen_cnt_reg[5]_0\(1) => cmd_translator_0_n_11,
\axlen_cnt_reg[5]_0\(0) => cmd_translator_0_n_12,
\cnt_read_reg[0]_rep__0\ => \cnt_read_reg[0]_rep__0\,
\cnt_read_reg[1]_rep__1\ => \cnt_read_reg[1]_rep__1\,
incr_next_pending => incr_next_pending,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[0]\ => \^b_push\,
\m_payload_i_reg[0]_0\(0) => E(0),
\m_payload_i_reg[35]\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\m_payload_i_reg[44]\ => \m_payload_i_reg[44]\,
\m_payload_i_reg[46]\ => \m_payload_i_reg[46]\,
\m_payload_i_reg[48]\ => \m_payload_i_reg[48]\,
\m_payload_i_reg[49]\(5 downto 3) => \m_payload_i_reg[64]\(21 downto 19),
\m_payload_i_reg[49]\(2 downto 0) => \m_payload_i_reg[64]\(17 downto 15),
\m_payload_i_reg[6]\ => \m_payload_i_reg[6]\,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
s_axburst_eq0_reg => aw_cmd_fsm_0_n_13,
s_axburst_eq1_reg => aw_cmd_fsm_0_n_17,
s_axburst_eq1_reg_0 => cmd_translator_0_n_14,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg => aw_cmd_fsm_0_n_24,
sel_first_reg_0 => aw_cmd_fsm_0_n_25,
sel_first_reg_1 => cmd_translator_0_n_2,
sel_first_reg_2 => \^sel_first\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep_0\ => \state_reg[1]_rep\,
\state_reg[1]_rep_1\ => \state_reg[1]_rep_0\,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[1]\(0) => \^d\(0),
\wrap_second_len_r_reg[1]_0\(0) => \wrap_cmd_0/wrap_second_len_r\(1)
);
cmd_translator_0: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_cmd_translator
port map (
CO(0) => CO(0),
D(3 downto 2) => p_1_in(5 downto 4),
D(1 downto 0) => p_1_in(1 downto 0),
E(0) => \^wrap_boundary_axaddr_r_reg[11]\,
O(3 downto 0) => O(3 downto 0),
Q(3) => cmd_translator_0_n_9,
Q(2) => cmd_translator_0_n_10,
Q(1) => cmd_translator_0_n_11,
Q(0) => cmd_translator_0_n_12,
S(3 downto 0) => S(3 downto 0),
aclk => aclk,
\axaddr_incr_reg[11]\ => \^sel_first\,
\axaddr_incr_reg[3]\(3 downto 0) => \axaddr_incr_reg[3]\(3 downto 0),
\axaddr_offset_r_reg[3]\(3 downto 0) => \^axaddr_offset_r_reg[3]_0\(3 downto 0),
\axaddr_offset_r_reg[3]_0\(3) => \^axaddr_offset_r_reg[3]\(0),
\axaddr_offset_r_reg[3]_0\(2 downto 0) => \m_payload_i_reg[35]\(2 downto 0),
\axlen_cnt_reg[4]\ => cmd_translator_0_n_17,
\axlen_cnt_reg[7]\ => cmd_translator_0_n_13,
incr_next_pending => incr_next_pending,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
\m_payload_i_reg[11]\(7 downto 0) => \m_payload_i_reg[11]\(7 downto 0),
\m_payload_i_reg[38]\ => \m_payload_i_reg[38]\,
\m_payload_i_reg[39]\ => aw_cmd_fsm_0_n_13,
\m_payload_i_reg[39]_0\ => aw_cmd_fsm_0_n_17,
\m_payload_i_reg[47]\ => \m_payload_i_reg[47]\,
\m_payload_i_reg[51]\(21 downto 20) => \m_payload_i_reg[64]\(23 downto 22),
\m_payload_i_reg[51]\(19 downto 0) => \m_payload_i_reg[64]\(19 downto 0),
\m_payload_i_reg[6]\(6 downto 0) => \m_payload_i_reg[6]_0\(6 downto 0),
m_valid_i_reg(0) => aw_cmd_fsm_0_n_20,
\next\ => \next\,
next_pending_r_reg => cmd_translator_0_n_0,
next_pending_r_reg_0 => cmd_translator_0_n_1,
next_pending_r_reg_1 => cmd_translator_0_n_15,
next_pending_r_reg_2 => cmd_translator_0_n_16,
\sel_first__0\ => \sel_first__0\,
sel_first_i => sel_first_i,
sel_first_reg_0 => cmd_translator_0_n_2,
sel_first_reg_1 => aw_cmd_fsm_0_n_21,
sel_first_reg_2 => aw_cmd_fsm_0_n_24,
sel_first_reg_3 => aw_cmd_fsm_0_n_25,
\state_reg[0]\ => aw_cmd_fsm_0_n_0,
\state_reg[0]_rep\ => \^b_push\,
\state_reg[1]\(1 downto 0) => \^q\(1 downto 0),
\state_reg[1]_rep\ => cmd_translator_0_n_14,
wrap_next_pending => wrap_next_pending,
\wrap_second_len_r_reg[3]\(3 downto 2) => \wrap_second_len_r_reg[3]\(2 downto 1),
\wrap_second_len_r_reg[3]\(1) => \wrap_cmd_0/wrap_second_len_r\(1),
\wrap_second_len_r_reg[3]\(0) => \wrap_second_len_r_reg[3]\(0),
\wrap_second_len_r_reg[3]_0\(3 downto 2) => \wrap_second_len_r_reg[3]_0\(2 downto 1),
\wrap_second_len_r_reg[3]_0\(1) => \^d\(0),
\wrap_second_len_r_reg[3]_0\(0) => \wrap_second_len_r_reg[3]_0\(0),
\wrap_second_len_r_reg[3]_1\(3 downto 2) => \wrap_second_len_r_reg[3]_1\(2 downto 1),
\wrap_second_len_r_reg[3]_1\(1) => aw_cmd_fsm_0_n_3,
\wrap_second_len_r_reg[3]_1\(0) => \wrap_second_len_r_reg[3]_1\(0)
);
\s_awid_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(24),
Q => \in\(8),
R => '0'
);
\s_awid_r_reg[10]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(34),
Q => \in\(18),
R => '0'
);
\s_awid_r_reg[11]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(35),
Q => \in\(19),
R => '0'
);
\s_awid_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(25),
Q => \in\(9),
R => '0'
);
\s_awid_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(26),
Q => \in\(10),
R => '0'
);
\s_awid_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(27),
Q => \in\(11),
R => '0'
);
\s_awid_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(28),
Q => \in\(12),
R => '0'
);
\s_awid_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(29),
Q => \in\(13),
R => '0'
);
\s_awid_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(30),
Q => \in\(14),
R => '0'
);
\s_awid_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(31),
Q => \in\(15),
R => '0'
);
\s_awid_r_reg[8]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(32),
Q => \in\(16),
R => '0'
);
\s_awid_r_reg[9]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(33),
Q => \in\(17),
R => '0'
);
\s_awlen_r_reg[0]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(16),
Q => \in\(0),
R => '0'
);
\s_awlen_r_reg[1]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(17),
Q => \in\(1),
R => '0'
);
\s_awlen_r_reg[2]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(18),
Q => \in\(2),
R => '0'
);
\s_awlen_r_reg[3]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(19),
Q => \in\(3),
R => '0'
);
\s_awlen_r_reg[4]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(20),
Q => \in\(4),
R => '0'
);
\s_awlen_r_reg[5]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(21),
Q => \in\(5),
R => '0'
);
\s_awlen_r_reg[6]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(22),
Q => \in\(6),
R => '0'
);
\s_awlen_r_reg[7]\: unisim.vcomponents.FDRE
port map (
C => aclk,
CE => '1',
D => \m_payload_i_reg[64]\(23),
Q => \in\(7),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
port (
s_axi_rvalid : out STD_LOGIC;
s_axi_awready : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_arready : out STD_LOGIC;
\m_axi_arprot[2]\ : out STD_LOGIC_VECTOR ( 22 downto 0 );
s_axi_bvalid : out STD_LOGIC;
\s_axi_bid[11]\ : out STD_LOGIC_VECTOR ( 13 downto 0 );
\s_axi_rid[11]\ : out STD_LOGIC_VECTOR ( 46 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
aclk : in STD_LOGIC;
\in\ : in STD_LOGIC_VECTOR ( 33 downto 0 );
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
aresetn : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s is
signal C : STD_LOGIC_VECTOR ( 11 downto 4 );
signal \RD.ar_channel_0_n_10\ : STD_LOGIC;
signal \RD.ar_channel_0_n_11\ : STD_LOGIC;
signal \RD.ar_channel_0_n_47\ : STD_LOGIC;
signal \RD.ar_channel_0_n_48\ : STD_LOGIC;
signal \RD.ar_channel_0_n_49\ : STD_LOGIC;
signal \RD.ar_channel_0_n_50\ : STD_LOGIC;
signal \RD.ar_channel_0_n_8\ : STD_LOGIC;
signal \RD.ar_channel_0_n_9\ : STD_LOGIC;
signal \RD.r_channel_0_n_0\ : STD_LOGIC;
signal \RD.r_channel_0_n_2\ : STD_LOGIC;
signal SI_REG_n_134 : STD_LOGIC;
signal SI_REG_n_135 : STD_LOGIC;
signal SI_REG_n_136 : STD_LOGIC;
signal SI_REG_n_137 : STD_LOGIC;
signal SI_REG_n_138 : STD_LOGIC;
signal SI_REG_n_139 : STD_LOGIC;
signal SI_REG_n_140 : STD_LOGIC;
signal SI_REG_n_141 : STD_LOGIC;
signal SI_REG_n_142 : STD_LOGIC;
signal SI_REG_n_143 : STD_LOGIC;
signal SI_REG_n_144 : STD_LOGIC;
signal SI_REG_n_145 : STD_LOGIC;
signal SI_REG_n_146 : STD_LOGIC;
signal SI_REG_n_147 : STD_LOGIC;
signal SI_REG_n_148 : STD_LOGIC;
signal SI_REG_n_149 : STD_LOGIC;
signal SI_REG_n_150 : STD_LOGIC;
signal SI_REG_n_151 : STD_LOGIC;
signal SI_REG_n_158 : STD_LOGIC;
signal SI_REG_n_162 : STD_LOGIC;
signal SI_REG_n_163 : STD_LOGIC;
signal SI_REG_n_164 : STD_LOGIC;
signal SI_REG_n_165 : STD_LOGIC;
signal SI_REG_n_166 : STD_LOGIC;
signal SI_REG_n_167 : STD_LOGIC;
signal SI_REG_n_171 : STD_LOGIC;
signal SI_REG_n_175 : STD_LOGIC;
signal SI_REG_n_176 : STD_LOGIC;
signal SI_REG_n_177 : STD_LOGIC;
signal SI_REG_n_178 : STD_LOGIC;
signal SI_REG_n_179 : STD_LOGIC;
signal SI_REG_n_180 : STD_LOGIC;
signal SI_REG_n_181 : STD_LOGIC;
signal SI_REG_n_182 : STD_LOGIC;
signal SI_REG_n_183 : STD_LOGIC;
signal SI_REG_n_184 : STD_LOGIC;
signal SI_REG_n_185 : STD_LOGIC;
signal SI_REG_n_186 : STD_LOGIC;
signal SI_REG_n_187 : STD_LOGIC;
signal SI_REG_n_188 : STD_LOGIC;
signal SI_REG_n_189 : STD_LOGIC;
signal SI_REG_n_190 : STD_LOGIC;
signal SI_REG_n_191 : STD_LOGIC;
signal SI_REG_n_192 : STD_LOGIC;
signal SI_REG_n_193 : STD_LOGIC;
signal SI_REG_n_194 : STD_LOGIC;
signal SI_REG_n_195 : STD_LOGIC;
signal SI_REG_n_196 : STD_LOGIC;
signal SI_REG_n_20 : STD_LOGIC;
signal SI_REG_n_21 : STD_LOGIC;
signal SI_REG_n_22 : STD_LOGIC;
signal SI_REG_n_23 : STD_LOGIC;
signal SI_REG_n_29 : STD_LOGIC;
signal SI_REG_n_79 : STD_LOGIC;
signal SI_REG_n_80 : STD_LOGIC;
signal SI_REG_n_81 : STD_LOGIC;
signal SI_REG_n_82 : STD_LOGIC;
signal SI_REG_n_88 : STD_LOGIC;
signal \WR.aw_channel_0_n_10\ : STD_LOGIC;
signal \WR.aw_channel_0_n_54\ : STD_LOGIC;
signal \WR.aw_channel_0_n_55\ : STD_LOGIC;
signal \WR.aw_channel_0_n_56\ : STD_LOGIC;
signal \WR.aw_channel_0_n_57\ : STD_LOGIC;
signal \WR.aw_channel_0_n_7\ : STD_LOGIC;
signal \WR.aw_channel_0_n_9\ : STD_LOGIC;
signal \WR.b_channel_0_n_1\ : STD_LOGIC;
signal \WR.b_channel_0_n_2\ : STD_LOGIC;
signal \ar_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \ar_pipe/p_1_in\ : STD_LOGIC;
signal areset_d1 : STD_LOGIC;
signal areset_d1_i_1_n_0 : STD_LOGIC;
signal \aw_cmd_fsm_0/state\ : STD_LOGIC_VECTOR ( 1 downto 0 );
signal \aw_pipe/p_1_in\ : STD_LOGIC;
signal b_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal b_awlen : STD_LOGIC_VECTOR ( 7 downto 0 );
signal b_push : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/incr_cmd_0/sel_first\ : STD_LOGIC;
signal \cmd_translator_0/incr_cmd_0/sel_first_4\ : STD_LOGIC;
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal r_rlast : STD_LOGIC;
signal s_arid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_arid_r : STD_LOGIC_VECTOR ( 11 downto 0 );
signal s_awid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_araddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_arburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_arlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_arsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_arvalid : STD_LOGIC;
signal si_rs_awaddr : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_awburst : STD_LOGIC_VECTOR ( 1 to 1 );
signal si_rs_awlen : STD_LOGIC_VECTOR ( 3 downto 0 );
signal si_rs_awsize : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_awvalid : STD_LOGIC;
signal si_rs_bid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_bready : STD_LOGIC;
signal si_rs_bresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal si_rs_bvalid : STD_LOGIC;
signal si_rs_rdata : STD_LOGIC_VECTOR ( 31 downto 0 );
signal si_rs_rid : STD_LOGIC_VECTOR ( 11 downto 0 );
signal si_rs_rlast : STD_LOGIC;
signal si_rs_rready : STD_LOGIC;
signal si_rs_rresp : STD_LOGIC_VECTOR ( 1 downto 0 );
signal wrap_cnt : STD_LOGIC_VECTOR ( 3 downto 0 );
begin
\RD.ar_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_ar_channel
port map (
CO(0) => SI_REG_n_147,
D(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
E(0) => \ar_pipe/p_1_in\,
O(3) => SI_REG_n_148,
O(2) => SI_REG_n_149,
O(1) => SI_REG_n_150,
O(0) => SI_REG_n_151,
Q(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
S(3) => \RD.ar_channel_0_n_47\,
S(2) => \RD.ar_channel_0_n_48\,
S(1) => \RD.ar_channel_0_n_49\,
S(0) => \RD.ar_channel_0_n_50\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\cnt_read_reg[2]_rep__0\ => \RD.r_channel_0_n_0\,
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\m_payload_i_reg[0]\ => \RD.ar_channel_0_n_9\,
\m_payload_i_reg[0]_0\ => \RD.ar_channel_0_n_10\,
\m_payload_i_reg[11]\(3) => SI_REG_n_143,
\m_payload_i_reg[11]\(2) => SI_REG_n_144,
\m_payload_i_reg[11]\(1) => SI_REG_n_145,
\m_payload_i_reg[11]\(0) => SI_REG_n_146,
\m_payload_i_reg[38]\ => SI_REG_n_196,
\m_payload_i_reg[3]\(3) => SI_REG_n_139,
\m_payload_i_reg[3]\(2) => SI_REG_n_140,
\m_payload_i_reg[3]\(1) => SI_REG_n_141,
\m_payload_i_reg[3]\(0) => SI_REG_n_142,
\m_payload_i_reg[44]\ => SI_REG_n_171,
\m_payload_i_reg[46]\ => SI_REG_n_177,
\m_payload_i_reg[47]\ => SI_REG_n_175,
\m_payload_i_reg[51]\ => SI_REG_n_176,
\m_payload_i_reg[64]\(35 downto 24) => s_arid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_79,
\m_payload_i_reg[64]\(22) => SI_REG_n_80,
\m_payload_i_reg[64]\(21) => SI_REG_n_81,
\m_payload_i_reg[64]\(20) => SI_REG_n_82,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_arlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_arburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_88,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_arsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_araddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_187,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_188,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_189,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_190,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_191,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_192,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_193,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_194,
\r_arid_r_reg[11]\(11 downto 0) => s_arid_r(11 downto 0),
r_push_r_reg => \RD.ar_channel_0_n_11\,
r_rlast => r_rlast,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
\wrap_boundary_axaddr_r_reg[11]\ => \RD.ar_channel_0_n_8\,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0),
\wrap_second_len_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_second_len_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_second_len_r_reg[3]_0\(0) => SI_REG_n_167
);
\RD.r_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_r_channel
port map (
D(11 downto 0) => s_arid_r(11 downto 0),
aclk => aclk,
areset_d1 => areset_d1,
\in\(33 downto 0) => \in\(33 downto 0),
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
m_valid_i_reg => \RD.r_channel_0_n_2\,
\out\(33 downto 32) => si_rs_rresp(1 downto 0),
\out\(31 downto 0) => si_rs_rdata(31 downto 0),
r_rlast => r_rlast,
s_ready_i_reg => SI_REG_n_178,
si_rs_rready => si_rs_rready,
\skid_buffer_reg[46]\(12 downto 1) => si_rs_rid(11 downto 0),
\skid_buffer_reg[46]\(0) => si_rs_rlast,
\state_reg[1]_rep\ => \RD.r_channel_0_n_0\,
\state_reg[1]_rep_0\ => \RD.ar_channel_0_n_11\
);
SI_REG: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_register_slice_v2_1_13_axi_register_slice
port map (
CO(0) => SI_REG_n_134,
D(2 downto 1) => wrap_cnt(3 downto 2),
D(0) => wrap_cnt(0),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(58 downto 47) => s_awid(11 downto 0),
Q(46) => SI_REG_n_20,
Q(45) => SI_REG_n_21,
Q(44) => SI_REG_n_22,
Q(43) => SI_REG_n_23,
Q(42 downto 39) => si_rs_awlen(3 downto 0),
Q(38) => si_rs_awburst(1),
Q(37) => SI_REG_n_29,
Q(36 downto 35) => si_rs_awsize(1 downto 0),
Q(34 downto 12) => Q(22 downto 0),
Q(11 downto 0) => si_rs_awaddr(11 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
aresetn => aresetn,
axaddr_incr_reg(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_incr_reg[11]\(7 downto 0) => C(11 downto 4),
\axaddr_incr_reg[11]_0\(3) => SI_REG_n_143,
\axaddr_incr_reg[11]_0\(2) => SI_REG_n_144,
\axaddr_incr_reg[11]_0\(1) => SI_REG_n_145,
\axaddr_incr_reg[11]_0\(0) => SI_REG_n_146,
\axaddr_incr_reg[3]\(3) => SI_REG_n_148,
\axaddr_incr_reg[3]\(2) => SI_REG_n_149,
\axaddr_incr_reg[3]\(1) => SI_REG_n_150,
\axaddr_incr_reg[3]\(0) => SI_REG_n_151,
\axaddr_incr_reg[3]_0\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg\(3 downto 0),
\axaddr_incr_reg[7]\(3) => SI_REG_n_139,
\axaddr_incr_reg[7]\(2) => SI_REG_n_140,
\axaddr_incr_reg[7]\(1) => SI_REG_n_141,
\axaddr_incr_reg[7]\(0) => SI_REG_n_142,
\axaddr_incr_reg[7]_0\(0) => SI_REG_n_147,
axaddr_offset(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
axaddr_offset_0(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(2 downto 0),
\axaddr_offset_r_reg[3]\ => SI_REG_n_179,
\axaddr_offset_r_reg[3]_0\ => SI_REG_n_187,
\axaddr_offset_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_2\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
\axaddr_offset_r_reg[3]_3\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset\(3),
\axaddr_offset_r_reg[3]_4\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r\(3 downto 0),
\axlen_cnt_reg[3]\ => SI_REG_n_162,
\axlen_cnt_reg[3]_0\ => SI_REG_n_175,
b_push => b_push,
\cnt_read_reg[3]_rep__0\ => SI_REG_n_178,
\cnt_read_reg[4]\(33 downto 32) => si_rs_rresp(1 downto 0),
\cnt_read_reg[4]\(31 downto 0) => si_rs_rdata(31 downto 0),
\cnt_read_reg[4]_rep__0\ => \RD.r_channel_0_n_2\,
\m_axi_araddr[10]\ => SI_REG_n_196,
\m_axi_awaddr[10]\ => SI_REG_n_195,
\m_payload_i_reg[3]\(3) => \RD.ar_channel_0_n_47\,
\m_payload_i_reg[3]\(2) => \RD.ar_channel_0_n_48\,
\m_payload_i_reg[3]\(1) => \RD.ar_channel_0_n_49\,
\m_payload_i_reg[3]\(0) => \RD.ar_channel_0_n_50\,
m_valid_i_reg(0) => \ar_pipe/p_1_in\,
next_pending_r_reg => SI_REG_n_163,
next_pending_r_reg_0 => SI_REG_n_164,
next_pending_r_reg_1 => SI_REG_n_176,
next_pending_r_reg_2 => SI_REG_n_177,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
r_push_r_reg(12 downto 1) => si_rs_rid(11 downto 0),
r_push_r_reg(0) => si_rs_rlast,
\s_arid_r_reg[11]\(58 downto 47) => s_arid(11 downto 0),
\s_arid_r_reg[11]\(46) => SI_REG_n_79,
\s_arid_r_reg[11]\(45) => SI_REG_n_80,
\s_arid_r_reg[11]\(44) => SI_REG_n_81,
\s_arid_r_reg[11]\(43) => SI_REG_n_82,
\s_arid_r_reg[11]\(42 downto 39) => si_rs_arlen(3 downto 0),
\s_arid_r_reg[11]\(38) => si_rs_arburst(1),
\s_arid_r_reg[11]\(37) => SI_REG_n_88,
\s_arid_r_reg[11]\(36 downto 35) => si_rs_arsize(1 downto 0),
\s_arid_r_reg[11]\(34 downto 12) => \m_axi_arprot[2]\(22 downto 0),
\s_arid_r_reg[11]\(11 downto 0) => si_rs_araddr(11 downto 0),
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 0) => \s_axi_bid[11]\(13 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 0) => \s_axi_rid[11]\(46 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
\s_bresp_acc_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0),
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
sel_first_2 => \cmd_translator_0/incr_cmd_0/sel_first\,
si_rs_arvalid => si_rs_arvalid,
si_rs_awvalid => si_rs_awvalid,
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
si_rs_rready => si_rs_rready,
\state_reg[0]_rep\ => \WR.aw_channel_0_n_10\,
\state_reg[0]_rep_0\ => \RD.ar_channel_0_n_9\,
\state_reg[1]\(1 downto 0) => \ar_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_0\(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_7\,
\state_reg[1]_rep_1\ => \RD.ar_channel_0_n_8\,
\state_reg[1]_rep_2\ => \RD.ar_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[6]\(6) => SI_REG_n_180,
\wrap_boundary_axaddr_r_reg[6]\(5) => SI_REG_n_181,
\wrap_boundary_axaddr_r_reg[6]\(4) => SI_REG_n_182,
\wrap_boundary_axaddr_r_reg[6]\(3) => SI_REG_n_183,
\wrap_boundary_axaddr_r_reg[6]\(2) => SI_REG_n_184,
\wrap_boundary_axaddr_r_reg[6]\(1) => SI_REG_n_185,
\wrap_boundary_axaddr_r_reg[6]\(0) => SI_REG_n_186,
\wrap_boundary_axaddr_r_reg[6]_0\(6) => SI_REG_n_188,
\wrap_boundary_axaddr_r_reg[6]_0\(5) => SI_REG_n_189,
\wrap_boundary_axaddr_r_reg[6]_0\(4) => SI_REG_n_190,
\wrap_boundary_axaddr_r_reg[6]_0\(3) => SI_REG_n_191,
\wrap_boundary_axaddr_r_reg[6]_0\(2) => SI_REG_n_192,
\wrap_boundary_axaddr_r_reg[6]_0\(1) => SI_REG_n_193,
\wrap_boundary_axaddr_r_reg[6]_0\(0) => SI_REG_n_194,
\wrap_cnt_r_reg[3]\ => SI_REG_n_158,
\wrap_cnt_r_reg[3]_0\(2) => SI_REG_n_165,
\wrap_cnt_r_reg[3]_0\(1) => SI_REG_n_166,
\wrap_cnt_r_reg[3]_0\(0) => SI_REG_n_167,
\wrap_cnt_r_reg[3]_1\ => SI_REG_n_171,
wrap_second_len(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
wrap_second_len_1(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(1),
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_2\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(3 downto 2),
\wrap_second_len_r_reg[3]_2\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r\(0)
);
\WR.aw_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_aw_channel
port map (
CO(0) => SI_REG_n_134,
D(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(1),
E(0) => \aw_pipe/p_1_in\,
O(3) => SI_REG_n_135,
O(2) => SI_REG_n_136,
O(1) => SI_REG_n_137,
O(0) => SI_REG_n_138,
Q(1 downto 0) => \aw_cmd_fsm_0/state\(1 downto 0),
S(3) => \WR.aw_channel_0_n_54\,
S(2) => \WR.aw_channel_0_n_55\,
S(1) => \WR.aw_channel_0_n_56\,
S(0) => \WR.aw_channel_0_n_57\,
aclk => aclk,
areset_d1 => areset_d1,
\axaddr_incr_reg[3]\(3 downto 0) => \cmd_translator_0/incr_cmd_0/axaddr_incr_reg_5\(3 downto 0),
\axaddr_offset_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(3),
\axaddr_offset_r_reg[3]_0\(3 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_r_2\(3 downto 0),
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\m_payload_i_reg[11]\(7 downto 0) => C(11 downto 4),
\m_payload_i_reg[35]\(2 downto 0) => \cmd_translator_0/wrap_cmd_0/axaddr_offset_0\(2 downto 0),
\m_payload_i_reg[38]\ => SI_REG_n_195,
\m_payload_i_reg[44]\ => SI_REG_n_158,
\m_payload_i_reg[46]\ => SI_REG_n_164,
\m_payload_i_reg[47]\ => SI_REG_n_162,
\m_payload_i_reg[48]\ => SI_REG_n_163,
\m_payload_i_reg[64]\(35 downto 24) => s_awid(11 downto 0),
\m_payload_i_reg[64]\(23) => SI_REG_n_20,
\m_payload_i_reg[64]\(22) => SI_REG_n_21,
\m_payload_i_reg[64]\(21) => SI_REG_n_22,
\m_payload_i_reg[64]\(20) => SI_REG_n_23,
\m_payload_i_reg[64]\(19 downto 16) => si_rs_awlen(3 downto 0),
\m_payload_i_reg[64]\(15) => si_rs_awburst(1),
\m_payload_i_reg[64]\(14) => SI_REG_n_29,
\m_payload_i_reg[64]\(13 downto 12) => si_rs_awsize(1 downto 0),
\m_payload_i_reg[64]\(11 downto 0) => si_rs_awaddr(11 downto 0),
\m_payload_i_reg[6]\ => SI_REG_n_179,
\m_payload_i_reg[6]_0\(6) => SI_REG_n_180,
\m_payload_i_reg[6]_0\(5) => SI_REG_n_181,
\m_payload_i_reg[6]_0\(4) => SI_REG_n_182,
\m_payload_i_reg[6]_0\(3) => SI_REG_n_183,
\m_payload_i_reg[6]_0\(2) => SI_REG_n_184,
\m_payload_i_reg[6]_0\(1) => SI_REG_n_185,
\m_payload_i_reg[6]_0\(0) => SI_REG_n_186,
sel_first => \cmd_translator_0/incr_cmd_0/sel_first_4\,
si_rs_awvalid => si_rs_awvalid,
\state_reg[1]_rep\ => \WR.aw_channel_0_n_9\,
\state_reg[1]_rep_0\ => \WR.aw_channel_0_n_10\,
\wrap_boundary_axaddr_r_reg[11]\ => \WR.aw_channel_0_n_7\,
\wrap_second_len_r_reg[3]\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(3 downto 2),
\wrap_second_len_r_reg[3]\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_r_3\(0),
\wrap_second_len_r_reg[3]_0\(2 downto 1) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(3 downto 2),
\wrap_second_len_r_reg[3]_0\(0) => \cmd_translator_0/wrap_cmd_0/wrap_second_len_1\(0),
\wrap_second_len_r_reg[3]_1\(2 downto 1) => wrap_cnt(3 downto 2),
\wrap_second_len_r_reg[3]_1\(0) => wrap_cnt(0)
);
\WR.b_channel_0\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s_b_channel
port map (
aclk => aclk,
areset_d1 => areset_d1,
b_push => b_push,
\cnt_read_reg[0]_rep__0\ => \WR.b_channel_0_n_1\,
\cnt_read_reg[1]_rep__1\ => \WR.b_channel_0_n_2\,
\in\(19 downto 8) => b_awid(11 downto 0),
\in\(7 downto 0) => b_awlen(7 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
\out\(11 downto 0) => si_rs_bid(11 downto 0),
si_rs_bready => si_rs_bready,
si_rs_bvalid => si_rs_bvalid,
\skid_buffer_reg[1]\(1 downto 0) => si_rs_bresp(1 downto 0)
);
areset_d1_i_1: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => aresetn,
O => areset_d1_i_1_n_0
);
areset_d1_reg: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => aclk,
CE => '1',
D => areset_d1_i_1_n_0,
Q => areset_d1,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 2;
attribute P_DECERR : string;
attribute P_DECERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b11";
attribute P_INCR : string;
attribute P_INCR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter : entity is "2'b10";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter is
signal \<const0>\ : STD_LOGIC;
signal \<const1>\ : STD_LOGIC;
signal \^m_axi_wready\ : STD_LOGIC;
signal \^s_axi_wdata\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \^s_axi_wstrb\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^s_axi_wvalid\ : STD_LOGIC;
begin
\^m_axi_wready\ <= m_axi_wready;
\^s_axi_wdata\(31 downto 0) <= s_axi_wdata(31 downto 0);
\^s_axi_wstrb\(3 downto 0) <= s_axi_wstrb(3 downto 0);
\^s_axi_wvalid\ <= s_axi_wvalid;
m_axi_arburst(1) <= \<const0>\;
m_axi_arburst(0) <= \<const1>\;
m_axi_arcache(3) <= \<const0>\;
m_axi_arcache(2) <= \<const0>\;
m_axi_arcache(1) <= \<const0>\;
m_axi_arcache(0) <= \<const0>\;
m_axi_arid(11) <= \<const0>\;
m_axi_arid(10) <= \<const0>\;
m_axi_arid(9) <= \<const0>\;
m_axi_arid(8) <= \<const0>\;
m_axi_arid(7) <= \<const0>\;
m_axi_arid(6) <= \<const0>\;
m_axi_arid(5) <= \<const0>\;
m_axi_arid(4) <= \<const0>\;
m_axi_arid(3) <= \<const0>\;
m_axi_arid(2) <= \<const0>\;
m_axi_arid(1) <= \<const0>\;
m_axi_arid(0) <= \<const0>\;
m_axi_arlen(7) <= \<const0>\;
m_axi_arlen(6) <= \<const0>\;
m_axi_arlen(5) <= \<const0>\;
m_axi_arlen(4) <= \<const0>\;
m_axi_arlen(3) <= \<const0>\;
m_axi_arlen(2) <= \<const0>\;
m_axi_arlen(1) <= \<const0>\;
m_axi_arlen(0) <= \<const0>\;
m_axi_arlock(0) <= \<const0>\;
m_axi_arqos(3) <= \<const0>\;
m_axi_arqos(2) <= \<const0>\;
m_axi_arqos(1) <= \<const0>\;
m_axi_arqos(0) <= \<const0>\;
m_axi_arregion(3) <= \<const0>\;
m_axi_arregion(2) <= \<const0>\;
m_axi_arregion(1) <= \<const0>\;
m_axi_arregion(0) <= \<const0>\;
m_axi_arsize(2) <= \<const0>\;
m_axi_arsize(1) <= \<const1>\;
m_axi_arsize(0) <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awburst(1) <= \<const0>\;
m_axi_awburst(0) <= \<const1>\;
m_axi_awcache(3) <= \<const0>\;
m_axi_awcache(2) <= \<const0>\;
m_axi_awcache(1) <= \<const0>\;
m_axi_awcache(0) <= \<const0>\;
m_axi_awid(11) <= \<const0>\;
m_axi_awid(10) <= \<const0>\;
m_axi_awid(9) <= \<const0>\;
m_axi_awid(8) <= \<const0>\;
m_axi_awid(7) <= \<const0>\;
m_axi_awid(6) <= \<const0>\;
m_axi_awid(5) <= \<const0>\;
m_axi_awid(4) <= \<const0>\;
m_axi_awid(3) <= \<const0>\;
m_axi_awid(2) <= \<const0>\;
m_axi_awid(1) <= \<const0>\;
m_axi_awid(0) <= \<const0>\;
m_axi_awlen(7) <= \<const0>\;
m_axi_awlen(6) <= \<const0>\;
m_axi_awlen(5) <= \<const0>\;
m_axi_awlen(4) <= \<const0>\;
m_axi_awlen(3) <= \<const0>\;
m_axi_awlen(2) <= \<const0>\;
m_axi_awlen(1) <= \<const0>\;
m_axi_awlen(0) <= \<const0>\;
m_axi_awlock(0) <= \<const0>\;
m_axi_awqos(3) <= \<const0>\;
m_axi_awqos(2) <= \<const0>\;
m_axi_awqos(1) <= \<const0>\;
m_axi_awqos(0) <= \<const0>\;
m_axi_awregion(3) <= \<const0>\;
m_axi_awregion(2) <= \<const0>\;
m_axi_awregion(1) <= \<const0>\;
m_axi_awregion(0) <= \<const0>\;
m_axi_awsize(2) <= \<const0>\;
m_axi_awsize(1) <= \<const1>\;
m_axi_awsize(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wdata(31 downto 0) <= \^s_axi_wdata\(31 downto 0);
m_axi_wid(11) <= \<const0>\;
m_axi_wid(10) <= \<const0>\;
m_axi_wid(9) <= \<const0>\;
m_axi_wid(8) <= \<const0>\;
m_axi_wid(7) <= \<const0>\;
m_axi_wid(6) <= \<const0>\;
m_axi_wid(5) <= \<const0>\;
m_axi_wid(4) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wlast <= \<const1>\;
m_axi_wstrb(3 downto 0) <= \^s_axi_wstrb\(3 downto 0);
m_axi_wuser(0) <= \<const0>\;
m_axi_wvalid <= \^s_axi_wvalid\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axi_wready <= \^m_axi_wready\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
VCC: unisim.vcomponents.VCC
port map (
P => \<const1>\
);
\gen_axilite.gen_b2s_conv.axilite_b2s\: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_b2s
port map (
Q(22 downto 20) => m_axi_awprot(2 downto 0),
Q(19 downto 0) => m_axi_awaddr(31 downto 12),
aclk => aclk,
aresetn => aresetn,
\in\(33 downto 32) => m_axi_rresp(1 downto 0),
\in\(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_araddr(11 downto 0) => m_axi_araddr(11 downto 0),
\m_axi_arprot[2]\(22 downto 20) => m_axi_arprot(2 downto 0),
\m_axi_arprot[2]\(19 downto 0) => m_axi_araddr(31 downto 12),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(11 downto 0) => m_axi_awaddr(11 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arsize(1 downto 0) => s_axi_arsize(1 downto 0),
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awsize(1 downto 0) => s_axi_awsize(1 downto 0),
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[11]\(13 downto 2) => s_axi_bid(11 downto 0),
\s_axi_bid[11]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[11]\(46 downto 35) => s_axi_rid(11 downto 0),
\s_axi_rid[11]\(34) => s_axi_rlast,
\s_axi_rid[11]\(33 downto 32) => s_axi_rresp(1 downto 0),
\s_axi_rid[11]\(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "zqynq_lab_1_design_auto_pc_2,axi_protocol_converter_v2_1_13_axi_protocol_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix : entity is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2.1";
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture STRUCTURE of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
signal NLW_inst_m_axi_wlast_UNCONNECTED : STD_LOGIC;
signal NLW_inst_m_axi_arburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_arcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_arlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_arlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_arqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_arsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awburst_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_inst_m_axi_awcache_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_awlen_UNCONNECTED : STD_LOGIC_VECTOR ( 7 downto 0 );
signal NLW_inst_m_axi_awlock_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awqos_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awregion_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_awsize_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 12;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "zynq";
attribute C_IGNORE_ID : integer;
attribute C_IGNORE_ID of inst : label is 0;
attribute C_M_AXI_PROTOCOL : integer;
attribute C_M_AXI_PROTOCOL of inst : label is 2;
attribute C_S_AXI_PROTOCOL : integer;
attribute C_S_AXI_PROTOCOL of inst : label is 0;
attribute C_TRANSLATION_MODE : integer;
attribute C_TRANSLATION_MODE of inst : label is 2;
attribute DowngradeIPIdentifiedWarnings of inst : label is "yes";
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_AXILITE_SIZE : string;
attribute P_AXILITE_SIZE of inst : label is "3'b010";
attribute P_CONVERSION : integer;
attribute P_CONVERSION of inst : label is 2;
attribute P_DECERR : string;
attribute P_DECERR of inst : label is "2'b11";
attribute P_INCR : string;
attribute P_INCR of inst : label is "2'b01";
attribute P_PROTECTION : integer;
attribute P_PROTECTION of inst : label is 1;
attribute P_SLVERR : string;
attribute P_SLVERR of inst : label is "2'b10";
begin
inst: entity work.decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_axi_protocol_converter_v2_1_13_axi_protocol_converter
port map (
aclk => aclk,
aresetn => aresetn,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => NLW_inst_m_axi_arburst_UNCONNECTED(1 downto 0),
m_axi_arcache(3 downto 0) => NLW_inst_m_axi_arcache_UNCONNECTED(3 downto 0),
m_axi_arid(11 downto 0) => NLW_inst_m_axi_arid_UNCONNECTED(11 downto 0),
m_axi_arlen(7 downto 0) => NLW_inst_m_axi_arlen_UNCONNECTED(7 downto 0),
m_axi_arlock(0) => NLW_inst_m_axi_arlock_UNCONNECTED(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => NLW_inst_m_axi_arqos_UNCONNECTED(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => NLW_inst_m_axi_arregion_UNCONNECTED(3 downto 0),
m_axi_arsize(2 downto 0) => NLW_inst_m_axi_arsize_UNCONNECTED(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => NLW_inst_m_axi_awburst_UNCONNECTED(1 downto 0),
m_axi_awcache(3 downto 0) => NLW_inst_m_axi_awcache_UNCONNECTED(3 downto 0),
m_axi_awid(11 downto 0) => NLW_inst_m_axi_awid_UNCONNECTED(11 downto 0),
m_axi_awlen(7 downto 0) => NLW_inst_m_axi_awlen_UNCONNECTED(7 downto 0),
m_axi_awlock(0) => NLW_inst_m_axi_awlock_UNCONNECTED(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => NLW_inst_m_axi_awqos_UNCONNECTED(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => NLW_inst_m_axi_awregion_UNCONNECTED(3 downto 0),
m_axi_awsize(2 downto 0) => NLW_inst_m_axi_awsize_UNCONNECTED(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(11 downto 0) => B"000000000000",
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(11 downto 0) => B"000000000000",
m_axi_rlast => '1',
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(11 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(11 downto 0),
m_axi_wlast => NLW_inst_m_axi_wlast_UNCONNECTED,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(11 downto 0) => s_axi_arid(11 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(11 downto 0) => s_axi_awid(11 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(11 downto 0) => s_axi_bid(11 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(11 downto 0) => s_axi_rid(11 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(11 downto 0) => B"000000000000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity styr_hot is
port(
clock: in std_logic;
input: in std_logic_vector(8 downto 0);
output: out std_logic_vector(9 downto 0)
);
end styr_hot;
architecture behaviour of styr_hot is
constant st0: std_logic_vector(29 downto 0) := "100000000000000000000000000000";
constant st12: std_logic_vector(29 downto 0) := "010000000000000000000000000000";
constant st10: std_logic_vector(29 downto 0) := "001000000000000000000000000000";
constant st1: std_logic_vector(29 downto 0) := "000100000000000000000000000000";
constant st2: std_logic_vector(29 downto 0) := "000010000000000000000000000000";
constant st8: std_logic_vector(29 downto 0) := "000001000000000000000000000000";
constant st3: std_logic_vector(29 downto 0) := "000000100000000000000000000000";
constant st7: std_logic_vector(29 downto 0) := "000000010000000000000000000000";
constant st4: std_logic_vector(29 downto 0) := "000000001000000000000000000000";
constant st5: std_logic_vector(29 downto 0) := "000000000100000000000000000000";
constant st6: std_logic_vector(29 downto 0) := "000000000010000000000000000000";
constant st29: std_logic_vector(29 downto 0) := "000000000001000000000000000000";
constant st9: std_logic_vector(29 downto 0) := "000000000000100000000000000000";
constant st28: std_logic_vector(29 downto 0) := "000000000000010000000000000000";
constant st11: std_logic_vector(29 downto 0) := "000000000000001000000000000000";
constant st13: std_logic_vector(29 downto 0) := "000000000000000100000000000000";
constant st14: std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant st15: std_logic_vector(29 downto 0) := "000000000000000001000000000000";
constant st16: std_logic_vector(29 downto 0) := "000000000000000000100000000000";
constant st22: std_logic_vector(29 downto 0) := "000000000000000000010000000000";
constant st19: std_logic_vector(29 downto 0) := "000000000000000000001000000000";
constant st17: std_logic_vector(29 downto 0) := "000000000000000000000100000000";
constant st18: std_logic_vector(29 downto 0) := "000000000000000000000010000000";
constant st20: std_logic_vector(29 downto 0) := "000000000000000000000001000000";
constant st21: std_logic_vector(29 downto 0) := "000000000000000000000000100000";
constant st25: std_logic_vector(29 downto 0) := "000000000000000000000000010000";
constant st23: std_logic_vector(29 downto 0) := "000000000000000000000000001000";
constant st24: std_logic_vector(29 downto 0) := "000000000000000000000000000100";
constant st26: std_logic_vector(29 downto 0) := "000000000000000000000000000010";
constant st27: std_logic_vector(29 downto 0) := "000000000000000000000000000001";
signal current_state, next_state: std_logic_vector(29 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "------------------------------"; output <= "----------";
case current_state is
when st0 =>
if std_match(input, "1-0000---") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-10-----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-1-0----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0010---") then next_state <= st10; output <= "1000----10";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "1010100110";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st1 =>
if std_match(input, "------0--") then next_state <= st2; output <= "0110010000";
elsif std_match(input, "------1--") then next_state <= st8; output <= "0110100100";
end if;
when st2 =>
if std_match(input, "1-00000--") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0011---") then next_state <= st2; output <= "010100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st2; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st7; output <= "010000--00";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st3 =>
if std_match(input, "1-0000---") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st3; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st3; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st5; output <= "0110001100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st4 =>
if std_match(input, "---------") then next_state <= st6; output <= "0110010000";
end if;
when st5 =>
if std_match(input, "---------") then next_state <= st1; output <= "0110010100";
end if;
when st6 =>
if std_match(input, "1-00000--") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0010---") then next_state <= st4; output <= "0110001000";
elsif std_match(input, "1-0011---") then next_state <= st6; output <= "010100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st6; output <= "010000--00";
elsif std_match(input, "1-0001---") then next_state <= st1; output <= "0110000100";
elsif std_match(input, "1-00001--") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st7 =>
if std_match(input, "1-0000---") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st7; output <= "110100--00";
elsif std_match(input, "11-11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "10-11----") then next_state <= st0; output <= "0010------";
elsif std_match(input, "1-010----") then next_state <= st7; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "01-------") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "00-------") then next_state <= st0; output <= "0000------";
end if;
when st29 =>
if std_match(input, "1-0000---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0010---") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0011---") then next_state <= st29; output <= "110100--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-010----") then next_state <= st29; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110100100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st8 =>
if std_match(input, "---------") then next_state <= st9; output <= "0110010000";
end if;
when st9 =>
if std_match(input, "1-00000--") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-10-----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-1-0----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-001----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st9; output <= "010000--00";
elsif std_match(input, "1-00001--") then next_state <= st28; output <= "010010--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st28 =>
if std_match(input, "1-0000---") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-10-----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-1-0----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1-001----") then next_state <= st28; output <= "110000--00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0010100000";
elsif std_match(input, "1-010----") then next_state <= st10; output <= "110000--00";
elsif std_match(input, "1-0001---") then next_state <= st8; output <= "0110000100";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0010100000";
end if;
when st10 =>
if std_match(input, "1--0---00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1---0--00") then next_state <= st10; output <= "0000----00";
elsif std_match(input, "1--0---10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--10") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0----1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0---1") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st11 =>
if std_match(input, "1--011-0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1---0--0-") then next_state <= st11; output <= "0000----00";
elsif std_match(input, "1--010-0-") then next_state <= st10; output <= "0100----00";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1---0--1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1--0---1-") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st12 =>
if std_match(input, "1--011---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--10----") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1--000---") then next_state <= st12; output <= "0000------";
elsif std_match(input, "1-0001---") then next_state <= st10; output <= "1000----01";
elsif std_match(input, "1--010---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st13 =>
if std_match(input, "1--000---") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--01----") then next_state <= st13; output <= "0000------";
elsif std_match(input, "1--001---") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----01";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st14 =>
if std_match(input, "1--000---") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--01----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--10----") then next_state <= st14; output <= "0000----00";
elsif std_match(input, "1--001---") then next_state <= st15; output <= "0010100100";
elsif std_match(input, "1--11----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st15 =>
if std_match(input, "--1------") then next_state <= st16; output <= "0010010000";
elsif std_match(input, "--0------") then next_state <= st22; output <= "0010010000";
end if;
when st16 =>
if std_match(input, "1--000---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--011---") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st16; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st17 =>
if std_match(input, "1--000---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st18; output <= "0010001100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st17; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st18 =>
if std_match(input, "---------") then next_state <= st19; output <= "0010010100";
end if;
when st19 =>
if std_match(input, "---------") then next_state <= st16; output <= "0010010000";
end if;
when st20 =>
if std_match(input, "---------") then next_state <= st21; output <= "0010010000";
end if;
when st21 =>
if std_match(input, "1--000---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--001---") then next_state <= st19; output <= "0010000100";
elsif std_match(input, "1--010---") then next_state <= st20; output <= "0010001000";
elsif std_match(input, "1--011---") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "1--1-----") then next_state <= st21; output <= "000000--00";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st22 =>
if std_match(input, "1-0000---") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st22; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st23 =>
if std_match(input, "1-0000---") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st24; output <= "0010001100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st23; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when st24 =>
if std_match(input, "---------") then next_state <= st25; output <= "0010010100";
end if;
when st25 =>
if std_match(input, "---------") then next_state <= st22; output <= "0010010000";
end if;
when st26 =>
if std_match(input, "---------") then next_state <= st27; output <= "0010010000";
end if;
when st27 =>
if std_match(input, "1-0000---") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-0001---") then next_state <= st25; output <= "0010000100";
elsif std_match(input, "1-0010---") then next_state <= st26; output <= "0010001000";
elsif std_match(input, "1-0011---") then next_state <= st10; output <= "1000----11";
elsif std_match(input, "1-010----") then next_state <= st27; output <= "000000--00";
elsif std_match(input, "1-011----") then next_state <= st0; output <= "0000------";
elsif std_match(input, "1-1------") then next_state <= st12; output <= "0000------";
elsif std_match(input, "0--------") then next_state <= st0; output <= "0000------";
end if;
when others => next_state <= "------------------------------"; output <= "----------";
end case;
end process;
end behaviour;
|
library ieee;
use ieee.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use ieee.numeric_std.all;
use std.textio.all;
use ieee.std_logic_textio.all;
use work.trfsmparts.all;
use work.trfsmpkg.all;
use work.tb_trfsmpkg.all;
use work.tbfuncs.all;
entity tb_trfsm is
end tb_trfsm;
architecture behavior of tb_trfsm is
constant InputWidth : integer range 1 to 256 := 10;
constant OutputWidth : integer range 1 to 256 := 7;
constant StateWidth : integer range 1 to 8 := 5;
constant UseResetRow : integer range 0 to 1 := 1;
constant UseCurrentState : integer range 0 to 1 := 1;
constant NumRows0 : integer := 3;
constant NumRows1 : integer := 2;
constant NumRows2 : integer := 6;
constant NumRows3 : integer := 6;
constant NumRows4 : integer := 9;
constant NumRows5 : integer := 0;
constant NumRows6 : integer := 0;
constant NumRows7 : integer := 0;
constant NumRows8 : integer := 0;
constant NumRows9 : integer := 0;
constant ConfigLength : integer := CalcTRFSMConfigLength(InputWidth,OutputWidth,StateWidth,UseResetRow,UseCurrentState,NumRows0,NumRows1,NumRows2,NumRows3,NumRows4,NumRows5,NumRows6,NumRows7,NumRows8,NumRows9);
-- Attention: don't make symmetric values because otherwise we can't find
-- problems with the order
constant CBS_S0_S1: std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1010xxxxxx","00000","00001","1100110");
constant CBS_S0_S2 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1111xxxxxx","00000","00010","0011001");
constant CBS_S0_S3 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"0000xxxxxx","00000","00011","0110011");
constant CBS_S0_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!1010xxxxxx,1111xxxxxx,0000xxxxxx","00000","00000","1111111");
constant CBS_S1_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"1100xxxxxx","00001","00110","1111111");
constant CBS_S1_S7 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"0011xxxxxx","00001","00111","1011101");
constant CBS_S1_S1 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!1100xxxxxx,0011xxxxxx","00001","00001","0111110");
constant CBS_S2_S3 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xxxx1xxxxx","00010","00011","1111000");
constant CBS_S2_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxx0xxxxx","00010","00101","0001111");
constant CBS_S3_S4 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,1,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,1,OutputWidth,
"xxxxxxxxx1","00011","00100","1110001");
constant CBS_S3_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,1,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,1,OutputWidth,
"xxxxxxxxx0","00011","00101","1100011");
constant CBS_S4_S1 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xx01xxxxxx","00100","00001","0111000");
constant CBS_S4_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"xx10xxxxxx","00100","00101","1000111");
constant CBS_S4_S4 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"!xx01xxxxxx,xx10xxxxxx","00100","00100","1111100");
constant CBS_S5_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx111","00101","00110","1100010");
constant CBS_S5_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx000","00101","00000","1100111");
constant CBS_S5_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"!xxxxxxx111,xxxxxxx000","00101","00101","0000000");
constant CBS_S6_S0 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,4,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,4,OutputWidth,
"xxxxxxx110","00110","00000","1010101");
constant CBS_S6_S5 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"xxxxxxx010","00110","00101","0101010");
constant CBS_S6_S6 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,3,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,3,OutputWidth,
"!xxxxxxx110,xxxxxxx010","00110","00110","1101111");
constant CBS_S7_S8 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","00111","01000","1011110");
constant CBS_S8_S9 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","01000","01001","1011111");
constant CBS_S9_S2 : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"!","01001","00010","1011100");
-- use an unused state to disable this TR
constant CBS_0_unused : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,0,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,0,OutputWidth,
"","11111","00000","1010101");
-- use a used state but set the IPG to "0000" to disable this TR
constant CBS_2_unused_noinput : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"","00001","00000","1010110");
-- use an unused state to disable this TR but set the IPG to "1111"
constant CBS_2_unused_nostate : std_logic_vector(CalcTRConfigLength(StateWidth,InputWidth,2,OutputWidth)-1 downto 0) :=
GenTRConfigBitStream(StateWidth,InputWidth,2,OutputWidth,
"!","11110","00000","1010111");
-- important: the LSBs of this vector are assiciated with the low-input TRs
constant ConfigBitStream : std_logic_vector(ConfigLength-1 downto 0) :=
-- Width = 0
CBS_S7_S8 &
CBS_S8_S9 &
CBS_0_unused &
-- Width = 1
CBS_S3_S4 &
CBS_S3_S5 &
-- Width = 2
CBS_S2_S3 &
CBS_S4_S1 &
CBS_S4_S5 &
CBS_S9_S2 &
CBS_2_unused_noinput &
CBS_2_unused_nostate &
-- Width = 3
CBS_S2_S5 &
CBS_S5_S6 &
CBS_S5_S0 &
CBS_S5_S5 &
CBS_S6_S5 &
CBS_S6_S6 &
-- Width = 4
CBS_S0_S1 &
CBS_S0_S2 &
CBS_S0_S3 &
CBS_S0_S0 &
CBS_S1_S6 &
CBS_S1_S7 &
CBS_S1_S1 &
CBS_S4_S4 &
CBS_S6_S0;
constant CfgClkHalfPeriode : time := 100 ns;
constant CheckOutputDelay : time := 20 ns;
constant SetupNextInputDelay : time := 20 ns;
signal Reset_n_i : std_logic;
signal Clk_i : std_logic;
signal Input_i : std_logic_vector(InputWidth-1 downto 0);
signal Output_o : std_logic_vector(OutputWidth-1 downto 0);
signal CfgMode_i : std_logic;
signal CfgClk_i : std_logic;
signal CfgShift_i : std_logic;
signal CfgDataIn_i : std_logic;
signal CfgDataOut_o : std_logic;
signal ScanEnable_i : std_logic;
signal ScanClk_i : std_logic;
signal ScanDataIn_i : std_logic;
signal ScanDataOut_o : std_logic;
procedure CheckTRFSM (
constant Input : in std_logic_vector(InputWidth-1 downto 0);
constant Output : in std_logic_vector(OutputWidth-1 downto 0);
signal Input_i : out std_logic_vector(InputWidth-1 downto 0);
signal Output_o : in std_logic_vector(OutputWidth-1 downto 0)
) is
variable l : line;
begin
Input_i <= Input;
write(l,string'("Input = "));
write(l,Input);
wait for CheckOutputDelay;
write(l,string'(" => Output = "));
write(l,Output_o);
if Output_o = Output then
write(l,string'(" OK "));
else
write(l,string'(" ERROR: should be "));
write(l,Output);
end if;
writeline(std.textio.output,l);
wait for SetupNextInputDelay;
end CheckTRFSM;
procedure ClkCycle (
signal Clk_i : out std_logic
) is
begin
Clk_i <= '1';
wait for CfgClkHalfPeriode;
Clk_i <= '0';
wait for CfgClkHalfPeriode;
end ClkCycle;
begin -- behavior
TRFSM_1: TRFSM
generic map (
InputWidth => InputWidth,
OutputWidth => OutputWidth,
StateWidth => StateWidth,
UseResetRow => UseResetRow,
NumRows0 => NumRows0,
NumRows1 => NumRows1,
NumRows2 => NumRows2,
NumRows3 => NumRows3,
NumRows4 => NumRows4,
NumRows5 => NumRows5,
NumRows6 => NumRows6,
NumRows7 => NumRows7,
NumRows8 => NumRows8,
NumRows9 => NumRows9)
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Input_i => Input_i,
Output_o => Output_o,
CfgMode_i => CfgMode_i,
CfgClk_i => CfgClk_i,
CfgShift_i => CfgShift_i,
CfgDataIn_i => CfgDataIn_i,
CfgDataOut_o => CfgDataOut_o,
ScanEnable_i => ScanEnable_i,
ScanClk_i => ScanClk_i,
ScanDataIn_i => ScanDataIn_i,
ScanDataOut_o => ScanDataOut_o);
Check: process
begin -- process Check
-- set all inputs
Clk_i <= '0';
Input_i <= (others => '0');
CfgMode_i <= '0';
CfgClk_i <= '0';
CfgShift_i <= '0';
CfgDataIn_i <= '0';
ScanEnable_i <= '0';
ScanClk_i <= '0';
ScanDataIn_i <= '0';
---------------------------------------------------------------------------
-- Reset
---------------------------------------------------------------------------
Reset_n_i <= '0';
wait for 1 us;
Reset_n_i <= '1';
wait for 1 ns;
---------------------------------------------------------------------------
-- Configuration
---------------------------------------------------------------------------
-- shift in the config bit stream with LSB first, the ConfigRegister will
-- shift this from right to left (=MSB to LSB), so after everything is
-- shifted, the bits have the same order as setup above and as visible at
-- the screen.
-- assert false report "ConfigBitStream = " & Vector2String(ConfigBitStream) severity note;
CfgMode_i <= '1';
CfgShift_i <= '1';
wait for CfgClkHalfPeriode; -- strange, ModelSim needs this :-(
for i in 0 to ConfigLength-1 loop
CfgDataIn_i <= ConfigBitStream(i);
wait for 1 ns; -- strange, ModelSim needs this :-(
CfgClk_i <= '1';
wait for CfgClkHalfPeriode;
CfgClk_i <= '0';
wait for CfgClkHalfPeriode;
end loop; -- i
CfgMode_i <= '0';
CfgShift_i <= '0';
wait for 1 ns; -- strange, ModelSim needs this :-(
assert false report "### Configuration done" severity note;
-- 127129ns
---------------------------------------------------------------------------
-- Action
---------------------------------------------------------------------------
-- State 0, test all transitions
CheckTRFSM("1010000000","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010111111","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010110011","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010010101","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1010101010","1100110",Input_i,Output_o); -- to S1
CheckTRFSM("1111000000","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111111111","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111001100","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111101010","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("1111010111","0011001",Input_i,Output_o); -- to S2
CheckTRFSM("0000000000","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000111111","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000101010","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000010101","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("0000110111","0110011",Input_i,Output_o); -- to S3
CheckTRFSM("1110000000","1111111",Input_i,Output_o); -- stay
CheckTRFSM("1110111011","1111111",Input_i,Output_o); -- stay
CheckTRFSM("0010000000","1111111",Input_i,Output_o); -- stay
CheckTRFSM("0101000000","1111111",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 0 again
CheckTRFSM("1010110111","1100110",Input_i,Output_o); -- to S1
ClkCycle(Clk_i);
-- State 1
CheckTRFSM("1100110111","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("1100111111","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("1100000000","1111111",Input_i,Output_o); -- to S6
CheckTRFSM("0011000000","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("0011111111","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("0011010101","1011101",Input_i,Output_o); -- to S7
CheckTRFSM("1111110111","0111110",Input_i,Output_o); -- stay
CheckTRFSM("0000000000","0111110",Input_i,Output_o); -- stay
CheckTRFSM("0010010101","0111110",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1100011001","1111111",Input_i,Output_o); -- to S6
ClkCycle(Clk_i);
-- State 6
CheckTRFSM("0000000110","1010101",Input_i,Output_o); -- to S0
CheckTRFSM("0000000010","0101010",Input_i,Output_o); -- to S5
CheckTRFSM("0000000111","1101111",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1111111010","0101010",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("0000000111","1100010",Input_i,Output_o); -- to S6
CheckTRFSM("1010111000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1111110111","0011001",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("0000100000","1111000",Input_i,Output_o); -- to S3
CheckTRFSM("0001110000","1111000",Input_i,Output_o); -- to S3
CheckTRFSM("1111011111","0001111",Input_i,Output_o); -- to S5
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
CheckTRFSM("0001110011","1111000",Input_i,Output_o); -- to S3
ClkCycle(Clk_i);
-- State 3
CheckTRFSM("0000000001","1110001",Input_i,Output_o); -- to S4
CheckTRFSM("1010101011","1110001",Input_i,Output_o); -- to S4
CheckTRFSM("0000000000","1100011",Input_i,Output_o); -- to S5
CheckTRFSM("0101010100","1100011",Input_i,Output_o); -- to S5
CheckTRFSM("0011100111","1110001",Input_i,Output_o); -- to S4
ClkCycle(Clk_i);
-- State 4
CheckTRFSM("0001000000","0111000",Input_i,Output_o); -- to S1
CheckTRFSM("1101111111","0111000",Input_i,Output_o); -- to S1
CheckTRFSM("0010000000","1000111",Input_i,Output_o); -- to S5
CheckTRFSM("1110111111","1000111",Input_i,Output_o); -- to S5
CheckTRFSM("1111111111","1111100",Input_i,Output_o); -- stay
CheckTRFSM("1100111111","1111100",Input_i,Output_o); -- stay
ClkCycle(Clk_i);
-- State 1 again
CheckTRFSM("1010101010","1000111",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("1111111111","1100010",Input_i,Output_o); -- to S6
ClkCycle(Clk_i);
-- State 6
CheckTRFSM("0000000110","1010101",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1111110111","0011001",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("1010111000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("0000011010","0110011",Input_i,Output_o); -- to S3
ClkCycle(Clk_i);
-- State 3
CheckTRFSM("1111111110","1100011",Input_i,Output_o); -- to S5
ClkCycle(Clk_i);
-- State 5
CheckTRFSM("0010011111","1100010",Input_i,Output_o); -- to S6
CheckTRFSM("0101010000","1100111",Input_i,Output_o); -- to S0
ClkCycle(Clk_i);
-- State 0
CheckTRFSM("1010011010","1100110",Input_i,Output_o); -- to S1
ClkCycle(Clk_i);
-- State 1
CheckTRFSM("0011000000","1011101",Input_i,Output_o); -- to S7
ClkCycle(Clk_i);
-- State 7
CheckTRFSM("0000000000","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1111111111","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1010101010","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("0101010101","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("1100110011","1011110",Input_i,Output_o); -- to S8
CheckTRFSM("0011001100","1011110",Input_i,Output_o); -- to S8
ClkCycle(Clk_i);
-- State 8
CheckTRFSM("0000000000","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1111111111","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1010101010","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("0101010101","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("1100110011","1011111",Input_i,Output_o); -- to S9
CheckTRFSM("0011001100","1011111",Input_i,Output_o); -- to S9
ClkCycle(Clk_i);
-- State 9
CheckTRFSM("0000000000","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1111111111","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1010101010","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("0101010101","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("1100110011","1011100",Input_i,Output_o); -- to S2
CheckTRFSM("0011001100","1011100",Input_i,Output_o); -- to S2
ClkCycle(Clk_i);
-- State 2
CheckTRFSM("1110001111","0001111",Input_i,Output_o); -- to S5
---------------------------------------------------------------------------
-- Simulation is finished
---------------------------------------------------------------------------
assert 0 = 1
report " simulation is finished "
severity failure ;
end process Check;
end behavior;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mult_pkg is
type mult_state_t is (NOP, DMULSL, DMULSL1, DMULSL2, DMULUL, DMULUL1, DMULUL2, MACL, MACL1, MACL2, MACW, MACW1, MACWS, MACWS1, MULL, MULL1, MULL2, MULSW, MULSW1, MULUW, MULUW1);
type mult_result_op_t is (IDENTITY, SATURATE32, SATURATE64);
type mult_sela_t is ( M1, MB );
type mult_size_t is ( B16, B32 );
constant P48MAX : std_logic_vector(63 downto 0) := x"00007fffffffffff";
constant N48MAX : std_logic_vector(63 downto 0) := x"ffff800000000000";
constant P32MAX : std_logic_vector(63 downto 0) := x"000000007fffffff";
constant N32MAX : std_logic_vector(63 downto 0) := x"ffffffff80000000";
type mult_codeline_t is record
state : mult_state_t;
busy : std_logic;
sela : mult_sela_t;
shift : std_logic;
sign : integer range 0 to 1;
size : mult_size_t;
mach_en : std_logic;
macl_en : std_logic;
use_h : std_logic;
end record;
type mult_microcode_t is array (mult_state_t) of mult_codeline_t;
constant MULT_CODE : mult_microcode_t := (
-- state busy sela shft sign size h_en l_en use_h
( NOP, '0', M1, '0', 0, B16, '0', '0', '1' ), -- NOP
( DMULSL1, '1', M1, '0', 1, B32, '0', '0', '1' ), -- DMULSL
( DMULSL2, '1', M1, '1', 1, B32, '1', '1', '1' ), -- DMULSL1
( NOP, '0', M1, '1', 1, B32, '1', '1', '1' ), -- DMULSL2
( DMULUL1, '1', M1, '0', 0, B32, '0', '0', '1' ), -- DMULUL
( DMULUL2, '1', M1, '1', 0, B32, '1', '1', '1' ), -- DMULUL1
( NOP, '0', M1, '1', 0, B32, '1', '1', '1' ), -- DMULUL2
( MACL1, '1', MB, '0', 1, B32, '0', '0', '1' ), -- MACL
( MACL2, '1', MB, '1', 1, B32, '1', '1', '1' ), -- MACL1
( NOP, '0', MB, '1', 1, B32, '1', '1', '1' ), -- MACL2
( MACW1, '1', M1, '0', 1, B16, '0', '0', '1' ), -- MACW
( NOP, '0', M1, '0', 1, B16, '1', '1', '1' ), -- MACW1
( MACWS1, '1', M1, '0', 1, B16, '0', '0', '0' ), -- MACWS
( NOP, '0', M1, '0', 1, B16, '0', '1', '0' ), -- MACWS1
( MULL1, '1', M1, '0', 1, B32, '0', '0', '0' ), -- MULL
( MULL2, '1', M1, '1', 1, B32, '0', '1', '0' ), -- MULL1
( NOP, '0', M1, '1', 1, B32, '0', '1', '0' ), -- MULL2
( MULSW1, '1', M1, '0', 1, B16, '0', '0', '0' ), -- MULSW
( NOP, '0', M1, '0', 1, B16, '0', '1', '0' ), -- MULSW1
( MULUW1, '1', M1, '0', 0, B16, '0', '0', '0' ), -- MULUW
( NOP, '0', M1, '0', 0, B16, '0', '1', '0' ) -- MULUW1
);
type mult_i_t is record
wr_m1 : std_logic;
command : mult_state_t;
s : std_logic;
wr_mach : std_logic;
wr_macl : std_logic;
in1 : std_logic_vector(31 downto 0);
in2 : std_logic_vector(31 downto 0);
end record;
type mult_o_t is record
mach : std_logic_vector(31 downto 0);
macl : std_logic_vector(31 downto 0);
busy : std_logic;
end record;
type mult_reg_t is record
state : mult_state_t;
result_op : mult_result_op_t;
m1, m2, mb : std_logic_vector(31 downto 0);
p23 : std_logic_vector(31 downto 0);
mach, macl : std_logic_vector(31 downto 0);
shift : std_logic;
abh : std_logic_vector(46 downto 0);
end record;
constant MULT_RESET : mult_reg_t := (state => NOP,
result_op => IDENTITY,
m1 => (others => '0'),
m2 => (others => '0'),
mb => (others => '0'),
p23 => (others => '0'),
mach => (others => '0'),
macl => (others => '0'),
shift => '0',
abh => (others => '0')
);
component mult is
port (
clk : in std_logic;
rst : in std_logic;
slot : in std_logic;
a : in mult_i_t;
y : out mult_o_t);
end component mult;
function to_slv(b : std_logic; s : integer) return std_logic_vector;
end package;
package body mult_pkg is
function to_slv(b : std_logic; s : integer) return std_logic_vector is
variable r : std_logic_vector(s-1 downto 0);
begin
r := (others => b);
return r;
end function to_slv;
end package body;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc168.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x00p01n01i00168ent IS
END c04s03b03x00p01n01i00168ent;
ARCHITECTURE c04s03b03x00p01n01i00168arch OF c04s03b03x00p01n01i00168ent IS
BEGIN
TESTING: PROCESS
variable V1 : INTEGER := 1;
alias V1_A1 : INTEGER is V1;
-- scalar alias of scalar
-- alias of variable
alias V1_A2 : INTEGER is V1_A1;
-- alias of alias
variable pass : integer := 0;
BEGIN
assert V1 = 1;
assert V1_A1 = 1;
assert V1_A2 = 1;
if (V1 /= 1 or V1_A1 /= 1 or V1_A2 /= 1) then
pass := 1;
end if;
V1 := 2; -- change value...
assert V1 = 2;
assert V1_A1 = 2; -- ... check read
assert V1_A2 = 2; -- ... check read
if (V1 /= 2 or V1_A1 /= 2 or V1_A2 /= 2) then
pass := 1;
end if;
V1_A1 := 3; -- change value using alias
assert V1 = 3; -- ... check that value changed
assert V1_A1 = 3;
assert V1_A2 = 3;
if (V1 /= 3 or V1_A1 /= 3 or V1_A2 /= 3) then
pass := 1;
end if;
V1_A2 := 4; -- change value using alias
assert V1 = 4; -- ... check that value changed
assert V1_A1 = 4;
assert V1_A2 = 4;
if (V1 /= 4 or V1_A1 /= 4 or V1_A2 /= 4) then
pass := 1;
end if;
wait for 5 ns;
assert NOT( pass = 0 )
report "***PASSED TEST: c04s03b03x00p01n01i00168"
severity NOTE;
assert ( pass = 0 )
report "***FAILED TEST: c04s03b03x00p01n01i00168 - Alias of alias variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x00p01n01i00168arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc168.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x00p01n01i00168ent IS
END c04s03b03x00p01n01i00168ent;
ARCHITECTURE c04s03b03x00p01n01i00168arch OF c04s03b03x00p01n01i00168ent IS
BEGIN
TESTING: PROCESS
variable V1 : INTEGER := 1;
alias V1_A1 : INTEGER is V1;
-- scalar alias of scalar
-- alias of variable
alias V1_A2 : INTEGER is V1_A1;
-- alias of alias
variable pass : integer := 0;
BEGIN
assert V1 = 1;
assert V1_A1 = 1;
assert V1_A2 = 1;
if (V1 /= 1 or V1_A1 /= 1 or V1_A2 /= 1) then
pass := 1;
end if;
V1 := 2; -- change value...
assert V1 = 2;
assert V1_A1 = 2; -- ... check read
assert V1_A2 = 2; -- ... check read
if (V1 /= 2 or V1_A1 /= 2 or V1_A2 /= 2) then
pass := 1;
end if;
V1_A1 := 3; -- change value using alias
assert V1 = 3; -- ... check that value changed
assert V1_A1 = 3;
assert V1_A2 = 3;
if (V1 /= 3 or V1_A1 /= 3 or V1_A2 /= 3) then
pass := 1;
end if;
V1_A2 := 4; -- change value using alias
assert V1 = 4; -- ... check that value changed
assert V1_A1 = 4;
assert V1_A2 = 4;
if (V1 /= 4 or V1_A1 /= 4 or V1_A2 /= 4) then
pass := 1;
end if;
wait for 5 ns;
assert NOT( pass = 0 )
report "***PASSED TEST: c04s03b03x00p01n01i00168"
severity NOTE;
assert ( pass = 0 )
report "***FAILED TEST: c04s03b03x00p01n01i00168 - Alias of alias variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x00p01n01i00168arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc168.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b03x00p01n01i00168ent IS
END c04s03b03x00p01n01i00168ent;
ARCHITECTURE c04s03b03x00p01n01i00168arch OF c04s03b03x00p01n01i00168ent IS
BEGIN
TESTING: PROCESS
variable V1 : INTEGER := 1;
alias V1_A1 : INTEGER is V1;
-- scalar alias of scalar
-- alias of variable
alias V1_A2 : INTEGER is V1_A1;
-- alias of alias
variable pass : integer := 0;
BEGIN
assert V1 = 1;
assert V1_A1 = 1;
assert V1_A2 = 1;
if (V1 /= 1 or V1_A1 /= 1 or V1_A2 /= 1) then
pass := 1;
end if;
V1 := 2; -- change value...
assert V1 = 2;
assert V1_A1 = 2; -- ... check read
assert V1_A2 = 2; -- ... check read
if (V1 /= 2 or V1_A1 /= 2 or V1_A2 /= 2) then
pass := 1;
end if;
V1_A1 := 3; -- change value using alias
assert V1 = 3; -- ... check that value changed
assert V1_A1 = 3;
assert V1_A2 = 3;
if (V1 /= 3 or V1_A1 /= 3 or V1_A2 /= 3) then
pass := 1;
end if;
V1_A2 := 4; -- change value using alias
assert V1 = 4; -- ... check that value changed
assert V1_A1 = 4;
assert V1_A2 = 4;
if (V1 /= 4 or V1_A1 /= 4 or V1_A2 /= 4) then
pass := 1;
end if;
wait for 5 ns;
assert NOT( pass = 0 )
report "***PASSED TEST: c04s03b03x00p01n01i00168"
severity NOTE;
assert ( pass = 0 )
report "***FAILED TEST: c04s03b03x00p01n01i00168 - Alias of alias variable test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b03x00p01n01i00168arch;
|
entity bug7 is
end entity bug7;
architecture x of bug7 is
constant cst : real := 5.5;
signal test : integer;
begin
test <= cst;
end architecture x;
|
entity bug7 is
end entity bug7;
architecture x of bug7 is
constant cst : real := 5.5;
signal test : integer;
begin
test <= cst;
end architecture x;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter_tb is
end entity;
architecture number_splitter_tb_arq of number_splitter_tb is
signal number_in: std_logic_vector(22 downto 0);
signal sign_out: std_logic;
signal exp_out: std_logic_vector(5 downto 0);
signal mant_out: std_logic_vector(15 downto 0);
component number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end component;
for number_splitter_0: number_splitter use entity work.number_splitter;
begin
number_splitter_0: number_splitter port map(
number_in => number_in,
sign_out => sign_out,
exp_out => exp_out,
mant_out => mant_out
);
process
type pattern_type is record
n : std_logic_vector(22 downto 0); --input number
s : std_logic; --output sign
m : std_logic_vector(15 downto 0); --output mantisa
e : std_logic_vector(5 downto 0); --output exponent
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
("11111111111111111111111", '1', "1111111111111111", "111111"),
("00000000000000000000000", '0', "0000000000000000", "000000"),
("10101010101010101010101", '1', "0101010101010101", "010101")
);
begin
for i in patterns'range loop
-- Set the inputs.
number_in <= patterns(i).n;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert sign_out = patterns(i).s report "BAD SIGN: " & std_logic'image(sign_out) severity error;
assert mant_out = patterns(i).m report "BAD MANTISSA: " & integer'image(to_integer(unsigned(mant_out))) severity error;
assert exp_out = patterns(i).e report "BAD EXP: " & integer'image(to_integer(unsigned(exp_out))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity number_splitter_tb is
end entity;
architecture number_splitter_tb_arq of number_splitter_tb is
signal number_in: std_logic_vector(22 downto 0);
signal sign_out: std_logic;
signal exp_out: std_logic_vector(5 downto 0);
signal mant_out: std_logic_vector(15 downto 0);
component number_splitter is
generic(
TOTAL_BITS:natural := 23;
EXP_BITS:natural := 6);
port (
number_in: in std_logic_vector(TOTAL_BITS-1 downto 0);
sign_out: out std_logic;
exp_out: out std_logic_vector(EXP_BITS-1 downto 0);
mant_out: out std_logic_vector(TOTAL_BITS - EXP_BITS - 2 downto 0)
);
end component;
for number_splitter_0: number_splitter use entity work.number_splitter;
begin
number_splitter_0: number_splitter port map(
number_in => number_in,
sign_out => sign_out,
exp_out => exp_out,
mant_out => mant_out
);
process
type pattern_type is record
n : std_logic_vector(22 downto 0); --input number
s : std_logic; --output sign
m : std_logic_vector(15 downto 0); --output mantisa
e : std_logic_vector(5 downto 0); --output exponent
end record;
-- The patterns to apply.
type pattern_array is array (natural range<>) of pattern_type;
constant patterns : pattern_array := (
("11111111111111111111111", '1', "1111111111111111", "111111"),
("00000000000000000000000", '0', "0000000000000000", "000000"),
("10101010101010101010101", '1', "0101010101010101", "010101")
);
begin
for i in patterns'range loop
-- Set the inputs.
number_in <= patterns(i).n;
-- Wait for the results.
wait for 1 ns;
-- Check the outputs.
assert sign_out = patterns(i).s report "BAD SIGN: " & std_logic'image(sign_out) severity error;
assert mant_out = patterns(i).m report "BAD MANTISSA: " & integer'image(to_integer(unsigned(mant_out))) severity error;
assert exp_out = patterns(i).e report "BAD EXP: " & integer'image(to_integer(unsigned(exp_out))) severity error;
end loop;
assert false report "end of test" severity note;
wait;
end process;
end;
|
-- NEED RESULT: ARCH00479: Choices in an element association of an aggregate may contain several or no choices passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00479
--
-- AUTHOR:
--
-- A. Wilmot
--
-- TEST OBJECTIVES:
--
-- 7.3.2 (7)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00479)
-- ENT00479_Test_Bench(ARCH00479_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00479 of E00000 is
type rec_1 is record
f1 : integer ;
f2 : integer ;
f3 : integer ;
f4 : bit_vector ( 0 to 3 ) ;
end record ;
type arr_1 is array ( integer range <> ) of bit_vector ( 0 to 3 ) ;
begin
process
variable v_int1 : integer := 4 ;
variable bool : boolean := true ;
variable v_rec_1_1, v_rec_1_2, v_rec_1_3 : rec_1 ;
subtype st_arr1 is arr_1 ( 1 to 4 ) ;
variable v_arr_1_1, v_arr_1_2, v_arr_1_3 : st_arr1 ;
begin
v_rec_1_1 := ( v_int1, v_int1, 3, f4 => B"0011" );
v_rec_1_2 := ( 3, f4 => B"1100", f2 | f3 => 4 ) ;
v_rec_1_3 := ( 3, 5, f4 => B"1010", others => 2 ) ;
v_arr_1_1 := ( B"0000", B"0001", B"0010", others => B"0010" ) ;
v_arr_1_2 := ( B"0011", B"0100", others => B"0101" ) ;
v_arr_1_3 := ( B"0110", B"1000", B"0111", others => B"1000" ) ;
bool := bool and v_rec_1_1.f1 = v_int1 ;
bool := bool and v_rec_1_1.f2 = v_int1 ;
bool := bool and v_rec_1_1.f3 = 3 ;
bool := bool and v_rec_1_1.f4 = B"0011" ;
bool := bool and v_rec_1_2.f1 = 3 ;
bool := bool and v_rec_1_2.f2 = 4 ;
bool := bool and v_rec_1_2.f3 = 4 ;
bool := bool and v_rec_1_2.f4 = B"1100" ;
bool := bool and v_rec_1_3.f1 = 3 ;
bool := bool and v_rec_1_3.f2 = 5 ;
bool := bool and v_rec_1_3.f3 = 2 ;
bool := bool and v_rec_1_3.f4 = B"1010" ;
bool := bool and v_arr_1_1(1) = B"0000" ;
bool := bool and v_arr_1_1(2) = B"0001" ;
bool := bool and v_arr_1_1(3) = B"0010" ;
bool := bool and v_arr_1_1(4) = B"0010" ;
bool := bool and v_arr_1_2(1) = B"0011" ;
bool := bool and v_arr_1_2(2) = B"0100" ;
bool := bool and v_arr_1_2(3) = B"0101" ;
bool := bool and v_arr_1_2(4) = B"0101" ;
bool := bool and v_arr_1_3(1) = B"0110" ;
bool := bool and v_arr_1_3(2) = B"1000" ;
bool := bool and v_arr_1_3(3) = B"0111" ;
bool := bool and v_arr_1_3(4) = B"1000" ;
test_report ( "ARCH00479" ,
"Choices in an element association of an aggregate"
& " may contain several or no choices" ,
bool ) ;
wait ;
end process ;
end ARCH00479 ;
entity ENT00479_Test_Bench is
end ENT00479_Test_Bench ;
architecture ARCH00479_Test_Bench of ENT00479_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00479 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00479_Test_Bench ;
|
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3;
v := c(1 to 2);
assert v = (1, 2);
v := c(3 to 4);
assert v = (3, 4);
wait;
end process;
end architecture;
|
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3;
v := c(1 to 2);
assert v = (1, 2);
v := c(3 to 4);
assert v = (3, 4);
wait;
end process;
end architecture;
|
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3;
v := c(1 to 2);
assert v = (1, 2);
v := c(3 to 4);
assert v = (3, 4);
wait;
end process;
end architecture;
|
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3;
v := c(1 to 2);
assert v = (1, 2);
v := c(3 to 4);
assert v = (3, 4);
wait;
end process;
end architecture;
|
entity const1 is
end entity;
architecture test of const1 is
type int_vector is array (integer range <>) of integer;
constant c : int_vector(1 to 5) := (1, 2, 3, 4, 5);
begin
process is
variable v : int_vector(1 to 2);
variable i : integer;
begin
i := c(3);
assert i = 3;
v := c(1 to 2);
assert v = (1, 2);
v := c(3 to 4);
assert v = (3, 4);
wait;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--! @file addrDecodeRtl.vhd
--
--! @brief Address Decoder for generating select signal
--
--! @details This address decoder generates a select signal depending on the
--! provided base- and high-addresses by using smaller/greater logic.
--! Additionally a strob is generated if the base or high address is selected.
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.global.all;
entity addrDecode is
generic (
--! Address bus width
gAddrWidth : natural := 32;
--! Decode space base address
gBaseAddr : natural := 16#1000#;
--! Decode space high address
gHighAddr : natural := 16#1FFF#
);
port (
--! Enable decoding
iEnable : in std_logic;
--! Address bus
iAddress : in std_logic_vector(gAddrWidth-1 downto 0);
--! Select output
oSelect : out std_logic
);
end addrDecode;
architecture rtl of addrDecode is
--! Address to be decoded
signal address : unsigned(gAddrWidth-1 downto 0);
--! Address is in range
signal addressInRange : std_logic;
--! Base address used for comparison
constant cBase : unsigned(gAddrWidth-1 downto 0) :=
to_unsigned(gBaseAddr, gAddrWidth);
--! High address used for comparison
constant cHigh : unsigned(gAddrWidth-1 downto 0) :=
to_unsigned(gHighAddr, gAddrWidth);
begin
-- check generics
assert (gBaseAddr < gHighAddr)
report "Base address should be smaller than High address!" severity failure;
-- connect ports to signals
oSelect <= addressInRange;
address <= unsigned(iAddress);
--! Decode input address logic
combAddrDec : process (
iEnable,
address
)
begin
--default assignments of process outputs
addressInRange <= cInactivated;
if iEnable = cActivated then
if (cBase <= address) and (address <= cHigh) then
addressInRange <= cActivated;
end if;
end if;
end process;
end rtl;
|
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