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--
-- BLK MEM GEN v7_2 Core - Stimulus Generator For TDP
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006_3010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: bmg_stim_gen.vhd
--
-- Description:
-- Stimulus Generation For TDP
-- 100 Writes and 100 Reads will be performed in a repeatitive loop till the
-- simulation ends
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: Sep 12, 2011 - First Release
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY REGISTER_LOGIC_TDP IS
PORT(
Q : OUT STD_LOGIC;
CLK : IN STD_LOGIC;
RST : IN STD_LOGIC;
D : IN STD_LOGIC
);
END REGISTER_LOGIC_TDP;
ARCHITECTURE REGISTER_ARCH OF REGISTER_LOGIC_TDP IS
SIGNAL Q_O : STD_LOGIC :='0';
BEGIN
Q <= Q_O;
FF_BEH: PROCESS(CLK)
BEGIN
IF(RISING_EDGE(CLK)) THEN
IF(RST ='1') THEN
Q_O <= '0';
ELSE
Q_O <= D;
END IF;
END IF;
END PROCESS;
END REGISTER_ARCH;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
--USE IEEE.NUMERIC_STD.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
USE IEEE.STD_LOGIC_MISC.ALL;
LIBRARY work;
USE work.ALL;
USE work.BMG_TB_PKG.ALL;
ENTITY BMG_STIM_GEN IS
PORT (
CLKA : IN STD_LOGIC;
CLKB : IN STD_LOGIC;
TB_RST : IN STD_LOGIC;
ADDRA : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINA : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
ENA : OUT STD_LOGIC :='0';
WEA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
WEB : OUT STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '0');
ADDRB : OUT STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
DINB : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
ENB : OUT STD_LOGIC :='0';
CHECK_DATA: OUT STD_LOGIC_VECTOR(1 DOWNTO 0):=(OTHERS => '0')
);
END BMG_STIM_GEN;
ARCHITECTURE BEHAVIORAL OF BMG_STIM_GEN IS
CONSTANT ZERO : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
CONSTANT ADDR_ZERO : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
CONSTANT DATA_PART_CNT_A : INTEGER:= DIVROUNDUP(16,16);
CONSTANT DATA_PART_CNT_B : INTEGER:= DIVROUNDUP(16,16);
SIGNAL WRITE_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_A : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL WRITE_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_INT_B : STD_LOGIC_VECTOR(9 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_A : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL READ_ADDR_B : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINA_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL DINB_INT : STD_LOGIC_VECTOR(15 DOWNTO 0) := (OTHERS => '0');
SIGNAL MAX_COUNT : STD_LOGIC_VECTOR(10 DOWNTO 0):=CONV_STD_LOGIC_VECTOR(1024,11);
SIGNAL DO_WRITE_A : STD_LOGIC := '0';
SIGNAL DO_READ_A : STD_LOGIC := '0';
SIGNAL DO_WRITE_B : STD_LOGIC := '0';
SIGNAL DO_READ_B : STD_LOGIC := '0';
SIGNAL COUNT_NO : STD_LOGIC_VECTOR (10 DOWNTO 0):=(OTHERS => '0');
SIGNAL DO_READ_RA : STD_LOGIC := '0';
SIGNAL DO_READ_RB : STD_LOGIC := '0';
SIGNAL DO_READ_REG_A: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL DO_READ_REG_B: STD_LOGIC_VECTOR(4 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEA_VCC: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEA_GND: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '0');
SIGNAL WEB_VCC: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '1');
SIGNAL WEB_GND: STD_LOGIC_VECTOR(1 DOWNTO 0) :=(OTHERS => '0');
SIGNAL COUNT : integer := 0;
SIGNAL COUNT_B : integer := 0;
CONSTANT WRITE_CNT_A : integer := 6;
CONSTANT READ_CNT_A : integer := 6;
CONSTANT WRITE_CNT_B : integer := 4;
CONSTANT READ_CNT_B : integer := 4;
signal porta_wr_rd : std_logic:='0';
signal portb_wr_rd : std_logic:='0';
signal porta_wr_rd_complete: std_logic:='0';
signal portb_wr_rd_complete: std_logic:='0';
signal incr_cnt : std_logic :='0';
signal incr_cnt_b : std_logic :='0';
SIGNAL PORTB_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTA_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_R2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_HAPPENED: STD_LOGIC :='0';
SIGNAL LATCH_PORTB_WR_RD_COMPLETE : STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L1 :STD_LOGIC :='0';
SIGNAL PORTB_WR_RD_L2 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R1 :STD_LOGIC :='0';
SIGNAL PORTA_WR_RD_R2 :STD_LOGIC :='0';
BEGIN
WRITE_ADDR_INT_A(9 DOWNTO 0) <= WRITE_ADDR_A(9 DOWNTO 0);
READ_ADDR_INT_A(9 DOWNTO 0) <= READ_ADDR_A(9 DOWNTO 0);
ADDRA <= IF_THEN_ELSE(DO_WRITE_A='1',WRITE_ADDR_INT_A,READ_ADDR_INT_A) ;
WRITE_ADDR_INT_B(9 DOWNTO 0) <= WRITE_ADDR_B(9 DOWNTO 0);
--To avoid collision during idle period, negating the read_addr of port A
READ_ADDR_INT_B(9 DOWNTO 0) <= IF_THEN_ELSE( (DO_WRITE_B='0' AND DO_READ_B='0'),ADDR_ZERO,READ_ADDR_B(9 DOWNTO 0));
ADDRB <= IF_THEN_ELSE(DO_WRITE_B='1',WRITE_ADDR_INT_B,READ_ADDR_INT_B) ;
DINA <= DINA_INT ;
DINB <= DINB_INT ;
CHECK_DATA(0) <= DO_READ_A;
CHECK_DATA(1) <= DO_READ_B;
RD_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_READ_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_A
);
WR_ADDR_GEN_INST_A:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH =>1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_A
);
RD_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_READ_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => READ_ADDR_B
);
WR_ADDR_GEN_INST_B:ENTITY work.ADDR_GEN
GENERIC MAP( C_MAX_DEPTH => 1024 ,
RST_INC => 1 )
PORT MAP(
CLK => CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
LOAD => '0',
LOAD_VALUE => ZERO,
ADDR_OUT => WRITE_ADDR_B
);
WR_DATA_GEN_INST_A:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>16,
DOUT_WIDTH => 16,
DATA_PART_CNT => 1,
SEED => 2)
PORT MAP (
CLK =>CLKA,
RST => TB_RST,
EN => DO_WRITE_A,
DATA_OUT => DINA_INT
);
WR_DATA_GEN_INST_B:ENTITY work.DATA_GEN
GENERIC MAP ( DATA_GEN_WIDTH =>16,
DOUT_WIDTH =>16 ,
DATA_PART_CNT =>1,
SEED => 2)
PORT MAP (
CLK =>CLKB,
RST => TB_RST,
EN => DO_WRITE_B,
DATA_OUT => DINB_INT
);
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
ELSIF(PORTB_WR_RD_COMPLETE='1') THEN
LATCH_PORTB_WR_RD_COMPLETE <='1';
ELSIF(PORTA_WR_RD_HAPPENED='1') THEN
LATCH_PORTB_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_L1 <='0';
PORTB_WR_RD_L2 <='0';
ELSE
PORTB_WR_RD_L1 <= LATCH_PORTB_WR_RD_COMPLETE;
PORTB_WR_RD_L2 <= PORTB_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_EN: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD <='1';
ELSE
PORTA_WR_RD <= PORTB_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_R1 <='0';
PORTA_WR_RD_R2 <='0';
ELSE
PORTA_WR_RD_R1 <=PORTA_WR_RD;
PORTA_WR_RD_R2 <=PORTA_WR_RD_R1;
END IF;
END IF;
END PROCESS;
PORTA_WR_RD_HAPPENED <= PORTA_WR_RD_R2;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
ELSIF(PORTA_WR_RD_COMPLETE='1') THEN
LATCH_PORTA_WR_RD_COMPLETE <='1';
ELSIF(PORTB_WR_RD_HAPPENED='1') THEN
LATCH_PORTA_WR_RD_COMPLETE<='0';
END IF;
END IF;
END PROCESS;
PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTA_WR_RD_L1 <='0';
PORTA_WR_RD_L2 <='0';
ELSE
PORTA_WR_RD_L1 <= LATCH_PORTA_WR_RD_COMPLETE;
PORTA_WR_RD_L2 <= PORTA_WR_RD_L1;
END IF;
END IF;
END PROCESS;
PORTB_EN: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD <='0';
ELSE
PORTB_WR_RD <= PORTA_WR_RD_L2;
END IF;
END IF;
END PROCESS;
PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
PORTB_WR_RD_R1 <='0';
PORTB_WR_RD_R2 <='0';
ELSE
PORTB_WR_RD_R1 <=PORTB_WR_RD;
PORTB_WR_RD_R2 <=PORTB_WR_RD_R1;
END IF;
END IF;
END PROCESS;
---double registered of porta complete on portb clk
PORTB_WR_RD_HAPPENED <= PORTB_WR_RD_R2;
PORTA_WR_RD_COMPLETE <= '1' when count=(WRITE_CNT_A+READ_CNT_A) else '0';
start_counter: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
incr_cnt <= '0';
elsif(porta_wr_rd ='1') then
incr_cnt <='1';
elsif(porta_wr_rd_complete='1') then
incr_cnt <='0';
end if;
end if;
end process;
COUNTER: process(clka)
begin
if(rising_edge(clka)) then
if(TB_RST='1') then
count <= 0;
elsif(incr_cnt='1') then
count<=count+1;
end if;
if(count=(WRITE_CNT_A+READ_CNT_A)) then
count<=0;
end if;
end if;
end process;
DO_WRITE_A<='1' when (count <WRITE_CNT_A and incr_cnt='1') else '0';
DO_READ_A <='1' when (count >WRITE_CNT_A and incr_cnt='1') else '0';
PORTB_WR_RD_COMPLETE <= '1' when count_b=(WRITE_CNT_B+READ_CNT_B) else '0';
startb_counter: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
incr_cnt_b <= '0';
elsif(portb_wr_rd ='1') then
incr_cnt_b <='1';
elsif(portb_wr_rd_complete='1') then
incr_cnt_b <='0';
end if;
end if;
end process;
COUNTER_B: process(clkb)
begin
if(rising_edge(clkb)) then
if(TB_RST='1') then
count_b <= 0;
elsif(incr_cnt_b='1') then
count_b<=count_b+1;
end if;
if(count_b=WRITE_CNT_B+READ_CNT_B) then
count_b<=0;
end if;
end if;
end process;
DO_WRITE_B<='1' when (count_b <WRITE_CNT_B and incr_cnt_b='1') else '0';
DO_READ_B <='1' when (count_b >WRITE_CNT_B and incr_cnt_b='1') else '0';
BEGIN_SHIFT_REG_A: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(0),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_A
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_A(I),
CLK =>CLKA,
RST=>TB_RST,
D =>DO_READ_REG_A(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_A;
BEGIN_SHIFT_REG_B: FOR I IN 0 TO 4 GENERATE
BEGIN
DFF_RIGHT: IF I=0 GENERATE
BEGIN
SHIFT_INST_0: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(0),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_B
);
END GENERATE DFF_RIGHT;
DFF_OTHERS: IF ((I>0) AND (I<=4)) GENERATE
BEGIN
SHIFT_INST: ENTITY work.REGISTER_LOGIC_TDP
PORT MAP(
Q => DO_READ_REG_B(I),
CLK =>CLKB,
RST=>TB_RST,
D =>DO_READ_REG_B(I-1)
);
END GENERATE DFF_OTHERS;
END GENERATE BEGIN_SHIFT_REG_B;
REGCEA_PROCESS: PROCESS(CLKA)
BEGIN
IF(RISING_EDGE(CLKA)) THEN
IF(TB_RST='1') THEN
DO_READ_RA <= '0';
ELSE
DO_READ_RA <= DO_READ_A;
END IF;
END IF;
END PROCESS;
REGCEB_PROCESS: PROCESS(CLKB)
BEGIN
IF(RISING_EDGE(CLKB)) THEN
IF(TB_RST='1') THEN
DO_READ_RB <= '0';
ELSE
DO_READ_RB <= DO_READ_B;
END IF;
END IF;
END PROCESS;
---REGCEB SHOULD BE SET AT THE CORE OUTPUT REGISTER/EMBEEDED OUTPUT REGISTER
--- WHEN CORE OUTPUT REGISTER IS SET REGCE SHOUD BE SET TO '1' WHEN THE READ DATA IS AVAILABLE AT THE CORE OUTPUT REGISTER
--WHEN CORE OUTPUT REGISTER IS '0' AND OUTPUT_PRIMITIVE_REG ='1', REGCE SHOULD BE SET WHEN THE DATA IS AVAILABLE AT THE PRIMITIVE OUTPUT REGISTER.
-- HERE, TO GENERAILIZE REGCE IS ASSERTED
ENA <= DO_READ_A OR DO_WRITE_A ;
ENB <= DO_READ_B OR DO_WRITE_B ;
WEA <= IF_THEN_ELSE(DO_WRITE_A='1', WEA_VCC,WEA_GND) ;
WEB <= IF_THEN_ELSE(DO_WRITE_B='1', WEB_VCC,WEB_GND) ;
END ARCHITECTURE;
|
-- VHDL de um contador de modulo 16
-- OBS: Para esse experimento so eh utilizada a contagem ate 11
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity contador is
port(clock : in std_logic;
zera : in std_logic;
conta : in std_logic;
contagem : out std_logic_vector(3 downto 0);
fim : out std_logic);
end contador;
architecture exemplo of contador is
signal IQ: unsigned(3 downto 0);
begin
process (clock, conta, IQ, zera)
begin
if clock'event and clock = '1' then
if zera = '1' then
IQ <= (others => '0');
elsif conta = '1' then
IQ <= IQ + 1;
end if;
end if;
if IQ = 11 then
fim <= '1';
else
fim <= '0';
end if;
contagem <= std_logic_vector(IQ);
end process;
end exemplo;
|
-- Pushbutton Debounce Module
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.all;
USE ieee.STD_LOGIC_UNSIGNED.all;
ENTITY Debo IS
PORT (
clk: IN STD_LOGIC; ---make it a low frequency Clock input
key: IN STD_LOGIC; -- active low input
pulse: OUT STD_LOGIC);
END Debo;
ARCHITECTURE onepulse OF Debo IS
SIGNAL cnt: STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
PROCESS (clk,key)
BEGIN
IF (key = '1') THEN
cnt <= "00";
ELSIF (clk'EVENT AND clk= '1') THEN
IF (cnt /= "11") THEN cnt <= cnt + 1; END IF;
END IF;
IF (cnt = "10") AND (key = '0') THEN
pulse <= '1';
ELSE pulse <= '0';
END IF;
END PROCESS; --You must BEGIN and END a PROCESS in VHDL.
END onepulse;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc78.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p10n04i00078ent IS
END c04s03b01x02p10n04i00078ent;
ARCHITECTURE c04s03b01x02p10n04i00078arch OF c04s03b01x02p10n04i00078ent IS
type int_array is array(1 to 1) of integer;
signal s : int_array := (others => 0);
BEGIN
s <= (others => 1);
s <= (others => 2);
TEST: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b01x02p10n04i00078 - Signal has multiple sources but is not a resolved signal."
severity ERROR;
wait;
END PROCESS TEST;
END c04s03b01x02p10n04i00078arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc78.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p10n04i00078ent IS
END c04s03b01x02p10n04i00078ent;
ARCHITECTURE c04s03b01x02p10n04i00078arch OF c04s03b01x02p10n04i00078ent IS
type int_array is array(1 to 1) of integer;
signal s : int_array := (others => 0);
BEGIN
s <= (others => 1);
s <= (others => 2);
TEST: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b01x02p10n04i00078 - Signal has multiple sources but is not a resolved signal."
severity ERROR;
wait;
END PROCESS TEST;
END c04s03b01x02p10n04i00078arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc78.vhd,v 1.2 2001-10-26 16:30:30 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b01x02p10n04i00078ent IS
END c04s03b01x02p10n04i00078ent;
ARCHITECTURE c04s03b01x02p10n04i00078arch OF c04s03b01x02p10n04i00078ent IS
type int_array is array(1 to 1) of integer;
signal s : int_array := (others => 0);
BEGIN
s <= (others => 1);
s <= (others => 2);
TEST: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST:c04s03b01x02p10n04i00078 - Signal has multiple sources but is not a resolved signal."
severity ERROR;
wait;
END PROCESS TEST;
END c04s03b01x02p10n04i00078arch;
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00604
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 11.1 (1)
--
-- DESIGN UNIT ORDERING:
--
-- N/A
--
-- REVISION HISTORY:
--
-- 24-AUG-1987 - initial revision
--
-- NOTES:
--
-- will be used in conjunction with test ct00607
--
--
package body PKG00603 is
procedure Proc is
begin
Null ;
end Proc ;
end PKG00603 ;
--
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO is
generic(
WIDTH : integer := 16;
DEPTH : integer := 4
);
port(
RB : in vl_logic;
CLR : in vl_logic;
CLK : in vl_logic;
WR : in vl_logic;
RD : in vl_logic;
D : in vl_logic_vector;
Q : out vl_logic_vector;
STORE : out vl_logic_vector;
WR_PTR : out vl_logic_vector;
RD_PTR : out vl_logic_vector;
EMPTY : out vl_logic;
FULL : out vl_logic;
AFULL : out vl_logic
);
end F2DSS_ACE_PPE_FIFO;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO is
generic(
WIDTH : integer := 16;
DEPTH : integer := 4
);
port(
RB : in vl_logic;
CLR : in vl_logic;
CLK : in vl_logic;
WR : in vl_logic;
RD : in vl_logic;
D : in vl_logic_vector;
Q : out vl_logic_vector;
STORE : out vl_logic_vector;
WR_PTR : out vl_logic_vector;
RD_PTR : out vl_logic_vector;
EMPTY : out vl_logic;
FULL : out vl_logic;
AFULL : out vl_logic
);
end F2DSS_ACE_PPE_FIFO;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_PPE_FIFO is
generic(
WIDTH : integer := 16;
DEPTH : integer := 4
);
port(
RB : in vl_logic;
CLR : in vl_logic;
CLK : in vl_logic;
WR : in vl_logic;
RD : in vl_logic;
D : in vl_logic_vector;
Q : out vl_logic_vector;
STORE : out vl_logic_vector;
WR_PTR : out vl_logic_vector;
RD_PTR : out vl_logic_vector;
EMPTY : out vl_logic;
FULL : out vl_logic;
AFULL : out vl_logic
);
end F2DSS_ACE_PPE_FIFO;
|
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Enumerations and components declarations --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package pack_mips is
-- Type signal on n bits
subtype bus64 is std_logic_vector(63 downto 0);
subtype bus33 is std_logic_vector(32 downto 0);
subtype bus32 is std_logic_vector(31 downto 0);
subtype bus31 is std_logic_vector(30 downto 0);
subtype bus26 is std_logic_vector(25 downto 0);
subtype bus24 is std_logic_vector(23 downto 0);
subtype bus16 is std_logic_vector(15 downto 0);
subtype bus8 is std_logic_vector(7 downto 0);
subtype bus6 is std_logic_vector(5 downto 0);
subtype bus5 is std_logic_vector(4 downto 0);
subtype bus4 is std_logic_vector(3 downto 0);
subtype bus2 is std_logic_vector(1 downto 0);
subtype bus1 is std_logic;
-- Address of a register type
subtype adr_reg_type is std_logic_vector(5 downto 0);
-- Coding of the level of data availability for UR
subtype level_type is std_logic_vector(1 downto 0);
constant LVL_DI : level_type := "11"; -- Data available from the op2 of DI stage
constant LVL_EX : level_type := "10"; -- Data available from the data_ual register of EX stage
constant LVL_MEM : level_type := "01"; -- Data available from the data_ecr register of MEM stage
constant LVL_REG : level_type := "00"; -- Data available only in the register bank
-- Different values of cause exceptions
constant IT_NOEXC : bus32 := X"00000000";
constant IT_ITMAT : bus32 := X"00000001";
constant IT_OVERF : bus32 := X"00000002";
constant IT_ERINS : bus32 := X"00000004";
constant IT_BREAK : bus32 := X"00000008";
constant IT_SCALL : bus32 := X"00000010";
-- Operation type of the coprocessor system (only the low 16 bits are valid)
constant SYS_NOP : bus32 := X"0000_0000";
constant SYS_MASK : bus32 := X"0000_0001";
constant SYS_UNMASK : bus32 := X"0000_0002";
constant SYS_ITRET : bus32 := X"0000_0004";
-- Type for the alu control
subtype alu_ctrl_type is std_logic_vector(27 downto 0);
-- Arithmetical operations
constant OP_ADD : alu_ctrl_type := "1000000000000000000000000000"; -- op1 + op2 sign
constant OP_ADDU : alu_ctrl_type := "0100000000000000000000000000"; -- op1 + op2 non sign
constant OP_SUB : alu_ctrl_type := "0010000000000000000000000000"; -- op1 - op2 sign
constant OP_SUBU : alu_ctrl_type := "0001000000000000000000000000"; -- op1 - op2 non signe
-- Logical operations
constant OP_AND : alu_ctrl_type := "0000100000000000000000000000"; -- et logique
constant OP_OR : alu_ctrl_type := "0000010000000000000000000000"; -- ou logique
constant OP_XOR : alu_ctrl_type := "0000001000000000000000000000"; -- ou exclusif logique
constant OP_NOR : alu_ctrl_type := "0000000100000000000000000000"; -- non ou logique
-- Tests : result to one if ok
constant OP_SLT : alu_ctrl_type := "0000000010000000000000000000"; -- op1 < op2 (sign)
constant OP_SLTU : alu_ctrl_type := "0000000001000000000000000000"; -- op1 < op2 (non sign)
constant OP_EQU : alu_ctrl_type := "0000000000100000000000000000"; -- op1 = op2
constant OP_NEQU : alu_ctrl_type := "0000000000010000000000000000"; -- op1 /= op2
constant OP_SNEG : alu_ctrl_type := "0000000000001000000000000000"; -- op1 < 0
constant OP_SPOS : alu_ctrl_type := "0000000000000100000000000000"; -- op1 > 0
constant OP_LNEG : alu_ctrl_type := "0000000000000010000000000000"; -- op1 <= 0
constant OP_LPOS : alu_ctrl_type := "0000000000000001000000000000"; -- op1 >= 0
-- Multiplications
constant OP_MULT : alu_ctrl_type := "0000000000000000100000000000"; -- op1 * op2 sign (chargement des poids faibles)
constant OP_MULTU : alu_ctrl_type := "0000000000000000010000000000"; -- op1 * op2 non sign (chargement des poids faibles)
-- Shifts
constant OP_SLL : alu_ctrl_type := "0000000000000000001000000000"; -- decallage logique a gauche
constant OP_SRL : alu_ctrl_type := "0000000000000000000100000000"; -- decallage logique a droite
constant OP_SRA : alu_ctrl_type := "0000000000000000000010000000"; -- decallage arithmetique a droite
constant OP_LUI : alu_ctrl_type := "0000000000000000000001000000"; -- met en poids fort la valeur immediate
-- Access to internal registers
constant OP_MFHI : alu_ctrl_type := "0000000000000000000000100000"; -- lecture des poids forts
constant OP_MFLO : alu_ctrl_type := "0000000000000000000000010000"; -- lecture des poids faibles
constant OP_MTHI : alu_ctrl_type := "0000000000000000000000001000"; -- ecriture des poids forts
constant OP_MTLO : alu_ctrl_type := "0000000000000000000000000100"; -- ecriture des poids faibles
-- Operations which do nothing but are useful
constant OP_OUI : alu_ctrl_type := "0000000000000000000000000010"; -- met a 1 le bit de poids faible en sortie
constant OP_OP2 : alu_ctrl_type := "0000000000000000000000000001"; -- recopie l'operande 2 en sortie
-- Starting boot address (after reset)
constant ADR_INIT : bus32 := X"00000000";
constant INS_NOP : bus32 := X"00000000";
-- Internal component of the pipeline stage
component alu
port (
clock : in bus1;
reset : in bus1;
op1 : in bus32;
op2 : in bus32;
ctrl : in alu_ctrl_type;
res : out bus32;
overflow : out bus1
);
end component;
-- Pipeline stage components
component pps_pf
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
bra_cmd : in bus1;
bra_cmd_pr : in bus1;
bra_adr : in bus32;
exch_cmd : in bus1;
exch_adr : in bus32;
stop_pf : in bus1;
PF_pc : out bus32
);
end component;
component pps_ei
port (
clock : in bus1;
reset : in bus1;
clear : in bus1;
stop_all : in bus1;
stop_ei : in bus1;
CTE_instr : in bus32;
ETC_adr : out bus32;
PF_pc : in bus32;
EI_instr : out bus32;
EI_adr : out bus32;
EI_it_ok : out bus1
);
end component;
component pps_di
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
adr_reg1 : out adr_reg_type;
adr_reg2 : out adr_reg_type;
use1 : out bus1;
use2 : out bus1;
stop_di : in bus1;
data1 : in bus32;
data2 : in bus32;
EI_adr : in bus32;
EI_instr : in bus32;
EI_it_ok : in bus1;
DI_bra : out bus1;
DI_link : out bus1;
DI_op1 : out bus32;
DI_op2 : out bus32;
DI_code_ual : out alu_ctrl_type;
DI_offset : out bus32;
DI_adr_reg_dest : out adr_reg_type;
DI_ecr_reg : out bus1;
DI_mode : out bus1;
DI_op_mem : out bus1;
DI_r_w : out bus1;
DI_adr : out bus32;
DI_exc_cause : out bus32;
DI_level : out level_type;
DI_it_ok : out bus1
);
end component;
component pps_ex
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
DI_bra : in bus1;
DI_link : in bus1;
DI_op1 : in bus32;
DI_op2 : in bus32;
DI_code_ual : in alu_ctrl_type;
DI_offset : in bus32;
DI_adr_reg_dest : in adr_reg_type;
DI_ecr_reg : in bus1;
DI_mode : in bus1;
DI_op_mem : in bus1;
DI_r_w : in bus1;
DI_adr : in bus32;
DI_exc_cause : in bus32;
DI_level : in level_type;
DI_it_ok : in bus1;
EX_adr : out bus32;
EX_bra_confirm : out bus1;
EX_data_ual : out bus32;
EX_adresse : out bus32;
EX_adr_reg_dest : out adr_reg_type;
EX_ecr_reg : out bus1;
EX_op_mem : out bus1;
EX_r_w : out bus1;
EX_exc_cause : out bus32;
EX_level : out level_type;
EX_it_ok : out bus1
);
end component;
component pps_mem
port (
clock : in bus1;
reset : in bus1;
stop_all : in bus1;
clear : in bus1;
MTC_data : out bus32;
MTC_adr : out bus32;
MTC_r_w : out bus1;
MTC_req : out bus1;
CTM_data : in bus32;
EX_adr : in bus32;
EX_data_ual : in bus32;
EX_adresse : in bus32;
EX_adr_reg_dest : in adr_reg_type;
EX_ecr_reg : in bus1;
EX_op_mem : in bus1;
EX_r_w : in bus1;
EX_exc_cause : in bus32;
EX_level : in level_type;
EX_it_ok : in bus1;
MEM_adr : out bus32;
MEM_adr_reg_dest : out adr_reg_type;
MEM_ecr_reg : out bus1;
MEM_data_ecr : out bus32;
MEM_exc_cause : out bus32;
MEM_level : out level_type;
MEM_it_ok : out bus1
);
end component;
component renvoi
port (
adr1 : in adr_reg_type;
adr2 : in adr_reg_type;
use1 : in bus1;
use2 : in bus1;
data1 : out bus32;
data2 : out bus32;
alea : out bus1;
DI_level : in level_type;
DI_adr : in adr_reg_type;
DI_ecr : in bus1;
DI_data : in bus32;
EX_level : in level_type;
EX_adr : in adr_reg_type;
EX_ecr : in bus1;
EX_data : in bus32;
MEM_level : in level_type;
MEM_adr : in adr_reg_type;
MEM_ecr : in bus1;
MEM_data : in bus32;
interrupt : in bus1;
write_data : out bus32;
write_adr : out bus5;
write_GPR : out bus1;
write_SCP : out bus1;
read_adr1 : out bus5;
read_adr2 : out bus5;
read_data1_GPR : in bus32;
read_data1_SCP : in bus32;
read_data2_GPR : in bus32;
read_data2_SCP : in bus32
);
end component;
component banc
port (
clock : in bus1;
reset : bus1;
reg_src1 : in bus5;
reg_src2 : in bus5;
reg_dest : in bus5;
donnee : in bus32;
cmd_ecr : in bus1;
data_src1 : out bus32;
data_src2 : out bus32
);
end component;
component bus_ctrl
port
(
clock : bus1;
reset : bus1;
interrupt : in std_logic;
adr_from_ei : in bus32;
instr_to_ei : out bus32;
req_from_mem : in bus1;
r_w_from_mem : in bus1;
adr_from_mem : in bus32;
data_from_mem : in bus32;
data_to_mem : out bus32;
req_to_ram : out std_logic;
adr_to_ram : out bus32;
r_w_to_ram : out bus1;
ack_from_ram : in bus1;
data_inout_ram : inout bus32;
stop_all : out bus1
);
end component;
component syscop
port
(
clock : in bus1;
reset : in bus1;
MEM_adr : in bus32;
MEM_exc_cause : in bus32;
MEM_it_ok : in bus1;
it_mat : in bus1;
interrupt : out bus1;
vecteur_it : out bus32;
write_data : in bus32;
write_adr : in bus5;
write_SCP : in bus1;
read_adr1 : in bus5;
read_adr2 : in bus5;
read_data1 : out bus32;
read_data2 : out bus32
);
end component;
component predict
generic (
nb_record : integer := 3
);
port (
clock : in std_logic;
reset : in std_logic;
PF_pc : in std_logic_vector(31 downto 0);
DI_bra : in std_logic;
DI_adr : in std_logic_vector(31 downto 0);
EX_bra_confirm : in std_logic;
EX_adr : in std_logic_vector(31 downto 0);
EX_adresse : in std_logic_vector(31 downto 0);
EX_uncleared : in std_logic;
PR_bra_cmd : out std_logic;
PR_bra_bad : out std_logic;
PR_bra_adr : out std_logic_vector(31 downto 0);
PR_clear : out std_logic
);
end component;
component minimips
port (
clock : in bus1;
reset : in bus1;
ram_req : out bus1;
ram_adr : out bus32;
ram_r_w : out bus1;
ram_data : inout bus32;
ram_ack : in bus1;
it_mat : in bus1
);
end component;
end pack_mips;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sram16
-- File: sram16.vhd
-- Author: Jiri Gaisler Gaisler Research
-- Description: Simulation model of generic 16-bit async SRAM
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library gaisler;
use gaisler.sim.all;
library grlib;
use grlib.stdlib.all;
entity sram16 is
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end;
architecture sim of sram16 is
signal cex : std_logic_vector(0 to 1);
begin
cex(0) <= ce or lb; cex(1) <= ce or ub;
sr0 : sram generic map (index+1, abits, tacc, fname)
port map (a, d(7 downto 0), cex(0), we, oe);
sr1 : sram generic map (index, abits, tacc, fname)
port map (a, d(15 downto 8), cex(1), we, oe);
end sim;
-- pragma translate_on
|
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_2i_core_ip is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
clk : in std_logic
);
end pfb_fir_2048ch_2i_core_ip;
-- Generated from Simulink block
library IEEE;
use IEEE.std_logic_1164.all;
library xil_defaultlib;
use xil_defaultlib.conv_pkg.all;
entity pfb_fir_2048ch_2i_core_ip_struct is
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
clk_1 : in std_logic;
ce_1 : in std_logic;
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 )
);
end pfb_fir_2048ch_2i_core_ip_struct;
architecture structural of pfb_fir_2048ch_2i_core_ip_struct is
component pfb_fir_2048ch_2i_core_ip
port (
pol0_in0 : in std_logic_vector( 8-1 downto 0 );
pol1_in0 : in std_logic_vector( 8-1 downto 0 );
sync : in std_logic_vector( 32-1 downto 0 );
pol0_in1 : in std_logic_vector( 8-1 downto 0 );
pol1_in1 : in std_logic_vector( 8-1 downto 0 );
pol0_out0 : out std_logic_vector( 18-1 downto 0 );
pol1_out0 : out std_logic_vector( 18-1 downto 0 );
sync_out : out std_logic_vector( 1-1 downto 0 );
pol0_out1 : out std_logic_vector( 18-1 downto 0 );
pol1_out1 : out std_logic_vector( 18-1 downto 0 );
clk : in std_logic
);
end component;
begin
pfb_fir_2048ch_2i_core_ip_inst : pfb_fir_2048ch_2i_core_ip
port map (
pol0_in0 => pol0_in0,
pol1_in0 => pol1_in0,
sync => sync,
pol0_in1 => pol0_in1,
pol1_in1 => pol1_in1,
clk => clk_1,
pol0_out0 => pol0_out0,
pol1_out0 => pol1_out0,
sync_out => sync_out,
pol0_out1 => pol0_out1,
pol1_out1 => pol1_out1
);
end structural;
|
architecture RTL of FIFO is
begin
process
begin
if a then
if b then
if c then
c <= d;
end if;
a <= b;
end if;
b <= c;
end if;
z <= a;
-- Violations below
if a then
if b then
if c then
c <= d;
end if;
a <= b;
end if;
b <= c;
end if;
z <= a;
end process;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Description: Generate analog 640x480 VGA, double-doublescanned from 19200 bytes of RAM
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity vga is
Port (
clk25 : in STD_LOGIC;
vga_red : out STD_LOGIC_VECTOR(3 downto 0);
vga_green : out STD_LOGIC_VECTOR(3 downto 0);
vga_blue : out STD_LOGIC_VECTOR(3 downto 0);
vga_hsync : out STD_LOGIC;
vga_vsync : out STD_LOGIC;
frame_addr : out STD_LOGIC_VECTOR(18 downto 0);
frame_pixel : in STD_LOGIC_VECTOR(11 downto 0)
);
end vga;
architecture Behavioral of vga is
-- Timing constants
constant hRez : natural := 640;
constant hStartSync : natural := 640+16;
constant hEndSync : natural := 640+16+96;
constant hMaxCount : natural := 800;
constant vRez : natural := 480;
constant vStartSync : natural := 480+10;
constant vEndSync : natural := 480+10+2;
constant vMaxCount : natural := 480+10+2+33;
constant hsync_active : std_logic := '0';
constant vsync_active : std_logic := '0';
signal hCounter : unsigned( 9 downto 0) := (others => '0');
signal vCounter : unsigned( 9 downto 0) := (others => '0');
signal address : unsigned(18 downto 0) := (others => '0');
signal blank : std_logic := '1';
begin
frame_addr <= std_logic_vector(address);
process(clk25)
begin
if rising_edge(clk25) then
-- Count the lines and rows
if hCounter = hMaxCount-1 then
hCounter <= (others => '0');
if vCounter = vMaxCount-1 then
vCounter <= (others => '0');
else
vCounter <= vCounter+1;
end if;
else
hCounter <= hCounter+1;
end if;
if blank = '0' then
vga_red <= frame_pixel(11 downto 8);
vga_green <= frame_pixel( 7 downto 4);
vga_blue <= frame_pixel( 3 downto 0);
else
vga_red <= (others => '0');
vga_green <= (others => '0');
vga_blue <= (others => '0');
end if;
if vCounter >= vRez then
address <= (others => '0');
blank <= '1';
else
if hCounter < 640 then
blank <= '0';
address <= address+1;
else
blank <= '1';
end if;
end if;
-- Are we in the hSync pulse? (one has been added to include frame_buffer_latency)
if hCounter > hStartSync and hCounter <= hEndSync then
vga_hSync <= hsync_active;
else
vga_hSync <= not hsync_active;
end if;
-- Are we in the vSync pulse?
if vCounter >= vStartSync and vCounter < vEndSync then
vga_vSync <= vsync_active;
else
vga_vSync <= not vsync_active;
end if;
end if;
end process;
end Behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2632.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02632ent IS
END c13s03b01x00p02n01i02632ent;
ARCHITECTURE c13s03b01x00p02n01i02632arch OF c13s03b01x00p02n01i02632ent IS
BEGIN
TESTING: PROCESS
variable k,k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02632 - Identifier can not contain ','."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02632arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2632.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02632ent IS
END c13s03b01x00p02n01i02632ent;
ARCHITECTURE c13s03b01x00p02n01i02632arch OF c13s03b01x00p02n01i02632ent IS
BEGIN
TESTING: PROCESS
variable k,k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02632 - Identifier can not contain ','."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02632arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2632.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s03b01x00p02n01i02632ent IS
END c13s03b01x00p02n01i02632ent;
ARCHITECTURE c13s03b01x00p02n01i02632arch OF c13s03b01x00p02n01i02632ent IS
BEGIN
TESTING: PROCESS
variable k,k : integer := 0;
BEGIN
assert FALSE
report "***FAILED TEST: c13s03b01x00p02n01i02632 - Identifier can not contain ','."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s03b01x00p02n01i02632arch;
|
---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
component SHKA65_4096X32X1CM4
port(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11 : in std_logic;
DO0,DO1,DO2,
DO3,DO4,DO5,DO6,DO7,DO8,DO9,DO10,DO11,DO12,
DO13,DO14,DO15,DO16,DO17,DO18,DO19,DO20,
DO21,DO22,DO23,DO24,DO25,DO26,DO27,DO28,
DO29,DO30,DO31 : out std_logic;
DI0,DI1,DI2,DI3,DI4,DI5,
DI6,DI7,DI8,DI9,DI10,DI11,DI12,DI13,DI14,
DI15,DI16,DI17,DI18,DI19,DI20,DI21,DI22,
DI23,DI24,DI25,DI26,DI27,DI28,DI29,DI30,
DI31,CK,WEB,DVSE,DVS0,DVS1,DVS2,CSB: in std_logic);
end component;
signal write_enable: std_logic;
signal not_clock: std_logic;
signal Mem_clk : std_logic;
signal Mem_reset : std_logic;
signal Mem_enable : std_logic;
signal Mem_write_byte_enable : std_logic_vector(3 downto 0);
signal Mem_address : std_logic_vector(31 downto 2);
signal Mem_data_write : std_logic_vector(31 downto 0);
signal Mem_data_read : std_logic_vector(31 downto 0);
begin
write_enable <= not(Mem_write_byte_enable(0) or Mem_write_byte_enable(1) or Mem_write_byte_enable(2) or Mem_write_byte_enable(3));
not_clock <= not Mem_clk;
process(IJTAG_select, clk, reset, enable, write_byte_enable, address,
data_write, Mem_data_read, IJTAG_clk, IJTAG_reset, IJTAG_enable,
IJTAG_write_byte_enable, IJTAG_address, IJTAG_data_write)
begin
case( IJTAG_select) is
when '0' =>
Mem_clk <= clk;
Mem_reset <= reset;
Mem_enable <= enable;
Mem_write_byte_enable <= write_byte_enable;
Mem_address <= address;
Mem_data_write <= data_write;
data_read <= Mem_data_read;
IJTAG_data_read <= (others =>'0');
when others =>
Mem_clk <= IJTAG_clk;
Mem_reset <= IJTAG_reset;
Mem_enable <= IJTAG_enable;
Mem_write_byte_enable <= IJTAG_write_byte_enable;
Mem_address <= IJTAG_address;
Mem_data_write <= IJTAG_data_write;
IJTAG_data_read <= Mem_data_read;
data_read <= (others =>'0');
end case;
end process;
RAM_unit: SHKA65_4096X32X1CM4
generic map (cdeFileInit => stim_file)
port map(
A0 => Mem_address(2),
A1 => Mem_address(3),
A2 => Mem_address(4),
A3 => Mem_address(5),
A4 => Mem_address(6),
A5 => Mem_address(7),
A6 => Mem_address(8),
A7 => Mem_address(9),
A8 => Mem_address(10),
A9 => Mem_address(11),
A10 => Mem_address(12),
A11 => Mem_address(13),
DO0 => Mem_data_read(0),
DO1 => Mem_data_read(1),
DO2 => Mem_data_read(2),
DO3 => Mem_data_read(3),
DO4 => Mem_data_read(4),
DO5 => Mem_data_read(5),
DO6 => Mem_data_read(6),
DO7 => Mem_data_read(7),
DO8 => Mem_data_read(8),
DO9 => Mem_data_read(9),
DO10 => Mem_data_read(10),
DO11 => Mem_data_read(11),
DO12 => Mem_data_read(12),
DO13 => Mem_data_read(13),
DO14 => Mem_data_read(14),
DO15 => Mem_data_read(15),
DO16 => Mem_data_read(16),
DO17 => Mem_data_read(17),
DO18 => Mem_data_read(18),
DO19 => Mem_data_read(19),
DO20 => Mem_data_read(20),
DO21 => Mem_data_read(21),
DO22 => Mem_data_read(22),
DO23 => Mem_data_read(23),
DO24 => Mem_data_read(24),
DO25 => Mem_data_read(25),
DO26 => Mem_data_read(26),
DO27 => Mem_data_read(27),
DO28 => Mem_data_read(28),
DO29 => Mem_data_read(29),
DO30 => Mem_data_read(30),
DO31 => Mem_data_read(31),
DI0 => Mem_data_write(0),
DI1 => Mem_data_write(1),
DI2 => Mem_data_write(2),
DI3 => Mem_data_write(3),
DI4 => Mem_data_write(4),
DI5 => Mem_data_write(5),
DI6 => Mem_data_write(6),
DI7 => Mem_data_write(7),
DI8 => Mem_data_write(8),
DI9 => Mem_data_write(9),
DI10 => Mem_data_write(10),
DI11 => Mem_data_write(11),
DI12 => Mem_data_write(12),
DI13 => Mem_data_write(13),
DI14 => Mem_data_write(14),
DI15 => Mem_data_write(15),
DI16 => Mem_data_write(16),
DI17 => Mem_data_write(17),
DI18 => Mem_data_write(18),
DI19 => Mem_data_write(19),
DI20 => Mem_data_write(20),
DI21 => Mem_data_write(21),
DI22 => Mem_data_write(22),
DI23 => Mem_data_write(23),
DI24 => Mem_data_write(24),
DI25 => Mem_data_write(25),
DI26 => Mem_data_write(26),
DI27 => Mem_data_write(27),
DI28 => Mem_data_write(28),
DI29 => Mem_data_write(29),
DI30 => Mem_data_write(30),
DI31 => Mem_data_write(31),
CK => Mem_clk,
WEB => write_enable,
DVSE => '0',
DVS0 => '0',
DVS1 => '0',
DVS2 => '0',
CSB => '0'
);
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
component SHKA65_4096X32X1CM4
port(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11 : in std_logic;
DO0,DO1,DO2,
DO3,DO4,DO5,DO6,DO7,DO8,DO9,DO10,DO11,DO12,
DO13,DO14,DO15,DO16,DO17,DO18,DO19,DO20,
DO21,DO22,DO23,DO24,DO25,DO26,DO27,DO28,
DO29,DO30,DO31 : out std_logic;
DI0,DI1,DI2,DI3,DI4,DI5,
DI6,DI7,DI8,DI9,DI10,DI11,DI12,DI13,DI14,
DI15,DI16,DI17,DI18,DI19,DI20,DI21,DI22,
DI23,DI24,DI25,DI26,DI27,DI28,DI29,DI30,
DI31,CK,WEB,DVSE,DVS0,DVS1,DVS2,CSB: in std_logic);
end component;
signal write_enable: std_logic;
signal not_clock: std_logic;
signal Mem_clk : std_logic;
signal Mem_reset : std_logic;
signal Mem_enable : std_logic;
signal Mem_write_byte_enable : std_logic_vector(3 downto 0);
signal Mem_address : std_logic_vector(31 downto 2);
signal Mem_data_write : std_logic_vector(31 downto 0);
signal Mem_data_read : std_logic_vector(31 downto 0);
begin
write_enable <= not(Mem_write_byte_enable(0) or Mem_write_byte_enable(1) or Mem_write_byte_enable(2) or Mem_write_byte_enable(3));
not_clock <= not Mem_clk;
process(IJTAG_select, clk, reset, enable, write_byte_enable, address,
data_write, Mem_data_read, IJTAG_clk, IJTAG_reset, IJTAG_enable,
IJTAG_write_byte_enable, IJTAG_address, IJTAG_data_write)
begin
case( IJTAG_select) is
when '0' =>
Mem_clk <= clk;
Mem_reset <= reset;
Mem_enable <= enable;
Mem_write_byte_enable <= write_byte_enable;
Mem_address <= address;
Mem_data_write <= data_write;
data_read <= Mem_data_read;
IJTAG_data_read <= (others =>'0');
when others =>
Mem_clk <= IJTAG_clk;
Mem_reset <= IJTAG_reset;
Mem_enable <= IJTAG_enable;
Mem_write_byte_enable <= IJTAG_write_byte_enable;
Mem_address <= IJTAG_address;
Mem_data_write <= IJTAG_data_write;
IJTAG_data_read <= Mem_data_read;
data_read <= (others =>'0');
end case;
end process;
RAM_unit: SHKA65_4096X32X1CM4
generic map (cdeFileInit => stim_file)
port map(
A0 => Mem_address(2),
A1 => Mem_address(3),
A2 => Mem_address(4),
A3 => Mem_address(5),
A4 => Mem_address(6),
A5 => Mem_address(7),
A6 => Mem_address(8),
A7 => Mem_address(9),
A8 => Mem_address(10),
A9 => Mem_address(11),
A10 => Mem_address(12),
A11 => Mem_address(13),
DO0 => Mem_data_read(0),
DO1 => Mem_data_read(1),
DO2 => Mem_data_read(2),
DO3 => Mem_data_read(3),
DO4 => Mem_data_read(4),
DO5 => Mem_data_read(5),
DO6 => Mem_data_read(6),
DO7 => Mem_data_read(7),
DO8 => Mem_data_read(8),
DO9 => Mem_data_read(9),
DO10 => Mem_data_read(10),
DO11 => Mem_data_read(11),
DO12 => Mem_data_read(12),
DO13 => Mem_data_read(13),
DO14 => Mem_data_read(14),
DO15 => Mem_data_read(15),
DO16 => Mem_data_read(16),
DO17 => Mem_data_read(17),
DO18 => Mem_data_read(18),
DO19 => Mem_data_read(19),
DO20 => Mem_data_read(20),
DO21 => Mem_data_read(21),
DO22 => Mem_data_read(22),
DO23 => Mem_data_read(23),
DO24 => Mem_data_read(24),
DO25 => Mem_data_read(25),
DO26 => Mem_data_read(26),
DO27 => Mem_data_read(27),
DO28 => Mem_data_read(28),
DO29 => Mem_data_read(29),
DO30 => Mem_data_read(30),
DO31 => Mem_data_read(31),
DI0 => Mem_data_write(0),
DI1 => Mem_data_write(1),
DI2 => Mem_data_write(2),
DI3 => Mem_data_write(3),
DI4 => Mem_data_write(4),
DI5 => Mem_data_write(5),
DI6 => Mem_data_write(6),
DI7 => Mem_data_write(7),
DI8 => Mem_data_write(8),
DI9 => Mem_data_write(9),
DI10 => Mem_data_write(10),
DI11 => Mem_data_write(11),
DI12 => Mem_data_write(12),
DI13 => Mem_data_write(13),
DI14 => Mem_data_write(14),
DI15 => Mem_data_write(15),
DI16 => Mem_data_write(16),
DI17 => Mem_data_write(17),
DI18 => Mem_data_write(18),
DI19 => Mem_data_write(19),
DI20 => Mem_data_write(20),
DI21 => Mem_data_write(21),
DI22 => Mem_data_write(22),
DI23 => Mem_data_write(23),
DI24 => Mem_data_write(24),
DI25 => Mem_data_write(25),
DI26 => Mem_data_write(26),
DI27 => Mem_data_write(27),
DI28 => Mem_data_write(28),
DI29 => Mem_data_write(29),
DI30 => Mem_data_write(30),
DI31 => Mem_data_write(31),
CK => Mem_clk,
WEB => write_enable,
DVSE => '0',
DVS0 => '0',
DVS1 => '0',
DVS2 => '0',
CSB => '0'
);
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: RAM wrapper
-- AUTHOR: Siavoosh Payandeh Azad
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_misc.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use std.textio.all;
use work.mlite_pack.all;
entity ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
component SHKA65_4096X32X1CM4
port(A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11 : in std_logic;
DO0,DO1,DO2,
DO3,DO4,DO5,DO6,DO7,DO8,DO9,DO10,DO11,DO12,
DO13,DO14,DO15,DO16,DO17,DO18,DO19,DO20,
DO21,DO22,DO23,DO24,DO25,DO26,DO27,DO28,
DO29,DO30,DO31 : out std_logic;
DI0,DI1,DI2,DI3,DI4,DI5,
DI6,DI7,DI8,DI9,DI10,DI11,DI12,DI13,DI14,
DI15,DI16,DI17,DI18,DI19,DI20,DI21,DI22,
DI23,DI24,DI25,DI26,DI27,DI28,DI29,DI30,
DI31,CK,WEB,DVSE,DVS0,DVS1,DVS2,CSB: in std_logic);
end component;
signal write_enable: std_logic;
signal not_clock: std_logic;
signal Mem_clk : std_logic;
signal Mem_reset : std_logic;
signal Mem_enable : std_logic;
signal Mem_write_byte_enable : std_logic_vector(3 downto 0);
signal Mem_address : std_logic_vector(31 downto 2);
signal Mem_data_write : std_logic_vector(31 downto 0);
signal Mem_data_read : std_logic_vector(31 downto 0);
begin
write_enable <= not(Mem_write_byte_enable(0) or Mem_write_byte_enable(1) or Mem_write_byte_enable(2) or Mem_write_byte_enable(3));
not_clock <= not Mem_clk;
process(IJTAG_select, clk, reset, enable, write_byte_enable, address,
data_write, Mem_data_read, IJTAG_clk, IJTAG_reset, IJTAG_enable,
IJTAG_write_byte_enable, IJTAG_address, IJTAG_data_write)
begin
case( IJTAG_select) is
when '0' =>
Mem_clk <= clk;
Mem_reset <= reset;
Mem_enable <= enable;
Mem_write_byte_enable <= write_byte_enable;
Mem_address <= address;
Mem_data_write <= data_write;
data_read <= Mem_data_read;
IJTAG_data_read <= (others =>'0');
when others =>
Mem_clk <= IJTAG_clk;
Mem_reset <= IJTAG_reset;
Mem_enable <= IJTAG_enable;
Mem_write_byte_enable <= IJTAG_write_byte_enable;
Mem_address <= IJTAG_address;
Mem_data_write <= IJTAG_data_write;
IJTAG_data_read <= Mem_data_read;
data_read <= (others =>'0');
end case;
end process;
RAM_unit: SHKA65_4096X32X1CM4
generic map (cdeFileInit => stim_file)
port map(
A0 => Mem_address(2),
A1 => Mem_address(3),
A2 => Mem_address(4),
A3 => Mem_address(5),
A4 => Mem_address(6),
A5 => Mem_address(7),
A6 => Mem_address(8),
A7 => Mem_address(9),
A8 => Mem_address(10),
A9 => Mem_address(11),
A10 => Mem_address(12),
A11 => Mem_address(13),
DO0 => Mem_data_read(0),
DO1 => Mem_data_read(1),
DO2 => Mem_data_read(2),
DO3 => Mem_data_read(3),
DO4 => Mem_data_read(4),
DO5 => Mem_data_read(5),
DO6 => Mem_data_read(6),
DO7 => Mem_data_read(7),
DO8 => Mem_data_read(8),
DO9 => Mem_data_read(9),
DO10 => Mem_data_read(10),
DO11 => Mem_data_read(11),
DO12 => Mem_data_read(12),
DO13 => Mem_data_read(13),
DO14 => Mem_data_read(14),
DO15 => Mem_data_read(15),
DO16 => Mem_data_read(16),
DO17 => Mem_data_read(17),
DO18 => Mem_data_read(18),
DO19 => Mem_data_read(19),
DO20 => Mem_data_read(20),
DO21 => Mem_data_read(21),
DO22 => Mem_data_read(22),
DO23 => Mem_data_read(23),
DO24 => Mem_data_read(24),
DO25 => Mem_data_read(25),
DO26 => Mem_data_read(26),
DO27 => Mem_data_read(27),
DO28 => Mem_data_read(28),
DO29 => Mem_data_read(29),
DO30 => Mem_data_read(30),
DO31 => Mem_data_read(31),
DI0 => Mem_data_write(0),
DI1 => Mem_data_write(1),
DI2 => Mem_data_write(2),
DI3 => Mem_data_write(3),
DI4 => Mem_data_write(4),
DI5 => Mem_data_write(5),
DI6 => Mem_data_write(6),
DI7 => Mem_data_write(7),
DI8 => Mem_data_write(8),
DI9 => Mem_data_write(9),
DI10 => Mem_data_write(10),
DI11 => Mem_data_write(11),
DI12 => Mem_data_write(12),
DI13 => Mem_data_write(13),
DI14 => Mem_data_write(14),
DI15 => Mem_data_write(15),
DI16 => Mem_data_write(16),
DI17 => Mem_data_write(17),
DI18 => Mem_data_write(18),
DI19 => Mem_data_write(19),
DI20 => Mem_data_write(20),
DI21 => Mem_data_write(21),
DI22 => Mem_data_write(22),
DI23 => Mem_data_write(23),
DI24 => Mem_data_write(24),
DI25 => Mem_data_write(25),
DI26 => Mem_data_write(26),
DI27 => Mem_data_write(27),
DI28 => Mem_data_write(28),
DI29 => Mem_data_write(29),
DI30 => Mem_data_write(30),
DI31 => Mem_data_write(31),
CK => Mem_clk,
WEB => write_enable,
DVSE => '0',
DVS0 => '0',
DVS1 => '0',
DVS2 => '0',
CSB => '0'
);
end; --architecture logic
|
--
-- This file is part of top_chenillard
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity top_chenillard is
port(
clk : in std_logic;
w1a : inout std_logic_vector(15 downto 0);
w1b : inout std_logic_vector(15 downto 0);
w2c : inout std_logic_vector(15 downto 0);
rx : in std_logic;
tx : inout std_logic
);
end top_chenillard;
architecture Behavioral of top_chenillard is
component chenillard
port(
clk : in std_logic;
reset : in std_logic;
button : in std_logic;
led1 : out std_logic;
led2 : out std_logic;
led3 : out std_logic;
led4 : out std_logic
);
end component;
signal reset : std_logic;
signal pre_Q : std_logic_vector(23 downto 0);
signal clock_slow : std_logic;
begin
process(clk,reset)
begin
if reset = '1' then
pre_Q <= (others => '0');
elsif rising_edge(clk) then
pre_Q <= pre_Q + 1;
end if;
end process;
clock_slow <= pre_q(23);
chenillard_inst : chenillard
port map(
clk => clock_slow,
reset =>reset,
button => w1a(7),
led1 => w1a(6),
led2 => w1a(4),
led3 => w1a(2),
led4 => w1a(0)
);
reset <= '0';
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1045.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01045ent IS
END c06s04b00x00p03n01i01045ent;
ARCHITECTURE c06s04b00x00p03n01i01045arch OF c06s04b00x00p03n01i01045ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type ONE is range 1 to 1;
type A2 is array (ONE) of BOOLEAN;
variable V1: BOOLEAN;
BEGIN
V1 := A1'(others=>TRUE)(2);
-- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01045 - Prefix of an indexed name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01045arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1045.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01045ent IS
END c06s04b00x00p03n01i01045ent;
ARCHITECTURE c06s04b00x00p03n01i01045arch OF c06s04b00x00p03n01i01045ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type ONE is range 1 to 1;
type A2 is array (ONE) of BOOLEAN;
variable V1: BOOLEAN;
BEGIN
V1 := A1'(others=>TRUE)(2);
-- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01045 - Prefix of an indexed name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01045arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1045.vhd,v 1.2 2001-10-26 16:30:05 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c06s04b00x00p03n01i01045ent IS
END c06s04b00x00p03n01i01045ent;
ARCHITECTURE c06s04b00x00p03n01i01045arch OF c06s04b00x00p03n01i01045ent IS
BEGIN
TESTING: PROCESS
type THREE is range 1 to 3;
type A1 is array (THREE) of BOOLEAN;
type ONE is range 1 to 1;
type A2 is array (ONE) of BOOLEAN;
variable V1: BOOLEAN;
BEGIN
V1 := A1'(others=>TRUE)(2);
-- SYNTAX ERROR: PREFIX OF INDEXED NAME CANNOT BE AN AGGREGATE
assert FALSE
report "***FAILED TEST: c06s04b00x00p03n01i01045 - Prefix of an indexed name cannot be an aggregate."
severity ERROR;
wait;
END PROCESS TESTING;
END c06s04b00x00p03n01i01045arch;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity nfa_accept_samples_generic_hw is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_req_din : OUT STD_LOGIC;
sample_buffer_req_full_n : IN STD_LOGIC;
sample_buffer_req_write : OUT STD_LOGIC;
sample_buffer_rsp_empty_n : IN STD_LOGIC;
sample_buffer_rsp_read : OUT STD_LOGIC;
sample_buffer_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_buffer_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_length : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_size : IN STD_LOGIC_VECTOR (15 downto 0);
begin_index : IN STD_LOGIC_VECTOR (15 downto 0);
begin_sample : IN STD_LOGIC_VECTOR (15 downto 0);
end_index : IN STD_LOGIC_VECTOR (15 downto 0);
end_sample : IN STD_LOGIC_VECTOR (15 downto 0);
stop_on_first : IN STD_LOGIC_VECTOR (0 downto 0);
accept : IN STD_LOGIC_VECTOR (0 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end;
architecture behav of nfa_accept_samples_generic_hw is
attribute CORE_GENERATION_INFO : STRING;
attribute CORE_GENERATION_INFO of behav : architecture is
"nfa_accept_samples_generic_hw,hls_ip_2013_4,{HLS_INPUT_TYPE=c,HLS_INPUT_FLOAT=0,HLS_INPUT_FIXED=0,HLS_INPUT_PART=xc6slx9ftg256-3,HLS_INPUT_CLOCK=1.000000,HLS_INPUT_ARCH=others,HLS_SYN_CLOCK=3.000000,HLS_SYN_LAT=92264012,HLS_SYN_TPT=none,HLS_SYN_MEM=0,HLS_SYN_DSP=0,HLS_SYN_FF=0,HLS_SYN_LUT=0}";
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_st1_fsm_0 : STD_LOGIC_VECTOR (5 downto 0) := "000000";
constant ap_ST_st2_fsm_1 : STD_LOGIC_VECTOR (5 downto 0) := "000001";
constant ap_ST_st3_fsm_2 : STD_LOGIC_VECTOR (5 downto 0) := "000010";
constant ap_ST_st4_fsm_3 : STD_LOGIC_VECTOR (5 downto 0) := "000011";
constant ap_ST_st5_fsm_4 : STD_LOGIC_VECTOR (5 downto 0) := "000100";
constant ap_ST_st6_fsm_5 : STD_LOGIC_VECTOR (5 downto 0) := "000101";
constant ap_ST_st7_fsm_6 : STD_LOGIC_VECTOR (5 downto 0) := "000110";
constant ap_ST_st8_fsm_7 : STD_LOGIC_VECTOR (5 downto 0) := "000111";
constant ap_ST_st9_fsm_8 : STD_LOGIC_VECTOR (5 downto 0) := "001000";
constant ap_ST_st10_fsm_9 : STD_LOGIC_VECTOR (5 downto 0) := "001001";
constant ap_ST_st11_fsm_10 : STD_LOGIC_VECTOR (5 downto 0) := "001010";
constant ap_ST_st12_fsm_11 : STD_LOGIC_VECTOR (5 downto 0) := "001011";
constant ap_ST_st13_fsm_12 : STD_LOGIC_VECTOR (5 downto 0) := "001100";
constant ap_ST_st14_fsm_13 : STD_LOGIC_VECTOR (5 downto 0) := "001101";
constant ap_ST_st15_fsm_14 : STD_LOGIC_VECTOR (5 downto 0) := "001110";
constant ap_ST_st16_fsm_15 : STD_LOGIC_VECTOR (5 downto 0) := "001111";
constant ap_ST_st17_fsm_16 : STD_LOGIC_VECTOR (5 downto 0) := "010000";
constant ap_ST_st18_fsm_17 : STD_LOGIC_VECTOR (5 downto 0) := "010001";
constant ap_ST_st19_fsm_18 : STD_LOGIC_VECTOR (5 downto 0) := "010010";
constant ap_ST_st20_fsm_19 : STD_LOGIC_VECTOR (5 downto 0) := "010011";
constant ap_ST_st21_fsm_20 : STD_LOGIC_VECTOR (5 downto 0) := "010100";
constant ap_ST_st22_fsm_21 : STD_LOGIC_VECTOR (5 downto 0) := "010101";
constant ap_ST_st23_fsm_22 : STD_LOGIC_VECTOR (5 downto 0) := "010110";
constant ap_ST_st24_fsm_23 : STD_LOGIC_VECTOR (5 downto 0) := "010111";
constant ap_ST_st25_fsm_24 : STD_LOGIC_VECTOR (5 downto 0) := "011000";
constant ap_ST_st26_fsm_25 : STD_LOGIC_VECTOR (5 downto 0) := "011001";
constant ap_ST_st27_fsm_26 : STD_LOGIC_VECTOR (5 downto 0) := "011010";
constant ap_ST_st28_fsm_27 : STD_LOGIC_VECTOR (5 downto 0) := "011011";
constant ap_ST_st29_fsm_28 : STD_LOGIC_VECTOR (5 downto 0) := "011100";
constant ap_ST_st30_fsm_29 : STD_LOGIC_VECTOR (5 downto 0) := "011101";
constant ap_ST_st31_fsm_30 : STD_LOGIC_VECTOR (5 downto 0) := "011110";
constant ap_ST_st32_fsm_31 : STD_LOGIC_VECTOR (5 downto 0) := "011111";
constant ap_ST_st33_fsm_32 : STD_LOGIC_VECTOR (5 downto 0) := "100000";
constant ap_ST_st34_fsm_33 : STD_LOGIC_VECTOR (5 downto 0) := "100001";
constant ap_ST_st35_fsm_34 : STD_LOGIC_VECTOR (5 downto 0) := "100010";
constant ap_const_lv1_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (5 downto 0) := "000000";
signal stop_on_first_read_read_fu_102_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_fu_228_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_reg_313 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_fu_233_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_10_reg_318 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_fu_238_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_i_11_reg_323 : STD_LOGIC_VECTOR (0 downto 0);
signal c_load_reg_327 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_return : STD_LOGIC_VECTOR (31 downto 0);
signal offset_reg_333 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_return : STD_LOGIC_VECTOR (0 downto 0);
signal r_reg_338 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_done : STD_LOGIC;
signal or_cond_fu_245_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal or_cond_reg_343 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_249_p2 : STD_LOGIC_VECTOR (31 downto 0);
signal c_1_reg_347 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_start : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_ap_idle : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_ap_ready : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_nfa_symbols : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_req_din : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_req_full_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_req_write : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_rsp_empty_n : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_rsp_read : STD_LOGIC;
signal grp_nfa_accept_sample_fu_176_sample_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_nfa_accept_sample_fu_176_sample_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_empty : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_length_r : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_start : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_done : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_idle : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_ap_ready : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_ap_ce : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_get_offset_fu_192_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_get_offset_fu_192_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_sample_buffer_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_get_offset_fu_192_sample_length : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_start : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_done : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_idle : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_ap_ready : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_samples_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_datain : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_dataout : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_indices_samples_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_ap_ce : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_begin_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_datain : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_dataout : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_begin_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_req_din : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_req_full_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_req_write : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_rsp_read : STD_LOGIC;
signal grp_sample_iterator_next_fu_209_indices_stride_address : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_datain : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_dataout : STD_LOGIC_VECTOR (7 downto 0);
signal grp_sample_iterator_next_fu_209_indices_stride_size : STD_LOGIC_VECTOR (31 downto 0);
signal grp_sample_iterator_next_fu_209_i_index : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_i_sample : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_return_0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_sample_iterator_next_fu_209_ap_return_1 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_reg_144 : STD_LOGIC_VECTOR (15 downto 0);
signal i_sample_reg_154 : STD_LOGIC_VECTOR (15 downto 0);
signal p_0_reg_164 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg : STD_LOGIC := '0';
signal grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg : STD_LOGIC := '0';
signal ap_NS_fsm : STD_LOGIC_VECTOR (5 downto 0);
signal grp_sample_iterator_next_fu_209_ap_start_ap_start_reg : STD_LOGIC := '0';
signal c_fu_92 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_p0 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_p1 : STD_LOGIC_VECTOR (31 downto 0);
signal grp_fu_249_ce : STD_LOGIC;
component nfa_accept_sample IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
nfa_initials_buckets_req_din : OUT STD_LOGIC;
nfa_initials_buckets_req_full_n : IN STD_LOGIC;
nfa_initials_buckets_req_write : OUT STD_LOGIC;
nfa_initials_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_initials_buckets_rsp_read : OUT STD_LOGIC;
nfa_initials_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_initials_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_req_din : OUT STD_LOGIC;
nfa_finals_buckets_req_full_n : IN STD_LOGIC;
nfa_finals_buckets_req_write : OUT STD_LOGIC;
nfa_finals_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_finals_buckets_rsp_read : OUT STD_LOGIC;
nfa_finals_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_finals_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_req_din : OUT STD_LOGIC;
nfa_forward_buckets_req_full_n : IN STD_LOGIC;
nfa_forward_buckets_req_write : OUT STD_LOGIC;
nfa_forward_buckets_rsp_empty_n : IN STD_LOGIC;
nfa_forward_buckets_rsp_read : OUT STD_LOGIC;
nfa_forward_buckets_address : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_datain : IN STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_forward_buckets_size : OUT STD_LOGIC_VECTOR (31 downto 0);
nfa_symbols : IN STD_LOGIC_VECTOR (7 downto 0);
sample_req_din : OUT STD_LOGIC;
sample_req_full_n : IN STD_LOGIC;
sample_req_write : OUT STD_LOGIC;
sample_rsp_empty_n : IN STD_LOGIC;
sample_rsp_read : OUT STD_LOGIC;
sample_address : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_datain : IN STD_LOGIC_VECTOR (7 downto 0);
sample_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
sample_size : OUT STD_LOGIC_VECTOR (31 downto 0);
empty : IN STD_LOGIC_VECTOR (31 downto 0);
length_r : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (0 downto 0) );
end component;
component sample_iterator_get_offset IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
sample_buffer_size : IN STD_LOGIC_VECTOR (31 downto 0);
sample_length : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
component sample_iterator_next IS
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (31 downto 0);
din1 : IN STD_LOGIC_VECTOR (31 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (31 downto 0) );
end component;
begin
grp_nfa_accept_sample_fu_176 : component nfa_accept_sample
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_nfa_accept_sample_fu_176_ap_start,
ap_done => grp_nfa_accept_sample_fu_176_ap_done,
ap_idle => grp_nfa_accept_sample_fu_176_ap_idle,
ap_ready => grp_nfa_accept_sample_fu_176_ap_ready,
nfa_initials_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din,
nfa_initials_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n,
nfa_initials_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write,
nfa_initials_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n,
nfa_initials_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read,
nfa_initials_buckets_address => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address,
nfa_initials_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain,
nfa_initials_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout,
nfa_initials_buckets_size => grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size,
nfa_finals_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din,
nfa_finals_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n,
nfa_finals_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write,
nfa_finals_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n,
nfa_finals_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read,
nfa_finals_buckets_address => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address,
nfa_finals_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain,
nfa_finals_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout,
nfa_finals_buckets_size => grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size,
nfa_forward_buckets_req_din => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din,
nfa_forward_buckets_req_full_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n,
nfa_forward_buckets_req_write => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write,
nfa_forward_buckets_rsp_empty_n => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n,
nfa_forward_buckets_rsp_read => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read,
nfa_forward_buckets_address => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address,
nfa_forward_buckets_datain => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain,
nfa_forward_buckets_dataout => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout,
nfa_forward_buckets_size => grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size,
nfa_symbols => grp_nfa_accept_sample_fu_176_nfa_symbols,
sample_req_din => grp_nfa_accept_sample_fu_176_sample_req_din,
sample_req_full_n => grp_nfa_accept_sample_fu_176_sample_req_full_n,
sample_req_write => grp_nfa_accept_sample_fu_176_sample_req_write,
sample_rsp_empty_n => grp_nfa_accept_sample_fu_176_sample_rsp_empty_n,
sample_rsp_read => grp_nfa_accept_sample_fu_176_sample_rsp_read,
sample_address => grp_nfa_accept_sample_fu_176_sample_address,
sample_datain => grp_nfa_accept_sample_fu_176_sample_datain,
sample_dataout => grp_nfa_accept_sample_fu_176_sample_dataout,
sample_size => grp_nfa_accept_sample_fu_176_sample_size,
empty => grp_nfa_accept_sample_fu_176_empty,
length_r => grp_nfa_accept_sample_fu_176_length_r,
ap_return => grp_nfa_accept_sample_fu_176_ap_return);
grp_sample_iterator_get_offset_fu_192 : component sample_iterator_get_offset
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_get_offset_fu_192_ap_start,
ap_done => grp_sample_iterator_get_offset_fu_192_ap_done,
ap_idle => grp_sample_iterator_get_offset_fu_192_ap_idle,
ap_ready => grp_sample_iterator_get_offset_fu_192_ap_ready,
indices_stride_req_din => grp_sample_iterator_get_offset_fu_192_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_get_offset_fu_192_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_get_offset_fu_192_indices_stride_address,
indices_stride_datain => grp_sample_iterator_get_offset_fu_192_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_get_offset_fu_192_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_get_offset_fu_192_indices_stride_size,
indices_begin_req_din => grp_sample_iterator_get_offset_fu_192_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_get_offset_fu_192_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_get_offset_fu_192_indices_begin_address,
indices_begin_datain => grp_sample_iterator_get_offset_fu_192_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_get_offset_fu_192_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_get_offset_fu_192_indices_begin_size,
ap_ce => grp_sample_iterator_get_offset_fu_192_ap_ce,
i_index => grp_sample_iterator_get_offset_fu_192_i_index,
i_sample => grp_sample_iterator_get_offset_fu_192_i_sample,
indices_samples_req_din => grp_sample_iterator_get_offset_fu_192_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_get_offset_fu_192_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_get_offset_fu_192_indices_samples_address,
indices_samples_datain => grp_sample_iterator_get_offset_fu_192_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_get_offset_fu_192_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_get_offset_fu_192_indices_samples_size,
sample_buffer_size => grp_sample_iterator_get_offset_fu_192_sample_buffer_size,
sample_length => grp_sample_iterator_get_offset_fu_192_sample_length,
ap_return => grp_sample_iterator_get_offset_fu_192_ap_return);
grp_sample_iterator_next_fu_209 : component sample_iterator_next
port map (
ap_clk => ap_clk,
ap_rst => ap_rst,
ap_start => grp_sample_iterator_next_fu_209_ap_start,
ap_done => grp_sample_iterator_next_fu_209_ap_done,
ap_idle => grp_sample_iterator_next_fu_209_ap_idle,
ap_ready => grp_sample_iterator_next_fu_209_ap_ready,
indices_samples_req_din => grp_sample_iterator_next_fu_209_indices_samples_req_din,
indices_samples_req_full_n => grp_sample_iterator_next_fu_209_indices_samples_req_full_n,
indices_samples_req_write => grp_sample_iterator_next_fu_209_indices_samples_req_write,
indices_samples_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n,
indices_samples_rsp_read => grp_sample_iterator_next_fu_209_indices_samples_rsp_read,
indices_samples_address => grp_sample_iterator_next_fu_209_indices_samples_address,
indices_samples_datain => grp_sample_iterator_next_fu_209_indices_samples_datain,
indices_samples_dataout => grp_sample_iterator_next_fu_209_indices_samples_dataout,
indices_samples_size => grp_sample_iterator_next_fu_209_indices_samples_size,
ap_ce => grp_sample_iterator_next_fu_209_ap_ce,
indices_begin_req_din => grp_sample_iterator_next_fu_209_indices_begin_req_din,
indices_begin_req_full_n => grp_sample_iterator_next_fu_209_indices_begin_req_full_n,
indices_begin_req_write => grp_sample_iterator_next_fu_209_indices_begin_req_write,
indices_begin_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n,
indices_begin_rsp_read => grp_sample_iterator_next_fu_209_indices_begin_rsp_read,
indices_begin_address => grp_sample_iterator_next_fu_209_indices_begin_address,
indices_begin_datain => grp_sample_iterator_next_fu_209_indices_begin_datain,
indices_begin_dataout => grp_sample_iterator_next_fu_209_indices_begin_dataout,
indices_begin_size => grp_sample_iterator_next_fu_209_indices_begin_size,
indices_stride_req_din => grp_sample_iterator_next_fu_209_indices_stride_req_din,
indices_stride_req_full_n => grp_sample_iterator_next_fu_209_indices_stride_req_full_n,
indices_stride_req_write => grp_sample_iterator_next_fu_209_indices_stride_req_write,
indices_stride_rsp_empty_n => grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n,
indices_stride_rsp_read => grp_sample_iterator_next_fu_209_indices_stride_rsp_read,
indices_stride_address => grp_sample_iterator_next_fu_209_indices_stride_address,
indices_stride_datain => grp_sample_iterator_next_fu_209_indices_stride_datain,
indices_stride_dataout => grp_sample_iterator_next_fu_209_indices_stride_dataout,
indices_stride_size => grp_sample_iterator_next_fu_209_indices_stride_size,
i_index => grp_sample_iterator_next_fu_209_i_index,
i_sample => grp_sample_iterator_next_fu_209_i_sample,
ap_return_0 => grp_sample_iterator_next_fu_209_ap_return_0,
ap_return_1 => grp_sample_iterator_next_fu_209_ap_return_1);
nfa_accept_samples_generic_hw_add_32ns_32ns_32_8_U38 : component nfa_accept_samples_generic_hw_add_32ns_32ns_32_8
generic map (
ID => 38,
NUM_STAGE => 8,
din0_WIDTH => 32,
din1_WIDTH => 32,
dout_WIDTH => 32)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_249_p0,
din1 => grp_fu_249_p1,
ce => grp_fu_249_ce,
dout => grp_fu_249_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_st1_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg assign process. --
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0;
else
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_nfa_accept_sample_fu_176_ap_ready)) then
grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg assign process. --
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st3_fsm_2 = ap_CS_fsm) and (ap_ST_st4_fsm_3 = ap_NS_fsm) and (tmp_i_11_fu_238_p2 = ap_const_lv1_0))) then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_get_offset_fu_192_ap_ready)) then
grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- grp_sample_iterator_next_fu_209_ap_start_ap_start_reg assign process. --
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0;
else
if (((ap_ST_st27_fsm_26 = ap_NS_fsm) and ((ap_ST_st19_fsm_18 = ap_CS_fsm) or (ap_ST_st26_fsm_25 = ap_CS_fsm)))) then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_1;
elsif ((ap_const_logic_1 = grp_sample_iterator_next_fu_209_ap_ready)) then
grp_sample_iterator_next_fu_209_ap_start_ap_start_reg <= ap_const_logic_0;
end if;
end if;
end if;
end process;
-- c_fu_92 assign process. --
c_fu_92_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st27_fsm_26 = ap_CS_fsm) and (or_cond_reg_343 = ap_const_lv1_0))) then
c_fu_92 <= c_1_reg_347;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
c_fu_92 <= ap_const_lv32_0;
end if;
end if;
end process;
-- i_index_reg_144 assign process. --
i_index_reg_144_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
i_index_reg_144 <= grp_sample_iterator_next_fu_209_ap_return_0;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_index_reg_144 <= begin_index;
end if;
end if;
end process;
-- i_sample_reg_154 assign process. --
i_sample_reg_154_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st34_fsm_33 = ap_CS_fsm)) then
i_sample_reg_154 <= grp_sample_iterator_next_fu_209_ap_return_1;
elsif (((ap_ST_st1_fsm_0 = ap_CS_fsm) and not((ap_start = ap_const_logic_0)))) then
i_sample_reg_154 <= begin_sample;
end if;
end if;
end process;
-- p_0_reg_164 assign process. --
p_0_reg_164_assign_proc : process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st19_fsm_18 = ap_CS_fsm) and not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
p_0_reg_164 <= ap_const_lv32_1;
elsif (((ap_ST_st4_fsm_3 = ap_CS_fsm) and not((tmp_i_11_reg_323 = ap_const_lv1_0)))) then
p_0_reg_164 <= c_fu_92;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st26_fsm_25 = ap_CS_fsm)) then
c_1_reg_347 <= grp_fu_249_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st4_fsm_3 = ap_CS_fsm)) then
c_load_reg_327 <= c_fu_92;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st17_fsm_16 = ap_CS_fsm)) then
offset_reg_333 <= grp_sample_iterator_get_offset_fu_192_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st19_fsm_18 = ap_CS_fsm)) then
or_cond_reg_343 <= or_cond_fu_245_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_st18_fsm_17 = ap_CS_fsm) and not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done)))) then
r_reg_338 <= grp_nfa_accept_sample_fu_176_ap_return;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st2_fsm_1 = ap_CS_fsm)) then
tmp_i_10_reg_318 <= tmp_i_10_fu_233_p2;
tmp_i_reg_313 <= tmp_i_fu_228_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if ((ap_ST_st3_fsm_2 = ap_CS_fsm)) then
tmp_i_11_reg_323 <= tmp_i_11_fu_238_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , stop_on_first_read_read_fu_102_p2 , tmp_i_11_reg_323 , grp_nfa_accept_sample_fu_176_ap_done , or_cond_fu_245_p2)
begin
case ap_CS_fsm is
when ap_ST_st1_fsm_0 =>
if (not((ap_start = ap_const_logic_0))) then
ap_NS_fsm <= ap_ST_st2_fsm_1;
else
ap_NS_fsm <= ap_ST_st1_fsm_0;
end if;
when ap_ST_st2_fsm_1 =>
ap_NS_fsm <= ap_ST_st3_fsm_2;
when ap_ST_st3_fsm_2 =>
ap_NS_fsm <= ap_ST_st4_fsm_3;
when ap_ST_st4_fsm_3 =>
if (not((tmp_i_11_reg_323 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st35_fsm_34;
else
ap_NS_fsm <= ap_ST_st5_fsm_4;
end if;
when ap_ST_st5_fsm_4 =>
ap_NS_fsm <= ap_ST_st6_fsm_5;
when ap_ST_st6_fsm_5 =>
ap_NS_fsm <= ap_ST_st7_fsm_6;
when ap_ST_st7_fsm_6 =>
ap_NS_fsm <= ap_ST_st8_fsm_7;
when ap_ST_st8_fsm_7 =>
ap_NS_fsm <= ap_ST_st9_fsm_8;
when ap_ST_st9_fsm_8 =>
ap_NS_fsm <= ap_ST_st10_fsm_9;
when ap_ST_st10_fsm_9 =>
ap_NS_fsm <= ap_ST_st11_fsm_10;
when ap_ST_st11_fsm_10 =>
ap_NS_fsm <= ap_ST_st12_fsm_11;
when ap_ST_st12_fsm_11 =>
ap_NS_fsm <= ap_ST_st13_fsm_12;
when ap_ST_st13_fsm_12 =>
ap_NS_fsm <= ap_ST_st14_fsm_13;
when ap_ST_st14_fsm_13 =>
ap_NS_fsm <= ap_ST_st15_fsm_14;
when ap_ST_st15_fsm_14 =>
ap_NS_fsm <= ap_ST_st16_fsm_15;
when ap_ST_st16_fsm_15 =>
ap_NS_fsm <= ap_ST_st17_fsm_16;
when ap_ST_st17_fsm_16 =>
ap_NS_fsm <= ap_ST_st18_fsm_17;
when ap_ST_st18_fsm_17 =>
if (not((ap_const_logic_0 = grp_nfa_accept_sample_fu_176_ap_done))) then
ap_NS_fsm <= ap_ST_st19_fsm_18;
else
ap_NS_fsm <= ap_ST_st18_fsm_17;
end if;
when ap_ST_st19_fsm_18 =>
if ((not((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0)) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st35_fsm_34;
elsif (((stop_on_first_read_read_fu_102_p2 = ap_const_lv1_0) and (or_cond_fu_245_p2 = ap_const_lv1_0))) then
ap_NS_fsm <= ap_ST_st20_fsm_19;
else
ap_NS_fsm <= ap_ST_st27_fsm_26;
end if;
when ap_ST_st20_fsm_19 =>
ap_NS_fsm <= ap_ST_st21_fsm_20;
when ap_ST_st21_fsm_20 =>
ap_NS_fsm <= ap_ST_st22_fsm_21;
when ap_ST_st22_fsm_21 =>
ap_NS_fsm <= ap_ST_st23_fsm_22;
when ap_ST_st23_fsm_22 =>
ap_NS_fsm <= ap_ST_st24_fsm_23;
when ap_ST_st24_fsm_23 =>
ap_NS_fsm <= ap_ST_st25_fsm_24;
when ap_ST_st25_fsm_24 =>
ap_NS_fsm <= ap_ST_st26_fsm_25;
when ap_ST_st26_fsm_25 =>
ap_NS_fsm <= ap_ST_st27_fsm_26;
when ap_ST_st27_fsm_26 =>
ap_NS_fsm <= ap_ST_st28_fsm_27;
when ap_ST_st28_fsm_27 =>
ap_NS_fsm <= ap_ST_st29_fsm_28;
when ap_ST_st29_fsm_28 =>
ap_NS_fsm <= ap_ST_st30_fsm_29;
when ap_ST_st30_fsm_29 =>
ap_NS_fsm <= ap_ST_st31_fsm_30;
when ap_ST_st31_fsm_30 =>
ap_NS_fsm <= ap_ST_st32_fsm_31;
when ap_ST_st32_fsm_31 =>
ap_NS_fsm <= ap_ST_st33_fsm_32;
when ap_ST_st33_fsm_32 =>
ap_NS_fsm <= ap_ST_st34_fsm_33;
when ap_ST_st34_fsm_33 =>
ap_NS_fsm <= ap_ST_st2_fsm_1;
when ap_ST_st35_fsm_34 =>
ap_NS_fsm <= ap_ST_st1_fsm_0;
when others =>
ap_NS_fsm <= "XXXXXX";
end case;
end process;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_st1_fsm_0 = ap_CS_fsm))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_CS_fsm)
begin
if ((ap_ST_st35_fsm_34 = ap_CS_fsm)) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_return <= p_0_reg_164;
grp_fu_249_ce <= ap_const_logic_1;
grp_fu_249_p0 <= c_load_reg_327;
grp_fu_249_p1 <= ap_const_lv32_1;
grp_nfa_accept_sample_fu_176_ap_start <= grp_nfa_accept_sample_fu_176_ap_start_ap_start_reg;
grp_nfa_accept_sample_fu_176_empty <= offset_reg_333;
grp_nfa_accept_sample_fu_176_length_r <= sample_length;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_datain <= nfa_finals_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_full_n <= nfa_finals_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_empty_n <= nfa_finals_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_datain <= nfa_forward_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_full_n <= nfa_forward_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_empty_n <= nfa_forward_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_datain <= nfa_initials_buckets_datain;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_full_n <= nfa_initials_buckets_req_full_n;
grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_empty_n <= nfa_initials_buckets_rsp_empty_n;
grp_nfa_accept_sample_fu_176_nfa_symbols <= nfa_symbols;
grp_nfa_accept_sample_fu_176_sample_datain <= sample_buffer_datain;
grp_nfa_accept_sample_fu_176_sample_req_full_n <= sample_buffer_req_full_n;
grp_nfa_accept_sample_fu_176_sample_rsp_empty_n <= sample_buffer_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_ap_ce <= ap_const_logic_1;
grp_sample_iterator_get_offset_fu_192_ap_start <= grp_sample_iterator_get_offset_fu_192_ap_start_ap_start_reg;
grp_sample_iterator_get_offset_fu_192_i_index <= i_index_reg_144;
grp_sample_iterator_get_offset_fu_192_i_sample <= i_sample_reg_154;
grp_sample_iterator_get_offset_fu_192_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_get_offset_fu_192_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_get_offset_fu_192_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_get_offset_fu_192_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
grp_sample_iterator_get_offset_fu_192_sample_buffer_size <= sample_buffer_length;
grp_sample_iterator_get_offset_fu_192_sample_length <= sample_length;
grp_sample_iterator_next_fu_209_ap_ce <= ap_const_logic_1;
grp_sample_iterator_next_fu_209_ap_start <= grp_sample_iterator_next_fu_209_ap_start_ap_start_reg;
grp_sample_iterator_next_fu_209_i_index <= i_index_reg_144;
grp_sample_iterator_next_fu_209_i_sample <= i_sample_reg_154;
grp_sample_iterator_next_fu_209_indices_begin_datain <= indices_begin_datain;
grp_sample_iterator_next_fu_209_indices_begin_req_full_n <= indices_begin_req_full_n;
grp_sample_iterator_next_fu_209_indices_begin_rsp_empty_n <= indices_begin_rsp_empty_n;
grp_sample_iterator_next_fu_209_indices_samples_datain <= indices_samples_datain;
grp_sample_iterator_next_fu_209_indices_samples_req_full_n <= indices_samples_req_full_n;
grp_sample_iterator_next_fu_209_indices_samples_rsp_empty_n <= indices_samples_rsp_empty_n;
grp_sample_iterator_next_fu_209_indices_stride_datain <= indices_stride_datain;
grp_sample_iterator_next_fu_209_indices_stride_req_full_n <= indices_stride_req_full_n;
grp_sample_iterator_next_fu_209_indices_stride_rsp_empty_n <= indices_stride_rsp_empty_n;
-- indices_begin_address assign process. --
indices_begin_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_address, grp_sample_iterator_next_fu_209_indices_begin_address)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_next_fu_209_indices_begin_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_address <= grp_sample_iterator_get_offset_fu_192_indices_begin_address;
else
indices_begin_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_dataout assign process. --
indices_begin_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_dataout, grp_sample_iterator_next_fu_209_indices_begin_dataout)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_next_fu_209_indices_begin_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_dataout <= grp_sample_iterator_get_offset_fu_192_indices_begin_dataout;
else
indices_begin_dataout <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_begin_req_din assign process. --
indices_begin_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_req_din, grp_sample_iterator_next_fu_209_indices_begin_req_din)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_next_fu_209_indices_begin_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_req_din <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_din;
else
indices_begin_req_din <= 'X';
end if;
end process;
-- indices_begin_req_write assign process. --
indices_begin_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_req_write, grp_sample_iterator_next_fu_209_indices_begin_req_write)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_next_fu_209_indices_begin_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_req_write <= grp_sample_iterator_get_offset_fu_192_indices_begin_req_write;
else
indices_begin_req_write <= 'X';
end if;
end process;
-- indices_begin_rsp_read assign process. --
indices_begin_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read, grp_sample_iterator_next_fu_209_indices_begin_rsp_read)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_next_fu_209_indices_begin_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_begin_rsp_read;
else
indices_begin_rsp_read <= 'X';
end if;
end process;
-- indices_begin_size assign process. --
indices_begin_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_begin_size, grp_sample_iterator_next_fu_209_indices_begin_size)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_next_fu_209_indices_begin_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_begin_size <= grp_sample_iterator_get_offset_fu_192_indices_begin_size;
else
indices_begin_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_address assign process. --
indices_samples_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_address, grp_sample_iterator_next_fu_209_indices_samples_address)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_next_fu_209_indices_samples_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_address <= grp_sample_iterator_get_offset_fu_192_indices_samples_address;
else
indices_samples_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_dataout assign process. --
indices_samples_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_dataout, grp_sample_iterator_next_fu_209_indices_samples_dataout)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_next_fu_209_indices_samples_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_dataout <= grp_sample_iterator_get_offset_fu_192_indices_samples_dataout;
else
indices_samples_dataout <= "XXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_samples_req_din assign process. --
indices_samples_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_req_din, grp_sample_iterator_next_fu_209_indices_samples_req_din)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_next_fu_209_indices_samples_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_req_din <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_din;
else
indices_samples_req_din <= 'X';
end if;
end process;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_req_write, grp_sample_iterator_next_fu_209_indices_samples_req_write)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_next_fu_209_indices_samples_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_req_write <= grp_sample_iterator_get_offset_fu_192_indices_samples_req_write;
else
indices_samples_req_write <= 'X';
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read, grp_sample_iterator_next_fu_209_indices_samples_rsp_read)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_next_fu_209_indices_samples_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_samples_rsp_read;
else
indices_samples_rsp_read <= 'X';
end if;
end process;
-- indices_samples_size assign process. --
indices_samples_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_samples_size, grp_sample_iterator_next_fu_209_indices_samples_size)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_next_fu_209_indices_samples_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_samples_size <= grp_sample_iterator_get_offset_fu_192_indices_samples_size;
else
indices_samples_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_address assign process. --
indices_stride_address_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_address, grp_sample_iterator_next_fu_209_indices_stride_address)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_next_fu_209_indices_stride_address;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_address <= grp_sample_iterator_get_offset_fu_192_indices_stride_address;
else
indices_stride_address <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
-- indices_stride_dataout assign process. --
indices_stride_dataout_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_dataout, grp_sample_iterator_next_fu_209_indices_stride_dataout)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_next_fu_209_indices_stride_dataout;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_dataout <= grp_sample_iterator_get_offset_fu_192_indices_stride_dataout;
else
indices_stride_dataout <= "XXXXXXXX";
end if;
end process;
-- indices_stride_req_din assign process. --
indices_stride_req_din_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_req_din, grp_sample_iterator_next_fu_209_indices_stride_req_din)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_next_fu_209_indices_stride_req_din;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_req_din <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_din;
else
indices_stride_req_din <= 'X';
end if;
end process;
-- indices_stride_req_write assign process. --
indices_stride_req_write_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_req_write, grp_sample_iterator_next_fu_209_indices_stride_req_write)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_next_fu_209_indices_stride_req_write;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_req_write <= grp_sample_iterator_get_offset_fu_192_indices_stride_req_write;
else
indices_stride_req_write <= 'X';
end if;
end process;
-- indices_stride_rsp_read assign process. --
indices_stride_rsp_read_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read, grp_sample_iterator_next_fu_209_indices_stride_rsp_read)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_next_fu_209_indices_stride_rsp_read;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_rsp_read <= grp_sample_iterator_get_offset_fu_192_indices_stride_rsp_read;
else
indices_stride_rsp_read <= 'X';
end if;
end process;
-- indices_stride_size assign process. --
indices_stride_size_assign_proc : process(ap_CS_fsm, tmp_i_11_reg_323, grp_sample_iterator_get_offset_fu_192_indices_stride_size, grp_sample_iterator_next_fu_209_indices_stride_size)
begin
if (((ap_ST_st34_fsm_33 = ap_CS_fsm) or (ap_ST_st27_fsm_26 = ap_CS_fsm) or (ap_ST_st28_fsm_27 = ap_CS_fsm) or (ap_ST_st29_fsm_28 = ap_CS_fsm) or (ap_ST_st30_fsm_29 = ap_CS_fsm) or (ap_ST_st31_fsm_30 = ap_CS_fsm) or (ap_ST_st32_fsm_31 = ap_CS_fsm) or (ap_ST_st33_fsm_32 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_next_fu_209_indices_stride_size;
elsif (((ap_ST_st17_fsm_16 = ap_CS_fsm) or ((ap_ST_st4_fsm_3 = ap_CS_fsm) and (tmp_i_11_reg_323 = ap_const_lv1_0)) or (ap_ST_st5_fsm_4 = ap_CS_fsm) or (ap_ST_st6_fsm_5 = ap_CS_fsm) or (ap_ST_st7_fsm_6 = ap_CS_fsm) or (ap_ST_st8_fsm_7 = ap_CS_fsm) or (ap_ST_st9_fsm_8 = ap_CS_fsm) or (ap_ST_st10_fsm_9 = ap_CS_fsm) or (ap_ST_st11_fsm_10 = ap_CS_fsm) or (ap_ST_st12_fsm_11 = ap_CS_fsm) or (ap_ST_st13_fsm_12 = ap_CS_fsm) or (ap_ST_st14_fsm_13 = ap_CS_fsm) or (ap_ST_st15_fsm_14 = ap_CS_fsm) or (ap_ST_st16_fsm_15 = ap_CS_fsm))) then
indices_stride_size <= grp_sample_iterator_get_offset_fu_192_indices_stride_size;
else
indices_stride_size <= "XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX";
end if;
end process;
nfa_finals_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_address;
nfa_finals_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_dataout;
nfa_finals_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_din;
nfa_finals_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_req_write;
nfa_finals_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_rsp_read;
nfa_finals_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_finals_buckets_size;
nfa_forward_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_address;
nfa_forward_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_dataout;
nfa_forward_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_din;
nfa_forward_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_req_write;
nfa_forward_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_rsp_read;
nfa_forward_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_forward_buckets_size;
nfa_initials_buckets_address <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_address;
nfa_initials_buckets_dataout <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_dataout;
nfa_initials_buckets_req_din <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_din;
nfa_initials_buckets_req_write <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_req_write;
nfa_initials_buckets_rsp_read <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_rsp_read;
nfa_initials_buckets_size <= grp_nfa_accept_sample_fu_176_nfa_initials_buckets_size;
or_cond_fu_245_p2 <= (r_reg_338 xor accept);
sample_buffer_address <= grp_nfa_accept_sample_fu_176_sample_address;
sample_buffer_dataout <= grp_nfa_accept_sample_fu_176_sample_dataout;
sample_buffer_req_din <= grp_nfa_accept_sample_fu_176_sample_req_din;
sample_buffer_req_write <= grp_nfa_accept_sample_fu_176_sample_req_write;
sample_buffer_rsp_read <= grp_nfa_accept_sample_fu_176_sample_rsp_read;
sample_buffer_size <= grp_nfa_accept_sample_fu_176_sample_size;
stop_on_first_read_read_fu_102_p2 <= stop_on_first;
tmp_i_10_fu_233_p2 <= "1" when (i_index_reg_144 = end_index) else "0";
tmp_i_11_fu_238_p2 <= (tmp_i_reg_313 and tmp_i_10_reg_318);
tmp_i_fu_228_p2 <= "1" when (i_sample_reg_154 = end_sample) else "0";
end behav;
|
-------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity AC_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLC_AC_size : out unsigned(4 downto 0);
VLC_AC : out unsigned(15 downto 0)
);
end entity AC_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of AC_ROM is
signal rom_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rom_addr <= runlength & VLI_size;
-------------------------------------------------------------------
-- AC-ROM
-------------------------------------------------------------------
p_AC_ROM : process(CLK, RST)
begin
if RST = '1' then
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
elsif CLK'event and CLK = '1' then
case runlength is
when X"0" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1010", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("00", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("01", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length);
VLC_AC <= resize("100", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000010", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000011", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"1" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1100", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11011", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110110", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"2" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11100", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"3" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"4" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"5" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"6" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"7" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"8" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"9" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"A" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001000", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001001", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001011", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001100", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001101", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001110", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001111", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"B" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010010", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010011", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"C" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011010", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011100", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011101", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011110", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011111", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100000", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100001", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"D" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100010", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100011", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100101", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100110", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100111", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101000", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101001", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101010", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"E" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101100", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101111", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110001", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110010", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110011", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110100", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"F" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111001", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110101", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when others =>
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
-------------------------------------------------------------------------------
-- File Name : AC_ROM.vhd
--
-- Project : JPEG_ENC
--
-- Module : AC_ROM
--
-- Content : AC_ROM Luminance
--
-- Description :
--
-- Spec. :
--
-- Author : Michal Krepa
--
-------------------------------------------------------------------------------
-- History :
-- 20090228: (MK): Initial Creation.
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- LIBRARY/PACKAGE ---------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- generic packages/libraries:
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
-------------------------------------------------------------------------------
-- user packages/libraries:
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ENTITY ------------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
entity AC_ROM is
port
(
CLK : in std_logic;
RST : in std_logic;
runlength : in std_logic_vector(3 downto 0);
VLI_size : in std_logic_vector(3 downto 0);
VLC_AC_size : out unsigned(4 downto 0);
VLC_AC : out unsigned(15 downto 0)
);
end entity AC_ROM;
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
----------------------------------- ARCHITECTURE ------------------------------
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
architecture RTL of AC_ROM is
signal rom_addr : std_logic_vector(7 downto 0);
-------------------------------------------------------------------------------
-- Architecture: begin
-------------------------------------------------------------------------------
begin
rom_addr <= runlength & VLI_size;
-------------------------------------------------------------------
-- AC-ROM
-------------------------------------------------------------------
p_AC_ROM : process(CLK, RST)
begin
if RST = '1' then
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
elsif CLK'event and CLK = '1' then
case runlength is
when X"0" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1010", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("00", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(2, VLC_AC_size'length);
VLC_AC <= resize("01", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(3, VLC_AC_size'length);
VLC_AC <= resize("100", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111000", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000010", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000011", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"1" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(4, VLC_AC_size'length);
VLC_AC <= resize("1100", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11011", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110110", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110000111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"2" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(5, VLC_AC_size'length);
VLC_AC <= resize("11100", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"3" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110001111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"4" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(6, VLC_AC_size'length);
VLC_AC <= resize("111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110010111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"5" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110011111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"6" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(7, VLC_AC_size'length);
VLC_AC <= resize("1111011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110100111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"7" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(8, VLC_AC_size'length);
VLC_AC <= resize("11111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(12, VLC_AC_size'length);
VLC_AC <= resize("111111110111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110101111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"8" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(15, VLC_AC_size'length);
VLC_AC <= resize("111111111000000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110110", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110110111", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111000", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111001", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111010", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111011", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111100", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111101", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"9" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111110111111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"A" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(9, VLC_AC_size'length);
VLC_AC <= resize("111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111000111", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001000", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001001", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001010", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001011", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001100", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001101", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001110", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111001111", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"B" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111001", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010000", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010001", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010010", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010011", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010100", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010101", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010110", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111010111", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011000", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"C" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(10, VLC_AC_size'length);
VLC_AC <= resize("1111111010", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011001", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011010", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011011", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011100", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011101", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011110", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111011111", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100000", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100001", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"D" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111000", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100010", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100011", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100100", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100101", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100110", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111100111", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101000", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101001", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101010", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"E" =>
case VLI_size is
when X"1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101011", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101100", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101101", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101110", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111101111", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110000", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110001", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110010", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110011", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110100", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when X"F" =>
case VLI_size is
when X"0" =>
VLC_AC_size <= to_unsigned(11, VLC_AC_size'length);
VLC_AC <= resize("11111111001", VLC_AC'length);
when X"1" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110101", VLC_AC'length);
when X"2" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110110", VLC_AC'length);
when X"3" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111110111", VLC_AC'length);
when X"4" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111000", VLC_AC'length);
when X"5" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111001", VLC_AC'length);
when X"6" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111010", VLC_AC'length);
when X"7" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111011", VLC_AC'length);
when X"8" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111100", VLC_AC'length);
when X"9" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111101", VLC_AC'length);
when X"A" =>
VLC_AC_size <= to_unsigned(16, VLC_AC_size'length);
VLC_AC <= resize("1111111111111110", VLC_AC'length);
when others =>
VLC_AC_size <= to_unsigned(0, VLC_AC_size'length);
VLC_AC <= resize("0", VLC_AC'length);
end case;
when others =>
VLC_AC_size <= (others => '0');
VLC_AC <= (others => '0');
end case;
end if;
end process;
end architecture RTL;
-------------------------------------------------------------------------------
-- Architecture: end
------------------------------------------------------------------------------- |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_516 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_516;
architecture augh of add_516 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_516 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_516;
architecture augh of add_516 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
-------------------------------------------------------------------------------------
-- FILE NAME : sip_capture_4x.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_mem_if_i
-- architecture - arch_sip_mem_if_i
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
-- Data comes in on in0 and it is multiplexed sequentially between out0 and out1
-- Data comes in on in1 and it is multiplexed sequentially between out2 and out3
-- Data comes in on in2 and if we are in mode = 0, it goes to out4 but converted from 64-bit to 128-bit
-- Data comes in on in3 and if we are in mode = 0 it is dropped stop will be held = 0. If we are in mode = 1
-- data must also come in on in2 because they are combined and go into out4.
-- sip_mem_if_i
-- Notes: sip_mem_if_i
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity sip_capture_x4 is
generic (
global_start_addr_gen : std_logic_vector(27 downto 0);
global_stop_addr_gen : std_logic_vector(27 downto 0);
private_start_addr_gen : std_logic_vector(27 downto 0);
private_stop_addr_gen : std_logic_vector(27 downto 0)
);
port (
--Wormhole 'cmdclk_in' of type 'cmdclk_in':
cmdclk_in_cmdclk : in std_logic;
--Wormhole 'cmd_in' of type 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out' of type 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'clk' of type 'clkin':
clk_clkin : in std_logic_vector(31 downto 0);
--Wormhole 'rst' of type 'rst_in':
rst_rstin : in std_logic_vector(31 downto 0);
--Wormhole 'out0' of type 'wh_out':
out0_out_stop : in std_logic;
out0_out_dval : out std_logic;
out0_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out1' of type 'wh_out':
out1_out_stop : in std_logic;
out1_out_dval : out std_logic;
out1_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out2' of type 'wh_out':
out2_out_stop : in std_logic;
out2_out_dval : out std_logic;
out2_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'out3' of type 'wh_out':
out3_out_stop : in std_logic;
out3_out_dval : out std_logic;
out3_out_data : out std_logic_vector(63 downto 0);
--Wormhole 'in0' of type 'wh_in':
in0_in_stop : out std_logic;
in0_in_dval : in std_logic;
in0_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in1' of type 'wh_in':
in1_in_stop : out std_logic;
in1_in_dval : in std_logic;
in1_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in2' of type 'wh_in':
in2_in_stop : out std_logic;
in2_in_dval : in std_logic;
in2_in_data : in std_logic_vector(63 downto 0);
--Wormhole 'in3' of type 'wh_in':
in3_in_stop : out std_logic;
in3_in_dval : in std_logic;
in3_in_data : in std_logic_vector(63 downto 0)
);
end entity sip_capture_x4;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture bev of sip_capture_x4 is
-------------------------------------------------------------------------------------
--Constants declaration
-------------------------------------------------------------------------------------
type bus64 is array(natural range <>) of std_logic_vector(63 downto 0);
type bus12 is array(natural range <>) of std_logic_vector(11 downto 0);
type bus08 is array(natural range <>) of std_logic_vector(7 downto 0);
attribute keep : string;
-------------------------------------------------------------------------------------
--Signal declaration
-------------------------------------------------------------------------------------
signal clk_in : std_logic;
signal clk_out : std_logic;
signal rst : std_logic;
signal local_reset : std_logic;
signal fifo_in : bus64(3 downto 0);
signal fifo_out : bus64(3 downto 0);
signal fifo_wr_en : std_logic_vector(3 downto 0);
signal fifo_valid : std_logic_vector(3 downto 0);
signal fifo_rd_en : std_logic_vector(3 downto 0);
signal fifo_empty : std_logic_vector(3 downto 0);
signal fifo_full : std_logic_vector(3 downto 0);
signal fifo_count : bus12(3 downto 0);
signal register0 : std_logic_vector(31 downto 0);
signal register1 : std_logic_vector(31 downto 0);
signal register0_r : std_logic_vector(31 downto 0);
signal register1_r : std_logic_vector(31 downto 0);
signal register2 : std_logic_vector(31 downto 0);
signal register3 : std_logic_vector(31 downto 0);
signal register4 : std_logic_vector(31 downto 0);
signal register5 : std_logic_vector(31 downto 0);
signal register6 : std_logic_vector(31 downto 0);
signal register7 : std_logic_vector(31 downto 0);
signal register8 : std_logic_vector(31 downto 0);
signal align_fifo_in : bus64(3 downto 0);
signal align_fifo_out : bus64(3 downto 0);
signal align_fifo_wr_en : std_logic_vector(3 downto 0);
signal align_fifo_valid : std_logic_vector(3 downto 0);
signal align_fifo_empty : std_logic_vector(3 downto 0);
signal align_fifo_rd_en : std_logic;
signal byte_align_out : bus64(3 downto 0);
signal byte_align_valid : std_logic_vector(3 downto 0);
signal status : bus08(3 downto 0);
signal check_reset : std_logic;
signal check_enable : std_logic;
signal perfomance_reset : std_logic;
signal performance_en : std_logic;
signal force_error : std_logic_vector(3 downto 0);
signal input_count : std_logic_vector(63 downto 0);
signal cycle_count : std_logic_vector(63 downto 0);
signal output_count : std_logic_vector(63 downto 0);
----------------------------------------------------------------------------------------
-- Debugging
---------------------------------------------------------------------------------------
COMPONENT ila_0
PORT (
clk : IN STD_LOGIC;
probe0 : IN STD_LOGIC_VECTOR(255 DOWNTO 0)
);
END COMPONENT;
ATTRIBUTE SYN_BLACK_BOX : BOOLEAN;
ATTRIBUTE SYN_BLACK_BOX OF ila_0 : COMPONENT IS TRUE;
ATTRIBUTE BLACK_BOX_PAD_PIN : STRING;
ATTRIBUTE BLACK_BOX_PAD_PIN OF ila_0 : COMPONENT IS "clk,probe0[255:0]";
signal probe0 : std_logic_vector(255 downto 0);
signal dbg_data0 : std_logic_vector(63 downto 0);
signal dbg_data1 : std_logic_vector(63 downto 0);
signal dbg_data2 : std_logic_vector(63 downto 0);
signal dbg_valid0 : std_logic;
signal dbg_valid1 : std_logic;
signal dbg_valid2 : std_logic;
attribute keep of dbg_data1 : signal is "true";
attribute keep of dbg_data2 : signal is "true";
attribute keep of dbg_data0 : signal is "true";
attribute keep of dbg_valid0 : signal is "true";
attribute keep of dbg_valid1 : signal is "true";
attribute keep of dbg_valid2 : signal is "true";
--***********************************************************************************
begin
--***********************************************************************************
clk_in <= clk_clkin(13);
clk_out <= clk_clkin(14);
rst <= rst_rstin(2);
-------------------------------------------------------------------------------------
-- Local reset
-------------------------------------------------------------------------------------
process(clk_in)
begin
if rst = '1' then
local_reset <= '1';
elsif rising_edge(clk_in) then
local_reset <= '0';
end if;
end process;
-------------------------------------------------------------------------------------
-- Align Input
-------------------------------------------------------------------------------------
process(clk_in)
begin
if rising_edge(clk_in) then
if force_error(0) = '1' then
align_fifo_in(0) <= (others=>'0');
else
align_fifo_in(0) <= in0_in_data;
end if;
if force_error(1) = '1' then
align_fifo_in(1) <= (others=>'0');
else
align_fifo_in(1) <= in1_in_data;
end if;
if force_error(2) = '1' then
align_fifo_in(2) <= (others=>'0');
else
align_fifo_in(2) <= in2_in_data;
end if;
if force_error(3) = '1' then
align_fifo_in(3) <= (others=>'0');
else
align_fifo_in(3) <= in3_in_data;
end if;
align_fifo_wr_en(0) <= in0_in_dval;
align_fifo_wr_en(1) <= in1_in_dval;
align_fifo_wr_en(2) <= in2_in_dval;
align_fifo_wr_en(3) <= in3_in_dval;
end if;
end process;
in0_in_stop <= '0';
in1_in_stop <= '0';
in2_in_stop <= '0';
in3_in_stop <= '0';
alignment_generate:
for I in 0 to 3 generate
async_fifo_align_64in_out_inst0:
entity work.async_fifo_align_64in_out
port map (
clk => clk_in,
rst => local_reset,
din => align_fifo_in(I),
wr_en => align_fifo_wr_en(I),
rd_en => align_fifo_rd_en,
dout => align_fifo_out(I),
full => open,
empty => align_fifo_empty(I),
valid => align_fifo_valid(I)
);
byte_align0:
entity work.data_align
port map (
clk_in => clk_in,
rst_in => local_reset,
data_in => align_fifo_out(I),
val_in => align_fifo_valid(I),
data_out => byte_align_out(I),
val_out => byte_align_valid(I)
);
-- Data Check
data_check_0:
entity work.data_check
port map (
clk_in => clk_in,
rst_in => check_reset,
data_in => byte_align_out(I),
valid_in => byte_align_valid(I),
check_en_in => check_enable,
status_out => status(I)
);
end generate;
align_fifo_rd_en <= not or_reduce(align_fifo_empty);
-------------------------------------------------------------------------------------------
-- Performance Measure
-------------------------------------------------------------------------------------------
performance_inst0:
entity work.performance
port map(
clk_in => clk_in,
rst_in => perfomance_reset,
start_in => performance_en,
in_val => '0',
out_val => align_fifo_valid(0), --fifo_wr,
in_cnt => input_count, -- out
cycle_cnt => cycle_count, -- out
out_cnt => output_count -- out
);
-------------------------------------------------------------------------------------
-- Capture incomming data
-------------------------------------------------------------------------------------
fifo_generate:
for I in 0 to 3 generate
fifo_64in_out_inst0 : entity work.fifo_64in_out
PORT MAP (
wr_clk => clk_in,
rd_clk => clk_out,
rst => local_reset,
din => align_fifo_in(I),
wr_en => align_fifo_wr_en(I),
rd_en => fifo_rd_en(I),
dout => fifo_out(I),
full => fifo_full(I),
empty => fifo_empty(I),
valid => fifo_valid(I),
rd_data_count => fifo_count(I)
);
end generate;
fifo_rd_en(0) <= (not fifo_empty(0) and not out0_out_stop);
fifo_rd_en(1) <= (not fifo_empty(1) and not out1_out_stop);
fifo_rd_en(2) <= (not fifo_empty(2) and not out2_out_stop);
fifo_rd_en(3) <= (not fifo_empty(3) and not out3_out_stop);
-------------------------------------------------------------------------------------
-- register outputs
-------------------------------------------------------------------------------------
process(clk_out)
begin
if rising_edge(clk_out) then
out0_out_dval <= fifo_valid(0);
out0_out_data <= fifo_out(0);
out1_out_dval <= fifo_valid(1);
out1_out_data <= fifo_out(1);
out2_out_dval <= fifo_valid(2);
out2_out_data <= fifo_out(2);
out3_out_dval <= fifo_valid(3);
out3_out_data <= fifo_out(3);
end if;
end process;
-------------------------------------------------------------------------------------
-- Command Interface
-------------------------------------------------------------------------------------
ip_block_ctrl_inst0: entity work.ip_block_ctrl
generic map (
START_ADDR => private_start_addr_gen,
STOP_ADDR => private_stop_addr_gen
)
port map(
rst => rst,
clk_cmd => clk_out,
in_cmd_val => cmd_in_cmdin_val,
in_cmd => cmd_in_cmdin,
out_cmd_val => cmd_out_cmdout_val,
out_cmd => cmd_out_cmdout,
cmd_busy => open,
reg0 => register0, -- out
reg1 => register1, -- out
reg2 => register2, -- in
reg3 => register3, -- in
reg4 => register4, -- in
reg5 => register5, -- in
reg6 => register6, -- in
reg7 => register7, -- in
reg8 => register8, -- in
mbx_in_reg => (others=>'0'), -- in
mbx_in_val => '0' -- in
);
-- register mapping synth clock domain
process(clk_in)
begin
if rising_edge(clk_in) then
register0_r <= register0;
register1_r <= register1;
check_reset <= register0_r(0);
perfomance_reset <= register0_r(4);
check_enable <= register1_r(0);
performance_en <= register1_r(4);
force_error <= register1_r(11 downto 8);
end if;
end process;
-- register mapping command clock domain
process(clk_out)
begin
if rising_edge(clk_out) then
register2 <= status(3) & status(2) & status(1) & status(0);
register3 <= cycle_count(31 downto 0); -- cycle count LSB
register4 <= output_count(31 downto 0); -- output count LSB
register5 <= cycle_count(63 downto 32); -- cycle count MSB
register6 <= output_count(63 downto 32); -- output count MSB
register7 <= "0001" & fifo_count(1) & "0000" & fifo_count(0);
register8 <= "0011" & fifo_count(3) & "0010" & fifo_count(2);
end if;
end process;
-------------------------------------------------------------------------------------
-- Debug Section
-------------------------------------------------------------------------------------
--ila_inst0 : ila_0
-- PORT MAP (
-- clk => clk_in,
-- probe0 => probe0
-- );
--
--process(clk_in)
--begin
-- if rising_edge(clk_in) then
-- dbg_data0 <= byte_align_out(0);
-- dbg_data1 <= byte_align_out(1);
-- dbg_data2 <= byte_align_out(2);
-- dbg_valid0 <= align_fifo_valid(0);
-- dbg_valid1 <= align_fifo_valid(1);
-- dbg_valid2 <= align_fifo_valid(2);
-- end if;
--end process;
--
--probe0(63 downto 0) <= dbg_data0;
--probe0(127 downto 64) <= dbg_data1;
--probe0(191 downto 128) <= dbg_data2;
--probe0(192) <= dbg_valid0;
--probe0(193) <= dbg_valid1;
--probe0(194) <= dbg_valid2;
--probe0(255 downto 195) <= (others=>'0');
--***********************************************************************************
end architecture bev;
--***********************************************************************************
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2018.2
-- Copyright (C) 1986-2018 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity video_scaler_ctrl_s_axi is
generic (
C_S_AXI_ADDR_WIDTH : INTEGER := 6;
C_S_AXI_DATA_WIDTH : INTEGER := 32);
port (
-- axi4 lite slave signals
ACLK :in STD_LOGIC;
ARESET :in STD_LOGIC;
ACLK_EN :in STD_LOGIC;
AWADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
AWVALID :in STD_LOGIC;
AWREADY :out STD_LOGIC;
WDATA :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
WSTRB :in STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH/8-1 downto 0);
WVALID :in STD_LOGIC;
WREADY :out STD_LOGIC;
BRESP :out STD_LOGIC_VECTOR(1 downto 0);
BVALID :out STD_LOGIC;
BREADY :in STD_LOGIC;
ARADDR :in STD_LOGIC_VECTOR(C_S_AXI_ADDR_WIDTH-1 downto 0);
ARVALID :in STD_LOGIC;
ARREADY :out STD_LOGIC;
RDATA :out STD_LOGIC_VECTOR(C_S_AXI_DATA_WIDTH-1 downto 0);
RRESP :out STD_LOGIC_VECTOR(1 downto 0);
RVALID :out STD_LOGIC;
RREADY :in STD_LOGIC;
interrupt :out STD_LOGIC;
-- user signals
ap_start :out STD_LOGIC;
ap_done :in STD_LOGIC;
ap_ready :in STD_LOGIC;
ap_idle :in STD_LOGIC;
in_width :out STD_LOGIC_VECTOR(31 downto 0);
in_height :out STD_LOGIC_VECTOR(31 downto 0);
out_width :out STD_LOGIC_VECTOR(31 downto 0);
out_height :out STD_LOGIC_VECTOR(31 downto 0)
);
end entity video_scaler_ctrl_s_axi;
-- ------------------------Address Info-------------------
-- 0x00 : Control signals
-- bit 0 - ap_start (Read/Write/COH)
-- bit 1 - ap_done (Read/COR)
-- bit 2 - ap_idle (Read)
-- bit 3 - ap_ready (Read)
-- bit 7 - auto_restart (Read/Write)
-- others - reserved
-- 0x04 : Global Interrupt Enable Register
-- bit 0 - Global Interrupt Enable (Read/Write)
-- others - reserved
-- 0x08 : IP Interrupt Enable Register (Read/Write)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x0c : IP Interrupt Status Register (Read/TOW)
-- bit 0 - Channel 0 (ap_done)
-- bit 1 - Channel 1 (ap_ready)
-- others - reserved
-- 0x10 : Data signal of in_width
-- bit 31~0 - in_width[31:0] (Read/Write)
-- 0x14 : reserved
-- 0x18 : Data signal of in_height
-- bit 31~0 - in_height[31:0] (Read/Write)
-- 0x1c : reserved
-- 0x20 : Data signal of out_width
-- bit 31~0 - out_width[31:0] (Read/Write)
-- 0x24 : reserved
-- 0x28 : Data signal of out_height
-- bit 31~0 - out_height[31:0] (Read/Write)
-- 0x2c : reserved
-- (SC = Self Clear, COR = Clear on Read, TOW = Toggle on Write, COH = Clear on Handshake)
architecture behave of video_scaler_ctrl_s_axi is
type states is (wridle, wrdata, wrresp, wrreset, rdidle, rddata, rdreset); -- read and write fsm states
signal wstate : states := wrreset;
signal rstate : states := rdreset;
signal wnext, rnext: states;
constant ADDR_AP_CTRL : INTEGER := 16#00#;
constant ADDR_GIE : INTEGER := 16#04#;
constant ADDR_IER : INTEGER := 16#08#;
constant ADDR_ISR : INTEGER := 16#0c#;
constant ADDR_IN_WIDTH_DATA_0 : INTEGER := 16#10#;
constant ADDR_IN_WIDTH_CTRL : INTEGER := 16#14#;
constant ADDR_IN_HEIGHT_DATA_0 : INTEGER := 16#18#;
constant ADDR_IN_HEIGHT_CTRL : INTEGER := 16#1c#;
constant ADDR_OUT_WIDTH_DATA_0 : INTEGER := 16#20#;
constant ADDR_OUT_WIDTH_CTRL : INTEGER := 16#24#;
constant ADDR_OUT_HEIGHT_DATA_0 : INTEGER := 16#28#;
constant ADDR_OUT_HEIGHT_CTRL : INTEGER := 16#2c#;
constant ADDR_BITS : INTEGER := 6;
signal waddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal wmask : UNSIGNED(31 downto 0);
signal aw_hs : STD_LOGIC;
signal w_hs : STD_LOGIC;
signal rdata_data : UNSIGNED(31 downto 0);
signal ar_hs : STD_LOGIC;
signal raddr : UNSIGNED(ADDR_BITS-1 downto 0);
signal AWREADY_t : STD_LOGIC;
signal WREADY_t : STD_LOGIC;
signal ARREADY_t : STD_LOGIC;
signal RVALID_t : STD_LOGIC;
-- internal registers
signal int_ap_idle : STD_LOGIC;
signal int_ap_ready : STD_LOGIC;
signal int_ap_done : STD_LOGIC := '0';
signal int_ap_start : STD_LOGIC := '0';
signal int_auto_restart : STD_LOGIC := '0';
signal int_gie : STD_LOGIC := '0';
signal int_ier : UNSIGNED(1 downto 0) := (others => '0');
signal int_isr : UNSIGNED(1 downto 0) := (others => '0');
signal int_in_width : UNSIGNED(31 downto 0) := (others => '0');
signal int_in_height : UNSIGNED(31 downto 0) := (others => '0');
signal int_out_width : UNSIGNED(31 downto 0) := (others => '0');
signal int_out_height : UNSIGNED(31 downto 0) := (others => '0');
begin
-- ----------------------- Instantiation------------------
-- ----------------------- AXI WRITE ---------------------
AWREADY_t <= '1' when wstate = wridle else '0';
AWREADY <= AWREADY_t;
WREADY_t <= '1' when wstate = wrdata else '0';
WREADY <= WREADY_t;
BRESP <= "00"; -- OKAY
BVALID <= '1' when wstate = wrresp else '0';
wmask <= (31 downto 24 => WSTRB(3), 23 downto 16 => WSTRB(2), 15 downto 8 => WSTRB(1), 7 downto 0 => WSTRB(0));
aw_hs <= AWVALID and AWREADY_t;
w_hs <= WVALID and WREADY_t;
-- write FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
wstate <= wrreset;
elsif (ACLK_EN = '1') then
wstate <= wnext;
end if;
end if;
end process;
process (wstate, AWVALID, WVALID, BREADY)
begin
case (wstate) is
when wridle =>
if (AWVALID = '1') then
wnext <= wrdata;
else
wnext <= wridle;
end if;
when wrdata =>
if (WVALID = '1') then
wnext <= wrresp;
else
wnext <= wrdata;
end if;
when wrresp =>
if (BREADY = '1') then
wnext <= wridle;
else
wnext <= wrresp;
end if;
when others =>
wnext <= wridle;
end case;
end process;
waddr_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (aw_hs = '1') then
waddr <= UNSIGNED(AWADDR(ADDR_BITS-1 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- AXI READ ----------------------
ARREADY_t <= '1' when (rstate = rdidle) else '0';
ARREADY <= ARREADY_t;
RDATA <= STD_LOGIC_VECTOR(rdata_data);
RRESP <= "00"; -- OKAY
RVALID_t <= '1' when (rstate = rddata) else '0';
RVALID <= RVALID_t;
ar_hs <= ARVALID and ARREADY_t;
raddr <= UNSIGNED(ARADDR(ADDR_BITS-1 downto 0));
-- read FSM
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
rstate <= rdreset;
elsif (ACLK_EN = '1') then
rstate <= rnext;
end if;
end if;
end process;
process (rstate, ARVALID, RREADY, RVALID_t)
begin
case (rstate) is
when rdidle =>
if (ARVALID = '1') then
rnext <= rddata;
else
rnext <= rdidle;
end if;
when rddata =>
if (RREADY = '1' and RVALID_t = '1') then
rnext <= rdidle;
else
rnext <= rddata;
end if;
when others =>
rnext <= rdidle;
end case;
end process;
rdata_proc : process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (ar_hs = '1') then
case (TO_INTEGER(raddr)) is
when ADDR_AP_CTRL =>
rdata_data <= (7 => int_auto_restart, 3 => int_ap_ready, 2 => int_ap_idle, 1 => int_ap_done, 0 => int_ap_start, others => '0');
when ADDR_GIE =>
rdata_data <= (0 => int_gie, others => '0');
when ADDR_IER =>
rdata_data <= (1 => int_ier(1), 0 => int_ier(0), others => '0');
when ADDR_ISR =>
rdata_data <= (1 => int_isr(1), 0 => int_isr(0), others => '0');
when ADDR_IN_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_in_width(31 downto 0), 32);
when ADDR_IN_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_in_height(31 downto 0), 32);
when ADDR_OUT_WIDTH_DATA_0 =>
rdata_data <= RESIZE(int_out_width(31 downto 0), 32);
when ADDR_OUT_HEIGHT_DATA_0 =>
rdata_data <= RESIZE(int_out_height(31 downto 0), 32);
when others =>
rdata_data <= (others => '0');
end case;
end if;
end if;
end if;
end process;
-- ----------------------- Register logic ----------------
interrupt <= int_gie and (int_isr(0) or int_isr(1));
ap_start <= int_ap_start;
in_width <= STD_LOGIC_VECTOR(int_in_width);
in_height <= STD_LOGIC_VECTOR(int_in_height);
out_width <= STD_LOGIC_VECTOR(int_out_width);
out_height <= STD_LOGIC_VECTOR(int_out_height);
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_start <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1' and WDATA(0) = '1') then
int_ap_start <= '1';
elsif (ap_ready = '1') then
int_ap_start <= int_auto_restart; -- clear on handshake/auto restart
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_done <= '0';
elsif (ACLK_EN = '1') then
if (ap_done = '1') then
int_ap_done <= '1';
elsif (ar_hs = '1' and raddr = ADDR_AP_CTRL) then
int_ap_done <= '0'; -- clear on read
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_idle <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_idle <= ap_idle;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ap_ready <= '0';
elsif (ACLK_EN = '1') then
if (true) then
int_ap_ready <= ap_ready;
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_auto_restart <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_AP_CTRL and WSTRB(0) = '1') then
int_auto_restart <= WDATA(7);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_gie <= '0';
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_GIE and WSTRB(0) = '1') then
int_gie <= WDATA(0);
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_ier <= "00";
elsif (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IER and WSTRB(0) = '1') then
int_ier <= UNSIGNED(WDATA(1 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(0) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(0) = '1' and ap_done = '1') then
int_isr(0) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(0) <= int_isr(0) xor WDATA(0); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ARESET = '1') then
int_isr(1) <= '0';
elsif (ACLK_EN = '1') then
if (int_ier(1) = '1' and ap_ready = '1') then
int_isr(1) <= '1';
elsif (w_hs = '1' and waddr = ADDR_ISR and WSTRB(0) = '1') then
int_isr(1) <= int_isr(1) xor WDATA(1); -- toggle on write
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IN_WIDTH_DATA_0) then
int_in_width(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in_width(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_IN_HEIGHT_DATA_0) then
int_in_height(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_in_height(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OUT_WIDTH_DATA_0) then
int_out_width(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_width(31 downto 0));
end if;
end if;
end if;
end process;
process (ACLK)
begin
if (ACLK'event and ACLK = '1') then
if (ACLK_EN = '1') then
if (w_hs = '1' and waddr = ADDR_OUT_HEIGHT_DATA_0) then
int_out_height(31 downto 0) <= (UNSIGNED(WDATA(31 downto 0)) and wmask(31 downto 0)) or ((not wmask(31 downto 0)) and int_out_height(31 downto 0));
end if;
end if;
end if;
end process;
-- ----------------------- Memory logic ------------------
end architecture behave;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 368;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"87444000";
when 16#0002D# => romdata <= X"8730E01C";
when 16#0002E# => romdata <= X"8688E00F";
when 16#0002F# => romdata <= X"12800016";
when 16#00030# => romdata <= X"03200000";
when 16#00031# => romdata <= X"05040E00";
when 16#00032# => romdata <= X"8410A233";
when 16#00033# => romdata <= X"C4204000";
when 16#00034# => romdata <= X"0539A81B";
when 16#00035# => romdata <= X"8410A260";
when 16#00036# => romdata <= X"C4206004";
when 16#00037# => romdata <= X"050003FC";
when 16#00038# => romdata <= X"C4206008";
when 16#00039# => romdata <= X"82103860";
when 16#0003A# => romdata <= X"C4004000";
when 16#0003B# => romdata <= X"8530A00C";
when 16#0003C# => romdata <= X"03000004";
when 16#0003D# => romdata <= X"82106009";
when 16#0003E# => romdata <= X"80A04002";
when 16#0003F# => romdata <= X"12800006";
when 16#00040# => romdata <= X"033FFC00";
when 16#00041# => romdata <= X"82106100";
when 16#00042# => romdata <= X"0539A81B";
when 16#00043# => romdata <= X"8410A260";
when 16#00044# => romdata <= X"C4204000";
when 16#00045# => romdata <= X"05000008";
when 16#00046# => romdata <= X"82100000";
when 16#00047# => romdata <= X"80A0E000";
when 16#00048# => romdata <= X"02800005";
when 16#00049# => romdata <= X"01000000";
when 16#0004A# => romdata <= X"82004002";
when 16#0004B# => romdata <= X"10BFFFFC";
when 16#0004C# => romdata <= X"8620E001";
when 16#0004D# => romdata <= X"3D1003FF";
when 16#0004E# => romdata <= X"BC17A3E0";
when 16#0004F# => romdata <= X"BC278001";
when 16#00050# => romdata <= X"9C27A060";
when 16#00051# => romdata <= X"03100000";
when 16#00052# => romdata <= X"81C04000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"01000000";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"00000000";
when 16#00059# => romdata <= X"00000000";
when 16#0005A# => romdata <= X"00000000";
when 16#0005B# => romdata <= X"00000000";
when 16#0005C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2004 GAISLER RESEARCH
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- See the file COPYING for the full details of the license.
--
-----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 9;
constant bytes : integer := 368;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hcache <= '1';
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= romdata;
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= romdata;
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"01000000";
when 16#00008# => romdata <= X"03002040";
when 16#00009# => romdata <= X"8210600F";
when 16#0000A# => romdata <= X"C2A00040";
when 16#0000B# => romdata <= X"87444000";
when 16#0000C# => romdata <= X"8608E01F";
when 16#0000D# => romdata <= X"88100000";
when 16#0000E# => romdata <= X"8A100000";
when 16#0000F# => romdata <= X"8C100000";
when 16#00010# => romdata <= X"8E100000";
when 16#00011# => romdata <= X"A0100000";
when 16#00012# => romdata <= X"A2100000";
when 16#00013# => romdata <= X"A4100000";
when 16#00014# => romdata <= X"A6100000";
when 16#00015# => romdata <= X"A8100000";
when 16#00016# => romdata <= X"AA100000";
when 16#00017# => romdata <= X"AC100000";
when 16#00018# => romdata <= X"AE100000";
when 16#00019# => romdata <= X"90100000";
when 16#0001A# => romdata <= X"92100000";
when 16#0001B# => romdata <= X"94100000";
when 16#0001C# => romdata <= X"96100000";
when 16#0001D# => romdata <= X"98100000";
when 16#0001E# => romdata <= X"9A100000";
when 16#0001F# => romdata <= X"9C100000";
when 16#00020# => romdata <= X"9E100000";
when 16#00021# => romdata <= X"86A0E001";
when 16#00022# => romdata <= X"16BFFFEF";
when 16#00023# => romdata <= X"81E00000";
when 16#00024# => romdata <= X"82102002";
when 16#00025# => romdata <= X"81904000";
when 16#00026# => romdata <= X"03000004";
when 16#00027# => romdata <= X"821060E0";
when 16#00028# => romdata <= X"81884000";
when 16#00029# => romdata <= X"01000000";
when 16#0002A# => romdata <= X"01000000";
when 16#0002B# => romdata <= X"01000000";
when 16#0002C# => romdata <= X"87444000";
when 16#0002D# => romdata <= X"8730E01C";
when 16#0002E# => romdata <= X"8688E00F";
when 16#0002F# => romdata <= X"12800016";
when 16#00030# => romdata <= X"03200000";
when 16#00031# => romdata <= X"05040E00";
when 16#00032# => romdata <= X"8410A233";
when 16#00033# => romdata <= X"C4204000";
when 16#00034# => romdata <= X"0539A81B";
when 16#00035# => romdata <= X"8410A260";
when 16#00036# => romdata <= X"C4206004";
when 16#00037# => romdata <= X"050003FC";
when 16#00038# => romdata <= X"C4206008";
when 16#00039# => romdata <= X"82103860";
when 16#0003A# => romdata <= X"C4004000";
when 16#0003B# => romdata <= X"8530A00C";
when 16#0003C# => romdata <= X"03000004";
when 16#0003D# => romdata <= X"82106009";
when 16#0003E# => romdata <= X"80A04002";
when 16#0003F# => romdata <= X"12800006";
when 16#00040# => romdata <= X"033FFC00";
when 16#00041# => romdata <= X"82106100";
when 16#00042# => romdata <= X"0539A81B";
when 16#00043# => romdata <= X"8410A260";
when 16#00044# => romdata <= X"C4204000";
when 16#00045# => romdata <= X"05000008";
when 16#00046# => romdata <= X"82100000";
when 16#00047# => romdata <= X"80A0E000";
when 16#00048# => romdata <= X"02800005";
when 16#00049# => romdata <= X"01000000";
when 16#0004A# => romdata <= X"82004002";
when 16#0004B# => romdata <= X"10BFFFFC";
when 16#0004C# => romdata <= X"8620E001";
when 16#0004D# => romdata <= X"3D1003FF";
when 16#0004E# => romdata <= X"BC17A3E0";
when 16#0004F# => romdata <= X"BC278001";
when 16#00050# => romdata <= X"9C27A060";
when 16#00051# => romdata <= X"03100000";
when 16#00052# => romdata <= X"81C04000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"01000000";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"00000000";
when 16#00059# => romdata <= X"00000000";
when 16#0005A# => romdata <= X"00000000";
when 16#0005B# => romdata <= X"00000000";
when 16#0005C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
architecture RTL of FIFO is
begin
-- These are passing
a <=
b or
d;
a <=
'0' when c = '0' else
'1' when d = '1' else
'Z';
-- Failing variations
a <=
b or
d;
a <=
'0' when c = '0' else
'1' when d = '1' else
'Z';
-- Arrays should be ignored
a <= (
b => 0,
c => 6
);
end architecture RTL;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- ============================================================================
-- Authors: Patrick Lehmann
--
-- Module: PicoBlaze System on FPGA (SoFPGA)
--
-- Description:
-- ------------------------------------
-- TODO
--
--
-- License:
-- ============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- ============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library UNISIM;
use UNISIM.VCOMPONENTS.all;
library PoC;
use PoC.my_project.MY_PROJECT_NAME;
use PoC.config.all;
use PoC.utils.all;
use PoC.vectors.all;
use PoC.strings.all;
use PoC.physical.all;
use PoC.io.all;
use PoC.xil.all;
library L_PicoBlaze;
use L_PicoBlaze.pb.all;
library L_Example;
use L_Example.pb_SoFPGA.all;
--use L_PicoBlaze.main_Page0_sim.all;
entity pb_SoFPGA_System is
generic (
DEBUG : BOOLEAN := TRUE;
CLOCK_FREQ : FREQ := 100 MHz;
EXTERNAL_DEVICE_COUNT : NATURAL := 1;
UART_BAUDRATE : BAUD := 115200 Bd;
ENABLE_JTAG_LOADER : BOOLEAN := TRUE;
ENABLE_SOFPGA_TRACER : BOOLEAN := TRUE;
ENABLE_UART_ILA : BOOLEAN := FALSE
);
port (
Clock : in STD_LOGIC;
ClockStable : in STD_LOGIC;
Reset : in STD_LOGIC;
CSP_ICON_ControlBus_Trace : inout T_XIL_CHIPSCOPE_CONTROL;
CSP_ICON_ControlBus_UART : inout T_XIL_CHIPSCOPE_CONTROL;
CSP_Tracer_TriggerEvent : out STD_LOGIC;
CSP_UART_TriggerEvent : out STD_LOGIC;
PicoBlazeBusOut : out T_PB_IOBUS_PB_DEV_VECTOR(EXTERNAL_DEVICE_COUNT - 1 downto 0);
PicoBlazeBusIn : in T_PB_IOBUS_DEV_PB_VECTOR(EXTERNAL_DEVICE_COUNT - 1 downto 0);
UART_TX : out STD_LOGIC;
UART_RX : in STD_LOGIC;
-- UARTFrame_TX_Valid : out STD_LOGIC;
-- UARTFrame_TX_Data : out T_SLV_8;
-- UARTFrame_TX_SOF : out STD_LOGIC;
-- UARTFrame_TX_EOF : out STD_LOGIC;
-- UARTFrame_TX_Ack : in STD_LOGIC;
--
-- UARTFrame_RX_Valid : in STD_LOGIC;
-- UARTFrame_RX_Data : in T_SLV_8;
-- UARTFrame_RX_SOF : in STD_LOGIC;
-- UARTFrame_RX_EOF : in STD_LOGIC;
-- UARTFrame_RX_Ack : out STD_LOGIC;
Raw_IIC_mux : out STD_LOGIC;
Raw_IIC_Clock_i : in STD_LOGIC;
Raw_IIC_Clock_t : out STD_LOGIC;
Raw_IIC_Data_i : in STD_LOGIC;
Raw_IIC_Data_t : out STD_LOGIC;
Raw_IIC_Switch_Reset : out STD_LOGIC
-- -- IICController_IIC interface
-- IIC1_Request : out STD_LOGIC;
-- IIC1_Grant : in STD_LOGIC;
--
-- IIC1_Command : out T_IO_IIC_COMMAND;
-- IIC1_Status : in T_IO_IIC_STATUS;
-- IIC1_Error : in T_IO_IIC_ERROR;
--
-- IIC1_Address : out STD_LOGIC_VECTOR(6 downto 0);
-- IIC1_WP_Valid : out STD_LOGIC;
-- IIC1_WP_Data : out T_SLV_8;
-- IIC1_WP_Last : out STD_LOGIC;
-- IIC1_WP_Ack : in STD_LOGIC;
-- IIC1_RP_Valid : in STD_LOGIC;
-- IIC1_RP_Data : in T_SLV_8;
-- IIC1_RP_Last : in STD_LOGIC;
-- IIC1_RP_Ack : out STD_LOGIC;
--
-- -- IICController_IIC interface
-- IIC2_Request : out STD_LOGIC;
-- IIC2_Grant : in STD_LOGIC;
--
-- IIC2_Command : out T_IO_IIC_COMMAND;
-- IIC2_Status : in T_IO_IIC_STATUS;
-- IIC2_Error : in T_IO_IIC_ERROR;
--
-- IIC2_Address : out STD_LOGIC_VECTOR(6 downto 0);
-- IIC2_WP_Valid : out STD_LOGIC;
-- IIC2_WP_Data : out T_SLV_8;
-- IIC2_WP_Last : out STD_LOGIC;
-- IIC2_WP_Ack : in STD_LOGIC;
-- IIC2_RP_Valid : in STD_LOGIC;
-- IIC2_RP_Data : in T_SLV_8;
-- IIC2_RP_Last : in STD_LOGIC;
-- IIC2_RP_Ack : out STD_LOGIC
);
end;
architecture rtl of pb_SoFPGA_System is
attribute KEEP : BOOLEAN;
constant PICOBLAZE_CLOCK_FREQ : FREQ := CLOCK_FREQ;
constant SOURCE_DIRECTORY : STRING := PROJECT_DIR & "psm/" & MY_PROJECT_NAME & "/";
constant ROM_PAGES : POSITIVE := 2;
constant ANY_PB_IOBUS_PORTS : NATURAL := pb_GetBusWidth(SOFPGA_SYSTEM, "Any");
constant INTERN_PB_IOBUS_PORTS : NATURAL := pb_GetBusWidth(SOFPGA_SYSTEM, "Intern");
constant EXTERN_PB_IOBUS_PORTS : NATURAL := pb_GetBusWidth(SOFPGA_SYSTEM, "Extern");
signal Any_PicoBlazeDeviceBus : T_PB_IOBUS_PB_DEV_VECTOR(ANY_PB_IOBUS_PORTS - 1 downto 0) := (others => T_PB_IOBUS_PB_DEV_Z);
signal Any_DevicePicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR(ANY_PB_IOBUS_PORTS - 1 downto 0) := (others => T_PB_IOBUS_DEV_PB_Z);
signal Intern_PicoBlazeDeviceBus : T_PB_IOBUS_PB_DEV_VECTOR(INTERN_PB_IOBUS_PORTS - 1 downto 0) := (others => T_PB_IOBUS_PB_DEV_Z);
signal Intern_DevicePicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR(INTERN_PB_IOBUS_PORTS - 1 downto 0) := (others => T_PB_IOBUS_DEV_PB_Z);
signal Extern_PicoBlazeDeviceBus : T_PB_IOBUS_PB_DEV_VECTOR(EXTERN_PB_IOBUS_PORTS - 1 downto 0) := (others => T_PB_IOBUS_PB_DEV_Z);
signal Extern_DevicePicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR(EXTERN_PB_IOBUS_PORTS - 1 downto 0) := (others => T_PB_IOBUS_DEV_PB_Z);
signal SoFPGA_Reset : STD_LOGIC;
signal CPU_Clock : STD_LOGIC;
signal CPU_ClockStable : STD_LOGIC;
signal CPU_Reset : STD_LOGIC;
signal CPU_Reset_i : STD_LOGIC;
signal PB_Sleep : STD_LOGIC;
signal PB_InstructionFetch : STD_LOGIC;
signal PB_InstructionFetch_d : STD_LOGIC := '0';
signal PB_InstructionPointer : T_SLV_12;
signal PB_PortID : T_SLV_8;
signal PB_ReadStrobe : STD_LOGIC;
signal PB_WriteStrobe : STD_LOGIC;
signal PB_WriteStrobe_k : STD_LOGIC;
signal PB_DataIn : T_SLV_8;
signal PB_DataOut : T_SLV_8;
signal PB_Interrupt_Ack : STD_LOGIC;
attribute KEEP of PB_PortID : signal is DEBUG;
attribute KEEP of PB_ReadStrobe : signal is DEBUG;
attribute KEEP of PB_WriteStrobe : signal is DEBUG;
attribute KEEP of PB_DataIn : signal is DEBUG;
attribute KEEP of PB_DataOut : signal is DEBUG;
signal PicoBlazeDeviceBus : T_PB_IOBUS_PB_DEV_VECTOR(ANY_PB_IOBUS_PORTS - 1 downto 0);
-- Instruction ROM
signal ROM_Instruction : STD_LOGIC_VECTOR(17 downto 0);
signal ROM_RebootCPU : STD_LOGIC;
signal DBG_PageNumber : STD_LOGIC_VECTOR(2 downto 0);
-- Interrupt Controller
signal IntC_Interrupt : STD_LOGIC;
-- Reset Circuit
signal UART_Reset : STD_LOGIC;
signal IICC1_Reset : STD_LOGIC;
signal IICC2_Reset : STD_LOGIC;
signal FreqM_Reset : STD_LOGIC;
signal CSP_Trigger : STD_LOGIC;
attribute KEEP of CSP_Trigger : signal is TRUE;
-- Accelerators
signal Accelerator_Clear : STD_LOGIC;
-- UART
-- signal CSP_ICON_ControlBus_UART : T_XIL_CHIPSCOPE_CONTROL;
begin
CPU_Clock <= Clock;
CPU_ClockStable <= ClockStable;
CPU_Reset <= Reset or SoFPGA_Reset or not CPU_ClockStable;
CPU_Reset_i <= CPU_Reset or ROM_RebootCPU;
PB_Sleep <= '0';
PicoBlaze : entity L_PicoBlaze.KCPSM6
generic map (
hwbuild => x"00",
interrupt_vector => x"FE0",
scratch_pad_memory_size => 256
)
port map (
clk => CPU_Clock,
reset => CPU_Reset_i,
sleep => PB_Sleep,
bram_enable => PB_InstructionFetch,
address => PB_InstructionPointer,
instruction => ROM_Instruction,
port_id => PB_PortID,
read_strobe => PB_ReadStrobe,
write_strobe => PB_WriteStrobe,
k_write_strobe => PB_WriteStrobe_k,
out_port => PB_DataOut,
in_port => PB_DataIn,
interrupt => IntC_Interrupt,
interrupt_ack => open
);
-- new interrupt ack signal on RETURNI instruction
PB_InstructionFetch_d <= PB_InstructionFetch when rising_edge(CPU_Clock);
PB_Interrupt_Ack <= PB_InstructionFetch_d and
(to_sl("00" & ROM_Instruction = x"29000") or
to_sl("00" & ROM_Instruction = x"29001"));
genPBDevBus : for i in Any_PicoBlazeDeviceBus'range generate
Any_PicoBlazeDeviceBus(i).PortID <= PB_PortID;
Any_PicoBlazeDeviceBus(i).Data <= PB_DataOut;
Any_PicoBlazeDeviceBus(i).WriteStrobe <= PB_WriteStrobe;
Any_PicoBlazeDeviceBus(i).WriteStrobe_K <= PB_WriteStrobe_K;
Any_PicoBlazeDeviceBus(i).ReadStrobe <= PB_ReadStrobe;
end generate;
Intern_PicoBlazeDeviceBus <= pb_GetSubOrdinateBus(Any_PicoBlazeDeviceBus, SOFPGA_SYSTEM, "Intern");
Extern_PicoBlazeDeviceBus <= pb_GetSubOrdinateBus(Any_PicoBlazeDeviceBus, SOFPGA_SYSTEM, "Extern");
PicoBlazeBusOut <= Extern_PicoBlazeDeviceBus;
Extern_DevicePicoBlazeBus <= PicoBlazeBusIn;
pb_AssignSubOrdinateBus(Any_DevicePicoBlazeBus, Intern_DevicePicoBlazeBus, SOFPGA_SYSTEM, "Intern");
pb_AssignSubOrdinateBus(Any_DevicePicoBlazeBus, Extern_DevicePicoBlazeBus, SOFPGA_SYSTEM, "Extern");
-- genSim : IF SIMULATION GENERATE
-- signal PB_FunctionName : T_PB_FUNCTIONS;
-- BEGIN
-- PB_FunctionName <= InstructionPointer2FunctionName(PB_InstructionPointer);
-- END GENERATE;
-- instruction ROM
blkROM : block
constant DEV_SHORT : STRING := "InstROM";
constant BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DEV_SHORT);
constant DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DEV_SHORT);
begin
ROM : entity L_PicoBlaze.pb_InstructionROM_Device
generic map (
PAGES => ROM_PAGES,
SOURCE_DIRECTORY => SOURCE_DIRECTORY,
DEVICE_INSTANCE => DEVICE_INST,
ENABLE_JTAG_LOADER => ENABLE_JTAG_LOADER
)
port map (
Clock => CPU_Clock,
Fetch => PB_InstructionFetch,
InstructionPointer => PB_InstructionPointer(11 downto 0),
Instruction => ROM_Instruction,
Reboot => ROM_RebootCPU,
-- PicoBlaze interface
Address => Intern_PicoBlazeDeviceBus(BUSINDEX).PortID,
WriteStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe,
WriteStrobe_K => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe_K,
ReadStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).ReadStrobe,
DataIn => Intern_PicoBlazeDeviceBus(BUSINDEX).Data,
DataOut => Intern_DevicePicoBlazeBus(BUSINDEX).Data,
Interrupt => Intern_DevicePicoBlazeBus(BUSINDEX).Interrupt,
Interrupt_Ack => Intern_PicoBlazeDeviceBus(BUSINDEX).Interrupt_Ack,
Message => Intern_DevicePicoBlazeBus(BUSINDEX).Message,
PageNumber => DBG_PageNumber
);
end block;
-- PB_DataIn multiplexer
blkDataInMux : block
function getDeviceMappingInBus(System : T_PB_SYSTEM; BusID : T_PB_BUSID) return T_NATVEC is
variable BusIndex : NATURAL;
variable Result : T_NATVEC(0 to System.DeviceInstanceCount-1);
variable CurBus : T_PB_BUS := System.Busses(BusID);
variable SubBusID : T_PB_BUSID;
variable SubResult : T_NATVEC(0 to System.DeviceInstanceCount-1);
begin
BusIndex := 0;
assert not PB_VERBOSE report "DEVINBUS: Enter " & integer'image(BusID) severity note;
for i in 0 to CurBus.SubBusCount-1 loop
SubBusID := CurBus.SubBusses(i);
SubResult := getDeviceMappingInBus(System, SubBusID);
for j in 0 to System.Busses(SubBusID).TotalDeviceCount-1 loop
Result(BusIndex) := SubResult(j);
assert not PB_VERBOSE report "DEVINBUS: Result(" & integer'image(BusIndex) & ") := " & integer'image(SubResult(j)) severity note;
BusIndex := BusIndex+1;
end loop;
end loop;
for i in 0 to CurBus.DeviceCount-1 loop
Result(BusIndex) := CurBus.Devices(i); -- DeviceID
assert not PB_VERBOSE report "DEVINBUS: Result(" & integer'image(BusIndex) & ") := " & integer'image(CurBus.Devices(i)) severity note;
BusIndex := BusIndex+1;
end loop;
assert not PB_VERBOSE report "DEVINBUS: Exit " & integer'image(BusID) severity note;
return Result;
end function;
function swapKeyValue(Input : T_NATVEC) return T_NATVEC is
variable Result : T_NATVEC(Input'range);
begin
for i in Input'range loop
Result(Input(i)) := i;
end loop;
return Result;
end function;
constant DevMappingInAnyBus : T_NATVEC := getDeviceMappingInBus(SoFPGA_System, 0);
constant PositionInsideAnyBus : T_NATVEC := swapKeyValue(DevMappingInAnyBus);
function toMuxVector(DevicePicoBlazeBus : T_PB_IOBUS_DEV_PB_VECTOR; System : T_PB_SYSTEM) return T_SLVV_8 is
variable Result : T_SLVV_8(127 downto 0) := (others => (others => '-'));
variable DeviceInstance : T_PB_DEVICE_INSTANCE;
variable Mapping : T_PB_PORTNUMBER_MAPPING;
begin
for i in 0 to System.DeviceInstanceCount - 1 loop
DeviceInstance := System.DeviceInstances(i);
for j in DeviceInstance.Mappings'range loop
Mapping := DeviceInstance.Mappings(j);
if (Mapping.MappingKind = PB_MAPPING_KIND_READ) then
Result(Mapping.PortNumber) := DevicePicoBlazeBus(PositionInsideAnyBus(i)).Data;
assert not PB_VERBOSE report "MUXIN: PortNumber = " & integer'image(Mapping.PortNumber) & ", AnyBusID = " & integer'image(PositionInsideAnyBus(i)) severity note;
end if;
end loop;
end loop;
return Result;
end function;
signal DataIn_MuxVector : T_SLVV_8(127 downto 0);
begin
DataIn_MuxVector <= toMuxVector(Any_DevicePicoBlazeBus, SOFPGA_SYSTEM);
process(CPU_Clock)
begin
if rising_edge(CPU_Clock) then
PB_DataIn <= DataIn_MuxVector(to_index(PB_PortID(log2ceilnz(DataIn_MuxVector'length) - 1 downto 0)));
end if;
end process;
end block;
genCSP : if (ENABLE_SOFPGA_TRACER = TRUE) generate
signal Tracer_DataIn : STD_LOGIC_VECTOR(62 downto 0);
signal Tracer_Trigger0 : STD_LOGIC_VECTOR(14 downto 0);
signal Tracer_Trigger1 : T_SLV_8;
signal Tracer_Trigger2 : STD_LOGIC_VECTOR(5 downto 0);
signal Tracer_Trigger3 : T_SLV_16;
signal Tracer_DataIn_d : STD_LOGIC_VECTOR(62 downto 0) := (others => '0');
signal Tracer_Trigger0_d : STD_LOGIC_VECTOR(14 downto 0) := (others => '0');
signal Tracer_Trigger1_d : T_SLV_8 := (others => '0');
signal Tracer_Trigger2_d : STD_LOGIC_VECTOR(5 downto 0) := (others => '0');
signal Tracer_Trigger3_d : T_SLV_16 := (others => '0');
begin
Tracer_DataIn(11 downto 0) <= PB_InstructionPointer;
Tracer_DataIn(29 downto 12) <= ROM_Instruction;
Tracer_DataIn(37 downto 30) <= PB_PortID;
Tracer_DataIn(45 downto 38) <= PB_DataOut;
Tracer_DataIn(53 downto 46) <= PB_DataIn;
Tracer_DataIn(54) <= PB_WriteStrobe;
Tracer_DataIn(55) <= PB_WriteStrobe_K;
Tracer_DataIn(56) <= PB_ReadStrobe;
Tracer_DataIn(57) <= IntC_Interrupt;
Tracer_DataIn(58) <= ROM_RebootCPU;
Tracer_DataIn(59) <= CSP_Trigger;
Tracer_DataIn(62 downto 60) <= DBG_PageNumber(2 downto 0);
Tracer_Trigger0(11 downto 0) <= PB_InstructionPointer;
Tracer_Trigger0(14 downto 12) <= DBG_PageNumber(2 downto 0);
Tracer_Trigger1 <= PB_PortID;
Tracer_Trigger2(0) <= PB_WriteStrobe;
Tracer_Trigger2(1) <= PB_WriteStrobe_K;
Tracer_Trigger2(2) <= PB_ReadStrobe;
Tracer_Trigger2(3) <= IntC_Interrupt;
Tracer_Trigger2(4) <= ROM_RebootCPU;
Tracer_Trigger2(5) <= CSP_Trigger;
Tracer_Trigger3(7 downto 0) <= PB_DataOut;
Tracer_Trigger3(15 downto 8) <= PB_DataIn;
Tracer_DataIn_d <= Tracer_DataIn when rising_edge(CPU_Clock);
Tracer_Trigger0_d <= Tracer_Trigger0 when rising_edge(CPU_Clock);
Tracer_Trigger1_d <= Tracer_Trigger1 when rising_edge(CPU_Clock);
Tracer_Trigger2_d <= Tracer_Trigger2 when rising_edge(CPU_Clock);
Tracer_Trigger3_d <= Tracer_Trigger3 when rising_edge(CPU_Clock);
Tracer : entity L_PicoBlaze.CSP_PB_Tracer_ILA
port map (
CONTROL => CSP_ICON_ControlBus_Trace,
CLK => CPU_Clock,
DATA => Tracer_DataIn_d,
TRIG0 => Tracer_Trigger0_d,
TRIG1 => Tracer_Trigger1_d,
TRIG2 => Tracer_Trigger2_d,
TRIG3 => Tracer_Trigger3_d,
TRIG_OUT => CSP_Tracer_TriggerEvent
);
end generate;
-- Reset registers
blkReset : block
constant DEV_SHORT : STRING := "Reset";
constant BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DEV_SHORT);
constant DEVICE_INSTANCE : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DEV_SHORT);
signal AdrDec_we : STD_LOGIC;
signal AdrDec_re : STD_LOGIC;
signal AdrDec_WriteAddress : T_SLV_8;
signal AdrDec_ReadAddress : T_SLV_8;
signal AdrDec_Data : T_SLV_8;
signal Reset_d : T_SLV_8 := (others => '0');
begin
AdrDec : entity L_PicoBlaze.PicoBlaze_AddressDecoder
generic map (
DEVICE_NAME => str_trim(DEVICE_INSTANCE.DeviceShort),
BUS_NAME => str_trim(DEVICE_INSTANCE.BusShort),
READ_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_READ),
WRITE_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITE),
WRITEK_MAPPINGS => pb_FilterMappings(DEVICE_INSTANCE, PB_MAPPING_KIND_WRITEK)
)
port map (
Clock => CPU_Clock,
Reset => CPU_Reset_i,
-- PicoBlaze interface
In_WriteStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe,
In_WriteStrobe_K => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe_K,
In_ReadStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).ReadStrobe,
In_Address => Intern_PicoBlazeDeviceBus(BUSINDEX).PortID,
In_Data => Intern_PicoBlazeDeviceBus(BUSINDEX).Data,
Out_WriteStrobe => AdrDec_we,
Out_ReadStrobe => open, --AdrDec_re,
Out_WriteAddress => open, --AdrDec_WriteAddress,
Out_ReadAddress => open, --AdrDec_ReadAddress,
Out_Data => AdrDec_Data
);
Intern_DevicePicoBlazeBus(BUSINDEX).Interrupt <= '0';
Intern_DevicePicoBlazeBus(BUSINDEX).Message <= x"00";
process(CPU_Clock)
begin
if rising_edge(CPU_Clock) then
if (AdrDec_we = '1') then
Reset_d <= AdrDec_Data;
else
Reset_d <= (others => '0');
end if;
end if;
end process;
Accelerator_Clear <= Reset_d(0);
UART_Reset <= Reset_d(1);
-- free <= Reset_d(2);
IICC1_Reset <= Reset_d(3);
IICC2_Reset <= Reset_d(3);
-- free <= Reset_d(4);
-- free <= Reset_d(5);
SoFPGA_Reset <= Reset_d(6);
CSP_Trigger <= Reset_d(7);
end block;
-- interrupt controller
blkInterrupt : block
constant DEV_SHORT : STRING := "IntC";
constant BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DEV_SHORT);
constant DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DEV_SHORT);
constant INTC_PORTS : POSITIVE := pb_GetInterruptCount(SOFPGA_SYSTEM);
signal Interrupt_Vector : STD_LOGIC_VECTOR(INTC_PORTS - 1 downto 0);
signal Interrupt_Messages : T_SLVV_8(INTC_PORTS - 1 downto 0);
signal IntC_Interrupt_Ack : STD_LOGIC_VECTOR(INTC_PORTS - 1 downto 0);
begin
IntC : entity L_PicoBlaze.pb_InterruptController_Device
generic map (
DEBUG => DEBUG,
DEVICE_INSTANCE => DEVICE_INST,
PORTS => INTC_PORTS
)
port map (
Clock => CPU_Clock,
Reset => CPU_Reset_i,
-- PicoBlaze interface
Address => Intern_PicoBlazeDeviceBus(BUSINDEX).PortID,
WriteStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe,
WriteStrobe_K => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe_K,
ReadStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).ReadStrobe,
DataIn => Intern_PicoBlazeDeviceBus(BUSINDEX).Data,
DataOut => Intern_DevicePicoBlazeBus(BUSINDEX).Data,
Interrupt => Intern_DevicePicoBlazeBus(BUSINDEX).Interrupt,
Interrupt_Ack => Intern_PicoBlazeDeviceBus(BUSINDEX).Interrupt_Ack,
Message => Intern_DevicePicoBlazeBus(BUSINDEX).Message,
-- PicoBlaze interrupt interface (direct coupled)
PB_Interrupt => IntC_Interrupt,
PB_Interrupt_Ack => PB_Interrupt_Ack,
-- Interrupt source interface
Dev_Interrupt => Interrupt_Vector,
Dev_Interrupt_Ack => IntC_Interrupt_Ack,
Dev_Interrupt_Message => Interrupt_Messages
);
-- wire PicoBlaze bus 'any' to the InterruptController
Interrupt_Vector <= pb_GetInterruptVector(Any_DevicePicoBlazeBus, SOFPGA_SYSTEM);
Interrupt_Messages <= pb_GetInterruptMessages(Any_DevicePicoBlazeBus, SOFPGA_SYSTEM);
pb_AssignInterruptAck(Any_PicoBlazeDeviceBus, IntC_Interrupt_Ack, SOFPGA_SYSTEM);
end block;
-- blkTimer : block
-- constant DEV_SHORT : STRING := "Timer";
-- constant BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DEV_SHORT);
-- constant DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DEV_SHORT);
--
-- begin
-- Timer : entity L_PicoBlaze.pb_Timer
-- generic map (
-- DEVICE_INSTANCE => DEVICE_INST
-- )
-- port map (
-- Clock => CPU_Clock,
-- Reset => CPU_Reset_i,
--
-- -- PicoBlaze interface
-- Address => Intern_PicoBlazeDeviceBus(BUSINDEX).PortID,
-- WriteStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe,
-- WriteStrobe_K => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe_K,
-- ReadStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).ReadStrobe,
-- DataIn => Intern_PicoBlazeDeviceBus(BUSINDEX).Data,
-- DataOut => Intern_DevicePicoBlazeBus(BUSINDEX).Data,
--
-- Interrupt => Intern_DevicePicoBlazeBus(BUSINDEX).Interrupt,
-- Interrupt_Ack => Intern_PicoBlazeDeviceBus(BUSINDEX).Interrupt_Ack,
-- Message => Intern_DevicePicoBlazeBus(BUSINDEX).Message,
--
-- EventIn => "00001"
-- );
-- end block;
blkAccellerator : block
constant MULT_SHORT : STRING := "Mult32";
constant MULT_BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, MULT_SHORT);
constant MULT_DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, MULT_SHORT);
constant DIV_SHORT : STRING := "Div32";
constant DIV_BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DIV_SHORT);
constant DIV_DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DIV_SHORT);
constant BCD_SHORT : STRING := "ConvBCD24";
constant BCD_BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, BCD_SHORT);
constant BCD_DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, BCD_SHORT);
signal Mult_Reset : STD_LOGIC;
signal Div_Reset : STD_LOGIC;
signal BCD_Reset : STD_LOGIC;
begin
Mult_Reset <= CPU_Reset or Accelerator_Clear;
Div_Reset <= CPU_Reset or Accelerator_Clear;
BCD_Reset <= CPU_Reset or Accelerator_Clear;
Mult : entity L_PicoBlaze.pb_Multiplier_Device
generic map (
DEVICE_INSTANCE => MULT_DEVICE_INST,
BITS => 32
)
port map (
Clock => CPU_Clock,
Reset => Mult_Reset,
-- PicoBlaze interface
Address => Intern_PicoBlazeDeviceBus(MULT_BUSINDEX).PortID,
WriteStrobe => Intern_PicoBlazeDeviceBus(MULT_BUSINDEX).WriteStrobe,
WriteStrobe_K => Intern_PicoBlazeDeviceBus(MULT_BUSINDEX).WriteStrobe_K,
ReadStrobe => Intern_PicoBlazeDeviceBus(MULT_BUSINDEX).ReadStrobe,
DataIn => Intern_PicoBlazeDeviceBus(MULT_BUSINDEX).Data,
DataOut => Intern_DevicePicoBlazeBus(MULT_BUSINDEX).Data,
Interrupt => Intern_DevicePicoBlazeBus(MULT_BUSINDEX).Interrupt,
Interrupt_Ack => Intern_PicoBlazeDeviceBus(MULT_BUSINDEX).Interrupt_Ack,
Message => Intern_DevicePicoBlazeBus(MULT_BUSINDEX).Message
);
Div : entity L_PicoBlaze.pb_Divider_Device
generic map (
DEVICE_INSTANCE => DIV_DEVICE_INST,
BITS => 32
)
port map (
Clock => CPU_Clock,
Reset => Div_Reset,
-- PicoBlaze interface
Address => Intern_PicoBlazeDeviceBus(DIV_BUSINDEX).PortID,
WriteStrobe => Intern_PicoBlazeDeviceBus(DIV_BUSINDEX).WriteStrobe,
WriteStrobe_K => Intern_PicoBlazeDeviceBus(DIV_BUSINDEX).WriteStrobe_K,
ReadStrobe => Intern_PicoBlazeDeviceBus(DIV_BUSINDEX).ReadStrobe,
DataIn => Intern_PicoBlazeDeviceBus(DIV_BUSINDEX).Data,
DataOut => Intern_DevicePicoBlazeBus(DIV_BUSINDEX).Data,
Interrupt => Intern_DevicePicoBlazeBus(DIV_BUSINDEX).Interrupt,
Interrupt_Ack => Intern_PicoBlazeDeviceBus(DIV_BUSINDEX).Interrupt_Ack,
Message => Intern_DevicePicoBlazeBus(DIV_BUSINDEX).Message
);
ConvBCD : entity L_PicoBlaze.pb_ConverterBCD24_Device
generic map (
DEVICE_INSTANCE => BCD_DEVICE_INST
)
port map (
Clock => CPU_Clock,
Reset => BCD_Reset,
-- PicoBlaze interface
Address => Intern_PicoBlazeDeviceBus(BCD_BUSINDEX).PortID,
WriteStrobe => Intern_PicoBlazeDeviceBus(BCD_BUSINDEX).WriteStrobe,
WriteStrobe_K => Intern_PicoBlazeDeviceBus(BCD_BUSINDEX).WriteStrobe_K,
ReadStrobe => Intern_PicoBlazeDeviceBus(BCD_BUSINDEX).ReadStrobe,
DataIn => Intern_PicoBlazeDeviceBus(BCD_BUSINDEX).Data,
DataOut => Intern_DevicePicoBlazeBus(BCD_BUSINDEX).Data,
Interrupt => Intern_DevicePicoBlazeBus(BCD_BUSINDEX).Interrupt,
Interrupt_Ack => Intern_PicoBlazeDeviceBus(BCD_BUSINDEX).Interrupt_Ack,
Message => Intern_DevicePicoBlazeBus(BCD_BUSINDEX).Message
);
end block;
blkGPIO : block
constant DEV_SHORT : STRING := "GPIO";
constant BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DEV_SHORT);
constant DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DEV_SHORT);
signal GPIO_DataIn : T_SLV_8;
signal GPIO_DataOut : T_SLV_8;
begin
GPIO : entity L_PicoBlaze.pb_GPIO_Adapter
generic map (
DEVICE_INSTANCE => DEVICE_INST
)
port map (
Clock => CPU_Clock,
Reset => '0',
-- PicoBlaze interface
Address => Intern_PicoBlazeDeviceBus(BUSINDEX).PortID,
WriteStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe,
WriteStrobe_K => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe_K,
ReadStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).ReadStrobe,
DataIn => Intern_PicoBlazeDeviceBus(BUSINDEX).Data,
DataOut => Intern_DevicePicoBlazeBus(BUSINDEX).Data,
Interrupt => Intern_DevicePicoBlazeBus(BUSINDEX).Interrupt,
Interrupt_Ack => Intern_PicoBlazeDeviceBus(BUSINDEX).Interrupt_Ack,
Message => Intern_DevicePicoBlazeBus(BUSINDEX).Message,
GPIO_Out => GPIO_DataOut,
GPIO_In => GPIO_DataIn
);
GPIO_DataIn <= x"00";
-- Raw_LCD_mux <= GPIO_DataOut(0);
-- Raw_UART_mux <= GPIO_DataOut(1);
Raw_IIC_mux <= GPIO_DataOut(2);
Raw_IIC_Switch_Reset <= GPIO_DataOut(7);
end block;
blkBBIO : block
constant DEV_SHORT : STRING := "BBIO8";
constant BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DEV_SHORT);
constant DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DEV_SHORT);
constant BBID_IIC_CLOCK : NATURAL := 0;
constant BBID_IIC_DATA : NATURAL := 1;
constant BITS : POSITIVE := 2;
constant INITIAL_VALUE : STD_LOGIC_VECTOR(BITS - 1 downto 0) := (
BBID_IIC_CLOCK => '1', -- set IIC Clock to Tri-State by default (-> Pullup, Idle state)
BBID_IIC_DATA => '1', -- set IIC Data to Tri-State by default (-> Pullup, Idle state)
others => '0'
);
signal BBIO_DataIn : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal BBIO_DataOut : STD_LOGIC_VECTOR(BITS - 1 downto 0);
begin
BBIO : entity L_PicoBlaze.pb_BitBangingIO_Device
generic map (
DEVICE_INSTANCE => DEVICE_INST,
BITS => BITS,
INITIAL_VALUE => INITIAL_VALUE
)
port map (
Clock => CPU_Clock,
Reset => CPU_Reset,
-- PicoBlaze interface
Address => Intern_PicoBlazeDeviceBus(BUSINDEX).PortID,
WriteStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe,
WriteStrobe_K => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe_K,
ReadStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).ReadStrobe,
DataIn => Intern_PicoBlazeDeviceBus(BUSINDEX).Data,
DataOut => Intern_DevicePicoBlazeBus(BUSINDEX).Data,
Interrupt => Intern_DevicePicoBlazeBus(BUSINDEX).Interrupt,
Interrupt_Ack => Intern_PicoBlazeDeviceBus(BUSINDEX).Interrupt_Ack,
Message => Intern_DevicePicoBlazeBus(BUSINDEX).Message,
BBIO_Out => BBIO_DataOut,
BBIO_In => BBIO_DataIn
);
BBIO_DataIn(BBID_IIC_CLOCK) <= Raw_IIC_Clock_i;
BBIO_DataIn(BBID_IIC_DATA) <= Raw_IIC_Data_i;
Raw_IIC_Clock_t <= BBIO_DataOut(BBID_IIC_CLOCK);
Raw_IIC_Data_t <= BBIO_DataOut(BBID_IIC_DATA);
end block;
blkUART : block
constant DEV_SHORT : STRING := "UART";
constant BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DEV_SHORT);
constant DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DEV_SHORT);
begin
UART : entity L_PicoBlaze.pb_UART_Wrapper
generic map (
DEBUG => DEBUG,
ENABLE_CHIPSCOPE => ENABLE_UART_ILA,
CLOCK_FREQ => CLOCK_FREQ,
DEVICE_INSTANCE => DEVICE_INST,
BAUDRATE => UART_BAUDRATE
)
port map (
Clock => CPU_Clock,
Reset => UART_Reset,
-- PicoBlaze interface
Address => Intern_PicoBlazeDeviceBus(BUSINDEX).PortID,
WriteStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe,
WriteStrobe_K => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe_K,
ReadStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).ReadStrobe,
DataIn => Intern_PicoBlazeDeviceBus(BUSINDEX).Data,
DataOut => Intern_DevicePicoBlazeBus(BUSINDEX).Data,
Interrupt => Intern_DevicePicoBlazeBus(BUSINDEX).Interrupt,
Interrupt_Ack => Intern_PicoBlazeDeviceBus(BUSINDEX).Interrupt_Ack,
Message => Intern_DevicePicoBlazeBus(BUSINDEX).Message,
ICON_ControlBus => CSP_ICON_ControlBus_UART,
UART_TX => UART_TX,
UART_RX => UART_RX
);
end block;
-- blkIIC : block
-- constant IICC1_DEV_SHORT : STRING := "IICCtrl1";
-- constant IICC1_BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, IICC1_DEV_SHORT);
-- constant IICC1_DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, IICC1_DEV_SHORT);
--
-- constant IICC2_DEV_SHORT : STRING := "IICCtrl2";
-- constant IICC2_BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, IICC2_DEV_SHORT);
-- constant IICC2_DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, IICC2_DEV_SHORT);
-- begin
-- IICC1 : entity L_PicoBlaze.pb_IICController_Adapter
-- generic map (
-- DEBUG => DEBUG,
-- ALLOW_MEALY_TRANSITION => FALSE,
-- DEVICE_INSTANCE => IICC1_DEVICE_INST
-- )
-- port map(
-- Clock => CPU_Clock,
-- Reset => IICC1_Reset,
--
-- -- PicoBlaze interface
-- Address => Intern_PicoBlazeDeviceBus(IICC1_BUSINDEX).PortID,
-- WriteStrobe => Intern_PicoBlazeDeviceBus(IICC1_BUSINDEX).WriteStrobe,
-- WriteStrobe_K => Intern_PicoBlazeDeviceBus(IICC1_BUSINDEX).WriteStrobe_K,
-- ReadStrobe => Intern_PicoBlazeDeviceBus(IICC1_BUSINDEX).ReadStrobe,
-- DataIn => Intern_PicoBlazeDeviceBus(IICC1_BUSINDEX).Data,
-- DataOut => Intern_DevicePicoBlazeBus(IICC1_BUSINDEX).Data,
--
-- Interrupt => Intern_DevicePicoBlazeBus(IICC1_BUSINDEX).Interrupt,
-- Interrupt_Ack => Intern_PicoBlazeDeviceBus(IICC1_BUSINDEX).Interrupt_Ack,
-- Message => Intern_DevicePicoBlazeBus(IICC1_BUSINDEX).Message,
--
-- -- IICController_IIC interface
-- IIC_Request => IIC1_Request,
-- IIC_Grant => IIC1_Grant,
--
-- IIC_Command => IIC1_Command,
-- IIC_Status => IIC1_Status,
-- IIC_Error => IIC1_Error,
--
-- IIC_Address => IIC1_Address,
-- IIC_WP_Valid => IIC1_WP_Valid,
-- IIC_WP_Data => IIC1_WP_Data,
-- IIC_WP_Last => IIC1_WP_Last,
-- IIC_WP_Ack => IIC1_WP_Ack,
-- IIC_RP_Valid => IIC1_RP_Valid,
-- IIC_RP_Data => IIC1_RP_Data,
-- IIC_RP_Last => IIC1_RP_Last,
-- IIC_RP_Ack => IIC1_RP_Ack
-- );
--
-- IICC2 : entity L_PicoBlaze.pb_IICController_Adapter
-- generic map (
-- DEBUG => DEBUG,
-- ALLOW_MEALY_TRANSITION => FALSE,
-- DEVICE_INSTANCE => IICC2_DEVICE_INST
-- )
-- port map(
-- Clock => CPU_Clock,
-- Reset => IICC2_Reset,
--
-- -- PicoBlaze interface
-- Address => Intern_PicoBlazeDeviceBus(IICC2_BUSINDEX).PortID,
-- WriteStrobe => Intern_PicoBlazeDeviceBus(IICC2_BUSINDEX).WriteStrobe,
-- WriteStrobe_K => Intern_PicoBlazeDeviceBus(IICC2_BUSINDEX).WriteStrobe_K,
-- ReadStrobe => Intern_PicoBlazeDeviceBus(IICC2_BUSINDEX).ReadStrobe,
-- DataIn => Intern_PicoBlazeDeviceBus(IICC2_BUSINDEX).Data,
-- DataOut => Intern_DevicePicoBlazeBus(IICC2_BUSINDEX).Data,
--
-- Interrupt => Intern_DevicePicoBlazeBus(IICC2_BUSINDEX).Interrupt,
-- Interrupt_Ack => Intern_PicoBlazeDeviceBus(IICC2_BUSINDEX).Interrupt_Ack,
-- Message => Intern_DevicePicoBlazeBus(IICC2_BUSINDEX).Message,
--
-- -- IICController_IIC interface
-- IIC_Request => IIC2_Request,
-- IIC_Grant => IIC2_Grant,
--
-- IIC_Command => IIC2_Command,
-- IIC_Status => IIC2_Status,
-- IIC_Error => IIC2_Error,
--
-- IIC_Address => IIC2_Address,
-- IIC_WP_Valid => IIC2_WP_Valid,
-- IIC_WP_Data => IIC2_WP_Data,
-- IIC_WP_Last => IIC2_WP_Last,
-- IIC_WP_Ack => IIC2_WP_Ack,
-- IIC_RP_Valid => IIC2_RP_Valid,
-- IIC_RP_Data => IIC2_RP_Data,
-- IIC_RP_Last => IIC2_RP_Last,
-- IIC_RP_Ack => IIC2_RP_Ack
-- );
-- end block;
-- blkFreqM : block
-- constant DEV_SHORT : STRING := "FreqM";
-- constant BUSINDEX : NATURAL := pb_GetBusIndex(SOFPGA_SYSTEM, DEV_SHORT);
-- constant DEVICE_INST : T_PB_DEVICE_INSTANCE := pb_GetDeviceInstance(SOFPGA_SYSTEM, DEV_SHORT);
-- begin
-- FreqM_Reset <= CPU_Reset;
--
-- FreqM : entity L_PicoBlaze.pb_FrequencyMeasurement_Wrapper
-- generic map (
-- REFERENCE_CLOCK_FREQ => PICOBLAZE_CLOCK_FREQ,
-- DEVICE_INSTANCE => DEVICE_INST
-- )
-- port map (
-- Clock => CPU_Clock,
-- Reset => FreqM_Reset,
--
-- -- PicoBlaze interface
-- Address => Intern_PicoBlazeDeviceBus(BUSINDEX).PortID,
-- WriteStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe,
-- WriteStrobe_K => Intern_PicoBlazeDeviceBus(BUSINDEX).WriteStrobe_K,
-- ReadStrobe => Intern_PicoBlazeDeviceBus(BUSINDEX).ReadStrobe,
-- DataIn => Intern_PicoBlazeDeviceBus(BUSINDEX).Data,
-- DataOut => Intern_DevicePicoBlazeBus(BUSINDEX).Data,
--
-- Interrupt => open,
-- Interrupt_Ack => '0',
-- Message => open,
--
-- ClockIn => FreqM_ClockIn
-- );
--
-- Intern_DevicePicoBlazeBus(BUSINDEX).Interrupt <= '0';
-- Intern_DevicePicoBlazeBus(BUSINDEX).Message <= x"00";
-- end block;
end;
|
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral; |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral; |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral; |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral; |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral; |
-- CTRL_InAB_INPUT
-- Einlesen des Datenstroms von InAB und Ausgabe als Einzelnes Bit, sowie Signalisierung das Byte komplet
-- Projekt: PROFIBUS MONITOR
-- Ersteller: Martin Harndt
-- Erstellt: 09.10.2012
-- Bearbeiter: mharndt
-- Geaendert: 29.01.2013
-- Umstellung auf: rising_edge(CLK) und falling_edge(CLK) und http://www.sigasi.com/content/clock-edge-detection
-- Optimierungen aus: http://www.lothar-miller.de/s9y/categories/37-FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity CTRL_InAB_INPUT_VHDL is
Port (InAB : in std_logic; --Eingangsvariable, Eingang Profibussignal
CHOSE_VALUE : in std_logic; --Eingangsvariable, Zählerwert aendern
EN_BIT_i : out std_logic_vector (8 downto 0); --Ausgangsvariable, Enable Bit i, 9bit
BIT_VALUE : out std_logic; --Ausgangsvariable, Bitwert
BYTE_CMPLT: out std_logic; --Ausgangsvariabel, Byte empfangen und komplett
PAUSE_END : out std_logic; --Ausgangssignal, Pause zu Ende
CLK : in std_logic; --Taktvariable
-- CLK_IO : in std_logic; --Tanktvariable,
--Ein- und Ausgangsregister
IN_NEXT_STATE: in std_logic; --1:Zustandsuebergang möglich
RESET : in std_logic; --1: Initialzustand annehmen
DISPL1_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl1, binärzahl
DISPL2_SV : out std_logic_vector (3 downto 0); --aktueller Zustand Zahl2, binärzahl
DISPL1_n_SV : out std_logic_vector (3 downto 0); --Folgezustand Zahl1, binärzahl
DISPL2_n_SV : out std_logic_vector (3 downto 0)); --Folgezustand Zahl2, binärzahl
end CTRL_InAB_INPUT_VHDL;
architecture Behavioral of CTRL_InAB_INPUT_VHDL is
type TYPE_STATE is
(ST_CTRL_00, --Zustaende CTRL_9P6_50MHZ
ST_CTRL_01,
ST_CTRL_02,
ST_CTRL_03,
ST_CTRL_04,
ST_CTRL_05,
ST_CTRL_06,
ST_CTRL_07,
ST_CTRL_08,
ST_CTRL_09,
ST_CTRL_0A, --10
ST_CTRL_0B, --11
ST_CTRL_0C, --12
ST_CTRL_0D, --13
ST_CTRL_0E, --14
ST_CTRL_0F);--15
signal SV : TYPE_STATE := ST_CTRL_00; --Zustandsvariable
signal n_SV: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, neuer Wert
signal SV_M: TYPE_STATE := ST_CTRL_00; --Zustandsvariable, Ausgang Master
signal COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Vektor, 20 Bit
signal n_COUNT_L : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, neuer Wert, Vektor, 20 Bit
signal COUNT_L_M : std_logic_vector (19 downto 0) := x"00000"; --großer Zaehler, Ausgang Master, Vektor, 20 Bit
signal COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Vektor, 16 Bit
signal n_COUNT_S : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, neuer Wert, Vektor, 16 Bit
signal COUNT_S_M : std_logic_vector (15 downto 0) := x"0000"; --kleiner Zaehler, Ausgang Master, Vektor, 16 Bit
signal InAB_S : std_logic := '0'; --Eingangsvariable
--Zwischengespeichert im Eingangsregister
--signal not_CLK : std_logic; --negierte Taktvariable
--signal not_CLK_IO: std_logic; --negierte Taktvariable
--Ein- und Ausgangsregister
signal STATE_SV : std_logic_vector (7 downto 0); -- aktueller Zustand in 8 Bit, binär
signal STATE_n_SV : std_logic_vector (7 downto 0); -- Folgezustand in 8 Bit, binär
signal EN_BIT_0 : std_logic := '0'; --BIT0
signal EN_BIT_1 : std_logic := '0'; --BIT1
signal EN_BIT_2 : std_logic := '0'; --BIT2
signal EN_BIT_3 : std_logic := '0'; --BIT3
signal EN_BIT_4 : std_logic := '0'; --BIT4
signal EN_BIT_5 : std_logic := '0'; --BIT5
signal EN_BIT_6 : std_logic := '0'; --BIT6
signal EN_BIT_7 : std_logic := '0'; --BIT7
signal EN_BIT_8 : std_logic := '0'; --Paritätsbit
signal CNTS30 : std_logic_vector (19 downto 0) := x"00000"; --Zählerwerte
signal CNTT01 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT02 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT03 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT04 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT05 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT06 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT07 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT08 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT09 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT10 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT11 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT12 : std_logic_vector (15 downto 0) := x"0000";
signal CNTT13 : std_logic_vector (15 downto 0) := x"0000";
--Konstanten, lang
constant long_CNTS30 : std_logic_vector := x"2625A"; --20 Bit
constant long_CNTT01 : std_logic_vector := x"0A2C"; --16 Bit
constant long_CNTT02 : std_logic_vector := x"1E84"; --usw.
constant long_CNTT03 : std_logic_vector := x"32DC";
constant long_CNTT04 : std_logic_vector := x"4735";
constant long_CNTT05 : std_logic_vector := x"5B8B";
constant long_CNTT06 : std_logic_vector := x"6FE4";
constant long_CNTT07 : std_logic_vector := x"8441";
constant long_CNTT08 : std_logic_vector := x"9872";
constant long_CNTT09 : std_logic_vector := x"ACEE";
constant long_CNTT10 : std_logic_vector := x"C147";
constant long_CNTT11 : std_logic_vector := x"D59F";
constant long_CNTT12 : std_logic_vector := x"D9B1";
constant long_CNTT13 : std_logic_vector := x"E5E6";
--Konstanten, kurz
constant short_CNTS30 : std_logic_vector := x"0000A"; --10
constant short_CNTT01 : std_logic_vector := x"0003"; --3
constant short_CNTT02 : std_logic_vector := x"0006"; --6
constant short_CNTT03 : std_logic_vector := x"0009"; --9
constant short_CNTT04 : std_logic_vector := x"000C"; --12
constant short_CNTT05 : std_logic_vector := x"000F"; --15
constant short_CNTT06 : std_logic_vector := x"0012"; --18
constant short_CNTT07 : std_logic_vector := x"0015"; --21
constant short_CNTT08 : std_logic_vector := x"0018"; --24
constant short_CNTT09 : std_logic_vector := x"001B"; --27
constant short_CNTT10 : std_logic_vector := x"001E"; --30
constant short_CNTT11 : std_logic_vector := x"0021"; --33
constant short_CNTT12 : std_logic_vector := x"0024"; --36
constant short_CNTT13 : std_logic_vector := x"002A"; --42
begin
--NOT_CLK_PROC: process (CLK) --negieren Taktvariable
--begin
-- not_CLK <= not CLK;
--end process;
---NOT_CLK_IO_PROC: process (CLK_IO) --negieren Taktvaraible
--Ein- und Ausgangsregister
--begin
-- not_CLK_IO <= not CLK_IO;
--end process;
IREG_PROC: process (InAB, InAB_S, CLK) --Eingangsregister
begin
if falling_edge(CLK) --Eingangsregister
then InAB_S <= InAB;
end if;
end process;
SREG_M_PROC: process (RESET, n_SV, n_COUNT_L,n_COUNT_S, CLK) --Master
begin
if (RESET ='1')
then SV_M <= ST_CTRL_00;
COUNT_L_M <= x"00000";
COUNT_S_M <= x"0000";
else
if rising_edge(CLK)
then
if (IN_NEXT_STATE = '1')
then SV_M <= n_SV;
COUNT_L_M <= n_COUNT_L;
COUNT_S_M <= n_COUNT_S;
else SV_M <= SV_M;
COUNT_L_M <= COUNT_L_M;
COUNT_S_M <= COUNT_S_M;
end if;
end if;
end if;
end process;
SREG_S_PROC: process (RESET, SV_M, COUNT_L_M, COUNT_S_M, CLK) --Slave
begin
if (RESET = '1')
then SV <= ST_CTRL_00;
COUNT_L <= x"00000";
COUNT_S <= x"0000";
else
if falling_edge(CLK)
then SV <= SV_M;
COUNT_L <= COUNT_L_M;
COUNT_S <= COUNT_S_M;
end if;
end if;
end process;
IL_OL_PROC: process (InAB_S, SV, COUNT_L,COUNT_S, CNTS30, CNTT01, CNTT02, CNTT03, CNTT04, CNTT05, CNTT06, CNTT07, CNTT08, CNTT09, CNTT10, CNTT11, CNTT12, CNTT13)
begin
case SV is
when ST_CTRL_00 =>
if (InAB_S = '1')
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler Neustart
n_COUNT_S <= x"0000"; -- kleiner Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; -- Zustandsuebgergang
else
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- großer Zaehler nullen
n_COUNT_S <= x"0000"; -- kleiner Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; --InAB = '0'
end if;
when ST_CTRL_01 =>
if (InAB_S = '1')
then
if (COUNT_L = CNTS30) --156250 -- if (COUNT >=3)
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; -- Zustandsuebgergang
else --not COUNT_L = CNTS30
--VAS01
PAUSE_END <= '0';
n_COUNT_L <= COUNT_L+1;
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_01; --Zaehlschleife
end if;
else --InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Zustandsuebgergang
end if;
when ST_CTRL_02 =>
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '1';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
else -- InAB_S = '1'
--VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_02; --warte ab bis InAB wieder NUll wird
end if;
when ST_CTRL_03 =>
if (COUNT_S = CNTT01) --2604
then
if (InAB_S = '0') -- Startbit erkannt
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; -- Zustandsuebgergang
else --InAB_S = '1'
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= x"0000";
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end if;
else
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when ST_CTRL_04 =>
if (COUNT_S = CNTT02) --7812
then
-- VAS04
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '1';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; -- Zustandsuebgergang
else --n_COUNT < CNTT02
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_04; --Zaehlschleife
end if;
when ST_CTRL_05 =>
if (COUNT_S = CNTT03) --13020
then
-- VAS05
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '1';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; -- Zustandsuebgergang
else --n_COUNT < CNTT03
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_05; --Zaehlschleife
end if;
when ST_CTRL_06 =>
if (COUNT_S = CNTT04) --18229
then
-- VAS06
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '1';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; -- Zustandsuebgergang
else --n_COUNT < CNTT04
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_06; --Zaehlschleife
end if;
when ST_CTRL_07 =>
if (COUNT_S = CNTT05) --23435
then
-- VAS07
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '1';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; -- Zustandsuebgergang
else --n_COUNT < CNTT05
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_07; --Zaehlschleife
end if;
when ST_CTRL_08 =>
if (COUNT_S = CNTT06) --28644
then
-- VAS08
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '1';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; -- Zustandsuebgergang
else --n_COUNT < CNTT06
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_08; --Zaehlschleife
end if;
when ST_CTRL_09 =>
if (COUNT_S = CNTT07) --33854
then
-- VAS09
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '1';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; -- Zustandsuebgergang
else --n_COUNT < CNTT07
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_09; --Zaehlschleife
end if;
when ST_CTRL_0A =>
if (COUNT_S = CNTT08) --39062
then
-- VAS10
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '1';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; -- Zustandsuebgergang
else --n_COUNT < CNTT08
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0A; --Zaehlschleife
end if;
when ST_CTRL_0B =>
if (COUNT_S = CNTT09) --44270
then
-- VAS11
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '1';
EN_BIT_8 <= '0';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; -- Zustandsuebgergang
else --n_COUNT < CNTT09
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0B; --Zaehlschleife
end if;
when ST_CTRL_0C =>
if (COUNT_S = CNTT10) --49479
then
-- VAS12
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '1';
BIT_VALUE <= InAB_S;
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; -- Zustandsuebgergang
else --n_COUNT < CNTT10
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0C; --Zaehlschleife
end if;
when ST_CTRL_0D =>
if (COUNT_S = CNTT11) --54687
then
if (InAB_S = '0')
then
-- VAS03
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Error: Kein Stoppbit, vormals ST_CTRL_05
else --InAB_S = '1'
-- VAS13
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '1';
n_SV <= ST_CTRL_0E; --Stoppbit erkannt
end if; --InAB_S = '0'
else --not COUNT_S = CNTT11
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0D; --Zaehlschleife
end if; --COUNT_S = CNTT11
when ST_CTRL_0E =>
if (COUNT_S = CNTT12) --60937
then
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; -- Zustandsuebgergang
else -- n_COUNT < CNTT12
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0E; --Zaehlschleife
end if;
when ST_CTRL_0F =>
if (InAB_S = '1') --Startbot bisher ncoh nicht gefunden
then
if (COUNT_S = CNTT13) --64062
then
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler nullen
n_COUNT_S <= x"0000"; -- Zaehler nullen
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00; -- Kein Startbit gefunden (neues SYN?)
else --not COUNT_S = CNTT13
-- VAS02
PAUSE_END <= '0';
n_COUNT_L <= x"00000";
n_COUNT_S <= COUNT_S+1;
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_0F; --Zaehlschleife
end if; --COUNT_S = CNTT13
else --InAB_S = '0'
-- Startbit gefunden
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_03; -- Zustandsuebgergang
end if;
when others =>
-- VAS00
PAUSE_END <= '0';
n_COUNT_L <= x"00000"; -- Zaehler Neustart
n_COUNT_S <= x"0000"; -- Zaehler Neustart
EN_BIT_0 <= '0';
EN_BIT_1 <= '0';
EN_BIT_2 <= '0';
EN_BIT_3 <= '0';
EN_BIT_4 <= '0';
EN_BIT_5 <= '0';
EN_BIT_6 <= '0';
EN_BIT_7 <= '0';
EN_BIT_8 <= '0';
BIT_VALUE <= '0';
BYTE_CMPLT <= '0';
n_SV <= ST_CTRL_00;
end case;
end process;
--BYTE_IN_PROC: process (EN_BIT_0, EN_BIT_1, EN_BIT_2, EN_BIT_3, EN_BIT_4, EN_BIT_5, EN_BIT_6, EN_BIT_7, EN_BIT_8) --Umwandlung einzelnes Bit EIN_BIT_0_S bis 8_S in Vector EN_BIT_i
-- begin
EN_BIT_i(0) <= EN_BIT_0;
EN_BIT_i(1) <= EN_BIT_1;
EN_BIT_i(2) <= EN_BIT_2;
EN_BIT_i(3) <= EN_BIT_3;
EN_BIT_i(4) <= EN_BIT_4;
EN_BIT_i(5) <= EN_BIT_5;
EN_BIT_i(6) <= EN_BIT_6;
EN_BIT_i(7) <= EN_BIT_7;
EN_BIT_i(8) <= EN_BIT_8;
--end process;
STATE_DISPL_PROC: process (SV, n_SV, STATE_SV, STATE_n_SV) -- Zustandsanzeige
begin
STATE_SV <= conv_std_logic_vector(TYPE_STATE'pos( SV),8); --Zustandsumwandlung in 8 Bit
STATE_n_SV <= conv_std_logic_vector(TYPE_STATE'pos(n_SV),8);
DISPL1_SV(0) <= STATE_SV(0); --Bit0
DISPL1_SV(1) <= STATE_SV(1); --Bit1
DISPL1_SV(2) <= STATE_SV(2); --Bit2
DISPL1_SV(3) <= STATE_SV(3); --Bit3
DISPL2_SV(0) <= STATE_SV(4); --usw.
DISPL2_SV(1) <= STATE_SV(5);
DISPL2_SV(2) <= STATE_SV(6);
DISPL2_SV(3) <= STATE_SV(7);
--Folgezustand anzeigen
DISPL1_n_SV(0) <= STATE_n_SV(0);
DISPL1_n_SV(1) <= STATE_n_SV(1);
DISPL1_n_SV(2) <= STATE_n_SV(2);
DISPL1_n_SV(3) <= STATE_n_SV(3);
DISPL2_n_SV(0) <= STATE_n_SV(4);
DISPL2_n_SV(1) <= STATE_n_SV(5);
DISPL2_n_SV(2) <= STATE_n_SV(6);
DISPL2_n_SV(3) <= STATE_n_SV(7);
end process;
SWITCH_VALUES_PROC: process (CHOSE_VALUE) --Schaltet zw. langen und kurzem Zaehler um
begin
if (CHOSE_VALUE = '0')
then
--normale Werte
CNTS30 <= long_CNTS30;
CNTT01 <= long_CNTT01;
CNTT02 <= long_CNTT02;
CNTT03 <= long_CNTT03;
CNTT04 <= long_CNTT04;
CNTT05 <= long_CNTT05;
CNTT06 <= long_CNTT06;
CNTT07 <= long_CNTT07;
CNTT08 <= long_CNTT08;
CNTT09 <= long_CNTT09;
CNTT10 <= long_CNTT10;
CNTT11 <= long_CNTT11;
CNTT12 <= long_CNTT12;
CNTT13 <= long_CNTT13;
else
--kurze Werte
CNTS30 <= short_CNTS30;
CNTT01 <= short_CNTT01;
CNTT02 <= short_CNTT02;
CNTT03 <= short_CNTT03;
CNTT04 <= short_CNTT04;
CNTT05 <= short_CNTT05;
CNTT06 <= short_CNTT06;
CNTT07 <= short_CNTT07;
CNTT08 <= short_CNTT08;
CNTT09 <= short_CNTT09;
CNTT10 <= short_CNTT10;
CNTT11 <= short_CNTT11;
CNTT12 <= short_CNTT12;
CNTT13 <= short_CNTT13;
end if;
end process;
end Behavioral; |
package ppkg1 is
type line is access string;
procedure rep1 (variable msg : line := new string (1 to 7));
procedure rep2;
procedure rep3;
end ppkg1;
package body ppkg is
procedure rep1 (msg : line := new string (1 to 7)) is
begin
msg.all := (others => ' ');
end rep1;
procedure rep2 is
begin
rep1;
rep1;
end rep2;
procedure rep3 is
begin
rep1;
end rep3;
end ppkg;
|
package ppkg1 is
type line is access string;
procedure rep1 (variable msg : line := new string (1 to 7));
procedure rep2;
procedure rep3;
end ppkg1;
package body ppkg is
procedure rep1 (msg : line := new string (1 to 7)) is
begin
msg.all := (others => ' ');
end rep1;
procedure rep2 is
begin
rep1;
rep1;
end rep2;
procedure rep3 is
begin
rep1;
end rep3;
end ppkg;
|
-- file: clk_video_clk_wiz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___193.158______0.000______50.0______236.796____297.965
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_video_clk_wiz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_193MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_video_clk_wiz;
architecture xilinx of clk_video_clk_wiz is
-- Input clock buffering / unused connectors
signal clk_100MHz_clk_video : std_logic;
-- Output clock buffering / unused connectors
signal clkfbout_clk_video : std_logic;
signal clkfbout_buf_clk_video : std_logic;
signal clkfboutb_unused : std_logic;
signal clk_193MHz_clk_video : std_logic;
signal clkout0b_unused : std_logic;
signal clkout1_unused : std_logic;
signal clkout1b_unused : std_logic;
signal clkout2_unused : std_logic;
signal clkout2b_unused : std_logic;
signal clkout3_unused : std_logic;
signal clkout3b_unused : std_logic;
signal clkout4_unused : std_logic;
signal clkout5_unused : std_logic;
signal clkout6_unused : std_logic;
-- Dynamic programming unused signals
signal do_unused : std_logic_vector(15 downto 0);
signal drdy_unused : std_logic;
-- Dynamic phase shift unused signals
signal psdone_unused : std_logic;
signal locked_int : std_logic;
-- Unused status signals
signal clkfbstopped_unused : std_logic;
signal clkinstopped_unused : std_logic;
begin
-- Input buffering
--------------------------------------
clkin1_bufg : BUFG
port map
(O => clk_100MHz_clk_video,
I => clk_100MHz);
-- Clocking PRIMITIVE
--------------------------------------
-- Instantiation of the MMCM PRIMITIVE
-- * Unused inputs are tied off
-- * Unused outputs are labeled unused
mmcm_adv_inst : MMCME2_ADV
generic map
(BANDWIDTH => "OPTIMIZED",
CLKOUT4_CASCADE => FALSE,
COMPENSATION => "ZHOLD",
STARTUP_WAIT => FALSE,
DIVCLK_DIVIDE => 5,
CLKFBOUT_MULT_F => 45.875,
CLKFBOUT_PHASE => 0.000,
CLKFBOUT_USE_FINE_PS => FALSE,
CLKOUT0_DIVIDE_F => 4.750,
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT0_USE_FINE_PS => FALSE,
CLKIN1_PERIOD => 10.0,
REF_JITTER1 => 0.010)
port map
-- Output clocks
(
CLKFBOUT => clkfbout_clk_video,
CLKFBOUTB => clkfboutb_unused,
CLKOUT0 => clk_193MHz_clk_video,
CLKOUT0B => clkout0b_unused,
CLKOUT1 => clkout1_unused,
CLKOUT1B => clkout1b_unused,
CLKOUT2 => clkout2_unused,
CLKOUT2B => clkout2b_unused,
CLKOUT3 => clkout3_unused,
CLKOUT3B => clkout3b_unused,
CLKOUT4 => clkout4_unused,
CLKOUT5 => clkout5_unused,
CLKOUT6 => clkout6_unused,
-- Input clock control
CLKFBIN => clkfbout_buf_clk_video,
CLKIN1 => clk_100MHz_clk_video,
CLKIN2 => '0',
-- Tied to always select the primary input clock
CLKINSEL => '1',
-- Ports for dynamic reconfiguration
DADDR => (others => '0'),
DCLK => '0',
DEN => '0',
DI => (others => '0'),
DO => do_unused,
DRDY => drdy_unused,
DWE => '0',
-- Ports for dynamic phase shift
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
PSDONE => psdone_unused,
-- Other control and status signals
LOCKED => locked_int,
CLKINSTOPPED => clkinstopped_unused,
CLKFBSTOPPED => clkfbstopped_unused,
PWRDWN => '0',
RST => '0');
locked <= locked_int;
-- Output buffering
-------------------------------------
clkf_buf : BUFG
port map
(O => clkfbout_buf_clk_video,
I => clkfbout_clk_video);
clkout1_buf : BUFG
port map
(O => clk_193MHz,
I => clk_193MHz_clk_video);
end xilinx;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HeRhTr is
Port ( clk : in STD_LOGIC;
reset:in STD_LOGIC;
sd_in: in STD_LOGIC;
sd_out:out STD_LOGIC;
TbmHeader:out STD_LOGIC;
RocHeader:out STD_LOGIC;
TbmTrailer:out STD_LOGIC;
TP:out STD_LOGIC;
TPP:out STD_LOGIC;
allowRocH:out STD_LOGIC);
end HeRhTr;
architecture Behaviorial of HeRhTr is
--signal
signal s_1: STD_LOGIC:='0';
signal s_2: STD_LOGIC:='0';
signal s_3: STD_LOGIC:='0';
signal s_4: STD_LOGIC:='0';
signal s_5: STD_LOGIC:='0';
signal s_6: STD_LOGIC:='0';
signal s_7: STD_LOGIC:='0';
signal s_8: STD_LOGIC:='0';
signal s_9: STD_LOGIC:='0';
signal s_10: STD_LOGIC:='0';
signal s_11: STD_LOGIC:='0';
signal s_12: STD_LOGIC:='0';
signal s_13: STD_LOGIC:='0';
signal s_d1: STD_LOGIC:='0';
signal s_d2: STD_LOGIC:='0';
signal s_d3: STD_LOGIC:='0';
signal s_d4: STD_LOGIC:='0';
signal s_d5: STD_LOGIC:='0';
signal s_d6: STD_LOGIC:='0';
signal s_d7: STD_LOGIC:='0';
signal s_d8: STD_LOGIC:='0';
signal s_d9: STD_LOGIC:='0';
signal s_d10: STD_LOGIC:='0';
signal s_d11: STD_LOGIC:='0';
signal s_d12: STD_LOGIC:='0';
signal s_d13: STD_LOGIC:='0';
signal s_d14: STD_LOGIC:='0';
signal s_d15: STD_LOGIC:='0';
signal s_d16: STD_LOGIC:='0';
signal s_HEADER: STD_LOGIC:='0';
signal s_ROC: STD_LOGIC:='0';
signal s_TRAILER: STD_LOGIC:='0';
signal s_DataWindow: STD_LOGIC:='0';
signal s_count: STD_LOGIC_VECTOR (3 downto 0):="0000";
signal s_TC: STD_LOGIC:='0';
begin
------------------------------------------------------------
p_pipe: process (clk)
begin
if (rising_edge(clk)) then
s_1 <= sd_in;
s_2 <= s_1;
s_3 <= s_2;
s_4 <= s_3;
s_5 <= s_4;
s_6 <= s_5;
s_7 <= s_6;
s_8 <= s_7;
s_9 <= s_8;
s_10 <= s_9;
s_11 <= s_10;
s_12 <= s_11;
s_13 <= s_12;
end if;
end process p_pipe;
sd_out <= s_13;
------------------------------------------------------------
s_HEADER <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and s_2
and (not s_1) and (not sd_in) );
s_ROC <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and (not s_2)
and s_d15 and s_DataWindow);
s_TRAILER <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and s_2
and s_1 and sd_in );
------------------------------------------------------------
p_DataWindow: process (clk, reset)
begin
if (reset = '1') then
s_DataWindow <= '0';
elsif (rising_edge(clk)) then
if ( s_HEADER = '1') then
s_DataWindow <= '1';
elsif ( s_TRAILER = '1') then
s_DataWindow <= '0';
end if;
end if;
end process p_DataWindow;
TP <= s_DataWindow;
------------------------------------------------------------
p_Mod12Cnt: process (clk)
begin
if (rising_edge(clk)) then
if (s_DataWindow = '1') then --count
if (s_count= "1011") then
s_count <= "0000";
s_TC <='1';
else
s_count <= s_count +1;
s_TC <='0';
end if;
else -- do not count
s_count <= "0000";
s_TC <='0';
end if;
end if;
end process p_Mod12Cnt;
TPP <= s_TC;
------------------------------------------------------------
p_delay: process (clk)
begin
if (rising_edge(clk)) then
s_d1 <= s_TC;
s_d2 <= s_d1;
s_d3 <= s_d2;
s_d4 <= s_d3;
s_d5 <= s_d4;
s_d6 <= s_d5;
s_d7 <= s_d6;
s_d8 <= s_d7;
s_d9 <= s_d8;
s_d10 <= s_d9;
s_d11 <= s_d10;
s_d12 <= s_d11;
s_d13 <= s_d12;
s_d14 <= s_d13;
s_d15 <= s_d14;
s_d16 <= s_d15;
end if;
end process p_delay;
allowRocH <= s_d16;
------------------------------------------------------------
p_output_registers : process (clk)
begin
if (rising_edge(clk)) then
TbmHeader <= s_HEADER;
RocHeader <= s_ROC;
TbmTrailer <= s_TRAILER;
end if;
end process p_output_registers;
------------------------------------------------------------
end;--Behavioral |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity HeRhTr is
Port ( clk : in STD_LOGIC;
reset:in STD_LOGIC;
sd_in: in STD_LOGIC;
sd_out:out STD_LOGIC;
TbmHeader:out STD_LOGIC;
RocHeader:out STD_LOGIC;
TbmTrailer:out STD_LOGIC;
TP:out STD_LOGIC;
TPP:out STD_LOGIC;
allowRocH:out STD_LOGIC);
end HeRhTr;
architecture Behaviorial of HeRhTr is
--signal
signal s_1: STD_LOGIC:='0';
signal s_2: STD_LOGIC:='0';
signal s_3: STD_LOGIC:='0';
signal s_4: STD_LOGIC:='0';
signal s_5: STD_LOGIC:='0';
signal s_6: STD_LOGIC:='0';
signal s_7: STD_LOGIC:='0';
signal s_8: STD_LOGIC:='0';
signal s_9: STD_LOGIC:='0';
signal s_10: STD_LOGIC:='0';
signal s_11: STD_LOGIC:='0';
signal s_12: STD_LOGIC:='0';
signal s_13: STD_LOGIC:='0';
signal s_d1: STD_LOGIC:='0';
signal s_d2: STD_LOGIC:='0';
signal s_d3: STD_LOGIC:='0';
signal s_d4: STD_LOGIC:='0';
signal s_d5: STD_LOGIC:='0';
signal s_d6: STD_LOGIC:='0';
signal s_d7: STD_LOGIC:='0';
signal s_d8: STD_LOGIC:='0';
signal s_d9: STD_LOGIC:='0';
signal s_d10: STD_LOGIC:='0';
signal s_d11: STD_LOGIC:='0';
signal s_d12: STD_LOGIC:='0';
signal s_d13: STD_LOGIC:='0';
signal s_d14: STD_LOGIC:='0';
signal s_d15: STD_LOGIC:='0';
signal s_d16: STD_LOGIC:='0';
signal s_HEADER: STD_LOGIC:='0';
signal s_ROC: STD_LOGIC:='0';
signal s_TRAILER: STD_LOGIC:='0';
signal s_DataWindow: STD_LOGIC:='0';
signal s_count: STD_LOGIC_VECTOR (3 downto 0):="0000";
signal s_TC: STD_LOGIC:='0';
begin
------------------------------------------------------------
p_pipe: process (clk)
begin
if (rising_edge(clk)) then
s_1 <= sd_in;
s_2 <= s_1;
s_3 <= s_2;
s_4 <= s_3;
s_5 <= s_4;
s_6 <= s_5;
s_7 <= s_6;
s_8 <= s_7;
s_9 <= s_8;
s_10 <= s_9;
s_11 <= s_10;
s_12 <= s_11;
s_13 <= s_12;
end if;
end process p_pipe;
sd_out <= s_13;
------------------------------------------------------------
s_HEADER <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and s_2
and (not s_1) and (not sd_in) );
s_ROC <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and (not s_2)
and s_d15 and s_DataWindow);
s_TRAILER <= ( (not s_11) and s_10 and s_9 and s_8 and s_7
and s_6 and s_5 and s_4 and s_3 and s_2
and s_1 and sd_in );
------------------------------------------------------------
p_DataWindow: process (clk, reset)
begin
if (reset = '1') then
s_DataWindow <= '0';
elsif (rising_edge(clk)) then
if ( s_HEADER = '1') then
s_DataWindow <= '1';
elsif ( s_TRAILER = '1') then
s_DataWindow <= '0';
end if;
end if;
end process p_DataWindow;
TP <= s_DataWindow;
------------------------------------------------------------
p_Mod12Cnt: process (clk)
begin
if (rising_edge(clk)) then
if (s_DataWindow = '1') then --count
if (s_count= "1011") then
s_count <= "0000";
s_TC <='1';
else
s_count <= s_count +1;
s_TC <='0';
end if;
else -- do not count
s_count <= "0000";
s_TC <='0';
end if;
end if;
end process p_Mod12Cnt;
TPP <= s_TC;
------------------------------------------------------------
p_delay: process (clk)
begin
if (rising_edge(clk)) then
s_d1 <= s_TC;
s_d2 <= s_d1;
s_d3 <= s_d2;
s_d4 <= s_d3;
s_d5 <= s_d4;
s_d6 <= s_d5;
s_d7 <= s_d6;
s_d8 <= s_d7;
s_d9 <= s_d8;
s_d10 <= s_d9;
s_d11 <= s_d10;
s_d12 <= s_d11;
s_d13 <= s_d12;
s_d14 <= s_d13;
s_d15 <= s_d14;
s_d16 <= s_d15;
end if;
end process p_delay;
allowRocH <= s_d16;
------------------------------------------------------------
p_output_registers : process (clk)
begin
if (rising_edge(clk)) then
TbmHeader <= s_HEADER;
RocHeader <= s_ROC;
TbmTrailer <= s_TRAILER;
end if;
end process p_output_registers;
------------------------------------------------------------
end;--Behavioral |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity verzoegerung is
port(
CLK, START : in std_logic;
STOP : in std_logic; -- Aufgabe 2
ALARM : out std_logic
);
end entity;
architecture behaviour of verzoegerung is
signal z : unsigned(2 downto 0) := "000";
begin
ALARM <= '1' when z = "100" else '0'; -- Ausgang
process(CLK)
begin
if rising_edge(CLK) then
-- if STOP = '1' then -- synchroner Reset (Aufgabe 2), für Afgabe 2 unkommentieren
-- z <= "000";
else
case z is
when "000" => -- Startzustand
if START = '1' then
z <= "001";
end if;
when "001" | "010" | "011" => -- Wartezustaende
z <= z + 1;
when "100" => -- Alarmzustand
if START = '0' then
z <= "000";
end if;
when others =>
end case;
-- end if; -- für Aufgabe 2 unkommentieren
end if;
end process;
end architecture;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
wait;
end process;
end only;
|
entity test is
end test;
architecture only of test is
begin -- only
doit: process
constant string_constant : string := "init";
begin -- process
assert string_constant(1) = 'i' REPORT "string_constant(1) not properly intialized" SEVERITY FAILURE;
assert string_constant(2) = 'n' REPORT "string_constant(2) not properly intialized" SEVERITY FAILURE;
assert string_constant(3) = 'i' REPORT "string_constant(3) not properly intialized" SEVERITY FAILURE;
assert string_constant(4) = 't' REPORT "string_constant(4) not properly intialized" SEVERITY FAILURE;
wait;
end process;
end only;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 21:28:51 05/22/2011
-- Design Name:
-- Module Name: /home/xiadz/prog/fpga/oscilloscope/test_trace_memory.vhd
-- Project Name: oscilloscope
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: trace_memory
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
ENTITY test_trace_memory IS
END test_trace_memory;
ARCHITECTURE behavior OF test_trace_memory IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT trace_memory
PORT(
clka : IN std_logic;
wea : IN std_logic_vector(0 downto 0);
addra : IN std_logic_vector(12 downto 0);
dina : IN std_logic_vector(8 downto 0);
clkb : IN std_logic;
rstb : IN std_logic;
addrb : IN std_logic_vector(12 downto 0);
doutb : OUT std_logic_vector(8 downto 0)
);
END COMPONENT;
--Inputs
signal clka : std_logic := '0';
signal wea : std_logic_vector(0 downto 0) := (others => '0');
signal addra : std_logic_vector(12 downto 0) := (others => '0');
signal dina : std_logic_vector(8 downto 0) := (others => '0');
signal clkb : std_logic := '0';
signal rstb : std_logic := '0';
signal addrb : std_logic_vector(12 downto 0) := (others => '0');
--Outputs
signal doutb : std_logic_vector(8 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: trace_memory PORT MAP (
clka => clka,
wea => wea,
addra => addra,
dina => dina,
clkb => clkb,
rstb => rstb,
addrb => addrb,
doutb => doutb
);
clk_process :process
begin
clka <= '0';
clkb <= '0';
wait for clk_period/2;
clka <= '1';
clkb <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
variable i: integer;
begin
-- hold reset state for 100 ns.
rstb <= '1';
wait for 100 ns;
rstb <= '0';
wait for clk_period * 10;
addra <= "0000000000000";
dina <= "010101101";
wea <= "1";
wait for clk_period;
wea <= "0";
wait for clk_period * 10;
wea <= "1";
for i in 0 to 20 loop
dina <= conv_std_logic_vector (i, 9);
addra <= conv_std_logic_vector (i, 13);
wait for clk_period;
end loop;
wea <= "0";
wait for clk_period * 10;
for i in 0 to 20 loop
addrb <= conv_std_logic_vector (i, 13);
wait for clk_period;
end loop;
wait;
end process;
END;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
library work;
use work.BusMasters.all;
entity ADT7310P32S16_tb is
end ADT7310P32S16_tb;
architecture behavior of ADT7310P32S16_tb is
component ADT7310P32S16
port (
Reset_n_i : in std_logic;
Clk_i : in std_logic;
Enable_i : in std_logic;
CpuIntr_o : out std_logic;
ADT7310CS_n_o : out std_logic;
SPI_Data_i : in std_logic_vector(7 downto 0);
SPI_Write_o : out std_logic;
SPI_ReadNext_o : out std_logic;
SPI_Data_o : out std_logic_vector(7 downto 0);
SPI_FIFOFull_i : in std_logic;
SPI_FIFOEmpty_i : in std_logic;
SPI_Transmission_i : in std_logic;
SPICounterPreset_i : in std_logic_vector(15 downto 0);
Threshold_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetH_i : in std_logic_vector(15 downto 0);
PeriodCounterPresetL_i : in std_logic_vector(15 downto 0);
SensorValue_o : out std_logic_vector(15 downto 0);
SPI_CPOL_o : out std_logic;
SPI_CPHA_o : out std_logic;
SPI_LSBFE_o : out std_logic
);
end component;
component adt7310_model
port (
SCLK_i : in std_logic;
DOUT_o : out std_logic;
DIN_i : in std_logic;
CS_n_i : in std_logic;
CT_n_o : out std_logic;
INT_n_o : out std_logic;
Temp_i : in real);
end component;
component ExtNames
port (
SPIFSM_Done : out std_logic
);
end component;
-- component generics
constant DataWidth : integer := 8;
-- Reset
signal Reset_n_i : std_logic := '0';
-- Clock
signal Clk_i : std_logic := '1';
signal Enable_i : std_logic;
signal CpuIntr_o : std_logic;
signal ADT7310CS_n_o : std_logic;
signal SPI_Data_i : std_logic_vector(7 downto 0);
signal SPI_Write_o : std_logic;
signal SPI_ReadNext_o : std_logic;
signal SPI_Data_o : std_logic_vector(7 downto 0);
signal SPI_FIFOFull_i : std_logic;
signal SPI_FIFOEmpty_i : std_logic;
signal SPI_Transmission_i : std_logic;
signal SPICounterPreset_i : std_logic_vector(15 downto 0);
signal Threshold_i : std_logic_vector(15 downto 0);
signal PeriodCounterPresetH_i : std_logic_vector(15 downto 0);
signal PeriodCounterPresetL_i : std_logic_vector(15 downto 0);
signal SensorValue_o : std_logic_vector(15 downto 0);
signal SensorValue_real : real;
signal SPI_CPOL_o : std_logic;
signal SPI_CPHA_o : std_logic;
signal SPI_LSBFE_o : std_logic;
signal SPI_SPPR_SPR_o : std_logic_vector(7 downto 0);
-- look into the ADT7310P32S16 app
-- alias SPIFSM_Done_i is << signal .adt7310_tb.DUT.SPIFSM_Done_s : std_logic >>;
-- ModelSim complains here, that the references signal is not a VHDL object.
-- True, this is a Verilog object. As a workaround the module ExtNames is created
-- which uses Verilog hierarchical names to reference the wire and assigns it to
-- an output. This module is instantiated (and it seems ModelSim only adds
-- Verilog<->VHDL signal converters on instance boundaries) and this output is
-- connected with the SPIFSM_Done_i signal.
signal SPIFSM_Done_i : std_logic; -- directly from inside SPI_FSM
-- Using the extracted Yosys FSM we get delta cycles and a glitch on
-- SPIFSM_Done_i. Therefore we generate a slightly delayed version and wait
-- on the ANDed value.
signal SPIFSM_Done_d : std_logic; -- sightly delayed
signal SPIFSM_Done_a : std_logic; -- SPIFSM_Done_i and SPIFSM_Done_d
-- ADT7310 component ports
signal SCLK_s : std_logic := '1';
signal DOUT_s : std_logic;
signal DIN_s : std_logic := '0';
signal CT_n_s : std_logic;
signal INT_n_s : std_logic;
signal Temp_s : real := 23.7;
-- SPI Master generics
constant SPPRWidth : integer := 4;
constant SPRWidth : integer := 4;
constant SPIFIFOReadWidth : integer := 4;
constant SPIFIFOWriteWidth : integer := 4;
-- SPI Master component ports
signal SPI_ScanEnable_s : std_logic := '0';
signal SPI_ScanClk_s : std_logic := '0';
signal SPI_ScanDataIn_s : std_logic := '0';
signal SPI_ScanDataOut_s : std_logic := '0';
-- The timer has to wait for 240ms. With a 16 bit resolution, the maximumn
-- counting periode is 3.66us. Here we set the clock signal to 10us = 100kHz.
-- The timer is preset to 24000.
constant ClkPeriode : time := 10 us;
begin
DUT: ADT7310P32S16
port map (
Reset_n_i => Reset_n_i,
Clk_i => Clk_i,
Enable_i => Enable_i,
CpuIntr_o => CpuIntr_o,
ADT7310CS_n_o => ADT7310CS_n_o,
SPI_Data_i => SPI_Data_i,
SPI_Write_o => SPI_Write_o,
SPI_ReadNext_o => SPI_ReadNext_o,
SPI_Data_o => SPI_Data_o,
SPI_FIFOFull_i => SPI_FIFOFull_i,
SPI_FIFOEmpty_i => SPI_FIFOEmpty_i,
SPI_Transmission_i => SPI_Transmission_i,
SPICounterPreset_i => SPICounterPreset_i,
Threshold_i => Threshold_i,
PeriodCounterPresetH_i => PeriodCounterPresetH_i,
PeriodCounterPresetL_i => PeriodCounterPresetL_i,
SensorValue_o => SensorValue_o,
SPI_CPOL_o => SPI_CPOL_o,
SPI_CPHA_o => SPI_CPHA_o,
SPI_LSBFE_o => SPI_LSBFE_o
);
SensorValue_real <= real(to_integer(unsigned(SensorValue_o)))/128.0;
ExtNames_1: ExtNames
port map (
SPIFSM_Done => SPIFSM_Done_i
);
SPIFSM_Done_d <= SPIFSM_Done_i after 1.0 ns;
SPIFSM_Done_a <= SPIFSM_Done_i and SPIFSM_Done_d;
spi_master_1: spi_master
generic map (
DataWidth => DataWidth,
SPPRWidth => SPPRWidth,
SPRWidth => SPRWidth,
FIFOReadWidth => SPIFIFOReadWidth,
FIFOWriteWidth => SPIFIFOWriteWidth
)
port map (
Reset_n => Reset_n_i,
Clk => Clk_i,
-- IO
SCK_o => SCLK_s,
MOSI_o => DIN_s,
MISO_i => DOUT_s,
-- control signals
CPOL_i => SPI_CPOL_o,
CPHA_i => SPI_CPHA_o,
LSBFE_i => SPI_LSBFE_o,
SPPR_i => SPI_SPPR_SPR_o(7 downto 4),
SPR_i => SPI_SPPR_SPR_o(3 downto 0),
Transmission_o => SPI_Transmission_i,
Write_i => SPI_Write_o,
ReadNext_i => SPI_ReadNext_o,
Data_i => SPI_Data_o,
Data_o => SPI_Data_i,
FIFOFull_o => SPI_FIFOFull_i,
FIFOEmpty_o => SPI_FIFOEmpty_i,
ScanEnable_i => SPI_ScanEnable_s,
ScanClk_i => SPI_ScanClk_s,
ScanDataIn_i => SPI_ScanDataIn_s,
ScanDataOut_o => SPI_ScanDataOut_s
);
adt7310_1: adt7310_model
port map (
SCLK_i => SCLK_s,
DOUT_o => DOUT_s,
DIN_i => DIN_s,
CS_n_i => ADT7310CS_n_o,
CT_n_o => CT_n_s,
INT_n_o => INT_n_s,
Temp_i => Temp_s);
-- constant value for reconfig signal
SPI_SPPR_SPR_o <= "00000000";
-- Generate clock signal
Clk_i <= not Clk_i after ClkPeriode*0.5;
StimulusProc: process
begin
Enable_i <= '0';
SPICounterPreset_i <= "0101110111000000";
Threshold_i <= "0000000000011110";
PeriodCounterPresetH_i <= "0000000000000000";
PeriodCounterPresetL_i <= "0000000000001010";
wait for 2.3*ClkPeriode;
assert SPI_CPOL_o = '1'
report "Dynamic signal SPI_CPOL_o should have constant value '1'" severity failure;
assert SPI_CPHA_o = '1'
report "Dynamic signal SPI_CPHA_o should have constant value '1'" severity failure;
assert SPI_LSBFE_o = '0'
report "Dynamic signal SPI_LSBFE_o should have constant value '0'" severity failure;
-- deassert Reset
Reset_n_i <= '1';
wait for 1.3*ClkPeriode; -- wait until spi_master's SCK_o goes '1' to conform to CPOL_i = '1'
Temp_s <= 23.7; -- degree C
-- three cycles with disabled SensorFSM
wait for 3*ClkPeriode;
-- enable SensorFSM
Enable_i <= '1';
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- The digital value is 128*Temp_s (plus/minus rounding to nearest
-- modulo 8). The threshold for too large changes is 30 (see
-- sensorfsm.vhd).
-- 23.7°C --> 3032
-- 25.7°C --> 3288 (delta: | 256| > 30)
-- 25.6°C --> 3280 (delta: | -8| < 30)
-- 25.5°C --> 3264 (delta: | -24| < 30)
-- 25.4°C --> 3248 (delta: | -40| >= 30)
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.7;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.6;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with small difference -> no notification
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.5;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '0' report "CpuIntr should still be '0' one cycle after SPIFSM is done for small value change" severity error;
assert abs(SensorValue_real - 25.7) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be old value " & real'image(25.7) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
-- new sensor value with large difference -> notify required
wait for 3*ClkPeriode; -- 3 cycle
Temp_s <= 25.4;
wait until SPIFSM_Done_d = '1';
assert ADT7310CS_n_o = '1' report "CS_n should be '1' when SPIFSM is done" severity error;
assert CpuIntr_o = '0' report "CpuIntr should be '0' directly after SPIFSM is done" severity error;
wait until rising_edge(Clk_i); wait for 0.1*ClkPeriode; -- 1 cycle
assert CpuIntr_o = '1' report "CpuIntr should be '1' one cycle after SPIFSM is done" severity error;
assert abs(SensorValue_real - Temp_s) <= 1.0/16.0/2.0
report "Invalid temperature value: " & real'image(SensorValue_real) & "°C, should be " & real'image(Temp_s) & "°C"
severity error;
wait for 1*ClkPeriode; -- 1 cycle
wait for 100 ms;
-- End of simulation
report "### Simulation Finished ###" severity failure;
wait;
end process StimulusProc;
end behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
entity graphics_engine is
end entity graphics_engine;
-- end not in book
architecture behavioral of graphics_engine is
type point is array (1 to 3) of real;
type transformation_matrix is array (1 to 3, 1 to 3) of real;
signal p, transformed_p : point;
signal a : transformation_matrix;
signal clock : bit;
-- . . .
begin
transform_stage : for i in 1 to 3 generate
begin
cross_product_transform : process is
variable result1, result2, result3 : real := 0.0;
begin
wait until clock = '1';
transformed_p(i) <= result3;
result3 := result2;
result2 := result1;
result1 := a(i, 1) * p(1) + a(i, 2) * p(2) + a(i, 3) * p(3);
end process cross_product_transform;
end generate transform_stage;
-- . . . -- other stages in the pipeline, etc
-- not in book
clock_gen : clock <= '1' after 10 ns, '0' after 20 ns when clock = '0';
stimulus : process is
begin
a <= ( (1.0, 0.0, 0.0), (0.0, 1.0, 0.0), (0.0, 0.0, 1.0) );
p <= ( 10.0, 10.0, 10.0 );
wait until clock = '0';
p <= ( 20.0, 20.0, 20.0 );
wait until clock = '0';
p <= ( 30.0, 30.0, 30.0 );
wait until clock = '0';
p <= ( 40.0, 40.0, 40.0 );
wait until clock = '0';
p <= ( 50.0, 50.0, 50.0 );
wait until clock = '0';
p <= ( 60.0, 60.0, 60.0 );
wait;
end process stimulus;
-- end not in book
end architecture behavioral;
|
entity test is
package a is new b generic map(c => foo(bar));
end;
|
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
-- Copyright (C) 2014 Jakub Kicinski <[email protected]>
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
use work.globals.all;
-- short description
entity __TMPL__ is
port (Clk : in std_logic;
Rst : in std_logic);
end __TMPL__;
-- Operation:
--
architecture Behavioral of __TMPL__ is
type state_t is (IDLE);
signal state, NEXT_state : state_t;
begin
NEXT_fsm : process (state)
begin
NEXT_state <= state;
case state is
when IDLE =>
end case;
end process;
fsm : process (Clk)
begin
if rising_edge(Clk) then
state <= NEXT_state;
if Rst = '1' then
state <= IDLE;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use ieee.math_real.all;
library std;
library altera_mf;
use altera_mf.altera_mf_components.all;
use work.harris_package_components.all;
--use work.harris_package_variables.all;
entity pipliner_7x7 is
generic (
LINE_WIDTH_MAX : integer;
PIX_WIDTH : integer;
HALF_WINDOW_WIDTH: integer -- The total window's width is :(HALF_WINDOW_WIDTH*2+1) : Should be an odd number
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
in_data : in std_logic_vector((PIX_WIDTH-1) downto 0);
in_fv : in std_logic;
in_dv : in std_logic;
out_data : out std_logic_vector((PIX_WIDTH-1) downto 0);
out_fv : out std_logic;
out_dv : out std_logic;
enable_i : in std_logic;
widthimg_i : in std_logic_vector(15 downto 0);
pixel_table_7_7 : out pixel_matrix
);
end pipliner_7x7;
architecture rtl of pipliner_7x7 is
type pixel_mask is array (0 to 2,0 to 2) of signed((PIX_WIDTH) downto 0);
type pix_out_signal is array (0 to 5) of std_logic_vector((PIX_WIDTH-1) downto 0);
--type pixel_matrix is array (0 to 6,0 to 6) of std_logic_vector((PIX_WIDTH-1) downto 0);
--type filter_matrix is array (0 to 6,0 to 6) of std_logic_vector(RESULT_LENGTH downto 0);
constant RESULT_LENGHT : integer := 64;
constant FIFO_LENGHT : integer := LINE_WIDTH_MAX-7;
constant FIFO_LENGHT_WIDTH : integer := integer(ceil(log2(real(FIFO_LENGHT))));
constant Ix_sobel_mask:pixel_mask:=((to_signed(-1,9),to_signed(0,9),to_signed(1,9)),(to_signed(-1,9),to_signed(0,9),to_signed(1,9)),(to_signed(-1,9),to_signed(0,9),to_signed(1,9)));
constant Iy_sobel_mask:pixel_mask:=((to_signed(-1,9),to_signed(-1,9),to_signed(-1,9)),(to_signed(0,9),to_signed(0,9),to_signed(0,9)),(to_signed(1,9),to_signed(1,9),to_signed(1,9)));
signal fv_signal,out_clk_dv:std_logic;
signal widthimg_temp : std_logic_vector(15 downto 0):=widthimg_i;
signal sig_wrreq:std_logic:='1';
signal sig_rdreq:std_logic:='0';
signal line_pix_out:pix_out_signal;
shared variable R:std_logic_vector((RESULT_LENGHT-1) downto 0);
shared variable Prev_R_max:std_logic_vector((RESULT_LENGHT-1) downto 0):=x"00000001DCD65000";
shared variable R_max:std_logic_vector((RESULT_LENGHT-1) downto 0):=x"00000001DCD65000";
shared variable conv_value_x,conv_value_y:signed(17 downto 0):=to_signed(0,18);
shared variable conv_value:integer:=0;
shared variable param_changing_reset:std_logic:='0';
shared variable Ixx,Ixy,Iyy:signed(31 downto 0):=to_signed(0,32);
shared variable cast_36_bits:std_logic_vector(35 downto 0);
shared variable aclr:std_logic:='0';
shared variable Ixx_vec,Iyy_vec:std_logic_vector(31 downto 0);
shared variable mult_a,mult_b,mult_2_a,mult_2_b,mult_3_a,mult_3_b:std_logic_vector(31 downto 0);
shared variable mult_s,mult_2_s,mult_3_s,comp_a,comp_a_2,comp_b,comp_b_2,add_a_1,add_b_1,add_b_2,add_s_inter,add_s :std_logic_vector(63 downto 0);
shared variable comp_s,comp_s_2:std_logic:='1';
shared variable pixel_matrix_kernel:pixel_matrix;
component scfifo
generic
( LPM_WIDTH: POSITIVE;
LPM_WIDTHU: POSITIVE;
LPM_NUMWORDS: POSITIVE;
LPM_SHOWAHEAD: STRING := "OFF";
ALLOW_RWCYCLE_WHEN_FULL: STRING := "OFF";
OVERFLOW_CHECKING: STRING:= "ON";
UNDERFLOW_CHECKING: STRING:= "ON"
);
port
(
data: in std_logic_vector(LPM_WIDTH-1 downto 0);
clock, wrreq, rdreq, aclr: in std_logic;
full, empty, almost_full, almost_empty: out std_logic;
q: out std_logic_vector(LPM_WIDTH-1 downto 0);
usedw: out std_logic_vector(LPM_WIDTHU-1 downto 0)
);
end component;
begin
sig_wrreq<='1';
G_1 : for i in 0 to 5 generate
line_fifo : scfifo
generic map (
LPM_WIDTH =>PIX_WIDTH,
LPM_WIDTHU =>FIFO_LENGHT_WIDTH,
LPM_NUMWORDS =>FIFO_LENGHT
)
port map(
data => pixel_matrix_kernel(i+1,0),
clock => clk_proc,
wrreq => in_dv,
q => line_pix_out(i),
rdreq => sig_rdreq and in_dv,
aclr =>param_changing_reset or(not(reset_n))
);
end generate;
process (clk_proc, reset_n)
variable x_pos,y_pos : unsigned(15 downto 0);
variable counter:integer:=0;
begin
fv_signal<=in_fv;
if(reset_n='0') then
x_pos := to_unsigned(0, 16);
y_pos := to_unsigned(0, 16);
out_clk_dv<='0';
elsif(rising_edge(clk_proc)) then
fv_signal<=in_fv;
out_clk_dv<='0';
if(in_fv='0') then
x_pos := to_unsigned(0, 16);y_pos := to_unsigned(0, 16);
out_clk_dv<='0';
------------------------------------------------------------------------------------------------------
elsif(in_dv='1') then
counter:=counter+1;
if(counter=(unsigned(widthimg_i)-8)) then
sig_rdreq<='1';
end if;
out_clk_dv<='1';
for o in 0 to 6 loop
for p in 0 to 5 loop
pixel_matrix_kernel(o,p):=pixel_matrix_kernel(o,p+1);
end loop;
if (o<6) then
pixel_matrix_kernel(o,6):=line_pix_out(o);
end if;
end loop;
pixel_matrix_kernel(6,6):=in_data;
----------- end of line ----------------
if(x_pos=unsigned(widthimg_i)) then
y_pos := y_pos+1;
x_pos := to_unsigned (1, 16);
else
x_pos := x_pos+1;
end if;
-----------------------------------------
----------------------- bloquage et débloquage de l'horloge -----------------------------------------------------
if (y_pos<=to_unsigned (HALF_WINDOW_WIDTH-1, 16)) then
out_clk_dv<='0';
end if;
----------------------- blocage de bords spéciale pour les deux premiers élements de bords ----------------------
if (x_pos<=to_unsigned (HALF_WINDOW_WIDTH, 16)) then
if (y_pos=to_unsigned (3, 16)) then
out_clk_dv<='0';
end if;
end if;
-----------------------------------------------------------------------------------------------------------------
else
end if;
-------------- changing widthimg_i parameter---------------------------------------------------------------------
if (unsigned(widthimg_i)=unsigned(widthimg_temp)) then
param_changing_reset:='0';
else
param_changing_reset:='1';
counter:=0;
sig_rdreq<='0';
end if;
widthimg_temp<=widthimg_i;
-----------------------------------------------------------------------------
else
end if;
end process;
out_data<= std_logic_vector(to_unsigned(conv_value, 8));
out_dv <= out_clk_dv;
out_fv <= fv_signal;
pixel_table_7_7<=pixel_matrix_kernel;
end rtl;
|
library IEEE;
use IEEE.std_logic_1164.ALL;
package mips_instruction_set is
-- --------------------------------------------------------------------------------------------------------
-- _____ _ _ _____ _______ _____ _ _ _____ _______ _____ ____ _ _ _____ ______ _______
-- |_ _| \ | |/ ____|__ __| __ \| | | |/ ____|__ __|_ _/ __ \| \ | | / ____| ____|__ __|
-- | | | \| | (___ | | | |__) | | | | | | | | || | | | \| | | (___ | |__ | |
-- | | | . ` |\___ \ | | | _ /| | | | | | | | || | | | . ` | \___ \| __| | |
-- _| |_| |\ |____) | | | | | \ \| |__| | |____ | | _| || |__| | |\ | ____) | |____ | |
-- |_____|_| \_|_____/ |_| |_| \_\\____/ \_____| |_| |_____\____/|_| \_| |_____/|______| |_|
-- --------------------------------------------------------------------------------------------------------
-- _ _ _ ____ ___ ____ _ _ ____ ___ _ ____ _ _ ____ ____ _ _ ___ ____ _ _ ____ _ _ ___ ____
-- | |\ | [__ | |__/ | | | | | | | |\ | | | | |\/| |__] | | |\ | |___ |\ | | [__
-- | | \| ___] | | \ |__| |___ | | |__| | \| |___ |__| | | | |__| | \| |___ | \| | ___]
--
subtype t_mips_opcode is std_logic_vector( 5 downto 0); -- operation code
subtype t_mips_format is std_logic_vector( 4 downto 0); -- format code
subtype t_mips_function is std_logic_vector( 5 downto 0); -- function code
subtype t_mips_reg_addr is std_logic_vector( 4 downto 0); -- register address
subtype t_mips_shamt is std_logic_vector( 4 downto 0); -- shift amount value
subtype t_mips_imm11 is std_logic_vector(10 downto 0); -- immediate value for coprocessor
subtype t_mips_imm16 is std_logic_vector(15 downto 0); -- immediate value for calculation/memory
subtype t_mips_imm26 is std_logic_vector(25 downto 0); -- immmediate value for jumps
subtype t_mips_fmt is std_logic_vector( 4 downto 0); -- format for coprocessor
subtype t_mips_cond is std_logic_vector( 3 downto 0); -- FPU compare condition
subtype t_mips_cc is std_logic_vector( 2 downto 0); -- FPU condition code address
subtype t_mips_z_branch is std_logic_vector( 1 downto 0); -- FPU branch coding
subtype t_mips_i_ctrl_bit is std_logic;
-- --------------------------------------------------------------------------------------
-- ____ ____ _ _ ____ ___ ____ ___ _ _ ___ ____
-- | | | |\ | [__ | |__| | |\ | | [__
-- |___ |__| | \| ___] | | | | | \| | ___]
--
-- SPECIAL REGISTER
--
constant MIPS_R_ZERO : t_mips_reg_addr := b"0_0000"; -- zero value register
constant MIPS_R_RA : t_mips_reg_addr := b"1_1111"; -- return value register address
-- --------------------------------------------------------------------------------------
-- ____ _ _ _ _ ____ ___ _ ____ _ _ ____ _ ____ _ _ ____ ____ ___ _ _ _ ____
-- |___ | | |\ | | | | | | |\ | |__| | |___ |\ | | | | | \ | |\ | | __
-- | |__| | \| |___ | | |__| | \| | | |___ |___ | \| |___ |__| |__/ | | \| |__]
-- --------------------------------------------------------------------------------------
-- ____ ____ ____ ____ ____ ____ _ ____ ___ ____ ____ ____ ____ ____ _ _ ____ ___
-- |___ | | |__/ |__/ |___ | __ | [__ | |___ |__/ |___ | | |__/ |\/| |__| |
-- | |__| | \ | \ |___ |__] | ___] | |___ | \ | |__| | \ | | | | |
--
-- opcode(6) & rs(5) & rt(5) & rd(5) & shamt(5) & funct(6)
--
constant MIPS_OPCODE_REG : t_mips_opcode := b"00_0000";
--
-- shifter operations
constant MIPS_FUNC_SLL : t_mips_function := b"00_0000"; -- rd = rt << sa
constant MIPS_FUNC_SRL : t_mips_function := b"00_0010"; -- rd = rt >> sa
constant MIPS_FUNC_SRA : t_mips_function := b"00_0011"; -- rd = signed(rt) >> sa
constant MIPS_FUNC_SLLV : t_mips_function := b"00_0100"; -- rd = rt << rs
constant MIPS_FUNC_SRLV : t_mips_function := b"00_0110"; -- rd = rt >> rs
constant MIPS_FUNC_SRAV : t_mips_function := b"00_0111"; -- rd = signed(rt) >> rs
-- jump register
constant MIPS_FUNC_JR : t_mips_function := b"00_1000"; -- pc = rs
constant MIPS_FUNC_JALR : t_mips_function := b"00_1001"; -- pc = rs; rd = pc
-- syscall and break
constant MIPS_FUNC_SYSCALL : t_mips_function := b"00_1100"; -- do nothing
constant MIPS_FUNC_BREAK : t_mips_function := b"00_1101"; -- do nothing
-- multiplication register moving
constant MIPS_FUNC_MFHI : t_mips_function := b"01_0000"; -- rd = HI
constant MIPS_FUNC_MTHI : t_mips_function := b"01_0001"; -- HI = rs
constant MIPS_FUNC_MFLO : t_mips_function := b"01_0010"; -- rd = LO
constant MIPS_FUNC_MTLO : t_mips_function := b"01_0011"; -- LO = rs
-- multiplication/division
constant MIPS_FUNC_MULT : t_mips_function := b"01_1000"; -- HI,LO = rs * rt
constant MIPS_FUNC_MULTU : t_mips_function := b"01_1001"; -- HI,LO = signed(rs) * signed(rt)
constant MIPS_FUNC_DIV : t_mips_function := b"01_1010"; -- HI = rs % rt; LO = rs / rt
constant MIPS_FUNC_DIVU : t_mips_function := b"01_1011"; -- HI = rs % rt; LO = signed(rs) / sigend(rt)
-- addition/substraction
constant MIPS_FUNC_ADD : t_mips_function := b"10_0000"; -- rd = rs + rt
constant MIPS_FUNC_ADDU : t_mips_function := b"10_0001"; -- rd = unsigned(rs) + unsigned(rt)
constant MIPS_FUNC_SUB : t_mips_function := b"10_0010"; -- rd = rs - rt
constant MIPS_FUNC_SUBU : t_mips_function := b"10_0011"; -- rd = unsigned(rs) - unsigned(rt)
-- logic manipulation
constant MIPS_FUNC_AND : t_mips_function := b"10_0100"; -- rd = rs and rt
constant MIPS_FUNC_OR : t_mips_function := b"10_0101"; -- rd = rs or rt
constant MIPS_FUNC_XOR : t_mips_function := b"10_0110"; -- rd = rs xor rt
constant MIPS_FUNC_NOR : t_mips_function := b"10_0111"; -- rd = rs nor rt
-- comparison
constant MIPS_FUNC_SLT : t_mips_function := b"10_1010"; -- rd = rs < rt
constant MIPS_FUNC_SLTU : t_mips_function := b"10_1011"; -- rd = unsigned(rs) < unsigend(rt)
-- ____ ____ ____ _ _ _ _ _
-- |__/ |___ | __ | |\/| |\/|
-- | \ |___ |__] | | | | |
--
-- 00_0001 & rs(5) & func & imm16
--
constant MIPS_OPCODE_REGIMM : t_mips_opcode := b"00_0001"; -- REGIMM instruction class
constant MIPS_OPCODE_BLTZ : t_mips_reg_addr := b"0_0000"; -- if(rs < 0) pc = imm16 << 2
constant MIPS_OPCODE_BGEZ : t_mips_reg_addr := b"0_0001"; -- if(rs >= 0) pc = imm16 << 2
constant MIPS_OPCODE_BLTZAL : t_mips_reg_addr := b"1_0000"; -- if(rs < 0) pc = imm16 << 2; r31 = pc
constant MIPS_OPCODE_BGEZAL : t_mips_reg_addr := b"1_0001"; -- if(rs >= 0) pc = imm16 << 2; r31 = pc
-- --------------------------------------------------------------------------------------
-- _ _ _ _ _ ___ ____ ____ ____ _ _ ____ ___
-- | | | |\/| |__] |___ | | |__/ |\/| |__| |
-- _| |__| | | | | |__| | \ | | | | |
-- --------------------------------------------------------------------------------------
--
-- opcode(6) & immediate(26)
--
constant MIPS_OPCODE_J : t_mips_opcode := b"00_0010"; -- pc = imm26 << 2
constant MIPS_OPCODE_JAL : t_mips_opcode := b"00_0011"; -- pc = imm26 << 2; r31 = pc
-- --------------------------------------------------------------------------------------
-- _ _ _ _ _ ____ ___ _ ____ ___ ____ ____ ____ ____ _ _ ____ ___
-- | |\/| |\/| |___ | \ | |__| | |___ |___ | | |__/ |\/| |__| |
-- | | | | | |___ |__/ | | | | |___ | |__| | \ | | | | |
-- --------------------------------------------------------------------------------------
--
-- opcode(6) & rs(5) & rt(5) & immediate(16)
--
-- ___ ____ ____ _ _ ____ _ _
-- |__] |__/ |__| |\ | | |__|
-- |__] | \ | | | \| |___ | |
constant MIPS_OPCODE_BEQ : t_mips_opcode := b"00_0100"; -- if(rs == rt) pc = imm16 << 2
constant MIPS_OPCODE_BNE : t_mips_opcode := b"00_0101"; -- if(rs != rt) pc = imm16 << 2
constant MIPS_OPCODE_BLEZ : t_mips_opcode := b"00_0110"; -- if(rs <= 0) pc = imm16 << 2
constant MIPS_OPCODE_BGTZ : t_mips_opcode := b"00_0111"; -- if(rs > 0) pc = imm16 << 2
-- addition, comparison, logic
constant MIPS_OPCODE_ADDI : t_mips_opcode := b"00_1000"; -- rt = rs + imm16
constant MIPS_OPCODE_ADDIU : t_mips_opcode := b"00_1001"; -- rt = unsigned(rs) + imm16
constant MIPS_OPCODE_SLTI : t_mips_opcode := b"00_1010"; -- rt = rs < imm16
constant MIPS_OPCODE_SLTIU : t_mips_opcode := b"00_1011"; -- rt = unsigned(rs) < imm16
constant MIPS_OPCODE_ANDI : t_mips_opcode := b"00_1100"; -- rt = rs and imm16
constant MIPS_OPCODE_ORI : t_mips_opcode := b"00_1101"; -- rt = rs or imm16
constant MIPS_OPCODE_XORI : t_mips_opcode := b"00_1110"; -- rt = rs xor imm16
constant MIPS_OPCODE_LUI : t_mips_opcode := b"00_1111"; -- rt = imm16 << 16
-- _ _ ____ _ _ ____ ____ _ _
-- |\/| |___ |\/| | | |__/ \_/
-- | | |___ | | |__| | \ |
-- load from memory
constant MIPS_OPCODE_LB : t_mips_opcode := b"10_0000"; -- rt = *(char* )(rs + offset)
constant MIPS_OPCODE_LH : t_mips_opcode := b"10_0001"; -- rt = *(short* )(rs + offset)
constant MIPS_OPCODE_LWL : t_mips_opcode := b"10_0010"; -- same as LW
constant MIPS_OPCODE_LW : t_mips_opcode := b"10_0011"; -- rt = *(int* )(rs + offset)
constant MIPS_OPCODE_LBU : t_mips_opcode := b"10_0100"; -- rt = *(unsigned char* )(rs + offset)
constant MIPS_OPCODE_LHU : t_mips_opcode := b"10_0101"; -- rt = *(unsigned short* )(rs + offset)
constant MIPS_OPCODE_LWR : t_mips_opcode := b"10_0110"; -- same as NOP
-- store to memory
constant MIPS_OPCODE_SB : t_mips_opcode := b"10_1000"; -- *(char* )(rs + offset) = rt
constant MIPS_OPCODE_SH : t_mips_opcode := b"10_1001"; -- *(short* )(rs + offset) = rt
constant MIPS_OPCODE_SWL : t_mips_opcode := b"10_1010"; -- same as SW
constant MIPS_OPCODE_SW : t_mips_opcode := b"10_1011"; -- *(int* )(rs + offset) = rt
constant MIPS_OPCODE_SWR : t_mips_opcode := b"10_1110"; -- same as NOP
end package mips_instruction_set;
|
--------------------------------------------------------------------------------
-- Copyright (C) 2016 Josi Coder
-- This program is free software: you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 3 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
-- more details.
--
-- You should have received a copy of the GNU General Public License along with
-- this program. If not, see <http://www.gnu.org/licenses/>.
----------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Creates sine, square, triangle, and sawtooth function values from an exter-
-- nally supplied phase value (i.e. no time-related signal is generated here).
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FunctionGenerator_Declarations.all;
entity FunctionGenerator is
generic
(
-- The width of the phase values.
phase_width: natural := 32;
-- The width of the phase values of the waveform lookup table (must not
-- exceed phase_width).
lookup_table_phase_width: natural := 12;
-- The width of the sample values.
sample_width: natural := 16
);
port
(
-- The system clock.
clk: in std_logic;
-- The configuration (e.g. waveforms).
config: in generator_config;
-- The current phase value.
phase: in unsigned (phase_width-1 downto 0);
-- The sample value according to the current phase.
sample: out signed (sample_width-1 downto 0) := (others => '0')
);
end entity;
architecture stdarch of FunctionGenerator is
type reg_type is record
sample: signed(sample_width-1 downto 0);
end record;
signal state, next_state: reg_type :=
(
sample => (others => '0')
);
signal lookup_sample: signed (sample_width-1 downto 0);
begin
--------------------------------------------------------------------------------
-- Component instantiation.
--------------------------------------------------------------------------------
lookup_table: entity work.LookupTableContainer
generic map
(
phase_width => lookup_table_phase_width,
sample_width => sample_width
)
port map
(
clk => clk,
phase => phase(phase'left downto phase_width-lookup_table_phase_width),
sample => lookup_sample
);
--------------------------------------------------------------------------------
-- State register.
--------------------------------------------------------------------------------
state_register: process is
begin
wait until rising_edge(clk);
state <= next_state;
end process;
--------------------------------------------------------------------------------
-- Next state logic.
--------------------------------------------------------------------------------
next_state_logic: process(state, config, phase) is
constant width_difference: integer := sample_width - phase_width;
begin
-- Defaults.
next_state <= state;
-- Create the next sample according to the selected waveform. Note that
-- the sample is signed and thus uses two´s complement. Samples read from
-- a lookup table are not handled here.
case config.waveform is
when waveform_square =>
-- Derive the square signal from the phase´s MSB.
next_state.sample(next_state.sample'high) <= phase(phase'high);
next_state.sample(next_state.sample'high-1 downto 0) <= (others => not phase(phase'high));
when waveform_sawtooth =>
-- Derive the sawtooth signal from the phase (pad or truncate LSBs
-- when widths are different).
next_state.sample <= (others => '0');
if (width_difference >= 0) then
next_state.sample(next_state.sample'high downto width_difference) <= signed(phase);
else
next_state.sample <= signed(phase(phase'high downto -width_difference));
end if;
when others =>
end case;
end process;
--------------------------------------------------------------------------------
-- Output logic.
--------------------------------------------------------------------------------
select_sample: process(state.sample, lookup_sample) is
begin
sample <= state.sample;
-- Select whether to use samples created here or those read from a lookup
-- table.
if config.waveform = waveform_sine then
sample <= lookup_sample;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 19:50:59 03/16/2014
-- Design Name:
-- Module Name: TB_DUAL_RAM - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use work.UMDRISC_pkg.ALL;
entity TB_REG_S16 is
end TB_REG_S16;
architecture Behavioral of TB_REG_S16 is
component REG_S16 is
generic(
REG_WIDTH: integer:=4 -- select between 16 different possible registers
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--Register A
REG_A_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A : out std_logic_vector(DATA_WIDTH-1 downto 0);
--Register B
REG_B_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_B : out std_logic_vector(DATA_WIDTH-1 downto 0);
--CHANGE REGISTER
REG_A_IN_ADDR : in std_logic_vector(REG_WIDTH-1 downto 0);
REG_A_IN : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end component;
CONSTANT REG_WIDTH:integer:=4;
signal CLOCK : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal REG_A_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_B_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_B : std_logic_vector(DATA_WIDTH-1 downto 0);
signal REG_A_IN_ADDR : std_logic_vector(REG_WIDTH-1 downto 0);
signal REG_A_IN : std_logic_vector(DATA_WIDTH-1 downto 0);
constant period : time := 10 ns;
begin
-- 15 24bit General purpose register
Reg1: REG_S16 port map(
CLOCK => Clock,
WE => WE,
REG_A_ADDR => REG_A_ADDR,
REG_A => REG_A,
REG_B_ADDR => REG_B_ADDR,
REG_B => REG_B,
REG_A_IN_ADDR => REG_A_IN_ADDR,
REG_A_IN => REG_A_IN
);
m50MHZ_Clock: process
begin
CLOCK <= '0'; wait for period;
CLOCK <= '1'; wait for period;
end process m50MHZ_Clock;
tb : process
begin
-- Wait 100 ns for global reset to finish
wait for 5*period;
report "Starting [name] Test Bench" severity NOTE;
----- Unit Test -----
REG_A_ADDR <= (others => '0');
REG_B_ADDR <= (others => '0');
REG_A_IN_ADDR <= (others => '0');
REG_A_IN <= x"FFFFFF";wait for 2*period;
--Enabling the register
WE <= '1'; wait for 2*period;
WE <= '0';
REG_A_IN_ADDR <= x"1";
WE <= '1'; wait for 2*period;
WE <= '0';
REG_B_ADDR <= x"1"; wait for 50*period;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity GeneralPropagate is
Port ( G_ik : in STD_LOGIC;
P_ik : in STD_LOGIC;
G_km1_j : in STD_LOGIC;
P_km1_j : in STD_LOGIC;
G_ij : out STD_LOGIC;
P_ij : out STD_LOGIC);
end GeneralPropagate;
architecture Behavioral of GeneralPropagate is
begin
G_ij <= G_ik OR (P_ik AND G_km1_j);
P_ij <= p_ik AND P_km1_j;
end Behavioral;
|
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/91 |
-- --------------------------------------------------------------------
PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( or_table( l, r )));
END "nor";
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (xor_table(l, r));
END "xor";
--START-!V87
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN not_table(xor_table(l, r));
END "xnor";
--END-!V87
FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table(l));
END "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
---------------------------------------------------------------------
FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
---------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
---------------------------------------------------------------------
FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
---------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
-- -------------------------------------------------------------------
-- -- xnor
-- -------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
--START-!V87
FUNCTION "xnor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
---------------------------------------------------------------------
FUNCTION "xnor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
--END-!V87
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
---------------------------------------------------------------------
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS
BEGIN
CASE s IS
WHEN '0' | 'L' => RETURN ('0');
WHEN '1' | 'H' => RETURN ('1');
WHEN OTHERS => RETURN xmap;
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
BEGIN
CASE b IS
WHEN '0' => RETURN '0';
WHEN '1' => RETURN '1';
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
BEGIN
RETURN (cvt_to_x01z(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (cvt_to_ux01(s));
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '0') AND
(To_X01(s'LAST_VALUE) = '1'));
END;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
BEGIN
CASE s IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
RETURN FALSE;
END;
END std_logic_1164;
|
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/91 |
-- --------------------------------------------------------------------
PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( or_table( l, r )));
END "nor";
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (xor_table(l, r));
END "xor";
--START-!V87
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN not_table(xor_table(l, r));
END "xnor";
--END-!V87
FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table(l));
END "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
---------------------------------------------------------------------
FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
---------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
---------------------------------------------------------------------
FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
---------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
-- -------------------------------------------------------------------
-- -- xnor
-- -------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
--START-!V87
FUNCTION "xnor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
---------------------------------------------------------------------
FUNCTION "xnor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
--END-!V87
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
---------------------------------------------------------------------
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS
BEGIN
CASE s IS
WHEN '0' | 'L' => RETURN ('0');
WHEN '1' | 'H' => RETURN ('1');
WHEN OTHERS => RETURN xmap;
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
BEGIN
CASE b IS
WHEN '0' => RETURN '0';
WHEN '1' => RETURN '1';
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
BEGIN
RETURN (cvt_to_x01z(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (cvt_to_ux01(s));
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '0') AND
(To_X01(s'LAST_VALUE) = '1'));
END;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
BEGIN
CASE s IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
RETURN FALSE;
END;
END std_logic_1164;
|
-- --------------------------------------------------------------------
--
-- Title : std_logic_1164 multi-value logic system
-- Library : This package shall be compiled into a library
-- : symbolically named IEEE.
-- :
-- Developers: IEEE model standards group (par 1164)
-- Purpose : This packages defines a standard for designers
-- : to use in describing the interconnection data types
-- : used in vhdl modeling.
-- :
-- Limitation: The logic system defined in this package may
-- : be insufficient for modeling switched transistors,
-- : since such a requirement is out of the scope of this
-- : effort. Furthermore, mathematics, primitives,
-- : timing standards, etc. are considered orthogonal
-- : issues as it relates to this package and are therefore
-- : beyond the scope of this effort.
-- :
-- Note : No declarations or definitions shall be included in,
-- : or excluded from this package. The "package declaration"
-- : defines the types, subtypes and declarations of
-- : std_logic_1164. The std_logic_1164 package body shall be
-- : considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement
-- : the package body in the most efficient manner available
-- : to them.
-- :
-- --------------------------------------------------------------------
-- modification history :
-- --------------------------------------------------------------------
-- version | mod. date:|
-- v4.200 | 01/02/91 |
-- --------------------------------------------------------------------
PACKAGE BODY std_logic_1164 IS
-------------------------------------------------------------------
-- local types
-------------------------------------------------------------------
TYPE stdlogic_1d IS ARRAY (std_ulogic) OF std_ulogic;
TYPE stdlogic_table IS ARRAY(std_ulogic, std_ulogic) OF std_ulogic;
-------------------------------------------------------------------
-- resolution function
-------------------------------------------------------------------
CONSTANT resolution_table : stdlogic_table := (
-- ---------------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ---------------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', 'X', '0', '0', '0', '0', 'X' ), -- | 0 |
( 'U', 'X', 'X', '1', '1', '1', '1', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', 'X' ), -- | Z |
( 'U', 'X', '0', '1', 'W', 'W', 'W', 'W', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'L', 'W', 'L', 'W', 'X' ), -- | L |
( 'U', 'X', '0', '1', 'H', 'W', 'W', 'H', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
FUNCTION resolved ( s : std_ulogic_vector ) RETURN std_ulogic IS
VARIABLE result : std_ulogic := 'Z'; -- weakest state default
BEGIN
-- the test for a single driver is essential otherwise the
-- loop would return 'X' for a single driver of '-' and that
-- would conflict with the value of a single driver unresolved
-- signal.
IF (s'LENGTH = 1) THEN RETURN s(s'LOW);
ELSE
FOR i IN s'RANGE LOOP
result := resolution_table(result, s(i));
END LOOP;
END IF;
RETURN result;
END resolved;
-------------------------------------------------------------------
-- tables for logical operations
-------------------------------------------------------------------
-- truth table for "and" function
CONSTANT and_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for "or" function
CONSTANT or_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', '1', 'U', 'U', 'U', '1', 'U' ), -- | U |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | Z |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ), -- | H |
( 'U', 'X', 'X', '1', 'X', 'X', 'X', '1', 'X' ) -- | - |
);
-- truth table for "xor" function
CONSTANT xor_table : stdlogic_table := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | X |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 0 |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ), -- | W |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | L |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' ), -- | H |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', 'X' ) -- | - |
);
-- truth table for "not" function
CONSTANT not_table: stdlogic_1d :=
-- -------------------------------------------------
-- | U X 0 1 Z W L H - |
-- -------------------------------------------------
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', 'X' );
-------------------------------------------------------------------
-- overloaded logical operators ( with optimizing hints )
-------------------------------------------------------------------
FUNCTION "and" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (and_table(l, r));
END "and";
FUNCTION "nand" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( and_table(l, r)));
END "nand";
FUNCTION "or" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (or_table(l, r));
END "or";
FUNCTION "nor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table ( or_table( l, r )));
END "nor";
FUNCTION "xor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (xor_table(l, r));
END "xor";
--START-!V87
FUNCTION "xnor" ( l : std_ulogic; r : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN not_table(xor_table(l, r));
END "xnor";
--END-!V87
FUNCTION "not" ( l : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (not_table(l));
END "not";
-------------------------------------------------------------------
-- and
-------------------------------------------------------------------
FUNCTION "and" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
---------------------------------------------------------------------
FUNCTION "and" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'and' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := and_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "and";
-------------------------------------------------------------------
-- nand
-------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
---------------------------------------------------------------------
FUNCTION "nand" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nand' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(and_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nand";
-------------------------------------------------------------------
-- or
-------------------------------------------------------------------
FUNCTION "or" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
---------------------------------------------------------------------
FUNCTION "or" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'or' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := or_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "or";
-------------------------------------------------------------------
-- nor
-------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
FUNCTION "nor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'nor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(or_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "nor";
---------------------------------------------------------------------
-- xor
-------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
---------------------------------------------------------------------
FUNCTION "xor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := xor_table (lv(i), rv(i));
END LOOP;
END IF;
RETURN result;
END "xor";
-- -------------------------------------------------------------------
-- -- xnor
-- -------------------------------------------------------------------
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this std_logic_1164 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
--START-!V87
FUNCTION "xnor" ( l,r : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_logic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
---------------------------------------------------------------------
FUNCTION "xnor" ( l,r : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
ALIAS rv : std_ulogic_vector ( 1 TO r'LENGTH ) IS r;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH );
BEGIN
IF ( l'LENGTH /= r'LENGTH ) THEN
ASSERT FALSE
REPORT "arguments of overloaded 'xnor' operator are not of the same length"
SEVERITY FAILURE;
ELSE
FOR i IN result'RANGE LOOP
result(i) := not_table(xor_table (lv(i), rv(i)));
END LOOP;
END IF;
RETURN result;
END "xnor";
--END-!V87
-------------------------------------------------------------------
-- not
-------------------------------------------------------------------
FUNCTION "not" ( l : std_logic_vector ) RETURN std_logic_vector IS
ALIAS lv : std_logic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_logic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
---------------------------------------------------------------------
FUNCTION "not" ( l : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS lv : std_ulogic_vector ( 1 TO l'LENGTH ) IS l;
VARIABLE result : std_ulogic_vector ( 1 TO l'LENGTH ) := (OTHERS => 'X');
BEGIN
FOR i IN result'RANGE LOOP
result(i) := not_table( lv(i) );
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- conversion tables
-------------------------------------------------------------------
TYPE logic_x01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01;
TYPE logic_x01z_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF X01Z;
TYPE logic_ux01_table IS ARRAY (std_ulogic'LOW TO std_ulogic'HIGH) OF UX01;
----------------------------------------------------------
-- table name : cvt_to_x01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01 : logic_x01_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_x01z
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : x01z -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_x01z (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_x01z : logic_x01z_table := (
'X', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'Z', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
----------------------------------------------------------
-- table name : cvt_to_ux01
--
-- parameters :
-- in : std_ulogic -- some logic value
-- returns : ux01 -- state value of logic value
-- purpose : to convert state-strength to state only
--
-- example : if (cvt_to_ux01 (input_signal) = '1' ) then ...
--
----------------------------------------------------------
CONSTANT cvt_to_ux01 : logic_ux01_table := (
'U', -- 'U'
'X', -- 'X'
'0', -- '0'
'1', -- '1'
'X', -- 'Z'
'X', -- 'W'
'0', -- 'L'
'1', -- 'H'
'X' -- '-'
);
-------------------------------------------------------------------
-- conversion functions
-------------------------------------------------------------------
FUNCTION To_bit ( s : std_ulogic; xmap : BIT := '0') RETURN BIT IS
BEGIN
CASE s IS
WHEN '0' | 'L' => RETURN ('0');
WHEN '1' | 'H' => RETURN ('1');
WHEN OTHERS => RETURN xmap;
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_logic_vector ; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_bitvector ( s : std_ulogic_vector; xmap : BIT := '0') RETURN BIT_VECTOR IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : BIT_VECTOR ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE sv(i) IS
WHEN '0' | 'L' => result(i) := '0';
WHEN '1' | 'H' => result(i) := '1';
WHEN OTHERS => result(i) := xmap;
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogic ( b : BIT ) RETURN std_ulogic IS
BEGIN
CASE b IS
WHEN '0' => RETURN '0';
WHEN '1' => RETURN '1';
END CASE;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_logic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdLogicVector ( s : std_ulogic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_logic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( b'LENGTH-1 DOWNTO 0 ) IS b;
VARIABLE result : std_ulogic_vector ( b'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_StdULogicVector ( s : std_logic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_logic_vector ( s'LENGTH-1 DOWNTO 0 ) IS s;
VARIABLE result : std_ulogic_vector ( s'LENGTH-1 DOWNTO 0 );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := sv(i);
END LOOP;
RETURN result;
END;
-------------------------------------------------------------------
-- strength strippers and type convertors
-------------------------------------------------------------------
-- to_x01
-------------------------------------------------------------------
FUNCTION To_X01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS
BEGIN
RETURN (cvt_to_x01(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01 ( b : BIT ) RETURN X01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_x01z
-------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_x01z (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( s : std_ulogic ) RETURN X01Z IS
BEGIN
RETURN (cvt_to_x01z(s));
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_X01Z ( b : BIT ) RETURN X01Z IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
--------------------------------------------------------------------
-- to_ux01
-------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_logic_vector ) RETURN std_logic_vector IS
ALIAS sv : std_logic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_logic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic_vector ) RETURN std_ulogic_vector IS
ALIAS sv : std_ulogic_vector ( 1 TO s'LENGTH ) IS s;
VARIABLE result : std_ulogic_vector ( 1 TO s'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
result(i) := cvt_to_ux01 (sv(i));
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( s : std_ulogic ) RETURN UX01 IS
BEGIN
RETURN (cvt_to_ux01(s));
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_logic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_logic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT_VECTOR ) RETURN std_ulogic_vector IS
ALIAS bv : BIT_VECTOR ( 1 TO b'LENGTH ) IS b;
VARIABLE result : std_ulogic_vector ( 1 TO b'LENGTH );
BEGIN
FOR i IN result'RANGE LOOP
CASE bv(i) IS
WHEN '0' => result(i) := '0';
WHEN '1' => result(i) := '1';
END CASE;
END LOOP;
RETURN result;
END;
--------------------------------------------------------------------
FUNCTION To_UX01 ( b : BIT ) RETURN UX01 IS
BEGIN
CASE b IS
WHEN '0' => RETURN('0');
WHEN '1' => RETURN('1');
END CASE;
END;
-------------------------------------------------------------------
-- edge detection
-------------------------------------------------------------------
FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '1') AND
(To_X01(s'LAST_VALUE) = '0'));
END;
FUNCTION falling_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
RETURN (s'EVENT AND (To_X01(s) = '0') AND
(To_X01(s'LAST_VALUE) = '1'));
END;
-------------------------------------------------------------------
-- object contains an unknown
-------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_logic_vector ) RETURN BOOLEAN IS
BEGIN
FOR i IN s'RANGE LOOP
CASE s(i) IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
END LOOP;
RETURN FALSE;
END;
--------------------------------------------------------------------
FUNCTION Is_X ( s : std_ulogic ) RETURN BOOLEAN IS
BEGIN
CASE s IS
WHEN 'U' | 'X' | 'Z' | 'W' | '-' => RETURN TRUE;
WHEN OTHERS => NULL;
END CASE;
RETURN FALSE;
END;
END std_logic_1164;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_23a is
end entity inline_23a;
architecture test of inline_23a is
signal digital_level : integer;
constant num_levels : integer := 63;
constant max_voltage : real := 10.0;
begin
block_1 : block is
quantity analog_voltage : real;
begin
-- code from book
analog_voltage == real(digital_level) / real(num_levels) * max_voltage;
-- end code from book
end block block_1;
block_2 : block is
signal real_digital_level : real;
quantity analog_voltage : real;
begin
-- code from book
real_digital_level <= real(digital_level);
analog_voltage == real_digital_level'ramp(1.0E-6) / real(num_levels) * max_voltage;
-- end code from book
end block block_2;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_23a is
end entity inline_23a;
architecture test of inline_23a is
signal digital_level : integer;
constant num_levels : integer := 63;
constant max_voltage : real := 10.0;
begin
block_1 : block is
quantity analog_voltage : real;
begin
-- code from book
analog_voltage == real(digital_level) / real(num_levels) * max_voltage;
-- end code from book
end block block_1;
block_2 : block is
signal real_digital_level : real;
quantity analog_voltage : real;
begin
-- code from book
real_digital_level <= real(digital_level);
analog_voltage == real_digital_level'ramp(1.0E-6) / real(num_levels) * max_voltage;
-- end code from book
end block block_2;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee_proposed; use ieee_proposed.electrical_systems.all;
entity inline_23a is
end entity inline_23a;
architecture test of inline_23a is
signal digital_level : integer;
constant num_levels : integer := 63;
constant max_voltage : real := 10.0;
begin
block_1 : block is
quantity analog_voltage : real;
begin
-- code from book
analog_voltage == real(digital_level) / real(num_levels) * max_voltage;
-- end code from book
end block block_1;
block_2 : block is
signal real_digital_level : real;
quantity analog_voltage : real;
begin
-- code from book
real_digital_level <= real(digital_level);
analog_voltage == real_digital_level'ramp(1.0E-6) / real(num_levels) * max_voltage;
-- end code from book
end block block_2;
end architecture test;
|
-- Pixel_On_Text determines if the current pixel is on text
-- param:
-- textlength, use to init the string
-- input:
-- VGA clock(the clk you used to update VGA)
-- display text
-- top left corner of the text box
-- current X and Y position
-- output:
-- a bit that represent whether is the pixel in text
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
-- note this line.The package is compiled to this directory by default.
-- so don't forget to include this directory.
library work;
-- this line also is must.This includes the particular package into your program.
use work.commonPak.all;
entity Pixel_On_Text is
generic(
-- needed for init displayText, the default value 11 is just a random number
textLength: integer := 11
);
port (
clk: in std_logic;
displayText: in string (1 to textLength) := (others => NUL);
-- top left corner of the text
position: in point_2d := (0, 0);
-- current pixel postion
horzCoord: in integer;
vertCoord: in integer;
pixel: out std_logic := '0'
);
end Pixel_On_Text;
architecture Behavioral of Pixel_On_Text is
signal fontAddress: integer;
-- A row of bit in a charactor, we check if our current (x,y) is 1 in char row
signal charBitInRow: std_logic_vector(FONT_WIDTH-1 downto 0) := (others => '0');
-- char in ASCII code
signal charCode:integer := 0;
-- the position(column) of a charactor in the given text
signal charPosition:integer := 0;
-- the bit position(column) in a charactor
signal bitPosition:integer := 0;
begin
-- (horzCoord - position.x): x positionin the top left of the whole text
charPosition <= (horzCoord - position.x)/FONT_WIDTH + 1;
bitPosition <= (horzCoord - position.x) mod FONT_WIDTH;
charCode <= character'pos(displayText(charPosition));
-- charCode*16: first row of the char
fontAddress <= charCode*16+(vertCoord - position.y);
fontRom: entity work.Font_Rom
port map(
clk => clk,
addr => fontAddress,
fontRow => charBitInRow
);
pixelOn: process(clk)
variable inXRange: boolean := false;
variable inYRange: boolean := false;
begin
if rising_edge(clk) then
-- reset
inXRange := false;
inYRange := false;
pixel <= '0';
-- If current pixel is in the horizontal range of text
if horzCoord >= position.x and horzCoord < position.x + (FONT_WIDTH * textlength) then
inXRange := true;
end if;
-- If current pixel is in the vertical range of text
if vertCoord >= position.y and vertCoord < position.y + FONT_HEIGHT then
inYRange := true;
end if;
-- need to check if the pixel is on for text
if inXRange and inYRange then
-- FONT_WIDTH-bitPosition: we are reverting the charactor
if charBitInRow(FONT_WIDTH-bitPosition) = '1' then
pixel <= '1';
end if;
end if;
end if;
end process;
end Behavioral; |
-- NEED RESULT: ARCH00145.P1: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P2: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P3: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P4: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P5: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P6: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P7: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P8: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P9: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P10: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P11: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P12: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P13: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P14: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P15: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P16: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145.P17: Multi inertial transactions occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Old transactions were removed on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: One inertial transaction occurred on signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: ARCH00145: Inertial semantics check on a signal asg with slice name on LHS failed
-- NEED RESULT: P17: Inertial transactions entirely completed failed
-- NEED RESULT: P16: Inertial transactions entirely completed failed
-- NEED RESULT: P15: Inertial transactions entirely completed failed
-- NEED RESULT: P14: Inertial transactions entirely completed failed
-- NEED RESULT: P13: Inertial transactions entirely completed failed
-- NEED RESULT: P12: Inertial transactions entirely completed failed
-- NEED RESULT: P11: Inertial transactions entirely completed failed
-- NEED RESULT: P10: Inertial transactions entirely completed failed
-- NEED RESULT: P9: Inertial transactions entirely completed failed
-- NEED RESULT: P8: Inertial transactions entirely completed failed
-- NEED RESULT: P7: Inertial transactions entirely completed failed
-- NEED RESULT: P6: Inertial transactions entirely completed failed
-- NEED RESULT: P5: Inertial transactions entirely completed failed
-- NEED RESULT: P4: Inertial transactions entirely completed failed
-- NEED RESULT: P3: Inertial transactions entirely completed failed
-- NEED RESULT: P2: Inertial transactions entirely completed failed
-- NEED RESULT: P1: Inertial transactions entirely completed failed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00145
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.3 (1)
-- 8.3 (2)
-- 8.3 (4)
-- 8.3 (5)
-- 8.3.1 (4)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00145(ARCH00145)
-- ENT00145_Test_Bench(ARCH00145_Test_Bench)
--
-- REVISION HISTORY:
--
-- 08-JUL-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
entity ENT00145 is
subtype chk_sig_type is integer range -1 to 100 ;
signal chk_st_boolean_vector : chk_sig_type := -1 ;
signal chk_st_bit_vector : chk_sig_type := -1 ;
signal chk_st_severity_level_vector : chk_sig_type := -1 ;
signal chk_st_string : chk_sig_type := -1 ;
signal chk_st_enum1_vector : chk_sig_type := -1 ;
signal chk_st_integer_vector : chk_sig_type := -1 ;
signal chk_st_int1_vector : chk_sig_type := -1 ;
signal chk_st_time_vector : chk_sig_type := -1 ;
signal chk_st_phys1_vector : chk_sig_type := -1 ;
signal chk_st_real_vector : chk_sig_type := -1 ;
signal chk_st_real1_vector : chk_sig_type := -1 ;
signal chk_st_rec1_vector : chk_sig_type := -1 ;
signal chk_st_rec2_vector : chk_sig_type := -1 ;
signal chk_st_rec3_vector : chk_sig_type := -1 ;
signal chk_st_arr1_vector : chk_sig_type := -1 ;
signal chk_st_arr2_vector : chk_sig_type := -1 ;
signal chk_st_arr3_vector : chk_sig_type := -1 ;
--
procedure Proc1 (
signal s_st_boolean_vector : inout st_boolean_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_boolean_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P1" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <= transport
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_boolean_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_boolean_vector (lowb+1 to lowb+3) <=
c_st_boolean_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_boolean_vector (lowb+1 to lowb+3) =
c_st_boolean_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_boolean_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc1 ;
--
procedure Proc2 (
signal s_st_bit_vector : inout st_bit_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_bit_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P2" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <= transport
c_st_bit_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_bit_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_bit_vector (lowb+1 to lowb+3) <=
c_st_bit_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_bit_vector (lowb+1 to lowb+3) =
c_st_bit_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_bit_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc2 ;
--
procedure Proc3 (
signal s_st_severity_level_vector : inout st_severity_level_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_severity_level_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P3" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <= transport
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_severity_level_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_severity_level_vector (lowb+1 to lowb+3) <=
c_st_severity_level_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_severity_level_vector (lowb+1 to lowb+3) =
c_st_severity_level_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_severity_level_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc3 ;
--
procedure Proc4 (
signal s_st_string : inout st_string ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_string : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P4" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <= transport
c_st_string_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_string (lowb+1 to lowb+3) <=
c_st_string_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_string_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_string (lowb+1 to lowb+3) <=
c_st_string_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_string (lowb+1 to lowb+3) =
c_st_string_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_string <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc4 ;
--
procedure Proc5 (
signal s_st_enum1_vector : inout st_enum1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_enum1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P5" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <= transport
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_enum1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_enum1_vector (lowb+1 to lowb+3) <=
c_st_enum1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_enum1_vector (lowb+1 to lowb+3) =
c_st_enum1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_enum1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc5 ;
--
procedure Proc6 (
signal s_st_integer_vector : inout st_integer_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_integer_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P6" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <= transport
c_st_integer_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_integer_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_integer_vector (lowb+1 to lowb+3) <=
c_st_integer_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_integer_vector (lowb+1 to lowb+3) =
c_st_integer_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_integer_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc6 ;
--
procedure Proc7 (
signal s_st_int1_vector : inout st_int1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_int1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P7" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <= transport
c_st_int1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_int1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_int1_vector (lowb+1 to lowb+3) <=
c_st_int1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_int1_vector (lowb+1 to lowb+3) =
c_st_int1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_int1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc7 ;
--
procedure Proc8 (
signal s_st_time_vector : inout st_time_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_time_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P8" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <= transport
c_st_time_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_time_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_time_vector (lowb+1 to lowb+3) <=
c_st_time_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_time_vector (lowb+1 to lowb+3) =
c_st_time_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_time_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc8 ;
--
procedure Proc9 (
signal s_st_phys1_vector : inout st_phys1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_phys1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P9" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <= transport
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_phys1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_phys1_vector (lowb+1 to lowb+3) <=
c_st_phys1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_phys1_vector (lowb+1 to lowb+3) =
c_st_phys1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_phys1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc9 ;
--
procedure Proc10 (
signal s_st_real_vector : inout st_real_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P10" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <= transport
c_st_real_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real_vector (lowb+1 to lowb+3) <=
c_st_real_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real_vector (lowb+1 to lowb+3) =
c_st_real_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc10 ;
--
procedure Proc11 (
signal s_st_real1_vector : inout st_real1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_real1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P11" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <= transport
c_st_real1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_real1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_real1_vector (lowb+1 to lowb+3) <=
c_st_real1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_real1_vector (lowb+1 to lowb+3) =
c_st_real1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_real1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc11 ;
--
procedure Proc12 (
signal s_st_rec1_vector : inout st_rec1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P12" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <= transport
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec1_vector (lowb+1 to lowb+3) <=
c_st_rec1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec1_vector (lowb+1 to lowb+3) =
c_st_rec1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc12 ;
--
procedure Proc13 (
signal s_st_rec2_vector : inout st_rec2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P13" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <= transport
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec2_vector (lowb+1 to lowb+3) <=
c_st_rec2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec2_vector (lowb+1 to lowb+3) =
c_st_rec2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc13 ;
--
procedure Proc14 (
signal s_st_rec3_vector : inout st_rec3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_rec3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P14" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <= transport
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_rec3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_rec3_vector (lowb+1 to lowb+3) <=
c_st_rec3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_rec3_vector (lowb+1 to lowb+3) =
c_st_rec3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_rec3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc14 ;
--
procedure Proc15 (
signal s_st_arr1_vector : inout st_arr1_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr1_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P15" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <= transport
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr1_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr1_vector (lowb+1 to lowb+3) <=
c_st_arr1_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr1_vector (lowb+1 to lowb+3) =
c_st_arr1_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr1_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc15 ;
--
procedure Proc16 (
signal s_st_arr2_vector : inout st_arr2_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr2_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P16" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <= transport
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr2_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr2_vector (lowb+1 to lowb+3) <=
c_st_arr2_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr2_vector (lowb+1 to lowb+3) =
c_st_arr2_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr2_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc16 ;
--
procedure Proc17 (
signal s_st_arr3_vector : inout st_arr3_vector ;
variable counter : inout integer ;
variable correct : inout boolean ;
variable savtime : inout time ;
signal chk_st_arr3_vector : out chk_sig_type
)
is
begin
case counter is
when 0
=> s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ;
--
when 1
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
--
when 2
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145.P17" ,
"Multi inertial transactions occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 3
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 5 ns ;
--
when 4
=> correct :=
correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 5 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <= transport
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 100 ns ;
--
when 5
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 100 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Old transactions were removed on signal " &
"asg with slice name on LHS",
correct ) ;
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 10 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 20 ns ,
c_st_arr3_vector_2 (lowb+1 to lowb+3) after 30 ns ,
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 6
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_2 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"One inertial transaction occurred on signal " &
"asg with slice name on LHS",
correct ) ;
-- Last transaction above is marked by following
s_st_arr3_vector (lowb+1 to lowb+3) <=
c_st_arr3_vector_1 (lowb+1 to lowb+3) after 40 ns ;
--
when 7
=> correct :=
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 30 ns) = Std.Standard.Now ;
--
when 8
=> correct := correct and
s_st_arr3_vector (lowb+1 to lowb+3) =
c_st_arr3_vector_1 (lowb+1 to lowb+3) and
(savtime + 10 ns) = Std.Standard.Now ;
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
correct ) ;
--
when others
=>
test_report ( "ARCH00145" ,
"Inertial semantics check on a signal " &
"asg with slice name on LHS",
false ) ;
--
end case ;
--
savtime := Std.Standard.Now ;
chk_st_arr3_vector <= transport counter after (1 us - savtime) ;
counter := counter + 1;
--
end Proc17 ;
--
--
end ENT00145 ;
--
architecture ARCH00145 of ENT00145 is
signal s_st_boolean_vector : st_boolean_vector
:= c_st_boolean_vector_1 ;
signal s_st_bit_vector : st_bit_vector
:= c_st_bit_vector_1 ;
signal s_st_severity_level_vector : st_severity_level_vector
:= c_st_severity_level_vector_1 ;
signal s_st_string : st_string
:= c_st_string_1 ;
signal s_st_enum1_vector : st_enum1_vector
:= c_st_enum1_vector_1 ;
signal s_st_integer_vector : st_integer_vector
:= c_st_integer_vector_1 ;
signal s_st_int1_vector : st_int1_vector
:= c_st_int1_vector_1 ;
signal s_st_time_vector : st_time_vector
:= c_st_time_vector_1 ;
signal s_st_phys1_vector : st_phys1_vector
:= c_st_phys1_vector_1 ;
signal s_st_real_vector : st_real_vector
:= c_st_real_vector_1 ;
signal s_st_real1_vector : st_real1_vector
:= c_st_real1_vector_1 ;
signal s_st_rec1_vector : st_rec1_vector
:= c_st_rec1_vector_1 ;
signal s_st_rec2_vector : st_rec2_vector
:= c_st_rec2_vector_1 ;
signal s_st_rec3_vector : st_rec3_vector
:= c_st_rec3_vector_1 ;
signal s_st_arr1_vector : st_arr1_vector
:= c_st_arr1_vector_1 ;
signal s_st_arr2_vector : st_arr2_vector
:= c_st_arr2_vector_1 ;
signal s_st_arr3_vector : st_arr3_vector
:= c_st_arr3_vector_1 ;
--
begin
P1 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc1 (
s_st_boolean_vector,
counter,
correct,
savtime,
chk_st_boolean_vector
) ;
wait until (not s_st_boolean_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P1 ;
--
PGEN_CHKP_1 :
process ( chk_st_boolean_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P1" ,
"Inertial transactions entirely completed",
chk_st_boolean_vector = 8 ) ;
end if ;
end process PGEN_CHKP_1 ;
--
P2 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc2 (
s_st_bit_vector,
counter,
correct,
savtime,
chk_st_bit_vector
) ;
wait until (not s_st_bit_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P2 ;
--
PGEN_CHKP_2 :
process ( chk_st_bit_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P2" ,
"Inertial transactions entirely completed",
chk_st_bit_vector = 8 ) ;
end if ;
end process PGEN_CHKP_2 ;
--
P3 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc3 (
s_st_severity_level_vector,
counter,
correct,
savtime,
chk_st_severity_level_vector
) ;
wait until (not s_st_severity_level_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P3 ;
--
PGEN_CHKP_3 :
process ( chk_st_severity_level_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P3" ,
"Inertial transactions entirely completed",
chk_st_severity_level_vector = 8 ) ;
end if ;
end process PGEN_CHKP_3 ;
--
P4 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc4 (
s_st_string,
counter,
correct,
savtime,
chk_st_string
) ;
wait until (not s_st_string'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P4 ;
--
PGEN_CHKP_4 :
process ( chk_st_string )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P4" ,
"Inertial transactions entirely completed",
chk_st_string = 8 ) ;
end if ;
end process PGEN_CHKP_4 ;
--
P5 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc5 (
s_st_enum1_vector,
counter,
correct,
savtime,
chk_st_enum1_vector
) ;
wait until (not s_st_enum1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P5 ;
--
PGEN_CHKP_5 :
process ( chk_st_enum1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P5" ,
"Inertial transactions entirely completed",
chk_st_enum1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_5 ;
--
P6 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc6 (
s_st_integer_vector,
counter,
correct,
savtime,
chk_st_integer_vector
) ;
wait until (not s_st_integer_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P6 ;
--
PGEN_CHKP_6 :
process ( chk_st_integer_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P6" ,
"Inertial transactions entirely completed",
chk_st_integer_vector = 8 ) ;
end if ;
end process PGEN_CHKP_6 ;
--
P7 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc7 (
s_st_int1_vector,
counter,
correct,
savtime,
chk_st_int1_vector
) ;
wait until (not s_st_int1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P7 ;
--
PGEN_CHKP_7 :
process ( chk_st_int1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P7" ,
"Inertial transactions entirely completed",
chk_st_int1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_7 ;
--
P8 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc8 (
s_st_time_vector,
counter,
correct,
savtime,
chk_st_time_vector
) ;
wait until (not s_st_time_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P8 ;
--
PGEN_CHKP_8 :
process ( chk_st_time_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P8" ,
"Inertial transactions entirely completed",
chk_st_time_vector = 8 ) ;
end if ;
end process PGEN_CHKP_8 ;
--
P9 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc9 (
s_st_phys1_vector,
counter,
correct,
savtime,
chk_st_phys1_vector
) ;
wait until (not s_st_phys1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P9 ;
--
PGEN_CHKP_9 :
process ( chk_st_phys1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P9" ,
"Inertial transactions entirely completed",
chk_st_phys1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_9 ;
--
P10 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc10 (
s_st_real_vector,
counter,
correct,
savtime,
chk_st_real_vector
) ;
wait until (not s_st_real_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P10 ;
--
PGEN_CHKP_10 :
process ( chk_st_real_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P10" ,
"Inertial transactions entirely completed",
chk_st_real_vector = 8 ) ;
end if ;
end process PGEN_CHKP_10 ;
--
P11 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc11 (
s_st_real1_vector,
counter,
correct,
savtime,
chk_st_real1_vector
) ;
wait until (not s_st_real1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P11 ;
--
PGEN_CHKP_11 :
process ( chk_st_real1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P11" ,
"Inertial transactions entirely completed",
chk_st_real1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_11 ;
--
P12 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc12 (
s_st_rec1_vector,
counter,
correct,
savtime,
chk_st_rec1_vector
) ;
wait until (not s_st_rec1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P12 ;
--
PGEN_CHKP_12 :
process ( chk_st_rec1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P12" ,
"Inertial transactions entirely completed",
chk_st_rec1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_12 ;
--
P13 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc13 (
s_st_rec2_vector,
counter,
correct,
savtime,
chk_st_rec2_vector
) ;
wait until (not s_st_rec2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P13 ;
--
PGEN_CHKP_13 :
process ( chk_st_rec2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P13" ,
"Inertial transactions entirely completed",
chk_st_rec2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_13 ;
--
P14 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc14 (
s_st_rec3_vector,
counter,
correct,
savtime,
chk_st_rec3_vector
) ;
wait until (not s_st_rec3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P14 ;
--
PGEN_CHKP_14 :
process ( chk_st_rec3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P14" ,
"Inertial transactions entirely completed",
chk_st_rec3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_14 ;
--
P15 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc15 (
s_st_arr1_vector,
counter,
correct,
savtime,
chk_st_arr1_vector
) ;
wait until (not s_st_arr1_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P15 ;
--
PGEN_CHKP_15 :
process ( chk_st_arr1_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P15" ,
"Inertial transactions entirely completed",
chk_st_arr1_vector = 8 ) ;
end if ;
end process PGEN_CHKP_15 ;
--
P16 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc16 (
s_st_arr2_vector,
counter,
correct,
savtime,
chk_st_arr2_vector
) ;
wait until (not s_st_arr2_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P16 ;
--
PGEN_CHKP_16 :
process ( chk_st_arr2_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P16" ,
"Inertial transactions entirely completed",
chk_st_arr2_vector = 8 ) ;
end if ;
end process PGEN_CHKP_16 ;
--
P17 :
process
variable counter : integer := 0 ;
variable correct : boolean ;
variable savtime : time ;
begin
Proc17 (
s_st_arr3_vector,
counter,
correct,
savtime,
chk_st_arr3_vector
) ;
wait until (not s_st_arr3_vector'Quiet) and
(savtime /= Std.Standard.Now) ;
--
end process P17 ;
--
PGEN_CHKP_17 :
process ( chk_st_arr3_vector )
begin
if Std.Standard.Now > 0 ns then
test_report ( "P17" ,
"Inertial transactions entirely completed",
chk_st_arr3_vector = 8 ) ;
end if ;
end process PGEN_CHKP_17 ;
--
--
end ARCH00145 ;
--
entity ENT00145_Test_Bench is
end ENT00145_Test_Bench ;
--
architecture ARCH00145_Test_Bench of ENT00145_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.ENT00145 ( ARCH00145 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00145_Test_Bench ;
|
library ieee;
use ieee.std_logic_1164.all;
entity d_testbench is end d_testbench;
architecture behavioral of d_testbench is
component d_Latch
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
component d_flipflop
port (
clk : in std_logic;
d : in std_logic;
q : out std_logic
);
end component;
signal input, clk, output_latch, output_flipflop : std_logic := '0';
begin
input <=
'0',
'1' after 15 ns,
'0' after 65 ns,
'1' after 70 ns,
'0' after 75 ns,
'1' after 125 ns;
clk<=
'0',
'1' after 20 NS,
'0' after 40 NS,
'1' after 60 ns,
'0' after 80 ns,
'1' after 100 ns,
'0' after 120 ns;
uut1: d_latch port map(input, clk, output_latch);
uut2: d_flipflop port map(input, clk, output_flipflop);
END behavioral;
|
constant TRFSM0Length : integer := 820;
constant TRFSM0Cfg : std_logic_vector(TRFSM0Length-1 downto 0) := "0000100100000000101000010001010000000000000110001000000100001111100000000000000011111000000000000000111110000000000000001111100000000000000011111000000000000000111110000000000000001111100000000000000000000000001010000000001000000000000000110000110000010000001000000010100000000010000100100000001100001100000100010010100001001000010000001100001010000101000101000000000011111000000000000000000000001111100000000000000000000000111110000000000000000000000011111000000000000000000000001111100000000000000000000000001111100000000000000000000000001111100000000000000000000000001111100000000000000000000000001111100000000000000000000000000000111110000000000000000000000000000011111000000000000000000000000000001111100000000000000000000000000000111110000000000000000000000000000000000000111110000000000000000000000000000000000000";
|
elsif std_match(mem_dout, "00000000") then -- NOP
elsif std_match(mem_dout, "00000010") then -- LD (BC) A
elsif std_match(mem_dout, "00000111") then -- RLCA
elsif std_match(mem_dout, "00001000") then -- LD (d16) SP
elsif std_match(mem_dout, "00001010") then -- LD A (BC)
elsif std_match(mem_dout, "00001111") then -- RRCA
elsif std_match(mem_dout, "00010000") then -- STOP
elsif std_match(mem_dout, "00010010") then -- LD (DE) A
elsif std_match(mem_dout, "00010111") then -- RLA
elsif std_match(mem_dout, "00011000") then -- JR r8
elsif std_match(mem_dout, "00011010") then -- LD A (DE)
elsif std_match(mem_dout, "00011111") then -- RRA
elsif std_match(mem_dout, "00100010") then -- LD (HL++) A
elsif std_match(mem_dout, "00100111") then -- DDA
elsif std_match(mem_dout, "00101010") then -- LD A (HL++)
elsif std_match(mem_dout, "00101111") then -- CPL
elsif std_match(mem_dout, "00110010") then -- LD (HL--) A
elsif std_match(mem_dout, "00110100") then -- INC (HL)
elsif std_match(mem_dout, "00110101") then -- DEC (HL)
elsif std_match(mem_dout, "00110110") then -- LD (HL) d8
elsif std_match(mem_dout, "00110111") then -- SCF
elsif std_match(mem_dout, "00111010") then -- LD A (HL--)
elsif std_match(mem_dout, "00111111") then -- CCF
elsif std_match(mem_dout, "11000011") then -- JP d16
elsif std_match(mem_dout, "11001001") then -- RET
elsif std_match(mem_dout, "11001011") then -- CB
elsif std_match(mem_dout, "11001101") then -- CALL d16
elsif std_match(mem_dout, "11010011") then -- INVALID
elsif std_match(mem_dout, "11011001") then -- RETI
elsif std_match(mem_dout, "11011011") then -- INVALID
elsif std_match(mem_dout, "11011101") then -- INVALID
elsif std_match(mem_dout, "11100000") then -- LDH (d8) A
elsif std_match(mem_dout, "11100010") then -- LD (C) A
elsif std_match(mem_dout, "11100011") then -- INVALID
elsif std_match(mem_dout, "11100100") then -- INVALID
elsif std_match(mem_dout, "11101000") then -- ADD SP r8
elsif std_match(mem_dout, "11101001") then -- JP PC (HL)
elsif std_match(mem_dout, "11101010") then -- LD (d16) A
elsif std_match(mem_dout, "11101011") then -- INVALID
elsif std_match(mem_dout, "11101100") then -- INVALID
elsif std_match(mem_dout, "11101101") then -- INVALID
elsif std_match(mem_dout, "11110000") then -- LDH A (d8)
elsif std_match(mem_dout, "11110010") then -- LD A (C)
elsif std_match(mem_dout, "11110011") then -- DI
elsif std_match(mem_dout, "11110100") then -- INVALID
elsif std_match(mem_dout, "11111000") then -- LD HL SP + r8
elsif std_match(mem_dout, "11111001") then -- LD SP HL
elsif std_match(mem_dout, "11111010") then -- LD A (d16)
elsif std_match(mem_dout, "11111011") then -- EI
elsif std_match(mem_dout, "11111100") then -- INVALID
elsif std_match(mem_dout, "11111101") then -- INVALID
elsif std_match(mem_dout, "01110110") then -- HALT
elsif std_match(mem_dout, "01110---") then -- LD (HL) r'
elsif std_match(mem_dout, "001--000") then -- JR cc r8
elsif std_match(mem_dout, "110--000") then -- RET cc
elsif std_match(mem_dout, "110--010") then -- JP cc d16
elsif std_match(mem_dout, "110--100") then -- CALL cc d16
elsif std_match(mem_dout, "00--0001") then -- LD dd d16
elsif std_match(mem_dout, "00--0011") then -- INC ss
elsif std_match(mem_dout, "00--1001") then -- ADD HL ss
elsif std_match(mem_dout, "00--1011") then -- DEC ss
elsif std_match(mem_dout, "11--0001") then -- POP qq
elsif std_match(mem_dout, "11--0101") then -- PUSH qq
elsif std_match(mem_dout, "00---100") then -- INC r
elsif std_match(mem_dout, "00---101") then -- DEC r
elsif std_match(mem_dout, "00---110") then -- LD r n
elsif std_match(mem_dout, "01---110") then -- LD r (HL)
elsif std_match(mem_dout, "10---110") then -- f A (HL)
elsif std_match(mem_dout, "11---110") then -- f A n
elsif std_match(mem_dout, "11---111") then -- RST t
elsif std_match(mem_dout, "01------") then -- LD r r'
elsif std_match(mem_dout, "10------") then -- f A r'
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:46:34 05/19/2016
-- Design Name:
-- Module Name: RAM_single_port - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity RAM_single_port is
Port ( clk : in STD_LOGIC;
data_write : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(11 downto 0);
ADDR : in STD_LOGIC_VECTOR (16 downto 0);
data_out : out STD_LOGIC_VECTOR (11 downto 0));
end RAM_single_port;
architecture Behavioral of RAM_single_port is
constant ADDR_WIDTH : integer := 16;
constant DATA_WIDTH : integer := 12;
-- Graphic RAM type. this object is the content of the displayed image
type GRAM is array (0 to 76799) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal screen : GRAM;-- := ram_function_name("../mandelbrot.bin"); -- the memory representation of the image
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (data_write = '1') then
screen(to_integer(unsigned(ADDR))) <= data_in;
data_out <= data_in;
else
data_out <= screen(to_integer(unsigned(ADDR)));
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc335.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00335ent IS
END c03s02b01x00p06n01i00335ent;
ARCHITECTURE c03s02b01x00p06n01i00335arch OF c03s02b01x00p06n01i00335ent IS
type bit_vctor is array (1 to 1) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1) := 56;
assert NOT(k(1)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00335"
severity NOTE;
assert (k(1)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00335 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00335arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc335.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00335ent IS
END c03s02b01x00p06n01i00335ent;
ARCHITECTURE c03s02b01x00p06n01i00335arch OF c03s02b01x00p06n01i00335ent IS
type bit_vctor is array (1 to 1) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1) := 56;
assert NOT(k(1)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00335"
severity NOTE;
assert (k(1)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00335 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00335arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc335.vhd,v 1.2 2001-10-26 16:29:53 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b01x00p06n01i00335ent IS
END c03s02b01x00p06n01i00335ent;
ARCHITECTURE c03s02b01x00p06n01i00335arch OF c03s02b01x00p06n01i00335ent IS
type bit_vctor is array (1 to 1) of integer;
BEGIN
TESTING: PROCESS
variable k :bit_vctor;
BEGIN
k(1) := 56;
assert NOT(k(1)=56)
report "***PASSED TEST: c03s02b01x00p06n01i00335"
severity NOTE;
assert (k(1)=56)
report "***FAILED TEST: c03s02b01x00p06n01i00335 - The index constraint is a list of discrete ranges enclosed within parentheses."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x00p06n01i00335arch;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 10:48:18 11/17/2016
-- Design Name:
-- Module Name: USB_Controller - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity USB_Controller is
Port(
clk : IN STD_LOGIC; -- clock input
rx : INOUT STD_LOGIC_VECTOR (7 downto 0); -- Byte that CPU will receive
tx : INOUT STD_LOGIC_VECTOR (7 downto 0); -- Byte that CPU will output
data : INOUT STD_LOGIC_VECTOR (7 downto 0); -- Data that is used to send or that has been received
USB_command : IN STD_LOGIC_VECTOR (3 downto 0) -- 4bit command that tells CPU to send or to receive data
);
end USB_Controller;
architecture Behavioral of USB_Controller is
begin
USB_Process : process (clk)
begin
if clk = '1' and clk'event then
if USB_command = "0001" then -- send data
tx <= data;
elsif USB_command = "0010" then -- receive data
rx <= data;
end if;
end if;
end process;
end Behavioral;
|
--------------------------------------------------------------------------------
--
-- BLK MEM GEN v7.1 Core - Top-level wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2006-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--------------------------------------------------------------------------------
--
-- Filename: k7_bram4096x64_prod.vhd
--
-- Description:
-- This is the top-level BMG wrapper (over BMG core).
--
--------------------------------------------------------------------------------
-- Author: IP Solutions Division
--
-- History: August 31, 2005 - First Release
--------------------------------------------------------------------------------
--
-- Configured Core Parameter Values:
-- (Refer to the SIM Parameters table in the datasheet for more information on
-- the these parameters.)
-- C_FAMILY : kintex7
-- C_XDEVICEFAMILY : kintex7
-- C_INTERFACE_TYPE : 0
-- C_ENABLE_32BIT_ADDRESS : 0
-- C_AXI_TYPE : 1
-- C_AXI_SLAVE_TYPE : 0
-- C_AXI_ID_WIDTH : 4
-- C_MEM_TYPE : 2
-- C_BYTE_SIZE : 8
-- C_ALGORITHM : 1
-- C_PRIM_TYPE : 1
-- C_LOAD_INIT_FILE : 0
-- C_INIT_FILE_NAME : no_coe_file_loaded
-- C_USE_DEFAULT_DATA : 0
-- C_DEFAULT_DATA : 0
-- C_RST_TYPE : SYNC
-- C_HAS_RSTA : 0
-- C_RST_PRIORITY_A : CE
-- C_RSTRAM_A : 0
-- C_INITA_VAL : 0
-- C_HAS_ENA : 0
-- C_HAS_REGCEA : 0
-- C_USE_BYTE_WEA : 1
-- C_WEA_WIDTH : 8
-- C_WRITE_MODE_A : WRITE_FIRST
-- C_WRITE_WIDTH_A : 64
-- C_READ_WIDTH_A : 64
-- C_WRITE_DEPTH_A : 4096
-- C_READ_DEPTH_A : 4096
-- C_ADDRA_WIDTH : 12
-- C_HAS_RSTB : 0
-- C_RST_PRIORITY_B : CE
-- C_RSTRAM_B : 0
-- C_INITB_VAL : 0
-- C_HAS_ENB : 0
-- C_HAS_REGCEB : 0
-- C_USE_BYTE_WEB : 1
-- C_WEB_WIDTH : 8
-- C_WRITE_MODE_B : WRITE_FIRST
-- C_WRITE_WIDTH_B : 64
-- C_READ_WIDTH_B : 64
-- C_WRITE_DEPTH_B : 4096
-- C_READ_DEPTH_B : 4096
-- C_ADDRB_WIDTH : 12
-- C_HAS_MEM_OUTPUT_REGS_A : 0
-- C_HAS_MEM_OUTPUT_REGS_B : 1
-- C_HAS_MUX_OUTPUT_REGS_A : 0
-- C_HAS_MUX_OUTPUT_REGS_B : 0
-- C_HAS_SOFTECC_INPUT_REGS_A : 0
-- C_HAS_SOFTECC_OUTPUT_REGS_B : 0
-- C_MUX_PIPELINE_STAGES : 0
-- C_USE_ECC : 0
-- C_USE_SOFTECC : 0
-- C_HAS_INJECTERR : 0
-- C_SIM_COLLISION_CHECK : ALL
-- C_COMMON_CLK : 0
-- C_DISABLE_WARN_BHV_COLL : 0
-- C_DISABLE_WARN_BHV_RANGE : 0
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY UNISIM;
USE UNISIM.VCOMPONENTS.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY k7_bram4096x64_prod IS
PORT (
--Port A
CLKA : IN STD_LOGIC;
RSTA : IN STD_LOGIC; --opt port
ENA : IN STD_LOGIC; --optional port
REGCEA : IN STD_LOGIC; --optional port
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--Port B
CLKB : IN STD_LOGIC;
RSTB : IN STD_LOGIC; --opt port
ENB : IN STD_LOGIC; --optional port
REGCEB : IN STD_LOGIC; --optional port
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
--ECC
INJECTSBITERR : IN STD_LOGIC; --optional port
INJECTDBITERR : IN STD_LOGIC; --optional port
SBITERR : OUT STD_LOGIC; --optional port
DBITERR : OUT STD_LOGIC; --optional port
RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0); --optional port
-- AXI BMG Input and Output Port Declarations
-- AXI Global Signals
S_ACLK : IN STD_LOGIC;
S_AXI_AWID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_AWADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_AWLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_AWSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_AWBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_AWVALID : IN STD_LOGIC;
S_AXI_AWREADY : OUT STD_LOGIC;
S_AXI_WDATA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_WSTRB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_WLAST : IN STD_LOGIC;
S_AXI_WVALID : IN STD_LOGIC;
S_AXI_WREADY : OUT STD_LOGIC;
S_AXI_BID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_BRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_BVALID : OUT STD_LOGIC;
S_AXI_BREADY : IN STD_LOGIC;
-- AXI Full/Lite Slave Read (Write side)
S_AXI_ARID : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
S_AXI_ARADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S_AXI_ARLEN : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
S_AXI_ARSIZE : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
S_AXI_ARBURST : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_ARVALID : IN STD_LOGIC;
S_AXI_ARREADY : OUT STD_LOGIC;
S_AXI_RID : OUT STD_LOGIC_VECTOR(3 DOWNTO 0):= (OTHERS => '0');
S_AXI_RDATA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
S_AXI_RRESP : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
S_AXI_RLAST : OUT STD_LOGIC;
S_AXI_RVALID : OUT STD_LOGIC;
S_AXI_RREADY : IN STD_LOGIC;
-- AXI Full/Lite Sideband Signals
S_AXI_INJECTSBITERR : IN STD_LOGIC;
S_AXI_INJECTDBITERR : IN STD_LOGIC;
S_AXI_SBITERR : OUT STD_LOGIC;
S_AXI_DBITERR : OUT STD_LOGIC;
S_AXI_RDADDRECC : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
S_ARESETN : IN STD_LOGIC
);
END k7_bram4096x64_prod;
ARCHITECTURE xilinx OF k7_bram4096x64_prod IS
COMPONENT k7_bram4096x64_exdes IS
PORT (
--Port A
WEA : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRA : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINA : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTA : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKA : IN STD_LOGIC;
--Port B
WEB : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
ADDRB : IN STD_LOGIC_VECTOR(11 DOWNTO 0);
DINB : IN STD_LOGIC_VECTOR(63 DOWNTO 0);
DOUTB : OUT STD_LOGIC_VECTOR(63 DOWNTO 0);
CLKB : IN STD_LOGIC
);
END COMPONENT;
BEGIN
bmg0 : k7_bram4096x64_exdes
PORT MAP (
--Port A
WEA => WEA,
ADDRA => ADDRA,
DINA => DINA,
DOUTA => DOUTA,
CLKA => CLKA,
--Port B
WEB => WEB,
ADDRB => ADDRB,
DINB => DINB,
DOUTB => DOUTB,
CLKB => CLKB
);
END xilinx;
|
---------------------------------------------------------------
-- Title : Altera remote update controller model
-- Project : -
---------------------------------------------------------------
-- Author : Andreas Geissler
-- Email : [email protected]
-- Organization : MEN Mikro Elektronik Nuremberg GmbH
-- Created : 05/02/14
---------------------------------------------------------------
-- Simulator : ModelSim-Altera PE 6.4c
-- Synthesis : Quartus II 12.1 SP2
---------------------------------------------------------------
-- Description :
--
---------------------------------------------------------------
-- Hierarchy:
--
---------------------------------------------------------------
-- Copyright (C) 2014, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: $
--
-- $Log: $
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
LIBRARY work;
USE work.fpga_pkg_2.all;
ENTITY z126_01_ru_cycloneiii IS
PORT (
clock : IN std_logic ;
data_in : IN std_logic_vector (23 DOWNTO 0);
param : IN std_logic_vector (2 DOWNTO 0);
read_param : IN std_logic ;
read_source : IN std_logic_vector (1 DOWNTO 0);
reconfig : IN std_logic ;
reset : IN std_logic ;
reset_timer : IN std_logic ;
write_param : IN std_logic ;
busy : OUT std_logic ;
data_out : OUT std_logic_vector (28 DOWNTO 0)
);
END z126_01_ru_cycloneiii;
ARCHITECTURE z126_01_ru_cycloneiii_arch OF z126_01_ru_cycloneiii IS
BEGIN
busy_p: PROCESS
BEGIN
WAIT UNTIL rising_edge(clock) OR reset = '1';
IF reset = '1' THEN
busy <= '0';
ELSIF read_param = '1' OR read_param = '1' THEN
WAIT FOR 100 ns;
WAIT UNTIL rising_edge(clock);
busy <= '1';
WAIT FOR 600 ns;
WAIT UNTIL rising_edge(clock);
busy <= '0';
END IF;
END PROCESS;
data_out <= (OTHERS => '0');
END z126_01_ru_cycloneiii_arch; |
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
-- Version 1.2 - 4th October 2012.
-- Addition of WebTalk information.
-- Version 1.3 - 21st May 2014.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
attribute hblknm : string;
attribute hblknm of reset_lut : label is "kcpsm6_control";
attribute hblknm of run_flop : label is "kcpsm6_control";
attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
attribute hblknm of t_state_lut : label is "kcpsm6_control";
attribute hblknm of t_state1_flop : label is "kcpsm6_control";
attribute hblknm of t_state2_flop : label is "kcpsm6_control";
attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_flop : label is "kcpsm6_stack1";
attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
attribute hblknm : string;
attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
attribute hblknm : string;
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
attribute hblknm : string;
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
-- Version 1.2 - 4th October 2012.
-- Addition of WebTalk information.
-- Version 1.3 - 21st May 2014.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
attribute hblknm : string;
attribute hblknm of reset_lut : label is "kcpsm6_control";
attribute hblknm of run_flop : label is "kcpsm6_control";
attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
attribute hblknm of t_state_lut : label is "kcpsm6_control";
attribute hblknm of t_state1_flop : label is "kcpsm6_control";
attribute hblknm of t_state2_flop : label is "kcpsm6_control";
attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_flop : label is "kcpsm6_stack1";
attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
attribute hblknm : string;
attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
attribute hblknm : string;
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
attribute hblknm : string;
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
-- KCPSM6 - PicoBlaze for Spartan-6 and Virtex-6 devices.
--
-- Start of design entry - 14th May 2010.
-- Alpha Version - 20th July 2010.
-- Version 1.0 - 30th September 2010.
-- Version 1.1 - 9th February 2011.
-- Correction to parity computation logic.
-- Version 1.2 - 4th October 2012.
-- Addition of WebTalk information.
-- Version 1.3 - 21st May 2014.
-- Disassembly of 'STAR sX, kk' instruction added to the simulation
-- code. No changes to functionality or the physical implementation.
--
-- Ken Chapman
-- Xilinx Ltd
-- Benchmark House
-- 203 Brooklands Road
-- Weybridge
-- Surrey KT13 ORH
-- United Kingdom
--
-- [email protected]
--
-------------------------------------------------------------------------------------------
--
-- Format of this file.
--
-- The module defines the implementation of the logic using Xilinx primitives.
-- These ensure predictable synthesis results and maximise the density of the implementation.
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
-- Main Entity for kcpsm6
--
entity kcpsm6 is
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end kcpsm6;
--
-------------------------------------------------------------------------------------------
--
-- Start of Main Architecture for kcpsm6
--
architecture low_level_definition of kcpsm6 is
--
-------------------------------------------------------------------------------------------
--
-- Signals used in kcpsm6
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Interrupt
--
signal t_state_value : std_logic_vector(2 downto 1);
signal t_state : std_logic_vector(2 downto 1);
signal run_value : std_logic;
signal run : std_logic;
signal internal_reset_value : std_logic;
signal internal_reset : std_logic;
signal sync_sleep : std_logic;
signal int_enable_type : std_logic;
signal interrupt_enable_value : std_logic;
signal interrupt_enable : std_logic;
signal sync_interrupt : std_logic;
signal active_interrupt_value : std_logic;
signal active_interrupt : std_logic;
--
-- Arithmetic and Logical Functions
--
signal arith_logical_sel : std_logic_vector(2 downto 0);
signal arith_carry_in : std_logic;
signal arith_carry_value : std_logic;
signal arith_carry : std_logic;
signal half_arith_logical : std_logic_vector(7 downto 0);
signal logical_carry_mask : std_logic_vector(7 downto 0);
signal carry_arith_logical : std_logic_vector(7 downto 0);
signal arith_logical_value : std_logic_vector(7 downto 0);
signal arith_logical_result : std_logic_vector(7 downto 0);
--
-- Shift and Rotate Functions
--
signal shift_rotate_value : std_logic_vector(7 downto 0);
signal shift_rotate_result : std_logic_vector(7 downto 0);
signal shift_in_bit : std_logic;
--
-- ALU structure
--
signal alu_result : std_logic_vector(7 downto 0);
signal alu_mux_sel_value : std_logic_vector(1 downto 0);
signal alu_mux_sel : std_logic_vector(1 downto 0);
--
-- Strobes
--
signal strobe_type : std_logic;
signal write_strobe_value : std_logic;
signal k_write_strobe_value : std_logic;
signal read_strobe_value : std_logic;
--
-- Flags
--
signal flag_enable_type : std_logic;
signal flag_enable_value : std_logic;
signal flag_enable : std_logic;
signal lower_parity : std_logic;
signal lower_parity_sel : std_logic;
signal carry_lower_parity : std_logic;
signal upper_parity : std_logic;
signal parity : std_logic;
signal shift_carry_value : std_logic;
signal shift_carry : std_logic;
signal carry_flag_value : std_logic;
signal carry_flag : std_logic;
signal use_zero_flag_value : std_logic;
signal use_zero_flag : std_logic;
signal drive_carry_in_zero : std_logic;
signal carry_in_zero : std_logic;
signal lower_zero : std_logic;
signal lower_zero_sel : std_logic;
signal carry_lower_zero : std_logic;
signal middle_zero : std_logic;
signal middle_zero_sel : std_logic;
signal carry_middle_zero : std_logic;
signal upper_zero_sel : std_logic;
signal zero_flag_value : std_logic;
signal zero_flag : std_logic;
--
-- Scratch Pad Memory
--
signal spm_enable_value : std_logic;
signal spm_enable : std_logic;
signal spm_ram_data : std_logic_vector(7 downto 0);
signal spm_data : std_logic_vector(7 downto 0);
--
-- Registers
--
signal regbank_type : std_logic;
signal bank_value : std_logic;
signal bank : std_logic;
signal loadstar_type : std_logic;
signal sx_addr4_value : std_logic;
signal register_enable_type : std_logic;
signal register_enable_value : std_logic;
signal register_enable : std_logic;
signal sx_addr : std_logic_vector(4 downto 0);
signal sy_addr : std_logic_vector(4 downto 0);
signal sx : std_logic_vector(7 downto 0);
signal sy : std_logic_vector(7 downto 0);
--
-- Second Operand
--
signal sy_or_kk : std_logic_vector(7 downto 0);
--
-- Program Counter
--
signal pc_move_is_valid : std_logic;
signal move_type : std_logic;
signal returni_type : std_logic;
signal pc_mode : std_logic_vector(2 downto 0);
signal register_vector : std_logic_vector(11 downto 0);
signal half_pc : std_logic_vector(11 downto 0);
signal carry_pc : std_logic_vector(10 downto 0);
signal pc_value : std_logic_vector(11 downto 0);
signal pc : std_logic_vector(11 downto 0);
signal pc_vector : std_logic_vector(11 downto 0);
--
-- Program Counter Stack
--
signal push_stack : std_logic;
signal pop_stack : std_logic;
signal stack_memory : std_logic_vector(11 downto 0);
signal return_vector : std_logic_vector(11 downto 0);
signal stack_carry_flag : std_logic;
signal shadow_carry_flag : std_logic;
signal stack_zero_flag : std_logic;
signal shadow_zero_value : std_logic;
signal shadow_zero_flag : std_logic;
signal stack_bank : std_logic;
signal shadow_bank : std_logic;
signal stack_bit : std_logic;
signal special_bit : std_logic;
signal half_pointer_value : std_logic_vector(4 downto 0);
signal feed_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer_carry : std_logic_vector(4 downto 0);
signal stack_pointer_value : std_logic_vector(4 downto 0);
signal stack_pointer : std_logic_vector(4 downto 0);
--
--
--
--**********************************************************************************
--
-- Signals between these *** lines are only made visible during simulation
--
--synthesis translate off
--
signal kcpsm6_opcode : string(1 to 19):= "LOAD s0, s0 ";
signal kcpsm6_status : string(1 to 16):= "A,NZ,NC,ID,Reset";
signal sim_s0 : std_logic_vector(7 downto 0);
signal sim_s1 : std_logic_vector(7 downto 0);
signal sim_s2 : std_logic_vector(7 downto 0);
signal sim_s3 : std_logic_vector(7 downto 0);
signal sim_s4 : std_logic_vector(7 downto 0);
signal sim_s5 : std_logic_vector(7 downto 0);
signal sim_s6 : std_logic_vector(7 downto 0);
signal sim_s7 : std_logic_vector(7 downto 0);
signal sim_s8 : std_logic_vector(7 downto 0);
signal sim_s9 : std_logic_vector(7 downto 0);
signal sim_sA : std_logic_vector(7 downto 0);
signal sim_sB : std_logic_vector(7 downto 0);
signal sim_sC : std_logic_vector(7 downto 0);
signal sim_sD : std_logic_vector(7 downto 0);
signal sim_sE : std_logic_vector(7 downto 0);
signal sim_sF : std_logic_vector(7 downto 0);
signal sim_spm00 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm01 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm02 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm03 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm04 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm05 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm06 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm07 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm08 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm09 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm0F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm10 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm11 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm12 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm13 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm14 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm15 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm16 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm17 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm18 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm19 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm1F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm20 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm21 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm22 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm23 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm24 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm25 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm26 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm27 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm28 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm29 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm2F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm30 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm31 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm32 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm33 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm34 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm35 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm36 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm37 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm38 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm39 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm3F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm40 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm41 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm42 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm43 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm44 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm45 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm46 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm47 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm48 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm49 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm4F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm50 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm51 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm52 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm53 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm54 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm55 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm56 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm57 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm58 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm59 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm5F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm60 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm61 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm62 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm63 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm64 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm65 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm66 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm67 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm68 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm69 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm6F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm70 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm71 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm72 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm73 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm74 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm75 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm76 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm77 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm78 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm79 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm7F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm80 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm81 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm82 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm83 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm84 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm85 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm86 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm87 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm88 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm89 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm8F : std_logic_vector(7 downto 0) := X"00";
signal sim_spm90 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm91 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm92 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm93 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm94 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm95 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm96 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm97 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm98 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm99 : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9A : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9B : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9C : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9D : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9E : std_logic_vector(7 downto 0) := X"00";
signal sim_spm9F : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmA9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmAF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmB9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmBF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmC9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmCF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmD9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmDF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmE9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmED : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmEF : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF0 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF1 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF2 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF3 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF4 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF5 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF6 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF7 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF8 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmF9 : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFA : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFB : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFC : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFD : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFE : std_logic_vector(7 downto 0) := X"00";
signal sim_spmFF : std_logic_vector(7 downto 0) := X"00";
--
--synthesis translate on
--
--**********************************************************************************
--
--
-------------------------------------------------------------------------------------------
--
-- WebTalk Attributes
--
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of low_level_definition : ARCHITECTURE IS
"kcpsm6,kcpsm6_v1_3,{component_name=kcpsm6}";
--
-- Attributes to guide mapping of logic into Slices.
--
attribute hblknm : string;
attribute hblknm of reset_lut : label is "kcpsm6_control";
attribute hblknm of run_flop : label is "kcpsm6_control";
attribute hblknm of internal_reset_flop : label is "kcpsm6_control";
attribute hblknm of t_state_lut : label is "kcpsm6_control";
attribute hblknm of t_state1_flop : label is "kcpsm6_control";
attribute hblknm of t_state2_flop : label is "kcpsm6_control";
attribute hblknm of active_interrupt_lut : label is "kcpsm6_control";
attribute hblknm of active_interrupt_flop : label is "kcpsm6_control";
attribute hblknm of sx_addr4_flop : label is "kcpsm6_control";
attribute hblknm of arith_carry_xorcy : label is "kcpsm6_control";
attribute hblknm of arith_carry_flop : label is "kcpsm6_control";
attribute hblknm of zero_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_flop : label is "kcpsm6_flags";
attribute hblknm of carry_flag_lut : label is "kcpsm6_flags";
attribute hblknm of lower_zero_lut : label is "kcpsm6_flags";
attribute hblknm of middle_zero_lut : label is "kcpsm6_flags";
attribute hblknm of upper_zero_lut : label is "kcpsm6_flags";
attribute hblknm of init_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of lower_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of middle_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of upper_zero_muxcy : label is "kcpsm6_flags";
attribute hblknm of int_enable_type_lut : label is "kcpsm6_decode0";
attribute hblknm of move_type_lut : label is "kcpsm6_decode0";
attribute hblknm of pc_move_is_valid_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_lut : label is "kcpsm6_decode0";
attribute hblknm of interrupt_enable_flop : label is "kcpsm6_decode0";
attribute hblknm of alu_decode1_lut : label is "kcpsm6_decode1";
attribute hblknm of alu_mux_sel1_flop : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_lut : label is "kcpsm6_decode1";
attribute hblknm of shift_carry_flop : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_lut : label is "kcpsm6_decode1";
attribute hblknm of use_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of interrupt_ack_flop : label is "kcpsm6_decode1";
attribute hblknm of shadow_zero_flag_flop : label is "kcpsm6_decode1";
attribute hblknm of alu_decode0_lut : label is "kcpsm6_decode2";
attribute hblknm of alu_mux_sel0_flop : label is "kcpsm6_decode2";
attribute hblknm of alu_decode2_lut : label is "kcpsm6_decode2";
attribute hblknm of lower_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_muxcy : label is "kcpsm6_decode2";
attribute hblknm of upper_parity_lut : label is "kcpsm6_decode2";
attribute hblknm of parity_xorcy : label is "kcpsm6_decode2";
attribute hblknm of sync_sleep_flop : label is "kcpsm6_decode2";
attribute hblknm of sync_interrupt_flop : label is "kcpsm6_decode2";
attribute hblknm of push_pop_lut : label is "kcpsm6_stack1";
attribute hblknm of regbank_type_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_lut : label is "kcpsm6_stack1";
attribute hblknm of bank_flop : label is "kcpsm6_stack1";
attribute hblknm of register_enable_type_lut : label is "kcpsm6_strobes";
attribute hblknm of register_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of flag_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of register_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_lut : label is "kcpsm6_strobes";
attribute hblknm of k_write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of spm_enable_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_lut : label is "kcpsm6_strobes";
attribute hblknm of write_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of read_strobe_flop : label is "kcpsm6_strobes";
attribute hblknm of stack_ram_low : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_carry_flag_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_zero_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of shadow_bank_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_bit_flop : label is "kcpsm6_stack_ram0";
attribute hblknm of stack_ram_high : label is "kcpsm6_stack_ram1";
attribute hblknm of lower_reg_banks : label is "kcpsm6_reg0";
attribute hblknm of upper_reg_banks : label is "kcpsm6_reg1";
attribute hblknm of pc_mode1_lut : label is "kcpsm6_vector1";
attribute hblknm of pc_mode2_lut : label is "kcpsm6_vector1";
--
-------------------------------------------------------------------------------------------
--
-- Start of kcpsm6 circuit description
--
-- Summary of all primitives defined.
--
-- 29 x LUT6 79 LUTs (plus 1 LUT will be required to form a GND signal)
-- 50 x LUT6_2
-- 48 x FD 82 flip-flops
-- 20 x FDR (Depending on the value of 'hwbuild' up)
-- 0 x FDS (to eight FDR will be replaced by FDS )
-- 14 x FDRE
-- 29 x MUXCY
-- 27 x XORCY
-- 4 x RAM32M (16 LUTs)
--
-- 2 x RAM64M or 8 x RAM128X1S or 8 x RAM256X1S
-- (8 LUTs) (16 LUTs) (32 LUTs)
--
-------------------------------------------------------------------------------------------
--
begin
--
-------------------------------------------------------------------------------------------
--
-- Perform check of generic to report error as soon as possible.
--
-------------------------------------------------------------------------------------------
--
assert ((scratch_pad_memory_size = 64)
or (scratch_pad_memory_size = 128)
or (scratch_pad_memory_size = 256))
report "Invalid 'scratch_pad_memory_size'. Please set to 64, 128 or 256."
severity FAILURE;
--
-------------------------------------------------------------------------------------------
--
-- State Machine and Control
--
--
-- 1 x LUT6
-- 4 x LUT6_2
-- 9 x FD
--
-------------------------------------------------------------------------------------------
--
reset_lut: LUT6_2
generic map (INIT => X"FFFFF55500000EEE")
port map( I0 => run,
I1 => internal_reset,
I2 => stack_pointer_carry(4),
I3 => t_state(2),
I4 => reset,
I5 => '1',
O5 => run_value,
O6 => internal_reset_value);
run_flop: FD
port map ( D => run_value,
Q => run,
C => clk);
internal_reset_flop: FD
port map ( D => internal_reset_value,
Q => internal_reset,
C => clk);
sync_sleep_flop: FD
port map ( D => sleep,
Q => sync_sleep,
C => clk);
t_state_lut: LUT6_2
generic map (INIT => X"0083000B00C4004C")
port map( I0 => t_state(1),
I1 => t_state(2),
I2 => sync_sleep,
I3 => internal_reset,
I4 => special_bit,
I5 => '1',
O5 => t_state_value(1),
O6 => t_state_value(2));
t_state1_flop: FD
port map ( D => t_state_value(1),
Q => t_state(1),
C => clk);
t_state2_flop: FD
port map ( D => t_state_value(2),
Q => t_state(2),
C => clk);
int_enable_type_lut: LUT6_2
generic map (INIT => X"0010000000000800")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => loadstar_type,
O6 => int_enable_type);
interrupt_enable_lut: LUT6
generic map (INIT => X"000000000000CAAA")
port map( I0 => interrupt_enable,
I1 => instruction(0),
I2 => int_enable_type,
I3 => t_state(1),
I4 => active_interrupt,
I5 => internal_reset,
O => interrupt_enable_value);
interrupt_enable_flop: FD
port map ( D => interrupt_enable_value,
Q => interrupt_enable,
C => clk);
sync_interrupt_flop: FD
port map ( D => interrupt,
Q => sync_interrupt,
C => clk);
active_interrupt_lut: LUT6_2
generic map (INIT => X"CC33FF0080808080")
port map( I0 => interrupt_enable,
I1 => t_state(2),
I2 => sync_interrupt,
I3 => bank,
I4 => loadstar_type,
I5 => '1',
O5 => active_interrupt_value,
O6 => sx_addr4_value);
active_interrupt_flop: FD
port map ( D => active_interrupt_value,
Q => active_interrupt,
C => clk);
interrupt_ack_flop: FD
port map ( D => active_interrupt,
Q => interrupt_ack,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Decoders
--
--
-- 2 x LUT6
-- 10 x LUT6_2
-- 2 x FD
-- 6 x FDR
--
-------------------------------------------------------------------------------------------
--
--
-- Decoding for Program Counter and Stack
--
pc_move_is_valid_lut: LUT6
generic map (INIT => X"5A3CFFFF00000000")
port map( I0 => carry_flag,
I1 => zero_flag,
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => pc_move_is_valid);
move_type_lut: LUT6_2
generic map (INIT => X"7777027700000200")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => returni_type,
O6 => move_type);
pc_mode1_lut: LUT6_2
generic map (INIT => X"0000F000000023FF")
port map( I0 => instruction(12),
I1 => returni_type,
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pc_mode(0),
O6 => pc_mode(1));
pc_mode2_lut: LUT6
generic map (INIT => X"FFFFFFFF00040000")
port map( I0 => instruction(12),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => active_interrupt,
O => pc_mode(2));
push_pop_lut: LUT6_2
generic map (INIT => X"FFFF100000002000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => move_type,
I3 => pc_move_is_valid,
I4 => active_interrupt,
I5 => '1',
O5 => pop_stack,
O6 => push_stack);
--
-- Decoding for ALU
--
alu_decode0_lut: LUT6_2
generic map (INIT => X"03CA000004200000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => alu_mux_sel_value(0),
O6 => arith_logical_sel(0));
alu_mux_sel0_flop: FD
port map ( D => alu_mux_sel_value(0),
Q => alu_mux_sel(0),
C => clk);
alu_decode1_lut: LUT6_2
generic map (INIT => X"7708000000000F00")
port map( I0 => carry_flag,
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => '1',
O5 => alu_mux_sel_value(1),
O6 => arith_carry_in);
alu_mux_sel1_flop: FD
port map ( D => alu_mux_sel_value(1),
Q => alu_mux_sel(1),
C => clk);
alu_decode2_lut: LUT6_2
generic map (INIT => X"D000000002000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O5 => arith_logical_sel(1),
O6 => arith_logical_sel(2));
--
-- Decoding for strobes and enables
--
register_enable_type_lut: LUT6_2
generic map (INIT => X"00013F3F0010F7CE")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => instruction(17),
I5 => '1',
O5 => flag_enable_type,
O6 => register_enable_type);
register_enable_lut: LUT6_2
generic map (INIT => X"C0CC0000A0AA0000")
port map( I0 => flag_enable_type,
I1 => register_enable_type,
I2 => instruction(12),
I3 => instruction(17),
I4 => t_state(1),
I5 => '1',
O5 => flag_enable_value,
O6 => register_enable_value);
flag_enable_flop: FDR
port map ( D => flag_enable_value,
Q => flag_enable,
R => active_interrupt,
C => clk);
register_enable_flop: FDR
port map ( D => register_enable_value,
Q => register_enable,
R => active_interrupt,
C => clk);
spm_enable_lut: LUT6_2
generic map (INIT => X"8000000020000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => k_write_strobe_value,
O6 => spm_enable_value);
k_write_strobe_flop: FDR
port map ( D => k_write_strobe_value,
Q => k_write_strobe,
R => active_interrupt,
C => clk);
spm_enable_flop: FDR
port map ( D => spm_enable_value,
Q => spm_enable,
R => active_interrupt,
C => clk);
read_strobe_lut: LUT6_2
generic map (INIT => X"4000000001000000")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(17),
I3 => strobe_type,
I4 => t_state(1),
I5 => '1',
O5 => read_strobe_value,
O6 => write_strobe_value);
write_strobe_flop: FDR
port map ( D => write_strobe_value,
Q => write_strobe,
R => active_interrupt,
C => clk);
read_strobe_flop: FDR
port map ( D => read_strobe_value,
Q => read_strobe,
R => active_interrupt,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- Register bank control
--
--
-- 2 x LUT6
-- 1 x FDR
-- 1 x FD
--
-------------------------------------------------------------------------------------------
--
regbank_type_lut: LUT6
generic map (INIT => X"0080020000000000")
port map( I0 => instruction(12),
I1 => instruction(13),
I2 => instruction(14),
I3 => instruction(15),
I4 => instruction(16),
I5 => instruction(17),
O => regbank_type);
bank_lut: LUT6
generic map (INIT => X"ACACFF00FF00FF00")
port map( I0 => instruction(0),
I1 => shadow_bank,
I2 => instruction(16),
I3 => bank,
I4 => regbank_type,
I5 => t_state(1),
O => bank_value);
bank_flop: FDR
port map ( D => bank_value,
Q => bank,
R => internal_reset,
C => clk);
sx_addr4_flop: FD
port map ( D => sx_addr4_value,
Q => sx_addr(4),
C => clk);
sx_addr(3 downto 0) <= instruction(11 downto 8);
sy_addr <= bank & instruction(7 downto 4);
--
-------------------------------------------------------------------------------------------
--
-- Flags
--
--
-- 3 x LUT6
-- 5 x LUT6_2
-- 3 x FD
-- 2 x FDRE
-- 2 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
arith_carry_xorcy: XORCY
port map( LI => '0',
CI => carry_arith_logical(7),
O => arith_carry_value);
arith_carry_flop: FD
port map ( D => arith_carry_value,
Q => arith_carry,
C => clk);
lower_parity_lut: LUT6_2
generic map (INIT => X"0000000087780000")
port map( I0 => instruction(13),
I1 => carry_flag,
I2 => arith_logical_result(0),
I3 => arith_logical_result(1),
I4 => '1',
I5 => '1',
O5 => lower_parity,
O6 => lower_parity_sel);
parity_muxcy: MUXCY
port map( DI => lower_parity,
CI => '0',
S => lower_parity_sel,
O => carry_lower_parity);
upper_parity_lut: LUT6
generic map (INIT => X"6996966996696996")
port map( I0 => arith_logical_result(2),
I1 => arith_logical_result(3),
I2 => arith_logical_result(4),
I3 => arith_logical_result(5),
I4 => arith_logical_result(6),
I5 => arith_logical_result(7),
O => upper_parity);
parity_xorcy: XORCY
port map( LI => upper_parity,
CI => carry_lower_parity,
O => parity);
shift_carry_lut: LUT6
generic map (INIT => X"FFFFAACCF0F0F0F0")
port map( I0 => sx(0),
I1 => sx(7),
I2 => shadow_carry_flag,
I3 => instruction(3),
I4 => instruction(7),
I5 => instruction(16),
O => shift_carry_value);
shift_carry_flop: FD
port map ( D => shift_carry_value,
Q => shift_carry,
C => clk);
carry_flag_lut: LUT6_2
generic map (INIT => X"3333AACCF0AA0000")
port map( I0 => shift_carry,
I1 => arith_carry,
I2 => parity,
I3 => instruction(14),
I4 => instruction(15),
I5 => instruction(16),
O5 => drive_carry_in_zero,
O6 => carry_flag_value);
carry_flag_flop: FDRE
port map ( D => carry_flag_value,
Q => carry_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
init_zero_muxcy: MUXCY
port map( DI => drive_carry_in_zero,
CI => '0',
S => carry_flag_value,
O => carry_in_zero);
use_zero_flag_lut: LUT6_2
generic map (INIT => X"A280000000F000F0")
port map( I0 => instruction(13),
I1 => instruction(14),
I2 => instruction(15),
I3 => instruction(16),
I4 => '1',
I5 => '1',
O5 => strobe_type,
O6 => use_zero_flag_value);
use_zero_flag_flop: FD
port map ( D => use_zero_flag_value,
Q => use_zero_flag,
C => clk);
lower_zero_lut: LUT6_2
generic map (INIT => X"0000000000000001")
port map( I0 => alu_result(0),
I1 => alu_result(1),
I2 => alu_result(2),
I3 => alu_result(3),
I4 => alu_result(4),
I5 => '1',
O5 => lower_zero,
O6 => lower_zero_sel);
lower_zero_muxcy: MUXCY
port map( DI => lower_zero,
CI => carry_in_zero,
S => lower_zero_sel,
O => carry_lower_zero);
middle_zero_lut: LUT6_2
generic map (INIT => X"0000000D00000000")
port map( I0 => use_zero_flag,
I1 => zero_flag,
I2 => alu_result(5),
I3 => alu_result(6),
I4 => alu_result(7),
I5 => '1',
O5 => middle_zero,
O6 => middle_zero_sel);
middle_zero_muxcy: MUXCY
port map( DI => middle_zero,
CI => carry_lower_zero,
S => middle_zero_sel,
O => carry_middle_zero);
upper_zero_lut: LUT6
generic map (INIT => X"FBFF000000000000")
port map( I0 => instruction(14),
I1 => instruction(15),
I2 => instruction(16),
I3 => '1',
I4 => '1',
I5 => '1',
O => upper_zero_sel);
upper_zero_muxcy: MUXCY
port map( DI => shadow_zero_flag,
CI => carry_middle_zero,
S => upper_zero_sel,
O => zero_flag_value);
zero_flag_flop: FDRE
port map ( D => zero_flag_value,
Q => zero_flag,
CE => flag_enable,
R => internal_reset,
C => clk);
--
-------------------------------------------------------------------------------------------
--
-- 12-bit Program Address Generation
--
-------------------------------------------------------------------------------------------
--
--
-- Prepare 12-bit vector from the sX and sY register outputs.
--
register_vector <= sx(3 downto 0) & sy;
address_loop: for i in 0 to 11 generate
attribute hblknm : string;
attribute hblknm of pc_flop : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of return_vector_flop : label is "kcpsm6_stack_ram" & integer'image((i+4)/8);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of vector to load program counter
--
-- instruction(12)
-- 0 Constant aaa from instruction(11:0)
-- 1 Return vector from stack
--
-- 'aaa' is used during 'JUMP aaa', 'JUMP c, aaa', 'CALL aaa' and 'CALL c, aaa'.
-- Return vector is used during 'RETURN', 'RETURN c', 'RETURN&LOAD' and 'RETURNI'.
--
-- 6 x LUT6_2
-- 12 x FD
--
-------------------------------------------------------------------------------------------
--
--
-- Pipeline output of the stack memory
--
return_vector_flop: FD
port map ( D => stack_memory(i),
Q => return_vector(i),
C => clk);
--
-- Multiplex instruction constant address and output from stack.
-- 2 bits per LUT so only generate when 'i' is even.
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of pc_vector_mux_lut : label is "kcpsm6_vector" & integer'image(i/8);
begin
pc_vector_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => instruction(i),
I1 => return_vector(i),
I2 => instruction(i+1),
I3 => return_vector(i+1),
I4 => instruction(12),
I5 => '1',
O5 => pc_vector(i),
O6 => pc_vector(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Program Counter
--
-- Reset by internal_reset has highest priority.
-- Enabled by t_state(1) has second priority.
--
-- The function performed is defined by pc_mode(2:0).
--
-- pc_mode (2) (1) (0)
-- 0 0 1 pc+1 for normal program flow.
-- 1 0 0 Forces interrupt vector value (+0) during active interrupt.
-- The vector is defined by a generic with default value FF0 hex.
-- 1 1 0 register_vector (+0) for 'JUMP (sX, sY)' and 'CALL (sX, sY)'.
-- 0 1 0 pc_vector (+0) for 'JUMP/CALL aaa' and 'RETURNI'.
-- 0 1 1 pc_vector+1 for 'RETURN'.
--
-- Note that pc_mode(0) is High during operations that require an increment to occur.
-- The LUT6 associated with the LSB must invert pc or pc_vector in these cases and
-- pc_mode(0) also has to be connected to the start of the carry chain.
--
-- 3 Slices
-- 12 x LUT6
-- 11 x MUXCY
-- 12 x XORCY
-- 12 x FDRE
--
-------------------------------------------------------------------------------------------
--
pc_flop: FDRE
port map ( D => pc_value(i),
Q => pc(i),
R => internal_reset,
CE => t_state(1),
C => clk);
lsb_pc: if i=0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of LSB must invert selected value when pc_mode(0) is High.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA000033CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FF33CC0F00")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- pc_mode(0) connected to first MUXCY and carry input is '0'
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => '0',
O => pc_value(i));
pc_muxcy: MUXCY
port map( DI => pc_mode(0),
CI => '0',
S => half_pc(i),
O => carry_pc(i));
end generate lsb_pc;
upper_pc: if i>0 generate
attribute hblknm : string;
attribute hblknm of pc_xorcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
--
-- Logic of upper section selects required value.
-- The interrupt vector is defined by a generic.
--
low_int_vector: if interrupt_vector(i)='0' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA0000CCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate low_int_vector;
high_int_vector: if interrupt_vector(i)='1' generate
attribute hblknm : string;
attribute hblknm of pc_lut : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_lut: LUT6
generic map (INIT => X"00AA00FFCCCCF000")
port map( I0 => register_vector(i),
I1 => pc_vector(i),
I2 => pc(i),
I3 => pc_mode(0),
I4 => pc_mode(1),
I5 => pc_mode(2),
O => half_pc(i));
end generate high_int_vector;
--
-- Carry chain implementing remainder of increment function
--
pc_xorcy: XORCY
port map( LI => half_pc(i),
CI => carry_pc(i-1),
O => pc_value(i));
--
-- No MUXCY required at the top of the chain
--
mid_pc: if i<11 generate
attribute hblknm : string;
attribute hblknm of pc_muxcy : label is "kcpsm6_pc" & integer'image(i/4);
begin
pc_muxcy: MUXCY
port map( DI => '0',
CI => carry_pc(i-1),
S => half_pc(i),
O => carry_pc(i));
end generate mid_pc;
end generate upper_pc;
--
-------------------------------------------------------------------------------------------
--
end generate address_loop;
--
-------------------------------------------------------------------------------------------
--
-- Stack
-- Preserves upto 31 nested values of the Program Counter during CALL and RETURN.
-- Also preserves flags and bank selection during interrupt.
--
-- 2 x RAM32M
-- 4 x FD
-- 5 x FDR
-- 1 x LUT6
-- 4 x LUT6_2
-- 5 x XORCY
-- 5 x MUXCY
--
-------------------------------------------------------------------------------------------
--
shadow_carry_flag_flop: FD
port map ( D => stack_carry_flag,
Q => shadow_carry_flag,
C => clk);
stack_zero_flop: FD
port map ( D => stack_zero_flag,
Q => shadow_zero_value,
C => clk);
shadow_zero_flag_flop: FD
port map ( D => shadow_zero_value,
Q => shadow_zero_flag,
C => clk);
shadow_bank_flop: FD
port map ( D => stack_bank,
Q => shadow_bank,
C => clk);
stack_bit_flop: FD
port map ( D => stack_bit,
Q => special_bit,
C => clk);
stack_ram_low : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA(0) => stack_carry_flag,
DOA(1) => stack_zero_flag,
DOB(0) => stack_bank,
DOB(1) => stack_bit,
DOC => stack_memory(1 downto 0),
DOD => stack_memory(3 downto 2),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA(0) => carry_flag,
DIA(1) => zero_flag,
DIB(0) => bank,
DIB(1) => run,
DIC => pc(1 downto 0),
DID => pc(3 downto 2),
WE => t_state(1),
WCLK => clk );
stack_ram_high : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => stack_memory(5 downto 4),
DOB => stack_memory(7 downto 6),
DOC => stack_memory(9 downto 8),
DOD => stack_memory(11 downto 10),
ADDRA => stack_pointer(4 downto 0),
ADDRB => stack_pointer(4 downto 0),
ADDRC => stack_pointer(4 downto 0),
ADDRD => stack_pointer(4 downto 0),
DIA => pc(5 downto 4),
DIB => pc(7 downto 6),
DIC => pc(9 downto 8),
DID => pc(11 downto 10),
WE => t_state(1),
WCLK => clk );
stack_loop: for i in 0 to 4 generate
begin
lsb_stack: if i=0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"001529AAAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => '0',
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => '0',
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate lsb_stack;
upper_stack: if i>0 generate
attribute hblknm : string;
attribute hblknm of pointer_flop : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_pointer_lut : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_xorcy : label is "kcpsm6_stack" & integer'image(i/4);
attribute hblknm of stack_muxcy : label is "kcpsm6_stack" & integer'image(i/4);
begin
pointer_flop: FDR
port map ( D => stack_pointer_value(i),
Q => stack_pointer(i),
R => internal_reset,
C => clk);
stack_pointer_lut: LUT6_2
generic map (INIT => X"002A252AAAAAAAAA")
port map( I0 => stack_pointer(i),
I1 => pop_stack,
I2 => push_stack,
I3 => t_state(1),
I4 => t_state(2),
I5 => '1',
O5 => feed_pointer_value(i),
O6 => half_pointer_value(i));
stack_xorcy: XORCY
port map( LI => half_pointer_value(i),
CI => stack_pointer_carry(i-1),
O => stack_pointer_value(i));
stack_muxcy: MUXCY
port map( DI => feed_pointer_value(i),
CI => stack_pointer_carry(i-1),
S => half_pointer_value(i),
O => stack_pointer_carry(i));
end generate upper_stack;
end generate stack_loop;
--
-------------------------------------------------------------------------------------------
--
-- 8-bit Data Path
--
-------------------------------------------------------------------------------------------
--
data_path_loop: for i in 0 to 7 generate
attribute hblknm : string;
attribute hblknm of arith_logical_lut : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_flop : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of alu_mux_lut : label is "kcpsm6_alu" & integer'image(i/4);
begin
--
-------------------------------------------------------------------------------------------
--
-- Selection of second operand to ALU and port_id
--
-- instruction(12)
-- 0 Register sY
-- 1 Constant kk
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
output_data: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of sy_kk_mux_lut : label is "kcpsm6_port_id";
begin
sy_kk_mux_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sy(i),
I1 => instruction(i),
I2 => sy(i+1),
I3 => instruction(i+1),
I4 => instruction(12),
I5 => '1',
O5 => sy_or_kk(i),
O6 => sy_or_kk(i+1));
end generate output_data;
--
-------------------------------------------------------------------------------------------
--
-- Selection of out_port value
--
-- instruction(13)
-- 0 Register sX
-- 1 Constant kk from instruction(11:4)
--
-- 4 x LUT6_2
--
-------------------------------------------------------------------------------------------
--
--
-- 2 bits per LUT so only generate when 'i' is even
--
second_operand: if (i rem 2)=0 generate
attribute hblknm : string;
attribute hblknm of out_port_lut : label is "kcpsm6_out_port";
begin
out_port_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i),
I1 => instruction(i+4),
I2 => sx(i+1),
I3 => instruction(i+5),
I4 => instruction(13),
I5 => '1',
O5 => out_port(i),
O6 => out_port(i+1));
end generate second_operand;
--
-------------------------------------------------------------------------------------------
--
-- Arithmetic and Logical operations
--
-- Definition of....
-- ADD and SUB also used for ADDCY, SUBCY, COMPARE and COMPARECY.
-- LOAD, AND, OR and XOR also used for LOAD*, RETURN&LOAD, TEST and TESTCY.
--
-- arith_logical_sel (2) (1) (0)
-- 0 0 0 - LOAD
-- 0 0 1 - AND
-- 0 1 0 - OR
-- 0 1 1 - XOR
-- 1 X 0 - SUB
-- 1 X 1 - ADD
--
-- Includes pipeline stage.
--
-- 2 Slices
-- 8 x LUT6_2
-- 8 x MUXCY
-- 8 x XORCY
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
arith_logical_lut: LUT6_2
generic map (INIT => X"69696E8ACCCC0000")
port map( I0 => sy_or_kk(i),
I1 => sx(i),
I2 => arith_logical_sel(0),
I3 => arith_logical_sel(1),
I4 => arith_logical_sel(2),
I5 => '1',
O5 => logical_carry_mask(i),
O6 => half_arith_logical(i));
arith_logical_flop: FD
port map ( D => arith_logical_value(i),
Q => arith_logical_result(i),
C => clk);
lsb_arith_logical: if i=0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Carry input to first MUXCY and XORCY
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => arith_carry_in,
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => arith_carry_in,
O => arith_logical_value(i));
end generate lsb_arith_logical;
upper_arith_logical: if i>0 generate
attribute hblknm : string;
attribute hblknm of arith_logical_muxcy : label is "kcpsm6_add" & integer'image(i/4);
attribute hblknm of arith_logical_xorcy : label is "kcpsm6_add" & integer'image(i/4);
begin
--
-- Main carry chain
--
arith_logical_muxcy: MUXCY
port map( DI => logical_carry_mask(i),
CI => carry_arith_logical(i-1),
S => half_arith_logical(i),
O => carry_arith_logical(i));
arith_logical_xorcy: XORCY
port map( LI => half_arith_logical(i),
CI => carry_arith_logical(i-1),
O => arith_logical_value(i));
end generate upper_arith_logical;
--
-------------------------------------------------------------------------------------------
--
-- Shift and Rotate operations
--
-- Definition of SL0, SL1, SLX, SLA, RL, SR0, SR1, SRX, SRA, and RR
--
-- instruction (3) (2) (1) (0)
-- 0 1 1 0 - SL0
-- 0 1 1 1 - SL1
-- 0 1 0 0 - SLX
-- 0 0 0 0 - SLA
-- 0 0 1 0 - RL
-- 1 1 1 0 - SR0
-- 1 1 1 1 - SR1
-- 1 0 1 0 - SRX
-- 1 0 0 0 - SRA
-- 1 1 0 0 - RR
--
-- instruction(3)
-- 0 - Left
-- 1 - Right
--
-- instruction (2) (1) Bit shifted in
-- 0 0 Carry_flag
-- 0 1 sX(7)
-- 1 0 sX(0)
-- 1 1 instruction(0)
--
-- Includes pipeline stage.
--
-- 4 x LUT6_2
-- 1 x LUT6
-- 8 x FD
--
-------------------------------------------------------------------------------------------
--
low_hwbuild: if hwbuild(i)='0' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Reset Flip-flop to form '0' for this bit of HWBUILD
--
shift_rotate_flop: FDR
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
R => instruction(7),
C => clk);
end generate low_hwbuild;
high_hwbuild: if hwbuild(i)='1' generate
attribute hblknm : string;
attribute hblknm of shift_rotate_flop : label is "kcpsm6_sandr";
begin
--
-- Set Flip-flop to form '1' for this bit of HWBUILD
--
shift_rotate_flop: FDS
port map ( D => shift_rotate_value(i),
Q => shift_rotate_result(i),
S => instruction(7),
C => clk);
end generate high_hwbuild;
lsb_shift_rotate: if i=0 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
attribute hblknm of shift_bit_lut : label is "kcpsm6_decode1";
begin
--
-- Select bit to be shifted or rotated into result
--
shift_bit_lut: LUT6
generic map (INIT => X"BFBC8F8CB3B08380")
port map( I0 => instruction(0),
I1 => instruction(1),
I2 => instruction(2),
I3 => carry_flag,
I4 => sx(0),
I5 => sx(7),
O => shift_in_bit);
--
-- Define lower bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => shift_in_bit,
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate lsb_shift_rotate;
mid_shift_rotate: if i=2 or i=4 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define middle bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => sx(i+2),
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate mid_shift_rotate;
msb_shift_rotate: if i=6 generate
attribute hblknm : string;
attribute hblknm of shift_rotate_lut : label is "kcpsm6_sandr";
begin
--
-- Define upper bits of result
--
shift_rotate_lut: LUT6_2
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => sx(i-1),
I1 => sx(i+1),
I2 => sx(i),
I3 => shift_in_bit,
I4 => instruction(3),
I5 => '1',
O5 => shift_rotate_value(i),
O6 => shift_rotate_value(i+1));
end generate msb_shift_rotate;
--
-------------------------------------------------------------------------------------------
--
-- Multiplex outputs from ALU functions, scratch pad memory and input port.
--
-- alu_mux_sel (1) (0)
-- 0 0 Arithmetic and Logical Instructions
-- 0 1 Shift and Rotate Instructions
-- 1 0 Input Port
-- 1 1 Scratch Pad Memory
--
-- 8 x LUT6
--
-------------------------------------------------------------------------------------------
--
alu_mux_lut: LUT6
generic map (INIT => X"FF00F0F0CCCCAAAA")
port map( I0 => arith_logical_result(i),
I1 => shift_rotate_result(i),
I2 => in_port(i),
I3 => spm_data(i),
I4 => alu_mux_sel(0),
I5 => alu_mux_sel(1),
O => alu_result(i));
--
-------------------------------------------------------------------------------------------
--
-- Scratchpad Memory with output register.
--
-- The size of the scratch pad memory is defined by the 'scratch_pad_memory_size' generic.
-- The default size is 64 bytes the same as KCPSM3 but this can be increased to 128 or 256
-- bytes at an additional cost of 2 and 6 Slices.
--
--
-- 8 x RAM256X1S (256 bytes).
-- 8 x RAM128X1S (128 bytes).
-- 2 x RAM64M (64 bytes).
--
-- 8 x FD.
--
-------------------------------------------------------------------------------------------
--
small_spm: if scratch_pad_memory_size = 64 generate
attribute hblknm : string;
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
small_spm_ram: if (i=0 or i=4) generate
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/4);
begin
spm_ram: RAM64M
generic map ( INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => spm_ram_data(i),
DOB => spm_ram_data(i+1),
DOC => spm_ram_data(i+2),
DOD => spm_ram_data(i+3),
ADDRA => sy_or_kk(5 downto 0),
ADDRB => sy_or_kk(5 downto 0),
ADDRC => sy_or_kk(5 downto 0),
ADDRD => sy_or_kk(5 downto 0),
DIA => sx(i),
DIB => sx(i+1),
DIC => sx(i+2),
DID => sx(i+3),
WE => spm_enable,
WCLK => clk );
end generate small_spm_ram;
end generate small_spm;
medium_spm: if scratch_pad_memory_size = 128 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i/2);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i/2);
begin
spm_ram: RAM128X1S
generic map(INIT => X"00000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A0 => sy_or_kk(0),
A1 => sy_or_kk(1),
A2 => sy_or_kk(2),
A3 => sy_or_kk(3),
A4 => sy_or_kk(4),
A5 => sy_or_kk(5),
A6 => sy_or_kk(6),
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate medium_spm;
large_spm: if scratch_pad_memory_size = 256 generate
attribute hblknm : string;
attribute hblknm of spm_ram : label is "kcpsm6_spm" & integer'image(i);
attribute hblknm of spm_flop : label is "kcpsm6_spm" & integer'image(i);
begin
spm_ram: RAM256X1S
generic map(INIT => X"0000000000000000000000000000000000000000000000000000000000000000")
port map ( D => sx(i),
WE => spm_enable,
WCLK => clk,
A => sy_or_kk,
O => spm_ram_data(i));
spm_flop: FD
port map ( D => spm_ram_data(i),
Q => spm_data(i),
C => clk);
end generate large_spm;
--
-------------------------------------------------------------------------------------------
--
end generate data_path_loop;
--
-------------------------------------------------------------------------------------------
--
-- Two Banks of 16 General Purpose Registers.
--
-- sx_addr - Address for sX is formed by bank select and instruction[11:8]
-- sy_addr - Address for sY is formed by bank select and instruction[7:4]
--
-- 2 Slices
-- 2 x RAM32M
--
-------------------------------------------------------------------------------------------
--
lower_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(1 downto 0),
DOB => sx(1 downto 0),
DOC => sy(3 downto 2),
DOD => sx(3 downto 2),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(1 downto 0),
DIB => alu_result(1 downto 0),
DIC => alu_result(3 downto 2),
DID => alu_result(3 downto 2),
WE => register_enable,
WCLK => clk );
upper_reg_banks : RAM32M
generic map (INIT_A => X"0000000000000000",
INIT_B => X"0000000000000000",
INIT_C => X"0000000000000000",
INIT_D => X"0000000000000000")
port map ( DOA => sy(5 downto 4),
DOB => sx(5 downto 4),
DOC => sy(7 downto 6),
DOD => sx(7 downto 6),
ADDRA => sy_addr,
ADDRB => sx_addr,
ADDRC => sy_addr,
ADDRD => sx_addr,
DIA => alu_result(5 downto 4),
DIB => alu_result(5 downto 4),
DIC => alu_result(7 downto 6),
DID => alu_result(7 downto 6),
WE => register_enable,
WCLK => clk );
--
-------------------------------------------------------------------------------------------
--
-- Connections to KCPSM6 outputs.
--
-------------------------------------------------------------------------------------------
--
address <= pc;
bram_enable <= t_state(2);
--
-------------------------------------------------------------------------------------------
--
-- Connections KCPSM6 Outputs.
--
-------------------------------------------------------------------------------------------
--
port_id <= sy_or_kk;
--
-------------------------------------------------------------------------------------------
--
-- End of description for kcpsm6 macro.
--
-------------------------------------------------------------------------------------------
--
-- *****************************************************
-- * Code for simulation purposes only after this line *
-- *****************************************************
--
--
-- Disassemble the instruction codes to form a text string for display.
-- Determine status of reset and flags and present in the form of a text string.
-- Provide signals to simulate the contents of each register and scratch pad memory
-- location.
--
-------------------------------------------------------------------------------------------
--
--All of this section is ignored during synthesis.
--synthesis translate off
simulation: process (clk, instruction, carry_flag, zero_flag, bank, interrupt_enable)
--
-- Variables for contents of each register in each bank
--
variable bank_a_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_a_se : std_logic_vector(7 downto 0) := X"00";
variable bank_a_sf : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s0 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s1 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s2 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s3 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s4 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s5 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s6 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s7 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s8 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_s9 : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sa : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sb : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sc : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sd : std_logic_vector(7 downto 0) := X"00";
variable bank_b_se : std_logic_vector(7 downto 0) := X"00";
variable bank_b_sf : std_logic_vector(7 downto 0) := X"00";
--
-- Temporary variables for instruction decoding
--
variable sx_decode : string(1 to 2); -- sX register specification
variable sy_decode : string(1 to 2); -- sY register specification
variable kk_decode : string(1 to 2); -- constant value kk, pp or ss
variable aaa_decode : string(1 to 3); -- address value aaa
--
-----------------------------------------------------------------------------------------
--
-- Function to convert 4-bit binary nibble to hexadecimal character
--
-----------------------------------------------------------------------------------------
--
function hexcharacter (nibble: std_logic_vector(3 downto 0))
return character is
variable hex: character;
begin
case nibble is
when "0000" => hex := '0';
when "0001" => hex := '1';
when "0010" => hex := '2';
when "0011" => hex := '3';
when "0100" => hex := '4';
when "0101" => hex := '5';
when "0110" => hex := '6';
when "0111" => hex := '7';
when "1000" => hex := '8';
when "1001" => hex := '9';
when "1010" => hex := 'A';
when "1011" => hex := 'B';
when "1100" => hex := 'C';
when "1101" => hex := 'D';
when "1110" => hex := 'E';
when "1111" => hex := 'F';
when others => hex := 'x';
end case;
return hex;
end hexcharacter;
--
-----------------------------------------------------------------------------------------
--
begin
-- decode first register sX
sx_decode(1) := 's';
sx_decode(2) := hexcharacter(instruction(11 downto 8));
-- decode second register sY
sy_decode(1) := 's';
sy_decode(2) := hexcharacter(instruction(7 downto 4));
-- decode constant value
kk_decode(1) := hexcharacter(instruction(7 downto 4));
kk_decode(2) := hexcharacter(instruction(3 downto 0));
-- address value
aaa_decode(1) := hexcharacter(instruction(11 downto 8));
aaa_decode(2) := hexcharacter(instruction(7 downto 4));
aaa_decode(3) := hexcharacter(instruction(3 downto 0));
-- decode instruction
case instruction(17 downto 12) is
when "000000" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & sy_decode & " ";
when "000001" => kcpsm6_opcode <= "LOAD " & sx_decode & ", " & kk_decode & " ";
when "010110" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & sy_decode & " ";
when "010111" => kcpsm6_opcode <= "STAR " & sx_decode & ", " & kk_decode & " ";
when "000010" => kcpsm6_opcode <= "AND " & sx_decode & ", " & sy_decode & " ";
when "000011" => kcpsm6_opcode <= "AND " & sx_decode & ", " & kk_decode & " ";
when "000100" => kcpsm6_opcode <= "OR " & sx_decode & ", " & sy_decode & " ";
when "000101" => kcpsm6_opcode <= "OR " & sx_decode & ", " & kk_decode & " ";
when "000110" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & sy_decode & " ";
when "000111" => kcpsm6_opcode <= "XOR " & sx_decode & ", " & kk_decode & " ";
when "001100" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & sy_decode & " ";
when "001101" => kcpsm6_opcode <= "TEST " & sx_decode & ", " & kk_decode & " ";
when "001110" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & sy_decode & " ";
when "001111" => kcpsm6_opcode <= "TESTCY " & sx_decode & ", " & kk_decode & " ";
when "010000" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & sy_decode & " ";
when "010001" => kcpsm6_opcode <= "ADD " & sx_decode & ", " & kk_decode & " ";
when "010010" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & sy_decode & " ";
when "010011" => kcpsm6_opcode <= "ADDCY " & sx_decode & ", " & kk_decode & " ";
when "011000" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & sy_decode & " ";
when "011001" => kcpsm6_opcode <= "SUB " & sx_decode & ", " & kk_decode & " ";
when "011010" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & sy_decode & " ";
when "011011" => kcpsm6_opcode <= "SUBCY " & sx_decode & ", " & kk_decode & " ";
when "011100" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & sy_decode & " ";
when "011101" => kcpsm6_opcode <= "COMPARE " & sx_decode & ", " & kk_decode & " ";
when "011110" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & sy_decode & " ";
when "011111" => kcpsm6_opcode <= "COMPARECY " & sx_decode & ", " & kk_decode & " ";
when "010100" =>
if instruction(7) = '1' then
kcpsm6_opcode <= "HWBUILD " & sx_decode & " ";
else
case instruction(3 downto 0) is
when "0110" => kcpsm6_opcode <= "SL0 " & sx_decode & " ";
when "0111" => kcpsm6_opcode <= "SL1 " & sx_decode & " ";
when "0100" => kcpsm6_opcode <= "SLX " & sx_decode & " ";
when "0000" => kcpsm6_opcode <= "SLA " & sx_decode & " ";
when "0010" => kcpsm6_opcode <= "RL " & sx_decode & " ";
when "1110" => kcpsm6_opcode <= "SR0 " & sx_decode & " ";
when "1111" => kcpsm6_opcode <= "SR1 " & sx_decode & " ";
when "1010" => kcpsm6_opcode <= "SRX " & sx_decode & " ";
when "1000" => kcpsm6_opcode <= "SRA " & sx_decode & " ";
when "1100" => kcpsm6_opcode <= "RR " & sx_decode & " ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
end if;
when "101100" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", (" & sy_decode & ") ";
when "101101" => kcpsm6_opcode <= "OUTPUT " & sx_decode & ", " & kk_decode & " ";
when "101011" => kcpsm6_opcode <= "OUTPUTK " & aaa_decode(1) & aaa_decode(2)
& ", " & aaa_decode(3) & " ";
when "001000" => kcpsm6_opcode <= "INPUT " & sx_decode & ", (" & sy_decode & ") ";
when "001001" => kcpsm6_opcode <= "INPUT " & sx_decode & ", " & kk_decode & " ";
when "101110" => kcpsm6_opcode <= "STORE " & sx_decode & ", (" & sy_decode & ") ";
when "101111" => kcpsm6_opcode <= "STORE " & sx_decode & ", " & kk_decode & " ";
when "001010" => kcpsm6_opcode <= "FETCH " & sx_decode & ", (" & sy_decode & ") ";
when "001011" => kcpsm6_opcode <= "FETCH " & sx_decode & ", " & kk_decode & " ";
when "100010" => kcpsm6_opcode <= "JUMP " & aaa_decode & " ";
when "110010" => kcpsm6_opcode <= "JUMP Z, " & aaa_decode & " ";
when "110110" => kcpsm6_opcode <= "JUMP NZ, " & aaa_decode & " ";
when "111010" => kcpsm6_opcode <= "JUMP C, " & aaa_decode & " ";
when "111110" => kcpsm6_opcode <= "JUMP NC, " & aaa_decode & " ";
when "100110" => kcpsm6_opcode <= "JUMP@ (" & sx_decode & ", " & sy_decode & ") ";
when "100000" => kcpsm6_opcode <= "CALL " & aaa_decode & " ";
when "110000" => kcpsm6_opcode <= "CALL Z, " & aaa_decode & " ";
when "110100" => kcpsm6_opcode <= "CALL NZ, " & aaa_decode & " ";
when "111000" => kcpsm6_opcode <= "CALL C, " & aaa_decode & " ";
when "111100" => kcpsm6_opcode <= "CALL NC, " & aaa_decode & " ";
when "100100" => kcpsm6_opcode <= "CALL@ (" & sx_decode & ", " & sy_decode & ") ";
when "100101" => kcpsm6_opcode <= "RETURN ";
when "110001" => kcpsm6_opcode <= "RETURN Z ";
when "110101" => kcpsm6_opcode <= "RETURN NZ ";
when "111001" => kcpsm6_opcode <= "RETURN C ";
when "111101" => kcpsm6_opcode <= "RETURN NC ";
when "100001" => kcpsm6_opcode <= "LOAD&RETURN " & sx_decode & ", " & kk_decode & " ";
when "101001" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "RETURNI DISABLE ";
when '1' => kcpsm6_opcode <= "RETURNI ENABLE ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "101000" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "DISABLE INTERRUPT ";
when '1' => kcpsm6_opcode <= "ENABLE INTERRUPT ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when "110111" =>
case instruction(0) is
when '0' => kcpsm6_opcode <= "REGBANK A ";
when '1' => kcpsm6_opcode <= "REGBANK B ";
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
when others => kcpsm6_opcode <= "Invalid Instruction";
end case;
-- Flag status information
if zero_flag = '0' then
kcpsm6_status(3 to 5) <= "NZ,";
else
kcpsm6_status(3 to 5) <= " Z,";
end if;
if carry_flag = '0' then
kcpsm6_status(6 to 8) <= "NC,";
else
kcpsm6_status(6 to 8) <= " C,";
end if;
if interrupt_enable = '0' then
kcpsm6_status(9 to 10) <= "ID";
else
kcpsm6_status(9 to 10) <= "IE";
end if;
-- Operational status
if clk'event and clk = '1' then
if internal_reset = '1' then
kcpsm6_status(11 to 16) <= ",Reset";
else
if sync_sleep = '1' and t_state = "00" then
kcpsm6_status(11 to 16) <= ",Sleep";
else
kcpsm6_status(11 to 16) <= " ";
end if;
end if;
end if;
-- Simulation of register contents
if clk'event and clk = '1' then
if register_enable = '1' then
case sx_addr is
when "00000" => bank_a_s0 := alu_result;
when "00001" => bank_a_s1 := alu_result;
when "00010" => bank_a_s2 := alu_result;
when "00011" => bank_a_s3 := alu_result;
when "00100" => bank_a_s4 := alu_result;
when "00101" => bank_a_s5 := alu_result;
when "00110" => bank_a_s6 := alu_result;
when "00111" => bank_a_s7 := alu_result;
when "01000" => bank_a_s8 := alu_result;
when "01001" => bank_a_s9 := alu_result;
when "01010" => bank_a_sa := alu_result;
when "01011" => bank_a_sb := alu_result;
when "01100" => bank_a_sc := alu_result;
when "01101" => bank_a_sd := alu_result;
when "01110" => bank_a_se := alu_result;
when "01111" => bank_a_sf := alu_result;
when "10000" => bank_b_s0 := alu_result;
when "10001" => bank_b_s1 := alu_result;
when "10010" => bank_b_s2 := alu_result;
when "10011" => bank_b_s3 := alu_result;
when "10100" => bank_b_s4 := alu_result;
when "10101" => bank_b_s5 := alu_result;
when "10110" => bank_b_s6 := alu_result;
when "10111" => bank_b_s7 := alu_result;
when "11000" => bank_b_s8 := alu_result;
when "11001" => bank_b_s9 := alu_result;
when "11010" => bank_b_sa := alu_result;
when "11011" => bank_b_sb := alu_result;
when "11100" => bank_b_sc := alu_result;
when "11101" => bank_b_sd := alu_result;
when "11110" => bank_b_se := alu_result;
when "11111" => bank_b_sf := alu_result;
when others => null;
end case;
end if;
--simulation of scratch pad memory contents
if spm_enable = '1' then
case sy_or_kk is
when "00000000" => sim_spm00 <= sx;
when "00000001" => sim_spm01 <= sx;
when "00000010" => sim_spm02 <= sx;
when "00000011" => sim_spm03 <= sx;
when "00000100" => sim_spm04 <= sx;
when "00000101" => sim_spm05 <= sx;
when "00000110" => sim_spm06 <= sx;
when "00000111" => sim_spm07 <= sx;
when "00001000" => sim_spm08 <= sx;
when "00001001" => sim_spm09 <= sx;
when "00001010" => sim_spm0A <= sx;
when "00001011" => sim_spm0B <= sx;
when "00001100" => sim_spm0C <= sx;
when "00001101" => sim_spm0D <= sx;
when "00001110" => sim_spm0E <= sx;
when "00001111" => sim_spm0F <= sx;
when "00010000" => sim_spm10 <= sx;
when "00010001" => sim_spm11 <= sx;
when "00010010" => sim_spm12 <= sx;
when "00010011" => sim_spm13 <= sx;
when "00010100" => sim_spm14 <= sx;
when "00010101" => sim_spm15 <= sx;
when "00010110" => sim_spm16 <= sx;
when "00010111" => sim_spm17 <= sx;
when "00011000" => sim_spm18 <= sx;
when "00011001" => sim_spm19 <= sx;
when "00011010" => sim_spm1A <= sx;
when "00011011" => sim_spm1B <= sx;
when "00011100" => sim_spm1C <= sx;
when "00011101" => sim_spm1D <= sx;
when "00011110" => sim_spm1E <= sx;
when "00011111" => sim_spm1F <= sx;
when "00100000" => sim_spm20 <= sx;
when "00100001" => sim_spm21 <= sx;
when "00100010" => sim_spm22 <= sx;
when "00100011" => sim_spm23 <= sx;
when "00100100" => sim_spm24 <= sx;
when "00100101" => sim_spm25 <= sx;
when "00100110" => sim_spm26 <= sx;
when "00100111" => sim_spm27 <= sx;
when "00101000" => sim_spm28 <= sx;
when "00101001" => sim_spm29 <= sx;
when "00101010" => sim_spm2A <= sx;
when "00101011" => sim_spm2B <= sx;
when "00101100" => sim_spm2C <= sx;
when "00101101" => sim_spm2D <= sx;
when "00101110" => sim_spm2E <= sx;
when "00101111" => sim_spm2F <= sx;
when "00110000" => sim_spm30 <= sx;
when "00110001" => sim_spm31 <= sx;
when "00110010" => sim_spm32 <= sx;
when "00110011" => sim_spm33 <= sx;
when "00110100" => sim_spm34 <= sx;
when "00110101" => sim_spm35 <= sx;
when "00110110" => sim_spm36 <= sx;
when "00110111" => sim_spm37 <= sx;
when "00111000" => sim_spm38 <= sx;
when "00111001" => sim_spm39 <= sx;
when "00111010" => sim_spm3A <= sx;
when "00111011" => sim_spm3B <= sx;
when "00111100" => sim_spm3C <= sx;
when "00111101" => sim_spm3D <= sx;
when "00111110" => sim_spm3E <= sx;
when "00111111" => sim_spm3F <= sx;
when "01000000" => sim_spm40 <= sx;
when "01000001" => sim_spm41 <= sx;
when "01000010" => sim_spm42 <= sx;
when "01000011" => sim_spm43 <= sx;
when "01000100" => sim_spm44 <= sx;
when "01000101" => sim_spm45 <= sx;
when "01000110" => sim_spm46 <= sx;
when "01000111" => sim_spm47 <= sx;
when "01001000" => sim_spm48 <= sx;
when "01001001" => sim_spm49 <= sx;
when "01001010" => sim_spm4A <= sx;
when "01001011" => sim_spm4B <= sx;
when "01001100" => sim_spm4C <= sx;
when "01001101" => sim_spm4D <= sx;
when "01001110" => sim_spm4E <= sx;
when "01001111" => sim_spm4F <= sx;
when "01010000" => sim_spm50 <= sx;
when "01010001" => sim_spm51 <= sx;
when "01010010" => sim_spm52 <= sx;
when "01010011" => sim_spm53 <= sx;
when "01010100" => sim_spm54 <= sx;
when "01010101" => sim_spm55 <= sx;
when "01010110" => sim_spm56 <= sx;
when "01010111" => sim_spm57 <= sx;
when "01011000" => sim_spm58 <= sx;
when "01011001" => sim_spm59 <= sx;
when "01011010" => sim_spm5A <= sx;
when "01011011" => sim_spm5B <= sx;
when "01011100" => sim_spm5C <= sx;
when "01011101" => sim_spm5D <= sx;
when "01011110" => sim_spm5E <= sx;
when "01011111" => sim_spm5F <= sx;
when "01100000" => sim_spm60 <= sx;
when "01100001" => sim_spm61 <= sx;
when "01100010" => sim_spm62 <= sx;
when "01100011" => sim_spm63 <= sx;
when "01100100" => sim_spm64 <= sx;
when "01100101" => sim_spm65 <= sx;
when "01100110" => sim_spm66 <= sx;
when "01100111" => sim_spm67 <= sx;
when "01101000" => sim_spm68 <= sx;
when "01101001" => sim_spm69 <= sx;
when "01101010" => sim_spm6A <= sx;
when "01101011" => sim_spm6B <= sx;
when "01101100" => sim_spm6C <= sx;
when "01101101" => sim_spm6D <= sx;
when "01101110" => sim_spm6E <= sx;
when "01101111" => sim_spm6F <= sx;
when "01110000" => sim_spm70 <= sx;
when "01110001" => sim_spm71 <= sx;
when "01110010" => sim_spm72 <= sx;
when "01110011" => sim_spm73 <= sx;
when "01110100" => sim_spm74 <= sx;
when "01110101" => sim_spm75 <= sx;
when "01110110" => sim_spm76 <= sx;
when "01110111" => sim_spm77 <= sx;
when "01111000" => sim_spm78 <= sx;
when "01111001" => sim_spm79 <= sx;
when "01111010" => sim_spm7A <= sx;
when "01111011" => sim_spm7B <= sx;
when "01111100" => sim_spm7C <= sx;
when "01111101" => sim_spm7D <= sx;
when "01111110" => sim_spm7E <= sx;
when "01111111" => sim_spm7F <= sx;
when "10000000" => sim_spm80 <= sx;
when "10000001" => sim_spm81 <= sx;
when "10000010" => sim_spm82 <= sx;
when "10000011" => sim_spm83 <= sx;
when "10000100" => sim_spm84 <= sx;
when "10000101" => sim_spm85 <= sx;
when "10000110" => sim_spm86 <= sx;
when "10000111" => sim_spm87 <= sx;
when "10001000" => sim_spm88 <= sx;
when "10001001" => sim_spm89 <= sx;
when "10001010" => sim_spm8A <= sx;
when "10001011" => sim_spm8B <= sx;
when "10001100" => sim_spm8C <= sx;
when "10001101" => sim_spm8D <= sx;
when "10001110" => sim_spm8E <= sx;
when "10001111" => sim_spm8F <= sx;
when "10010000" => sim_spm90 <= sx;
when "10010001" => sim_spm91 <= sx;
when "10010010" => sim_spm92 <= sx;
when "10010011" => sim_spm93 <= sx;
when "10010100" => sim_spm94 <= sx;
when "10010101" => sim_spm95 <= sx;
when "10010110" => sim_spm96 <= sx;
when "10010111" => sim_spm97 <= sx;
when "10011000" => sim_spm98 <= sx;
when "10011001" => sim_spm99 <= sx;
when "10011010" => sim_spm9A <= sx;
when "10011011" => sim_spm9B <= sx;
when "10011100" => sim_spm9C <= sx;
when "10011101" => sim_spm9D <= sx;
when "10011110" => sim_spm9E <= sx;
when "10011111" => sim_spm9F <= sx;
when "10100000" => sim_spma0 <= sx;
when "10100001" => sim_spmA1 <= sx;
when "10100010" => sim_spmA2 <= sx;
when "10100011" => sim_spmA3 <= sx;
when "10100100" => sim_spmA4 <= sx;
when "10100101" => sim_spmA5 <= sx;
when "10100110" => sim_spmA6 <= sx;
when "10100111" => sim_spmA7 <= sx;
when "10101000" => sim_spmA8 <= sx;
when "10101001" => sim_spmA9 <= sx;
when "10101010" => sim_spmAA <= sx;
when "10101011" => sim_spmAB <= sx;
when "10101100" => sim_spmAC <= sx;
when "10101101" => sim_spmAD <= sx;
when "10101110" => sim_spmAE <= sx;
when "10101111" => sim_spmAF <= sx;
when "10110000" => sim_spmB0 <= sx;
when "10110001" => sim_spmB1 <= sx;
when "10110010" => sim_spmB2 <= sx;
when "10110011" => sim_spmB3 <= sx;
when "10110100" => sim_spmB4 <= sx;
when "10110101" => sim_spmB5 <= sx;
when "10110110" => sim_spmB6 <= sx;
when "10110111" => sim_spmB7 <= sx;
when "10111000" => sim_spmB8 <= sx;
when "10111001" => sim_spmB9 <= sx;
when "10111010" => sim_spmBA <= sx;
when "10111011" => sim_spmBB <= sx;
when "10111100" => sim_spmBC <= sx;
when "10111101" => sim_spmBD <= sx;
when "10111110" => sim_spmBE <= sx;
when "10111111" => sim_spmBF <= sx;
when "11000000" => sim_spmC0 <= sx;
when "11000001" => sim_spmC1 <= sx;
when "11000010" => sim_spmC2 <= sx;
when "11000011" => sim_spmC3 <= sx;
when "11000100" => sim_spmC4 <= sx;
when "11000101" => sim_spmC5 <= sx;
when "11000110" => sim_spmC6 <= sx;
when "11000111" => sim_spmC7 <= sx;
when "11001000" => sim_spmC8 <= sx;
when "11001001" => sim_spmC9 <= sx;
when "11001010" => sim_spmCA <= sx;
when "11001011" => sim_spmCB <= sx;
when "11001100" => sim_spmCC <= sx;
when "11001101" => sim_spmCD <= sx;
when "11001110" => sim_spmCE <= sx;
when "11001111" => sim_spmCF <= sx;
when "11010000" => sim_spmD0 <= sx;
when "11010001" => sim_spmD1 <= sx;
when "11010010" => sim_spmD2 <= sx;
when "11010011" => sim_spmD3 <= sx;
when "11010100" => sim_spmD4 <= sx;
when "11010101" => sim_spmD5 <= sx;
when "11010110" => sim_spmD6 <= sx;
when "11010111" => sim_spmD7 <= sx;
when "11011000" => sim_spmD8 <= sx;
when "11011001" => sim_spmD9 <= sx;
when "11011010" => sim_spmDA <= sx;
when "11011011" => sim_spmDB <= sx;
when "11011100" => sim_spmDC <= sx;
when "11011101" => sim_spmDD <= sx;
when "11011110" => sim_spmDE <= sx;
when "11011111" => sim_spmDF <= sx;
when "11100000" => sim_spmE0 <= sx;
when "11100001" => sim_spmE1 <= sx;
when "11100010" => sim_spmE2 <= sx;
when "11100011" => sim_spmE3 <= sx;
when "11100100" => sim_spmE4 <= sx;
when "11100101" => sim_spmE5 <= sx;
when "11100110" => sim_spmE6 <= sx;
when "11100111" => sim_spmE7 <= sx;
when "11101000" => sim_spmE8 <= sx;
when "11101001" => sim_spmE9 <= sx;
when "11101010" => sim_spmEA <= sx;
when "11101011" => sim_spmEB <= sx;
when "11101100" => sim_spmEC <= sx;
when "11101101" => sim_spmED <= sx;
when "11101110" => sim_spmEE <= sx;
when "11101111" => sim_spmEF <= sx;
when "11110000" => sim_spmF0 <= sx;
when "11110001" => sim_spmF1 <= sx;
when "11110010" => sim_spmF2 <= sx;
when "11110011" => sim_spmF3 <= sx;
when "11110100" => sim_spmF4 <= sx;
when "11110101" => sim_spmF5 <= sx;
when "11110110" => sim_spmF6 <= sx;
when "11110111" => sim_spmF7 <= sx;
when "11111000" => sim_spmF8 <= sx;
when "11111001" => sim_spmF9 <= sx;
when "11111010" => sim_spmFA <= sx;
when "11111011" => sim_spmFB <= sx;
when "11111100" => sim_spmFC <= sx;
when "11111101" => sim_spmFD <= sx;
when "11111110" => sim_spmFE <= sx;
when "11111111" => sim_spmFF <= sx;
when others => null;
end case;
end if;
end if;
--
-- Assignment of internal register variables to active registers
--
if bank = '0' then
kcpsm6_status(1 to 2) <= "A,";
sim_s0 <= bank_a_s0;
sim_s1 <= bank_a_s1;
sim_s2 <= bank_a_s2;
sim_s3 <= bank_a_s3;
sim_s4 <= bank_a_s4;
sim_s5 <= bank_a_s5;
sim_s6 <= bank_a_s6;
sim_s7 <= bank_a_s7;
sim_s8 <= bank_a_s8;
sim_s9 <= bank_a_s9;
sim_sA <= bank_a_sA;
sim_sB <= bank_a_sB;
sim_sC <= bank_a_sC;
sim_sD <= bank_a_sD;
sim_sE <= bank_a_sE;
sim_sF <= bank_a_sF;
else
kcpsm6_status(1 to 2) <= "B,";
sim_s0 <= bank_b_s0;
sim_s1 <= bank_b_s1;
sim_s2 <= bank_b_s2;
sim_s3 <= bank_b_s3;
sim_s4 <= bank_b_s4;
sim_s5 <= bank_b_s5;
sim_s6 <= bank_b_s6;
sim_s7 <= bank_b_s7;
sim_s8 <= bank_b_s8;
sim_s9 <= bank_b_s9;
sim_sA <= bank_b_sA;
sim_sB <= bank_b_sB;
sim_sC <= bank_b_sC;
sim_sD <= bank_b_sD;
sim_sE <= bank_b_sE;
sim_sF <= bank_b_sF;
end if;
--
end process simulation;
--synthesis translate on
--
-- **************************
-- * End of simulation code *
-- **************************
--
--
-------------------------------------------------------------------------------------------
--
end low_level_definition;
--
-------------------------------------------------------------------------------------------
--
-- END OF FILE kcpsm6.vhd
--
-------------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_pntr
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_pntr.vhd
-- Description: This entity manages descriptor pointers and determine scatter
-- gather idle mode.
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/20/10 v1_00_a
-- ^^^^^^
-- CR568950
-- Qualified reseting of sg_idle from axi_sg_ftch_pntr with associated channel's
-- flush control.
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_pntr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32 ;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_INCLUDE_CH1 : integer range 0 to 1 := 1 ;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
nxtdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
------------------------------- --
-- CHANNEL 1 --
------------------------------- --
ch1_run_stop : in std_logic ; --
ch1_desc_flush : in std_logic ; --CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch1_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch1_tailpntr_enabled : in std_logic ; --
ch1_taildesc_wren : in std_logic ; --
ch1_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch1_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch1_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch1_sg_idle : out std_logic ; --
--
------------------------------- --
-- CHANNEL 2 --
------------------------------- --
ch2_run_stop : in std_logic ; --
ch2_desc_flush : in std_logic ;--CR568950 --
--
-- CURDESC update to fetch pointer on run/stop assertion --
ch2_curdesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- TAILDESC update on CPU write (from axi_dma_reg_module) --
ch2_tailpntr_enabled : in std_logic ; --
ch2_taildesc_wren : in std_logic ; --
ch2_taildesc : in std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
--
-- NXTDESC update on descriptor fetch (from axi_sg_ftchq_if) --
ch2_nxtdesc_wren : in std_logic ; --
--
-- Current address of descriptor to fetch --
ch2_fetch_address : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
ch2_sg_idle : out std_logic --
);
end axi_sg_ftch_pntr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_pntr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Constants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal ch1_run_stop_d1 : std_logic := '0';
signal ch1_run_stop_re : std_logic := '0';
signal ch1_use_crntdesc : std_logic := '0';
signal ch1_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
signal ch2_run_stop_d1 : std_logic := '0';
signal ch2_run_stop_re : std_logic := '0';
signal ch2_use_crntdesc : std_logic := '0';
signal ch2_fetch_address_i : std_logic_vector
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0)
:= (others => '0');
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- Channel 1 is included therefore generate pointer logic
GEN_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 1 generate
begin
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_run_stop_d1 <= '0';
else
ch1_run_stop_d1 <= ch1_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch1_run_stop_re <= ch1_run_stop and not ch1_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch1_nxtdesc_wren = '1')then
ch1_use_crntdesc <= '0';
elsif(ch1_run_stop_re = '1')then
ch1_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch1_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch1_use_crntdesc = '1' and ch1_nxtdesc_wren = '0')then
ch1_fetch_address_i <= ch1_curdesc;
-- On desriptor fetch capture next pointer
elsif(ch1_nxtdesc_wren = '1')then
ch1_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch1_fetch_address <= ch1_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch1_run_stop = '0' or ch1_desc_flush = '1')then
ch1_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch1_taildesc_wren = '1' or ch1_tailpntr_enabled = '0')then
ch1_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch1_nxtdesc_wren = '1'
and ch1_taildesc = ch1_fetch_address_i)then
ch1_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH1;
-- Channel 1 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH1 : if C_INCLUDE_CH1 = 0 generate
begin
ch1_fetch_address <= (others =>'0');
ch1_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH1;
-- Channel 2 is included therefore generate pointer logic
GEN_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- Create clock delay of run_stop in order to generate a rising edge pulse
---------------------------------------------------------------------------
GEN_RUNSTOP_RE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_run_stop_d1 <= '0';
else
ch2_run_stop_d1 <= ch2_run_stop;
end if;
end if;
end process GEN_RUNSTOP_RE;
ch2_run_stop_re <= ch2_run_stop and not ch2_run_stop_d1;
---------------------------------------------------------------------------
-- At setting of run/stop need to use current descriptor pointer therefor
-- flag for use
---------------------------------------------------------------------------
GEN_INIT_PNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or ch2_nxtdesc_wren = '1')then
ch2_use_crntdesc <= '0';
elsif(ch2_run_stop_re = '1')then
ch2_use_crntdesc <= '1';
end if;
end if;
end process GEN_INIT_PNTR;
---------------------------------------------------------------------------
-- Register Current Fetch Address. During start (run/stop asserts) reg
-- curdesc pointer from register module. Once running use nxtdesc pointer.
---------------------------------------------------------------------------
REG_FETCH_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
ch2_fetch_address_i <= (others => '0');
-- On initial tail pointer write use current desc pointer
elsif(ch2_use_crntdesc = '1' and ch2_nxtdesc_wren = '0')then
ch2_fetch_address_i <= ch2_curdesc;
-- On descirptor fetch capture next pointer
elsif(ch2_nxtdesc_wren = '1')then
ch2_fetch_address_i <= nxtdesc;
end if;
end if;
end process REG_FETCH_ADDRESS;
-- Pass address out of module
ch2_fetch_address <= ch2_fetch_address_i;
---------------------------------------------------------------------------
-- Compair tail descriptor pointer to scatter gather engine current
-- descriptor pointer. Set idle if matched. Only check if DMA engine
-- is running and current descriptor is in process of being fetched. This
-- forces at least 1 descriptor fetch before checking for IDLE condition.
---------------------------------------------------------------------------
COMPARE_ADDRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- SG is IDLE on reset and on stop.
--CR568950 - reset idlag on descriptor flush
--if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0')then
if(m_axi_sg_aresetn = '0' or ch2_run_stop = '0' or ch2_desc_flush = '1')then
ch2_sg_idle <= '1';
-- taildesc_wren must be in this 'if' to force a minimum
-- of 1 clock of sg_idle = '0'.
elsif(ch2_taildesc_wren = '1' or ch2_tailpntr_enabled = '0')then
ch2_sg_idle <= '0';
-- Descriptor at fetch_address is being fetched (wren=1)
-- therefore safe to check if tail matches the fetch address
elsif(ch2_nxtdesc_wren = '1'
and ch2_taildesc = ch2_fetch_address_i)then
ch2_sg_idle <= '1';
end if;
end if;
end process COMPARE_ADDRESS;
end generate GEN_PNTR_FOR_CH2;
-- Channel 2 is NOT included therefore tie off pointer logic
GEN_NO_PNTR_FOR_CH2 : if C_INCLUDE_CH2 = 0 generate
begin
ch2_fetch_address <= (others =>'0');
ch2_sg_idle <= '0';
end generate GEN_NO_PNTR_FOR_CH2;
end implementation;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity StackPointer is
port (
D_IN_BUS : in STD_LOGIC_VECTOR (7 downto 0);
SEL : in STD_LOGIC_VECTOR (1 downto 0);
LD : in STD_LOGIC;
RST : in STD_LOGIC;
CLK : in STD_LOGIC;
D_OUT : out STD_LOGIC_VECTOR (7 downto 0);
D_OUT_DEC : out STD_LOGIC_VECTOR (7 downto 0)
);
end StackPointer;
architecture Stack of StackPointer is
signal SP : STD_LOGIC_VECTOR (7 downto 0) := x"00";
begin
-- Load new value if needed
LOAD : process (CLK, LD, SP, RST) begin
if (rising_edge(CLK)) then
if (LD = '1') then
if (SEL = "00") then
SP <= D_IN_BUS;
elsif (SEL = "10") then
SP <= SP - 1;
elsif (SEL = "11") then
SP <= SP + 1;
end if;
end if;
end if;
if (RST = '1') then
SP <= (others => '0');
end if;
end process LOAD;
-- Output resulting stack pointers
D_OUT <= SP;
D_OUT_DEC <= SP - 1;
end Stack;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc180.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p03n01i00180ent IS
END c04s04b00x00p03n01i00180ent;
ARCHITECTURE c04s04b00x00p03n01i00180arch OF c04s04b00x00p03n01i00180ent IS
attribute p: POSITIVE;
signal s: integer;
attribute p of s: signal is 10; -- Success_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( s'p=10 )
report "***PASSED TEST: c04s04b00x00p03n01i00180"
severity NOTE;
assert ( s'p=10 )
report "***FAILED TEST: c04s04b00x00p03n01i00180 - In attribute declaration, the reserved word attribute must be followed by an identifier, a colon, a type mark and a semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p03n01i00180arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc180.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p03n01i00180ent IS
END c04s04b00x00p03n01i00180ent;
ARCHITECTURE c04s04b00x00p03n01i00180arch OF c04s04b00x00p03n01i00180ent IS
attribute p: POSITIVE;
signal s: integer;
attribute p of s: signal is 10; -- Success_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( s'p=10 )
report "***PASSED TEST: c04s04b00x00p03n01i00180"
severity NOTE;
assert ( s'p=10 )
report "***FAILED TEST: c04s04b00x00p03n01i00180 - In attribute declaration, the reserved word attribute must be followed by an identifier, a colon, a type mark and a semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p03n01i00180arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc180.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s04b00x00p03n01i00180ent IS
END c04s04b00x00p03n01i00180ent;
ARCHITECTURE c04s04b00x00p03n01i00180arch OF c04s04b00x00p03n01i00180ent IS
attribute p: POSITIVE;
signal s: integer;
attribute p of s: signal is 10; -- Success_here
BEGIN
TESTING: PROCESS
BEGIN
wait for 10 ns;
assert NOT( s'p=10 )
report "***PASSED TEST: c04s04b00x00p03n01i00180"
severity NOTE;
assert ( s'p=10 )
report "***FAILED TEST: c04s04b00x00p03n01i00180 - In attribute declaration, the reserved word attribute must be followed by an identifier, a colon, a type mark and a semicolon."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s04b00x00p03n01i00180arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: misc
-- File: mul_dware.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Dware multipliers
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity mul_dw is
generic (
a_width : positive := 2; -- multiplier word width
b_width : positive := 2; -- multiplicand word width
num_stages : positive := 2; -- number of pipeline stages
stall_mode : natural range 0 to 1 := 1 -- '0': non-stallable; '1': stallable
);
port(a : in std_logic_vector(a_width-1 downto 0);
b : in std_logic_vector(b_width-1 downto 0);
clk : in std_logic;
en : in std_logic;
sign : in std_logic;
product : out std_logic_vector(a_width+b_width-1 downto 0));
end;
architecture rtl of mul_dw is
component DW02_mult
generic( A_width: NATURAL; -- multiplier wordlength
B_width: NATURAL); -- multiplicand wordlength
port(A : in std_logic_vector(A_width-1 downto 0);
B : in std_logic_vector(B_width-1 downto 0);
TC : in std_logic; -- signed -> '1', unsigned -> '0'
PRODUCT : out std_logic_vector(A_width+B_width-1 downto 0));
end component;
signal gnd : std_ulogic;
begin
gnd <= '0';
np : if num_stages = 1 generate
u0 : DW02_mult
generic map ( a_width => a_width, b_width => b_width)
port map (a => a, b => b, TC => sign, product => product);
end generate;
pipe : if num_stages > 1 generate
u0 : DW_mult_pipe
generic map ( a_width => a_width, b_width => b_width,
num_stages => num_stages, stall_mode => stall_mode, rst_mode => 0)
port map (a => a, b => b, TC => sign, clk => clk, product => product,
rst_n => gnd, en => en);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
library Dware;
use DWARE.DWpackages.all;
use DWARE.DW_Foundation_comp_arith.all;
entity dw_mul_61x61 is
port(A : in std_logic_vector(60 downto 0);
B : in std_logic_vector(60 downto 0);
CLK : in std_logic;
PRODUCT : out std_logic_vector(121 downto 0));
end;
architecture rtl of dw_mul_61x61 is
signal gnd : std_ulogic;
signal pin, p : std_logic_vector(121 downto 0);
begin
gnd <= '0';
-- u0 : DW02_mult_2_stage
-- generic map ( A_width => A'length, B_width => B'length )
-- port map ( A => A, B => B, TC => gnd, CLK => CLK, PRODUCT => pin );
u0 : DW_mult_pipe
generic map ( a_width => 61, b_width => 61,
num_stages => 2, stall_mode => 0, rst_mode => 0)
port map (a => a, b => b, TC => gnd, clk => clk, product => pin,
rst_n => gnd, en => gnd);
reg0 : process(CLK)
begin
if rising_edge(CLK) then
p <= pin;
end if;
end process;
PRODUCT <= p;
end;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
USE ieee.numeric_std.ALL;
ENTITY kernel_tb IS
END kernel_tb;
ARCHITECTURE behavior OF kernel_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT kernel
PORT(
IN1 : IN std_logic_vector(7 downto 0);
IN2 : IN std_logic_vector(7 downto 0);
IN3 : IN std_logic_vector(7 downto 0);
IN4 : IN std_logic_vector(7 downto 0);
IN5 : IN std_logic_vector(7 downto 0);
IN6 : IN std_logic_vector(7 downto 0);
IN7 : IN std_logic_vector(7 downto 0);
IN8 : IN std_logic_vector(7 downto 0);
IN9 : IN std_logic_vector(7 downto 0);
m1 : IN signed(3 downto 0);
m2 : IN signed(3 downto 0);
m3 : IN signed(3 downto 0);
m4 : IN signed(3 downto 0);
m5 : IN signed(3 downto 0);
m6 : IN signed(3 downto 0);
m7 : IN signed(3 downto 0);
m8 : IN signed(3 downto 0);
m9 : IN signed(3 downto 0);
divider_selector : IN std_logic;
WR_EN: in std_logic;
RD_EN: out std_logic;
OP : OUT std_logic_vector(7 downto 0);
RESET : IN std_logic;
clk : IN std_logic
);
END COMPONENT;
--Inputs
signal IN1 : std_logic_vector(7 downto 0) := (others => '0');
signal IN2 : std_logic_vector(7 downto 0) := (others => '0');
signal IN3 : std_logic_vector(7 downto 0) := (others => '0');
signal IN4 : std_logic_vector(7 downto 0) := (others => '0');
signal IN5 : std_logic_vector(7 downto 0) := (others => '0');
signal IN6 : std_logic_vector(7 downto 0) := (others => '0');
signal IN7 : std_logic_vector(7 downto 0) := (others => '0');
signal IN8 : std_logic_vector(7 downto 0) := (others => '0');
signal IN9 : std_logic_vector(7 downto 0) := (others => '0');
signal m1 : signed(3 downto 0) := (others => '0');
signal m2 : signed(3 downto 0) := (others => '0');
signal m3 : signed(3 downto 0) := (others => '0');
signal m4 : signed(3 downto 0) := (others => '0');
signal m5 : signed(3 downto 0) := (others => '0');
signal m6 : signed(3 downto 0) := (others => '0');
signal m7 : signed(3 downto 0) := (others => '0');
signal m8 : signed(3 downto 0) := (others => '0');
signal m9 : signed(3 downto 0) := (others => '0');
signal divider_selector : std_logic := '0';
signal WR_EN: std_logic := '0';
signal RD_EN: std_logic := '0';
signal RESET : std_logic := '0';
signal clk : std_logic := '0';
--Outputs
signal OP : std_logic_vector(7 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: kernel PORT MAP (
IN1 => IN1,
IN2 => IN2,
IN3 => IN3,
IN4 => IN4,
IN5 => IN5,
IN6 => IN6,
IN7 => IN7,
IN8 => IN8,
IN9 => IN9,
m1 => m1,
m2 => m2,
m3 => m3,
m4 => m4,
m5 => m5,
m6 => m6,
m7 => m7,
m8 => m8,
m9 => m9,
divider_selector => divider_selector,
WR_EN => WR_EN,
RD_EN => RD_EN,
OP => OP,
RESET => RESET,
clk => clk
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
reset <= '1';
wait for clk_period * 5;
reset <= '0';
wait for clk_period * 1;
m1 <= "1111";
m2 <= "1110";
m3 <= "1111";
m4 <= x"0";
m5 <= x"0";
m6 <= x"0";
m7 <= x"1";
m8 <= x"2";
m9 <= x"1";
-- m1 <= x"0";
-- m2 <= x"0";
-- m3 <= x"0";
-- m4 <= x"0";
-- m5 <= x"8";
-- m6 <= x"0";
-- m7 <= x"0";
-- m8 <= x"0";
-- m9 <= x"0";
wait for clk_period * 5;
WR_EN <= '1';
in1<=x"08";
in2<=x"01";
in3<=x"01";
in4<=x"01";
in5<=x"01";
in6<=x"01";
in7<=x"0c";
in8<=x"31";
in9<=x"FF";
wait for clk_period*1;
in1<=x"02";
in2<=x"02";
in3<=x"02";
in4<=x"02";
in5<=x"02";
in6<=x"02";
in7<=x"02";
in8<=x"02";
in9<=x"02";
wait for clk_period*1;
in1<=x"03";
in2<=x"03";
in3<=x"03";
in4<=x"03";
in5<=x"07";
in6<=x"03";
in7<=x"03";
in8<=x"03";
in9<=x"03";
wait for clk_period*1;
in1<="11111111";
in2<="11111111";
in3<="11111111";
in4<="11111111";
in5<="11111110";
in6<="11111111";
in7<="11111111";
in8<="11111111";
in9<="11111111";
wait for clk_period*1;
in1<="11111111";
in2<="11111111";
in3<="11111111";
in4<="11111111";
in5<="11111110";
in6<=x"22";
in7<=x"22";
in8<=x"0a";
in9<=x"0a";
wait for clk_period*1;
in1<=x"f2";
in2<=x"02";
in3<=x"33";
in4<=x"aa";
in5<=x"bb";
in6<=x"bc";
in7<=x"23";
in8<=x"2a";
in9<=x"1a";
wait for clk_period*1;
WR_EN <= '0';
wait for clk_period * 7;
assert false report "NONE. End of your simulation." severity failure;
end process;
END;
|
----------------------------------------------------------------------------------
-- Company: ITESM
-- Engineer: Miguel Gonzalez A01203712
--
-- Create Date: 09:42:15 09/11/2015
-- Design Name:
-- Module Name: Ripple_Counter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: 4 bit ripple adder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Ripple_Counter is
Port ( A : in STD_LOGIC_VECTOR (3 downto 0);
B : in STD_LOGIC_VECTOR (3 downto 0);
Cin : in STD_LOGIC;
Res : out STD_LOGIC_VECTOR (3 downto 0);
Cout : out STD_LOGIC);
end Ripple_Counter;
architecture Behavioral of Ripple_Counter is
signal C : STD_LOGIC_VECTOR (4 downto 0);
begin
ripple_adder: process(A, B, C, Cin)
begin
c(0) <= Cin;
for i in 0 to 3 loop
Res(i) <= A(i) xor B(i) xor C(i);
C(i+1) <= (A(i) and B(i)) or (A(i) and C(i)) or (B(i) and C(i));
end loop;
Cout <= C(4);
end process ripple_adder;
end Behavioral;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.3 (lin64) Build 2018833 Wed Oct 4 19:58:07 MDT 2017
-- Date : Tue Oct 17 18:54:10 2017
-- Host : TacitMonolith running 64-bit Ubuntu 16.04.3 LTS
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ ip_design_nco_0_0_stub.vhdl
-- Design : ip_design_nco_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
s_axi_AXILiteS_AWADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_AWVALID : in STD_LOGIC;
s_axi_AXILiteS_AWREADY : out STD_LOGIC;
s_axi_AXILiteS_WDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_WSTRB : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_AXILiteS_WVALID : in STD_LOGIC;
s_axi_AXILiteS_WREADY : out STD_LOGIC;
s_axi_AXILiteS_BRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_BVALID : out STD_LOGIC;
s_axi_AXILiteS_BREADY : in STD_LOGIC;
s_axi_AXILiteS_ARADDR : in STD_LOGIC_VECTOR ( 5 downto 0 );
s_axi_AXILiteS_ARVALID : in STD_LOGIC;
s_axi_AXILiteS_ARREADY : out STD_LOGIC;
s_axi_AXILiteS_RDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_AXILiteS_RRESP : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_AXILiteS_RVALID : out STD_LOGIC;
s_axi_AXILiteS_RREADY : in STD_LOGIC;
ap_clk : in STD_LOGIC;
ap_rst_n : in STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "s_axi_AXILiteS_AWADDR[5:0],s_axi_AXILiteS_AWVALID,s_axi_AXILiteS_AWREADY,s_axi_AXILiteS_WDATA[31:0],s_axi_AXILiteS_WSTRB[3:0],s_axi_AXILiteS_WVALID,s_axi_AXILiteS_WREADY,s_axi_AXILiteS_BRESP[1:0],s_axi_AXILiteS_BVALID,s_axi_AXILiteS_BREADY,s_axi_AXILiteS_ARADDR[5:0],s_axi_AXILiteS_ARVALID,s_axi_AXILiteS_ARREADY,s_axi_AXILiteS_RDATA[31:0],s_axi_AXILiteS_RRESP[1:0],s_axi_AXILiteS_RVALID,s_axi_AXILiteS_RREADY,ap_clk,ap_rst_n";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "nco,Vivado 2017.3";
begin
end;
|
------------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2013 Aeroflex Gaisler AB
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
use work.debug.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use gaisler.jtagtst.all;
library dare;
use work.config.all; -- configuration
entity testbench_netlist is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 1000; -- system clock period
romwidth : integer := 32; -- rom data width (8/32)
romdepth : integer := 20; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 20; -- ram address depth
srambanks : integer := 2; -- number of ram banks
testen : integer := 0;
scanen : integer := 0;
testrst : integer := 0;
testoen : integer := 0
);
end;
architecture behav of testbench_netlist is
constant promfile : string := "prom.srec"; -- rom contents
constant sramfile : string := "ram.srec"; -- ram contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(27 downto 0);
signal data : std_logic_vector(31 downto 0);
signal cb : std_logic_vector(15 downto 0);
signal ramsn : std_logic_vector(4 downto 0);
signal ramoen : std_logic_vector(4 downto 0);
signal rwen : std_logic_vector(3 downto 0);
signal rwenx : std_logic_vector(3 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal iosn : std_ulogic;
signal oen : std_ulogic;
signal read : std_ulogic;
signal writen : std_ulogic;
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdogn : std_logic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal error : std_logic;
signal gpio : std_logic_vector(CFG_GRGPIO_WIDTH-1 downto 0);
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal sdcke : std_logic_vector ( 1 downto 0); -- clk en
signal sdcsn : std_logic_vector ( 1 downto 0); -- chip sel
signal sdwen : std_ulogic; -- write en
signal sdrasn : std_ulogic; -- row addr stb
signal sdcasn : std_ulogic; -- col addr stb
signal sddqm : std_logic_vector ( 3 downto 0); -- data i/o mask
signal sdclk : std_ulogic := '0';
signal plllock : std_ulogic;
signal txd1, rxd1 : std_ulogic;
signal txd2, rxd2 : std_ulogic;
signal roen, roout, nandout, promedac : std_ulogic;
constant lresp : boolean := false;
signal gnd : std_logic_vector(3 downto 0);
signal clksel : std_logic_vector(1 downto 0);
signal promwidth: std_logic_vector(1 downto 0);
signal spw_clksel : std_logic_vector(1 downto 0);
signal spw_clk : std_ulogic := '0';
signal spw_rxdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsp : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_rxsn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txdn : std_logic_vector(0 to CFG_SPW_NUM-1);
signal spw_txsn : std_logic_vector(0 to CFG_SPW_NUM-1);
begin
-- clock and reset
test <= '0' when testen = 0 else '1';
rxd1 <= '1' when (testen = 1) and (testoen = 1) else
'0' when (testen = 1) and (testoen = 0) else txd1;
dsuen <= '1' when (testen = 1) and (testrst = 1) else
'0' when (testen = 1) and (testrst = 0) else '1';
dsubre <= '1' when (testen = 1) and (scanen = 1) else
'0' when (testen = 1) and (scanen = 0) else '0';
clksel <= "00";
spw_clksel <= "00";
error <= 'H';
gnd <= "0000";
clk <= not clk after ct * 1 ns;
spw_clk <= not spw_clk after 10 ns;
rst <= dsurst;
bexcn <= '1'; wdogn <= 'H';
gpio(2 downto 0) <= "HHL";
-- gpio(CFG_GRGPIO_WIDTH-1 downto 3) <= (others => 'H');
gpio(15 downto 11) <= "HLLHH"; --19
gpio(10 downto 8) <= "HLL"; --4
gpio(7 downto 0) <= (others => 'L');
cb(15 downto 8) <= "HHHHHHHH";
spw_rxdp <= spw_txdp; spw_rxsp <= spw_txsp;
spw_rxdn <= spw_txdn; spw_rxsn <= spw_txsn;
roen <= '0';
promedac <= '0';
promwidth <= "10";
rxd2 <= txd2;
d3 : entity dare.leon3mp
port map (rst, clksel, clk, error, wdogn, address, data,
cb(7 downto 0), sdclk, sdcsn, sdwen,
sdrasn, sdcasn, sddqm, dsutx, dsurx, dsuen, dsubre, dsuact,
txd1, rxd1, txd2, rxd2,
ramsn, ramoen, rwen, oen, writen, read, iosn, romsn, brdyn, bexcn, gpio,
promwidth, promedac,
spw_clksel, spw_clk, spw_rxdp, spw_rxdn, spw_rxsp, spw_rxsn, spw_txdp, spw_txdn,
spw_txsp, spw_txsn, gnd(0), roen, roout, nandout, test);
-- optional sdram
sd0 : if (CFG_MCTRLFT_SDEN = 1) and (CFG_MCTRLFT_SEPBUS = 0) generate
u0: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u1: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb0: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(0), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
u2: mt48lc16m16a2 generic map (index => 0, fname => sdramfile)
PORT MAP(
Dq => data(31 downto 16), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(3 downto 2));
u3: mt48lc16m16a2 generic map (index => 16, fname => sdramfile)
PORT MAP(
Dq => data(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
cb1: ftmt48lc16m16a2 generic map (index => 8, fname => sdramfile)
PORT MAP(
Dq => cb(15 downto 0), Addr => address(14 downto 2),
Ba => address(16 downto 15), Clk => sdclk, Cke => sdcke(0),
Cs_n => sdcsn(1), Ras_n => sdrasn, Cas_n => sdcasn, We_n => sdwen,
Dqm => sddqm(1 downto 0));
end generate;
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn(0),
rwen(i), oen);
end generate;
promcb0 : sramft generic map (index => 7, abits => romdepth, fname => promfile)
port map (address(romdepth+1 downto 2), cb(7 downto 0), romsn(0), writen, oen);
sram0 : for i in 0 to (sramwidth/8)-1 generate
sr0 : sram generic map (index => i, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), data(31-i*8 downto 24-i*8), ramsn(0),
rwen(0), ramoen(0));
end generate;
sramcb0 : sramft generic map (index => 7, abits => sramdepth, fname => sramfile)
port map (address(sramdepth+1 downto 2), cb(7 downto 0), ramsn(0), rwen(0), ramoen(0));
iuerr : process
begin
wait for (100*clkperiod) * 1 ns;
if to_x01(error) = '1' then wait on error; end if;
assert (to_x01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure ;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data), (others => 'H') after 250 ns;
cb <= buskeep(cb), (others => 'H') after 250 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := clkperiod*16 * 1 ns;
begin
dsutx <= '1';
dsurst <= '0';
wait for 500 ns;
dsurst <= '1';
wait; -- remove to run the DSU UART
wait for 5010 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#01#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0e#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#06#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#40#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#30#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
txc(dsutx, 16#c0#, txp);
txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
txc(dsutx, 16#80#, txp);
txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end ;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003, Gaisler Research
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: virage_simprims
-- File: virage_simprims.vhd
-- Author: Jiri Gaisler, Gaisler Research
-- Description: Simple simulation models for VIRAGE RAMs
-----------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
package virage_simprims is
component virage_syncram_sim
generic ( abits : integer := 10; dbits : integer := 8 );
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end component;
-- synchronous 2-port ram
component virage_2pram_sim
generic (
abits : integer := 8;
dbits : integer := 32;
words : integer := 256
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end component;
component virage_dpram_sim
generic (
abits : integer := 8;
dbits : integer := 32
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end component;
end;
-- 1-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_syncram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addr : in std_logic_vector((abits -1) downto 0);
clk : in std_logic;
di : in std_logic_vector((dbits -1) downto 0);
do : out std_logic_vector((dbits -1) downto 0);
me : in std_logic;
oe : in std_logic;
we : in std_logic
);
end;
architecture behavioral of virage_syncram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clk, oe, me)
variable memarr : mem;-- := (others => (others => '0'));
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clk) and (me = '1') and not is_x(addr) then
if (we = '1') then memarr(to_integer(unsigned(addr))) := di; end if;
doint := memarr(to_integer(unsigned(addr)));
end if;
-- if (me and oe) = '1' then do <= doint;
if oe = '1' then do <= doint;
else do <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous 2-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_2pram_sim is
generic (
abits : integer := 10;
dbits : integer := 8;
words : integer := 1024
);
port (
addra, addrb : in std_logic_vector((abits -1) downto 0);
clka, clkb : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
mea, wea, meb, oeb : in std_logic
);
end;
architecture behavioral of virage_2pram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (words-1)) of word;
begin
main : process(clka, clkb, oeb, mea, meb, wea)
variable memarr : mem;
variable doint : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra)) mod words) := dia; end if;
end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
doint := memarr(to_integer(unsigned(addrb)) mod words);
end if;
if oeb = '1' then dob <= doint;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
-- synchronous dual-port ram
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity virage_dpram_sim is
generic (
abits : integer := 10;
dbits : integer := 8
);
port (
addra : in std_logic_vector((abits -1) downto 0);
clka : in std_logic;
dia : in std_logic_vector((dbits -1) downto 0);
doa : out std_logic_vector((dbits -1) downto 0);
mea, oea, wea : in std_logic;
addrb : in std_logic_vector((abits -1) downto 0);
clkb : in std_logic;
dib : in std_logic_vector((dbits -1) downto 0);
dob : out std_logic_vector((dbits -1) downto 0);
meb, oeb, web : in std_logic
);
end;
architecture behavioral of virage_dpram_sim is
subtype word is std_logic_vector((dbits -1) downto 0);
type mem is array(0 to (2**abits -1)) of word;
begin
main : process(clka, oea, mea, clkb, oeb, meb)
variable memarr : mem;
variable dointa, dointb : std_logic_vector((dbits -1) downto 0);
begin
if rising_edge(clka) and (mea = '1') and not is_x(addra) then
if (wea = '1') then memarr(to_integer(unsigned(addra))) := dia; end if;
dointa := memarr(to_integer(unsigned(addra)));
end if;
if oea = '1' then doa <= dointa;
else doa <= (others => 'Z'); end if;
if rising_edge(clkb) and (meb = '1') and not is_x(addrb) then
if (web = '1') then memarr(to_integer(unsigned(addrb))) := dib; end if;
dointb := memarr(to_integer(unsigned(addrb)));
end if;
if oeb = '1' then dob <= dointb;
else dob <= (others => 'Z'); end if;
end process;
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_128x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(6 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_128x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 7, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_256x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(7 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_256x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 8, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_512x38cm4sw0ab is
port (
addr, taddr : in std_logic_vector(8 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(37 downto 0);
do : out std_logic_vector(37 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_512x38cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 9, dbits => 38)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_1024x32cm4sw0ab is
port (
addr, taddr : in std_logic_vector(9 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_1024x32cm4sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 10, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_2048x32cm8sw0ab is
port (
addr, taddr : in std_logic_vector(10 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(31 downto 0);
do : out std_logic_vector(31 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_2048x32cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 11, dbits => 32)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_4096x36cm8sw0ab is
port (
addr, taddr : in std_logic_vector(11 downto 0);
clk : in std_logic;
di, tdi : in std_logic_vector(35 downto 0);
do : out std_logic_vector(35 downto 0);
me, oe, we, tme, twe, awt, biste, toe : in std_logic
);
end;
architecture behavioral of hdss1_4096x36cm8sw0ab is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 12, dbits => 36)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss1_16384x8cm16sw0 is
port (
addr : in std_logic_vector(13 downto 0);
clk : in std_logic;
di : in std_logic_vector(7 downto 0);
do : out std_logic_vector(7 downto 0);
me, oe, we : in std_logic
);
end;
architecture behavioral of hdss1_16384x8cm16sw0 is
begin
syncram0 : virage_syncram_sim
generic map ( abits => 14, dbits => 8)
port map ( addr, clk, di, do, me, oe, we);
end behavioral;
-- 2-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_136x40cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(39 downto 0);
dob : out std_logic_vector(39 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_136x40cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 40, words => 136)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity rfss2_168x32cm2sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dob : out std_logic_vector(31 downto 0);
mea, wea, tmea, twea, bistea : in std_logic;
meb, oeb, tmeb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of rfss2_168x32cm2sw0ab is
begin
syncram0 : virage_2pram_sim
generic map ( abits => 8, dbits => 32, words => 168)
port map ( addra, addrb, clka, clkb, dia, dob, mea, wea, meb, oeb);
end behavioral;
-- dual-port syncronous ram
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_64x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(5 downto 0);
addrb, taddrb : in std_logic_vector(5 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_64x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 6, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_128x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(6 downto 0);
addrb, taddrb : in std_logic_vector(6 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_128x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 7, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_256x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(7 downto 0);
addrb, taddrb : in std_logic_vector(7 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_256x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 8, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x32cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(31 downto 0);
dib, tdib : in std_logic_vector(31 downto 0);
doa, dob : out std_logic_vector(31 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x32cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 32)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_512x38cm4sw0ab is
port (
addra, taddra : in std_logic_vector(8 downto 0);
addrb, taddrb : in std_logic_vector(8 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(37 downto 0);
dib, tdib : in std_logic_vector(37 downto 0);
doa, dob : out std_logic_vector(37 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_512x38cm4sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 9, dbits => 38)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
library ieee;
use ieee.std_logic_1164.all;
library virage;
use virage.virage_simprims.all;
entity hdss2_8192x8cm16sw0ab is
port (
addra, taddra : in std_logic_vector(12 downto 0);
addrb, taddrb : in std_logic_vector(12 downto 0);
clka, clkb : in std_logic;
dia, tdia : in std_logic_vector(7 downto 0);
dib, tdib : in std_logic_vector(7 downto 0);
doa, dob : out std_logic_vector(7 downto 0);
mea, oea, wea, tmea, twea, awta, bistea, toea : in std_logic;
meb, oeb, web, tmeb, tweb, awtb, bisteb, toeb : in std_logic
);
end;
architecture behavioral of hdss2_8192x8cm16sw0ab is
begin
syncram0 : virage_dpram_sim
generic map ( abits => 13, dbits => 8)
port map ( addra, clka, dia, doa, mea, oea, wea,
addrb, clkb, dib, dob, meb, oeb, web);
end behavioral;
-- pragma translate_on
|
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