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------------------------------------------------------------
-- implemented the 8 Byte X 24 byte memory
--
-- Instruction memory on it is the following:
--
-- ADDI R0, 2 ; ADDI R0<-2 500002
-- ADDI R1, 1 ; ADDI R1<-1 510001
-- ADD R0, R1 ; ADD R0<-R0 + R1 001000
-- AND R0, R1 ; AND R0<-R0 & R1 201000
-- OR R0, R1 ; OR R0<-R0 or R1 301000
-- ADD R0, R1 ; ADD R0<-R0 + R1 001000
-- MOV R5, R0 ; R5 <- R0 450000
--
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
entity RAM_8x24 is
generic(
RAM_WIDTH: integer:=8; -- 00 - FF choice
DATA_WIDTH: integer:=24
);
port(
CLOCK : in std_logic;
WE : in std_logic;
--OUTPUT RAM
OUT_ADDR : in std_logic_vector(RAM_WIDTH-1 downto 0);
OUT_DATA : out std_logic_vector(DATA_WIDTH-1 downto 0);
--INPUT RAM
IN_ADDR : in std_logic_vector(RAM_WIDTH-1 downto 0);
IN_DATA : in std_logic_vector(DATA_WIDTH-1 downto 0)
);
end RAM_8x24;
architecture RAM_ARCH of RAM_8x24 is
type ram_type is array (0 to 2**RAM_WIDTH-1) of std_logic_vector (DATA_WIDTH-1 downto 0);
signal RAM : ram_type := (
x"500002", x"510001", x"001000", x"201000", x"301000", x"001000", x"450000", x"000000", -- 00 - 07
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 08 - 0F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 10 - 17
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 18 - 1F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 20 - 27
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 28 - 2F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 30 - 37
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 38 - 3F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 40 - 47
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 48 - 4F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 50 - 57
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 58 - 5F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 60 - 67
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 68 - 6F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 70 - 77
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 78 - 7F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 80 - 87
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 88 - 8F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 90 - 97
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- 98 - 9F
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- A0 - A7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- A8 - AF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- B0 - B7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- B8 - BF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- C0 - C7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- C8 - CF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- D0 - D7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- D8 - DF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- E0 - E7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- E8 - EF
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", -- F0 - F7
x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000", x"000000" -- F8 - FF
);
signal ADDR_IN: std_logic_vector(RAM_WIDTH-1 downto 0);
begin
process(CLOCK,WE)
begin
if (CLOCK'event and CLOCK = '0') then
if (WE = '1') then
RAM(to_integer(unsigned(IN_ADDR))) <= IN_DATA;
end if;
ADDR_IN <= OUT_ADDR;
end if;
end process;
OUT_DATA <= RAM(to_integer(unsigned(ADDR_IN)));
end RAM_ARCH;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2011-2014, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- KCPSM6 reference design using 'uart_tx6' and 'uart_rx6'macros.
--
-- Ken Chapman - Xilinx Ltd.
--
-- 20th June 2014 - Initial version for KC705 board using Vivado 2014.1
--
-- This reference design provides a simple UART communication example. Please see
-- 'UART6_User_Guide_and_Reference_Designs_30Sept14.pdf' (or later) for more detailed
-- descriptions.
--
-- The KC705 board provides a 200MHz clock to the Kintex-7 device which is used by all
-- circuits in this design including KCPSM6 and the UART macros. In this example, KCPSM6
-- computes a constant which is applied to a clock division circuit to define a UART
-- communication BAUD rate of 115200.
--
-- Whilst the design is presented as a working example for the XC7K325TFFG900-2 device on
-- the KC705 Evaluation Board (www.xilinx.com), it is a simple reference design that is
-- easily adapted or incorporated into a design for use with any hardware platform. Indeed,
-- the method presented to define the BAUD rate can make this code even easier to port as
-- it only requires one constant to be defined and KCPSM6 works out everything else.
--
--
-------------------------------------------------------------------------------------------
--
-- Library declarations
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
-------------------------------------------------------------------------------------------
--
--
entity uart6_kc705 is
Port ( uart_rx : in std_logic;
uart_tx : out std_logic;
clk200_p : in std_logic;
clk200_n : in std_logic);
end uart6_kc705;
--
-------------------------------------------------------------------------------------------
--
-- Start of test architecture
--
architecture Behavioral of uart6_kc705 is
--
-------------------------------------------------------------------------------------------
--
-- Components
--
-------------------------------------------------------------------------------------------
--
--
-- declaration of KCPSM6
--
component kcpsm6
generic( hwbuild : std_logic_vector(7 downto 0) := X"00";
interrupt_vector : std_logic_vector(11 downto 0) := X"3FF";
scratch_pad_memory_size : integer := 64);
port ( address : out std_logic_vector(11 downto 0);
instruction : in std_logic_vector(17 downto 0);
bram_enable : out std_logic;
in_port : in std_logic_vector(7 downto 0);
out_port : out std_logic_vector(7 downto 0);
port_id : out std_logic_vector(7 downto 0);
write_strobe : out std_logic;
k_write_strobe : out std_logic;
read_strobe : out std_logic;
interrupt : in std_logic;
interrupt_ack : out std_logic;
sleep : in std_logic;
reset : in std_logic;
clk : in std_logic);
end component;
--
-- Development Program Memory
--
component auto_baud_rate_control
generic( C_FAMILY : string := "S6";
C_RAM_SIZE_KWORDS : integer := 1;
C_JTAG_LOADER_ENABLE : integer := 0);
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
rdl : out std_logic;
clk : in std_logic);
end component;
--
-- UART Transmitter with integral 16 byte FIFO buffer
--
component uart_tx6
Port ( data_in : in std_logic_vector(7 downto 0);
en_16_x_baud : in std_logic;
serial_out : out std_logic;
buffer_write : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
-- UART Receiver with integral 16 byte FIFO buffer
--
component uart_rx6
Port ( serial_in : in std_logic;
en_16_x_baud : in std_logic;
data_out : out std_logic_vector(7 downto 0);
buffer_read : in std_logic;
buffer_data_present : out std_logic;
buffer_half_full : out std_logic;
buffer_full : out std_logic;
buffer_reset : in std_logic;
clk : in std_logic);
end component;
--
--
-------------------------------------------------------------------------------------------
--
-- Signals
--
-------------------------------------------------------------------------------------------
--
--
-- Signals used to create internal 200MHz clock from 200MHz differential clock
--
signal clk200 : std_logic;
signal clk : std_logic;
--
-- Constant to specify the clock frequency in megahertz.
--
constant clock_frequency_in_MHz : integer range 0 to 255 := 200;
--
--
-- Signals used to connect KCPSM6
--
signal address : std_logic_vector(11 downto 0);
signal instruction : std_logic_vector(17 downto 0);
signal bram_enable : std_logic;
signal in_port : std_logic_vector(7 downto 0);
signal out_port : std_logic_vector(7 downto 0);
signal port_id : std_logic_vector(7 downto 0);
signal write_strobe : std_logic;
signal k_write_strobe : std_logic;
signal read_strobe : std_logic;
signal interrupt : std_logic;
signal interrupt_ack : std_logic;
signal kcpsm6_sleep : std_logic;
signal kcpsm6_reset : std_logic;
signal rdl : std_logic;
--
-- Signals used to connect UART_TX6
--
signal uart_tx_data_in : std_logic_vector(7 downto 0);
signal write_to_uart_tx : std_logic;
signal pipe_port_id0 : std_logic := '0';
signal uart_tx_data_present : std_logic;
signal uart_tx_half_full : std_logic;
signal uart_tx_full : std_logic;
signal uart_tx_reset : std_logic;
--
-- Signals used to connect UART_RX6
--
signal uart_rx_data_out : std_logic_vector(7 downto 0);
signal read_from_uart_rx : std_logic := '0';
signal uart_rx_data_present : std_logic;
signal uart_rx_half_full : std_logic;
signal uart_rx_full : std_logic;
signal uart_rx_reset : std_logic;
--
-- Signals used to define baud rate
--
signal set_baud_rate : std_logic_vector(7 downto 0) := "00000000";
signal baud_rate_counter : std_logic_vector(7 downto 0) := "00000000";
signal en_16_x_baud : std_logic := '0';
--
--
-------------------------------------------------------------------------------------------
--
-- Start of circuit description
--
-------------------------------------------------------------------------------------------
--
begin
--
-----------------------------------------------------------------------------------------
-- Create and distribute an internal 200MHz clock from 200MHz differential clock
-----------------------------------------------------------------------------------------
--
diff_clk_buffer: IBUFGDS
port map ( I => clk200_p,
IB => clk200_n,
O => clk200);
--
-- BUFG used to reach the entire device with 200MHz
--
buffer200: BUFG
port map ( I => clk200,
O => clk);
--
-----------------------------------------------------------------------------------------
-- Instantiate KCPSM6 and connect to program ROM
-----------------------------------------------------------------------------------------
--
-- The generics can be defined as required. In this case the 'hwbuild' value is used to
-- define a version using the ASCII code for the desired letter.
--
processor: kcpsm6
generic map ( hwbuild => X"41", -- 41 hex is ASCII Character "A"
interrupt_vector => X"7FF",
scratch_pad_memory_size => 64)
port map( address => address,
instruction => instruction,
bram_enable => bram_enable,
port_id => port_id,
write_strobe => write_strobe,
k_write_strobe => k_write_strobe,
out_port => out_port,
read_strobe => read_strobe,
in_port => in_port,
interrupt => interrupt,
interrupt_ack => interrupt_ack,
sleep => kcpsm6_sleep,
reset => kcpsm6_reset,
clk => clk);
--
-- Reset connected to JTAG Loader enabled Program Memory
--
kcpsm6_reset <= rdl;
--
-- Unused signals tied off until required.
-- Tying to other signals used to minimise warning messages.
--
kcpsm6_sleep <= write_strobe and k_write_strobe; -- Always '0'
interrupt <= interrupt_ack;
--
-- Development Program Memory
-- JTAG Loader enabled for rapid code development.
--
program_rom: auto_baud_rate_control
generic map( C_FAMILY => "7S",
C_RAM_SIZE_KWORDS => 2,
C_JTAG_LOADER_ENABLE => 1)
port map( address => address,
instruction => instruction,
enable => bram_enable,
rdl => rdl,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART Transmitter with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Write to buffer in UART Transmitter at port address 01 hex
--
tx: uart_tx6
port map ( data_in => uart_tx_data_in,
en_16_x_baud => en_16_x_baud,
serial_out => uart_tx,
buffer_write => write_to_uart_tx,
buffer_data_present => uart_tx_data_present,
buffer_half_full => uart_tx_half_full,
buffer_full => uart_tx_full,
buffer_reset => uart_tx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART Receiver with integral 16 byte FIFO buffer
-----------------------------------------------------------------------------------------
--
-- Read from buffer in UART Receiver at port address 01 hex.
--
-- When KCPMS6 reads data from the receiver a pulse must be generated so that the
-- FIFO buffer presents the next character to be read and updates the buffer flags.
--
rx: uart_rx6
port map ( serial_in => uart_rx,
en_16_x_baud => en_16_x_baud,
data_out => uart_rx_data_out,
buffer_read => read_from_uart_rx,
buffer_data_present => uart_rx_data_present,
buffer_half_full => uart_rx_half_full,
buffer_full => uart_rx_full,
buffer_reset => uart_rx_reset,
clk => clk);
--
-----------------------------------------------------------------------------------------
-- UART baud rate
-----------------------------------------------------------------------------------------
--
-- The baud rate is defined by the frequency of 'en_16_x_baud' pulses. These should occur
-- at 16 times the desired baud rate. KCPSM6 computes and sets an 8-bit value into
-- 'set_baud_rate' which is used to divide the clock frequency appropriately.
--
-- For example, if the clock frequency is 200MHz and the desired serial communication
-- baud rate is 115200 then PicoBlaze will set 'set_baud_rate' to 6C hex (108 decimal).
-- This circuit will then generate an 'en_16_x_baud' pulse once every 109 clock cycles
-- (note that 'baud_rate_counter' will include state zero). This would actually result
-- in a baud rate of 114,679 baud but that is only 0.45% low and well within limits.
--
baud_rate: process(clk)
begin
if clk'event and clk = '1' then
if baud_rate_counter = set_baud_rate then
baud_rate_counter <= "00000000";
en_16_x_baud <= '1'; -- single cycle enable pulse
else
baud_rate_counter <= baud_rate_counter + 1;
en_16_x_baud <= '0';
end if;
end if;
end process baud_rate;
--
-----------------------------------------------------------------------------------------
-- General Purpose Input Ports.
-----------------------------------------------------------------------------------------
--
-- Three input ports are used with the UART macros.
--
-- The first is used to monitor the flags on both the transmitter and receiver.
-- The second is used to read the data from the receiver and generate a 'buffer_read'
-- pulse.
-- The third is used to read a user defined constant that enabled KCPSM6 to know the
-- clock frequency so that it can compute values which will define the BAUD rate
-- for UART communications (as well as values used to define software delays).
--
input_ports: process(clk)
begin
if clk'event and clk = '1' then
case port_id(1 downto 0) is
-- Read UART status at port address 00 hex
when "00" => in_port(0) <= uart_tx_data_present;
in_port(1) <= uart_tx_half_full;
in_port(2) <= uart_tx_full;
in_port(3) <= uart_rx_data_present;
in_port(4) <= uart_rx_half_full;
in_port(5) <= uart_rx_full;
-- Read UART_RX6 data at port address 01 hex
-- (see 'buffer_read' pulse generation below)
when "01" => in_port <= uart_rx_data_out;
-- Read clock frequency contant at port address 02 hex
when "10" => in_port <= conv_std_logic_vector(clock_frequency_in_MHz, 8);
-- Specify don't care for all other inputs to obtain optimum implementation
when others => in_port <= "XXXXXXXX";
end case;
-- Generate 'buffer_read' pulse following read from port address 01
if (read_strobe = '1') and (port_id(1 downto 0) = "01") then
read_from_uart_rx <= '1';
else
read_from_uart_rx <= '0';
end if;
end if;
end process input_ports;
--
-----------------------------------------------------------------------------------------
-- General Purpose Output Ports
-----------------------------------------------------------------------------------------
--
-- In this design there are two general purpose output ports.
--
-- A port used to write data directly to the FIFO buffer within 'uart_tx6' macro.
--
-- A port used to define the communication BAUD rate of the UART.
--
-- Note that the assignment and decoding of 'port_id' is a one-hot resulting
-- in the minimum number of signals actually being decoded for a fast and
-- optimum implementation.
--
output_ports: process(clk)
begin
if clk'event and clk = '1' then
-- 'write_strobe' is used to qualify all writes to general output ports.
if write_strobe = '1' then
-- Write to UART at port addresses 01 hex
-- See below this clocked process for the combinatorial decode required.
-- Write to 'set_baud_rate' at port addresses 02 hex
-- This value is set by KCPSM6 to define the BAUD rate of the UART.
-- See the 'UART baud rate' section for details.
if (port_id(1) = '1') then
set_baud_rate <= out_port;
end if;
end if;
--
-- *** To reliably achieve 200MHz performance when writing to the FIFO buffer
-- within the UART transmitter, 'port_id' is pipelined to exploit both of
-- the clock cycles that it is valid.
--
pipe_port_id0 <= port_id(0);
end if;
end process output_ports;
--
-- Write directly to the FIFO buffer within 'uart_tx6' macro at port address 01 hex.
-- Note the direct connection of 'out_port' to the UART transmitter macro and the
-- way that a single clock cycle write pulse is generated to capture the data.
--
uart_tx_data_in <= out_port;
-- See *** above for definition of 'pipe_port_id0'.
write_to_uart_tx <= '1' when (write_strobe = '1') and (pipe_port_id0 = '1')
else '0';
--
-----------------------------------------------------------------------------------------
-- Constant-Optimised Output Ports
-----------------------------------------------------------------------------------------
--
-- One constant-optimised output port is used to facilitate resetting of the UART macros.
--
constant_output_ports: process(clk)
begin
if clk'event and clk = '1' then
if k_write_strobe = '1' then
if port_id(0) = '1' then
uart_tx_reset <= out_port(0);
uart_rx_reset <= out_port(1);
end if;
end if;
end if;
end process constant_output_ports;
--
-----------------------------------------------------------------------------------------
--
end Behavioral;
-------------------------------------------------------------------------------------------
--
-- END OF FILE uart6_kc705.vhd
--
-------------------------------------------------------------------------------------------
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
constant NI_reserved_data_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant NI_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant NI_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
constant uart_count_value_address : std_logic_vector(29 downto 0) := "000000000000000010000000000100";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component NI
generic(current_address : integer := 10 -- the current node's address
); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
--NI_read_flag : out std_logic;
--NI_write_flag : out std_logic;
irq_out : out std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --network interface
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
component memory
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end component; --entity memory
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable A1, B1, S : UNSIGNED(a'length downto 0);
begin
A1 := resize(unsigned(a), A1'length);
B1 := resize(unsigned(b), B1'length);
if do_add = '1' then
S := A1 + B1;
else
S := A1 - B1;
end if;
return std_logic_vector(S);
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
constant NI_reserved_data_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant NI_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant NI_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
constant uart_count_value_address : std_logic_vector(29 downto 0) := "000000000000000010000000000100";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component NI
generic(current_address : integer := 10 -- the current node's address
); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
--NI_read_flag : out std_logic;
--NI_write_flag : out std_logic;
irq_out : out std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --network interface
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
component memory
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end component; --entity memory
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable A1, B1, S : UNSIGNED(a'length downto 0);
begin
A1 := resize(unsigned(a), A1'length);
B1 := resize(unsigned(b), B1'length);
if do_add = '1' then
S := A1 + B1;
else
S := A1 - B1;
end if;
return std_logic_vector(S);
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
constant NI_reserved_data_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant NI_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant NI_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
constant uart_count_value_address : std_logic_vector(29 downto 0) := "000000000000000010000000000100";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
component ram
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
enable : in std_logic;
reset : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end component; --ram
component NI
generic(current_address : integer := 10 -- the current node's address
); -- reserved address for the counter
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
--NI_read_flag : out std_logic;
--NI_write_flag : out std_logic;
irq_out : out std_logic;
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --network interface
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
component memory
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end component; --entity memory
end; --package mlite_pack
package body mlite_pack is
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable A1, B1, S : UNSIGNED(a'length downto 0);
begin
A1 := resize(unsigned(a), A1'length);
B1 := resize(unsigned(b), B1'length);
if do_add = '1' then
S := A1 + B1;
else
S := A1 - B1;
end if;
return std_logic_vector(S);
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_reset.vhd
--
-- Description:
-- This file implements the DataMover Reset module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_datamover_reset is
generic (
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0
-- 0 = Use Synchronous Command/Statys User Interface
-- 1 = Use Asynchronous Command/Statys User Interface
);
port (
-- Primary Clock and Reset Inputs -----------------
--
primary_aclk : in std_logic; --
primary_aresetn : in std_logic; --
---------------------------------------------------
-- Async operation clock and reset from User ------
-- Used for Command/Status User interface --
-- synchronization when C_STSCMD_IS_ASYNC = 1 --
--
secondary_awclk : in std_logic; --
secondary_aresetn : in std_logic; --
---------------------------------------------------
-- Halt request input control -------------------------------
halt_req : in std_logic; --
-- Active high soft shutdown request (can be a pulse) --
--
-- Halt Complete status flag --
halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------------------
--
flush_stop_request : Out std_logic; --
-- Active high soft stop request to modules --
--
data_cntlr_stopped : in std_logic; --
-- Active high flag indicating the data controller is flushed and stopped --
--
addr_cntlr_stopped : in std_logic; --
-- Active high flag indicating the address controller is flushed and stopped --
--
aux1_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 1 module --
-- Tie high if unused --
--
aux2_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 2 module --
-- Tie high if unused --
------------------------------------------------------------------------------------
-- HW Reset outputs to reset groups -------------------------------------
--
cmd_stat_rst_user : Out std_logic; --
-- The reset to the Command/Status Module User interface side --
--
cmd_stat_rst_int : Out std_logic; --
-- The reset to the Command/Status Module internal interface side --
--
mmap_rst : Out std_logic; --
-- The reset to the Memory Map interface side --
--
stream_rst : Out std_logic --
-- The reset to the Stream interface side --
--------------------------------------------------------------------------
);
end entity axi_datamover_reset;
architecture implementation of axi_datamover_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
constant MTBF_STAGES : integer := 4;
-- ATTRIBUTE async_reg : STRING;
-- Signals
signal sig_cmd_stat_rst_user_n : std_logic := '0';
signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0';
signal sig_cmd_stat_rst_int_reg_n : std_logic := '0';
signal sig_mmap_rst_reg_n : std_logic := '0';
signal sig_stream_rst_reg_n : std_logic := '0';
signal sig_syncd_sec_rst : std_logic := '0';
-- soft shutdown support
signal sig_internal_reset : std_logic := '0';
signal sig_s_h_halt_reg : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
-- additional CDC synchronization signals
signal sig_sec_neg_edge_plus_delay : std_logic := '0';
signal sig_secondary_aresetn_reg : std_logic := '0';
signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0';
signal sig_prim2sec_rst_reg2_n : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true";
begin --(architecture implementation)
-- Assign outputs
cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n);
cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
mmap_rst <= not(sig_mmap_rst_reg_n) or
sig_syncd_sec_rst;
stream_rst <= not(sig_stream_rst_reg_n) or
sig_syncd_sec_rst;
-- Internal logic Implmentation
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Synchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_syncd_sec_rst <= '0';
sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from);
end generate GEN_SYNC_CMDSTAT_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Asynchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
-- ATTRIBUTE async_reg : STRING;
signal sig_sec_reset_in_reg_n : std_logic := '0';
signal sig_secondary_aresetn_reg_tmp : std_logic := '0';
-- Secondary reset pulse stretcher
signal sig_secondary_dly1 : std_logic := '0';
signal sig_secondary_dly2 : std_logic := '0';
signal sig_neg_edge_detect : std_logic := '0';
signal sig_sec2prim_reset : std_logic := '0';
signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0';
signal sig_sec2prim_reset_reg2 : std_logic := '0';
signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0';
signal sig_sec2prim_rst_syncro2 : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true";
begin
-- Generate the reset in the primary clock domain. Use the longer
-- of the pulse stretched reset or the actual reset.
sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or
sig_sec2prim_rst_syncro2;
-- Check for falling edge of secondary_aresetn input
sig_neg_edge_detect <= '1'
when (sig_sec_reset_in_reg_n = '1' and
secondary_aresetn = '0')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSE_STRETCH_FLOPS
--
-- Process Description:
-- This process implements a 3 clock wide pulse whenever the
-- secondary reset is asserted
--
-------------------------------------------------------------
IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
If (sig_secondary_dly2 = '1') Then
sig_secondary_dly1 <= '0' ;
sig_secondary_dly2 <= '0' ;
Elsif (sig_neg_edge_detect = '1') Then
sig_secondary_dly1 <= '1';
else
sig_secondary_dly2 <= sig_secondary_dly1 ;
End if;
end if;
end process IMP_PUSE_STRETCH_FLOPS;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_NEG_EDGE
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- negative edge detection,
--
-------------------------------------------------------------
SYNC_NEG_EDGE : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or
sig_secondary_dly1 or
sig_secondary_dly2;
end if;
end process SYNC_NEG_EDGE;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO
--
-- Process Description:
-- This process registers the secondary reset input to
-- the primary clock domain.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_sec_neg_edge_plus_delay,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_reset_reg2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ;
--
-- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig;
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SEC_RST
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- secondary reset input,
--
-------------------------------------------------------------
REG_SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_secondary_aresetn_reg <= secondary_aresetn;
end if;
end process REG_SEC_RST;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO_2
--
-- Process Description:
-- Second stage (destination) synchronizers for the secondary
-- reset CDC to the primary clock.
--
-------------------------------------------------------------
sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg);
SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_secondary_aresetn_reg_tmp,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_rst_syncro2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn);
-- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg);
-- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig;
--
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO_2;
-- Generate the Command and Status side reset
sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and
sig_prim2sec_rst_reg2_n;
-- CDC sig_cmd_stat_rst_user_reg_n_cdc_from;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RESET_ASYNC
--
-- Process Description:
-- This process registers the secondary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_RESET_ASYNC : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_reset_in_reg_n <= secondary_aresetn;
end if;
end process REG_RESET_ASYNC;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_PRIM2SEC_RST
--
-- Process Description:
-- Second (destination clock) stage synchronizers for CDC of
-- primary reset input,
--
-------------------------------------------------------------
SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => secondary_awclk,
scndry_resetn => '0',
scndry_out => sig_prim2sec_rst_reg2_n,
scndry_vect_out => open
);
-- SYNC_PRIM2SEC_RST : process (secondary_awclk)
-- begin
-- if (secondary_awclk'event and secondary_awclk = '1') then
--
-- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from;
-- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to;
--
-- end if;
-- end process SYNC_PRIM2SEC_RST;
--
end generate GEN_ASYNC_CMDSTAT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_PRIM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_PRIM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn;
end if;
end process REG_CMDSTAT_PRIM_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_INT_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status internal interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_INT_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_int_reg_n <= primary_aresetn;
end if;
end process REG_CMDSTAT_INT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_MMAP_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Memory Map interface reset.
--
-------------------------------------------------------------
REG_MMAP_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_rst_reg_n <= primary_aresetn;
end if;
end process REG_MMAP_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STREAM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Stream interface reset.
--
-------------------------------------------------------------
REG_STREAM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_stream_rst_reg_n <= primary_aresetn;
end if;
end process REG_STREAM_RESET;
-- Soft Shutdown logic ------------------------------------------------------
sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
flush_stop_request <= sig_s_h_halt_reg;
halt_cmplt <= sig_halt_cmplt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_HALT_REQ
--
-- Process Description:
-- Implements a sample and hold flop for the halt request
-- input. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
REG_HALT_REQ : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_s_h_halt_reg <= '0';
elsif (halt_req = '1') then
sig_s_h_halt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process REG_HALT_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT
--
-- Process Description:
-- Implements a the flop for the halt complete status
-- output. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_halt_cmplt <= '0';
elsif (data_cntlr_stopped = '1' and
addr_cntlr_stopped = '1' and
aux1_stopped = '1' and
aux2_stopped = '1') then
sig_halt_cmplt <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_reset.vhd
--
-- Description:
-- This file implements the DataMover Reset module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_datamover_reset is
generic (
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0
-- 0 = Use Synchronous Command/Statys User Interface
-- 1 = Use Asynchronous Command/Statys User Interface
);
port (
-- Primary Clock and Reset Inputs -----------------
--
primary_aclk : in std_logic; --
primary_aresetn : in std_logic; --
---------------------------------------------------
-- Async operation clock and reset from User ------
-- Used for Command/Status User interface --
-- synchronization when C_STSCMD_IS_ASYNC = 1 --
--
secondary_awclk : in std_logic; --
secondary_aresetn : in std_logic; --
---------------------------------------------------
-- Halt request input control -------------------------------
halt_req : in std_logic; --
-- Active high soft shutdown request (can be a pulse) --
--
-- Halt Complete status flag --
halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------------------
--
flush_stop_request : Out std_logic; --
-- Active high soft stop request to modules --
--
data_cntlr_stopped : in std_logic; --
-- Active high flag indicating the data controller is flushed and stopped --
--
addr_cntlr_stopped : in std_logic; --
-- Active high flag indicating the address controller is flushed and stopped --
--
aux1_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 1 module --
-- Tie high if unused --
--
aux2_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 2 module --
-- Tie high if unused --
------------------------------------------------------------------------------------
-- HW Reset outputs to reset groups -------------------------------------
--
cmd_stat_rst_user : Out std_logic; --
-- The reset to the Command/Status Module User interface side --
--
cmd_stat_rst_int : Out std_logic; --
-- The reset to the Command/Status Module internal interface side --
--
mmap_rst : Out std_logic; --
-- The reset to the Memory Map interface side --
--
stream_rst : Out std_logic --
-- The reset to the Stream interface side --
--------------------------------------------------------------------------
);
end entity axi_datamover_reset;
architecture implementation of axi_datamover_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
constant MTBF_STAGES : integer := 4;
-- ATTRIBUTE async_reg : STRING;
-- Signals
signal sig_cmd_stat_rst_user_n : std_logic := '0';
signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0';
signal sig_cmd_stat_rst_int_reg_n : std_logic := '0';
signal sig_mmap_rst_reg_n : std_logic := '0';
signal sig_stream_rst_reg_n : std_logic := '0';
signal sig_syncd_sec_rst : std_logic := '0';
-- soft shutdown support
signal sig_internal_reset : std_logic := '0';
signal sig_s_h_halt_reg : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
-- additional CDC synchronization signals
signal sig_sec_neg_edge_plus_delay : std_logic := '0';
signal sig_secondary_aresetn_reg : std_logic := '0';
signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0';
signal sig_prim2sec_rst_reg2_n : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true";
begin --(architecture implementation)
-- Assign outputs
cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n);
cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
mmap_rst <= not(sig_mmap_rst_reg_n) or
sig_syncd_sec_rst;
stream_rst <= not(sig_stream_rst_reg_n) or
sig_syncd_sec_rst;
-- Internal logic Implmentation
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Synchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_syncd_sec_rst <= '0';
sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from);
end generate GEN_SYNC_CMDSTAT_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Asynchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
-- ATTRIBUTE async_reg : STRING;
signal sig_sec_reset_in_reg_n : std_logic := '0';
signal sig_secondary_aresetn_reg_tmp : std_logic := '0';
-- Secondary reset pulse stretcher
signal sig_secondary_dly1 : std_logic := '0';
signal sig_secondary_dly2 : std_logic := '0';
signal sig_neg_edge_detect : std_logic := '0';
signal sig_sec2prim_reset : std_logic := '0';
signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0';
signal sig_sec2prim_reset_reg2 : std_logic := '0';
signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0';
signal sig_sec2prim_rst_syncro2 : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true";
begin
-- Generate the reset in the primary clock domain. Use the longer
-- of the pulse stretched reset or the actual reset.
sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or
sig_sec2prim_rst_syncro2;
-- Check for falling edge of secondary_aresetn input
sig_neg_edge_detect <= '1'
when (sig_sec_reset_in_reg_n = '1' and
secondary_aresetn = '0')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSE_STRETCH_FLOPS
--
-- Process Description:
-- This process implements a 3 clock wide pulse whenever the
-- secondary reset is asserted
--
-------------------------------------------------------------
IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
If (sig_secondary_dly2 = '1') Then
sig_secondary_dly1 <= '0' ;
sig_secondary_dly2 <= '0' ;
Elsif (sig_neg_edge_detect = '1') Then
sig_secondary_dly1 <= '1';
else
sig_secondary_dly2 <= sig_secondary_dly1 ;
End if;
end if;
end process IMP_PUSE_STRETCH_FLOPS;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_NEG_EDGE
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- negative edge detection,
--
-------------------------------------------------------------
SYNC_NEG_EDGE : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or
sig_secondary_dly1 or
sig_secondary_dly2;
end if;
end process SYNC_NEG_EDGE;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO
--
-- Process Description:
-- This process registers the secondary reset input to
-- the primary clock domain.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_sec_neg_edge_plus_delay,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_reset_reg2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ;
--
-- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig;
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SEC_RST
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- secondary reset input,
--
-------------------------------------------------------------
REG_SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_secondary_aresetn_reg <= secondary_aresetn;
end if;
end process REG_SEC_RST;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO_2
--
-- Process Description:
-- Second stage (destination) synchronizers for the secondary
-- reset CDC to the primary clock.
--
-------------------------------------------------------------
sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg);
SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_secondary_aresetn_reg_tmp,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_rst_syncro2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn);
-- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg);
-- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig;
--
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO_2;
-- Generate the Command and Status side reset
sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and
sig_prim2sec_rst_reg2_n;
-- CDC sig_cmd_stat_rst_user_reg_n_cdc_from;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RESET_ASYNC
--
-- Process Description:
-- This process registers the secondary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_RESET_ASYNC : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_reset_in_reg_n <= secondary_aresetn;
end if;
end process REG_RESET_ASYNC;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_PRIM2SEC_RST
--
-- Process Description:
-- Second (destination clock) stage synchronizers for CDC of
-- primary reset input,
--
-------------------------------------------------------------
SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => secondary_awclk,
scndry_resetn => '0',
scndry_out => sig_prim2sec_rst_reg2_n,
scndry_vect_out => open
);
-- SYNC_PRIM2SEC_RST : process (secondary_awclk)
-- begin
-- if (secondary_awclk'event and secondary_awclk = '1') then
--
-- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from;
-- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to;
--
-- end if;
-- end process SYNC_PRIM2SEC_RST;
--
end generate GEN_ASYNC_CMDSTAT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_PRIM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_PRIM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn;
end if;
end process REG_CMDSTAT_PRIM_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_INT_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status internal interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_INT_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_int_reg_n <= primary_aresetn;
end if;
end process REG_CMDSTAT_INT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_MMAP_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Memory Map interface reset.
--
-------------------------------------------------------------
REG_MMAP_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_rst_reg_n <= primary_aresetn;
end if;
end process REG_MMAP_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STREAM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Stream interface reset.
--
-------------------------------------------------------------
REG_STREAM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_stream_rst_reg_n <= primary_aresetn;
end if;
end process REG_STREAM_RESET;
-- Soft Shutdown logic ------------------------------------------------------
sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
flush_stop_request <= sig_s_h_halt_reg;
halt_cmplt <= sig_halt_cmplt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_HALT_REQ
--
-- Process Description:
-- Implements a sample and hold flop for the halt request
-- input. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
REG_HALT_REQ : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_s_h_halt_reg <= '0';
elsif (halt_req = '1') then
sig_s_h_halt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process REG_HALT_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT
--
-- Process Description:
-- Implements a the flop for the halt complete status
-- output. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_halt_cmplt <= '0';
elsif (data_cntlr_stopped = '1' and
addr_cntlr_stopped = '1' and
aux1_stopped = '1' and
aux2_stopped = '1') then
sig_halt_cmplt <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_reset.vhd
--
-- Description:
-- This file implements the DataMover Reset module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_datamover_reset is
generic (
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0
-- 0 = Use Synchronous Command/Statys User Interface
-- 1 = Use Asynchronous Command/Statys User Interface
);
port (
-- Primary Clock and Reset Inputs -----------------
--
primary_aclk : in std_logic; --
primary_aresetn : in std_logic; --
---------------------------------------------------
-- Async operation clock and reset from User ------
-- Used for Command/Status User interface --
-- synchronization when C_STSCMD_IS_ASYNC = 1 --
--
secondary_awclk : in std_logic; --
secondary_aresetn : in std_logic; --
---------------------------------------------------
-- Halt request input control -------------------------------
halt_req : in std_logic; --
-- Active high soft shutdown request (can be a pulse) --
--
-- Halt Complete status flag --
halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------------------
--
flush_stop_request : Out std_logic; --
-- Active high soft stop request to modules --
--
data_cntlr_stopped : in std_logic; --
-- Active high flag indicating the data controller is flushed and stopped --
--
addr_cntlr_stopped : in std_logic; --
-- Active high flag indicating the address controller is flushed and stopped --
--
aux1_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 1 module --
-- Tie high if unused --
--
aux2_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 2 module --
-- Tie high if unused --
------------------------------------------------------------------------------------
-- HW Reset outputs to reset groups -------------------------------------
--
cmd_stat_rst_user : Out std_logic; --
-- The reset to the Command/Status Module User interface side --
--
cmd_stat_rst_int : Out std_logic; --
-- The reset to the Command/Status Module internal interface side --
--
mmap_rst : Out std_logic; --
-- The reset to the Memory Map interface side --
--
stream_rst : Out std_logic --
-- The reset to the Stream interface side --
--------------------------------------------------------------------------
);
end entity axi_datamover_reset;
architecture implementation of axi_datamover_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
constant MTBF_STAGES : integer := 4;
-- ATTRIBUTE async_reg : STRING;
-- Signals
signal sig_cmd_stat_rst_user_n : std_logic := '0';
signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0';
signal sig_cmd_stat_rst_int_reg_n : std_logic := '0';
signal sig_mmap_rst_reg_n : std_logic := '0';
signal sig_stream_rst_reg_n : std_logic := '0';
signal sig_syncd_sec_rst : std_logic := '0';
-- soft shutdown support
signal sig_internal_reset : std_logic := '0';
signal sig_s_h_halt_reg : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
-- additional CDC synchronization signals
signal sig_sec_neg_edge_plus_delay : std_logic := '0';
signal sig_secondary_aresetn_reg : std_logic := '0';
signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0';
signal sig_prim2sec_rst_reg2_n : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true";
begin --(architecture implementation)
-- Assign outputs
cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n);
cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
mmap_rst <= not(sig_mmap_rst_reg_n) or
sig_syncd_sec_rst;
stream_rst <= not(sig_stream_rst_reg_n) or
sig_syncd_sec_rst;
-- Internal logic Implmentation
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Synchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_syncd_sec_rst <= '0';
sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from);
end generate GEN_SYNC_CMDSTAT_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Asynchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
-- ATTRIBUTE async_reg : STRING;
signal sig_sec_reset_in_reg_n : std_logic := '0';
signal sig_secondary_aresetn_reg_tmp : std_logic := '0';
-- Secondary reset pulse stretcher
signal sig_secondary_dly1 : std_logic := '0';
signal sig_secondary_dly2 : std_logic := '0';
signal sig_neg_edge_detect : std_logic := '0';
signal sig_sec2prim_reset : std_logic := '0';
signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0';
signal sig_sec2prim_reset_reg2 : std_logic := '0';
signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0';
signal sig_sec2prim_rst_syncro2 : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true";
begin
-- Generate the reset in the primary clock domain. Use the longer
-- of the pulse stretched reset or the actual reset.
sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or
sig_sec2prim_rst_syncro2;
-- Check for falling edge of secondary_aresetn input
sig_neg_edge_detect <= '1'
when (sig_sec_reset_in_reg_n = '1' and
secondary_aresetn = '0')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSE_STRETCH_FLOPS
--
-- Process Description:
-- This process implements a 3 clock wide pulse whenever the
-- secondary reset is asserted
--
-------------------------------------------------------------
IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
If (sig_secondary_dly2 = '1') Then
sig_secondary_dly1 <= '0' ;
sig_secondary_dly2 <= '0' ;
Elsif (sig_neg_edge_detect = '1') Then
sig_secondary_dly1 <= '1';
else
sig_secondary_dly2 <= sig_secondary_dly1 ;
End if;
end if;
end process IMP_PUSE_STRETCH_FLOPS;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_NEG_EDGE
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- negative edge detection,
--
-------------------------------------------------------------
SYNC_NEG_EDGE : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or
sig_secondary_dly1 or
sig_secondary_dly2;
end if;
end process SYNC_NEG_EDGE;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO
--
-- Process Description:
-- This process registers the secondary reset input to
-- the primary clock domain.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_sec_neg_edge_plus_delay,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_reset_reg2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ;
--
-- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig;
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SEC_RST
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- secondary reset input,
--
-------------------------------------------------------------
REG_SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_secondary_aresetn_reg <= secondary_aresetn;
end if;
end process REG_SEC_RST;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO_2
--
-- Process Description:
-- Second stage (destination) synchronizers for the secondary
-- reset CDC to the primary clock.
--
-------------------------------------------------------------
sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg);
SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_secondary_aresetn_reg_tmp,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_rst_syncro2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn);
-- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg);
-- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig;
--
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO_2;
-- Generate the Command and Status side reset
sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and
sig_prim2sec_rst_reg2_n;
-- CDC sig_cmd_stat_rst_user_reg_n_cdc_from;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RESET_ASYNC
--
-- Process Description:
-- This process registers the secondary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_RESET_ASYNC : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_reset_in_reg_n <= secondary_aresetn;
end if;
end process REG_RESET_ASYNC;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_PRIM2SEC_RST
--
-- Process Description:
-- Second (destination clock) stage synchronizers for CDC of
-- primary reset input,
--
-------------------------------------------------------------
SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => secondary_awclk,
scndry_resetn => '0',
scndry_out => sig_prim2sec_rst_reg2_n,
scndry_vect_out => open
);
-- SYNC_PRIM2SEC_RST : process (secondary_awclk)
-- begin
-- if (secondary_awclk'event and secondary_awclk = '1') then
--
-- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from;
-- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to;
--
-- end if;
-- end process SYNC_PRIM2SEC_RST;
--
end generate GEN_ASYNC_CMDSTAT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_PRIM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_PRIM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn;
end if;
end process REG_CMDSTAT_PRIM_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_INT_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status internal interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_INT_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_int_reg_n <= primary_aresetn;
end if;
end process REG_CMDSTAT_INT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_MMAP_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Memory Map interface reset.
--
-------------------------------------------------------------
REG_MMAP_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_rst_reg_n <= primary_aresetn;
end if;
end process REG_MMAP_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STREAM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Stream interface reset.
--
-------------------------------------------------------------
REG_STREAM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_stream_rst_reg_n <= primary_aresetn;
end if;
end process REG_STREAM_RESET;
-- Soft Shutdown logic ------------------------------------------------------
sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
flush_stop_request <= sig_s_h_halt_reg;
halt_cmplt <= sig_halt_cmplt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_HALT_REQ
--
-- Process Description:
-- Implements a sample and hold flop for the halt request
-- input. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
REG_HALT_REQ : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_s_h_halt_reg <= '0';
elsif (halt_req = '1') then
sig_s_h_halt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process REG_HALT_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT
--
-- Process Description:
-- Implements a the flop for the halt complete status
-- output. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_halt_cmplt <= '0';
elsif (data_cntlr_stopped = '1' and
addr_cntlr_stopped = '1' and
aux1_stopped = '1' and
aux2_stopped = '1') then
sig_halt_cmplt <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_reset.vhd
--
-- Description:
-- This file implements the DataMover Reset module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_datamover_reset is
generic (
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0
-- 0 = Use Synchronous Command/Statys User Interface
-- 1 = Use Asynchronous Command/Statys User Interface
);
port (
-- Primary Clock and Reset Inputs -----------------
--
primary_aclk : in std_logic; --
primary_aresetn : in std_logic; --
---------------------------------------------------
-- Async operation clock and reset from User ------
-- Used for Command/Status User interface --
-- synchronization when C_STSCMD_IS_ASYNC = 1 --
--
secondary_awclk : in std_logic; --
secondary_aresetn : in std_logic; --
---------------------------------------------------
-- Halt request input control -------------------------------
halt_req : in std_logic; --
-- Active high soft shutdown request (can be a pulse) --
--
-- Halt Complete status flag --
halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------------------
--
flush_stop_request : Out std_logic; --
-- Active high soft stop request to modules --
--
data_cntlr_stopped : in std_logic; --
-- Active high flag indicating the data controller is flushed and stopped --
--
addr_cntlr_stopped : in std_logic; --
-- Active high flag indicating the address controller is flushed and stopped --
--
aux1_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 1 module --
-- Tie high if unused --
--
aux2_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 2 module --
-- Tie high if unused --
------------------------------------------------------------------------------------
-- HW Reset outputs to reset groups -------------------------------------
--
cmd_stat_rst_user : Out std_logic; --
-- The reset to the Command/Status Module User interface side --
--
cmd_stat_rst_int : Out std_logic; --
-- The reset to the Command/Status Module internal interface side --
--
mmap_rst : Out std_logic; --
-- The reset to the Memory Map interface side --
--
stream_rst : Out std_logic --
-- The reset to the Stream interface side --
--------------------------------------------------------------------------
);
end entity axi_datamover_reset;
architecture implementation of axi_datamover_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
constant MTBF_STAGES : integer := 4;
-- ATTRIBUTE async_reg : STRING;
-- Signals
signal sig_cmd_stat_rst_user_n : std_logic := '0';
signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0';
signal sig_cmd_stat_rst_int_reg_n : std_logic := '0';
signal sig_mmap_rst_reg_n : std_logic := '0';
signal sig_stream_rst_reg_n : std_logic := '0';
signal sig_syncd_sec_rst : std_logic := '0';
-- soft shutdown support
signal sig_internal_reset : std_logic := '0';
signal sig_s_h_halt_reg : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
-- additional CDC synchronization signals
signal sig_sec_neg_edge_plus_delay : std_logic := '0';
signal sig_secondary_aresetn_reg : std_logic := '0';
signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0';
signal sig_prim2sec_rst_reg2_n : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true";
begin --(architecture implementation)
-- Assign outputs
cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n);
cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
mmap_rst <= not(sig_mmap_rst_reg_n) or
sig_syncd_sec_rst;
stream_rst <= not(sig_stream_rst_reg_n) or
sig_syncd_sec_rst;
-- Internal logic Implmentation
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Synchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_syncd_sec_rst <= '0';
sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from);
end generate GEN_SYNC_CMDSTAT_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Asynchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
-- ATTRIBUTE async_reg : STRING;
signal sig_sec_reset_in_reg_n : std_logic := '0';
signal sig_secondary_aresetn_reg_tmp : std_logic := '0';
-- Secondary reset pulse stretcher
signal sig_secondary_dly1 : std_logic := '0';
signal sig_secondary_dly2 : std_logic := '0';
signal sig_neg_edge_detect : std_logic := '0';
signal sig_sec2prim_reset : std_logic := '0';
signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0';
signal sig_sec2prim_reset_reg2 : std_logic := '0';
signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0';
signal sig_sec2prim_rst_syncro2 : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true";
begin
-- Generate the reset in the primary clock domain. Use the longer
-- of the pulse stretched reset or the actual reset.
sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or
sig_sec2prim_rst_syncro2;
-- Check for falling edge of secondary_aresetn input
sig_neg_edge_detect <= '1'
when (sig_sec_reset_in_reg_n = '1' and
secondary_aresetn = '0')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSE_STRETCH_FLOPS
--
-- Process Description:
-- This process implements a 3 clock wide pulse whenever the
-- secondary reset is asserted
--
-------------------------------------------------------------
IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
If (sig_secondary_dly2 = '1') Then
sig_secondary_dly1 <= '0' ;
sig_secondary_dly2 <= '0' ;
Elsif (sig_neg_edge_detect = '1') Then
sig_secondary_dly1 <= '1';
else
sig_secondary_dly2 <= sig_secondary_dly1 ;
End if;
end if;
end process IMP_PUSE_STRETCH_FLOPS;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_NEG_EDGE
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- negative edge detection,
--
-------------------------------------------------------------
SYNC_NEG_EDGE : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or
sig_secondary_dly1 or
sig_secondary_dly2;
end if;
end process SYNC_NEG_EDGE;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO
--
-- Process Description:
-- This process registers the secondary reset input to
-- the primary clock domain.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_sec_neg_edge_plus_delay,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_reset_reg2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ;
--
-- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig;
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SEC_RST
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- secondary reset input,
--
-------------------------------------------------------------
REG_SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_secondary_aresetn_reg <= secondary_aresetn;
end if;
end process REG_SEC_RST;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO_2
--
-- Process Description:
-- Second stage (destination) synchronizers for the secondary
-- reset CDC to the primary clock.
--
-------------------------------------------------------------
sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg);
SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_secondary_aresetn_reg_tmp,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_rst_syncro2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn);
-- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg);
-- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig;
--
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO_2;
-- Generate the Command and Status side reset
sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and
sig_prim2sec_rst_reg2_n;
-- CDC sig_cmd_stat_rst_user_reg_n_cdc_from;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RESET_ASYNC
--
-- Process Description:
-- This process registers the secondary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_RESET_ASYNC : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_reset_in_reg_n <= secondary_aresetn;
end if;
end process REG_RESET_ASYNC;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_PRIM2SEC_RST
--
-- Process Description:
-- Second (destination clock) stage synchronizers for CDC of
-- primary reset input,
--
-------------------------------------------------------------
SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => secondary_awclk,
scndry_resetn => '0',
scndry_out => sig_prim2sec_rst_reg2_n,
scndry_vect_out => open
);
-- SYNC_PRIM2SEC_RST : process (secondary_awclk)
-- begin
-- if (secondary_awclk'event and secondary_awclk = '1') then
--
-- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from;
-- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to;
--
-- end if;
-- end process SYNC_PRIM2SEC_RST;
--
end generate GEN_ASYNC_CMDSTAT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_PRIM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_PRIM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn;
end if;
end process REG_CMDSTAT_PRIM_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_INT_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status internal interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_INT_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_int_reg_n <= primary_aresetn;
end if;
end process REG_CMDSTAT_INT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_MMAP_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Memory Map interface reset.
--
-------------------------------------------------------------
REG_MMAP_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_rst_reg_n <= primary_aresetn;
end if;
end process REG_MMAP_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STREAM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Stream interface reset.
--
-------------------------------------------------------------
REG_STREAM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_stream_rst_reg_n <= primary_aresetn;
end if;
end process REG_STREAM_RESET;
-- Soft Shutdown logic ------------------------------------------------------
sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
flush_stop_request <= sig_s_h_halt_reg;
halt_cmplt <= sig_halt_cmplt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_HALT_REQ
--
-- Process Description:
-- Implements a sample and hold flop for the halt request
-- input. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
REG_HALT_REQ : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_s_h_halt_reg <= '0';
elsif (halt_req = '1') then
sig_s_h_halt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process REG_HALT_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT
--
-- Process Description:
-- Implements a the flop for the halt complete status
-- output. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_halt_cmplt <= '0';
elsif (data_cntlr_stopped = '1' and
addr_cntlr_stopped = '1' and
aux1_stopped = '1' and
aux2_stopped = '1') then
sig_halt_cmplt <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_reset.vhd
--
-- Description:
-- This file implements the DataMover Reset module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_datamover_reset is
generic (
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0
-- 0 = Use Synchronous Command/Statys User Interface
-- 1 = Use Asynchronous Command/Statys User Interface
);
port (
-- Primary Clock and Reset Inputs -----------------
--
primary_aclk : in std_logic; --
primary_aresetn : in std_logic; --
---------------------------------------------------
-- Async operation clock and reset from User ------
-- Used for Command/Status User interface --
-- synchronization when C_STSCMD_IS_ASYNC = 1 --
--
secondary_awclk : in std_logic; --
secondary_aresetn : in std_logic; --
---------------------------------------------------
-- Halt request input control -------------------------------
halt_req : in std_logic; --
-- Active high soft shutdown request (can be a pulse) --
--
-- Halt Complete status flag --
halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------------------
--
flush_stop_request : Out std_logic; --
-- Active high soft stop request to modules --
--
data_cntlr_stopped : in std_logic; --
-- Active high flag indicating the data controller is flushed and stopped --
--
addr_cntlr_stopped : in std_logic; --
-- Active high flag indicating the address controller is flushed and stopped --
--
aux1_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 1 module --
-- Tie high if unused --
--
aux2_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 2 module --
-- Tie high if unused --
------------------------------------------------------------------------------------
-- HW Reset outputs to reset groups -------------------------------------
--
cmd_stat_rst_user : Out std_logic; --
-- The reset to the Command/Status Module User interface side --
--
cmd_stat_rst_int : Out std_logic; --
-- The reset to the Command/Status Module internal interface side --
--
mmap_rst : Out std_logic; --
-- The reset to the Memory Map interface side --
--
stream_rst : Out std_logic --
-- The reset to the Stream interface side --
--------------------------------------------------------------------------
);
end entity axi_datamover_reset;
architecture implementation of axi_datamover_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
constant MTBF_STAGES : integer := 4;
-- ATTRIBUTE async_reg : STRING;
-- Signals
signal sig_cmd_stat_rst_user_n : std_logic := '0';
signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0';
signal sig_cmd_stat_rst_int_reg_n : std_logic := '0';
signal sig_mmap_rst_reg_n : std_logic := '0';
signal sig_stream_rst_reg_n : std_logic := '0';
signal sig_syncd_sec_rst : std_logic := '0';
-- soft shutdown support
signal sig_internal_reset : std_logic := '0';
signal sig_s_h_halt_reg : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
-- additional CDC synchronization signals
signal sig_sec_neg_edge_plus_delay : std_logic := '0';
signal sig_secondary_aresetn_reg : std_logic := '0';
signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0';
signal sig_prim2sec_rst_reg2_n : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true";
begin --(architecture implementation)
-- Assign outputs
cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n);
cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
mmap_rst <= not(sig_mmap_rst_reg_n) or
sig_syncd_sec_rst;
stream_rst <= not(sig_stream_rst_reg_n) or
sig_syncd_sec_rst;
-- Internal logic Implmentation
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Synchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_syncd_sec_rst <= '0';
sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from);
end generate GEN_SYNC_CMDSTAT_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Asynchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
-- ATTRIBUTE async_reg : STRING;
signal sig_sec_reset_in_reg_n : std_logic := '0';
signal sig_secondary_aresetn_reg_tmp : std_logic := '0';
-- Secondary reset pulse stretcher
signal sig_secondary_dly1 : std_logic := '0';
signal sig_secondary_dly2 : std_logic := '0';
signal sig_neg_edge_detect : std_logic := '0';
signal sig_sec2prim_reset : std_logic := '0';
signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0';
signal sig_sec2prim_reset_reg2 : std_logic := '0';
signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0';
signal sig_sec2prim_rst_syncro2 : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true";
begin
-- Generate the reset in the primary clock domain. Use the longer
-- of the pulse stretched reset or the actual reset.
sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or
sig_sec2prim_rst_syncro2;
-- Check for falling edge of secondary_aresetn input
sig_neg_edge_detect <= '1'
when (sig_sec_reset_in_reg_n = '1' and
secondary_aresetn = '0')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSE_STRETCH_FLOPS
--
-- Process Description:
-- This process implements a 3 clock wide pulse whenever the
-- secondary reset is asserted
--
-------------------------------------------------------------
IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
If (sig_secondary_dly2 = '1') Then
sig_secondary_dly1 <= '0' ;
sig_secondary_dly2 <= '0' ;
Elsif (sig_neg_edge_detect = '1') Then
sig_secondary_dly1 <= '1';
else
sig_secondary_dly2 <= sig_secondary_dly1 ;
End if;
end if;
end process IMP_PUSE_STRETCH_FLOPS;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_NEG_EDGE
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- negative edge detection,
--
-------------------------------------------------------------
SYNC_NEG_EDGE : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or
sig_secondary_dly1 or
sig_secondary_dly2;
end if;
end process SYNC_NEG_EDGE;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO
--
-- Process Description:
-- This process registers the secondary reset input to
-- the primary clock domain.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_sec_neg_edge_plus_delay,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_reset_reg2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ;
--
-- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig;
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SEC_RST
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- secondary reset input,
--
-------------------------------------------------------------
REG_SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_secondary_aresetn_reg <= secondary_aresetn;
end if;
end process REG_SEC_RST;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO_2
--
-- Process Description:
-- Second stage (destination) synchronizers for the secondary
-- reset CDC to the primary clock.
--
-------------------------------------------------------------
sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg);
SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_secondary_aresetn_reg_tmp,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_rst_syncro2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn);
-- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg);
-- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig;
--
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO_2;
-- Generate the Command and Status side reset
sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and
sig_prim2sec_rst_reg2_n;
-- CDC sig_cmd_stat_rst_user_reg_n_cdc_from;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RESET_ASYNC
--
-- Process Description:
-- This process registers the secondary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_RESET_ASYNC : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_reset_in_reg_n <= secondary_aresetn;
end if;
end process REG_RESET_ASYNC;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_PRIM2SEC_RST
--
-- Process Description:
-- Second (destination clock) stage synchronizers for CDC of
-- primary reset input,
--
-------------------------------------------------------------
SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => secondary_awclk,
scndry_resetn => '0',
scndry_out => sig_prim2sec_rst_reg2_n,
scndry_vect_out => open
);
-- SYNC_PRIM2SEC_RST : process (secondary_awclk)
-- begin
-- if (secondary_awclk'event and secondary_awclk = '1') then
--
-- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from;
-- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to;
--
-- end if;
-- end process SYNC_PRIM2SEC_RST;
--
end generate GEN_ASYNC_CMDSTAT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_PRIM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_PRIM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn;
end if;
end process REG_CMDSTAT_PRIM_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_INT_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status internal interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_INT_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_int_reg_n <= primary_aresetn;
end if;
end process REG_CMDSTAT_INT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_MMAP_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Memory Map interface reset.
--
-------------------------------------------------------------
REG_MMAP_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_rst_reg_n <= primary_aresetn;
end if;
end process REG_MMAP_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STREAM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Stream interface reset.
--
-------------------------------------------------------------
REG_STREAM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_stream_rst_reg_n <= primary_aresetn;
end if;
end process REG_STREAM_RESET;
-- Soft Shutdown logic ------------------------------------------------------
sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
flush_stop_request <= sig_s_h_halt_reg;
halt_cmplt <= sig_halt_cmplt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_HALT_REQ
--
-- Process Description:
-- Implements a sample and hold flop for the halt request
-- input. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
REG_HALT_REQ : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_s_h_halt_reg <= '0';
elsif (halt_req = '1') then
sig_s_h_halt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process REG_HALT_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT
--
-- Process Description:
-- Implements a the flop for the halt complete status
-- output. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_halt_cmplt <= '0';
elsif (data_cntlr_stopped = '1' and
addr_cntlr_stopped = '1' and
aux1_stopped = '1' and
aux2_stopped = '1') then
sig_halt_cmplt <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT;
end implementation;
|
-------------------------------------------------------------------------------
-- axi_datamover_reset.vhd
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_datamover_reset.vhd
--
-- Description:
-- This file implements the DataMover Reset module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library lib_cdc_v1_0;
-------------------------------------------------------------------------------
entity axi_datamover_reset is
generic (
C_STSCMD_IS_ASYNC : Integer range 0 to 1 := 0
-- 0 = Use Synchronous Command/Statys User Interface
-- 1 = Use Asynchronous Command/Statys User Interface
);
port (
-- Primary Clock and Reset Inputs -----------------
--
primary_aclk : in std_logic; --
primary_aresetn : in std_logic; --
---------------------------------------------------
-- Async operation clock and reset from User ------
-- Used for Command/Status User interface --
-- synchronization when C_STSCMD_IS_ASYNC = 1 --
--
secondary_awclk : in std_logic; --
secondary_aresetn : in std_logic; --
---------------------------------------------------
-- Halt request input control -------------------------------
halt_req : in std_logic; --
-- Active high soft shutdown request (can be a pulse) --
--
-- Halt Complete status flag --
halt_cmplt : Out std_logic; --
-- Active high soft shutdown complete status --
-------------------------------------------------------------
-- Soft Shutdown internal interface ------------------------------------------------
--
flush_stop_request : Out std_logic; --
-- Active high soft stop request to modules --
--
data_cntlr_stopped : in std_logic; --
-- Active high flag indicating the data controller is flushed and stopped --
--
addr_cntlr_stopped : in std_logic; --
-- Active high flag indicating the address controller is flushed and stopped --
--
aux1_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 1 module --
-- Tie high if unused --
--
aux2_stopped : in std_logic; --
-- Active high flag flush complete for auxillary 2 module --
-- Tie high if unused --
------------------------------------------------------------------------------------
-- HW Reset outputs to reset groups -------------------------------------
--
cmd_stat_rst_user : Out std_logic; --
-- The reset to the Command/Status Module User interface side --
--
cmd_stat_rst_int : Out std_logic; --
-- The reset to the Command/Status Module internal interface side --
--
mmap_rst : Out std_logic; --
-- The reset to the Memory Map interface side --
--
stream_rst : Out std_logic --
-- The reset to the Stream interface side --
--------------------------------------------------------------------------
);
end entity axi_datamover_reset;
architecture implementation of axi_datamover_reset is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
constant MTBF_STAGES : integer := 4;
-- ATTRIBUTE async_reg : STRING;
-- Signals
signal sig_cmd_stat_rst_user_n : std_logic := '0';
signal sig_cmd_stat_rst_user_reg_n_cdc_from : std_logic := '0';
signal sig_cmd_stat_rst_int_reg_n : std_logic := '0';
signal sig_mmap_rst_reg_n : std_logic := '0';
signal sig_stream_rst_reg_n : std_logic := '0';
signal sig_syncd_sec_rst : std_logic := '0';
-- soft shutdown support
signal sig_internal_reset : std_logic := '0';
signal sig_s_h_halt_reg : std_logic := '0';
signal sig_halt_cmplt : std_logic := '0';
-- additional CDC synchronization signals
signal sig_sec_neg_edge_plus_delay : std_logic := '0';
signal sig_secondary_aresetn_reg : std_logic := '0';
signal sig_prim2sec_rst_reg1_n_cdc_to : std_logic := '0';
signal sig_prim2sec_rst_reg2_n : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg1_n_cdc_to : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_prim2sec_rst_reg2_n : SIGNAL IS "true";
begin --(architecture implementation)
-- Assign outputs
cmd_stat_rst_user <= not(sig_cmd_stat_rst_user_n);
cmd_stat_rst_int <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
mmap_rst <= not(sig_mmap_rst_reg_n) or
sig_syncd_sec_rst;
stream_rst <= not(sig_stream_rst_reg_n) or
sig_syncd_sec_rst;
-- Internal logic Implmentation
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_SYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Synchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_SYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 0) generate
begin
sig_syncd_sec_rst <= '0';
sig_cmd_stat_rst_user_n <= not(sig_cmd_stat_rst_user_reg_n_cdc_from);
end generate GEN_SYNC_CMDSTAT_RESET;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_ASYNC_CMDSTAT_RESET
--
-- If Generate Description:
-- This IfGen assigns the reset for the
-- Asynchronous Command/Status User interface case
--
------------------------------------------------------------
GEN_ASYNC_CMDSTAT_RESET : if (C_STSCMD_IS_ASYNC = 1) generate
-- ATTRIBUTE async_reg : STRING;
signal sig_sec_reset_in_reg_n : std_logic := '0';
signal sig_secondary_aresetn_reg_tmp : std_logic := '0';
-- Secondary reset pulse stretcher
signal sig_secondary_dly1 : std_logic := '0';
signal sig_secondary_dly2 : std_logic := '0';
signal sig_neg_edge_detect : std_logic := '0';
signal sig_sec2prim_reset : std_logic := '0';
signal sig_sec2prim_reset_reg_cdc_tig : std_logic := '0';
signal sig_sec2prim_reset_reg2 : std_logic := '0';
signal sig_sec2prim_rst_syncro1_cdc_tig : std_logic := '0';
signal sig_sec2prim_rst_syncro2 : std_logic := '0';
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_reset_reg2 : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF sig_sec2prim_rst_syncro2 : SIGNAL IS "true";
begin
-- Generate the reset in the primary clock domain. Use the longer
-- of the pulse stretched reset or the actual reset.
sig_syncd_sec_rst <= sig_sec2prim_reset_reg2 or
sig_sec2prim_rst_syncro2;
-- Check for falling edge of secondary_aresetn input
sig_neg_edge_detect <= '1'
when (sig_sec_reset_in_reg_n = '1' and
secondary_aresetn = '0')
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSE_STRETCH_FLOPS
--
-- Process Description:
-- This process implements a 3 clock wide pulse whenever the
-- secondary reset is asserted
--
-------------------------------------------------------------
IMP_PUSE_STRETCH_FLOPS : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
If (sig_secondary_dly2 = '1') Then
sig_secondary_dly1 <= '0' ;
sig_secondary_dly2 <= '0' ;
Elsif (sig_neg_edge_detect = '1') Then
sig_secondary_dly1 <= '1';
else
sig_secondary_dly2 <= sig_secondary_dly1 ;
End if;
end if;
end process IMP_PUSE_STRETCH_FLOPS;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_NEG_EDGE
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- negative edge detection,
--
-------------------------------------------------------------
SYNC_NEG_EDGE : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_neg_edge_plus_delay <= sig_neg_edge_detect or
sig_secondary_dly1 or
sig_secondary_dly2;
end if;
end process SYNC_NEG_EDGE;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO
--
-- Process Description:
-- This process registers the secondary reset input to
-- the primary clock domain.
--
-------------------------------------------------------------
SEC2PRIM_RST_SYNCRO : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_sec_neg_edge_plus_delay,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_reset_reg2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- sig_sec2prim_reset_reg_cdc_tig <= sig_sec_neg_edge_plus_delay ;
--
-- sig_sec2prim_reset_reg2 <= sig_sec2prim_reset_reg_cdc_tig;
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_SEC_RST
--
-- Process Description:
-- First (source clock) stage synchronizer for CDC of
-- secondary reset input,
--
-------------------------------------------------------------
REG_SEC_RST : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_secondary_aresetn_reg <= secondary_aresetn;
end if;
end process REG_SEC_RST;
--
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SEC2PRIM_RST_SYNCRO_2
--
-- Process Description:
-- Second stage (destination) synchronizers for the secondary
-- reset CDC to the primary clock.
--
-------------------------------------------------------------
sig_secondary_aresetn_reg_tmp <= not(sig_secondary_aresetn_reg);
SEC2PRIM_RST_SYNCRO_2 : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_secondary_aresetn_reg_tmp,
prmry_vect_in => (others => '0'),
scndry_aclk => primary_aclk,
scndry_resetn => '0',
scndry_out => sig_sec2prim_rst_syncro2,
scndry_vect_out => open
);
-- SEC2PRIM_RST_SYNCRO_2 : process (primary_aclk)
-- begin
-- if (primary_aclk'event and primary_aclk = '1') then
--
--
-- -- CDC sig_sec2prim_rst_syncro1_cdc_tig <= not(secondary_aresetn);
-- sig_sec2prim_rst_syncro1_cdc_tig <= not(sig_secondary_aresetn_reg);
-- sig_sec2prim_rst_syncro2 <= sig_sec2prim_rst_syncro1_cdc_tig;
--
--
-- end if;
-- end process SEC2PRIM_RST_SYNCRO_2;
-- Generate the Command and Status side reset
sig_cmd_stat_rst_user_n <= sig_sec_reset_in_reg_n and
sig_prim2sec_rst_reg2_n;
-- CDC sig_cmd_stat_rst_user_reg_n_cdc_from;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_RESET_ASYNC
--
-- Process Description:
-- This process registers the secondary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_RESET_ASYNC : process (secondary_awclk)
begin
if (secondary_awclk'event and secondary_awclk = '1') then
sig_sec_reset_in_reg_n <= secondary_aresetn;
end if;
end process REG_RESET_ASYNC;
-- CDC add
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: SYNC_PRIM2SEC_RST
--
-- Process Description:
-- Second (destination clock) stage synchronizers for CDC of
-- primary reset input,
--
-------------------------------------------------------------
SYNC_PRIM2SEC_RST : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => MTBF_STAGES
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => sig_cmd_stat_rst_user_reg_n_cdc_from,
prmry_vect_in => (others => '0'),
scndry_aclk => secondary_awclk,
scndry_resetn => '0',
scndry_out => sig_prim2sec_rst_reg2_n,
scndry_vect_out => open
);
-- SYNC_PRIM2SEC_RST : process (secondary_awclk)
-- begin
-- if (secondary_awclk'event and secondary_awclk = '1') then
--
-- sig_prim2sec_rst_reg1_n_cdc_to <= sig_cmd_stat_rst_user_reg_n_cdc_from;
-- sig_prim2sec_rst_reg2_n <= sig_prim2sec_rst_reg1_n_cdc_to;
--
-- end if;
-- end process SYNC_PRIM2SEC_RST;
--
end generate GEN_ASYNC_CMDSTAT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_PRIM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status User interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_PRIM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_user_reg_n_cdc_from <= primary_aresetn;
end if;
end process REG_CMDSTAT_PRIM_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_CMDSTAT_INT_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Command/Status internal interface reset.
--
-------------------------------------------------------------
REG_CMDSTAT_INT_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_cmd_stat_rst_int_reg_n <= primary_aresetn;
end if;
end process REG_CMDSTAT_INT_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_MMAP_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Memory Map interface reset.
--
-------------------------------------------------------------
REG_MMAP_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_mmap_rst_reg_n <= primary_aresetn;
end if;
end process REG_MMAP_RESET;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_STREAM_RESET
--
-- Process Description:
-- This process registers the primary reset input to
-- generate the Stream interface reset.
--
-------------------------------------------------------------
REG_STREAM_RESET : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
sig_stream_rst_reg_n <= primary_aresetn;
end if;
end process REG_STREAM_RESET;
-- Soft Shutdown logic ------------------------------------------------------
sig_internal_reset <= not(sig_cmd_stat_rst_int_reg_n) or
sig_syncd_sec_rst;
flush_stop_request <= sig_s_h_halt_reg;
halt_cmplt <= sig_halt_cmplt;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_HALT_REQ
--
-- Process Description:
-- Implements a sample and hold flop for the halt request
-- input. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
REG_HALT_REQ : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_s_h_halt_reg <= '0';
elsif (halt_req = '1') then
sig_s_h_halt_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process REG_HALT_REQ;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_CMPLT
--
-- Process Description:
-- Implements a the flop for the halt complete status
-- output. Can only be cleared on a HW reset.
--
-------------------------------------------------------------
IMP_HALT_CMPLT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_internal_reset = '1') then
sig_halt_cmplt <= '0';
elsif (data_cntlr_stopped = '1' and
addr_cntlr_stopped = '1' and
aux1_stopped = '1' and
aux2_stopped = '1') then
sig_halt_cmplt <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_HALT_CMPLT;
end implementation;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
end mwe;
architecture lulz of mwe is
constant cnt_len : integer := 2;
constant cnt_stages : integer := 2;
type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
signal ctl_cnt : ctl_sig(0 to cnt_stages-1);
signal ctl_cnt_tmp : ctl_sig(0 to cnt_stages-1);
signal clk : std_logic := '0';
begin
clk <= not clk after 50 ns;
controller : entity work.counter
generic map(
width => cnt_len
)
port map(
clk => clk,
q => ctl_cnt(0)
);
-- workaround: use concurrent assignment of temporary signal
bla : for k in 1 to cnt_stages-1 generate
ctl_cnt(k) <= ctl_cnt_tmp(k);
end generate bla;
ctl_cnt_delay : process
begin
wait until rising_edge(clk);
for i in 0 to cnt_stages-2 loop
-- then this works...
ctl_cnt_tmp(i+1) <= ctl_cnt(i);
end loop;
end process;
end lulz;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
end mwe;
architecture lulz of mwe is
constant cnt_len : integer := 2;
constant cnt_stages : integer := 2;
type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
signal ctl_cnt : ctl_sig(0 to cnt_stages-1);
signal ctl_cnt_tmp : ctl_sig(0 to cnt_stages-1);
signal clk : std_logic := '0';
begin
clk <= not clk after 50 ns;
controller : entity work.counter
generic map(
width => cnt_len
)
port map(
clk => clk,
q => ctl_cnt(0)
);
-- workaround: use concurrent assignment of temporary signal
bla : for k in 1 to cnt_stages-1 generate
ctl_cnt(k) <= ctl_cnt_tmp(k);
end generate bla;
ctl_cnt_delay : process
begin
wait until rising_edge(clk);
for i in 0 to cnt_stages-2 loop
-- then this works...
ctl_cnt_tmp(i+1) <= ctl_cnt(i);
end loop;
end process;
end lulz;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mwe is
end mwe;
architecture lulz of mwe is
constant cnt_len : integer := 2;
constant cnt_stages : integer := 2;
type ctl_sig is array (natural range <>) of std_logic_vector(cnt_len-1 downto 0);
signal ctl_cnt : ctl_sig(0 to cnt_stages-1);
signal ctl_cnt_tmp : ctl_sig(0 to cnt_stages-1);
signal clk : std_logic := '0';
begin
clk <= not clk after 50 ns;
controller : entity work.counter
generic map(
width => cnt_len
)
port map(
clk => clk,
q => ctl_cnt(0)
);
-- workaround: use concurrent assignment of temporary signal
bla : for k in 1 to cnt_stages-1 generate
ctl_cnt(k) <= ctl_cnt_tmp(k);
end generate bla;
ctl_cnt_delay : process
begin
wait until rising_edge(clk);
for i in 0 to cnt_stages-2 loop
-- then this works...
ctl_cnt_tmp(i+1) <= ctl_cnt(i);
end loop;
end process;
end lulz;
|
--*****************************************************************************
-- (c) Copyright 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
--*****************************************************************************
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor : Xilinx
-- \ \ \/ Version : 3.9
-- \ \ Application : MIG
-- / / Filename : sim_tb_top.vhd
-- /___/ /\ Date Last Modified : $Date: 2011/06/02 07:16:58 $
-- \ \ / \ Date Created : Jul 03 2009
-- \___\/\___\
--
-- Device : Spartan-6
-- Design Name : DDR/DDR2/DDR3/LPDDR
-- Purpose : This is the simulation testbench which is used to verify the
-- design. The basic clocks and resets to the interface are
-- generated here. This also connects the memory interface to the
-- memory model.
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity sim_tb_top is
end entity sim_tb_top;
architecture arch of sim_tb_top is
-- ========================================================================== --
-- Parameters --
-- ========================================================================== --
constant DEBUG_EN : integer :=0;
constant C1_HW_TESTING : string := "FALSE";
constant C3_HW_TESTING : string := "FALSE";
function c1_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C1_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
function c3_sim_hw (val1:std_logic_vector( 31 downto 0); val2: std_logic_vector( 31 downto 0) ) return std_logic_vector is
begin
if (C3_HW_TESTING = "FALSE") then
return val1;
else
return val2;
end if;
end function;
constant C1_MEMCLK_PERIOD : integer := 2500;
constant C1_RST_ACT_LOW : integer := 0;
constant C1_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
constant C1_CLK_PERIOD_NS : real := 2500.0 / 1000.0;
constant C1_TCYC_SYS : real := C1_CLK_PERIOD_NS/2.0;
constant C1_TCYC_SYS_DIV2 : time := C1_TCYC_SYS * 1 ns;
constant C1_NUM_DQ_PINS : integer := 16;
constant C1_MEM_ADDR_WIDTH : integer := 14;
constant C1_MEM_BANKADDR_WIDTH : integer := 3;
constant C1_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C1_P0_MASK_SIZE : integer := 4;
constant C1_P0_DATA_PORT_SIZE : integer := 32;
constant C1_P1_MASK_SIZE : integer := 4;
constant C1_P1_DATA_PORT_SIZE : integer := 32;
constant C1_MEM_BURST_LEN : integer := 8;
constant C1_MEM_NUM_COL_BITS : integer := 10;
constant C1_SIMULATION : string := "TRUE";
constant C1_CALIB_SOFT_IP : string := "TRUE";
constant C3_MEMCLK_PERIOD : integer := 2500;
constant C3_RST_ACT_LOW : integer := 0;
constant C3_INPUT_CLK_TYPE : string := "DIFFERENTIAL";
constant C3_CLK_PERIOD_NS : real := 2500.0 / 1000.0;
constant C3_TCYC_SYS : real := C3_CLK_PERIOD_NS/2.0;
constant C3_TCYC_SYS_DIV2 : time := C3_TCYC_SYS * 1 ns;
constant C3_NUM_DQ_PINS : integer := 16;
constant C3_MEM_ADDR_WIDTH : integer := 14;
constant C3_MEM_BANKADDR_WIDTH : integer := 3;
constant C3_MEM_ADDR_ORDER : string := "ROW_BANK_COLUMN";
constant C3_P0_MASK_SIZE : integer := 4;
constant C3_P0_DATA_PORT_SIZE : integer := 32;
constant C3_P1_MASK_SIZE : integer := 4;
constant C3_P1_DATA_PORT_SIZE : integer := 32;
constant C3_MEM_BURST_LEN : integer := 8;
constant C3_MEM_NUM_COL_BITS : integer := 10;
constant C3_SIMULATION : string := "TRUE";
constant C3_CALIB_SOFT_IP : string := "TRUE";
constant C1_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C1_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C1_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c1_sim_hw (x"000002ff", x"02ffffff");
constant C1_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"fffffc00", x"fc000000");
constant C1_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c1_sim_hw (x"00000100", x"01000000");
constant C3_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
constant C3_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
constant C3_p0_END_ADDRESS : std_logic_vector(31 downto 0) := c3_sim_hw (x"000002ff", x"02ffffff");
constant C3_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"fffffc00", x"fc000000");
constant C3_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := c3_sim_hw (x"00000100", x"01000000");
-- ========================================================================== --
-- Component Declarations
-- ========================================================================== --
component ddr3_controller is
generic
(
C1_P0_MASK_SIZE : integer;
C1_P0_DATA_PORT_SIZE : integer;
C1_P1_MASK_SIZE : integer;
C1_P1_DATA_PORT_SIZE : integer;
C1_MEMCLK_PERIOD : integer;
C1_RST_ACT_LOW : integer;
C1_INPUT_CLK_TYPE : string;
DEBUG_EN : integer;
C1_CALIB_SOFT_IP : string;
C1_SIMULATION : string;
C1_MEM_ADDR_ORDER : string;
C1_NUM_DQ_PINS : integer;
C1_MEM_ADDR_WIDTH : integer;
C1_MEM_BANKADDR_WIDTH : integer;
C3_P0_MASK_SIZE : integer;
C3_P0_DATA_PORT_SIZE : integer;
C3_P1_MASK_SIZE : integer;
C3_P1_DATA_PORT_SIZE : integer;
C3_MEMCLK_PERIOD : integer;
C3_RST_ACT_LOW : integer;
C3_INPUT_CLK_TYPE : string;
C3_CALIB_SOFT_IP : string;
C3_SIMULATION : string;
C3_MEM_ADDR_ORDER : string;
C3_NUM_DQ_PINS : integer;
C3_MEM_ADDR_WIDTH : integer;
C3_MEM_BANKADDR_WIDTH : integer
);
port
(
mcb1_dram_dq : inout std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
mcb1_dram_a : out std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
mcb1_dram_ba : out std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
mcb1_dram_ras_n : out std_logic;
mcb1_dram_cas_n : out std_logic;
mcb1_dram_we_n : out std_logic;
mcb1_dram_odt : out std_logic;
mcb1_dram_cke : out std_logic;
mcb1_dram_dm : out std_logic;
mcb1_rzq : inout std_logic;
mcb1_zio : inout std_logic;
c1_sys_clk_p : in std_logic;
c1_sys_clk_n : in std_logic;
c1_sys_rst_i : in std_logic;
c1_calib_done : out std_logic;
c1_clk0 : out std_logic;
c1_rst0 : out std_logic;
mcb1_dram_dqs : inout std_logic;
mcb1_dram_dqs_n : inout std_logic;
mcb1_dram_ck : out std_logic;
mcb1_dram_udqs : inout std_logic;
mcb1_dram_udqs_n : inout std_logic;
mcb1_dram_udm : out std_logic;
mcb1_dram_ck_n : out std_logic;
mcb1_dram_reset_n : out std_logic; mcb3_dram_dq : inout std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
mcb3_dram_a : out std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
mcb3_dram_ba : out std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
mcb3_dram_ras_n : out std_logic;
mcb3_dram_cas_n : out std_logic;
mcb3_dram_we_n : out std_logic;
mcb3_dram_odt : out std_logic;
mcb3_dram_cke : out std_logic;
mcb3_dram_dm : out std_logic;
mcb3_rzq : inout std_logic;
mcb3_zio : inout std_logic;
c3_sys_clk_p : in std_logic;
c3_sys_clk_n : in std_logic;
c3_sys_rst_i : in std_logic;
c3_calib_done : out std_logic;
c3_clk0 : out std_logic;
c3_rst0 : out std_logic;
mcb3_dram_dqs : inout std_logic;
mcb3_dram_dqs_n : inout std_logic;
mcb3_dram_ck : out std_logic;
mcb3_dram_udqs : inout std_logic;
mcb3_dram_udqs_n : inout std_logic;
mcb3_dram_udm : out std_logic;
mcb3_dram_ck_n : out std_logic;
mcb3_dram_reset_n : out std_logic; c1_p0_cmd_clk : in std_logic;
c1_p0_cmd_en : in std_logic;
c1_p0_cmd_instr : in std_logic_vector(2 downto 0);
c1_p0_cmd_bl : in std_logic_vector(5 downto 0);
c1_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c1_p0_cmd_empty : out std_logic;
c1_p0_cmd_full : out std_logic;
c1_p0_wr_clk : in std_logic;
c1_p0_wr_en : in std_logic;
c1_p0_wr_mask : in std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
c1_p0_wr_data : in std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_wr_full : out std_logic;
c1_p0_wr_empty : out std_logic;
c1_p0_wr_count : out std_logic_vector(6 downto 0);
c1_p0_wr_underrun : out std_logic;
c1_p0_wr_error : out std_logic;
c1_p0_rd_clk : in std_logic;
c1_p0_rd_en : in std_logic;
c1_p0_rd_data : out std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
c1_p0_rd_full : out std_logic;
c1_p0_rd_empty : out std_logic;
c1_p0_rd_count : out std_logic_vector(6 downto 0);
c1_p0_rd_overflow : out std_logic;
c1_p0_rd_error : out std_logic;
c3_p0_cmd_clk : in std_logic;
c3_p0_cmd_en : in std_logic;
c3_p0_cmd_instr : in std_logic_vector(2 downto 0);
c3_p0_cmd_bl : in std_logic_vector(5 downto 0);
c3_p0_cmd_byte_addr : in std_logic_vector(29 downto 0);
c3_p0_cmd_empty : out std_logic;
c3_p0_cmd_full : out std_logic;
c3_p0_wr_clk : in std_logic;
c3_p0_wr_en : in std_logic;
c3_p0_wr_mask : in std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
c3_p0_wr_data : in std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_wr_full : out std_logic;
c3_p0_wr_empty : out std_logic;
c3_p0_wr_count : out std_logic_vector(6 downto 0);
c3_p0_wr_underrun : out std_logic;
c3_p0_wr_error : out std_logic;
c3_p0_rd_clk : in std_logic;
c3_p0_rd_en : in std_logic;
c3_p0_rd_data : out std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
c3_p0_rd_full : out std_logic;
c3_p0_rd_empty : out std_logic;
c3_p0_rd_count : out std_logic_vector(6 downto 0);
c3_p0_rd_overflow : out std_logic;
c3_p0_rd_error : out std_logic
);
end component;
component ddr3_model_c1 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C1_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C1_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C1_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C1_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component ddr3_model_c3 is
port (
ck : in std_logic;
ck_n : in std_logic;
cke : in std_logic;
cs_n : in std_logic;
ras_n : in std_logic;
cas_n : in std_logic;
we_n : in std_logic;
dm_tdqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
ba : in std_logic_vector((C3_MEM_BANKADDR_WIDTH - 1) downto 0);
addr : in std_logic_vector((C3_MEM_ADDR_WIDTH - 1) downto 0);
dq : inout std_logic_vector((C3_NUM_DQ_PINS - 1) downto 0);
dqs : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
dqs_n : inout std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
tdqs_n : out std_logic_vector((C3_NUM_DQ_PINS/16) downto 0);
odt : in std_logic;
rst_n : in std_logic
);
end component;
component memc1_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
component memc3_tb_top is
generic
(
C_P0_MASK_SIZE : integer := 4;
C_P0_DATA_PORT_SIZE : integer := 32;
C_P1_MASK_SIZE : integer := 4;
C_P1_DATA_PORT_SIZE : integer := 32;
C_MEM_BURST_LEN : integer := 8;
C_MEM_NUM_COL_BITS : integer := 11;
C_NUM_DQ_PINS : integer := 8;
C_p0_BEGIN_ADDRESS : std_logic_vector(31 downto 0) := X"00000100";
C_p0_DATA_MODE : std_logic_vector(3 downto 0) := "0010";
C_p0_END_ADDRESS : std_logic_vector(31 downto 0) := X"000002ff";
C_p0_PRBS_EADDR_MASK_POS : std_logic_vector(31 downto 0) := X"fffffc00";
C_p0_PRBS_SADDR_MASK_POS : std_logic_vector(31 downto 0) := X"00000100"
);
port
(
clk0 : in std_logic;
rst0 : in std_logic;
calib_done : in std_logic;
p0_mcb_cmd_en_o : out std_logic;
p0_mcb_cmd_instr_o : out std_logic_vector(2 downto 0);
p0_mcb_cmd_bl_o : out std_logic_vector(5 downto 0);
p0_mcb_cmd_addr_o : out std_logic_vector(29 downto 0);
p0_mcb_cmd_full_i : in std_logic;
p0_mcb_wr_en_o : out std_logic;
p0_mcb_wr_mask_o : out std_logic_vector(C_P0_MASK_SIZE - 1 downto 0);
p0_mcb_wr_data_o : out std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_wr_full_i : in std_logic;
p0_mcb_wr_fifo_counts : in std_logic_vector(6 downto 0);
p0_mcb_rd_en_o : out std_logic;
p0_mcb_rd_data_i : in std_logic_vector(C_P0_DATA_PORT_SIZE - 1 downto 0);
p0_mcb_rd_empty_i : in std_logic;
p0_mcb_rd_fifo_counts : in std_logic_vector(6 downto 0);
vio_modify_enable : in std_logic;
vio_data_mode_value : in std_logic_vector(2 downto 0);
vio_addr_mode_value : in std_logic_vector(2 downto 0);
cmp_error : out std_logic;
error : out std_logic;
error_status : out std_logic_vector(127 downto 0)
);
end component;
-- ========================================================================== --
-- Signal Declarations --
-- ========================================================================== --
-- Clocks
-- Clocks
signal c1_sys_clk : std_logic := '0';
signal c1_sys_clk_p : std_logic;
signal c1_sys_clk_n : std_logic;
-- System Reset
signal c1_sys_rst : std_logic := '0';
signal c1_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c1_error : std_logic;
signal c1_calib_done : std_logic;
signal c1_error_status : std_logic_vector(127 downto 0);
signal mcb1_dram_a : std_logic_vector(C1_MEM_ADDR_WIDTH-1 downto 0);
signal mcb1_dram_ba : std_logic_vector(C1_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb1_dram_ck : std_logic;
signal mcb1_dram_ck_n : std_logic;
signal mcb1_dram_dq : std_logic_vector(C1_NUM_DQ_PINS-1 downto 0);
signal mcb1_dram_dqs : std_logic;
signal mcb1_dram_dqs_n : std_logic;
signal mcb1_dram_dm : std_logic;
signal mcb1_dram_ras_n : std_logic;
signal mcb1_dram_cas_n : std_logic;
signal mcb1_dram_we_n : std_logic;
signal mcb1_dram_cke : std_logic;
signal mcb1_dram_odt : std_logic;
signal mcb1_dram_reset_n : std_logic;
signal mcb1_dram_udqs : std_logic;
signal mcb1_dram_udqs_n : std_logic;
signal mcb1_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb1_dram_udm :std_logic; -- for X16 parts
signal mcb1_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c1_clk0 : std_logic;
signal c1_rst0 : std_logic;
signal c1_cmp_error : std_logic;
signal c1_vio_modify_enable : std_logic;
signal c1_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c1_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb1_command : std_logic_vector(2 downto 0);
signal mcb1_enable1 : std_logic;
signal mcb1_enable2 : std_logic;
signal c1_p0_cmd_en : std_logic;
signal c1_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c1_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c1_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c1_p0_cmd_empty : std_logic;
signal c1_p0_cmd_full : std_logic;
signal c1_p0_wr_en : std_logic;
signal c1_p0_wr_mask : std_logic_vector(C1_P0_MASK_SIZE - 1 downto 0);
signal c1_p0_wr_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_wr_full : std_logic;
signal c1_p0_wr_empty : std_logic;
signal c1_p0_wr_count : std_logic_vector(6 downto 0);
signal c1_p0_wr_underrun : std_logic;
signal c1_p0_wr_error : std_logic;
signal c1_p0_rd_en : std_logic;
signal c1_p0_rd_data : std_logic_vector(C1_P0_DATA_PORT_SIZE - 1 downto 0);
signal c1_p0_rd_full : std_logic;
signal c1_p0_rd_empty : std_logic;
signal c1_p0_rd_count : std_logic_vector(6 downto 0);
signal c1_p0_rd_overflow : std_logic;
signal c1_p0_rd_error : std_logic;
signal c1_selfrefresh_enter : std_logic;
signal c1_selfrefresh_mode : std_logic;
-- Clocks
-- Clocks
signal c3_sys_clk : std_logic := '0';
signal c3_sys_clk_p : std_logic;
signal c3_sys_clk_n : std_logic;
-- System Reset
signal c3_sys_rst : std_logic := '0';
signal c3_sys_rst_i : std_logic;
-- Design-Top Port Map
signal c3_error : std_logic;
signal c3_calib_done : std_logic;
signal c3_error_status : std_logic_vector(127 downto 0);
signal mcb3_dram_a : std_logic_vector(C3_MEM_ADDR_WIDTH-1 downto 0);
signal mcb3_dram_ba : std_logic_vector(C3_MEM_BANKADDR_WIDTH-1 downto 0);
signal mcb3_dram_ck : std_logic;
signal mcb3_dram_ck_n : std_logic;
signal mcb3_dram_dq : std_logic_vector(C3_NUM_DQ_PINS-1 downto 0);
signal mcb3_dram_dqs : std_logic;
signal mcb3_dram_dqs_n : std_logic;
signal mcb3_dram_dm : std_logic;
signal mcb3_dram_ras_n : std_logic;
signal mcb3_dram_cas_n : std_logic;
signal mcb3_dram_we_n : std_logic;
signal mcb3_dram_cke : std_logic;
signal mcb3_dram_odt : std_logic;
signal mcb3_dram_reset_n : std_logic;
signal mcb3_dram_udqs : std_logic;
signal mcb3_dram_udqs_n : std_logic;
signal mcb3_dram_dqs_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_dqs_n_vector : std_logic_vector(1 downto 0);
signal mcb3_dram_udm :std_logic; -- for X16 parts
signal mcb3_dram_dm_vector : std_logic_vector(1 downto 0);
-- User design Sim
signal c3_clk0 : std_logic;
signal c3_rst0 : std_logic;
signal c3_cmp_error : std_logic;
signal c3_vio_modify_enable : std_logic;
signal c3_vio_data_mode_value : std_logic_vector(2 downto 0);
signal c3_vio_addr_mode_value : std_logic_vector(2 downto 0);
signal mcb3_command : std_logic_vector(2 downto 0);
signal mcb3_enable1 : std_logic;
signal mcb3_enable2 : std_logic;
signal c3_p0_cmd_en : std_logic;
signal c3_p0_cmd_instr : std_logic_vector(2 downto 0);
signal c3_p0_cmd_bl : std_logic_vector(5 downto 0);
signal c3_p0_cmd_byte_addr : std_logic_vector(29 downto 0);
signal c3_p0_cmd_empty : std_logic;
signal c3_p0_cmd_full : std_logic;
signal c3_p0_wr_en : std_logic;
signal c3_p0_wr_mask : std_logic_vector(C3_P0_MASK_SIZE - 1 downto 0);
signal c3_p0_wr_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_wr_full : std_logic;
signal c3_p0_wr_empty : std_logic;
signal c3_p0_wr_count : std_logic_vector(6 downto 0);
signal c3_p0_wr_underrun : std_logic;
signal c3_p0_wr_error : std_logic;
signal c3_p0_rd_en : std_logic;
signal c3_p0_rd_data : std_logic_vector(C3_P0_DATA_PORT_SIZE - 1 downto 0);
signal c3_p0_rd_full : std_logic;
signal c3_p0_rd_empty : std_logic;
signal c3_p0_rd_count : std_logic_vector(6 downto 0);
signal c3_p0_rd_overflow : std_logic;
signal c3_p0_rd_error : std_logic;
signal c3_selfrefresh_enter : std_logic;
signal c3_selfrefresh_mode : std_logic;
signal rzq1 : std_logic;
signal rzq3 : std_logic;
signal zio1 : std_logic;
signal zio3 : std_logic;
signal calib_done : std_logic;
signal error : std_logic;
function vector (asi:std_logic) return std_logic_vector is
variable v : std_logic_vector(0 downto 0) ;
begin
v(0) := asi;
return(v);
end function vector;
begin
-- ========================================================================== --
-- Clocks Generation --
-- ========================================================================== --
process
begin
c1_sys_clk <= not c1_sys_clk;
wait for (C1_TCYC_SYS_DIV2);
end process;
c1_sys_clk_p <= c1_sys_clk;
c1_sys_clk_n <= not c1_sys_clk;
process
begin
c3_sys_clk <= not c3_sys_clk;
wait for (C3_TCYC_SYS_DIV2);
end process;
c3_sys_clk_p <= c3_sys_clk;
c3_sys_clk_n <= not c3_sys_clk;
-- ========================================================================== --
-- Reset Generation --
-- ========================================================================== --
process
begin
c1_sys_rst <= '0';
wait for 200 ns;
c1_sys_rst <= '1';
wait;
end process;
c1_sys_rst_i <= c1_sys_rst when (C1_RST_ACT_LOW = 1) else (not c1_sys_rst);
process
begin
c3_sys_rst <= '0';
wait for 200 ns;
c3_sys_rst <= '1';
wait;
end process;
c3_sys_rst_i <= c3_sys_rst when (C3_RST_ACT_LOW = 1) else (not c3_sys_rst);
error <= c1_error or c3_error;
calib_done <= c1_calib_done and c3_calib_done;
-- The PULLDOWN component is connected to the ZIO signal primarily to avoid the
-- unknown state in simulation. In real hardware, ZIO should be a no connect(NC) pin.
zio_pulldown1 : PULLDOWN port map(O => zio1);
zio_pulldown3 : PULLDOWN port map(O => zio3);
rzq_pulldown1 : PULLDOWN port map(O => rzq1);
rzq_pulldown3 : PULLDOWN port map(O => rzq3);
-- ========================================================================== --
-- DESIGN TOP INSTANTIATION --
-- ========================================================================== --
design_top : ddr3_controller generic map
(
C1_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C1_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C1_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C1_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C1_MEMCLK_PERIOD => C1_MEMCLK_PERIOD,
C1_RST_ACT_LOW => C1_RST_ACT_LOW,
C1_INPUT_CLK_TYPE => C1_INPUT_CLK_TYPE,
DEBUG_EN => DEBUG_EN,
C1_MEM_ADDR_ORDER => C1_MEM_ADDR_ORDER,
C1_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C1_MEM_ADDR_WIDTH => C1_MEM_ADDR_WIDTH,
C1_MEM_BANKADDR_WIDTH => C1_MEM_BANKADDR_WIDTH,
C1_SIMULATION => C1_SIMULATION,
C1_CALIB_SOFT_IP => C1_CALIB_SOFT_IP,
C3_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C3_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C3_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C3_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C3_MEMCLK_PERIOD => C3_MEMCLK_PERIOD,
C3_RST_ACT_LOW => C3_RST_ACT_LOW,
C3_INPUT_CLK_TYPE => C3_INPUT_CLK_TYPE,
C3_MEM_ADDR_ORDER => C3_MEM_ADDR_ORDER,
C3_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C3_MEM_ADDR_WIDTH => C3_MEM_ADDR_WIDTH,
C3_MEM_BANKADDR_WIDTH => C3_MEM_BANKADDR_WIDTH,
C3_SIMULATION => C3_SIMULATION,
C3_CALIB_SOFT_IP => C3_CALIB_SOFT_IP
)
port map (
c1_sys_clk_p => c1_sys_clk_p,
c1_sys_clk_n => c1_sys_clk_n,
c1_sys_rst_i => c1_sys_rst_i,
mcb1_dram_dq => mcb1_dram_dq,
mcb1_dram_a => mcb1_dram_a,
mcb1_dram_ba => mcb1_dram_ba,
mcb1_dram_ras_n => mcb1_dram_ras_n,
mcb1_dram_cas_n => mcb1_dram_cas_n,
mcb1_dram_we_n => mcb1_dram_we_n,
mcb1_dram_odt => mcb1_dram_odt,
mcb1_dram_cke => mcb1_dram_cke,
mcb1_dram_ck => mcb1_dram_ck,
mcb1_dram_ck_n => mcb1_dram_ck_n,
mcb1_dram_dqs => mcb1_dram_dqs,
mcb1_dram_dqs_n => mcb1_dram_dqs_n,
mcb1_dram_reset_n => mcb1_dram_reset_n,
mcb1_dram_udqs => mcb1_dram_udqs, -- for X16 parts
mcb1_dram_udqs_n => mcb1_dram_udqs_n, -- for X16 parts
mcb1_dram_udm => mcb1_dram_udm, -- for X16 parts
mcb1_dram_dm => mcb1_dram_dm,
c1_clk0 => c1_clk0,
c1_rst0 => c1_rst0,
c1_calib_done => c1_calib_done,
mcb1_rzq => rzq1,
mcb1_zio => zio1,
c1_p0_cmd_clk => (c1_clk0),
c1_p0_cmd_en => c1_p0_cmd_en,
c1_p0_cmd_instr => c1_p0_cmd_instr,
c1_p0_cmd_bl => c1_p0_cmd_bl,
c1_p0_cmd_byte_addr => c1_p0_cmd_byte_addr,
c1_p0_cmd_empty => c1_p0_cmd_empty,
c1_p0_cmd_full => c1_p0_cmd_full,
c1_p0_wr_clk => (c1_clk0),
c1_p0_wr_en => c1_p0_wr_en,
c1_p0_wr_mask => c1_p0_wr_mask,
c1_p0_wr_data => c1_p0_wr_data,
c1_p0_wr_full => c1_p0_wr_full,
c1_p0_wr_empty => c1_p0_wr_empty,
c1_p0_wr_count => c1_p0_wr_count,
c1_p0_wr_underrun => c1_p0_wr_underrun,
c1_p0_wr_error => c1_p0_wr_error,
c1_p0_rd_clk => (c1_clk0),
c1_p0_rd_en => c1_p0_rd_en,
c1_p0_rd_data => c1_p0_rd_data,
c1_p0_rd_full => c1_p0_rd_full,
c1_p0_rd_empty => c1_p0_rd_empty,
c1_p0_rd_count => c1_p0_rd_count,
c1_p0_rd_overflow => c1_p0_rd_overflow,
c1_p0_rd_error => c1_p0_rd_error,
c3_sys_clk_p => c3_sys_clk_p,
c3_sys_clk_n => c3_sys_clk_n,
c3_sys_rst_i => c3_sys_rst_i,
mcb3_dram_dq => mcb3_dram_dq,
mcb3_dram_a => mcb3_dram_a,
mcb3_dram_ba => mcb3_dram_ba,
mcb3_dram_ras_n => mcb3_dram_ras_n,
mcb3_dram_cas_n => mcb3_dram_cas_n,
mcb3_dram_we_n => mcb3_dram_we_n,
mcb3_dram_odt => mcb3_dram_odt,
mcb3_dram_cke => mcb3_dram_cke,
mcb3_dram_ck => mcb3_dram_ck,
mcb3_dram_ck_n => mcb3_dram_ck_n,
mcb3_dram_dqs => mcb3_dram_dqs,
mcb3_dram_dqs_n => mcb3_dram_dqs_n,
mcb3_dram_reset_n => mcb3_dram_reset_n,
mcb3_dram_udqs => mcb3_dram_udqs, -- for X16 parts
mcb3_dram_udqs_n => mcb3_dram_udqs_n, -- for X16 parts
mcb3_dram_udm => mcb3_dram_udm, -- for X16 parts
mcb3_dram_dm => mcb3_dram_dm,
c3_clk0 => c3_clk0,
c3_rst0 => c3_rst0,
c3_calib_done => c3_calib_done,
mcb3_rzq => rzq3,
mcb3_zio => zio3,
c3_p0_cmd_clk => (c3_clk0),
c3_p0_cmd_en => c3_p0_cmd_en,
c3_p0_cmd_instr => c3_p0_cmd_instr,
c3_p0_cmd_bl => c3_p0_cmd_bl,
c3_p0_cmd_byte_addr => c3_p0_cmd_byte_addr,
c3_p0_cmd_empty => c3_p0_cmd_empty,
c3_p0_cmd_full => c3_p0_cmd_full,
c3_p0_wr_clk => (c3_clk0),
c3_p0_wr_en => c3_p0_wr_en,
c3_p0_wr_mask => c3_p0_wr_mask,
c3_p0_wr_data => c3_p0_wr_data,
c3_p0_wr_full => c3_p0_wr_full,
c3_p0_wr_empty => c3_p0_wr_empty,
c3_p0_wr_count => c3_p0_wr_count,
c3_p0_wr_underrun => c3_p0_wr_underrun,
c3_p0_wr_error => c3_p0_wr_error,
c3_p0_rd_clk => (c3_clk0),
c3_p0_rd_en => c3_p0_rd_en,
c3_p0_rd_data => c3_p0_rd_data,
c3_p0_rd_full => c3_p0_rd_full,
c3_p0_rd_empty => c3_p0_rd_empty,
c3_p0_rd_count => c3_p0_rd_count,
c3_p0_rd_overflow => c3_p0_rd_overflow,
c3_p0_rd_error => c3_p0_rd_error
);
-- user interface
memc1_tb_top_inst : memc1_tb_top generic map
(
C_NUM_DQ_PINS => C1_NUM_DQ_PINS,
C_MEM_BURST_LEN => C1_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C1_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C1_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C1_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C1_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C1_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C1_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C1_p0_DATA_MODE,
C_p0_END_ADDRESS => C1_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C1_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C1_p0_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c1_clk0,
rst0 => c1_rst0,
calib_done => c1_calib_done,
cmp_error => c1_cmp_error,
error => c1_error,
error_status => c1_error_status,
vio_modify_enable => c1_vio_modify_enable,
vio_data_mode_value => c1_vio_data_mode_value,
vio_addr_mode_value => c1_vio_addr_mode_value,
p0_mcb_cmd_en_o => c1_p0_cmd_en,
p0_mcb_cmd_instr_o => c1_p0_cmd_instr,
p0_mcb_cmd_bl_o => c1_p0_cmd_bl,
p0_mcb_cmd_addr_o => c1_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c1_p0_cmd_full,
p0_mcb_wr_en_o => c1_p0_wr_en,
p0_mcb_wr_mask_o => c1_p0_wr_mask,
p0_mcb_wr_data_o => c1_p0_wr_data,
p0_mcb_wr_full_i => c1_p0_wr_full,
p0_mcb_wr_fifo_counts => c1_p0_wr_count,
p0_mcb_rd_en_o => c1_p0_rd_en,
p0_mcb_rd_data_i => c1_p0_rd_data,
p0_mcb_rd_empty_i => c1_p0_rd_empty,
p0_mcb_rd_fifo_counts => c1_p0_rd_count
);
-- user interface
memc3_tb_top_inst : memc3_tb_top generic map
(
C_NUM_DQ_PINS => C3_NUM_DQ_PINS,
C_MEM_BURST_LEN => C3_MEM_BURST_LEN,
C_MEM_NUM_COL_BITS => C3_MEM_NUM_COL_BITS,
C_P0_MASK_SIZE => C3_P0_MASK_SIZE,
C_P0_DATA_PORT_SIZE => C3_P0_DATA_PORT_SIZE,
C_P1_MASK_SIZE => C3_P1_MASK_SIZE,
C_P1_DATA_PORT_SIZE => C3_P1_DATA_PORT_SIZE,
C_p0_BEGIN_ADDRESS => C3_p0_BEGIN_ADDRESS,
C_p0_DATA_MODE => C3_p0_DATA_MODE,
C_p0_END_ADDRESS => C3_p0_END_ADDRESS,
C_p0_PRBS_EADDR_MASK_POS => C3_p0_PRBS_EADDR_MASK_POS,
C_p0_PRBS_SADDR_MASK_POS => C3_p0_PRBS_SADDR_MASK_POS
)
port map
(
clk0 => c3_clk0,
rst0 => c3_rst0,
calib_done => c3_calib_done,
cmp_error => c3_cmp_error,
error => c3_error,
error_status => c3_error_status,
vio_modify_enable => c3_vio_modify_enable,
vio_data_mode_value => c3_vio_data_mode_value,
vio_addr_mode_value => c3_vio_addr_mode_value,
p0_mcb_cmd_en_o => c3_p0_cmd_en,
p0_mcb_cmd_instr_o => c3_p0_cmd_instr,
p0_mcb_cmd_bl_o => c3_p0_cmd_bl,
p0_mcb_cmd_addr_o => c3_p0_cmd_byte_addr,
p0_mcb_cmd_full_i => c3_p0_cmd_full,
p0_mcb_wr_en_o => c3_p0_wr_en,
p0_mcb_wr_mask_o => c3_p0_wr_mask,
p0_mcb_wr_data_o => c3_p0_wr_data,
p0_mcb_wr_full_i => c3_p0_wr_full,
p0_mcb_wr_fifo_counts => c3_p0_wr_count,
p0_mcb_rd_en_o => c3_p0_rd_en,
p0_mcb_rd_data_i => c3_p0_rd_data,
p0_mcb_rd_empty_i => c3_p0_rd_empty,
p0_mcb_rd_fifo_counts => c3_p0_rd_count
);
-- ========================================================================== --
-- Memory model instances --
-- ========================================================================== --
mcb1_command <= (mcb1_dram_ras_n & mcb1_dram_cas_n & mcb1_dram_we_n);
process(mcb1_dram_ck)
begin
if (rising_edge(mcb1_dram_ck)) then
if (c1_sys_rst = '0') then
mcb1_enable1 <= '0';
mcb1_enable2 <= '0';
elsif (mcb1_command = "100") then
mcb1_enable2 <= '0';
elsif (mcb1_command = "101") then
mcb1_enable2 <= '1';
else
mcb1_enable2 <= mcb1_enable2;
end if;
mcb1_enable1 <= mcb1_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb1_dram_dqs_vector(1 downto 0) <= (mcb1_dram_udqs & mcb1_dram_dqs)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
mcb1_dram_dqs_n_vector(1 downto 0) <= (mcb1_dram_udqs_n & mcb1_dram_dqs_n)
when (mcb1_enable2 = '0' and mcb1_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb1_dram_dqs <= mcb1_dram_dqs_vector(0)
when ( mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs <= mcb1_dram_dqs_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_dqs_n <= mcb1_dram_dqs_n_vector(0)
when (mcb1_enable1 = '1') else 'Z';
mcb1_dram_udqs_n <= mcb1_dram_dqs_n_vector(1)
when (mcb1_enable1 = '1') else 'Z';
mcb3_command <= (mcb3_dram_ras_n & mcb3_dram_cas_n & mcb3_dram_we_n);
process(mcb3_dram_ck)
begin
if (rising_edge(mcb3_dram_ck)) then
if (c3_sys_rst = '0') then
mcb3_enable1 <= '0';
mcb3_enable2 <= '0';
elsif (mcb3_command = "100") then
mcb3_enable2 <= '0';
elsif (mcb3_command = "101") then
mcb3_enable2 <= '1';
else
mcb3_enable2 <= mcb3_enable2;
end if;
mcb3_enable1 <= mcb3_enable2;
end if;
end process;
-----------------------------------------------------------------------------
--read
-----------------------------------------------------------------------------
mcb3_dram_dqs_vector(1 downto 0) <= (mcb3_dram_udqs & mcb3_dram_dqs)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
mcb3_dram_dqs_n_vector(1 downto 0) <= (mcb3_dram_udqs_n & mcb3_dram_dqs_n)
when (mcb3_enable2 = '0' and mcb3_enable1 = '0')
else "ZZ";
-----------------------------------------------------------------------------
--write
-----------------------------------------------------------------------------
mcb3_dram_dqs <= mcb3_dram_dqs_vector(0)
when ( mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs <= mcb3_dram_dqs_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_dqs_n <= mcb3_dram_dqs_n_vector(0)
when (mcb3_enable1 = '1') else 'Z';
mcb3_dram_udqs_n <= mcb3_dram_dqs_n_vector(1)
when (mcb3_enable1 = '1') else 'Z';
mcb1_dram_dm_vector <= (mcb1_dram_udm & mcb1_dram_dm);
u_mem_c1 : ddr3_model_c1 port map
(
ck => mcb1_dram_ck,
ck_n => mcb1_dram_ck_n,
cke => mcb1_dram_cke,
cs_n => '0',
ras_n => mcb1_dram_ras_n,
cas_n => mcb1_dram_cas_n,
we_n => mcb1_dram_we_n,
dm_tdqs => mcb1_dram_dm_vector,
ba => mcb1_dram_ba,
addr => mcb1_dram_a,
dq => mcb1_dram_dq,
dqs => mcb1_dram_dqs_vector,
dqs_n => mcb1_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb1_dram_odt,
rst_n => mcb1_dram_reset_n
);
mcb3_dram_dm_vector <= (mcb3_dram_udm & mcb3_dram_dm);
u_mem_c3 : ddr3_model_c3 port map
(
ck => mcb3_dram_ck,
ck_n => mcb3_dram_ck_n,
cke => mcb3_dram_cke,
cs_n => '0',
ras_n => mcb3_dram_ras_n,
cas_n => mcb3_dram_cas_n,
we_n => mcb3_dram_we_n,
dm_tdqs => mcb3_dram_dm_vector,
ba => mcb3_dram_ba,
addr => mcb3_dram_a,
dq => mcb3_dram_dq,
dqs => mcb3_dram_dqs_vector,
dqs_n => mcb3_dram_dqs_n_vector,
tdqs_n => open,
odt => mcb3_dram_odt,
rst_n => mcb3_dram_reset_n
);
-----------------------------------------------------------------------------
-- Reporting the test case status
-----------------------------------------------------------------------------
Logging: process
begin
wait for 200 us;
if (calib_done = '1') then
if (error = '0') then
report ("****TEST PASSED****");
else
report ("****TEST FAILED: DATA ERROR****");
end if;
else
report ("****TEST FAILED: INITIALIZATION DID NOT COMPLETE****");
end if;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--
-- The timer unit.
--
-- $Id: t400_timer.vhd,v 1.1 2006-05-20 02:47:12 arniml Exp $
--
-- Copyright (c) 2006 Arnim Laeuger ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t400/
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.t400_pack.all;
entity t400_timer is
port (
-- System Interface -------------------------------------------------------
ck_i : in std_logic;
ck_en_i : in boolean;
por_i : in boolean;
icyc_en_i : in boolean;
-- Skip Interface ---------------------------------------------------------
op_i : in skip_op_t;
c_o : out boolean
);
end t400_timer;
library ieee;
use ieee.numeric_std.all;
architecture rtl of t400_timer is
signal cnt_q : unsigned(9 downto 0);
signal c_q : boolean;
begin
-----------------------------------------------------------------------------
-- Process seq
--
-- Purpose:
-- Implements the sequential elements:
-- * timer counter
-- * carry (underflow) marker flag
--
seq: process (ck_i, por_i)
begin
if por_i then
cnt_q <= (others => '1');
c_q <= false;
elsif ck_i'event and ck_i = '1' then
if icyc_en_i then
if cnt_q = 0 then
-- counter underflow:
-- * reload counter
-- * set marker flag
cnt_q <= (others => '1');
c_q <= true;
else
cnt_q <= cnt_q - 1;
end if;
end if;
if ck_en_i and op_i = SKIP_TIMER then
c_q <= false;
end if;
end if;
end process seq;
--
-----------------------------------------------------------------------------
c_o <= c_q;
end rtl;
-------------------------------------------------------------------------------
-- File History:
--
-- $Log: not supported by cvs2svn $
-------------------------------------------------------------------------------
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"AD030000_0081181B_8CE20000_0102381B", -- Loc 0C, 08, 04, 00
-- X"00000020_8D020004_AD000008_8D0C0000", -- Loc 1C, 18, 14, 10
X"00000020_8D0C0000_AD000008_8D020004", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Byung-Yeob Kim
-- Modified: 08-01-2008
--
-- 0102381B -- div $7, $8, $2
-- 8CE20000 -- lw $2, 0($7)
-- 0081181B -- div $3, $4, $1
-- AD030000 -- sw $3, 0($8)
-- 8D020004 -- lw $2, 4($8)
-- AD000008 -- sw $0, 8($8)
-- 8D0C0000 -- lw $12, 0($8)
--
----------------------------------------------
--
-- div $7, $8, $2 is ...
-- 000000 8 2 7 00000 011011
-- 000000 01000 00010 00111 00000 011011
-- 0000 0001 0000 0010 0011 1000 0001 1011
-- 0102381B
--
-- div $3, $4, $1 is ...
-- 000000 4 1 3 00000 011011
-- 000000 00100 00001 00011 00000 011011
-- 0000 0000 1000 0001 0001 1000 0001 1011
-- 0081181B
----------------------------------------------
--
-- The register file and data memory are expected to change as follows.
--
-- REGISTER
-- $0 0
-- $1 1
-- $2 2 -> 030h
-- $3 3 -> 4
-- $4 4
-- $5 5
-- $6 6
-- $7 7 -> 4
-- $8 8
-- $9 9
-- $A A
-- $B B
-- $C C -> 4
--
-- MEM
-- 00 000h
-- 04 010h
-- 08 020h -> 4
-- 0c 030h
-- 10 040h -> 0
-- 14 050h
--
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"AD030000_0081181B_8CE20000_0102381B", -- Loc 0C, 08, 04, 00
-- X"00000020_8D020004_AD000008_8D0C0000", -- Loc 1C, 18, 14, 10
X"00000020_8D0C0000_AD000008_8D020004", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Byung-Yeob Kim
-- Modified: 08-01-2008
--
-- 0102381B -- div $7, $8, $2
-- 8CE20000 -- lw $2, 0($7)
-- 0081181B -- div $3, $4, $1
-- AD030000 -- sw $3, 0($8)
-- 8D020004 -- lw $2, 4($8)
-- AD000008 -- sw $0, 8($8)
-- 8D0C0000 -- lw $12, 0($8)
--
----------------------------------------------
--
-- div $7, $8, $2 is ...
-- 000000 8 2 7 00000 011011
-- 000000 01000 00010 00111 00000 011011
-- 0000 0001 0000 0010 0011 1000 0001 1011
-- 0102381B
--
-- div $3, $4, $1 is ...
-- 000000 4 1 3 00000 011011
-- 000000 00100 00001 00011 00000 011011
-- 0000 0000 1000 0001 0001 1000 0001 1011
-- 0081181B
----------------------------------------------
--
-- The register file and data memory are expected to change as follows.
--
-- REGISTER
-- $0 0
-- $1 1
-- $2 2 -> 030h
-- $3 3 -> 4
-- $4 4
-- $5 5
-- $6 6
-- $7 7 -> 4
-- $8 8
-- $9 9
-- $A A
-- $B B
-- $C C -> 4
--
-- MEM
-- 00 000h
-- 04 010h
-- 08 020h -> 4
-- 0c 030h
-- 10 040h -> 0
-- 14 050h
--
|
-- file: i_fetch_test_stream_instr_stream_pkg.vhd (version: i_fetch_test_stream_instr_stream_pkg_non_aligned_branches.vhd)
-- Written by Gandhi Puvvada
-- date of last rivision: 7/23/2008
--
-- A package file to define the instruction stream to be placed in the instr_cache.
-- This package, "instr_stream_pkg", is refered in a use clause in the inst_cache_sprom module.
-- We will use several files similar to this containining different instruction streams.
-- The package name will remain the same, namely instr_stream_pkg.
-- Only the file name changes from, say i_fetch_test_stream_instr_stream_pkg.vhd
-- to say mult_test_stream_instr_stream_pkg.vhd.
-- Depending on which instr_stream_pkg file was analysed/compiled most recently,
-- that stream will be used for simulation/synthesis.
----------------------------------------------------------
library std, ieee;
use ieee.std_logic_1164.all;
package instr_stream_pkg is
constant DATA_WIDTH_CONSTANT : integer := 128; -- data width of of our cache
constant ADDR_WIDTH_CONSTANT : integer := 6; -- address width of our cache
-- type declarations
type mem_type is array (0 to (2**ADDR_WIDTH_CONSTANT)-1) of std_logic_vector((DATA_WIDTH_CONSTANT-1) downto 0);
signal mem : mem_type := (
X"AD030000_0081181B_8CE20000_0102381B", -- Loc 0C, 08, 04, 00
-- X"00000020_8D020004_AD000008_8D0C0000", -- Loc 1C, 18, 14, 10
X"00000020_8D0C0000_AD000008_8D020004", -- Loc 1C, 18, 14, 10 -- corrected
X"00000020_00000020_00000020_00000020", -- Loc 2C, 28, 24, 20
X"00000020_00000020_00000020_00000020", -- Loc 3C, 38, 34, 30
X"00000020_00000020_00000020_00000020", -- Loc 4C, 48, 44, 40
X"00000020_00000020_00000020_00000020", -- Loc 5C, 58, 54, 50
X"00000020_00000020_00000020_00000020", -- Loc 6C, 68, 64, 60
X"00000020_00000020_00000020_00000020", -- Loc 7C, 78, 74, 70
X"00000020_00000020_00000020_00000020", -- Loc 8C, 88, 84, 80
X"00000020_00000020_00000020_00000020", -- Loc 9C, 98, 94, 90
X"00000020_00000020_00000020_00000020", -- Loc AC, A8, A4, A0
X"00000020_00000020_00000020_00000020", -- Loc BC, B8, B4, B0
X"00000020_00000020_00000020_00000020", -- Loc CC, C8, C4, C0
X"00000020_00000020_00000020_00000020", -- Loc DC, D8, D4, D0
X"00000020_00000020_00000020_00000020", -- Loc EC, E8, E4, E0
X"00000020_00000020_00000020_00000020", -- Loc FC, F8, F4, F0
X"00000020_00000020_00000020_00000020", -- Loc 10C, 108, 104, 100
X"00000020_00000020_00000020_00000020", -- Loc 11C, 118, 114, 110
X"00000020_00000020_00000020_00000020", -- Loc 12C, 128, 124, 120
X"00000020_00000020_00000020_00000020", -- Loc 13C, 138, 134, 130
X"00000020_00000020_00000020_00000020", -- Loc 14C, 148, 144, 140
X"00000020_00000020_00000020_00000020", -- Loc 15C, 158, 154, 150
X"00000020_00000020_00000020_00000020", -- Loc 16C, 168, 164, 160
X"00000020_00000020_00000020_00000020", -- Loc 17C, 178, 174, 170
X"00000020_00000020_00000020_00000020", -- Loc 18C, 188, 184, 180
X"00000020_00000020_00000020_00000020", -- Loc 19C, 198, 194, 190
X"00000020_00000020_00000020_00000020", -- Loc 1AC, 1A8, 1A4, 1A0
X"00000020_00000020_00000020_00000020", -- Loc 1BC, 1B8, 1B4, 1B0
X"00000020_00000020_00000020_00000020", -- Loc 1CC, 1C8, 1C4, 1C0
X"00000020_00000020_00000020_00000020", -- Loc 1DC, 1D8, 1D4, 1D0
X"00000020_00000020_00000020_00000020", -- Loc 1EC, 1E8, 1E4, 1E0
X"00000020_00000020_00000020_00000020", -- Loc 1FC, 1F8, 1F4, 1F0
X"00000020_00000020_00000020_00000020", -- Loc 20C, 208, 204, 200
X"00000020_00000020_00000020_00000020", -- Loc 21C, 218, 214, 221
X"00000020_00000020_00000020_00000020", -- Loc 22C, 228, 224, 220
X"00000020_00000020_00000020_00000020", -- Loc 23C, 238, 234, 230
X"00000020_00000020_00000020_00000020", -- Loc 24C, 248, 244, 240
X"00000020_00000020_00000020_00000020", -- Loc 25C, 258, 254, 250
X"00000020_00000020_00000020_00000020", -- Loc 26C, 268, 264, 260
X"00000020_00000020_00000020_00000020", -- Loc 27C, 278, 274, 270
X"00000020_00000020_00000020_00000020", -- Loc 28C, 288, 284, 280
X"00000020_00000020_00000020_00000020", -- Loc 29C, 298, 294, 290
X"00000020_00000020_00000020_00000020", -- Loc 2AC, 2A8, 2A4, 2A0
X"00000020_00000020_00000020_00000020", -- Loc 2BC, 2B8, 2B4, 2B0
X"00000020_00000020_00000020_00000020", -- Loc 2CC, 2C8, 2C4, 2C0
X"00000020_00000020_00000020_00000020", -- Loc 2DC, 2D8, 2D4, 2D0
X"00000020_00000020_00000020_00000020", -- Loc 2EC, 2E8, 2E4, 2E0
X"00000020_00000020_00000020_00000020", -- Loc 2FC, 2F8, 2F4, 2F0
X"00000020_00000020_00000020_00000020", -- Loc 30C, 308, 304, 300
X"00000020_00000020_00000020_00000020", -- Loc 31C, 318, 314, 331
X"00000020_00000020_00000020_00000020", -- Loc 32C, 328, 324, 320
X"00000020_00000020_00000020_00000020", -- Loc 33C, 338, 334, 330
X"00000020_00000020_00000020_00000020", -- Loc 34C, 348, 344, 340
X"00000020_00000020_00000020_00000020", -- Loc 35C, 358, 354, 350
X"00000020_00000020_00000020_00000020", -- Loc 36C, 368, 364, 360
X"00000020_00000020_00000020_00000020", -- Loc 37C, 378, 374, 370
X"00000020_00000020_00000020_00000020", -- Loc 38C, 388, 384, 380
X"00000020_00000020_00000020_00000020", -- Loc 39C, 398, 394, 390
X"00000020_00000020_00000020_00000020", -- Loc 3AC, 3A8, 3A4, 3A0
X"00000020_00000020_00000020_00000020", -- Loc 3BC, 3B8, 3B4, 3B0
-- the last 16 instructions are looping jump instructions
X"080000F3_080000F2_080000F1_080000F0", -- Loc 3CC, 3C8, 3C4, 3C0
X"080000F7_080000F6_080000F5_080000F4", -- Loc 3DC, 3D8, 3D4, 3D0
X"080000FB_080000FA_080000F9_080000F8", -- Loc 3EC, 3E8, 3E4, 3E0
X"080000FF_080000FE_080000FD_080000FC" -- Loc 3FC, 3F8, 3F4, 3F0
) ;
end package instr_stream_pkg;
-- MEMORY DISAMBIGUATION
-- Byung-Yeob Kim
-- Modified: 08-01-2008
--
-- 0102381B -- div $7, $8, $2
-- 8CE20000 -- lw $2, 0($7)
-- 0081181B -- div $3, $4, $1
-- AD030000 -- sw $3, 0($8)
-- 8D020004 -- lw $2, 4($8)
-- AD000008 -- sw $0, 8($8)
-- 8D0C0000 -- lw $12, 0($8)
--
----------------------------------------------
--
-- div $7, $8, $2 is ...
-- 000000 8 2 7 00000 011011
-- 000000 01000 00010 00111 00000 011011
-- 0000 0001 0000 0010 0011 1000 0001 1011
-- 0102381B
--
-- div $3, $4, $1 is ...
-- 000000 4 1 3 00000 011011
-- 000000 00100 00001 00011 00000 011011
-- 0000 0000 1000 0001 0001 1000 0001 1011
-- 0081181B
----------------------------------------------
--
-- The register file and data memory are expected to change as follows.
--
-- REGISTER
-- $0 0
-- $1 1
-- $2 2 -> 030h
-- $3 3 -> 4
-- $4 4
-- $5 5
-- $6 6
-- $7 7 -> 4
-- $8 8
-- $9 9
-- $A A
-- $B B
-- $C C -> 4
--
-- MEM
-- 00 000h
-- 04 010h
-- 08 020h -> 4
-- 0c 030h
-- 10 040h -> 0
-- 14 050h
--
|
architecture Empty of MyReconfigLogic is
begin
CfgIntfDOut_o <= (others => '0');
AdcDoConvert_o <= '0';
I2C_DataIn_o <= "00000000";
I2C_ErrAckParam_o <= '0';
I2C_F100_400_n_o <= '0';
I2C_FIFOReadNext_o <= '0';
I2C_FIFOWrite_o <= '0';
I2C_ReceiveSend_n_o <= '0';
I2C_StartProcess_o <= '0';
I2C_ReadCount_o <= (others => '0');
-- OneWire_CondReadROM_o <= '0';
-- OneWire_CondSearchROM_o <= '0';
-- OneWire_DataIn_o <= "00000000";
-- OneWire_DeactivateOverdriveMode_o <= '0';
-- OneWire_GetROMID_o <= '0';
-- OneWire_MatchROM_o <= '0';
-- OneWire_OWReset_o <= '0';
-- OneWire_OverdriveMatchROM_o <= '0';
-- OneWire_OverdriveSkipROM_o <= '0';
-- OneWire_ReadByte_o <= '0';
-- OneWire_ReadROM_o <= '0';
-- OneWire_ResumeROM_o <= '0';
-- OneWire_SearchROM_o <= '0';
-- OneWire_SkipROM_o <= '0';
-- OneWire_WriteByte_o <= '0';
Outputs_o <= (others => '0');
-- PWM_Polarity_o <= '0';
-- SENT_Chipselect_o <= '0';
-- SENT_OutMUX_o(0) <= '0';
-- SENT_OutMUX_o(1) <= '0';
-- SENT_NumDatNibble_o <= (others => '0');
-- SPC_OutMUX_o(0) <= '0';
-- SPC_OutMUX_o(1) <= '0';
-- SPC_Start_o <= '0';
-- SPC_NumDatNibble_o <= (others => '0');
SPI_SPPR_SPR_o <= "00000000";
ReconfModuleIRQs_o <= (others => '0');
ReconfModuleOut_o <= (others => '0');
ParamIntfDOut_o <= (others => '0');
I2C_Divider800_o <= (others => '0');
SPI_CPHA_o <= '0';
SPI_CPOL_o <= '0';
SPI_DataIn_o <= (others => '0');
SPI_LSBFE_o <= '0';
SPI_ReadNext_o <= '0';
SPI_Write_o <= '0';
-- OneWire_ODRDSlotInitTime_o <= (others => '0');
-- OneWire_ODRDSlotSampleTime_o <= (others => '0');
-- OneWire_ODResetLowTime_o <= (others => '0');
-- OneWire_ODResetPrecenceIntervalDuration_o <= (others => '0');
-- OneWire_ODResetTime_o <= (others => '0');
-- OneWire_ODResetWaitForDetectionDuration_o <= (others => '0');
-- OneWire_ODSlotDuration_o <= (others => '0');
-- OneWire_ODSlotLowDataTime_o <= (others => '0');
-- OneWire_ODWRSlotHighDataTime_o <= (others => '0');
-- OneWire_RDSlotInitTime_o <= (others => '0');
-- OneWire_RDSlotSampleTime_o <= (others => '0');
-- OneWire_ResetLowTime_o <= (others => '0');
-- OneWire_ResetPrecenceIntervalDuration_o <= (others => '0');
-- OneWire_ResetTime_o <= (others => '0');
-- OneWire_ResetWaitForDetectionDuration_o <= (others => '0');
-- OneWire_SlotDuration_o <= (others => '0');
-- OneWire_SlotLowDataTime_o <= (others => '0');
-- OneWire_WRSlotHighDataTime_o <= (others => '0');
-- SENT_MinSync_o <= (others => '0');
-- SPC_LengthTimeout_o <= (others => '0');
-- SPC_LengthTrigger_o <= (others => '0');
-- SPC_MinSync_o <= (others => '0');
end Empty;
|
component pr_region_default_sysid_qsys_0 is
port (
clock : in std_logic := 'X'; -- clk
readdata : out std_logic_vector(31 downto 0); -- readdata
address : in std_logic := 'X'; -- address
reset_n : in std_logic := 'X' -- reset_n
);
end component pr_region_default_sysid_qsys_0;
u0 : component pr_region_default_sysid_qsys_0
port map (
clock => CONNECTED_TO_clock, -- clk.clk
readdata => CONNECTED_TO_readdata, -- control_slave.readdata
address => CONNECTED_TO_address, -- .address
reset_n => CONNECTED_TO_reset_n -- reset.reset_n
);
|
-- $Id: gray2bin_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray2bin_gen - syn
-- Description: Gray code to binary converter
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end entity gray2bin_gen;
architecture syn of gray2bin_gen is
begin
proc_comb: process (DI)
variable ido : slv(DWIDTH-1 downto 0);
begin
ido := (others=>'0');
ido(DWIDTH-1) := DI(DWIDTH-1);
for i in DWIDTH-2 downto 0 loop
ido(i) := ido(i+1) xor DI(i);
end loop;
DO <= ido;
end process proc_comb;
end syn;
|
-- $Id: gray2bin_gen.vhd 418 2011-10-23 20:11:40Z mueller $
--
-- Copyright 2007- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: gray2bin_gen - syn
-- Description: Gray code to binary converter
--
-- Dependencies: -
-- Test bench: tb/tb_debounce_gen
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2; ghdl 0.18-0.25
-- Revision History:
-- Date Rev Version Comment
-- 2007-12-26 106 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
entity gray2bin_gen is -- gray->bin converter, generic vector
generic (
DWIDTH : positive := 4); -- data width
port (
DI : in slv(DWIDTH-1 downto 0); -- gray code input
DO : out slv(DWIDTH-1 downto 0) -- binary code output
);
end entity gray2bin_gen;
architecture syn of gray2bin_gen is
begin
proc_comb: process (DI)
variable ido : slv(DWIDTH-1 downto 0);
begin
ido := (others=>'0');
ido(DWIDTH-1) := DI(DWIDTH-1);
for i in DWIDTH-2 downto 0 loop
ido(i) := ido(i+1) xor DI(i);
end loop;
DO <= ido;
end process proc_comb;
end syn;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.1 (lin64) Build 881834 Fri Apr 4 14:00:25 MDT 2014
-- Date : Mon Jan 26 10:14:21 2015
-- Host : xilinxvivadotools running 64-bit unknown
-- Command : write_vhdl -force -mode funcsim
-- /home/ece532/testing/ov7670/nexys4ddr_ov7670/nexys4ddr_ov7670.srcs/sources_1/ip/clk_wiz_0/clk_wiz_0_funcsim.vhdl
-- Design : clk_wiz_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0clk_wiz_0_clk_wiz is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of clk_wiz_0clk_wiz_0_clk_wiz : entity is "clk_wiz_0_clk_wiz";
end clk_wiz_0clk_wiz_0_clk_wiz;
architecture STRUCTURE of clk_wiz_0clk_wiz_0_clk_wiz is
signal clk_in1_clk_wiz_0 : STD_LOGIC;
signal clk_out1_clk_wiz_0 : STD_LOGIC;
signal clk_out2_clk_wiz_0 : STD_LOGIC;
signal clkfbout_buf_clk_wiz_0 : STD_LOGIC;
signal clkfbout_clk_wiz_0 : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DRDY_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_LOCKED_UNCONNECTED : STD_LOGIC;
signal NLW_plle2_adv_inst_DO_UNCONNECTED : STD_LOGIC_VECTOR ( 15 downto 0 );
attribute BOX_TYPE : string;
attribute BOX_TYPE of clkf_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkin1_ibufg : label is "PRIMITIVE";
attribute CAPACITANCE : string;
attribute CAPACITANCE of clkin1_ibufg : label is "DONT_CARE";
attribute IBUF_DELAY_VALUE : string;
attribute IBUF_DELAY_VALUE of clkin1_ibufg : label is "0";
attribute IFD_DELAY_VALUE : string;
attribute IFD_DELAY_VALUE of clkin1_ibufg : label is "AUTO";
attribute BOX_TYPE of clkout1_buf : label is "PRIMITIVE";
attribute BOX_TYPE of clkout2_buf : label is "PRIMITIVE";
attribute BOX_TYPE of plle2_adv_inst : label is "PRIMITIVE";
begin
clkf_buf: unisim.vcomponents.BUFG
port map (
I => clkfbout_clk_wiz_0,
O => clkfbout_buf_clk_wiz_0
);
clkin1_ibufg: unisim.vcomponents.IBUF
generic map(
IOSTANDARD => "DEFAULT"
)
port map (
I => clk_in1,
O => clk_in1_clk_wiz_0
);
clkout1_buf: unisim.vcomponents.BUFG
port map (
I => clk_out1_clk_wiz_0,
O => clk_out1
);
clkout2_buf: unisim.vcomponents.BUFG
port map (
I => clk_out2_clk_wiz_0,
O => clk_out2
);
plle2_adv_inst: unisim.vcomponents.PLLE2_ADV
generic map(
BANDWIDTH => "OPTIMIZED",
CLKFBOUT_MULT => 8,
CLKFBOUT_PHASE => 0.000000,
CLKIN1_PERIOD => 10.000000,
CLKIN2_PERIOD => 0.000000,
CLKOUT0_DIVIDE => 16,
CLKOUT0_DUTY_CYCLE => 0.500000,
CLKOUT0_PHASE => 0.000000,
CLKOUT1_DIVIDE => 32,
CLKOUT1_DUTY_CYCLE => 0.500000,
CLKOUT1_PHASE => 0.000000,
CLKOUT2_DIVIDE => 1,
CLKOUT2_DUTY_CYCLE => 0.500000,
CLKOUT2_PHASE => 0.000000,
CLKOUT3_DIVIDE => 1,
CLKOUT3_DUTY_CYCLE => 0.500000,
CLKOUT3_PHASE => 0.000000,
CLKOUT4_DIVIDE => 1,
CLKOUT4_DUTY_CYCLE => 0.500000,
CLKOUT4_PHASE => 0.000000,
CLKOUT5_DIVIDE => 1,
CLKOUT5_DUTY_CYCLE => 0.500000,
CLKOUT5_PHASE => 0.000000,
COMPENSATION => "ZHOLD",
DIVCLK_DIVIDE => 1,
IS_CLKINSEL_INVERTED => '0',
IS_PWRDWN_INVERTED => '0',
IS_RST_INVERTED => '0',
REF_JITTER1 => 0.010000,
REF_JITTER2 => 0.010000,
STARTUP_WAIT => "FALSE"
)
port map (
CLKFBIN => clkfbout_buf_clk_wiz_0,
CLKFBOUT => clkfbout_clk_wiz_0,
CLKIN1 => clk_in1_clk_wiz_0,
CLKIN2 => '0',
CLKINSEL => '1',
CLKOUT0 => clk_out1_clk_wiz_0,
CLKOUT1 => clk_out2_clk_wiz_0,
CLKOUT2 => NLW_plle2_adv_inst_CLKOUT2_UNCONNECTED,
CLKOUT3 => NLW_plle2_adv_inst_CLKOUT3_UNCONNECTED,
CLKOUT4 => NLW_plle2_adv_inst_CLKOUT4_UNCONNECTED,
CLKOUT5 => NLW_plle2_adv_inst_CLKOUT5_UNCONNECTED,
DADDR(6) => '0',
DADDR(5) => '0',
DADDR(4) => '0',
DADDR(3) => '0',
DADDR(2) => '0',
DADDR(1) => '0',
DADDR(0) => '0',
DCLK => '0',
DEN => '0',
DI(15) => '0',
DI(14) => '0',
DI(13) => '0',
DI(12) => '0',
DI(11) => '0',
DI(10) => '0',
DI(9) => '0',
DI(8) => '0',
DI(7) => '0',
DI(6) => '0',
DI(5) => '0',
DI(4) => '0',
DI(3) => '0',
DI(2) => '0',
DI(1) => '0',
DI(0) => '0',
DO(15 downto 0) => NLW_plle2_adv_inst_DO_UNCONNECTED(15 downto 0),
DRDY => NLW_plle2_adv_inst_DRDY_UNCONNECTED,
DWE => '0',
LOCKED => NLW_plle2_adv_inst_LOCKED_UNCONNECTED,
PWRDWN => '0',
RST => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity clk_wiz_0 is
port (
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
clk_out2 : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of clk_wiz_0 : entity is true;
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of clk_wiz_0 : entity is "clk_wiz_0,clk_wiz_v5_1,{component_name=clk_wiz_0,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=PLL,num_out_clk=2,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=false,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
end clk_wiz_0;
architecture STRUCTURE of clk_wiz_0 is
begin
inst: entity work.clk_wiz_0clk_wiz_0_clk_wiz
port map (
clk_in1 => clk_in1,
clk_out1 => clk_out1,
clk_out2 => clk_out2
);
end STRUCTURE;
|
------------------------------------------------------------------
-- _____
-- / \
-- /____ \____
-- / \===\ \==/
-- /___\===\___\/ AVNET
-- \======/
-- \====/
-----------------------------------------------------------------
--
-- This design is the property of Avnet. Publication of this
-- design is not authorized without written consent from Avnet.
--
-- Please direct any questions to: [email protected]
--
-- Disclaimer:
-- Avnet, Inc. makes no warranty for the use of this code or design.
-- This code is provided "As Is". Avnet, Inc assumes no responsibility for
-- any errors, which may appear in this code, nor does it make a commitment
-- to update the information contained herein. Avnet, Inc specifically
-- disclaims any implied warranties of fitness for a particular purpose.
-- Copyright(c) 2011 Avnet, Inc.
-- All rights reserved.
--
------------------------------------------------------------------
--
-- Create Date: May 19, 2012
-- Design Name: ZedBoard HDMI Output
-- Module Name: zed_hdmi_out.vhd
-- Project Name: ZedBoard HDMI Output
-- Target Devices: Zynq-7000
--
-- Tool versions: ISE 14.3
--
-- Description: ZedBoard HDMI output interface.
--
-- Dependencies:
--
-- Revision: May 19, 2012: 1.02 Initial version
-- Dec 21, 2012: 2.01 Remove XSVI bus interface
-- Remove xsvi_ prefixes to video_
-- Rename active_video to de
-- Change IP_GROUP to FMC-IMAGEON
--
------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;
entity zed_hdmi_out is
Generic
(
C_DATA_WIDTH : integer := 16;
C_FAMILY : string := "virtex6"
);
Port
(
clk : in std_logic;
reset : in std_logic;
-- Audio Input Port
audio_spdif : in std_logic;
-- Video Ports
video_vsync : in std_logic;
video_hsync : in std_logic;
video_de : in std_logic;
video_data : in std_logic_vector((C_DATA_WIDTH-1) downto 0);
-- I/O pins
io_hdmio_spdif : out std_logic;
io_hdmio_video : out std_logic_vector(15 downto 0);
io_hdmio_vsync : out std_logic;
io_hdmio_hsync : out std_logic;
io_hdmio_de : out std_logic;
io_hdmio_clk : out std_logic
);
end zed_hdmi_out;
architecture rtl of zed_hdmi_out is
signal clk_n : std_logic;
signal net0 : std_logic;
signal net1 : std_logic;
signal oe : std_logic;
signal oe_n : std_logic;
--
-- Audio Port
--
signal spdif_r : std_logic;
--
-- Video Port
--
signal video_r : std_logic_vector(15 downto 0);
signal vsync_r : std_logic;
signal hsync_r : std_logic;
signal de_r : std_logic;
--
-- IOB Registers
--
signal hdmi_spdif_o : std_logic;
signal hdmi_video_o : std_logic_vector(15 downto 0);
signal hdmi_vsync_o : std_logic;
signal hdmi_hsync_o : std_logic;
signal hdmi_de_o : std_logic;
signal hdmi_clk_o : std_logic;
signal hdmi_spdif_t : std_logic;
signal hdmi_video_t : std_logic_vector(15 downto 0);
signal hdmi_vsync_t : std_logic;
signal hdmi_hsync_t : std_logic;
signal hdmi_de_t : std_logic;
signal hdmi_clk_t : std_logic;
attribute IOB : string;
attribute IOB of hdmi_spdif_o : signal is "TRUE";
attribute IOB of hdmi_video_o : signal is "TRUE";
attribute IOB of hdmi_vsync_o : signal is "TRUE";
attribute IOB of hdmi_hsync_o : signal is "TRUE";
attribute IOB of hdmi_de_o : signal is "TRUE";
attribute IOB of hdmi_clk_o : signal is "TRUE";
begin
clk_n <= not clk;
oe <= '1';
oe_n <= not oe;
net0 <= '0';
net1 <= '1';
--
-- Audio Port
--
spdif_r <= audio_spdif;
--
-- Video Ports
--
VIDEO_PORTS_16BIT_GEN : if (C_DATA_WIDTH = 16) generate
video_ports_16bit_iregs_l : process (clk)
begin
if Rising_Edge(clk) then
video_r <= video_data(15 downto 0);
vsync_r <= video_vsync;
hsync_r <= video_hsync;
de_r <= video_de;
end if;
end process;
end generate VIDEO_PORTS_16BIT_GEN;
--
-- IOB Registers
--
io_oregs_l : process (clk)
begin
if Rising_Edge(clk) then
hdmi_spdif_o <= spdif_r;
hdmi_video_o <= video_r;
hdmi_vsync_o <= vsync_r;
hdmi_hsync_o <= hsync_r;
hdmi_de_o <= de_r;
--
hdmi_spdif_t <= oe_n;
hdmi_video_t <= (others => oe_n);
hdmi_vsync_t <= oe_n;
hdmi_hsync_t <= oe_n;
hdmi_de_t <= oe_n;
end if;
end process;
S3ADSP_GEN : if (C_FAMILY = "spartan3adsp") generate
ODDR_hdmi_clk_o : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR2
generic map (
DDR_ALIGNMENT => "NONE", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S3ADSP_GEN;
S6_GEN : if (C_FAMILY = "spartan6") generate
ODDR_hdmi_clk_o : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => net0,
D1 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR2
generic map (
DDR_ALIGNMENT => "C0", -- "NONE", "C0" or "C1"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C0 => clk,
C1 => clk_n,
CE => net1,
D0 => oe_n,
D1 => oe_n,
R => net0,
S => net0);
end generate S6_GEN;
V6_GEN : if (C_FAMILY = "virtex6" or C_FAMILY = "zynq" or C_FAMILY = "kintex7" or C_FAMILY = "artix7" or C_FAMILY = "virtex7") generate
ODDR_hdmi_clk_o : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_o,
C => clk,
CE => net1,
D1 => net0,
D2 => net1,
R => net0,
S => net0);
ODDR_hdmi_clk_t : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE", -- "OPPOSITE_EDGE" or "SAME_EDGE"
INIT => '1', -- Sets initial state of Q
SRTYPE => "ASYNC") -- Reset type
port map (
Q => hdmi_clk_t,
C => clk,
CE => net1,
D1 => oe_n,
D2 => oe_n,
R => net0,
S => net0);
end generate V6_GEN;
--
-- Tri-stateable outputs
-- Can be used to disable outputs to FMC connector
-- until FMC module is correctly identified.
--
OBUFT_hdmio_spdif : OBUFT
port map (
O => io_hdmio_spdif,
I => hdmi_spdif_o,
T => hdmi_spdif_t
);
IO1: for I in 0 to 15 generate
OBUFT_hdmio_video : OBUFT
port map (
O => io_hdmio_video(I),
I => hdmi_video_o(I),
T => hdmi_video_t(I)
);
end generate IO1;
OBUFT_hdmio_vsync : OBUFT
port map (
O => io_hdmio_vsync,
I => hdmi_vsync_o,
T => hdmi_vsync_t
);
OBUFT_hdmio_hsync : OBUFT
port map (
O => io_hdmio_hsync,
I => hdmi_hsync_o,
T => hdmi_hsync_t
);
OBUFT_hdmio_de : OBUFT
port map (
O => io_hdmio_de,
I => hdmi_de_o,
T => hdmi_de_t
);
OBUFT_hdmio_clk : OBUFT
port map (
O => io_hdmio_clk,
I => hdmi_clk_o,
T => hdmi_clk_t
);
end rtl;
|
architecture RTL of FIFO is
begin
process
begin
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
-- Violations below
if a = '1' then
b <= '0';
elsif c = '1' then
b <= '1';
else
if x = '1' then
z <= '0';
elsif x = '0' then
z <= '1';
else
z <= 'Z';
end if;
end if;
end process;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company: XILINX
-- Engineer: Stephan Koster
--
-- Create Date: 07.03.2014 15:16:37
-- Design Name: stats module
-- Module Name: stats_module - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description: Sniffs an axi streaming bus, gathers stats and exposes them in a register
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_MISC.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity stats_module is
Generic(
data_size: INTEGER:=64;
period_counter_size: INTEGER :=22
);
Port (
ACLK : in std_logic;
RESET : in std_logic;
M_AXIS_TDATA : out std_logic_vector (data_size-1 downto 0);
M_AXIS_TSTRB : out std_logic_vector (7 downto 0);
M_AXIS_TVALID : out std_logic;
M_AXIS_TREADY : in std_logic;
M_AXIS_TLAST : out std_logic;
S_AXIS_TDATA : in std_logic_vector (data_size-1 downto 0);
S_AXIS_TSTRB : in std_logic_vector (7 downto 0);
S_AXIS_TUSER : in std_logic_vector (127 downto 0);
S_AXIS_TVALID : in std_logic;
S_AXIS_TREADY : out std_logic;
S_AXIS_TLAST : in std_logic;
--Expose the gathered stats
STATS_DATA : out std_logic_vector(31 downto 0)
);
end stats_module;
architecture Behavioral of stats_module is
signal rst,clk: std_logic;--rename hard to type signals
signal busycount: std_logic_vector(31 downto 0);--counts how many cycles both ready and valid are on
signal idlecount: std_logic_vector(31 downto 0);--so far does nothing
signal period_tracker: std_logic_vector(period_counter_size-1 downto 0);--measuring period ends on rollaround
signal count_reset:std_logic;
begin
rst<=RESET;
clk<=ACLK;
--axi stream signals pass straight through from master to slave. We just read Ready and Valid signals
M_AXIS_TDATA <= S_AXIS_TDATA;
M_AXIS_TSTRB <= S_AXIS_TSTRB;
M_AXIS_TVALID <= S_AXIS_TVALID;
S_AXIS_TREADY <= M_AXIS_TREADY;
M_AXIS_TLAST <= S_AXIS_TLAST;
generate_period:process(rst,clk)
begin
if(rst='1') then
period_tracker<=(others=>'0');
elsif(rising_edge(clk)) then
period_tracker<=std_logic_vector(unsigned(period_tracker)+1);
count_reset<=AND_REDUCE( period_tracker);--bitwise and
end if;
end process;
process(rst,clk)
begin
if(rst='1') then
--reset state
busycount<=(others=>'0');
STATS_DATA<=(others=>'0');
elsif(rising_edge(clk)) then
--write the output signal with the stats when the period counter rolls around
if(count_reset='1') then
--STATS_DATA(31)<='1';
STATS_DATA(period_counter_size downto 0)<=busycount(period_counter_size downto 0);
busycount<=(others=>'0');
else
--sniff the axi stream signals, gather stats
if(M_AXIS_TREADY='1' and S_AXIS_TVALID='1') then
busycount<=std_logic_vector(unsigned(busycount)+1);
end if;
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_signed.all;
use IEEE.STD_logic_arith.all;
entity operational_unit is
generic(
N: integer := 4
);
port(
clk,rst : in STD_LOGIC;
y : in STD_LOGIC_VECTOR(12 downto 1);
d1 : in STD_LOGIC_VECTOR(N-1 downto 0);
d2 : in STD_LOGIC_VECTOR(N-1 downto 0);
r:out STD_LOGIC_VECTOR(2*N-1 downto 0);
x:out STD_LOGIC_vector(4 downto 1)
);
end operational_unit;
architecture operational_unit of operational_unit is
signal A,Ain: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal B,Bin: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal CnT, CnTin: std_logic_vector(7 downto 0);
signal C, Cin: STD_LOGIC_VECTOR(N-1 downto 0) ;
signal overflow, carry: std_logic;
signal of_in, cf_in: std_logic;
signal of_sum, cf_sum: std_logic;
signal sum_result: std_logic_vector(N-1 downto 0);
signal TgB, TgBin: std_logic;
component adder is
generic(
N: integer := 4
);
port(A, B: in std_logic_vector(N-1 downto 0);
Cin: in std_logic;
S: out std_logic_vector(N-1 downto 0);
Cout: out std_logic;
overflow: out std_logic);
end component;
begin
process(clk,rst)is
begin
if rst='0' then
a<=(others=>'0');
b<=(others=>'0');
TgB<='0';
overflow<='0';
Carry <= '0';
CnT<=(others=>'0');
elsif rising_edge(clk)then
A<=Ain;B<=Bin ;CnT <= CnTin; C <= Cin; TgB <= TgBin;
Overflow <= of_in;
Carry <= cf_in;
end if;
end process;
-- Ïîäêëþ÷åíèå ñóììàòîðà
SUM : adder port map(A => C, B => A(N-1 downto 0), Cin => '0', Cout => cf_sum, overflow => of_sum, S => sum_result);
ain<= D1 when y(1)='1'
else a;
bin<= D2 when y(2) = '1'
else C(0) & B(N-1 downto 1) when y(7) = '1'
else b;
Cin <= (others=>'0') when y(3)='1'
else sum_result when y(5) = '1'
else carry & C(N-1 downto 1) when y(9) = '1'
else C(N-1) & C(N-1 downto 1) when y(10) = '1'
else C + not A + 1 when y(11) = '1'
else C;
CnTin <= conv_std_logic_vector(N, 8) when y(4) = '1'
else CnT - 1 when y(8) = '1'
else CnT;
TgBin <= B(0) when y(6) = '1'
else TgB;
R <= C & B when y(12) = '1'
else (others => 'Z');
cf_in <= cf_sum when y(5) = '1'
else carry;
of_in <= of_sum when y(5) = '1'
else overflow;
x(1) <= '1' when B(0) = '1' else '0';
x(2) <= '1' when overflow = '1' else '0';
x(3) <= '1' when CnT = 0 else '0';
x(4) <= '1' when TgB = '1' else '0';
end operational_unit; |
--------------------------------------------------------------------------------
-- This file is owned and controlled by Xilinx and must be used --
-- solely for design, simulation, implementation and creation of --
-- design files limited to Xilinx devices or technologies. Use --
-- with non-Xilinx devices or technologies is expressly prohibited --
-- and immediately terminates your license. --
-- --
-- XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION "AS IS" --
-- SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR --
-- XILINX DEVICES. BY PROVIDING THIS DESIGN, CODE, OR INFORMATION --
-- AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION --
-- OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS --
-- IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT, --
-- AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE --
-- FOR YOUR IMPLEMENTATION. XILINX EXPRESSLY DISCLAIMS ANY --
-- WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE --
-- IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR --
-- REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF --
-- INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS --
-- FOR A PARTICULAR PURPOSE. --
-- --
-- Xilinx products are not intended for use in life support --
-- appliances, devices, or systems. Use in such applications are --
-- expressly prohibited. --
-- --
-- (c) Copyright 1995-2009 Xilinx, Inc. --
-- All rights reserved. --
--------------------------------------------------------------------------------
-- You must compile the wrapper file iserdes_fifo_10_bit.vhd when simulating
-- the core, iserdes_fifo_10_bit. When compiling the wrapper file, be sure to
-- reference the XilinxCoreLib VHDL simulation library. For detailed
-- instructions, please refer to the "CORE Generator Help".
-- The synthesis directives "translate_off/translate_on" specified
-- below are supported by Xilinx, Mentor Graphics and Synplicity
-- synthesis tools. Ensure they are correct for your synthesis tool(s).
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- synthesis translate_off
Library XilinxCoreLib;
-- synthesis translate_on
ENTITY iserdes_fifo_10_bit IS
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(9 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(9 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
END iserdes_fifo_10_bit;
ARCHITECTURE iserdes_fifo_10_bit_a OF iserdes_fifo_10_bit IS
-- synthesis translate_off
component wrapped_iserdes_fifo_10_bit
port (
rst: IN std_logic;
wr_clk: IN std_logic;
rd_clk: IN std_logic;
din: IN std_logic_VECTOR(9 downto 0);
wr_en: IN std_logic;
rd_en: IN std_logic;
dout: OUT std_logic_VECTOR(9 downto 0);
full: OUT std_logic;
empty: OUT std_logic);
end component;
-- Configuration specification
for all : wrapped_iserdes_fifo_10_bit use entity XilinxCoreLib.fifo_generator_v6_2(behavioral)
generic map(
c_has_int_clk => 0,
c_wr_response_latency => 1,
c_rd_freq => 1,
c_has_srst => 0,
c_enable_rst_sync => 1,
c_has_rd_data_count => 0,
c_din_width => 10,
c_has_wr_data_count => 0,
c_full_flags_rst_val => 1,
c_implementation_type => 2,
c_family => "virtex5",
c_use_embedded_reg => 0,
c_has_wr_rst => 0,
c_wr_freq => 1,
c_use_dout_rst => 1,
c_underflow_low => 0,
c_has_meminit_file => 0,
c_has_overflow => 0,
c_preload_latency => 1,
c_dout_width => 10,
c_msgon_val => 1,
c_rd_depth => 16,
c_default_value => "BlankString",
c_mif_file_name => "BlankString",
c_error_injection_type => 0,
c_has_underflow => 0,
c_has_rd_rst => 0,
c_has_almost_full => 0,
c_has_rst => 1,
c_data_count_width => 4,
c_has_wr_ack => 0,
c_use_ecc => 0,
c_wr_ack_low => 0,
c_common_clock => 0,
c_rd_pntr_width => 4,
c_use_fwft_data_count => 0,
c_has_almost_empty => 0,
c_rd_data_count_width => 4,
c_enable_rlocs => 0,
c_wr_pntr_width => 4,
c_overflow_low => 0,
c_prog_empty_type => 0,
c_optimization_mode => 0,
c_wr_data_count_width => 4,
c_preload_regs => 0,
c_dout_rst_val => "0",
c_has_data_count => 0,
c_prog_full_thresh_negate_val => 12,
c_wr_depth => 16,
c_prog_empty_thresh_negate_val => 3,
c_prog_empty_thresh_assert_val => 2,
c_has_valid => 0,
c_init_wr_pntr_val => 0,
c_prog_full_thresh_assert_val => 13,
c_use_fifo16_flags => 0,
c_has_backup => 0,
c_valid_low => 0,
c_prim_fifo_type => "512x36",
c_count_type => 0,
c_prog_full_type => 0,
c_memory_type => 2);
-- synthesis translate_on
BEGIN
-- synthesis translate_off
U0 : wrapped_iserdes_fifo_10_bit
port map (
rst => rst,
wr_clk => wr_clk,
rd_clk => rd_clk,
din => din,
wr_en => wr_en,
rd_en => rd_en,
dout => dout,
full => full,
empty => empty);
-- synthesis translate_on
END iserdes_fifo_10_bit_a;
|
---------------------------------------------------------------------
-- TITLE: Random Access Memory for Xilinx
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 11/06/05
-- FILENAME: ram_xilinx.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements Plasma internal RAM as RAMB for Spartan 3x
--
-- Compile the MIPS C and assembly code into "test.axf".
-- Run convert.exe to change "test.axf" to "code.txt" which
-- will contain the hex values of the opcodes.
-- Next run "ram_image ram_xilinx.vhd code.txt ram_image.vhd",
-- to create the "ram_image.vhd" file that will have the opcodes
-- correctly placed inside the INIT_00 => strings.
-- Then include ram_image.vhd in the simulation/synthesis.
--
-- Warning: Addresses 0x1000 - 0x1FFF are reserved for the cache
-- if the DDR cache is enabled.
---------------------------------------------------------------------
-- UPDATED: 09/07/10 Olivier Rinaudo ([email protected])
-- new behaviour: 8KB expandable to 64KB of internal RAM
--
-- MEMORY MAP
-- 0000..1FFF : 8KB 8KB block0 (upper 4KB used as DDR cache)
-- 2000..3FFF : 8KB 16KB block1
-- 4000..5FFF : 8KB 24KB block2
-- 6000..7FFF : 8KB 32KB block3
-- 8000..9FFF : 8KB 40KB block4
-- A000..BFFF : 8KB 48KB block5
-- C000..DFFF : 8KB 56KB block6
-- E000..FFFF : 8KB 64KB block7
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use work.mlite_pack.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity ram is
generic(memory_type : string := "DEFAULT";
--Number of 8KB blocks of internal RAM, up to 64KB (1 to 8)
block_count : integer := 16);
port(clk : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector( 3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0));
end; --entity ram
architecture logic of ram is
--type
type mem32_vector IS ARRAY (NATURAL RANGE<>) OF std_logic_vector(31 downto 0);
--Which 8KB block
alias block_sel: std_logic_vector(3 downto 0) is address(16 downto 13);
--Address within a 8KB block (without lower two bits)
alias block_addr : std_logic_vector(10 downto 0) is address(12 downto 2);
--Block enable with 1 bit per memory block
signal block_enable: std_logic_vector(15 downto 0);
--Block Data Out
signal block_do: mem32_vector(15 downto 0);
--Remember which block was selected
signal block_sel_buf: std_logic_vector(3 downto 0);
begin
block_enable<= "0000000000000001" when (enable='1') and (block_sel="0000") else
"0000000000000010" when (enable='1') and (block_sel="0001") else
"0000000000000100" when (enable='1') and (block_sel="0010") else
"0000000000001000" when (enable='1') and (block_sel="0011") else
"0000000000010000" when (enable='1') and (block_sel="0100") else
"0000000000100000" when (enable='1') and (block_sel="0101") else
"0000000001000000" when (enable='1') and (block_sel="0110") else
"0000000010000000" when (enable='1') and (block_sel="0111") else
"0000000100000000" when (enable='1') and (block_sel="1000") else
"0000001000000000" when (enable='1') and (block_sel="1001") else
"0000010000000000" when (enable='1') and (block_sel="1010") else
"0000100000000000" when (enable='1') and (block_sel="1011") else
"0001000000000000" when (enable='1') and (block_sel="1100") else
"0010000000000000" when (enable='1') and (block_sel="1101") else
"0100000000000000" when (enable='1') and (block_sel="1110") else
"1000000000000000" when (enable='1') and (block_sel="1111") else
"0000000000000000";
proc_blocksel: process (clk, block_sel) is
begin
if rising_edge(clk) then
block_sel_buf <= block_sel;
end if;
end process;
proc_do: process (block_do, block_sel_buf) is
begin
data_read <= block_do(conv_integer(block_sel_buf));
end process;
-----------------------------------------------------------------------------
--
-- BLOCKS generation
--
-----------------------------------------------------------------------------
block0: if (block_count > 0) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(0)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(0),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
block1: if (block_count > 1) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(1)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(1),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
block2: if (block_count > 2) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(2)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(2),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
block3: if (block_count > 3) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(3)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(3),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
block4: if (block_count > 4) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(4)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(4),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
block5: if (block_count > 5) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(5)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(5),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
block6: if (block_count > 6) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(6)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(6),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
block7: if (block_count > 7) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(7)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(7),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block8: if (block_count > 8) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000c080400",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000d090501",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000e0a0602",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"000000000000000000000000000000000000000000000000000000000f0b0703",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(8)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(8),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block0
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 9)
--
-----------------------------------------------------------------------------
block9: if (block_count > 9) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(9)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(9),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block1
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 10)
--
-----------------------------------------------------------------------------
block10: if (block_count > 10) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(10)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(10),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block2
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 11)
--
-----------------------------------------------------------------------------
block11: if (block_count > 11) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(11)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(11),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block3
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 12)
--
-----------------------------------------------------------------------------
block12: if (block_count > 12) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(12)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(12),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block4
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block13: if (block_count > 13) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(13)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(13),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block5
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 8)
--
-----------------------------------------------------------------------------
block14: if (block_count > 14) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(14)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(14),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block6
-----------------------------------------------------------------------------
--
-- BLOCKS generation (BLOCK 15)
--
-----------------------------------------------------------------------------
block15: if (block_count > 15) generate
begin
ram_byte3 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(31 downto 24),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(31 downto 24),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(3));
ram_byte2 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(23 downto 16),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(23 downto 16),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(2));
ram_byte1 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(15 downto 8),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(15 downto 8),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(1));
ram_byte0 : RAMB16_S9
generic map (
INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_10 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_11 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000"
)
port map (
DO => block_do(15)(7 downto 0),
DOP => open,
ADDR => block_addr,
CLK => clk,
DI => data_write(7 downto 0),
DIP => ZERO(0 downto 0),
EN => block_enable(15),
SSR => ZERO(0),
WE => write_byte_enable(0));
end generate; --block7
end; --architecture logic
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library std;
entity AveragingFilter_slave is
generic (
CLK_PROC_FREQ : integer
);
port (
clk_proc : in std_logic;
reset_n : in std_logic;
---------------- dynamic parameters ports ---------------
status_reg_enable_bit : out std_logic;
widthimg_reg_width : out std_logic_vector(15 downto 0);
--======================= Slaves ========================
------------------------- bus_sl ------------------------
addr_rel_i : in std_logic_vector(3 downto 0);
wr_i : in std_logic;
rd_i : in std_logic;
datawr_i : in std_logic_vector(31 downto 0);
datard_o : out std_logic_vector(31 downto 0)
);
end AveragingFilter_slave;
architecture rtl of AveragingFilter_slave is
-- Registers address
constant STATUS_REG_REG_ADDR : natural := 0;
constant WIDTHIMG_REG_REG_ADDR : natural := 1;
-- Internal registers
signal status_reg_enable_bit_reg : std_logic;
signal widthimg_reg_width_reg : std_logic_vector (15 downto 0);
begin
write_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
status_reg_enable_bit_reg <= '0';
widthimg_reg_width_reg <= "0000000000000000";
elsif(rising_edge(clk_proc)) then
if(wr_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
status_reg_enable_bit_reg <= datawr_i(0);
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
widthimg_reg_width_reg <= datawr_i(15) & datawr_i(14) & datawr_i(13) & datawr_i(12) & datawr_i(11) & datawr_i(10) & datawr_i(9) & datawr_i(8) & datawr_i(7) & datawr_i(6) & datawr_i(5) & datawr_i(4) & datawr_i(3) & datawr_i(2) & datawr_i(1) & datawr_i(0);
when others=>
end case;
end if;
end if;
end process;
read_reg : process (clk_proc, reset_n)
begin
if(reset_n='0') then
datard_o <= (others => '0');
elsif(rising_edge(clk_proc)) then
if(rd_i='1') then
case addr_rel_i is
when std_logic_vector(to_unsigned(STATUS_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000000000000000000" & status_reg_enable_bit_reg;
when std_logic_vector(to_unsigned(WIDTHIMG_REG_REG_ADDR, 4))=>
datard_o <= "0000000000000000" & widthimg_reg_width_reg(15) & widthimg_reg_width_reg(14) & widthimg_reg_width_reg(13) & widthimg_reg_width_reg(12) & widthimg_reg_width_reg(11) & widthimg_reg_width_reg(10) & widthimg_reg_width_reg(9) & widthimg_reg_width_reg(8) & widthimg_reg_width_reg(7) & widthimg_reg_width_reg(6) & widthimg_reg_width_reg(5) & widthimg_reg_width_reg(4) & widthimg_reg_width_reg(3) & widthimg_reg_width_reg(2) & widthimg_reg_width_reg(1) & widthimg_reg_width_reg(0);
when others=>
datard_o <= (others => '0');
end case;
end if;
end if;
end process;
status_reg_enable_bit <= status_reg_enable_bit_reg;
widthimg_reg_width <= widthimg_reg_width_reg;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_tb is
end entity;
architecture beh of test_tb is
signal rx_data : std_logic_vector(159 downto 0);
procedure to_t( signal sa : out std_logic_vector(31 downto 0)) is
begin
sa <= (others => '1');
assert false report "lol";
end procedure;
begin
asd : for i in 0 to 4 generate
begin
process
begin
-- rx_data(32*(i+1)-1 downto 32*i) <= (others => '0');
wait for 10 ns;
to_t(rx_data(32*(i+1)-1 downto 32*i));
wait;
end process;
end generate;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity test_tb is
end entity;
architecture beh of test_tb is
signal rx_data : std_logic_vector(159 downto 0);
procedure to_t( signal sa : out std_logic_vector(31 downto 0)) is
begin
sa <= (others => '1');
assert false report "lol";
end procedure;
begin
asd : for i in 0 to 4 generate
begin
process
begin
-- rx_data(32*(i+1)-1 downto 32*i) <= (others => '0');
wait for 10 ns;
to_t(rx_data(32*(i+1)-1 downto 32*i));
wait;
end process;
end generate;
end architecture;
|
---------------------------------------------------------------
-- Title : Dual Ported IRAM with Wishbone Interface
-- Project : -
---------------------------------------------------------------
-- File : iram_dp_wb.vhd
-- Author : Michael Miehling
-- Email : [email protected]
-- Organization : MEN Mikroelektronik Nuernberg GmbH
-- Created : 28/11/05
---------------------------------------------------------------
-- Simulator : Modelsim PE 5.7g
-- Synthesis : Quartus II 3.0
---------------------------------------------------------------
-- Description :
--
--
---------------------------------------------------------------
-- Hierarchy:
--
--
---------------------------------------------------------------
-- Copyright (C) 2001, MEN Mikroelektronik Nuernberg GmbH
--
-- All rights reserved. Reproduction in whole or part is
-- prohibited without the written permission of the
-- copyright owner.
---------------------------------------------------------------
-- History
---------------------------------------------------------------
-- $Revision: 1.3 $
--
-- $Log: iram_dp_wb.vhd,v $
-- Revision 1.3 2007/11/21 13:46:06 FLenhardt
-- Added ERR output to Wishbone interfaces
--
-- Revision 1.2 2006/01/04 15:57:18 mmiehling
-- added generic usedw_width
--
-- Revision 1.1 2005/12/15 15:38:42 mmiehling
-- Initial Revision
--
--
---------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
library altera_mf;
use altera_mf.altera_mf_components.all;
ENTITY iram_dp_wb IS
GENERIC
(
USEDW_WIDTH : positive := 6; -- width of address vector (6 = one M4K)
SAME_CLK : boolean:= TRUE -- true: sl0_clk = sl1_clk; false: sl0_clk /= sl1_clk
);
PORT
(
rst : IN std_logic; -- global async high active reset
-- Wishbone Bus #0
sl0_clk : IN std_logic; -- Wishbone Bus #0 Clock
sl0_stb : IN std_logic; -- request
sl0_cyc : IN std_logic; -- chip select
sl0_ack : OUT std_logic; -- acknowledge
sl0_err : OUT std_logic; -- error
sl0_we : IN std_logic; -- write=1 read=0
sl0_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
sl0_adr : IN std_logic_vector(31 DOWNTO 0);
sl0_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
sl0_dat_o : OUT std_logic_vector(31 DOWNTO 0); -- data out
-- Wishbone Bus #0
sl1_clk : IN std_logic; -- Wishbone Bus #0 Clock
sl1_stb : IN std_logic; -- request
sl1_cyc : IN std_logic; -- chip select
sl1_ack : OUT std_logic; -- acknowledge
sl1_err : OUT std_logic; -- error
sl1_we : IN std_logic; -- write=1 read=0
sl1_sel : IN std_logic_vector(3 DOWNTO 0); -- byte enables
sl1_adr : IN std_logic_vector(31 DOWNTO 0);
sl1_dat_i : IN std_logic_vector(31 DOWNTO 0); -- data in
sl1_dat_o : OUT std_logic_vector(31 DOWNTO 0) -- data out
);
END iram_dp_wb;
ARCHITECTURE iram_dp_wb_arch OF iram_dp_wb IS
SIGNAL sl0_loc_be : std_logic_vector(3 DOWNTO 0);
SIGNAL sl0_ack_o_int : std_logic;
SIGNAL sl0_clk_int : std_logic;
SIGNAL sl0_write : std_logic;
SIGNAL sl1_loc_be : std_logic_vector(3 DOWNTO 0);
SIGNAL sl1_ack_o_int : std_logic;
SIGNAL sl1_clk_int : std_logic;
SIGNAL sl1_write : std_logic;
BEGIN
-------------------------------------------------------------------------------------------
-- WB #0 Interface
sl0_ack <= sl0_ack_o_int;
sl0_err <= '0';
sl0_write <= '1' WHEN sl0_ack_o_int = '1' AND sl0_we = '1' ELSE '0';
sl0: PROCESS(rst, sl0_clk_int)
BEGIN
IF(rst = '1') THEN
sl0_loc_be <= (OTHERS => '0');
sl0_ack_o_int <= '0';
ELSIF(sl0_clk_int'EVENT AND sl0_clk_int = '1') THEN
IF((sl0_stb = '1' AND sl0_cyc = '1') AND sl0_ack_o_int = '0') THEN
IF(sl0_we = '1') THEN
sl0_loc_be <= sl0_sel;
ELSE
sl0_loc_be <= (OTHERS => '0');
END IF;
sl0_ack_o_int <= '1';
ELSE
sl0_loc_be <= (OTHERS => '0');
sl0_ack_o_int <= '0';
END IF;
END IF;
END PROCESS sl0;
-------------------------------------------------------------------------------------------
-- WB #1 Interface
sl1_ack <= sl1_ack_o_int;
sl1_err <= '0';
sl1_write <= '1' WHEN sl1_ack_o_int = '1' AND sl1_we = '1' ELSE '0';
sl1: PROCESS(rst, sl1_clk_int)
BEGIN
IF(rst = '1') THEN
sl1_loc_be <= (OTHERS => '0');
sl1_ack_o_int <= '0';
ELSIF(sl1_clk_int'EVENT AND sl1_clk_int = '1') THEN
IF((sl1_stb = '1' AND sl1_cyc = '1') AND sl1_ack_o_int = '0') THEN
IF(sl1_we = '1') THEN
sl1_loc_be <= sl1_sel;
ELSE
sl1_loc_be <= (OTHERS => '0');
END IF;
sl1_ack_o_int <= '1';
ELSE
sl1_loc_be <= (OTHERS => '0');
sl1_ack_o_int <= '0';
END IF;
END IF;
END PROCESS sl1;
-------------------------------------------------------------------------------------------
gen_2clk: IF NOT SAME_CLK GENERATE
sl0_clk_int <= sl0_clk;
sl1_clk_int <= sl1_clk;
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
operation_mode => "BIDIR_DUAL_PORT",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
width_b => 32,
widthad_b => USEDW_WIDTH,
numwords_b => 2**USEDW_WIDTH,
lpm_type => "altsyncram",
width_byteena_a => 4,
width_byteena_b => 4,
byte_size => 8,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
outdata_reg_b => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
byteena_aclr_a => "NONE",
indata_reg_b => "CLOCK1",
address_reg_b => "CLOCK1",
wrcontrol_wraddress_reg_b => "CLOCK1",
indata_aclr_b => "NONE",
wrcontrol_aclr_b => "NONE",
address_aclr_b => "NONE",
byteena_reg_b => "CLOCK1",
byteena_aclr_b => "NONE",
outdata_aclr_b => "NONE",
power_up_uninitialized => "FALSE",
init_file => "iram.hex"
)
PORT MAP (
clock0 => sl0_clk,
wren_a => sl0_write,
byteena_a => sl0_loc_be,
address_a => sl0_adr(USEDW_WIDTH+1 DOWNTO 2),
data_a => sl0_dat_i,
q_a => sl0_dat_o,
clock1 => sl1_clk,
wren_b => sl1_write,
byteena_b => sl1_loc_be,
address_b => sl1_adr(USEDW_WIDTH+1 DOWNTO 2),
data_b => sl1_dat_i,
q_b => sl1_dat_o);
END GENERATE gen_2clk;
gen_1clk: IF SAME_CLK GENERATE
sl0_clk_int <= sl0_clk;
sl1_clk_int <= sl0_clk;
altsyncram_component : altsyncram
GENERIC MAP (
intended_device_family => "Cyclone",
ram_block_type => "M4K",
operation_mode => "BIDIR_DUAL_PORT",
width_a => 32,
widthad_a => USEDW_WIDTH,
numwords_a => 2**USEDW_WIDTH,
width_b => 32,
widthad_b => USEDW_WIDTH,
numwords_b => 2**USEDW_WIDTH,
lpm_type => "altsyncram",
width_byteena_a => 4,
width_byteena_b => 4,
byte_size => 8,
outdata_reg_a => "UNREGISTERED",
outdata_aclr_a => "NONE",
outdata_reg_b => "UNREGISTERED",
indata_aclr_a => "NONE",
wrcontrol_aclr_a => "NONE",
address_aclr_a => "NONE",
byteena_aclr_a => "NONE",
indata_reg_b => "CLOCK0",
address_reg_b => "CLOCK0",
wrcontrol_wraddress_reg_b => "CLOCK0",
indata_aclr_b => "NONE",
wrcontrol_aclr_b => "NONE",
address_aclr_b => "NONE",
byteena_reg_b => "CLOCK0",
byteena_aclr_b => "NONE",
outdata_aclr_b => "NONE",
read_during_write_mode_mixed_ports => "OLD_DATA",
power_up_uninitialized => "FALSE",
init_file => "iram.hex")
PORT MAP (
clock0 => sl0_clk,
wren_a => sl0_write,
byteena_a => sl0_loc_be,
address_a => sl0_adr(USEDW_WIDTH+1 DOWNTO 2),
data_a => sl0_dat_i,
q_a => sl0_dat_o,
wren_b => sl1_write,
byteena_b => sl1_loc_be,
address_b => sl1_adr(USEDW_WIDTH+1 DOWNTO 2),
data_b => sl1_dat_i,
q_b => sl1_dat_o);
END GENERATE gen_1clk;
END iram_dp_wb_arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2010.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02010ent IS
END c07s02b02x00p10n01i02010ent;
ARCHITECTURE c07s02b02x00p10n01i02010arch OF c07s02b02x00p10n01i02010ent IS
BEGIN
TESTING: PROCESS
type a1 is array (1 to 5) of integer;
variable a : a1 := (1,2,3,4,5);
variable b : a1 := (2,3,4,5,6);
variable k : integer := 0;
BEGIN
if ((a < b) or (a <= b) or (a > b) or (a >= b)) then
-- No_failure_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p10n01i02010"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p10n01i02010 - Ordering operators are defined only for scalar type or any discrete array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02010arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2010.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02010ent IS
END c07s02b02x00p10n01i02010ent;
ARCHITECTURE c07s02b02x00p10n01i02010arch OF c07s02b02x00p10n01i02010ent IS
BEGIN
TESTING: PROCESS
type a1 is array (1 to 5) of integer;
variable a : a1 := (1,2,3,4,5);
variable b : a1 := (2,3,4,5,6);
variable k : integer := 0;
BEGIN
if ((a < b) or (a <= b) or (a > b) or (a >= b)) then
-- No_failure_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p10n01i02010"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p10n01i02010 - Ordering operators are defined only for scalar type or any discrete array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02010arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2010.vhd,v 1.2 2001-10-26 16:29:45 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b02x00p10n01i02010ent IS
END c07s02b02x00p10n01i02010ent;
ARCHITECTURE c07s02b02x00p10n01i02010arch OF c07s02b02x00p10n01i02010ent IS
BEGIN
TESTING: PROCESS
type a1 is array (1 to 5) of integer;
variable a : a1 := (1,2,3,4,5);
variable b : a1 := (2,3,4,5,6);
variable k : integer := 0;
BEGIN
if ((a < b) or (a <= b) or (a > b) or (a >= b)) then
-- No_failure_here
k := 5;
end if;
assert NOT(k=5)
report "***PASSED TEST: c07s02b02x00p10n01i02010"
severity NOTE;
assert (k=5)
report "***FAILED TEST: c07s02b02x00p10n01i02010 - Ordering operators are defined only for scalar type or any discrete array type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b02x00p10n01i02010arch;
|
-- Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2018.2 (win64) Build 2258646 Thu Jun 14 20:03:12 MDT 2018
-- Date : Mon Sep 16 05:33:33 2019
-- Host : varun-laptop running 64-bit Service Pack 1 (build 7601)
-- Command : write_vhdl -force -mode synth_stub -rename_top decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix -prefix
-- decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix_ design_1_processing_system7_0_2_stub.vhdl
-- Design : design_1_processing_system7_0_2
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z010clg400-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
Port (
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
IRQ_F2P : in STD_LOGIC_VECTOR ( 0 to 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix;
architecture stub of decalper_eb_ot_sdeen_pot_pi_dehcac_xnilix is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "USB0_PORT_INDCTL[1:0],USB0_VBUS_PWRSELECT,USB0_VBUS_PWRFAULT,M_AXI_GP0_ARVALID,M_AXI_GP0_AWVALID,M_AXI_GP0_BREADY,M_AXI_GP0_RREADY,M_AXI_GP0_WLAST,M_AXI_GP0_WVALID,M_AXI_GP0_ARID[11:0],M_AXI_GP0_AWID[11:0],M_AXI_GP0_WID[11:0],M_AXI_GP0_ARBURST[1:0],M_AXI_GP0_ARLOCK[1:0],M_AXI_GP0_ARSIZE[2:0],M_AXI_GP0_AWBURST[1:0],M_AXI_GP0_AWLOCK[1:0],M_AXI_GP0_AWSIZE[2:0],M_AXI_GP0_ARPROT[2:0],M_AXI_GP0_AWPROT[2:0],M_AXI_GP0_ARADDR[31:0],M_AXI_GP0_AWADDR[31:0],M_AXI_GP0_WDATA[31:0],M_AXI_GP0_ARCACHE[3:0],M_AXI_GP0_ARLEN[3:0],M_AXI_GP0_ARQOS[3:0],M_AXI_GP0_AWCACHE[3:0],M_AXI_GP0_AWLEN[3:0],M_AXI_GP0_AWQOS[3:0],M_AXI_GP0_WSTRB[3:0],M_AXI_GP0_ACLK,M_AXI_GP0_ARREADY,M_AXI_GP0_AWREADY,M_AXI_GP0_BVALID,M_AXI_GP0_RLAST,M_AXI_GP0_RVALID,M_AXI_GP0_WREADY,M_AXI_GP0_BID[11:0],M_AXI_GP0_RID[11:0],M_AXI_GP0_BRESP[1:0],M_AXI_GP0_RRESP[1:0],M_AXI_GP0_RDATA[31:0],IRQ_F2P[0:0],FCLK_CLK0,FCLK_RESET0_N,MIO[53:0],DDR_CAS_n,DDR_CKE,DDR_Clk_n,DDR_Clk,DDR_CS_n,DDR_DRSTB,DDR_ODT,DDR_RAS_n,DDR_WEB,DDR_BankAddr[2:0],DDR_Addr[14:0],DDR_VRN,DDR_VRP,DDR_DM[3:0],DDR_DQ[31:0],DDR_DQS_n[3:0],DDR_DQS[3:0],PS_SRSTB,PS_CLK,PS_PORB";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "processing_system7_v5_5_processing_system7,Vivado 2018.2";
begin
end;
|
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_t_e
--
-- Generated
-- by: wig
-- on: Sat Mar 3 17:18:10 2007
-- cmd: /cygdrive/c/Documents and Settings/wig/My Documents/work/MIX/mix_0.pl ../case.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_t_e-rtl-conf-c.vhd,v 1.1 2007/03/05 08:59:00 wig Exp $
-- $Date: 2007/03/05 08:59:00 $
-- $Log: inst_t_e-rtl-conf-c.vhd,v $
-- Revision 1.1 2007/03/05 08:59:00 wig
-- Upgraded testcases
-- case/force still not fully operational (internal names keep case).
--
-- Revision 1.1 2007/03/03 17:24:06 wig
-- Updated testcase for case matches. Added filename serialization.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.101 2007/03/01 16:28:38 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_t_e_rtl_conf / inst_t_e
--
configuration inst_t_e_rtl_conf of inst_t_e is
for rtl
-- Generated Configuration
for inst_A : inst_A_e
use configuration work.inst_A_e_rtl_conf;
end for;
for inst_a : inst_a_e
use configuration work.inst_a_e_rtl_conf;
end for;
for inst_b : inst_b_e
use configuration work.inst_b_e_rtl_conf;
end for;
end for;
end inst_t_e_rtl_conf;
--
-- End of Generated Configuration inst_t_e_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5408)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5408)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 45888)
`protect data_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 45888)
`protect data_block
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SCFW
`protect end_protected
|
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity attr12 is
end entity;
use work.pack.all;
architecture test of attr12 is
begin
process is
begin
proc;
wait;
end process;
end architecture;
|
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity attr12 is
end entity;
use work.pack.all;
architecture test of attr12 is
begin
process is
begin
proc;
wait;
end process;
end architecture;
|
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity attr12 is
end entity;
use work.pack.all;
architecture test of attr12 is
begin
process is
begin
proc;
wait;
end process;
end architecture;
|
package pack is
constant iname : string := pack'instance_name;
procedure proc;
end package;
package body pack is
procedure proc is
begin
report pack'instance_name;
report iname;
end procedure;
end package body;
-------------------------------------------------------------------------------
entity attr12 is
end entity;
use work.pack.all;
architecture test of attr12 is
begin
process is
begin
proc;
wait;
end process;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity spi is
generic
(
SPI_SIZE: integer := 8;
CPOL : std_logic := '0';
CPHA : std_logic := '0'
);
port
(
--AXI BUS
Clk: in std_logic;
Rst: in std_logic;
--CPU baud rate select
ps_val: in std_logic_vector(4 downto 0);
--data to slave
data_to_slave : in std_logic_vector(SPI_SIZE-1 downto 0);
send_req: in std_logic;
--slave to CPU
data_from_slave : out std_logic_vector(SPI_SIZE-1 downto 0);
MISO: in std_logic;
MOSI: out std_logic;
CS: out std_logic;
SCLK: out std_logic
);
end entity;
architecture main of spi is
-- prescale clock pour la comm
component spi_baud is
port
(
--AXI
Clk: in std_logic;
Rst: in std_logic;
--BaudRate
ps_val: in std_logic_vector(4 downto 0);
tick: out std_logic
);
end component;
component spi_send_recv is
generic
(
CPOL : std_logic := '0';
CPHA : std_logic := '0';
SPI_SIZE : integer := 8
);
port
(
-- AXI BUS
Clk : in std_logic;
Rst : in std_logic;
-- SPI
cs_o : out std_logic;
sck_o: out std_logic;
mosi_o : out std_logic;
miso_i : in std_logic;
-- CPU To Slave
send_req_i : in std_logic;
data_i : in std_logic_vector(SPI_SIZE-1 downto 0);
-- Slave To CPU
data_o : out std_logic_vector(SPI_SIZE-1 downto 0);
-- BAUD RATE
tick_i : in std_logic
);
end component;
signal tick_s: std_logic;
begin
SPI_BAUD_GENERATOR: spi_baud
port map ( Clk => Clk,
Rst => Rst,
ps_val => ps_val,
tick => tick_s );
SPI_SEND_REC: spi_send_recv
generic map(
CPOL => CPOL,
CPHA => CPHA,
SPI_SIZE => SPI_SIZE
)
port map (
-- AXI
Clk => Clk,
Rst => Rst,
-- SPI
cs_o => CS,
sck_o => SCLK,
mosi_o => MOSI,
miso_i => MISO,
-- CPU To Slave
send_req_i => send_req,
data_i => data_to_slave,
-- Slave To CPU
data_o => data_from_slave,
-- BAUD RATE
tick_i => tick_s
);
end main;
|
entity static is
generic ( G : integer := 1 );
end entity;
architecture test of static is
begin
process is
subtype byte is bit_vector(7 downto 0);
variable bv : byte;
variable i : integer;
attribute hello : integer;
attribute hello of bv : variable is 6;
begin
case i is
when bv'length => -- OK
null;
when bv'left => -- OK
null;
when byte'right => -- OK
null;
when bv'hello => -- OK
null;
when others =>
null;
end case;
end process;
process is
variable v : bit_vector(3 downto 0);
constant c : bit_vector := "1010";
constant d : bit_vector(G downto 0) := (others => '0');
begin
case v is
when c => -- Error
null;
when others =>
null;
end case;
case v is
when d => -- Error
null;
when others =>
null;
end case;
end process;
end architecture;
-------------------------------------------------------------------------------
entity sub is
generic ( N : integer );
port ( x : bit_vector );
end entity;
architecture test of sub is
signal y : bit_vector(N - 1 downto 0) := (others => '0') ;
begin
sub_i: entity work.sub
generic map ( N => N )
port map (
x => x(x'left downto x'right) ); -- Error
gen1: for i in y'range generate -- OK
end generate;
b1: block is
type r is record
x, y : integer;
end record;
signal x : r := (1, 2);
begin
gen2: if (N, 2) = r'(1, 2) generate -- OK
end generate;
end block;
sub2_i: entity work.sub
generic map ( N => N )
port map (
x(N downto 0) => x ); -- Error
process is
type rec is record
f1, f2 : integer;
end record;
subtype rs is rec; -- OK
constant rc : rs := (0, 0); -- OK
constant i : integer := rc.f1; -- OK
begin
end process;
end architecture;
|
entity vunit5 is
generic ( vunit5 : integer ); -- OK (hides entity)
end entity;
architecture test of vunit5 is
signal x : integer := vunit5; -- OK
begin
end architecture;
|
----------------------------------------------------------------------------------
-- Company: ITESM - CQ
-- Engineer: Me
--
-- Create Date: 09:01:11 10/06/2015
-- Design Name:
-- Module Name: Counter0to19 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description: Simulating an ascending counter
-- 0 to 19
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
entity Counter is
Port ( Clk : in STD_LOGIC;
Rst : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end Counter;
architecture Behavioral of Counter is
-- Embedded Counter
signal Count : STD_LOGIC_VECTOR (3 downto 0);
begin
-- -- Define the ascending counter
-- -- Counts will go from 0 to 9
-- -- Using signals
-- Counter: process(Rst,Clk,Count)
-- begin
-- -- Asynchronous reset
-- if (Rst = '1') then
-- Count <= (others => '0');
-- elsif (rising_edge(Clk)) then
-- -- Check if the counter has reached its
-- -- final value of 9
-- if (Count = "1001") then
-- Count <= (others => '0');
-- else
-- Count <= Count + 1;
-- end if;
-- end if;
-- Q <= Count;
-- end process Counter;
-- Define the ascending counter
-- Counts will go from 0 to 9
-- Using signals and wait
Counter: process
begin
wait until (Clk'event and Clk = '1');
-- Asynchronous reset
if (Rst = '1') then
Count <= (others => '0');
-- Check if the counter has reached its
-- final value of 9
elsif (Count = "1001") then
Count <= (others => '0');
else
Count <= Count + 1;
end if;
Q <= Count;
end process Counter;
end Behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Package: sim
-- File: sim.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: Simulation models and functions declarations
------------------------------------------------------------------------------
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.amba.all;
use grlib.devices.all;
library gaisler;
package sim is
component sram
generic (index : integer := 0; -- Byte lane (0 - 3)
Abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- Clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
D : inout std_logic_vector(7 downto 0);
CE1 : in std_logic;
WE : in std_logic;
OE : in std_logic);
end component;
component sram16
generic (
index : integer := 0; -- Byte lane (0 - 3)
abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
echk : integer := 0; -- Generate EDAC checksum
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"; -- File to read from
clear : integer := 0); -- Clear memory
port (
a : in std_logic_vector(abits-1 downto 0);
d : inout std_logic_vector(15 downto 0);
lb : in std_logic;
ub : in std_logic;
ce : in std_logic;
we : in std_ulogic;
oe : in std_ulogic);
end component;
component sramft
generic (index : integer := 0; -- Byte lane (0 - 3)
Abits: Positive := 10; -- Default 10 address bits (1 Kbyte)
tacc : integer := 10; -- access time (ns)
fname : string := "ram.dat"); -- File to read from
port (
a : in std_logic_vector(abits-1 downto 0);
D : inout std_logic_vector(7 downto 0);
CE1 : in std_logic;
WE : in std_logic;
OE : in std_logic);
end component;
function buskeep(signal v : in std_logic_vector) return std_logic_vector;
function buskeep(signal c : in std_logic) return std_logic;
component phy is
generic(
address : integer range 0 to 31 := 0;
extended_regs : integer range 0 to 1 := 1;
aneg : integer range 0 to 1 := 1;
base100_t4 : integer range 0 to 1 := 0;
base100_x_fd : integer range 0 to 1 := 1;
base100_x_hd : integer range 0 to 1 := 1;
fd_10 : integer range 0 to 1 := 1;
hd_10 : integer range 0 to 1 := 1;
base100_t2_fd : integer range 0 to 1 := 1;
base100_t2_hd : integer range 0 to 1 := 1;
base1000_x_fd : integer range 0 to 1 := 0;
base1000_x_hd : integer range 0 to 1 := 0;
base1000_t_fd : integer range 0 to 1 := 1;
base1000_t_hd : integer range 0 to 1 := 1;
rmii : integer range 0 to 1 := 0;
rgmii : integer range 0 to 1 := 0
);
port(
rstn : in std_logic;
mdio : inout std_logic;
tx_clk : out std_logic;
rx_clk : out std_logic;
rxd : out std_logic_vector(7 downto 0);
rx_dv : out std_logic;
rx_er : out std_logic;
rx_col : out std_logic;
rx_crs : out std_logic;
txd : in std_logic_vector(7 downto 0);
tx_en : in std_logic;
tx_er : in std_logic;
mdc : in std_logic;
gtx_clk : in std_logic
);
end component;
component phy_sgmii is
generic (
INSTANCE_NUMBER : integer := 0
);
port (
-- Physical Interface (Transceiver)
--------------------------------
txp : in std_logic;
txn : in std_logic;
rxp : out std_logic;
rxn : out std_logic;
-- GMII Interface
-----------------
gmii_tx_clk : out std_logic;
gmii_rx_clk : in std_logic;
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
-- Test bench speed selection
-----------------------------
speed_is_10_100 : in std_logic;
speed_is_100 : in std_logic;
-- Test Bench Semaphores
------------------------
configuration_finished : in boolean;
tx_monitor_finished : out boolean;
rx_monitor_finished : out boolean
);
end component;
procedure leon3_subtest(subtest : integer);
procedure mctrl_subtest(subtest : integer);
procedure gptimer_subtest(subtest : integer);
procedure dsu3_subtest(subtest : integer);
procedure spw_subtest(subtest : integer);
procedure spictrl_subtest(subtest : integer);
procedure i2cmst_subtest(subtest : integer);
procedure uhc_subtest(subtest : integer);
procedure ehc_subtest(subtest : integer);
procedure irqmp_subtest(subtest : integer);
procedure spimctrl_subtest(subtest : integer);
procedure svgactrl_subtest(subtest : integer);
procedure apbps2_subtest(subtest : integer);
procedure i2cslv_subtest(subtest : integer);
procedure grpwm_subtest(subtest : integer);
procedure grgpio_subtest(subtest : integer);
procedure griommu_subtest(subtest : integer);
procedure l4stat_subtest(subtest : integer);
procedure call_subtest(vendorid, deviceid, subtest : integer);
component ahbrep
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
halt : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end component;
component i2c_slave_model
port (
scl : inout std_logic;
sda : inout std_logic
);
end component;
component grusbdcsim
generic (
functm : integer range 0 to 1 := 0;
keepclk : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : out std_ulogic;
d : inout std_logic_vector(7 downto 0);
nxt : out std_ulogic;
stp : in std_ulogic;
dir : out std_ulogic
);
end component;
type grusb_dcl_debug_data is array (0 to 503) of std_logic_vector(7 downto 0);
component grusb_dclsim
generic (
functm : integer range 0 to 1 := 0;
keepclk : integer range 0 to 1 := 0);
port (
rst : in std_ulogic;
clk : out std_ulogic;
d : inout std_logic_vector(7 downto 0);
nxt : out std_ulogic;
stp : in std_ulogic;
dir : out std_ulogic;
delay : in std_ulogic := '0';
dstart : in std_ulogic;
drw : in std_ulogic;
daddr : in std_logic_vector(31 downto 0);
dlen : in std_logic_vector(14 downto 0);
ddi : in grusb_dcl_debug_data;
ddone : out std_ulogic;
ddo : out grusb_dcl_debug_data;
start : in std_ulogic := '1');
end component;
component ulpi
generic (
LSDEV : boolean := false -- Low-Speed device attached
);
port (
clkout : out std_ulogic;
d : inout std_logic_vector(7 downto 0);
nxt : out std_ulogic;
stp : in std_ulogic;
dir : out std_ulogic;
resetn : in std_ulogic
);
end component;
component utmi
generic (
LSDEV : boolean := false; -- Low-Speed device attached
utmi_dw8 : integer -- Interface data width
);
port (
uclk : out std_ulogic;
xcvrsel : in std_logic_vector(1 downto 0);
termsel : in std_ulogic;
suspendm : in std_ulogic;
opmode : in std_logic_vector(1 downto 0);
txvalid : in std_ulogic;
drvvbus : in std_ulogic;
validho : in std_ulogic;
host : in std_ulogic;
utm_rst : in std_ulogic;
linestate : out std_logic_vector(1 downto 0);
txready : out std_ulogic;
rxvalid : out std_ulogic;
rxactive : out std_ulogic;
rxerror : out std_ulogic;
vbusvalid : out std_ulogic;
validhi : out std_ulogic;
hostdisc : out std_ulogic;
datah : inout std_logic_vector(7 downto 0);
data : inout std_logic_vector(7 downto 0)
);
end component;
component delay_wire
generic(
data_width : integer := 1;
delay_atob : real := 0.0;
delay_btoa : real := 0.0
);
port(
a : inout std_logic_vector(data_width-1 downto 0);
b : inout std_logic_vector(data_width-1 downto 0);
x : in std_logic_vector(data_width-1 downto 0) := (others => '0')
);
end component;
component spi_flash
generic (
ftype : integer := 0; -- Flash type
debug : integer := 0; -- Debug output
fname : string := "prom.srec"; -- File to read from
readcmd : integer := 16#0B#; -- SPI memory device read command
dummybyte : integer := 1;
dualoutput : integer := 0;
memoffset : integer := 0);
port (
sck : in std_ulogic;
di : inout std_logic;
do : inout std_logic;
csn : inout std_logic;
-- Test control inputs
sd_cmd_timeout : in std_ulogic := '0';
sd_data_timeout : in std_ulogic := '0'
);
end component;
component pwm_check
port (
clk : in std_ulogic;
address : in std_logic_vector(21 downto 2);
data : inout std_logic_vector(31 downto 0);
iosn : in std_ulogic;
oen : in std_ulogic;
writen : in std_ulogic;
pwm : in std_logic_vector(15 downto 0)
);
end component;
type ramback_in_type is record
-- Data access
addr: std_logic_vector(31 downto 0);
wr: std_logic_vector(15 downto 0);
din: std_logic_vector(127 downto 0);
-- Command strobes
clear,reload,dbgdump: std_logic;
end record;
constant ramback_in_none: ramback_in_type :=
((others => '0'), (others => '0'), (others => '0'), '0', '0', '0');
type ramback_out_type is record
addr: std_logic_vector(31 downto 0);
dout: std_logic_vector(127 downto 0);
cmdack: std_logic;
end record;
constant ramback_out_none: ramback_out_type := ((others => '0'), (others => '0'), '0');
type ramback_in_array is array(natural range <>) of ramback_in_type;
type ramback_out_array is array(natural range <>) of ramback_out_type;
component ramback
generic (
abits: integer := 16;
dbits: integer := 32;
fname: string := "dummy";
autoload: integer := 0;
pagesize: integer := 4096;
listsize: integer := 128;
rstmode: integer := 0;
rstdatah: integer := 16#DEAD#;
rstdatal: integer := 16#BEEF#;
nports: integer := 4
);
port (
bein: in ramback_in_array(1 to nports);
beout: out ramback_out_array(1 to nports)
);
end component;
component zbtssram is
generic (
nohold: integer := 1;
flowthru: integer := 0;
dbits: integer := 32
);
port (
-- SSRAM signals
clk: in std_logic;
a: in std_logic_vector(20 downto 0);
bwn: in std_logic_vector(dbits/8-1 downto 0);
wen: in std_logic;
advld: in std_logic;
ce1n: in std_logic;
ce2: in std_logic;
ce3n: in std_logic;
oen: in std_logic;
cen: in std_logic;
zz: inout std_logic;
dq: inout std_logic_vector(dbits-1 downto 0);
mode: in std_logic;
-- Backend interface
be_addr: out std_logic_vector(20 downto 0);
be_rdd : in std_logic_vector(dbits-1 downto 0);
be_wr : out std_logic_vector(dbits/8-1 downto 0);
be_wrd : out std_logic_vector(dbits-1 downto 0)
);
end component;
component slavecheck is
generic (
hindex: integer := 0;
hbar: integer := 0;
ahbbits: integer := 32;
fname: string;
autoload: integer := 0
);
port (
rst: in std_logic;
clk: in std_logic;
ahbsi: in ahb_slv_in_type;
ahbso: in ahb_slv_out_type
);
end component;
component spwtrace is
generic (name: string );
port (d,s: in std_ulogic);
end component;
component spwtracev is
generic (
width: integer := 8;
prefix: string := "SPW#";
lono: integer := 0
);
port (d,s: in std_logic_vector(width-1 downto 0));
end component;
procedure ps2_device (
signal clk : inout std_logic;
signal data : inout std_logic;
-- Configuration
constant DELAY : in time := 40 us
);
procedure grusb_dcl_read (
signal clk : in std_ulogic;
signal rw : out std_ulogic;
signal start : out std_ulogic;
signal done : in std_ulogic
);
procedure grusb_dcl_write (
signal clk : in std_ulogic;
signal rw : out std_ulogic;
signal start : out std_ulogic;
signal done : in std_ulogic
);
end;
package body sim is
-----------------------------------------------------------------------------
-- Helper functions
-----------------------------------------------------------------------------
function to_xlhz(i : std_logic) return std_logic is
begin
case to_X01Z(i) is
when 'Z' => return('Z');
when '0' => return('L');
when '1' => return('H');
when others => return('X');
end case;
end;
type logic_xlhz_table IS ARRAY (std_logic'LOW TO std_logic'HIGH) OF std_logic;
constant cvt_to_xlhz : logic_xlhz_table := (
'Z', -- 'U'
'Z', -- 'X'
'L', -- '0'
'H', -- '1'
'Z', -- 'Z'
'Z', -- 'W'
'L', -- 'L'
'H', -- 'H'
'Z' -- '-'
);
function buskeep (signal v : in std_logic_vector) return std_logic_vector is
variable res : std_logic_vector(v'range);
begin
for i in v'range loop res(i) := cvt_to_xlhz(v(i)); end loop;
return(res);
end;
function buskeep (signal c : in std_logic) return std_logic is
begin
return(cvt_to_xlhz(c));
end;
-----------------------------------------------------------------------------
-- Subtest print out
-----------------------------------------------------------------------------
procedure gptimer_subtest(subtest : integer) is
begin
case subtest is
when 0 | 1 | 2 | 3 | 4 | 5 | 6 => print(" timer " & tost(subtest+1));
when 8 => print(" chain mode");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure leon3_subtest(subtest : integer) is
begin
case (subtest mod 16) is
when 3 => print(" CPU#" & (tost(subtest/16)) & " register file");
when 4 => print(" CPU#" & (tost(subtest/16)) & " multiplier");
when 5 => print(" CPU#" & (tost(subtest/16)) & " radix-2 divider");
when 6 => print(" CPU#" & (tost(subtest/16)) & " cache system");
when 7 => print(" CPU#" & (tost(subtest/16)) & " multi-processing");
when 8 => print(" CPU#" & (tost(subtest/16)) & " floating-point unit");
when 9 => print(" CPU#" & (tost(subtest/16)) & " itag cache ram");
when 10 => print(" CPU#" & (tost(subtest/16)) & " dtag cache ram");
when 11 => print(" CPU#" & (tost(subtest/16)) & " idata cache ram");
when 12 => print(" CPU#" & (tost(subtest/16)) & " ddata cache ram");
when 13 => print(" CPU#" & (tost(subtest/16)) & " GRFPU test");
when 14 => print(" CPU#" & (tost(subtest/16)) & " memory management unit");
when 15 => print(" CPU#" & (tost(subtest/16)) & " CASA");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure mctrl_subtest(subtest : integer) is
begin
case subtest is
when 3 => print(" sub-word write");
when 4 => print(" EDAC");
when 5 => print(" write protection");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure dsu3_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" AHB trace buffer memory (0x55555555)");
when 2 => print(" AHB trace buffer memory (0xAAAAAAAA)");
when 3 => print(" AHB trace buffer addressing");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure spw_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Nominal operation, snooping enabled");
when 2 => print(" Nominal operation, snooping disabled");
when 3 => print(" RMAP packet reception");
when 4 => print(" Time functionality");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure spictrl_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" APB interface reset values");
when 2 => print(" Loopback mode");
when 3 => print(" AM Loopback mode");
when 4 => print(" External device test");
when 5 => print(" Interrupt line test");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure i2cmst_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" APB interface reset values");
when 2 => print(" Data transfer");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure uhc_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" I/O register reset values");
when 2 => print(" Host Controller Reset");
when 3 => print(" Isochronous IN and OUT");
when 4 => print(" Control OUT, Bulk IN");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure ehc_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Register reset values");
when 2 => print(" Host Controller Reset");
when 3 => print(" Periodic schedule");
when 4 => print(" Asynchronous schedule");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure irqmp_subtest(subtest : integer) is
begin
case subtest is
when 0 to 15 => print(" Testing internal controller " & tost(subtest));
when 16 => print(" Testing timestamping using GPIO port");
when 17 => print(" Testing watchdog functionality");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure spimctrl_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Initial values");
when 2 => print(" User mode transfer");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure svgactrl_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Check available clocks");
when 2 => print(" Draw screen");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure apbps2_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Transmit test");
when 2 => print(" Receive test");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure i2cslv_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Register interface");
when 2 => print(" Combined I2CMST/I2CSLV test");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure grpwm_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Asymmetric PWM test");
when 2 => print(" Symmetric PWM test");
when 3 => print(" Waveform PWM test (asymmetric)");
when 4 => print(" Waveform PWM test (symmetric)");
when others =>
-- 247 - 255 if used for configuring pwm_check
if subtest < 247 then
print(" sub-system test " & tost(subtest));
end if;
end case;
end;
procedure grgpio_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" IN, OUT and DIR registers");
when 2 => print(" Interrupt generation");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure griommu_subtest(subtest : integer) is
begin
case subtest is
when 1 => print(" Register interface");
when 2 => print(" Cache flush");
when 3 => print(" Diagnostic cache accesses");
when 4 => print(" Fault tolerance");
when others => print(" sub-system test " & tost(subtest));
end case;
end;
procedure l4stat_subtest(subtest : integer) is
begin
print(" testing counter " & tost(subtest));
end;
procedure call_subtest(vendorid, deviceid, subtest : integer) is
begin
if vendorid = VENDOR_GAISLER then
case deviceid is
when GAISLER_LEON3 | GAISLER_LEON4 | GAISLER_L2CACHE=> leon3_subtest(subtest);
when GAISLER_FTMCTRL => mctrl_subtest(subtest);
when GAISLER_GPTIMER => gptimer_subtest(subtest);
when GAISLER_LEON3DSU => dsu3_subtest(subtest);
when GAISLER_SPW => spw_subtest(subtest);
when GAISLER_SPICTRL => spictrl_subtest(subtest);
when GAISLER_I2CMST => i2cmst_subtest(subtest);
when GAISLER_UHCI => uhc_subtest(subtest);
when GAISLER_EHCI => ehc_subtest(subtest);
when GAISLER_IRQMP => irqmp_subtest(subtest);
when GAISLER_SPIMCTRL => spimctrl_subtest(subtest);
when GAISLER_SVGACTRL => svgactrl_subtest(subtest);
when GAISLER_APBPS2 => apbps2_subtest(subtest);
when GAISLER_I2CSLV => i2cslv_subtest(subtest);
when GAISLER_PWM => grpwm_subtest(subtest);
when GAISLER_GPIO => grgpio_subtest(subtest);
when GAISLER_GRIOMMU => griommu_subtest(subtest);
when GAISLER_L4STAT => l4stat_subtest(subtest);
when others =>
print (" subtest " & tost(subtest));
end case;
elsif vendorid = VENDOR_ESA then
case deviceid is
when ESA_LEON2 => leon3_subtest(subtest);
when ESA_MCTRL => mctrl_subtest(subtest);
when ESA_TIMER => gptimer_subtest(subtest);
when others =>
print ("subtest " & tost(subtest));
end case;
else
print ("subtest " & tost(subtest));
end if;
end;
-----------------------------------------------------------------------------
-- Simple simulation models
-----------------------------------------------------------------------------
-- Description: Simple "PS/2" device. When the device receives the data
-- 0xAA it will respond with the bytes 0x5A, 0xA5.
-- The argument DELAY is the PS/2 clock period / 2
procedure ps2_device (
signal clk : inout std_logic;
signal data : inout std_logic;
-- Configuration
constant DELAY : in time := 40 us) is
variable d : std_logic_vector(9 downto 0);
begin -- ps2_device
clk <= 'Z'; data <= 'Z';
loop
-- Wait for host request-to-send
wait until clk = '0';
wait until data = '0';
wait until clk /= '0';
wait for DELAY;
-- Generate clock and shift in data
for i in 0 to 9 loop
wait for DELAY/2;
clk <= '0';
wait for DELAY;
clk <= 'Z';
d(i) := data;
wait for DELAY/2;
end loop; -- i = 0
-- Acknowledge data
data <= '0';
wait for DELAY/2;
clk <= '0';
wait for DELAY;
clk <= 'Z'; data <= 'Z';
-- Check parity
assert xorv(d(7 downto 0)) /= d(8)
report "Wrong parity on PS/2 bus" severity warning;
-- Continue if data is not 0xAA
if d(7 downto 0) /= conv_std_logic_vector(16#AA#, 8) then next; end if;
wait for 2*DELAY;
-- Transmit two byte response
d(8) := '1'; d(7 downto 0) := conv_std_logic_vector(16#A5#, 8);
for i in 0 to 1 loop
d(7 downto 0) := d(3 downto 0) & d(7 downto 4);
data <= '0'; clk <= '0';
wait for DELAY;
clk <= 'Z';
for j in 0 to 8 loop
wait for DELAY/2;
data <= d(j);
wait for DELAY/2;
clk <= '0';
wait for DELAY;
clk <= 'Z';
end loop; -- j
-- Stop bit
wait for DELAY/2;
data <= 'Z';
wait for DELAY/2;
clk <= '0';
wait for DELAY;
clk <= 'Z';
-- Insert delay between transmissions
if i = 0 then wait for 2*DELAY; end if;
end loop; -- i
end loop;
end ps2_device;
procedure grusb_dcl_read (
signal clk : in std_ulogic;
signal rw : out std_ulogic;
signal start : out std_ulogic;
signal done : in std_ulogic) is
begin
rw <= '0';
wait until rising_edge(clk);
start <= '1';
wait until rising_edge(done);
start <= '0';
wait until falling_edge(done);
end grusb_dcl_read;
procedure grusb_dcl_write (
signal clk : in std_ulogic;
signal rw : out std_ulogic;
signal start : out std_ulogic;
signal done : in std_ulogic) is
begin
rw <= '1';
wait until rising_edge(clk);
start <= '1';
wait until rising_edge(done);
start <= '0';
wait until falling_edge(done);
end grusb_dcl_write;
end;
-- pragma translate_on
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- Uncomment the following lines to use the declarations that are
-- provided for instantiating Xilinx primitive components.
--library UNISIM;
--use UNISIM.VComponents.all;
entity segment is
Port
(
clock : in std_logic;
selector : out std_logic_vector( 2 downto 0 );
segment_data : out std_logic_vector( 7 downto 0 )
);
end segment;
architecture Behavioral of segment is
signal number:std_logic_vector( 3 downto 0 ); -- decimal 0 to 15
signal count:std_logic_vector( 15 downto 0 );
begin
process( clock ) begin
if clock'event and clock = '1' then
count <= count + 1;
if count = 0 then
if number = 0 then
selector <= "000";
elsif number = 1 then
selector <= "001";
elsif number = 2 then
selector <= "010";
elsif number = 3 then
selector <= "011";
elsif number = 4 then
selector <= "100";
elsif number = 5 then
selector <= "101";------------
elsif number = 6 then
selector <= "000";
elsif number = 7 then
selector <= "001";
elsif number = 8 then
selector <= "010";
elsif number = 9 then
selector <= "011";
elsif number = 10 then
selector <= "100";
elsif number = 11 then
selector <= "101";-------
elsif number = 12 then
selector <= "000";
elsif number = 13 then
selector <= "001";
elsif number = 14 then
selector <= "010";
elsif number = 15 then
selector <= "011";
end if;
number <= number + 1;
end if;
end if;
end process;
segment_data <=
"01000000" when number = 0 else --0
"01111001" when number = 1 else --1
"00100100" when number = 2 else --2
"00110000" when number = 3 else --3
"00011001" when number = 4 else --4
"00010010" when number = 5 else --5
"00000010" when number = 6 else --6
"01111000" when number = 7 else --7
"00000000" when number = 8 else --8
"00010000" when number = 9 else --9
"00001000" when number = 10 else --A
"00000011" when number = 11 else --B
"01000110" when number = 12 else --C
"00100001" when number = 13 else --D
"00000110" when number = 14 else --E
"00001110"; --F
end Behavioral;
|
--
-- 65xx compatible microprocessor core
--
-- Version : 0246
--
-- Copyright (c) 2002 Daniel Wallner ([email protected])
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author, but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- The latest version of this file can be found at:
-- http://www.opencores.org/cvsweb.shtml/t65/
--
-- Limitations :
--
-- 65C02 and 65C816 modes are incomplete
-- Undocumented instructions are not supported
-- Some interface signals behaves incorrect
--
-- File history :
--
-- 0246 : First release
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.T65_Pack.all;
entity T65 is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65C816
Res_n : in std_logic;
Clk : in std_logic;
Rdy : in std_logic;
Abort_n : in std_logic;
IRQ_n : in std_logic;
NMI_n : in std_logic;
SO_n : in std_logic;
R_W_n : out std_logic;
Sync : out std_logic;
EF : out std_logic;
MF : out std_logic;
XF : out std_logic;
ML_n : out std_logic;
VP_n : out std_logic;
VDA : out std_logic;
VPA : out std_logic;
A : out std_logic_vector(23 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0)
);
end T65;
architecture rtl of T65 is
-- Registers
signal ABC, X, Y, D : std_logic_vector(15 downto 0);
signal P, AD, DL : std_logic_vector(7 downto 0);
signal BAH : std_logic_vector(7 downto 0);
signal BAL : std_logic_vector(8 downto 0);
signal PBR : std_logic_vector(7 downto 0);
signal DBR : std_logic_vector(7 downto 0);
signal PC : unsigned(15 downto 0);
signal S : unsigned(15 downto 0);
signal EF_i : std_logic;
signal MF_i : std_logic;
signal XF_i : std_logic;
signal IR : std_logic_vector(7 downto 0);
signal MCycle : std_logic_vector(2 downto 0);
signal Mode_r : std_logic_vector(1 downto 0);
signal ALU_Op_r : std_logic_vector(3 downto 0);
signal Write_Data_r : std_logic_vector(2 downto 0);
signal Set_Addr_To_r : std_logic_vector(1 downto 0);
signal PCAdder : unsigned(8 downto 0);
signal RstCycle : std_logic;
signal IRQCycle : std_logic;
signal NMICycle : std_logic;
signal B_o : std_logic;
signal SO_n_o : std_logic;
signal IRQ_n_o : std_logic;
signal NMI_n_o : std_logic;
signal NMIAct : std_logic;
signal Break : std_logic;
-- ALU signals
signal BusA : std_logic_vector(7 downto 0);
signal BusA_r : std_logic_vector(7 downto 0);
signal BusB : std_logic_vector(7 downto 0);
signal ALU_Q : std_logic_vector(7 downto 0);
signal P_Out : std_logic_vector(7 downto 0);
-- Micro code outputs
signal LCycle : std_logic_vector(2 downto 0);
signal ALU_Op : std_logic_vector(3 downto 0);
signal Set_BusA_To : std_logic_vector(2 downto 0);
signal Set_Addr_To : std_logic_vector(1 downto 0);
signal Write_Data : std_logic_vector(2 downto 0);
signal Jump : std_logic_vector(1 downto 0);
signal BAAdd : std_logic_vector(1 downto 0);
signal BreakAtNA : std_logic;
signal ADAdd : std_logic;
signal PCAdd : std_logic;
signal Inc_S : std_logic;
signal Dec_S : std_logic;
signal LDA : std_logic;
signal LDP : std_logic;
signal LDX : std_logic;
signal LDY : std_logic;
signal LDS : std_logic;
signal LDDI : std_logic;
signal LDALU : std_logic;
signal LDAD : std_logic;
signal LDBAL : std_logic;
signal LDBAH : std_logic;
signal SaveP : std_logic;
signal Write : std_logic;
begin
Sync <= '1' when MCycle = "000" else '0';
EF <= EF_i;
MF <= MF_i;
XF <= XF_i;
ML_n <= '0' when IR(7 downto 6) /= "10" and IR(2 downto 1) = "11" and MCycle(2 downto 1) /= "00" else '1';
VP_n <= '0' when IRQCycle = '1' and (MCycle = "101" or MCycle = "110") else '1';
VDA <= '1' when Set_Addr_To_r /= "000" else '0'; -- Incorrect !!!!!!!!!!!!
VPA <= '1' when Jump(1) = '0' else '0'; -- Incorrect !!!!!!!!!!!!
mcode : T65_MCode
port map(
Mode => Mode_r,
IR => IR,
MCycle => MCycle,
P => P,
LCycle => LCycle,
ALU_Op => ALU_Op,
Set_BusA_To => Set_BusA_To,
Set_Addr_To => Set_Addr_To,
Write_Data => Write_Data,
Jump => Jump,
BAAdd => BAAdd,
BreakAtNA => BreakAtNA,
ADAdd => ADAdd,
PCAdd => PCAdd,
Inc_S => Inc_S,
Dec_S => Dec_S,
LDA => LDA,
LDP => LDP,
LDX => LDX,
LDY => LDY,
LDS => LDS,
LDDI => LDDI,
LDALU => LDALU,
LDAD => LDAD,
LDBAL => LDBAL,
LDBAH => LDBAH,
SaveP => SaveP,
Write => Write);
alu : T65_ALU
port map(
Mode => Mode_r,
Op => ALU_Op_r,
BusA => BusA_r,
BusB => BusB,
P_In => P,
P_Out => P_Out,
Q => ALU_Q);
process (Res_n, Clk)
begin
if Res_n = '0' then
PC <= (others => '0'); -- Program Counter
IR <= "00000000";
S <= (others => '0'); -- Dummy !!!!!!!!!!!!!!!!!!!!!
D <= (others => '0');
PBR <= (others => '0');
DBR <= (others => '0');
Mode_r <= (others => '0');
ALU_Op_r <= "1100";
Write_Data_r <= "000";
Set_Addr_To_r <= "00";
R_W_n <= '1';
EF_i <= '1';
MF_i <= '1';
XF_i <= '1';
elsif Clk'event and Clk = '1' then
if Rdy = '1' then
R_W_n <= not Write or RstCycle;
D <= (others => '1'); -- Dummy
PBR <= (others => '1'); -- Dummy
DBR <= (others => '1'); -- Dummy
EF_i <= '0'; -- Dummy
MF_i <= '0'; -- Dummy
XF_i <= '0'; -- Dummy
if MCycle = "000" then
Mode_r <= Mode;
if IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
if IRQCycle = '1' or NMICycle = '1' then
IR <= "00000000";
else
IR <= DI;
end if;
end if;
ALU_Op_r <= ALU_Op;
Write_Data_r <= Write_Data;
if Break = '1' then
Set_Addr_To_r <= "00";
else
Set_Addr_To_r <= Set_Addr_To;
end if;
if Inc_S = '1' then
S <= S + 1;
end if;
if Dec_S = '1' and RstCycle = '0' then
S <= S - 1;
end if;
if LDS = '1' then
S(7 downto 0) <= unsigned(ALU_Q);
end if;
if IR = "00000000" and MCycle = "001" and IRQCycle = '0' and NMICycle = '0' then
PC <= PC + 1;
end if;
case Jump is
when "01" =>
PC <= PC + 1;
when "10" =>
PC <= unsigned(DI & DL);
when "11" =>
if PCAdder(8) = '1' then
if DL(7) = '0' then
PC(15 downto 8) <= PC(15 downto 8) + 1;
else
PC(15 downto 8) <= PC(15 downto 8) - 1;
end if;
end if;
PC(7 downto 0) <= PCAdder(7 downto 0);
when others =>
end case;
end if;
end if;
end process;
process (Clk)
begin
if Clk'event and Clk = '1' then
if Rdy = '1' then
if MCycle = "000" then
if LDA = '1' then
ABC(7 downto 0) <= ALU_Q;
end if;
if LDX = '1' then
X(7 downto 0) <= ALU_Q;
end if;
if LDY = '1' then
Y(7 downto 0) <= ALU_Q;
end if;
if (LDA or LDX or LDY) = '1' then
P <= P_Out;
end if;
end if;
if SaveP = '1' then
P <= P_Out;
end if;
if LDP = '1' then
P <= ALU_Q;
end if;
if IR(4 downto 0) = "11000" then
case IR(7 downto 5) is
when "000" =>
P(Flag_C) <= '0';
when "001" =>
P(Flag_C) <= '1';
when "010" =>
P(Flag_I) <= '0';
when "011" =>
P(Flag_I) <= '1';
when "101" =>
P(Flag_V) <= '0';
when "110" =>
P(Flag_D) <= '0';
when "111" =>
P(Flag_D) <= '1';
when others =>
end case;
end if;
if IR = "00000000" and MCycle = "011" and RstCycle = '0' and NMICycle = '0' then
P(Flag_B) <= '1';
end if;
if IR = "00000000" and MCycle = "100" and RstCycle = '0' and NMICycle = '0' then
P(Flag_I) <= '1';
P(Flag_B) <= B_o;
end if;
if SO_n_o = '1' and SO_n = '0' then
P(Flag_V) <= '1';
end if;
if RstCycle = '1' and Mode_r /= "00" then
P(Flag_1) <= '1';
P(Flag_D) <= '0';
P(Flag_I) <= '1';
end if;
P(Flag_1) <= '1';
B_o <= P(Flag_B);
SO_n_o <= SO_n;
IRQ_n_o <= IRQ_n;
NMI_n_o <= NMI_n;
end if;
end if;
end process;
---------------------------------------------------------------------------
--
-- Buses
--
---------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
BusA_r <= (others => '0');
BusB <= (others => '0');
AD <= (others => '0');
BAL <= (others => '0');
BAH <= (others => '0');
DL <= (others => '0');
elsif Clk'event and Clk = '1' then
if Rdy = '1' then
BusA_r <= BusA;
BusB <= DI;
case BAAdd is
when "01" =>
-- BA Inc
AD <= std_logic_vector(unsigned(AD) + 1);
BAL <= std_logic_vector(unsigned(BAL) + 1);
when "10" =>
-- BA Add
BAL <= std_logic_vector(resize(unsigned(BAL(7 downto 0)),9) + resize(unsigned(BusA),9));
when "11" =>
-- BA Adj
if BAL(8) = '1' then
BAH <= std_logic_vector(unsigned(BAH) + 1);
end if;
when others =>
end case;
if ADAdd = '1' then
AD <= std_logic_vector(unsigned(AD) + unsigned(X(7 downto 0)));
end if;
if IR = "00000000" then
BAL <= (others => '1');
BAH <= (others => '1');
if RstCycle = '1' then
BAL(2 downto 0) <= "100";
elsif NMICycle = '1' then
BAL(2 downto 0) <= "010";
else
BAL(2 downto 0) <= "110";
end if;
if Set_addr_To_r = "11" then
BAL(0) <= '1';
end if;
end if;
if LDDI = '1' then
DL <= DI;
end if;
if LDALU = '1' then
DL <= ALU_Q;
end if;
if LDAD = '1' then
AD <= DI;
end if;
if LDBAL = '1' then
BAL(7 downto 0) <= DI;
end if;
if LDBAH = '1' then
BAH <= DI;
end if;
end if;
end if;
end process;
Break <= (BreakAtNA and not BAL(8)) or (PCAdd and not PCAdder(8));
PCAdder <= resize(PC(7 downto 0),9) + resize(unsigned(DL(7) & DL),9) when PCAdd = '1' else "0" & PC(7 downto 0);
with Set_BusA_To select
BusA <= DI when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
(others => '-') when others;
with Set_Addr_To_r select
A <= "0000000000000001" & std_logic_vector(S(7 downto 0)) when "01",
DBR & "00000000" & AD when "10",
"00000000" & BAH & BAL(7 downto 0) when "11",
PBR & std_logic_vector(PC(15 downto 8)) & std_logic_vector(PCAdder(7 downto 0)) when others;
with Write_Data_r select
DO <= DL when "000",
ABC(7 downto 0) when "001",
X(7 downto 0) when "010",
Y(7 downto 0) when "011",
std_logic_vector(S(7 downto 0)) when "100",
P when "101",
std_logic_vector(PC(7 downto 0)) when "110",
std_logic_vector(PC(15 downto 8)) when others;
-------------------------------------------------------------------------
--
-- Main state machine
--
-------------------------------------------------------------------------
process (Res_n, Clk)
begin
if Res_n = '0' then
MCycle <= "001";
RstCycle <= '1';
IRQCycle <= '0';
NMICycle <= '0';
NMIAct <= '0';
elsif Clk'event and Clk = '1' then
if Rdy = '1' then
if MCycle = LCycle or Break = '1' then
MCycle <= "000";
RstCycle <= '0';
IRQCycle <= '0';
NMICycle <= '0';
if NMIAct = '1' then
NMICycle <= '1';
elsif IRQ_n_o = '0' and P(Flag_I) = '0' then
IRQCycle <= '1';
end if;
else
MCycle <= std_logic_vector(unsigned(MCycle) + 1);
end if;
if NMICycle = '1' then
NMIAct <= '0';
end if;
if NMI_n_o = '1' and NMI_n = '0' then
NMIAct <= '1';
end if;
end if;
end if;
end process;
end;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.4
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use ieee.std_logic_textio.all;
use std.textio.all;
entity AESL_axi_slave_AXILiteS is
generic (
constant TV_IN_P_mode : STRING (1 to 27) := "./c.ANN.autotvin_P_mode.dat";
constant TV_IN_P_index1 : STRING (1 to 29) := "./c.ANN.autotvin_P_index1.dat";
constant TV_IN_P_index2 : STRING (1 to 29) := "./c.ANN.autotvin_P_index2.dat";
constant TV_IN_P_intIn_index3 : STRING (1 to 35) := "./c.ANN.autotvin_P_intIn_index3.dat";
constant TV_IN_P_floatIn : STRING (1 to 30) := "./c.ANN.autotvin_P_floatIn.dat";
constant TV_OUT_ap_return : STRING (1 to 38) := "./impl_rtl.ANN.autotvout_ap_return.dat";
constant ADDR_WIDTH : INTEGER := 7;
constant DATA_WIDTH : INTEGER := 32;
constant P_mode_DEPTH : INTEGER := 1;
constant P_mode_c_bitwidth : INTEGER := 32;
constant P_index1_DEPTH : INTEGER := 1;
constant P_index1_c_bitwidth : INTEGER := 32;
constant P_index2_DEPTH : INTEGER := 1;
constant P_index2_c_bitwidth : INTEGER := 32;
constant P_intIn_index3_DEPTH : INTEGER := 1;
constant P_intIn_index3_c_bitwidth : INTEGER := 32;
constant P_floatIn_DEPTH : INTEGER := 1;
constant P_floatIn_c_bitwidth : INTEGER := 32;
constant ap_return_DEPTH : INTEGER := 1;
constant ap_return_c_bitwidth : INTEGER := 32;
constant START_ADDR : INTEGER := 0;
constant ANN_continue_addr : INTEGER := 0;
constant ANN_auto_start_addr : INTEGER := 0;
constant P_mode_data_in_addr : INTEGER := 24;
constant P_index1_data_in_addr : INTEGER := 32;
constant P_index2_data_in_addr : INTEGER := 40;
constant P_intIn_index3_data_in_addr : INTEGER := 48;
constant P_floatIn_data_in_addr : INTEGER := 56;
constant ap_return_data_out_addr : INTEGER := 16;
constant STATUS_ADDR : INTEGER := 0;
constant INTERFACE_TYPE : STRING (1 to 8) := "AXILiteS"
);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_AWADDR : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
TRAN_s_axi_AXILiteS_AWVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_AWREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_WVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_WREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_WDATA : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
TRAN_s_axi_AXILiteS_WSTRB : OUT STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0);
TRAN_s_axi_AXILiteS_ARADDR : OUT STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
TRAN_s_axi_AXILiteS_ARVALID : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_ARREADY : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_RVALID : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_RREADY : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_RDATA : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
TRAN_s_axi_AXILiteS_RRESP : IN STD_LOGIC_VECTOR(2 - 1 downto 0);
TRAN_s_axi_AXILiteS_BVALID : IN STD_LOGIC;
TRAN_s_axi_AXILiteS_BREADY : OUT STD_LOGIC;
TRAN_s_axi_AXILiteS_BRESP : IN STD_LOGIC_VECTOR(2 - 1 downto 0);
TRAN_AXILiteS_write_data_finish : OUT STD_LOGIC;
TRAN_AXILiteS_read_data_finish : OUT STD_LOGIC;
TRAN_AXILiteS_start_in : IN STD_LOGIC;
TRAN_AXILiteS_done_out : OUT STD_LOGIC;
TRAN_AXILiteS_ready_out : OUT STD_LOGIC;
TRAN_AXILiteS_ready_in : IN STD_LOGIC;
TRAN_AXILiteS_idle_out : OUT STD_LOGIC;
TRAN_AXILiteS_write_start_in : IN STD_LOGIC;
TRAN_AXILiteS_write_start_finish : OUT STD_LOGIC;
TRAN_AXILiteS_interrupt : IN STD_LOGIC;
TRAN_AXILiteS_transaction_done_in : IN STD_LOGIC
);
end AESL_axi_slave_AXILiteS;
architecture behav of AESL_axi_slave_AXILiteS is
------------------------Local signal-------------------
shared variable P_mode_OPERATE_DEPTH : INTEGER;
shared variable P_index1_OPERATE_DEPTH : INTEGER;
shared variable P_index2_OPERATE_DEPTH : INTEGER;
shared variable P_intIn_index3_OPERATE_DEPTH : INTEGER;
shared variable P_floatIn_OPERATE_DEPTH : INTEGER;
shared variable ap_return_OPERATE_DEPTH : INTEGER;
signal AWADDR_reg : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_0_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_1_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_2_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_3_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_4_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_5_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_6_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_7_AWADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal AWVALID_reg : STD_LOGIC := '0';
signal process_0_AWVALID_var : STD_LOGIC := '0';
signal process_1_AWVALID_var : STD_LOGIC := '0';
signal process_2_AWVALID_var : STD_LOGIC := '0';
signal process_3_AWVALID_var : STD_LOGIC := '0';
signal process_4_AWVALID_var : STD_LOGIC := '0';
signal process_5_AWVALID_var : STD_LOGIC := '0';
signal process_6_AWVALID_var : STD_LOGIC := '0';
signal process_7_AWVALID_var : STD_LOGIC := '0';
signal WVALID_reg : STD_LOGIC := '0';
signal process_0_WVALID_var : STD_LOGIC := '0';
signal process_1_WVALID_var : STD_LOGIC := '0';
signal process_2_WVALID_var : STD_LOGIC := '0';
signal process_3_WVALID_var : STD_LOGIC := '0';
signal process_4_WVALID_var : STD_LOGIC := '0';
signal process_5_WVALID_var : STD_LOGIC := '0';
signal process_6_WVALID_var : STD_LOGIC := '0';
signal process_7_WVALID_var : STD_LOGIC := '0';
signal WDATA_reg : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_0_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_1_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_2_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_3_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_4_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_5_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_6_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_7_WDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal WSTRB_reg : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_0_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_1_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_2_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_3_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_4_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_5_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_6_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal process_7_WSTRB_var : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0) := (others => '0');
signal ARADDR_reg : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_0_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_1_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_2_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_3_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_4_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_5_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_6_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal process_7_ARADDR_var : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0) := (others => '0');
signal ARVALID_reg : STD_LOGIC := '0';
signal process_0_ARVALID_var : STD_LOGIC := '0';
signal process_1_ARVALID_var : STD_LOGIC := '0';
signal process_2_ARVALID_var : STD_LOGIC := '0';
signal process_3_ARVALID_var : STD_LOGIC := '0';
signal process_4_ARVALID_var : STD_LOGIC := '0';
signal process_5_ARVALID_var : STD_LOGIC := '0';
signal process_6_ARVALID_var : STD_LOGIC := '0';
signal process_7_ARVALID_var : STD_LOGIC := '0';
signal RREADY_reg : STD_LOGIC := '0';
signal process_0_RREADY_var : STD_LOGIC := '0';
signal process_1_RREADY_var : STD_LOGIC := '0';
signal process_2_RREADY_var : STD_LOGIC := '0';
signal process_3_RREADY_var : STD_LOGIC := '0';
signal process_4_RREADY_var : STD_LOGIC := '0';
signal process_5_RREADY_var : STD_LOGIC := '0';
signal process_6_RREADY_var : STD_LOGIC := '0';
signal process_7_RREADY_var : STD_LOGIC := '0';
signal RDATA_reg : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_0_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_1_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_2_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_3_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_4_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_5_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_6_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal process_7_RDATA_var : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
signal BREADY_reg : STD_LOGIC := '0';
signal process_0_BREADY_var : STD_LOGIC := '0';
signal process_1_BREADY_var : STD_LOGIC := '0';
signal process_2_BREADY_var : STD_LOGIC := '0';
signal process_3_BREADY_var : STD_LOGIC := '0';
signal process_4_BREADY_var : STD_LOGIC := '0';
signal process_5_BREADY_var : STD_LOGIC := '0';
signal process_6_BREADY_var : STD_LOGIC := '0';
signal process_7_BREADY_var : STD_LOGIC := '0';
type mem_P_mode_arr2D is array(0 to P_mode_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_mode : mem_P_mode_arr2D;
signal P_mode_write_data_finish : STD_LOGIC := '0';
type mem_P_index1_arr2D is array(0 to P_index1_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_index1 : mem_P_index1_arr2D;
signal P_index1_write_data_finish : STD_LOGIC := '0';
type mem_P_index2_arr2D is array(0 to P_index2_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_index2 : mem_P_index2_arr2D;
signal P_index2_write_data_finish : STD_LOGIC := '0';
type mem_P_intIn_index3_arr2D is array(0 to P_intIn_index3_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_intIn_index3 : mem_P_intIn_index3_arr2D;
signal P_intIn_index3_write_data_finish : STD_LOGIC := '0';
type mem_P_floatIn_arr2D is array(0 to P_floatIn_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_P_floatIn : mem_P_floatIn_arr2D;
signal P_floatIn_write_data_finish : STD_LOGIC := '0';
type mem_ap_return_arr2D is array(0 to ap_return_DEPTH - 1) of STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
shared variable mem_ap_return : mem_ap_return_arr2D;
signal ap_return_read_data_finish : STD_LOGIC := '0';
signal AESL_ready_out_index_reg : STD_LOGIC := '0';
signal AESL_write_start_finish : STD_LOGIC := '0';
signal AESL_ready_reg : STD_LOGIC;
signal ready_initial : STD_LOGIC;
signal AESL_done_index_reg : STD_LOGIC := '0';
signal AESL_idle_index_reg : STD_LOGIC := '0';
signal AESL_auto_restart_index_reg : STD_LOGIC;
signal process_0_finish : STD_LOGIC := '0';
signal process_1_finish : STD_LOGIC := '0';
signal process_2_finish : STD_LOGIC := '0';
signal process_3_finish : STD_LOGIC := '0';
signal process_4_finish : STD_LOGIC := '0';
signal process_5_finish : STD_LOGIC := '0';
signal process_6_finish : STD_LOGIC := '0';
signal process_7_finish : STD_LOGIC := '0';
--write P_mode reg
shared variable write_P_mode_count : INTEGER;
signal write_P_mode_run_flag : STD_LOGIC := '0';
signal write_one_P_mode_data_done : STD_LOGIC := '0';
--write P_index1 reg
shared variable write_P_index1_count : INTEGER;
signal write_P_index1_run_flag : STD_LOGIC := '0';
signal write_one_P_index1_data_done : STD_LOGIC := '0';
--write P_index2 reg
shared variable write_P_index2_count : INTEGER;
signal write_P_index2_run_flag : STD_LOGIC := '0';
signal write_one_P_index2_data_done : STD_LOGIC := '0';
--write P_intIn_index3 reg
shared variable write_P_intIn_index3_count : INTEGER;
signal write_P_intIn_index3_run_flag : STD_LOGIC := '0';
signal write_one_P_intIn_index3_data_done : STD_LOGIC := '0';
--write P_floatIn reg
shared variable write_P_floatIn_count : INTEGER;
signal write_P_floatIn_run_flag : STD_LOGIC := '0';
signal write_one_P_floatIn_data_done : STD_LOGIC := '0';
--read ap_return reg
shared variable read_ap_return_count : INTEGER;
signal read_ap_return_run_flag : STD_LOGIC := '0';
signal read_one_ap_return_data_done : STD_LOGIC := '0';
shared variable write_start_count : INTEGER;
signal write_start_run_flag : STD_LOGIC := '0';
--===================process control=================
signal ongoing_process_number : INTEGER;
-- Process number depends on how much processes needed.
shared variable process_busy : STD_LOGIC := '0';
function esl_icmp_eq(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if v1 = v2 then
res := "1";
else
res := "0";
end if;
return res;
end function;
procedure esl_read_token (file textfile: TEXT; textline: inout LINE; token: out STRING; token_len: out INTEGER) is
variable whitespace : CHARACTER;
variable i : INTEGER;
variable ok: BOOLEAN;
variable buff: STRING(1 to token'length);
begin
ok := false;
i := 1;
loop_main: while not endfile(textfile) loop
if textline = null or textline'length = 0 then
readline(textfile, textline);
end if;
loop_remove_whitespace: while textline'length > 0 loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
read(textline, whitespace);
else
exit loop_remove_whitespace;
end if;
end loop;
loop_aesl_read_token: while textline'length > 0 and i <= buff'length loop
if textline(textline'left) = ' ' or
textline(textline'left) = HT or
textline(textline'left) = CR or
textline(textline'left) = LF then
exit loop_aesl_read_token;
else
read(textline, buff(i));
i := i + 1;
end if;
ok := true;
end loop;
if ok = true then
exit loop_main;
end if;
end loop;
buff(i) := ' ';
token := buff;
token_len:= i-1;
end procedure esl_read_token;
procedure esl_read_token (file textfile: TEXT;
textline: inout LINE;
token: out STRING) is
variable i : INTEGER;
begin
esl_read_token (textfile, textline, token, i);
end procedure esl_read_token;
function esl_add(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : unsigned(v1'length-1 downto 0);
begin
res := unsigned(v1) + unsigned(v2);
return std_logic_vector(res);
end function;
function esl_icmp_ult(v1, v2 : STD_LOGIC_VECTOR) return STD_LOGIC_VECTOR is
variable res : STD_LOGIC_VECTOR(0 downto 0);
begin
if unsigned(v1) < unsigned(v2) then
res := "1";
else
res := "0";
end if;
return res;
end function;
function esl_str2lv_hex (RHS : STRING; data_width : INTEGER) return STD_LOGIC_VECTOR is
variable ret : STD_LOGIC_VECTOR(data_width - 1 downto 0);
variable idx : integer := 3;
begin
ret := (others => '0');
if(RHS(1) /= '0' and (RHS(2) /= 'x' or RHS(2) /= 'X')) then
report "Error! The format of hex number is not initialed by 0x";
end if;
while true loop
if (data_width > 4) then
case RHS(idx) is
when '0' => ret := ret(data_width - 5 downto 0) & "0000";
when '1' => ret := ret(data_width - 5 downto 0) & "0001";
when '2' => ret := ret(data_width - 5 downto 0) & "0010";
when '3' => ret := ret(data_width - 5 downto 0) & "0011";
when '4' => ret := ret(data_width - 5 downto 0) & "0100";
when '5' => ret := ret(data_width - 5 downto 0) & "0101";
when '6' => ret := ret(data_width - 5 downto 0) & "0110";
when '7' => ret := ret(data_width - 5 downto 0) & "0111";
when '8' => ret := ret(data_width - 5 downto 0) & "1000";
when '9' => ret := ret(data_width - 5 downto 0) & "1001";
when 'a' | 'A' => ret := ret(data_width - 5 downto 0) & "1010";
when 'b' | 'B' => ret := ret(data_width - 5 downto 0) & "1011";
when 'c' | 'C' => ret := ret(data_width - 5 downto 0) & "1100";
when 'd' | 'D' => ret := ret(data_width - 5 downto 0) & "1101";
when 'e' | 'E' => ret := ret(data_width - 5 downto 0) & "1110";
when 'f' | 'F' => ret := ret(data_width - 5 downto 0) & "1111";
when 'x' | 'X' => ret := ret(data_width - 5 downto 0) & "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 4) then
case RHS(idx) is
when '0' => ret := "0000";
when '1' => ret := "0001";
when '2' => ret := "0010";
when '3' => ret := "0011";
when '4' => ret := "0100";
when '5' => ret := "0101";
when '6' => ret := "0110";
when '7' => ret := "0111";
when '8' => ret := "1000";
when '9' => ret := "1001";
when 'a' | 'A' => ret := "1010";
when 'b' | 'B' => ret := "1011";
when 'c' | 'C' => ret := "1100";
when 'd' | 'D' => ret := "1101";
when 'e' | 'E' => ret := "1110";
when 'f' | 'F' => ret := "1111";
when 'x' | 'X' => ret := "XXXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 3) then
case RHS(idx) is
when '0' => ret := "000";
when '1' => ret := "001";
when '2' => ret := "010";
when '3' => ret := "011";
when '4' => ret := "100";
when '5' => ret := "101";
when '6' => ret := "110";
when '7' => ret := "111";
when 'x' | 'X' => ret := "XXX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 2) then
case RHS(idx) is
when '0' => ret := "00";
when '1' => ret := "01";
when '2' => ret := "10";
when '3' => ret := "11";
when 'x' | 'X' => ret := "XX";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
elsif (data_width = 1) then
case RHS(idx) is
when '0' => ret := "0";
when '1' => ret := "1";
when 'x' | 'X' => ret := "X";
when ' ' => return ret;
when others => report "Wrong hex char " & RHS(idx); return ret;
end case;
else
report string'("Wrong data_width.");
return ret;
end if;
idx := idx + 1;
end loop;
return ret;
end function;
function esl_conv_string_hex (lv : STD_LOGIC_VECTOR) return STRING is
constant str_len : integer := (lv'length + 3)/4;
variable ret : STRING (1 to str_len);
variable i, tmp: INTEGER;
variable normal_lv : STD_LOGIC_VECTOR(lv'length - 1 downto 0);
variable tmp_lv : STD_LOGIC_VECTOR(3 downto 0);
begin
normal_lv := lv;
for i in 1 to str_len loop
if(i = 1) then
if((lv'length mod 4) = 3) then
tmp_lv(2 downto 0) := normal_lv(lv'length - 1 downto lv'length - 3);
case tmp_lv(2 downto 0) is
when "000" => ret(i) := '0';
when "001" => ret(i) := '1';
when "010" => ret(i) := '2';
when "011" => ret(i) := '3';
when "100" => ret(i) := '4';
when "101" => ret(i) := '5';
when "110" => ret(i) := '6';
when "111" => ret(i) := '7';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 2) then
tmp_lv(1 downto 0) := normal_lv(lv'length - 1 downto lv'length - 2);
case tmp_lv(1 downto 0) is
when "00" => ret(i) := '0';
when "01" => ret(i) := '1';
when "10" => ret(i) := '2';
when "11" => ret(i) := '3';
when others => ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 1) then
tmp_lv(0 downto 0) := normal_lv(lv'length - 1 downto lv'length - 1);
case tmp_lv(0 downto 0) is
when "0" => ret(i) := '0';
when "1" => ret(i) := '1';
when others=> ret(i) := 'X';
end case;
elsif((lv'length mod 4) = 0) then
tmp_lv(3 downto 0) := normal_lv(lv'length - 1 downto lv'length - 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
else
tmp_lv(3 downto 0) := normal_lv((str_len - i) * 4 + 3 downto (str_len - i) * 4);
case tmp_lv(3 downto 0) is
when "0000" => ret(i) := '0';
when "0001" => ret(i) := '1';
when "0010" => ret(i) := '2';
when "0011" => ret(i) := '3';
when "0100" => ret(i) := '4';
when "0101" => ret(i) := '5';
when "0110" => ret(i) := '6';
when "0111" => ret(i) := '7';
when "1000" => ret(i) := '8';
when "1001" => ret(i) := '9';
when "1010" => ret(i) := 'a';
when "1011" => ret(i) := 'b';
when "1100" => ret(i) := 'c';
when "1101" => ret(i) := 'd';
when "1110" => ret(i) := 'e';
when "1111" => ret(i) := 'f';
when others => ret(i) := 'X';
end case;
end if;
end loop;
return ret;
end function;
procedure count_c_data_four_byte_num_by_bitwidth (constant bitwidth : IN INTEGER; variable num : OUT INTEGER) is
variable factor : INTEGER;
variable i : INTEGER;
begin
factor := 32;
for i in 1 to 32 loop
if (bitwidth <= factor and bitwidth > factor - 32) then
num := i;
end if;
factor := factor + 32;
end loop;
end procedure;
procedure count_seperate_factor_by_bitwidth(bitwidth : in INTEGER; factor : out INTEGER) is
begin
if (bitwidth <= 8) then
factor := 4;
elsif (bitwidth <= 16 and bitwidth > 8 ) then
factor := 2;
elsif (bitwidth <= 32 and bitwidth > 16 ) then
factor := 1;
elsif (bitwidth <= 1024 and bitwidth > 32 ) then
factor := 1;
end if;
end procedure;
procedure count_operate_depth_by_bitwidth_and_depth(bitwidth : in INTEGER; depth : in INTEGER; operate_depth : out INTEGER) is
variable factor : INTEGER;
variable remain : INTEGER;
variable operate_depth_tmp : INTEGER;
begin
count_seperate_factor_by_bitwidth (bitwidth , factor);
operate_depth_tmp := depth / factor;
remain := depth mod factor;
if (remain > 0) then
operate_depth_tmp := operate_depth_tmp + 1;
end if;
operate_depth := operate_depth_tmp;
end procedure;
begin
--=================== signal connection ==============
TRAN_s_axi_AXILiteS_AWADDR <= AWADDR_reg;
TRAN_s_axi_AXILiteS_AWVALID <= AWVALID_reg;
TRAN_s_axi_AXILiteS_WVALID <= WVALID_reg;
TRAN_s_axi_AXILiteS_WDATA <= WDATA_reg;
TRAN_s_axi_AXILiteS_WSTRB <= WSTRB_reg;
TRAN_s_axi_AXILiteS_ARADDR <= ARADDR_reg;
TRAN_s_axi_AXILiteS_ARVALID <= ARVALID_reg;
TRAN_s_axi_AXILiteS_RREADY <= RREADY_reg;
TRAN_s_axi_AXILiteS_BREADY <= BREADY_reg;
TRAN_AXILiteS_done_out <= AESL_done_index_reg;
TRAN_AXILiteS_ready_out <= AESL_ready_out_index_reg;
TRAN_AXILiteS_write_start_finish <= AESL_write_start_finish;
TRAN_AXILiteS_idle_out <= AESL_idle_index_reg;
TRAN_AXILiteS_read_data_finish <= '1' and ap_return_read_data_finish;
TRAN_AXILiteS_write_data_finish <= '1' and P_mode_write_data_finish and P_index1_write_data_finish and P_index2_write_data_finish and P_intIn_index3_write_data_finish and P_floatIn_write_data_finish;
AESL_ready_reg_proc : process(TRAN_AXILiteS_ready_in, ready_initial)
begin
AESL_ready_reg <= TRAN_AXILiteS_ready_in or ready_initial;
end process;
gen_ready_initial_proc : process
begin
ready_initial <= '0';
wait until reset = '1';
wait until clk'event and clk = '1';
ready_initial <= '1';
wait until clk'event and clk = '1';
ready_initial <= '0';
wait;
end process;
ongoing_process_number_gen : process(reset , process_0_finish , process_1_finish , process_2_finish , process_3_finish , process_4_finish , process_5_finish , process_6_finish , process_7_finish )
begin
if (reset = '0') then
ongoing_process_number <= 0;
elsif (ongoing_process_number = 0 and process_0_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 1 and process_1_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 2 and process_2_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 3 and process_3_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 4 and process_4_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 5 and process_5_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 6 and process_6_finish = '1') then
ongoing_process_number <= ongoing_process_number + 1;
elsif (ongoing_process_number = 7 and process_7_finish = '1') then
ongoing_process_number <= 0;
end if;
end process;
output_reg_write_value_function : process
begin
wait until reset = '1';
wait until clk'event and clk = '1';
while (true) loop
if (ongoing_process_number = 0 ) then
AWADDR_reg <= process_0_AWADDR_var;
AWVALID_reg <= process_0_AWVALID_var;
WVALID_reg <= process_0_WVALID_var;
WDATA_reg <= process_0_WDATA_var;
WSTRB_reg <= process_0_WSTRB_var;
ARADDR_reg <= process_0_ARADDR_var;
ARVALID_reg <= process_0_ARVALID_var;
RREADY_reg <= process_0_RREADY_var;
BREADY_reg <= process_0_BREADY_var;
elsif (ongoing_process_number = 1 ) then
AWADDR_reg <= process_1_AWADDR_var;
AWVALID_reg <= process_1_AWVALID_var;
WVALID_reg <= process_1_WVALID_var;
WDATA_reg <= process_1_WDATA_var;
WSTRB_reg <= process_1_WSTRB_var;
ARADDR_reg <= process_1_ARADDR_var;
ARVALID_reg <= process_1_ARVALID_var;
RREADY_reg <= process_1_RREADY_var;
BREADY_reg <= process_1_BREADY_var;
elsif (ongoing_process_number = 2 ) then
AWADDR_reg <= process_2_AWADDR_var;
AWVALID_reg <= process_2_AWVALID_var;
WVALID_reg <= process_2_WVALID_var;
WDATA_reg <= process_2_WDATA_var;
WSTRB_reg <= process_2_WSTRB_var;
ARADDR_reg <= process_2_ARADDR_var;
ARVALID_reg <= process_2_ARVALID_var;
RREADY_reg <= process_2_RREADY_var;
BREADY_reg <= process_2_BREADY_var;
elsif (ongoing_process_number = 3 ) then
AWADDR_reg <= process_3_AWADDR_var;
AWVALID_reg <= process_3_AWVALID_var;
WVALID_reg <= process_3_WVALID_var;
WDATA_reg <= process_3_WDATA_var;
WSTRB_reg <= process_3_WSTRB_var;
ARADDR_reg <= process_3_ARADDR_var;
ARVALID_reg <= process_3_ARVALID_var;
RREADY_reg <= process_3_RREADY_var;
BREADY_reg <= process_3_BREADY_var;
elsif (ongoing_process_number = 4 ) then
AWADDR_reg <= process_4_AWADDR_var;
AWVALID_reg <= process_4_AWVALID_var;
WVALID_reg <= process_4_WVALID_var;
WDATA_reg <= process_4_WDATA_var;
WSTRB_reg <= process_4_WSTRB_var;
ARADDR_reg <= process_4_ARADDR_var;
ARVALID_reg <= process_4_ARVALID_var;
RREADY_reg <= process_4_RREADY_var;
BREADY_reg <= process_4_BREADY_var;
elsif (ongoing_process_number = 5 ) then
AWADDR_reg <= process_5_AWADDR_var;
AWVALID_reg <= process_5_AWVALID_var;
WVALID_reg <= process_5_WVALID_var;
WDATA_reg <= process_5_WDATA_var;
WSTRB_reg <= process_5_WSTRB_var;
ARADDR_reg <= process_5_ARADDR_var;
ARVALID_reg <= process_5_ARVALID_var;
RREADY_reg <= process_5_RREADY_var;
BREADY_reg <= process_5_BREADY_var;
elsif (ongoing_process_number = 6 ) then
AWADDR_reg <= process_6_AWADDR_var;
AWVALID_reg <= process_6_AWVALID_var;
WVALID_reg <= process_6_WVALID_var;
WDATA_reg <= process_6_WDATA_var;
WSTRB_reg <= process_6_WSTRB_var;
ARADDR_reg <= process_6_ARADDR_var;
ARVALID_reg <= process_6_ARVALID_var;
RREADY_reg <= process_6_RREADY_var;
BREADY_reg <= process_6_BREADY_var;
elsif (ongoing_process_number = 7 ) then
AWADDR_reg <= process_7_AWADDR_var;
AWVALID_reg <= process_7_AWVALID_var;
WVALID_reg <= process_7_WVALID_var;
WDATA_reg <= process_7_WDATA_var;
WSTRB_reg <= process_7_WSTRB_var;
ARADDR_reg <= process_7_ARADDR_var;
ARVALID_reg <= process_7_ARVALID_var;
RREADY_reg <= process_7_RREADY_var;
BREADY_reg <= process_7_BREADY_var;
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
update_status_proc : process
variable process_num : INTEGER;
variable read_status_resp : INTEGER;
variable process_0_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
begin
wait until reset = '1';
wait until clk'event and clk = '1';
process_num := 0;
while (true) loop
process_0_finish <= '0';
AESL_done_index_reg <= '0';
AESL_ready_out_index_reg <= '0';
if (ongoing_process_number = process_num and process_busy = '0') then
process_busy := '1';
--=======================one single read operate======================
read_status_resp := 0;
process_0_ARADDR_var <= STD_LOGIC_VECTOR(to_unsigned(STATUS_ADDR, ADDR_WIDTH));
process_0_ARVALID_var <= '1';
while (TRAN_s_axi_AXILiteS_ARREADY /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_0_ARVALID_var <= '0';
process_0_RREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_RVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_0_RDATA_tmp := TRAN_s_axi_AXILiteS_RDATA;
process_0_RREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_RRESP = (2 => '0') ) then
read_status_resp := 1;
--output success. in fact RRESP is always 2'b00
end if;
wait until clk'event and clk = '1';
--=======================one single read operate end======================
AESL_done_index_reg <= process_0_RDATA_tmp(1);
AESL_ready_out_index_reg <= process_0_RDATA_tmp(1);
AESL_idle_index_reg <= process_0_RDATA_tmp(2);
process_busy := '0';
process_0_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_mode_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_mode_write_data_finish <= '0';
write_P_mode_run_flag <= '0';
write_P_mode_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_mode_c_bitwidth, P_mode_DEPTH, P_mode_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_mode_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_mode_run_flag <= '1';
write_P_mode_count := 0;
end if;
if (write_one_P_mode_data_done = '1') then
write_P_mode_count := write_P_mode_count + 1;
if (write_P_mode_count = P_mode_OPERATE_DEPTH) then
write_P_mode_run_flag <= '0';
P_mode_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_mode_proc : process
variable write_P_mode_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_1_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_mode_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_mode_c_bitwidth;
process_num := 1;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_1_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_mode_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_mode data
for i in 0 to four_byte_num - 1 loop
if (P_mode_c_bitwidth < 32) then
P_mode_data_tmp_reg := mem_P_mode(write_P_mode_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_mode_c_bitwidth) then
P_mode_data_tmp_reg(j) := mem_P_mode(write_P_mode_count)(i*32 + j);
else
P_mode_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_mode_resp := 0;
aw_flag := '0';
w_flag := '0';
process_1_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_mode_data_in_addr + write_P_mode_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_1_AWVALID_var <= '1';
process_1_WDATA_var <= P_mode_data_tmp_reg;
process_1_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_1_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_1_AWVALID_var <= not aw_flag;
process_1_WVALID_var <= not w_flag;
end loop;
process_1_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_1_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_mode_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_mode_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_mode_data_done <= '0';
end if;
process_1_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_index1_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_index1_write_data_finish <= '0';
write_P_index1_run_flag <= '0';
write_P_index1_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_index1_c_bitwidth, P_index1_DEPTH, P_index1_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_index1_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_index1_run_flag <= '1';
write_P_index1_count := 0;
end if;
if (write_one_P_index1_data_done = '1') then
write_P_index1_count := write_P_index1_count + 1;
if (write_P_index1_count = P_index1_OPERATE_DEPTH) then
write_P_index1_run_flag <= '0';
P_index1_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_index1_proc : process
variable write_P_index1_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_2_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_index1_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_index1_c_bitwidth;
process_num := 2;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_2_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_index1_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_index1 data
for i in 0 to four_byte_num - 1 loop
if (P_index1_c_bitwidth < 32) then
P_index1_data_tmp_reg := mem_P_index1(write_P_index1_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_index1_c_bitwidth) then
P_index1_data_tmp_reg(j) := mem_P_index1(write_P_index1_count)(i*32 + j);
else
P_index1_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_index1_resp := 0;
aw_flag := '0';
w_flag := '0';
process_2_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_index1_data_in_addr + write_P_index1_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_2_AWVALID_var <= '1';
process_2_WDATA_var <= P_index1_data_tmp_reg;
process_2_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_2_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_2_AWVALID_var <= not aw_flag;
process_2_WVALID_var <= not w_flag;
end loop;
process_2_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_2_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_index1_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_index1_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_index1_data_done <= '0';
end if;
process_2_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_index2_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_index2_write_data_finish <= '0';
write_P_index2_run_flag <= '0';
write_P_index2_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_index2_c_bitwidth, P_index2_DEPTH, P_index2_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_index2_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_index2_run_flag <= '1';
write_P_index2_count := 0;
end if;
if (write_one_P_index2_data_done = '1') then
write_P_index2_count := write_P_index2_count + 1;
if (write_P_index2_count = P_index2_OPERATE_DEPTH) then
write_P_index2_run_flag <= '0';
P_index2_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_index2_proc : process
variable write_P_index2_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_3_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_index2_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_index2_c_bitwidth;
process_num := 3;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_3_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_index2_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_index2 data
for i in 0 to four_byte_num - 1 loop
if (P_index2_c_bitwidth < 32) then
P_index2_data_tmp_reg := mem_P_index2(write_P_index2_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_index2_c_bitwidth) then
P_index2_data_tmp_reg(j) := mem_P_index2(write_P_index2_count)(i*32 + j);
else
P_index2_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_index2_resp := 0;
aw_flag := '0';
w_flag := '0';
process_3_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_index2_data_in_addr + write_P_index2_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_3_AWVALID_var <= '1';
process_3_WDATA_var <= P_index2_data_tmp_reg;
process_3_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_3_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_3_AWVALID_var <= not aw_flag;
process_3_WVALID_var <= not w_flag;
end loop;
process_3_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_3_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_index2_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_index2_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_index2_data_done <= '0';
end if;
process_3_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_intIn_index3_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_intIn_index3_write_data_finish <= '0';
write_P_intIn_index3_run_flag <= '0';
write_P_intIn_index3_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_intIn_index3_c_bitwidth, P_intIn_index3_DEPTH, P_intIn_index3_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_intIn_index3_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_intIn_index3_run_flag <= '1';
write_P_intIn_index3_count := 0;
end if;
if (write_one_P_intIn_index3_data_done = '1') then
write_P_intIn_index3_count := write_P_intIn_index3_count + 1;
if (write_P_intIn_index3_count = P_intIn_index3_OPERATE_DEPTH) then
write_P_intIn_index3_run_flag <= '0';
P_intIn_index3_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_intIn_index3_proc : process
variable write_P_intIn_index3_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_4_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_intIn_index3_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_intIn_index3_c_bitwidth;
process_num := 4;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_4_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_intIn_index3_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_intIn_index3 data
for i in 0 to four_byte_num - 1 loop
if (P_intIn_index3_c_bitwidth < 32) then
P_intIn_index3_data_tmp_reg := mem_P_intIn_index3(write_P_intIn_index3_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_intIn_index3_c_bitwidth) then
P_intIn_index3_data_tmp_reg(j) := mem_P_intIn_index3(write_P_intIn_index3_count)(i*32 + j);
else
P_intIn_index3_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_intIn_index3_resp := 0;
aw_flag := '0';
w_flag := '0';
process_4_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_intIn_index3_data_in_addr + write_P_intIn_index3_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_4_AWVALID_var <= '1';
process_4_WDATA_var <= P_intIn_index3_data_tmp_reg;
process_4_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_4_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_4_AWVALID_var <= not aw_flag;
process_4_WVALID_var <= not w_flag;
end loop;
process_4_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_4_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_intIn_index3_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_intIn_index3_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_intIn_index3_data_done <= '0';
end if;
process_4_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_P_floatIn_run_flag : process (reset , clk)
begin
if (reset = '0') then
P_floatIn_write_data_finish <= '0';
write_P_floatIn_run_flag <= '0';
write_P_floatIn_count := 0;
count_operate_depth_by_bitwidth_and_depth (P_floatIn_c_bitwidth, P_floatIn_DEPTH, P_floatIn_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (TRAN_AXILiteS_start_in = '1') then
P_floatIn_write_data_finish <= '0';
end if;
if (AESL_ready_reg = '1') then
write_P_floatIn_run_flag <= '1';
write_P_floatIn_count := 0;
end if;
if (write_one_P_floatIn_data_done = '1') then
write_P_floatIn_count := write_P_floatIn_count + 1;
if (write_P_floatIn_count = P_floatIn_OPERATE_DEPTH) then
write_P_floatIn_run_flag <= '0';
P_floatIn_write_data_finish <= '1';
end if;
end if;
end if;
end process;
write_P_floatIn_proc : process
variable write_P_floatIn_resp : INTEGER;
variable process_num : INTEGER;
variable get_ack : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable process_5_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
variable P_floatIn_data_tmp_reg : STD_LOGIC_VECTOR(31 downto 0);
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := P_floatIn_c_bitwidth;
process_num := 5;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_5_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
get_ack := 1;
if (write_P_floatIn_run_flag = '1' and get_ack = 1) then
process_busy := '1';
-- write P_floatIn data
for i in 0 to four_byte_num - 1 loop
if (P_floatIn_c_bitwidth < 32) then
P_floatIn_data_tmp_reg := mem_P_floatIn(write_P_floatIn_count);
else
for j in 0 to 31 loop
if (i*32 + j < P_floatIn_c_bitwidth) then
P_floatIn_data_tmp_reg(j) := mem_P_floatIn(write_P_floatIn_count)(i*32 + j);
else
P_floatIn_data_tmp_reg(j) := '0';
end if;
end loop;
end if;
--=======================one single write operate======================
write_P_floatIn_resp := 0;
aw_flag := '0';
w_flag := '0';
process_5_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(P_floatIn_data_in_addr + write_P_floatIn_count * four_byte_num * 4 + i * 4, ADDR_WIDTH));
process_5_AWVALID_var <= '1';
process_5_WDATA_var <= P_floatIn_data_tmp_reg;
process_5_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_5_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_5_AWVALID_var <= not aw_flag;
process_5_WVALID_var <= not w_flag;
end loop;
process_5_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_5_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_P_floatIn_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
end loop;
process_busy := '0';
write_one_P_floatIn_data_done <= '1';
wait until clk'event and clk = '1';
write_one_P_floatIn_data_done <= '0';
end if;
process_5_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_write_start_run_flag : process (reset , clk)
begin
if (reset = '0') then
write_start_run_flag <= '0';
write_start_count := 0;
elsif (clk'event and clk = '1') then
if (write_start_count >= 265) then
write_start_run_flag <= '0';
elsif (TRAN_AXILiteS_write_start_in = '1') then
write_start_run_flag <= '1';
end if;
if (AESL_write_start_finish = '1') then
write_start_count := write_start_count + 1;
write_start_run_flag <= '0';
end if;
end if;
end process;
write_start_proc : process
variable process_num : INTEGER;
variable write_start_resp : INTEGER;
variable write_start_tmp : STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0) ;
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 );
variable i : INTEGER;
begin
wait until reset = '1';
wait until clk'event and clk = '1';
process_num := 6;
while (true) loop
process_6_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
if (write_start_run_flag = '1') then
process_busy := '1';
write_start_tmp := (others => '0');
write_start_tmp(0) := '1';
--=======================one single write operate======================
write_start_resp := 0;
aw_flag := '0';
w_flag := '0';
process_6_AWADDR_var <= STD_LOGIC_VECTOR(to_unsigned(START_ADDR, ADDR_WIDTH));
process_6_AWVALID_var <= '1';
process_6_WDATA_var <= write_start_tmp;
process_6_WVALID_var <= '1';
for i in 0 to DATA_WIDTH/8 - 1 loop
wstrb_tmp(i) := '1';
end loop;
process_6_WSTRB_var <= wstrb_tmp;
while (aw_flag = '0' or w_flag = '0') loop
wait until clk'event and clk = '1';
if (aw_flag /= '1') then
aw_flag := TRAN_s_axi_AXILiteS_AWREADY and AWVALID_reg;
end if;
if (w_flag /= '1') then
w_flag := TRAN_s_axi_AXILiteS_WREADY and WVALID_reg;
end if;
process_6_AWVALID_var <= not aw_flag;
process_6_WVALID_var <= not w_flag;
end loop;
process_6_BREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_BVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_6_BREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_BRESP = (2 => '0')) then
write_start_resp := 1;
--input success. in fact BRESP is always 2'b00
end if;
--=======================one single write operate======================
process_busy := '0';
AESL_write_start_finish <= '1';
wait until clk'event and clk = '1';
AESL_write_start_finish <= '0';
end if;
process_6_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
wait;
end process;
gen_read_ap_return_run_flag : process (reset , clk)
begin
if (reset = '0') then
ap_return_read_data_finish <= '0';
read_ap_return_run_flag <= '0';
read_ap_return_count := 0;
count_operate_depth_by_bitwidth_and_depth (ap_return_c_bitwidth, ap_return_DEPTH, ap_return_OPERATE_DEPTH);
elsif (clk'event and clk = '1') then
if (AESL_done_index_reg = '1') then
read_ap_return_run_flag <= '1';
end if;
if (TRAN_AXILiteS_transaction_done_in = '1') then
ap_return_read_data_finish <= '0';
read_ap_return_count := 0;
end if;
if (read_one_ap_return_data_done = '1') then
read_ap_return_count := read_ap_return_count + 1;
if (read_ap_return_count = ap_return_OPERATE_DEPTH) then
read_ap_return_run_flag <= '0';
ap_return_read_data_finish <= '1';
end if;
end if;
end if;
end process;
read_ap_return_proc : process
variable read_ap_return_resp : INTEGER;
variable process_num : INTEGER;
variable get_vld : INTEGER;
variable four_byte_num : INTEGER;
variable c_bitwidth : INTEGER;
variable process_7_RDATA_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable i : INTEGER;
variable j : INTEGER;
variable aw_flag : STD_LOGIC;
variable w_flag : STD_LOGIC;
variable wstrb_tmp : STD_LOGIC_VECTOR(DATA_WIDTH/8 - 1 downto 0 ) := (others => '0');
begin
wait until reset = '1';
wait until clk'event and clk = '1';
c_bitwidth := ap_return_c_bitwidth;
process_num := 7;
count_c_data_four_byte_num_by_bitwidth (c_bitwidth , four_byte_num) ;
while (true) loop
process_7_finish <= '0';
if (ongoing_process_number = process_num and process_busy = '0' ) then
if (read_ap_return_run_flag = '1') then
process_busy := '1';
get_vld := 1;
if (get_vld = 1) then
--read ap_return data
for i in 0 to four_byte_num - 1 loop
--=======================one single read operate======================
read_ap_return_resp := 0;
process_7_ARADDR_var <= STD_LOGIC_VECTOR(to_unsigned(ap_return_data_out_addr + read_ap_return_count * four_byte_num * 4 + 4*i, ADDR_WIDTH));
process_7_ARVALID_var <= '1';
while (TRAN_s_axi_AXILiteS_ARREADY /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_7_ARVALID_var <= '0';
process_7_RREADY_var <= '1';
while (TRAN_s_axi_AXILiteS_RVALID /= '1') loop
--wait for response
wait until clk'event and clk = '1';
end loop;
wait until clk'event and clk = '1';
process_7_RDATA_tmp := TRAN_s_axi_AXILiteS_RDATA;
process_7_RREADY_var <= '0';
if (TRAN_s_axi_AXILiteS_RRESP = (2 => '0') ) then
read_ap_return_resp := 1;
--output success. in fact RRESP is always 2'b00
end if;
wait until clk'event and clk = '1';
--=======================one single read operate end======================
if (ap_return_c_bitwidth < 32) then
mem_ap_return(read_ap_return_count) := process_7_RDATA_tmp;
else
for j in 0 to 32 - 1 loop
if (i*32 + j < ap_return_c_bitwidth) then
mem_ap_return(read_ap_return_count)(i*32 + j) := process_7_RDATA_tmp(j);
end if;
end loop;
end if;
end loop;
read_one_ap_return_data_done <= '1';
wait until clk'event and clk = '1';
read_one_ap_return_data_done <= '0';
end if;
process_busy := '0';
end if;
process_7_finish <= '1';
end if;
wait until clk'event and clk = '1';
end loop;
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_mode_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_mode_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_mode_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_mode , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_mode & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_mode_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_mode_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_mode_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_mode(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_mode_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_mode(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_mode_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_mode_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_mode(i)(31 downto 0) := mem_tmp_32;
else
mem_P_mode(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_mode(P_mode_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_mode(P_mode_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_index1_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_index1_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_index1_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_index1 , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_index1 & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_index1_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_index1_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_index1_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_index1(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_index1_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_index1(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_index1_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_index1_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_index1(i)(31 downto 0) := mem_tmp_32;
else
mem_P_index1(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_index1(P_index1_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_index1(P_index1_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_index2_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_index2_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_index2_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_index2 , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_index2 & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_index2_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_index2_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_index2_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_index2(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_index2_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_index2(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_index2_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_index2_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_index2(i)(31 downto 0) := mem_tmp_32;
else
mem_P_index2(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_index2(P_index2_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_index2(P_index2_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_intIn_index3_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_intIn_index3_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_intIn_index3_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_intIn_index3 , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_intIn_index3 & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_intIn_index3_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_intIn_index3_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_intIn_index3_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_intIn_index3(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_intIn_index3_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_intIn_index3(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_intIn_index3_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_intIn_index3_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_intIn_index3(i)(31 downto 0) := mem_tmp_32;
else
mem_P_intIn_index3(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_intIn_index3(P_intIn_index3_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_intIn_index3(P_intIn_index3_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Read file------------------------
-- Read data from file
read_P_floatIn_file_process : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 128);
variable token_tmp : STD_LOGIC_VECTOR(P_floatIn_c_bitwidth - 1 downto 0) := (others => '0');
variable mem_tmp : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0) := (others => '0');
variable mem_tmp_8 : STD_LOGIC_VECTOR(8 - 1 downto 0) := (others => '0');
variable mem_tmp_16 : STD_LOGIC_VECTOR(16 - 1 downto 0) := (others => '0');
variable mem_tmp_32 : STD_LOGIC_VECTOR(32 - 1 downto 0) := (others => '0');
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable j : INTEGER;
variable factor : INTEGER;
variable remain : INTEGER;
variable read_counter : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (P_floatIn_c_bitwidth , factor);
file_open(fstatus, fp, TV_IN_P_floatIn , READ_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_IN_P_floatIn & " failed!!!" severity failure;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 13) /= "[[[runtime]]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
while(token(1 to 14) /= "[[[/runtime]]]") loop
if(token(1 to 15) /= "[[transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token); -- Skip transaction number
wait until clk'event and clk = '1';
wait for 0.2 ns;
while(AESL_ready_reg /= '1') loop
wait until clk'event and clk = '1';
wait for 0.2 ns;
end loop;
read_counter := 0;
for i in 0 to P_floatIn_DEPTH - 1 loop
read_counter := read_counter + 1;
esl_read_token(fp, token_line, token);
token_tmp := esl_str2lv_hex(token, P_floatIn_c_bitwidth);
remain := i mod factor;
if (factor = 4) then
mem_tmp_8 (7 downto 0) := (others => '0');
for j in 0 to P_floatIn_c_bitwidth - 1 loop
mem_tmp_8 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (7 downto 0) := mem_tmp_8;
elsif (remain = 1) then
mem_tmp (15 downto 8) := mem_tmp_8;
elsif (remain = 2) then
mem_tmp (23 downto 16) := mem_tmp_8;
elsif (remain = 3) then
mem_tmp (31 downto 24) := mem_tmp_8;
mem_P_floatIn(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 2) then
mem_tmp_16 (15 downto 0) := (others => '0');
for j in 0 to P_floatIn_c_bitwidth - 1 loop
mem_tmp_16 (j downto j) := token_tmp (j downto j);
end loop;
if (remain = 0) then
mem_tmp (15 downto 0) := mem_tmp_16;
elsif (remain = 1) then
mem_tmp (31 downto 16) := mem_tmp_16;
mem_P_floatIn(i/factor)(31 downto 0) := mem_tmp;
mem_tmp (DATA_WIDTH - 1 downto 0) := (others => '0');
end if;
elsif (factor = 1) then
if (P_floatIn_c_bitwidth < 32) then
mem_tmp_32 (31 downto 0) := (others => '0');
for j in 0 to P_floatIn_c_bitwidth - 1 loop
mem_tmp_32 (j downto j) := token_tmp (j downto j);
end loop;
mem_P_floatIn(i)(31 downto 0) := mem_tmp_32;
else
mem_P_floatIn(i) := token_tmp;
end if;
end if;
end loop;
remain := read_counter mod factor;
if (factor = 4) then
if (remain /= 0) then
mem_P_floatIn(P_floatIn_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
elsif (factor = 2) then
if (remain /= 0) then
mem_P_floatIn(P_floatIn_DEPTH/factor)(31 downto 0) := mem_tmp;
end if;
end if;
esl_read_token(fp, token_line, token);
if(token(1 to 16) /= "[[/transaction]]") then
assert false report "ERROR: Simulation using HLS TB failed." severity failure;
end if;
esl_read_token(fp, token_line, token);
transaction_idx := transaction_idx + 1;
end loop;
file_close(fp);
end process;
--------------------------Write file-----------------------
-- Write data to file
write_ap_return_file_proc : process
file fp : TEXT;
variable fstatus : FILE_OPEN_STATUS;
variable token_line : LINE;
variable token : STRING(1 to 1024);
variable transaction_idx : INTEGER;
variable i : INTEGER;
variable mem_tmp : STD_LOGIC_VECTOR(ap_return_c_bitwidth - 1 downto 0) := (others => '0');
variable factor : INTEGER;
variable remain : INTEGER;
variable mem_page : INTEGER;
begin
transaction_idx := 0;
count_seperate_factor_by_bitwidth (ap_return_c_bitwidth , factor);
while(true) loop
wait until clk'event and clk = '1';
while (TRAN_AXILiteS_transaction_done_in /= '1') loop
wait until clk'event and clk = '1';
end loop;
wait for 0.1 ns;
file_open(fstatus, fp, TV_OUT_ap_return, APPEND_MODE);
if(fstatus /= OPEN_OK) then
assert false report "Open file " & TV_OUT_ap_return & " failed!!!" severity failure;
end if;
write(token_line, "[[transaction]] " & integer'image(transaction_idx));
writeline(fp, token_line);
for i in 0 to (ap_return_DEPTH - ap_return_DEPTH mod factor) - 1 loop
remain := i mod factor;
if (factor = 4) then
if (remain = 0) then
mem_tmp := mem_ap_return(i/factor)(7 downto 0);
elsif (remain = 1) then
mem_tmp := mem_ap_return(i/factor)(15 downto 8);
elsif (remain = 2) then
mem_tmp := mem_ap_return(i/factor)(23 downto 16);
elsif (remain = 3) then
mem_tmp := mem_ap_return(i/factor)(31 downto 24);
end if;
write(token_line, "0x" & esl_conv_string_hex(mem_tmp));
writeline(fp, token_line);
elsif (factor = 2) then
if (remain = 0) then
mem_tmp := mem_ap_return(i/factor)(15 downto 0);
elsif (remain = 1) then
mem_tmp := mem_ap_return(i/factor)(31 downto 16);
end if;
write(token_line, "0x" & esl_conv_string_hex(mem_tmp));
writeline(fp, token_line);
elsif (factor = 1) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(i)));
writeline(fp, token_line);
end if;
end loop;
remain := (ap_return_DEPTH - 1) mod factor;
if (factor = 4) then
if (remain = 2) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(7 downto 0)));
writeline(fp, token_line);
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(15 downto 8)));
writeline(fp, token_line);
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(23 downto 16)));
writeline(fp, token_line);
elsif (remain = 1) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(7 downto 0)));
writeline(fp, token_line);
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(15 downto 8)));
writeline(fp, token_line);
elsif (remain = 0) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(7 downto 0)));
writeline(fp, token_line);
end if;
elsif (factor = 2) then
if (remain = 0) then
write(token_line, "0x" & esl_conv_string_hex(mem_ap_return(ap_return_DEPTH/factor)(15 downto 0)));
writeline(fp, token_line);
end if;
end if;
write(token_line, string'("[[/transaction]]"));
writeline(fp, token_line);
transaction_idx := transaction_idx + 1;
file_close(fp);
end loop;
end process;
end behav;
|
-- Copyright (c) 2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and-or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Unary minus operator test
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vhdl_unary_minus is
port(data_in : in signed(7 downto 0);
clk : in std_logic;
data_out : out signed(7 downto 0)
);
end vhdl_unary_minus;
architecture test of vhdl_unary_minus is
begin
process(clk)
begin
if rising_edge(clk) then
data_out <= -data_in;
end if;
end process;
end test;
|
-- Copyright (c) 2016 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and-or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Unary minus operator test
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity vhdl_unary_minus is
port(data_in : in signed(7 downto 0);
clk : in std_logic;
data_out : out signed(7 downto 0)
);
end vhdl_unary_minus;
architecture test of vhdl_unary_minus is
begin
process(clk)
begin
if rising_edge(clk) then
data_out <= -data_in;
end if;
end process;
end test;
|
entity tb_match01 is
end tb_match01;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_match01 is
signal a : std_logic_vector(3 downto 0);
signal z : std_logic;
begin
dut: entity work.match01
port map (a, z);
process
begin
a <= "1000";
wait for 1 ns;
assert z = '1' severity failure;
a <= "1010";
wait for 1 ns;
assert z = '1' severity failure;
a <= "0000";
wait for 1 ns;
assert z = '0' severity failure;
a <= "0001";
wait for 1 ns;
assert z = '0' severity failure;
wait;
end process;
end behav;
|
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
ROM_form.vhd
Production template for a 2K program for KCPSM6 in a Spartan-6 device using
2 x RAMB18WER primitives.
Ken Chapman (Xilinx Ltd)
5th August 2011
This is a VHDL template file for the KCPSM6 assembler.
This VHDL file is not valid as input directly into a synthesis or a simulation tool.
The assembler will read this template and insert the information required to complete
the definition of program ROM and write it out to a new '.vhd' file that is ready for
synthesis and simulation.
This template can be modified to define alternative memory definitions. However, you are
responsible for ensuring the template is correct as the assembler does not perform any
checking of the VHDL.
The assembler identifies all text enclosed by {} characters, and replaces these
character strings. All templates should include these {} character strings for
the assembler to work correctly.
The next line is used to determine where the template actually starts.
{begin template}
--
-------------------------------------------------------------------------------------------
-- Copyright © 2010-2011, Xilinx, Inc.
-- This file contains confidential and proprietary information of Xilinx, Inc. and is
-- protected under U.S. and international copyright and other intellectual property laws.
-------------------------------------------------------------------------------------------
--
-- Disclaimer:
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to
-- you by Xilinx, and to the maximum extent permitted by applicable law: (1) THESE
-- MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS, AND XILINX HEREBY
-- DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT,
-- OR FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable
-- (whether in contract or tort, including negligence, or under any other theory
-- of liability) for any loss or damage of any kind or nature related to, arising
-- under or in connection with these materials, including for any direct, or any
-- indirect, special, incidental, or consequential loss or damage (including loss
-- of data, profits, goodwill, or any type of loss or damage suffered as a result
-- of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-safe, or for use in any
-- application requiring fail-safe performance, such as life-support or safety
-- devices or systems, Class III medical devices, nuclear facilities, applications
-- related to the deployment of airbags, or any other applications that could lead
-- to death, personal injury, or severe property or environmental damage
-- (individually and collectively, "Critical Applications"). Customer assumes the
-- sole risk and liability of any use of Xilinx products in Critical Applications,
-- subject only to applicable laws and regulations governing limitations on product
-- liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
-------------------------------------------------------------------------------------------
--
--
-- Production definition of a 2K program for KCPSM6 in a Spartan-6 device using
-- 2 x RAMB18WER primitives.
--
-- Note: The complete 12-bit address bus is connected to KCPSM6 to facilitate future code
-- expansion with minimum changes being required to the hardware description.
-- Only the lower 11-bits of the address are actually used for the 2K address range
-- 000 to 7FF hex.
--
-- Program defined by '{psmname}.psm'.
--
-- Generated by KCPSM6 Assembler: {timestamp}.
--
-- Standard IEEE libraries
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
--
-- The Unisim Library is used to define Xilinx primitives. It is also used during
-- simulation. The source can be viewed at %XILINX%\vhdl\src\unisims\unisim_VCOMP.vhd
--
library unisim;
use unisim.vcomponents.all;
--
--
entity {name} is
Port ( address : in std_logic_vector(11 downto 0);
instruction : out std_logic_vector(17 downto 0);
enable : in std_logic;
clk : in std_logic);
end {name};
--
architecture low_level_definition of {name} is
--
signal address_a : std_logic_vector(13 downto 0);
signal data_in_a : std_logic_vector(35 downto 0);
signal data_out_a_l : std_logic_vector(35 downto 0);
signal data_out_a_h : std_logic_vector(35 downto 0);
signal address_b : std_logic_vector(13 downto 0);
signal data_in_b_l : std_logic_vector(35 downto 0);
signal data_out_b_l : std_logic_vector(35 downto 0);
signal data_in_b_h : std_logic_vector(35 downto 0);
signal data_out_b_h : std_logic_vector(35 downto 0);
signal enable_b : std_logic;
signal clk_b : std_logic;
signal we_b : std_logic_vector(3 downto 0);
--
begin
--
address_a <= address(10 downto 0) & "000";
instruction <= data_out_a_h(32) & data_out_a_h(7 downto 0) & data_out_a_l(32) & data_out_a_l(7 downto 0);
data_in_a <= "00000000000000000000000000000000000" & address(11);
--
address_b <= "00000000000000";
data_in_b_l <= "000" & data_out_b_l(32) & "000000000000000000000000" & data_out_b_l(7 downto 0);
data_in_b_h <= "000" & data_out_b_h(32) & "000000000000000000000000" & data_out_b_h(7 downto 0);
enable_b <= '0';
we_b <= "0000";
clk_b <= '0';
--
--
--
kcpsm6_rom_l: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[8:0]_INIT_00}",
INIT_01 => X"{[8:0]_INIT_01}",
INIT_02 => X"{[8:0]_INIT_02}",
INIT_03 => X"{[8:0]_INIT_03}",
INIT_04 => X"{[8:0]_INIT_04}",
INIT_05 => X"{[8:0]_INIT_05}",
INIT_06 => X"{[8:0]_INIT_06}",
INIT_07 => X"{[8:0]_INIT_07}",
INIT_08 => X"{[8:0]_INIT_08}",
INIT_09 => X"{[8:0]_INIT_09}",
INIT_0A => X"{[8:0]_INIT_0A}",
INIT_0B => X"{[8:0]_INIT_0B}",
INIT_0C => X"{[8:0]_INIT_0C}",
INIT_0D => X"{[8:0]_INIT_0D}",
INIT_0E => X"{[8:0]_INIT_0E}",
INIT_0F => X"{[8:0]_INIT_0F}",
INIT_10 => X"{[8:0]_INIT_10}",
INIT_11 => X"{[8:0]_INIT_11}",
INIT_12 => X"{[8:0]_INIT_12}",
INIT_13 => X"{[8:0]_INIT_13}",
INIT_14 => X"{[8:0]_INIT_14}",
INIT_15 => X"{[8:0]_INIT_15}",
INIT_16 => X"{[8:0]_INIT_16}",
INIT_17 => X"{[8:0]_INIT_17}",
INIT_18 => X"{[8:0]_INIT_18}",
INIT_19 => X"{[8:0]_INIT_19}",
INIT_1A => X"{[8:0]_INIT_1A}",
INIT_1B => X"{[8:0]_INIT_1B}",
INIT_1C => X"{[8:0]_INIT_1C}",
INIT_1D => X"{[8:0]_INIT_1D}",
INIT_1E => X"{[8:0]_INIT_1E}",
INIT_1F => X"{[8:0]_INIT_1F}",
INIT_20 => X"{[8:0]_INIT_20}",
INIT_21 => X"{[8:0]_INIT_21}",
INIT_22 => X"{[8:0]_INIT_22}",
INIT_23 => X"{[8:0]_INIT_23}",
INIT_24 => X"{[8:0]_INIT_24}",
INIT_25 => X"{[8:0]_INIT_25}",
INIT_26 => X"{[8:0]_INIT_26}",
INIT_27 => X"{[8:0]_INIT_27}",
INIT_28 => X"{[8:0]_INIT_28}",
INIT_29 => X"{[8:0]_INIT_29}",
INIT_2A => X"{[8:0]_INIT_2A}",
INIT_2B => X"{[8:0]_INIT_2B}",
INIT_2C => X"{[8:0]_INIT_2C}",
INIT_2D => X"{[8:0]_INIT_2D}",
INIT_2E => X"{[8:0]_INIT_2E}",
INIT_2F => X"{[8:0]_INIT_2F}",
INIT_30 => X"{[8:0]_INIT_30}",
INIT_31 => X"{[8:0]_INIT_31}",
INIT_32 => X"{[8:0]_INIT_32}",
INIT_33 => X"{[8:0]_INIT_33}",
INIT_34 => X"{[8:0]_INIT_34}",
INIT_35 => X"{[8:0]_INIT_35}",
INIT_36 => X"{[8:0]_INIT_36}",
INIT_37 => X"{[8:0]_INIT_37}",
INIT_38 => X"{[8:0]_INIT_38}",
INIT_39 => X"{[8:0]_INIT_39}",
INIT_3A => X"{[8:0]_INIT_3A}",
INIT_3B => X"{[8:0]_INIT_3B}",
INIT_3C => X"{[8:0]_INIT_3C}",
INIT_3D => X"{[8:0]_INIT_3D}",
INIT_3E => X"{[8:0]_INIT_3E}",
INIT_3F => X"{[8:0]_INIT_3F}",
INITP_00 => X"{[8:0]_INITP_00}",
INITP_01 => X"{[8:0]_INITP_01}",
INITP_02 => X"{[8:0]_INITP_02}",
INITP_03 => X"{[8:0]_INITP_03}",
INITP_04 => X"{[8:0]_INITP_04}",
INITP_05 => X"{[8:0]_INITP_05}",
INITP_06 => X"{[8:0]_INITP_06}",
INITP_07 => X"{[8:0]_INITP_07}")
port map( ADDRA => address_a,
ENA => enable,
CLKA => clk,
DOA => data_out_a_l(31 downto 0),
DOPA => data_out_a_l(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b,
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_l(31 downto 0),
DOPB => data_out_b_l(35 downto 32),
DIB => data_in_b_l(31 downto 0),
DIPB => data_in_b_l(35 downto 32),
WEB => we_b,
REGCEB => '0',
RSTB => '0');
--
--
--
kcpsm6_rom_h: RAMB16BWER
generic map ( DATA_WIDTH_A => 9,
DOA_REG => 0,
EN_RSTRAM_A => FALSE,
INIT_A => X"000000000",
RST_PRIORITY_A => "CE",
SRVAL_A => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
DATA_WIDTH_B => 9,
DOB_REG => 0,
EN_RSTRAM_B => FALSE,
INIT_B => X"000000000",
RST_PRIORITY_B => "CE",
SRVAL_B => X"000000000",
WRITE_MODE_B => "WRITE_FIRST",
RSTTYPE => "SYNC",
INIT_FILE => "NONE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "SPARTAN6",
INIT_00 => X"{[17:9]_INIT_00}",
INIT_01 => X"{[17:9]_INIT_01}",
INIT_02 => X"{[17:9]_INIT_02}",
INIT_03 => X"{[17:9]_INIT_03}",
INIT_04 => X"{[17:9]_INIT_04}",
INIT_05 => X"{[17:9]_INIT_05}",
INIT_06 => X"{[17:9]_INIT_06}",
INIT_07 => X"{[17:9]_INIT_07}",
INIT_08 => X"{[17:9]_INIT_08}",
INIT_09 => X"{[17:9]_INIT_09}",
INIT_0A => X"{[17:9]_INIT_0A}",
INIT_0B => X"{[17:9]_INIT_0B}",
INIT_0C => X"{[17:9]_INIT_0C}",
INIT_0D => X"{[17:9]_INIT_0D}",
INIT_0E => X"{[17:9]_INIT_0E}",
INIT_0F => X"{[17:9]_INIT_0F}",
INIT_10 => X"{[17:9]_INIT_10}",
INIT_11 => X"{[17:9]_INIT_11}",
INIT_12 => X"{[17:9]_INIT_12}",
INIT_13 => X"{[17:9]_INIT_13}",
INIT_14 => X"{[17:9]_INIT_14}",
INIT_15 => X"{[17:9]_INIT_15}",
INIT_16 => X"{[17:9]_INIT_16}",
INIT_17 => X"{[17:9]_INIT_17}",
INIT_18 => X"{[17:9]_INIT_18}",
INIT_19 => X"{[17:9]_INIT_19}",
INIT_1A => X"{[17:9]_INIT_1A}",
INIT_1B => X"{[17:9]_INIT_1B}",
INIT_1C => X"{[17:9]_INIT_1C}",
INIT_1D => X"{[17:9]_INIT_1D}",
INIT_1E => X"{[17:9]_INIT_1E}",
INIT_1F => X"{[17:9]_INIT_1F}",
INIT_20 => X"{[17:9]_INIT_20}",
INIT_21 => X"{[17:9]_INIT_21}",
INIT_22 => X"{[17:9]_INIT_22}",
INIT_23 => X"{[17:9]_INIT_23}",
INIT_24 => X"{[17:9]_INIT_24}",
INIT_25 => X"{[17:9]_INIT_25}",
INIT_26 => X"{[17:9]_INIT_26}",
INIT_27 => X"{[17:9]_INIT_27}",
INIT_28 => X"{[17:9]_INIT_28}",
INIT_29 => X"{[17:9]_INIT_29}",
INIT_2A => X"{[17:9]_INIT_2A}",
INIT_2B => X"{[17:9]_INIT_2B}",
INIT_2C => X"{[17:9]_INIT_2C}",
INIT_2D => X"{[17:9]_INIT_2D}",
INIT_2E => X"{[17:9]_INIT_2E}",
INIT_2F => X"{[17:9]_INIT_2F}",
INIT_30 => X"{[17:9]_INIT_30}",
INIT_31 => X"{[17:9]_INIT_31}",
INIT_32 => X"{[17:9]_INIT_32}",
INIT_33 => X"{[17:9]_INIT_33}",
INIT_34 => X"{[17:9]_INIT_34}",
INIT_35 => X"{[17:9]_INIT_35}",
INIT_36 => X"{[17:9]_INIT_36}",
INIT_37 => X"{[17:9]_INIT_37}",
INIT_38 => X"{[17:9]_INIT_38}",
INIT_39 => X"{[17:9]_INIT_39}",
INIT_3A => X"{[17:9]_INIT_3A}",
INIT_3B => X"{[17:9]_INIT_3B}",
INIT_3C => X"{[17:9]_INIT_3C}",
INIT_3D => X"{[17:9]_INIT_3D}",
INIT_3E => X"{[17:9]_INIT_3E}",
INIT_3F => X"{[17:9]_INIT_3F}",
INITP_00 => X"{[17:9]_INITP_00}",
INITP_01 => X"{[17:9]_INITP_01}",
INITP_02 => X"{[17:9]_INITP_02}",
INITP_03 => X"{[17:9]_INITP_03}",
INITP_04 => X"{[17:9]_INITP_04}",
INITP_05 => X"{[17:9]_INITP_05}",
INITP_06 => X"{[17:9]_INITP_06}",
INITP_07 => X"{[17:9]_INITP_07}")
port map( ADDRA => address_a,
ENA => enable,
CLKA => clk,
DOA => data_out_a_h(31 downto 0),
DOPA => data_out_a_h(35 downto 32),
DIA => data_in_a(31 downto 0),
DIPA => data_in_a(35 downto 32),
WEA => "0000",
REGCEA => '0',
RSTA => '0',
ADDRB => address_b,
ENB => enable_b,
CLKB => clk_b,
DOB => data_out_b_h(31 downto 0),
DOPB => data_out_b_h(35 downto 32),
DIB => data_in_b_h(31 downto 0),
DIPB => data_in_b_h(35 downto 32),
WEB => we_b,
REGCEB => '0',
RSTB => '0');
--
--
end low_level_definition;
--
------------------------------------------------------------------------------------
--
-- END OF FILE {name}.vhd
--
------------------------------------------------------------------------------------
|
-------------------------------------------------------------------------------
--! @file fetch_page_sram_dim.vhd
--! @author Johannes Walter <[email protected]>
--! @copyright CERN TE-EPC-CCE
--! @date 2014-11-19
--! @brief Prepare SRAM page with DIM data for NanoFIP communication.
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! @brief Entity declaration of fetch_page_sram_dim
--! @details
--! This component prepares the SRAM DIM log page for the NanoFIP response.
entity fetch_page_sram_dim is
port (
--! @name Clock and resets
--! @{
--! System clock
clk_i : in std_ulogic;
--! Asynchronous active-low reset
rst_asy_n_i : in std_ulogic;
--! Synchronous active-high reset
rst_syn_i : in std_ulogic;
--! @}
--! @name Commands
--! @{
--! Start flag
start_i : in std_ulogic;
--! Done flag
done_o : out std_ulogic;
--! @}
--! @name Memory page interface
--! @{
--! Address
page_addr_o : out std_ulogic_vector(5 downto 0);
--! Write enable
page_wr_en_o : out std_ulogic;
--! Data output
page_data_o : out std_ulogic_vector(7 downto 0);
--! Done flag
page_done_i : in std_ulogic;
--! @}
--! @name External SRAM data
--! @{
-- Address
sram_addr_o : out std_ulogic_vector(4 downto 0);
--! Read request
sram_rd_en_o : out std_ulogic;
--! Data input
sram_data_i : in std_ulogic_vector(15 downto 0);
--! Data input enable
sram_data_en_i : in std_ulogic);
--! @}
end entity fetch_page_sram_dim;
--! RTL implementation of fetch_page_sram_dim
architecture rtl of fetch_page_sram_dim is
---------------------------------------------------------------------------
--! @name Types and Constants
---------------------------------------------------------------------------
--! @{
type state_t is (IDLE, WRITE_LOW, WRITE_HIGH, DONE);
type reg_t is record
state : state_t;
addr : unsigned(5 downto 0);
data : std_ulogic_vector(7 downto 0);
wr_en : std_ulogic;
rd_en : std_ulogic;
done : std_ulogic;
end record;
constant init_c : reg_t := (
state => IDLE,
addr => (others => '0'),
data => (others => '0'),
wr_en => '0',
rd_en => '0',
done => '0');
--! @}
---------------------------------------------------------------------------
--! @name Internal Registers
---------------------------------------------------------------------------
--! @{
signal reg : reg_t;
--! @}
---------------------------------------------------------------------------
--! @name Internal Wires
---------------------------------------------------------------------------
--! @{
signal next_reg : reg_t;
--! @}
begin -- architecture rtl
---------------------------------------------------------------------------
-- Outputs
---------------------------------------------------------------------------
page_addr_o <= std_ulogic_vector(reg.addr);
page_wr_en_o <= reg.wr_en;
page_data_o <= reg.data;
sram_addr_o <= std_ulogic_vector(reg.addr(5 downto 1));
sram_rd_en_o <= reg.rd_en;
done_o <= reg.done;
---------------------------------------------------------------------------
-- Registers
---------------------------------------------------------------------------
regs : process (clk_i, rst_asy_n_i) is
procedure reset is
begin
reg <= init_c;
end procedure reset;
begin -- process regs
if rst_asy_n_i = '0' then
reset;
elsif rising_edge(clk_i) then
if rst_syn_i = '1' then
reset;
else
reg <= next_reg;
end if;
end if;
end process regs;
---------------------------------------------------------------------------
-- Combinatorics
---------------------------------------------------------------------------
comb : process (reg, start_i, page_done_i, sram_data_i, sram_data_en_i) is
begin -- comb
-- Defaults
next_reg <= reg;
next_reg.rd_en <= '0';
next_reg.wr_en <= '0';
next_reg.done <= '0';
case reg.state is
when IDLE =>
if start_i = '1' then
next_reg.rd_en <= '1';
next_reg.state <= WRITE_LOW;
end if;
when WRITE_LOW =>
if sram_data_en_i = '1' then
next_reg.data <= sram_data_i(7 downto 0);
next_reg.wr_en <= '1';
end if;
if page_done_i = '1' then
next_reg.addr <= reg.addr + 1;
next_reg.state <= WRITE_HIGH;
end if;
when WRITE_HIGH =>
next_reg.data <= sram_data_i(15 downto 8);
next_reg.wr_en <= '1';
next_reg.state <= DONE;
when DONE =>
if page_done_i = '1' then
if to_integer(reg.addr) < 63 then
next_reg.addr <= reg.addr + 1;
next_reg.rd_en <= '1';
next_reg.state <= WRITE_LOW;
else
next_reg <= init_c;
next_reg.done <= '1';
end if;
end if;
end case;
end process comb;
end architecture rtl;
|
entity bounds2 is
end entity;
architecture test of bounds2 is
begin
asssignment_delays: block
signal b1,b2,b3,b4,b5,b6,b7 : boolean;
begin
b1 <= true; -- OK
b2 <= true after 10 ns; -- OK
b3 <= true after 0 ns; -- OK
b4 <= true after -1 ns; -- Error
process
begin
b5 <= true; -- OK
b5 <= true after 0 ns; -- OK
b5 <= true after 1 fs; -- OK
b5 <= true after -1 fs; -- Error
wait;
end process;
b6 <= true after -10 ns when true else false;
b7 <= true when true else false after -10 ns;
end block;
rejection_limits: block
signal b1,b2,b3 : boolean;
begin
b1 <= reject 10 ns inertial true after 10 ns; -- OK
b2 <= reject -10 ns inertial true; -- Error
b3 <= reject 10 ns inertial true after 5 ns; -- Error
end block;
process
begin
wait for -10 ns; -- Error
wait;
end process;
default_values: block
type r is range 0 to 1;
constant ok1 : integer range 0 to 1 := 1; -- OK
constant ok2 : character range 'a' to 'z' := 'b'; -- OK
constant ok3 : real range 0.0 to 1.0 := 0.0; -- OK
constant ok4 : time range 10 ns to 20 ns := 10 ns; -- OK
constant ok5 : r := 0; -- OK
signal s : integer range 0 to 9 := 20; -- Error
constant c1 : character range 'a' to 'z' := 'Z'; -- Error
shared variable v : real range 0.0 to 5.0 := 10.0; -- Error
constant t : time range 10 ns to 10 us := 0 fs; -- Error
constant c2 : r := 10; -- Error
subtype subint is integer range 1 to 10;
procedure test(a : subint := 30) is
begin
end procedure;
function test(a : character range 'a' to 'b' := 'c') return integer is
begin
return 1;
end function;
component comp is
generic (
g2 : integer range 10 downto 0 := 20
);
port (
p2 : in integer range 0 to 1 := 2
);
end component;
begin
process is
variable v2 : real range 0.0 to 5.0 := 5.1; -- Error
begin
end process;
end block;
end architecture;
|
library IEEE;
use IEEE.std_logic_1164.all;
entity valid is
port
(
ip0: in std_logic; -- $SOL:0:0$
ip1: in std_logic; -- $SOL:1:0$
ip2: in std_logic;
ip3: in std_logic;
op0: out std_logic;
op1: out std_logic;
op2: out std_logic;
op3: out std_logic
);
end;
architecture RTL of valid is
signal s0: std_logic; -- $SOL:2:0$
signal s1: std_logic; -- $SOL:3:0$
signal s2: std_logic;
signal s3: std_logic;
begin
op0 <= ip1 when (ip0 = '0') else ip2;
process (s1, ip1, s2)
begin
if (ip1 = '0')
then
op0 <= '0';
else
op0 <= s2;
end if;
if (ip1 = '0')
then
op1 <= s1;
else
op1 <= '1';
end if;
end process;
s3 <= s1 when (s0 = '0') else s2;
process (s1, ip1, s2)
begin
if (s1 = '0')
then
op0 <= '0';
else
op0 <= s2;
end if;
if (s1 = '0')
then
op1 <= ip1;
else
op1 <= '1';
end if;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity FourBitAdder is
generic(WIDTH : integer := 4);
port(
A, B: IN std_logic_vector(WIDTH - 1 downto 0);
S: OUT std_logic_vector(WIDTH - 1 downto 0);
COUT: out std_logic
);
end FourBitAdder;
architecture impl of FourBitAdder is
component OneBitAdder is
port(
A, B, CIN: IN std_logic;
S, COUT: OUT std_logic
);
end component;
signal c: std_logic_vector(WIDTH downto 0);
begin
c(0)<= '0';
cout <= c(WIDTH);
SUM: for i in WIDTH - 1 downto 0 generate
ad : oneBitAdder port map(
a(i), b(i), c(i), s(i), c(i + 1)
);
end generate;
end; |
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench configuration
-- Copyright (C) 2009 Aeroflex Gaisler
------------------------------------------------------------------------------
library techmap;
use techmap.gencomp.all;
package config is
-- Technology and synthesis options
constant CFG_FABTECH : integer := cyclone3;
constant CFG_MEMTECH : integer := cyclone3;
constant CFG_PADTECH : integer := cyclone3;
constant CFG_NOASYNC : integer := 0;
constant CFG_SCAN : integer := 0;
-- Clock generator
constant CFG_CLKTECH : integer := cyclone3;
constant CFG_CLKMUL : integer := (10);
constant CFG_CLKDIV : integer := (10);
constant CFG_OCLKDIV : integer := 1;
constant CFG_OCLKBDIV : integer := 0;
constant CFG_OCLKCDIV : integer := 0;
constant CFG_PCIDLL : integer := 0;
constant CFG_PCISYSCLK: integer := 0;
constant CFG_CLK_NOFB : integer := 0;
-- LEON3 processor core
constant CFG_LEON3 : integer := 1;
constant CFG_NCPU : integer := (1);
constant CFG_NWIN : integer := (8);
constant CFG_V8 : integer := 16#32# + 4*0;
constant CFG_MAC : integer := 0;
constant CFG_BP : integer := 1;
constant CFG_SVT : integer := 0;
constant CFG_RSTADDR : integer := 16#00000#;
constant CFG_LDDEL : integer := (1);
constant CFG_NOTAG : integer := 0;
constant CFG_NWP : integer := (2);
constant CFG_PWD : integer := 0*2;
constant CFG_FPU : integer := 0 + 16*0 + 32*0;
constant CFG_GRFPUSH : integer := 0;
constant CFG_ICEN : integer := 1;
constant CFG_ISETS : integer := 2;
constant CFG_ISETSZ : integer := 8;
constant CFG_ILINE : integer := 8;
constant CFG_IREPL : integer := 0;
constant CFG_ILOCK : integer := 0;
constant CFG_ILRAMEN : integer := 0;
constant CFG_ILRAMADDR: integer := 16#8E#;
constant CFG_ILRAMSZ : integer := 1;
constant CFG_DCEN : integer := 1;
constant CFG_DSETS : integer := 2;
constant CFG_DSETSZ : integer := 4;
constant CFG_DLINE : integer := 4;
constant CFG_DREPL : integer := 0;
constant CFG_DLOCK : integer := 0;
constant CFG_DSNOOP : integer := 1*2 + 4*0;
constant CFG_DFIXED : integer := 16#0#;
constant CFG_DLRAMEN : integer := 0;
constant CFG_DLRAMADDR: integer := 16#8F#;
constant CFG_DLRAMSZ : integer := 1;
constant CFG_MMUEN : integer := 1;
constant CFG_ITLBNUM : integer := 8;
constant CFG_DTLBNUM : integer := 2;
constant CFG_TLB_TYPE : integer := 1 + 0*2;
constant CFG_TLB_REP : integer := 1;
constant CFG_MMU_PAGE : integer := 0;
constant CFG_DSU : integer := 1;
constant CFG_ITBSZ : integer := 2;
constant CFG_ATBSZ : integer := 2;
constant CFG_LEON3FT_EN : integer := 0;
constant CFG_IUFT_EN : integer := 0;
constant CFG_FPUFT_EN : integer := 0;
constant CFG_RF_ERRINJ : integer := 0;
constant CFG_CACHE_FT_EN : integer := 0;
constant CFG_CACHE_ERRINJ : integer := 0;
constant CFG_LEON3_NETLIST: integer := 0;
constant CFG_DISAS : integer := 0 + 0;
constant CFG_PCLOW : integer := 2;
-- AMBA settings
constant CFG_DEFMST : integer := (0);
constant CFG_RROBIN : integer := 1;
constant CFG_SPLIT : integer := 0;
constant CFG_FPNPEN : integer := 0;
constant CFG_AHBIO : integer := 16#FFF#;
constant CFG_APBADDR : integer := 16#800#;
constant CFG_AHB_MON : integer := 0;
constant CFG_AHB_MONERR : integer := 0;
constant CFG_AHB_MONWAR : integer := 0;
constant CFG_AHB_DTRACE : integer := 0;
-- DSU UART
constant CFG_AHB_UART : integer := 0;
-- JTAG based DSU interface
constant CFG_AHB_JTAG : integer := 1;
-- LEON2 memory controller
constant CFG_MCTRL_LEON2 : integer := 1;
constant CFG_MCTRL_RAM8BIT : integer := 0;
constant CFG_MCTRL_RAM16BIT : integer := 1;
constant CFG_MCTRL_5CS : integer := 0;
constant CFG_MCTRL_SDEN : integer := 0;
constant CFG_MCTRL_SEPBUS : integer := 0;
constant CFG_MCTRL_INVCLK : integer := 0;
constant CFG_MCTRL_SD64 : integer := 0;
constant CFG_MCTRL_PAGE : integer := 0 + 0;
-- SSRAM controller
constant CFG_SSCTRL : integer := 0;
constant CFG_SSCTRLP16 : integer := 0;
-- DDR controller
constant CFG_DDRSP : integer := 1;
constant CFG_DDRSP_INIT : integer := 1;
constant CFG_DDRSP_FREQ : integer := (100);
constant CFG_DDRSP_COL : integer := (9);
constant CFG_DDRSP_SIZE : integer := (32);
constant CFG_DDRSP_RSKEW : integer := (2500);
-- AHB ROM
constant CFG_AHBROMEN : integer := 0;
constant CFG_AHBROPIP : integer := 0;
constant CFG_AHBRODDR : integer := 16#000#;
constant CFG_ROMADDR : integer := 16#000#;
constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
-- AHB RAM
constant CFG_AHBRAMEN : integer := 0;
constant CFG_AHBRSZ : integer := 1;
constant CFG_AHBRADDR : integer := 16#A00#;
constant CFG_AHBRPIPE : integer := 0;
-- UART 1
constant CFG_UART1_ENABLE : integer := 1;
constant CFG_UART1_FIFO : integer := 8;
-- LEON3 interrupt controller
constant CFG_IRQ3_ENABLE : integer := 1;
constant CFG_IRQ3_NSEC : integer := 0;
-- Modular timer
constant CFG_GPT_ENABLE : integer := 1;
constant CFG_GPT_NTIM : integer := (2);
constant CFG_GPT_SW : integer := (8);
constant CFG_GPT_TW : integer := (32);
constant CFG_GPT_IRQ : integer := (8);
constant CFG_GPT_SEPIRQ : integer := 1;
constant CFG_GPT_WDOGEN : integer := 0;
constant CFG_GPT_WDOG : integer := 16#0#;
-- GPIO port
constant CFG_GRGPIO_ENABLE : integer := 1;
constant CFG_GRGPIO_IMASK : integer := 16#6#;
constant CFG_GRGPIO_WIDTH : integer := (3);
-- GRLIB debugging
constant CFG_DUART : integer := 0;
end;
|
-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2014.4 (win64) Build 1071353 Tue Nov 18 18:29:27 MST 2014
-- Date : Tue Jun 30 15:19:47 2015
-- Host : Vangelis-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- C:/Users/Vfor/Documents/GitHub/Minesweeper_Vivado/Minesweeper_Vivado.srcs/sources_1/ip/MemWinner/MemWinner_stub.vhdl
-- Design : MemWinner
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7a100tcsg324-3
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity MemWinner is
Port (
a : in STD_LOGIC_VECTOR ( 4 downto 0 );
clk : in STD_LOGIC;
spo : out STD_LOGIC_VECTOR ( 107 downto 0 )
);
end MemWinner;
architecture stub of MemWinner is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "a[4:0],clk,spo[107:0]";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "dist_mem_gen_v8_0,Vivado 2014.4";
begin
end;
|
--
-- This file is part of top_optim_sharp_driver
-- Copyright (C) 2011 Julien Thevenon ( julien_thevenon at yahoo.fr )
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>
--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity driver_compare is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC);
end driver_compare;
architecture Behavioral of driver_compare is
-- Signals for reference driver
signal reference_vsync : std_logic ;
signal reference_hsync : std_logic ;
signal reference_enable : std_logic ;
signal reference_x_out : std_logic_vector ( 9 downto 0);
signal reference_y_out : std_logic_vector ( 8 downto 0);
-- Signals for new driver
signal new_vsync : std_logic ;
signal new_hsync : std_logic ;
signal new_enable : std_logic ;
signal new_x_out : std_logic_vector ( 9 downto 0);
signal new_y_out : std_logic_vector ( 8 downto 0);
begin
Inst_reference_driver_sharp : entity work.driver_sharp(v1_0) PORT MAP(
clk => clk,
rst => rst,
vsync => reference_vsync,
hsync => reference_hsync,
enable => reference_enable,
x_out => reference_x_out,
y_out => reference_y_out
);
Inst_new_driver_sharp : entity work.driver_sharp(v1_4) PORT MAP(
clk => clk,
rst => rst,
vsync => new_vsync,
hsync => new_hsync,
enable => new_enable,
x_out => new_x_out,
y_out => new_y_out
);
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Extender is
generic (N : integer := 8);
port (A : in std_logic_vector(N-1 downto 0);
Y : out std_logic_vector((2*N)-1 downto 0)
);
end Extender;
architecture Behavioral of Extender is
begin
process(A)
begin
if (A(N-1) = '0') then
Y(N-1 downto 0) <= A;
Y((2*N)-1 downto N) <= (others => '0');
else
Y(N-1 downto 0) <= A;
Y((2*N)-1 downto N) <= (others => '1');
end if;
end process;
end Behavioral;
|
-- $Id: tbd_serport_uart_rxtx.vhd 417 2011-10-22 10:30:29Z mueller $
--
-- Copyright 2007-2011 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: tbd_serport_uart_rxtx - syn
-- Description: Wrapper for serport_uart_rxtx to avoid records. It
-- has a port interface which will not be modified by xst
-- synthesis (no records, no generic port).
--
-- Dependencies: serport_uart_rxtx
--
-- To test: serport_uart_rxtx
--
-- Target Devices: generic
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2007-10-27 92 9.2.02 J39 xc3s1000-4 69 122 0 - t 9.13
-- 2007-10-27 92 9.1 J30 xc3s1000-4 69 122 0 - t 9.13
-- 2007-10-27 92 8.2.03 I34 xc3s1000-4 73 152 0 81 s 9.30
-- 2007-10-27 92 8.1.03 I27 xc3s1000-4 73 125 0 - s 9.30
--
-- Tool versions: xst 8.2, 9.1, 9.2, 13.1; ghdl 0.18-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2007-10-21 91 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serport.all;
entity tbd_serport_uart_rxtx is -- serial port uart [tb design]
-- generic: CDWIDTH=13
port (
CLK : in slbit; -- clock
RESET : in slbit; -- reset
CLKDIV : in slv13; -- clock divider setting
RXSD : in slbit; -- receive serial data (uart view)
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXERR : out slbit; -- receiver data error (frame error)
RXACT : out slbit; -- receiver active
TXSD : out slbit; -- transmit serial data (uart view)
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit -- transmit busy
);
end tbd_serport_uart_rxtx;
architecture syn of tbd_serport_uart_rxtx is
begin
UART : serport_uart_rxtx
generic map (
CDWIDTH => 13)
port map (
CLK => CLK,
RESET => RESET,
CLKDIV => CLKDIV,
RXSD => RXSD,
RXDATA => RXDATA,
RXVAL => RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => TXDATA,
TXENA => TXENA,
TXBUSY => TXBUSY
);
end syn;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:10:20 05/21/2017
-- Design Name:
-- Module Name: mux_result - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity mux_result is
Port ( alusrc : in STD_LOGIC_VECTOR (1 downto 0);
mux_alures : in STD_LOGIC_VECTOR (15 downto 0);
mux_menres : in STD_LOGIC_VECTOR (15 downto 0);
mux_dataC : out STD_LOGIC_VECTOR (15 downto 0));
end mux_result;
architecture Behavioral of mux_result is
begin
process(alusrc)
begin
case alusrc is
when "00"=>
mux_dataC<=mux_alures;
when "01"=>
mux_dataC<=mux_menres;
when others=>null;
end case;
end process;
end Behavioral;
|
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = t1;
wait for 2 ns;
t0 := x'transaction;
report bit'image(t0);
assert t0 = not t1;
wait for 2 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = not t1;
wait;
end process;
end architecture;
|
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = t1;
wait for 2 ns;
t0 := x'transaction;
report bit'image(t0);
assert t0 = not t1;
wait for 2 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = not t1;
wait;
end process;
end architecture;
|
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = t1;
wait for 2 ns;
t0 := x'transaction;
report bit'image(t0);
assert t0 = not t1;
wait for 2 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = not t1;
wait;
end process;
end architecture;
|
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = t1;
wait for 2 ns;
t0 := x'transaction;
report bit'image(t0);
assert t0 = not t1;
wait for 2 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = not t1;
wait;
end process;
end architecture;
|
entity implicit2 is
end entity;
architecture test of implicit2 is
signal x : integer;
begin
x <= 1, 2 after 2 ns, 3 after 4 ns;
process is
variable t0, t1 : bit;
begin
t0 := x'transaction;
report bit'image(t0);
wait for 1 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = t1;
wait for 2 ns;
t0 := x'transaction;
report bit'image(t0);
assert t0 = not t1;
wait for 2 ns;
t1 := x'transaction;
report bit'image(t1);
assert t0 = not t1;
wait;
end process;
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design test bench
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
-- modified by Thomas Ameseder, Gleichmann Electronics 2004, 2005 to
-- support the use of an external AHB slave and different HPE board versions
------------------------------------------------------------------------------
-- further adapted from Hpe_compact to Hpe_mini (Feb. 2005)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.libdcom.all;
use gaisler.sim.all;
library techmap;
use techmap.gencomp.all;
library micron;
use micron.components.all;
use work.config.all; -- configuration
use work.debug.all;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
use grlib.devices.all;
entity testbench is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
clktech : integer := CFG_CLKTECH;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW;
clkperiod : integer := 20; -- system clock period
romwidth : integer := 16; -- rom data width (8/32)
romdepth : integer := 16; -- rom address depth
sramwidth : integer := 32; -- ram data width (8/16/32)
sramdepth : integer := 18; -- ram address depth
srambanks : integer := 2 -- number of ram banks
);
end;
architecture behav of testbench is
constant promfile : string := "prom.srec"; -- rom contents
constant sdramfile : string := "ram.srec"; -- sdram contents
signal clk : std_logic := '0';
signal Rst : std_logic := '0'; -- Reset
constant ct : integer := clkperiod/2;
signal address : std_logic_vector(23 downto 0);
signal data : std_logic_vector(31 downto 0);
signal romsn : std_logic_vector(1 downto 0);
signal oen : std_ulogic;
signal writen : std_ulogic;
signal iosn : std_ulogic;
-- ddr memory
signal ddr_clk : std_logic;
signal ddr_clkb : std_logic;
signal ddr_clk_fb : std_logic;
signal ddr_cke : std_logic;
signal ddr_csb : std_logic;
signal ddr_web : std_ulogic; -- ddr write enable
signal ddr_rasb : std_ulogic; -- ddr ras
signal ddr_casb : std_ulogic; -- ddr cas
signal ddr_dm : std_logic_vector (1 downto 0); -- ddr dm
signal ddr_dqs : std_logic_vector (1 downto 0); -- ddr dqs
signal ddr_ad : std_logic_vector (12 downto 0); -- ddr address
signal ddr_ba : std_logic_vector (1 downto 0); -- ddr bank address
signal ddr_dq : std_logic_vector (15 downto 0); -- ddr data
signal brdyn : std_ulogic;
signal bexcn : std_ulogic;
signal wdog : std_ulogic;
signal dsuen, dsutx, dsurx, dsubre, dsuact : std_ulogic;
signal dsurst : std_ulogic;
signal test : std_ulogic;
signal rtsn, ctsn : std_ulogic;
signal error : std_logic;
signal pio : std_logic_vector(15 downto 0);
signal GND : std_ulogic := '0';
signal VCC : std_ulogic := '1';
signal NC : std_ulogic := 'Z';
signal clk2 : std_ulogic := '1';
signal plllock : std_ulogic;
-- pulled up high, therefore std_logic
signal txd, rxd1 : std_logic;
signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic := '0';
signal erxd, etxd : std_logic_vector(3 downto 0) := (others => '0');
signal emdc, emdio : std_logic; --dummy signal for the mdc,mdio in the phy which is not used
constant lresp : boolean := false;
signal resoutn : std_logic;
signal dsubren : std_ulogic;
signal dsuactn : std_ulogic;
begin
dsubren <= not dsubre;
-- clock and reset
clk <= not clk after ct * 1 ns;
rst <= '1', '0' after 100 ns;
dsuen <= '0'; dsubre <= '0'; rxd1 <= 'H';
address(0) <= '0';
ddr_dqs <= (others => 'L');
d3 : entity work.leon3mp
port map (
reset => rst,
clk_50mhz => clk,
errorn => error,
address => address(23 downto 0),
data => data(31 downto 16),
testdata => data(15 downto 0),
ddr_clk0 => ddr_clk,
ddr_clk0b => ddr_clkb,
ddr_clk_fb => ddr_clk_fb,
ddr_cke0 => ddr_cke,
ddr_cs0b => ddr_csb,
ddr_web => ddr_web,
ddr_rasb => ddr_rasb,
ddr_casb => ddr_casb,
ddr_dm => ddr_dm,
ddr_dqs => ddr_dqs,
ddr_ad => ddr_ad,
ddr_ba => ddr_ba,
ddr_dq => ddr_dq,
dsuen => dsuen,
dsubre => dsubre,
-- dsuact => dsuactn,
dsutx => dsutx,
dsurx => dsurx,
oen => oen,
writen => writen,
iosn => iosn,
romsn => romsn(0),
utxd1 => txd,
urxd1 => txd,
emdio => emdio,
etx_clk => etx_clk,
erx_clk => erx_clk,
erxd => erxd,
erx_dv => erx_dv,
erx_er => erx_er,
erx_col => erx_col,
erx_crs => erx_crs,
etxd => etxd,
etx_en => etx_en,
etx_er => etx_er,
emdc => emdc
);
ddr_clk_fb <= ddr_clk;
-- u1 : mt46v16m16
-- generic map (index => -1, fname => sdramfile)
-- port map(
-- Dq => ddr_dq(15 downto 0), Dqs => ddr_dqs(1 downto 0), Addr => ddr_ad,
-- Ba => ddr_ba, Clk => ddr_clk, Clk_n => ddr_clkb, Cke => ddr_cke,
-- Cs_n => ddr_csb, Ras_n => ddr_rasb, Cas_n => ddr_casb, We_n => ddr_web,
-- Dm => ddr_dm(1 downto 0));
ddr0 : ddrram
generic map(width => 16, abits => 13, colbits => 9, rowbits => 13,
implbanks => 1, fname => sdramfile, speedbin => 1, density => 2)
port map (ck => ddr_clk, cke => ddr_cke, csn => ddr_csb,
rasn => ddr_rasb, casn => ddr_casb, wen => ddr_web,
dm => ddr_dm, ba => ddr_ba, a => ddr_ad, dq => ddr_dq,
dqs => ddr_dqs);
prom0 : for i in 0 to (romwidth/8)-1 generate
sr0 : sram generic map (index => i+4, abits => romdepth, fname => promfile)
port map (address(romdepth downto 1), data(31-i*8 downto 24-i*8), romsn(0),
writen, oen);
end generate;
-- phy0 : if CFG_GRETH > 0 generate
-- p0 : phy
-- port map(rst, led_cfg, open, etx_clk, erx_clk, erxd, erx_dv,
-- erx_er, erx_col, erx_crs, etxd, etx_en, etx_er, emdc);
-- end generate;
error <= 'H'; -- ERROR pull-up
iuerr : process
begin
wait for 5 us;
assert (to_X01(error) = '1')
report "*** IU in error mode, simulation halted ***"
severity failure;
end process;
test0 : grtestmod
port map ( rst, clk, error, address(21 downto 2), data,
iosn, oen, writen, brdyn);
data <= buskeep(data) after 5 ns;
dsucom : process
procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
variable w32 : std_logic_vector(31 downto 0);
variable c8 : std_logic_vector(7 downto 0);
constant txp : time := 160 * 1 ns;
begin
dsutx <= '1';
dsurst <= '1';
wait;
wait for 5000 ns;
txc(dsutx, 16#55#, txp); -- sync uart
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#ef#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
--
-- txc(dsutx, 16#c0#, txp);
-- txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
-- txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
--
-- txc(dsutx, 16#80#, txp);
-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
-- rxi(dsurx, w32, txp, lresp);
txc(dsutx, 16#a0#, txp);
txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
rxi(dsurx, w32, txp, lresp);
end;
begin
dsucfg(dsutx, dsurx);
wait;
end process;
end;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it10 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_samples_addr_read_reg_146 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_reg_156 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_2_fu_99_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_161 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_83_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_reg_167 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_reg_172 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_77_p0 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_77_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_83_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_83_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_fu_93_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_2_fu_99_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_reg_156_temp: signed (17-1 downto 0);
signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_ce : STD_LOGIC;
signal grp_fu_83_ce : STD_LOGIC;
signal grp_fu_88_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (16 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (16 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_U30 : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4
generic map (
ID => 30,
NUM_STAGE => 4,
din0_WIDTH => 17,
din1_WIDTH => 17,
dout_WIDTH => 17)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_77_p0,
din1 => grp_fu_77_p1,
ce => grp_fu_77_ce,
dout => grp_fu_77_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U31 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 31,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_83_p0,
din1 => grp_fu_83_p1,
ce => grp_fu_83_ce,
dout => grp_fu_83_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U32 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 32,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_88_p0,
din1 => grp_fu_88_p1,
ce => grp_fu_88_ce,
dout => grp_fu_88_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134;
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it9;
ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1;
ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3;
ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4;
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5;
ap_reg_ppstg_i_index_read_reg_134_pp0_it7 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
ap_reg_ppstg_i_index_read_reg_134_pp0_it8 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it7;
ap_reg_ppstg_i_index_read_reg_134_pp0_it9 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it8;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it5;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it7;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it8;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_index_read_reg_134 <= i_index;
i_sample_read_reg_128 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_addr_read_reg_146 <= indices_samples_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_1_reg_156 <= grp_fu_77_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_2_reg_161 <= tmp_2_fu_99_p2;
tmp_3_reg_172 <= grp_fu_88_p2;
tmp_4_reg_167 <= grp_fu_83_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
agg_result_index_write_assign_fu_111_p3 <=
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 when (tmp_2_reg_161(0) = '1') else
tmp_4_reg_167;
agg_result_sample_write_assign_fu_105_p3 <=
tmp_3_reg_172 when (tmp_2_reg_161(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it11, indices_samples_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it11) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_index_write_assign_fu_111_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_105_p3;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_77_ce assign process. --
grp_fu_77_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_77_ce <= ap_const_logic_1;
else
grp_fu_77_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_77_p0 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_146),17));
grp_fu_77_p1 <= ap_const_lv17_1FFFF;
-- grp_fu_83_ce assign process. --
grp_fu_83_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_83_ce <= ap_const_logic_1;
else
grp_fu_83_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_83_p0 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
grp_fu_83_p1 <= ap_const_lv16_1;
-- grp_fu_88_ce assign process. --
grp_fu_88_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_88_ce <= ap_const_logic_1;
else
grp_fu_88_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_88_p0 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
grp_fu_88_p1 <= ap_const_lv16_1;
indices_begin_address <= ap_const_lv32_0;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
indices_begin_req_write <= ap_const_logic_0;
indices_begin_rsp_read <= ap_const_logic_0;
indices_begin_size <= ap_const_lv32_0;
indices_samples_address <= tmp_9_fu_63_p1(32 - 1 downto 0);
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_req_write <= ap_const_logic_1;
else
indices_samples_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_rsp_read <= ap_const_logic_1;
else
indices_samples_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_samples_size <= ap_const_lv32_1;
indices_stride_address <= ap_const_lv32_0;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
indices_stride_req_write <= ap_const_logic_0;
indices_stride_rsp_read <= ap_const_logic_0;
indices_stride_size <= ap_const_lv32_0;
tmp_1_reg_156_temp <= signed(tmp_1_reg_156);
tmp_2_fu_99_p1 <= std_logic_vector(resize(tmp_1_reg_156_temp,18));
tmp_2_fu_99_p2 <= "1" when (signed(tmp_cast_fu_93_p1) < signed(tmp_2_fu_99_p1)) else "0";
tmp_9_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),64));
tmp_cast_fu_93_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it9),18));
end behav;
|
-- ==============================================================
-- RTL generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2013.4
-- Copyright (C) 2013 Xilinx Inc. All rights reserved.
--
-- ===========================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity sample_iterator_next is
port (
ap_clk : IN STD_LOGIC;
ap_rst : IN STD_LOGIC;
ap_start : IN STD_LOGIC;
ap_done : OUT STD_LOGIC;
ap_idle : OUT STD_LOGIC;
ap_ready : OUT STD_LOGIC;
indices_samples_req_din : OUT STD_LOGIC;
indices_samples_req_full_n : IN STD_LOGIC;
indices_samples_req_write : OUT STD_LOGIC;
indices_samples_rsp_empty_n : IN STD_LOGIC;
indices_samples_rsp_read : OUT STD_LOGIC;
indices_samples_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_samples_datain : IN STD_LOGIC_VECTOR (15 downto 0);
indices_samples_dataout : OUT STD_LOGIC_VECTOR (15 downto 0);
indices_samples_size : OUT STD_LOGIC_VECTOR (31 downto 0);
ap_ce : IN STD_LOGIC;
indices_begin_req_din : OUT STD_LOGIC;
indices_begin_req_full_n : IN STD_LOGIC;
indices_begin_req_write : OUT STD_LOGIC;
indices_begin_rsp_empty_n : IN STD_LOGIC;
indices_begin_rsp_read : OUT STD_LOGIC;
indices_begin_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_datain : IN STD_LOGIC_VECTOR (31 downto 0);
indices_begin_dataout : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_begin_size : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_req_din : OUT STD_LOGIC;
indices_stride_req_full_n : IN STD_LOGIC;
indices_stride_req_write : OUT STD_LOGIC;
indices_stride_rsp_empty_n : IN STD_LOGIC;
indices_stride_rsp_read : OUT STD_LOGIC;
indices_stride_address : OUT STD_LOGIC_VECTOR (31 downto 0);
indices_stride_datain : IN STD_LOGIC_VECTOR (7 downto 0);
indices_stride_dataout : OUT STD_LOGIC_VECTOR (7 downto 0);
indices_stride_size : OUT STD_LOGIC_VECTOR (31 downto 0);
i_index : IN STD_LOGIC_VECTOR (15 downto 0);
i_sample : IN STD_LOGIC_VECTOR (15 downto 0);
ap_return_0 : OUT STD_LOGIC_VECTOR (15 downto 0);
ap_return_1 : OUT STD_LOGIC_VECTOR (15 downto 0) );
end;
architecture behav of sample_iterator_next is
constant ap_const_logic_1 : STD_LOGIC := '1';
constant ap_const_logic_0 : STD_LOGIC := '0';
constant ap_ST_pp0_stg0_fsm_0 : STD_LOGIC_VECTOR (0 downto 0) := "0";
constant ap_const_lv32_0 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000000";
constant ap_const_lv32_1 : STD_LOGIC_VECTOR (31 downto 0) := "00000000000000000000000000000001";
constant ap_const_lv17_1FFFF : STD_LOGIC_VECTOR (16 downto 0) := "11111111111111111";
constant ap_const_lv16_1 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000001";
constant ap_const_lv16_0 : STD_LOGIC_VECTOR (15 downto 0) := "0000000000000000";
constant ap_const_lv8_0 : STD_LOGIC_VECTOR (7 downto 0) := "00000000";
signal ap_CS_fsm : STD_LOGIC_VECTOR (0 downto 0) := "0";
signal ap_reg_ppiten_pp0_it0 : STD_LOGIC;
signal ap_reg_ppiten_pp0_it1 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it2 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it3 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it4 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it5 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it6 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it7 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it8 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it9 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it10 : STD_LOGIC := '0';
signal ap_reg_ppiten_pp0_it11 : STD_LOGIC := '0';
signal i_sample_read_reg_128 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal i_index_read_reg_134 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it1 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it2 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it3 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it4 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it5 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it6 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it7 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it8 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it9 : STD_LOGIC_VECTOR (15 downto 0);
signal ap_reg_ppstg_i_index_read_reg_134_pp0_it10 : STD_LOGIC_VECTOR (15 downto 0);
signal indices_samples_addr_read_reg_146 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_p2 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_1_reg_156 : STD_LOGIC_VECTOR (16 downto 0);
signal tmp_2_fu_99_p2 : STD_LOGIC_VECTOR (0 downto 0);
signal tmp_2_reg_161 : STD_LOGIC_VECTOR (0 downto 0);
signal grp_fu_83_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_4_reg_167 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p2 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_3_reg_172 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_9_fu_63_p1 : STD_LOGIC_VECTOR (63 downto 0);
signal grp_fu_77_p0 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_77_p1 : STD_LOGIC_VECTOR (16 downto 0);
signal grp_fu_83_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_83_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p0 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_88_p1 : STD_LOGIC_VECTOR (15 downto 0);
signal tmp_cast_fu_93_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_2_fu_99_p1 : STD_LOGIC_VECTOR (17 downto 0);
signal tmp_1_reg_156_temp: signed (17-1 downto 0);
signal agg_result_index_write_assign_fu_111_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal agg_result_sample_write_assign_fu_105_p3 : STD_LOGIC_VECTOR (15 downto 0);
signal grp_fu_77_ce : STD_LOGIC;
signal grp_fu_83_ce : STD_LOGIC;
signal grp_fu_88_ce : STD_LOGIC;
signal ap_NS_fsm : STD_LOGIC_VECTOR (0 downto 0);
signal ap_sig_pprstidle_pp0 : STD_LOGIC;
component nfa_accept_samples_generic_hw_add_17ns_17s_17_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (16 downto 0);
din1 : IN STD_LOGIC_VECTOR (16 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (16 downto 0) );
end component;
component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4 IS
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER );
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR (15 downto 0);
din1 : IN STD_LOGIC_VECTOR (15 downto 0);
ce : IN STD_LOGIC;
dout : OUT STD_LOGIC_VECTOR (15 downto 0) );
end component;
begin
nfa_accept_samples_generic_hw_add_17ns_17s_17_4_U30 : component nfa_accept_samples_generic_hw_add_17ns_17s_17_4
generic map (
ID => 30,
NUM_STAGE => 4,
din0_WIDTH => 17,
din1_WIDTH => 17,
dout_WIDTH => 17)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_77_p0,
din1 => grp_fu_77_p1,
ce => grp_fu_77_ce,
dout => grp_fu_77_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U31 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 31,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_83_p0,
din1 => grp_fu_83_p1,
ce => grp_fu_83_ce,
dout => grp_fu_83_p2);
nfa_accept_samples_generic_hw_add_16ns_16ns_16_4_U32 : component nfa_accept_samples_generic_hw_add_16ns_16ns_16_4
generic map (
ID => 32,
NUM_STAGE => 4,
din0_WIDTH => 16,
din1_WIDTH => 16,
dout_WIDTH => 16)
port map (
clk => ap_clk,
reset => ap_rst,
din0 => grp_fu_88_p0,
din1 => grp_fu_88_p1,
ce => grp_fu_88_ce,
dout => grp_fu_88_p2);
-- the current state (ap_CS_fsm) of the state machine. --
ap_CS_fsm_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_CS_fsm <= ap_ST_pp0_stg0_fsm_0;
else
ap_CS_fsm <= ap_NS_fsm;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it1 assign process. --
ap_reg_ppiten_pp0_it1_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it1 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it1 <= ap_reg_ppiten_pp0_it0;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it10 assign process. --
ap_reg_ppiten_pp0_it10_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it10 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it10 <= ap_reg_ppiten_pp0_it9;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it11 assign process. --
ap_reg_ppiten_pp0_it11_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it11 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it11 <= ap_reg_ppiten_pp0_it10;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it2 assign process. --
ap_reg_ppiten_pp0_it2_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it2 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it2 <= ap_reg_ppiten_pp0_it1;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it3 assign process. --
ap_reg_ppiten_pp0_it3_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it3 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it3 <= ap_reg_ppiten_pp0_it2;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it4 assign process. --
ap_reg_ppiten_pp0_it4_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it4 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it4 <= ap_reg_ppiten_pp0_it3;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it5 assign process. --
ap_reg_ppiten_pp0_it5_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it5 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it5 <= ap_reg_ppiten_pp0_it4;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it6 assign process. --
ap_reg_ppiten_pp0_it6_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it6 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it6 <= ap_reg_ppiten_pp0_it5;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it7 assign process. --
ap_reg_ppiten_pp0_it7_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it7 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it7 <= ap_reg_ppiten_pp0_it6;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it8 assign process. --
ap_reg_ppiten_pp0_it8_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it8 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it8 <= ap_reg_ppiten_pp0_it7;
end if;
end if;
end if;
end process;
-- ap_reg_ppiten_pp0_it9 assign process. --
ap_reg_ppiten_pp0_it9_assign_proc : process(ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (ap_rst = '1') then
ap_reg_ppiten_pp0_it9 <= ap_const_logic_0;
else
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)) or not((ap_const_logic_1 = ap_ce)))))) then
ap_reg_ppiten_pp0_it9 <= ap_reg_ppiten_pp0_it8;
end if;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_reg_ppstg_i_index_read_reg_134_pp0_it1 <= i_index_read_reg_134;
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it9;
ap_reg_ppstg_i_index_read_reg_134_pp0_it2 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it1;
ap_reg_ppstg_i_index_read_reg_134_pp0_it3 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it2;
ap_reg_ppstg_i_index_read_reg_134_pp0_it4 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it3;
ap_reg_ppstg_i_index_read_reg_134_pp0_it5 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it4;
ap_reg_ppstg_i_index_read_reg_134_pp0_it6 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it5;
ap_reg_ppstg_i_index_read_reg_134_pp0_it7 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
ap_reg_ppstg_i_index_read_reg_134_pp0_it8 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it7;
ap_reg_ppstg_i_index_read_reg_134_pp0_it9 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it8;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it1 <= i_sample_read_reg_128;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it2 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it1;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it3 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it2;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it4 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it3;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it5 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it4;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it6 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it5;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it7 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it8 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it7;
ap_reg_ppstg_i_sample_read_reg_128_pp0_it9 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it8;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
i_index_read_reg_134 <= i_index;
i_sample_read_reg_128 <= i_sample;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_addr_read_reg_146 <= indices_samples_datain;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it9) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_1_reg_156 <= grp_fu_77_p2;
end if;
end if;
end process;
-- assign process. --
process (ap_clk)
begin
if (ap_clk'event and ap_clk = '1') then
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it10) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
tmp_2_reg_161 <= tmp_2_fu_99_p2;
tmp_3_reg_172 <= grp_fu_88_p2;
tmp_4_reg_167 <= grp_fu_83_p2;
end if;
end if;
end process;
-- the next state (ap_NS_fsm) of the state machine. --
ap_NS_fsm_assign_proc : process (ap_start , ap_CS_fsm , ap_reg_ppiten_pp0_it0 , ap_reg_ppiten_pp0_it5 , indices_samples_rsp_empty_n , ap_ce , ap_sig_pprstidle_pp0)
begin
case ap_CS_fsm is
when ap_ST_pp0_stg0_fsm_0 =>
ap_NS_fsm <= ap_ST_pp0_stg0_fsm_0;
when others =>
ap_NS_fsm <= "X";
end case;
end process;
agg_result_index_write_assign_fu_111_p3 <=
ap_reg_ppstg_i_index_read_reg_134_pp0_it10 when (tmp_2_reg_161(0) = '1') else
tmp_4_reg_167;
agg_result_sample_write_assign_fu_105_p3 <=
tmp_3_reg_172 when (tmp_2_reg_161(0) = '1') else
ap_const_lv16_0;
-- ap_done assign process. --
ap_done_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it11, indices_samples_rsp_empty_n, ap_ce)
begin
if (((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0)) or ((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it11) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce)))) then
ap_done <= ap_const_logic_1;
else
ap_done <= ap_const_logic_0;
end if;
end process;
-- ap_idle assign process. --
ap_idle_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10, ap_reg_ppiten_pp0_it11)
begin
if ((not((ap_const_logic_1 = ap_start)) and (ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it11))) then
ap_idle <= ap_const_logic_1;
else
ap_idle <= ap_const_logic_0;
end if;
end process;
-- ap_ready assign process. --
ap_ready_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
ap_ready <= ap_const_logic_1;
else
ap_ready <= ap_const_logic_0;
end if;
end process;
ap_reg_ppiten_pp0_it0 <= ap_start;
ap_return_0 <= agg_result_index_write_assign_fu_111_p3;
ap_return_1 <= agg_result_sample_write_assign_fu_105_p3;
-- ap_sig_pprstidle_pp0 assign process. --
ap_sig_pprstidle_pp0_assign_proc : process(ap_start, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it1, ap_reg_ppiten_pp0_it2, ap_reg_ppiten_pp0_it3, ap_reg_ppiten_pp0_it4, ap_reg_ppiten_pp0_it5, ap_reg_ppiten_pp0_it6, ap_reg_ppiten_pp0_it7, ap_reg_ppiten_pp0_it8, ap_reg_ppiten_pp0_it9, ap_reg_ppiten_pp0_it10)
begin
if (((ap_const_logic_0 = ap_reg_ppiten_pp0_it0) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it1) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it2) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it3) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it4) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it5) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it6) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it7) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it8) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it9) and (ap_const_logic_0 = ap_reg_ppiten_pp0_it10) and (ap_const_logic_0 = ap_start))) then
ap_sig_pprstidle_pp0 <= ap_const_logic_1;
else
ap_sig_pprstidle_pp0 <= ap_const_logic_0;
end if;
end process;
-- grp_fu_77_ce assign process. --
grp_fu_77_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_77_ce <= ap_const_logic_1;
else
grp_fu_77_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_77_p0 <= std_logic_vector(resize(unsigned(indices_samples_addr_read_reg_146),17));
grp_fu_77_p1 <= ap_const_lv17_1FFFF;
-- grp_fu_83_ce assign process. --
grp_fu_83_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_83_ce <= ap_const_logic_1;
else
grp_fu_83_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_83_p0 <= ap_reg_ppstg_i_index_read_reg_134_pp0_it6;
grp_fu_83_p1 <= ap_const_lv16_1;
-- grp_fu_88_ce assign process. --
grp_fu_88_ce_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
grp_fu_88_ce <= ap_const_logic_1;
else
grp_fu_88_ce <= ap_const_logic_0;
end if;
end process;
grp_fu_88_p0 <= ap_reg_ppstg_i_sample_read_reg_128_pp0_it6;
grp_fu_88_p1 <= ap_const_lv16_1;
indices_begin_address <= ap_const_lv32_0;
indices_begin_dataout <= ap_const_lv32_0;
indices_begin_req_din <= ap_const_logic_0;
indices_begin_req_write <= ap_const_logic_0;
indices_begin_rsp_read <= ap_const_logic_0;
indices_begin_size <= ap_const_lv32_0;
indices_samples_address <= tmp_9_fu_63_p1(32 - 1 downto 0);
indices_samples_dataout <= ap_const_lv16_0;
indices_samples_req_din <= ap_const_logic_0;
-- indices_samples_req_write assign process. --
indices_samples_req_write_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_req_write <= ap_const_logic_1;
else
indices_samples_req_write <= ap_const_logic_0;
end if;
end process;
-- indices_samples_rsp_read assign process. --
indices_samples_rsp_read_assign_proc : process(ap_start, ap_CS_fsm, ap_reg_ppiten_pp0_it0, ap_reg_ppiten_pp0_it5, indices_samples_rsp_empty_n, ap_ce)
begin
if (((ap_ST_pp0_stg0_fsm_0 = ap_CS_fsm) and (ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and not((((ap_const_logic_1 = ap_reg_ppiten_pp0_it0) and (ap_start = ap_const_logic_0)) or ((ap_const_logic_1 = ap_reg_ppiten_pp0_it5) and (indices_samples_rsp_empty_n = ap_const_logic_0)))) and (ap_const_logic_1 = ap_ce))) then
indices_samples_rsp_read <= ap_const_logic_1;
else
indices_samples_rsp_read <= ap_const_logic_0;
end if;
end process;
indices_samples_size <= ap_const_lv32_1;
indices_stride_address <= ap_const_lv32_0;
indices_stride_dataout <= ap_const_lv8_0;
indices_stride_req_din <= ap_const_logic_0;
indices_stride_req_write <= ap_const_logic_0;
indices_stride_rsp_read <= ap_const_logic_0;
indices_stride_size <= ap_const_lv32_0;
tmp_1_reg_156_temp <= signed(tmp_1_reg_156);
tmp_2_fu_99_p1 <= std_logic_vector(resize(tmp_1_reg_156_temp,18));
tmp_2_fu_99_p2 <= "1" when (signed(tmp_cast_fu_93_p1) < signed(tmp_2_fu_99_p1)) else "0";
tmp_9_fu_63_p1 <= std_logic_vector(resize(unsigned(i_index),64));
tmp_cast_fu_93_p1 <= std_logic_vector(resize(unsigned(ap_reg_ppstg_i_sample_read_reg_128_pp0_it9),18));
end behav;
|
/*
This file is part of fpgaNES.
fpgaNES is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
fpgaNES is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with fpgaNES. If not, see <http://www.gnu.org/licenses/>.
*/
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package common is
type flags_t is record
n : std_logic;
v : std_logic;
d : std_logic;
i : std_logic;
z : std_logic;
c : std_logic;
end record;
type mode_t is (imp, imm, acc, zpn, zpx, zpy, abn, abx, aby, inx, iny, ind, rel);
type instruction_t is (unk, nop, lda, ldx, ldy, tax, tay, txa, tya, tsx, txs, clc, cli, clv, cld, secr, sed, sei, adc, sbc, inc, inx, iny, dec, dex, dey, cpx, cpy, bcc, bcs, beq, bne, bmi, bpl, bvc, bvs, jsr, rts, rti, ora, and_i, eor, cmp, sta, stx, sty, pha, php, pla, plp, rol_i, ror_i, lsr, asl, jmp, bit_i, brk);
type pc_op_t is (nop, inc, split, pla, pha, daq, enb);
type in_op_t is (nop, ena, alq, ald, fff);
type out_op_t is (nop, ena, din, pch, pcl, arg, xrg, yrg, flg);
type reg_op_t is (nop, arg, xrg, yrg, srg);
type alu_op_t is (psa, add, adc, sub, sbc, ada, ora, eor, rla, rra, lsr, asl);
type addr_op_t is (nop, zaq, daq, aqd, div, oaq, oad, zvl, adv, vaq);
type ctrl_op_t is (nop, alc, bcc, bcs, beq, bne, bmi, bpl, bvc, bvs, don);
type flags_op_t is (nop, din, nz, nzc, nzv, nvzc, clc, cli, clv, cld, stc, sed, sei);
type alu_inp_t is (din, val, arg, xrg, yrg, srg, one, pcl, pch, aci, alq, auc, brk);
type video_mode_t is (ntsc, pal);
-- Constants
constant N_FLAG : integer := 7;
constant V_FLAG : integer := 6;
constant D_FLAG : integer := 3;
constant I_FLAG : integer := 2;
constant Z_FLAG : integer := 1;
constant C_FLAG : integer := 0;
-- Functions
function to_std_logic_vector(a: flags_t; b: std_logic) return std_logic_vector;
function reverse_vector(a: in std_logic_vector) return std_logic_vector;
end common;
package body common is
function to_std_logic_vector(a: flags_t; b: std_logic) return std_logic_vector is
begin
return a.n & a.v & '1' & b & a.d & a.i & a.z & a.c;
end;
function reverse_vector(a: in std_logic_vector) return std_logic_vector is
variable result: std_logic_vector(a'range);
alias aa: std_logic_vector(a'reverse_range) is a;
begin
for i in aa'range loop
result(i) := aa(i);
end loop;
return result;
end;
end package body;
|
--
-- BananaCore - A processor written in VHDL
--
-- Created by Rogiel Sulzbach.
-- Copyright (c) 2014-2015 Rogiel Sulzbach. All rights reserved.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_1164.std_logic;
library BananaCore;
use BananaCore.Core.all;
use BananaCore.Memory.all;
use BananaCore.RegisterPackage.all;
-- The {EntityName} entity
entity {EntityName} is
port(
-- the processor main clock
clock: in BananaCore.Core.Clock;
-- enables the instruction
enable: in std_logic;
-- the first register to operate on (argument 0)
arg0_address: in RegisterAddress;
-- the first register to operate on (argument 1)
arg1_address: in RegisterAddress;
-- a bus indicating if the instruction is ready or not
instruction_ready: out std_logic := '0';
------------------------------------------
-- MEMORY BUS
------------------------------------------
-- the address to read/write memory from/to
memory_address: out MemoryAddress := (others => '0');
-- the memory being read to
memory_data_read: in MemoryData;
-- the memory being written to
memory_data_write: out MemoryData := (others => '0');
-- the operation to perform on the memory
memory_operation: out MemoryOperation := MEMORY_OP_DISABLED;
-- a flag indicating if a memory operation should be performed
memory_enable: out std_logic;
-- a flag indicating if a memory operation has completed
memory_ready: in std_logic;
------------------------------------------
-- REGISTER BUS
------------------------------------------
-- the processor register address bus
register_address: out RegisterAddress := (others => '0');
-- the processor register data bus
register_data_read: in RegisterData;
-- the processor register data bus
register_data_write: out RegisterData := (others => '0');
-- the processor register operation signal
register_operation: out RegisterOperation := OP_REG_DISABLED;
-- the processor register enable signal
register_enable: out std_logic := '0';
------------------------------------------
-- IO ports
------------------------------------------
-- io port: port0
port0: in IOPortData;
-- io port: port1
port1: out IOPortData := (others => '0')
);
end {EntityName};
architecture {EntityName}Impl of {EntityName} is
type state_type is (
fetch_arg0,
store_arg0,
fetch_arg1,
store_arg1,
execute,
store_result,
complete
);
signal state: state_type := fetch_arg0;
signal arg0: RegisterData;
signal arg1: RegisterData;
signal result: RegisterData;
begin
process (clock) begin
if clock'event and clock = '1' then
if enable = '1' then
case state is
when fetch_arg0 =>
instruction_ready <= '0';
register_address <= arg0_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg0;
when store_arg0 =>
arg0 <= register_data_read;
state <= fetch_arg1;
when fetch_arg1 =>
register_address <= arg1_address;
register_operation <= OP_REG_GET;
register_enable <= '1';
state <= store_arg1;
when store_arg1 =>
arg1 <= register_data_read;
state <= execute;
register_enable <= '0';
when execute =>
-- TODO implement instruction here
state <= store_result;
when store_result =>
register_address <= AccumulatorRegister;
register_operation <= OP_REG_SET;
register_data_write <= result;
register_enable <= '1';
instruction_ready <= '1';
state <= complete;
when complete =>
state <= complete;
end case;
else
instruction_ready <= '0';
state <= fetch_arg0;
end if;
end if;
end process;
end {EntityName}Impl; |
-- $Id: $
-- File name: tb_tristate.vhd
-- Created: 4/19/2012
-- Author: John Wyant
-- Lab Section: 337-02
-- Version: 1.0 Initial Test Bench
library ieee;
--library gold_lib; --UNCOMMENT if you're using a GOLD model
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--use gold_lib.all; --UNCOMMENT if you're using a GOLD model
entity tb_tristate is
end tb_tristate;
architecture TEST of tb_tristate is
function UINT_TO_STD_LOGIC( X: INTEGER; NumBits: INTEGER )
return STD_LOGIC_VECTOR is
begin
return std_logic_vector(to_unsigned(X, NumBits));
end;
function STD_LOGIC_TO_UINT( X: std_logic_vector)
return integer is
begin
return to_integer(unsigned(x));
end;
component tristate
PORT(
lock : in std_logic;
interceptorInput : out std_logic;
interceptorOutput : in std_logic;
dataLine : inout std_logic
);
end component;
-- Insert signals Declarations here
signal lock : std_logic;
signal interceptorInput : std_logic;
signal interceptorOutput : std_logic;
signal dataLine : std_logic;
-- signal <name> : <type>;
begin
DUT: tristate port map(
lock => lock,
interceptorInput => interceptorInput,
interceptorOutput => interceptorOutput,
dataLine => dataLine
);
-- GOLD: <GOLD_NAME> port map(<put mappings here>);
process
begin
-- Insert TEST BENCH Code Here
-- interceptor drives bus
lock <= '1';
interceptorOutput <= '1';
dataLine <= 'Z';
wait for 70 ns;
interceptorOutput <= '0';
wait for 70 ns;
interceptorOutput <= '1';
wait for 70 ns;
interceptorOutput <= '0';
wait for 70 ns;
interceptorOutput <= '1';
-- usb drives bus
lock <= '0';
dataLine <= '1';
wait for 70 ns;
dataLine <= '0';
wait for 70 ns;
dataLine <= '1';
wait for 70 ns;
dataLine <= '0';
-- interceptor drives bus
lock <= '1';
dataLine <= 'Z';
wait for 70 ns;
end process;
end TEST; |
-- Twofish_ecb_tbl_testbench_192bits.vhd
-- Copyright (C) 2006 Spyros Ninos
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this library; see the file COPYING. If not, write to:
--
-- Free Software Foundation
-- 59 Temple Place - Suite 330
-- Boston, MA 02111-1307, USA.
--
-- description : this file is the testbench for the TABLES KAT of the twofish cipher with 192 bit key
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_textio.all;
use ieee.std_logic_arith.all;
use std.textio.all;
entity tbl_testbench192 is
end tbl_testbench192;
architecture tbl_encryption192_testbench_arch of tbl_testbench192 is
component reg128
port (
in_reg128 : in std_logic_vector(127 downto 0);
out_reg128 : out std_logic_vector(127 downto 0);
enable_reg128, reset_reg128, clk_reg128 : in std_logic
);
end component;
component twofish_keysched192
port (
odd_in_tk192,
even_in_tk192 : in std_logic_vector(7 downto 0);
in_key_tk192 : in std_logic_vector(191 downto 0);
out_key_up_tk192,
out_key_down_tk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_whit_keysched192
port (
in_key_twk192 : in std_logic_vector(191 downto 0);
out_K0_twk192,
out_K1_twk192,
out_K2_twk192,
out_K3_twk192,
out_K4_twk192,
out_K5_twk192,
out_K6_twk192,
out_K7_twk192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_encryption_round192
port (
in1_ter192,
in2_ter192,
in3_ter192,
in4_ter192,
in_Sfirst_ter192,
in_Ssecond_ter192,
in_Sthird_ter192,
in_key_up_ter192,
in_key_down_ter192 : in std_logic_vector(31 downto 0);
out1_ter192,
out2_ter192,
out3_ter192,
out4_ter192 : out std_logic_vector(31 downto 0)
);
end component;
component twofish_data_input
port (
in_tdi : in std_logic_vector(127 downto 0);
out_tdi : out std_logic_vector(127 downto 0)
);
end component;
component twofish_data_output
port (
in_tdo : in std_logic_vector(127 downto 0);
out_tdo : out std_logic_vector(127 downto 0)
);
end component;
component demux128
port ( in_demux128 : in std_logic_vector(127 downto 0);
out1_demux128, out2_demux128 : out std_logic_vector(127 downto 0);
selection_demux128 : in std_logic
);
end component;
component mux128
port ( in1_mux128, in2_mux128 : in std_logic_vector(127 downto 0);
selection_mux128 : in std_logic;
out_mux128 : out std_logic_vector(127 downto 0)
);
end component;
component twofish_S192
port (
in_key_ts192 : in std_logic_vector(191 downto 0);
out_Sfirst_ts192,
out_Ssecond_ts192,
out_Sthird_ts192 : out std_logic_vector(31 downto 0)
);
end component;
FILE input_file : text is in "twofish_ecb_tbl_testvalues_192bits.txt";
FILE output_file : text is out "twofish_ecb_tbl_192bits_results.txt";
-- we create the functions that transform a number to text
-- transforming a signle digit to a character
function digit_to_char(number : integer range 0 to 9) return character is
begin
case number is
when 0 => return '0';
when 1 => return '1';
when 2 => return '2';
when 3 => return '3';
when 4 => return '4';
when 5 => return '5';
when 6 => return '6';
when 7 => return '7';
when 8 => return '8';
when 9 => return '9';
end case;
end;
-- transforming multi-digit number to text
function to_text(int_number : integer range 1 to 50) return string is
variable our_text : string (1 to 3) := (others => ' ');
variable hundreds,
tens,
ones : integer range 0 to 9;
begin
ones := int_number mod 10;
tens := ((int_number mod 100) - ones) / 10;
hundreds := (int_number - (int_number mod 100)) / 100;
our_text(1) := digit_to_char(hundreds);
our_text(2) := digit_to_char(tens);
our_text(3) := digit_to_char(ones);
return our_text;
end;
signal odd_number,
even_number : std_logic_vector(7 downto 0);
signal input_data,
output_data,
to_encr_reg128,
from_tdi_to_xors,
to_output_whit_xors,
from_xors_to_tdo,
to_mux, to_demux,
from_input_whit_xors,
to_round,
to_input_mux : std_logic_vector(127 downto 0) ;
signal twofish_key : std_logic_vector(191 downto 0);
signal key_up,
key_down,
Sfirst,
Ssecond,
Sthird,
from_xor0,
from_xor1,
from_xor2,
from_xor3,
K0,K1,K2,K3,
K4,K5,K6,K7 : std_logic_vector(31 downto 0);
signal clk : std_logic := '0';
signal mux_selection : std_logic := '0';
signal demux_selection: std_logic := '0';
signal enable_encr_reg : std_logic := '0';
signal reset : std_logic := '0';
signal enable_round_reg : std_logic := '0';
-- begin the testbench arch description
begin
-- getting data to encrypt
data_input: twofish_data_input
port map (
in_tdi => input_data,
out_tdi => from_tdi_to_xors
);
-- producing whitening keys K0..7
the_whitening_step: twofish_whit_keysched192
port map (
in_key_twk192 => twofish_key,
out_K0_twk192 => K0,
out_K1_twk192 => K1,
out_K2_twk192 => K2,
out_K3_twk192 => K3,
out_K4_twk192 => K4,
out_K5_twk192 => K5,
out_K6_twk192 => K6,
out_K7_twk192 => K7
);
-- performing the input whitening XORs
from_xor0 <= K0 XOR from_tdi_to_xors(127 downto 96);
from_xor1 <= K1 XOR from_tdi_to_xors(95 downto 64);
from_xor2 <= K2 XOR from_tdi_to_xors(63 downto 32);
from_xor3 <= K3 XOR from_tdi_to_xors(31 downto 0);
from_input_whit_xors <= from_xor0 & from_xor1 & from_xor2 & from_xor3;
round_reg: reg128
port map ( in_reg128 => from_input_whit_xors,
out_reg128 => to_input_mux,
enable_reg128 => enable_round_reg,
reset_reg128 => reset,
clk_reg128 => clk );
input_mux: mux128
port map ( in1_mux128 => to_input_mux,
in2_mux128 => to_mux,
out_mux128 => to_round,
selection_mux128 => mux_selection
);
-- creating a round
the_keysched_of_the_round: twofish_keysched192
port map (
odd_in_tk192 => odd_number,
even_in_tk192 => even_number,
in_key_tk192 => twofish_key,
out_key_up_tk192 => key_up,
out_key_down_tk192 => key_down
);
producing_the_Skeys: twofish_S192
port map (
in_key_ts192 => twofish_key,
out_Sfirst_ts192 => Sfirst,
out_Ssecond_ts192 => Ssecond,
out_Sthird_ts192 => Sthird
);
the_encryption_circuit: twofish_encryption_round192
port map (
in1_ter192 => to_round(127 downto 96),
in2_ter192 => to_round(95 downto 64),
in3_ter192 => to_round(63 downto 32),
in4_ter192 => to_round(31 downto 0),
in_Sfirst_ter192 => Sfirst,
in_Ssecond_ter192 => Ssecond,
in_Sthird_ter192 => Sthird,
in_key_up_ter192 => key_up,
in_key_down_ter192 => key_down,
out1_ter192 => to_encr_reg128(127 downto 96),
out2_ter192 => to_encr_reg128(95 downto 64),
out3_ter192 => to_encr_reg128(63 downto 32),
out4_ter192 => to_encr_reg128(31 downto 0)
);
encr_reg: reg128
port map ( in_reg128 => to_encr_reg128,
out_reg128 => to_demux,
enable_reg128 => enable_encr_reg,
reset_reg128 => reset,
clk_reg128 => clk );
output_demux: demux128
port map ( in_demux128 => to_demux,
out1_demux128 => to_output_whit_xors,
out2_demux128 => to_mux,
selection_demux128 => demux_selection );
-- don't forget the last swap !!!
from_xors_to_tdo(127 downto 96) <= K4 XOR to_output_whit_xors(63 downto 32);
from_xors_to_tdo(95 downto 64) <= K5 XOR to_output_whit_xors(31 downto 0);
from_xors_to_tdo(63 downto 32) <= K6 XOR to_output_whit_xors(127 downto 96);
from_xors_to_tdo(31 downto 0) <= K7 XOR to_output_whit_xors(95 downto 64);
taking_the_output: twofish_data_output
port map (
in_tdo => from_xors_to_tdo,
out_tdo => output_data
);
-- we create the clock
clk <= not clk after 50 ns; -- period 100 ns
tbl_proc: process
variable key_f, -- key input from file
pt_f, -- plaintext from file
ct_f : line; -- ciphertext from file
variable pt_v , -- plaintext vector
ct_v : std_logic_vector(127 downto 0); -- ciphertext vector
variable key_v : std_logic_vector(191 downto 0); -- key vector input
variable counter : integer range 1 to 50 := 1;
variable round : integer range 0 to 16 := 0;
begin
while not endfile(input_file) loop
readline(input_file, key_f);
readline(input_file, pt_f);
readline(input_file,ct_f);
hread(key_f,key_v);
hread(pt_f,pt_v);
hread(ct_f,ct_v);
twofish_key <= key_v;
input_data <= pt_v;
wait for 25 ns;
reset <= '1';
wait for 50 ns;
reset <= '0';
mux_selection <= '0';
demux_selection <= '1';
enable_encr_reg <= '0';
enable_round_reg <= '0';
wait for 50 ns;
enable_round_reg <= '1';
wait for 50 ns;
enable_round_reg <= '0';
-- the first round
even_number <= "00001000"; -- 8
odd_number <= "00001001"; -- 9
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
demux_selection <= '1';
mux_selection <= '1';
-- the rest 15 rounds
for round in 1 to 15 loop
even_number <= conv_std_logic_vector(((round*2)+8), 8);
odd_number <= conv_std_logic_vector(((round*2)+9), 8);
wait for 50 ns;
enable_encr_reg <= '1';
wait for 50 ns;
enable_encr_reg <= '0';
end loop;
-- taking final results
demux_selection <= '0';
wait for 25 ns;
assert (ct_v = output_data) report "file entry and encryption result DO NOT match!!! :( " severity failure;
assert (ct_v /= output_data) report "Encryption I=" & to_text(counter) &" OK" severity note;
counter := counter+1;
hwrite(pt_f,input_data);
hwrite(ct_f,output_data);
hwrite(key_f,key_v);
writeline(output_file,key_f);
writeline(output_file,pt_f);
writeline(output_file,ct_f);
end loop;
assert false report "***** Tables Known Answer Test with 192 bits key size ended succesfully! :) *****" severity failure;
end process tbl_proc;
end tbl_encryption192_testbench_arch;
|
library ieee;
use ieee.std_logic_1164.all;
entity IDEX_register is
port(Clk, reset : in std_logic;
sign_extended_i, pc_i, data1_i, data2_i: in std_logic_vector(31 downto 0);
sign_extended_o, pc_o, data1_o, data2_o: out std_logic_vector(31 downto 0);
register_address_0_i, register_address_1_i: in std_logic_vector(4 downto 0);
register_address_0_o, register_address_1_o: out std_logic_vector(4 downto 0);
RegDst_i, Jump_i, Branch_i, MemRead_i, MemtoReg_i, ALUOp_i, MemWrite_i, ALUSrc_i, RegWrite_i: in std_logic;
RegDst_o, Jump_o, Branch_o, MemRead_o, MemtoReg_o, ALUOp_o, MemWrite_o, ALUSrc_o, RegWrite_o: out std_logic);
end IDEX_register;
architecture IDEX_register_a of IDEX_register is
type tmp_array is array (0 to 1) of std_logic_vector(31 downto 0);
type tmp_array_short is array (0 to 1) of std_logic_vector(4 downto 0);
type tmp_array_logic is array (0 to 1) of std_logic;
signal pc_tmp, sign_extended_tmp, data1_tmp, data2_tmp: tmp_array;
signal register_address_0_tmp, register_address_1_tmp: tmp_array_short;
signal RegDst_tmp, Jump_tmp ,Branch_tmp, MemRead_tmp, MemtoReg_tmp, ALUOp_tmp, MemWrite_tmp, ALUSrc_tmp, RegWrite_tmp: tmp_array_logic;
begin
process (Clk)
begin
if (reset = '1') then
pc_tmp(1) <= (others => '0');
sign_extended_tmp(1) <= (others => '0');
data1_tmp(1) <= (others => '0');
data2_tmp(1) <= (others => '0');
register_address_0_tmp(1) <= (others => '0');
register_address_1_tmp(1) <= (others => '0');
RegDst_tmp(1) <= '0';
Jump_tmp(1) <= '0';
Branch_tmp(1) <= '0';
MemRead_tmp(1) <= '0';
MemtoReg_tmp(1) <= '0';
ALUOp_tmp(1) <= '0';
MemWrite_tmp(1) <= '0';
ALUSrc_tmp(1) <= '0';
RegWrite_tmp(1) <= '0';
elsif (rising_edge(clk)) then
pc_tmp(0) <= pc_tmp(1);
sign_extended_tmp(0) <= sign_extended_tmp(1);
data1_tmp(0) <= data1_tmp(1);
data2_tmp(0) <= data2_tmp(1);
register_address_0_tmp(0) <= register_address_0_tmp(1);
register_address_1_tmp(0) <= register_address_1_tmp(1);
RegDst_tmp(0) <= RegDst_tmp(1);
Jump_tmp(0) <= Jump_tmp(1);
Branch_tmp(0) <= Branch_tmp(1);
MemRead_tmp(0) <= MemRead_tmp(1);
MemtoReg_tmp(0) <= MemtoReg_tmp(1);
ALUOp_tmp(0) <= ALUOp_tmp(1);
MemWrite_tmp(0) <= MemWrite_tmp(1);
ALUSrc_tmp(0) <= ALUSrc_tmp(1);
RegWrite_tmp(0) <= RegWrite_tmp(1);
pc_tmp(1) <= pc_i;
sign_extended_tmp(1) <= sign_extended_i;
data1_tmp(1) <= data1_i;
data2_tmp(1) <= data2_i;
register_address_0_tmp(1) <= register_address_0_i;
register_address_1_tmp(1) <= register_address_1_i;
RegDst_tmp(1) <= RegDst_i;
Jump_tmp(1) <= Jump_i;
Branch_tmp(1) <= Branch_i;
MemRead_tmp(1) <= MemRead_i;
MemtoReg_tmp(1) <= MemtoReg_i;
ALUOp_tmp(1) <= ALUOp_i;
MemWrite_tmp(1) <= MemWrite_i;
ALUSrc_tmp(1) <= ALUSrc_i;
RegWrite_tmp(1) <= RegWrite_i;
end if;
end process;
pc_o <= pc_tmp(0);
sign_extended_o <= sign_extended_tmp(0);
data1_o <= data1_tmp(0);
data2_o <= data2_tmp(0);
register_address_0_o <= register_address_0_tmp(0);
register_address_1_o <= register_address_1_tmp(0);
RegDst_o <= RegDst_tmp(0);
Jump_o <= Jump_tmp(0);
Branch_o <= Branch_tmp(0);
MemRead_o <= MemRead_tmp(0);
MemtoReg_o <= MemtoReg_tmp(0);
ALUOp_o <= ALUOp_tmp(0);
MemWrite_o <= MemWrite_tmp(0);
ALUSrc_o <= ALUSrc_tmp(0);
RegWrite_o <= RegWrite_tmp(0);
end IDEX_register_a; |
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_block
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
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JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
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2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
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