content
stringlengths 1
1.04M
⌀ |
|---|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
US2mB3ZU2xYMwSgf2KG3QONmAU5qxOR5gFmXyP3MzegSXblZ76jq0dw3DGi2XivflSREvQG+tGNr
93kJJN9RHg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
cVCcDe3dO8A3aQlcacvtDrMlOeMM3iFulWP1GnL0AstVpxpdCCRRxU3UHiCxbevv+1Dnaf6o7WxT
G4MiJBrZR0NZpyZrN6elCTa1aex/x1et3mJ/kXtaSnXZDYRGWgFlsFwFLktb6kdkyrjtbx1rPCM3
CfbtCvTObEIGzIf/FJI=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ybpmXaWiA2h4ouUhToF83n5FZ6mSwY7i2SbAGhh214jlEV4EAw60pDdsC9S1DXRUJs2H5ijqRHjq
O6r3TnjNUgOULu96coukm/eTQWKkKJe9Aqdi1COsXCRXpY/qPst8iFpcYgvP7x9BLqj2FuOVCOp1
vBc1X163t+3g+Wnu5wdB02cYtsPg85Aym4KDvpdGC2+lcbTElJIi+JurCHNEVSPxn/s/byKj9Aee
BWqSso/XFdRP+TM7huy2D0efcTINLjUE/2qeG1Z2VdFBpyOvUXxDlOhNEr+qAiw/pCiqNyrHCapM
TfSbH498t2P5uuhd9n2zpj2CUOFq13OvODvHsg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
o4nr3qLm7Rem+yVuZpGX2Dwzye61TgXXpiZsrYTQhxAIOttLQ5qy48oMqssSkd1Afuq4E1AgeeLD
pr9heGHoD5AjWxk13hv9r2YUI3BND7NaVLyrx7mIkF/pxjMjFTBF3rI5FZuYgxY00aftrEFjG/AI
XeOeb4w/KZQIUde+tJY=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
dHlANyrutuNgAtytsZMPMatpxiEBkM3u/gDZ64fIbSRqU16FBJ0WguNKCot1/TeXAq8CSJHQCt8x
3wxDlxfMsEEJdw5OF5Pn172rV07Ce6wZ30zB83ou1uUKjnNgy6pYqTworLe5Tj4SYl9VY0bcZ0g/
rN0niMih/6g+8XwbbPNRS7in3icwjpeqxdXwsRyEX3dbCrKVz4LXcfmP+ybNfKunFSp+imrzoFLt
cLJF8o/HdEoH/59p1whEdIyNin1+Ra+5d2hGnILLEgUP28LNS8Xr0dqjxGFNrkIDmtSmsmF2E1fl
JbLYu0fIIENjFn9nAJCzGQU523347ABwMPcyhA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 5328)
`protect data_block
o9U+AsHog7J5leFsl5pPk+ZHEKa37F9CufU9Tg7oO8cn3pKjvXjivYfHZPy6Ak9lIJ/g8MQ/uCTK
Ehrbnhlng/9tS4nwvy1jeqzV9p4Wx14vetUZIH+RYNl/tKHn10mg7gwhajzAeDIUrNMsFnoFx+fh
CP5tWTah6TibDlGo9SnATjNqGHF/s7qSik59t6DEZ+HWQm4Kug44ul8KvGmUIvaAZ9lSfvD+tmzr
QWN5KMd/d9Ft5N6FPW89MjNwor4yoMmAQ4MqruxG9KbOkDKB+cw61C5bDfOjZby0KAkPC4tT54AJ
+nCMTu8XLudFXsOLT9SWzI4eCiuy+a3Ns6XrGRNt2xDZ8Jjh4LidJoj/D3PIefXlfjIWFJTZPubw
vLhdnExMO/SNb6RASjhmuLlnvFYhlvJGmgBWEjTlGkB6k9DTSi7sQahQwPwz4UATwUdru05UU0gv
7NYfLyuSS0cG90Kbf+GK/Slz38AVcadSb9vuxwfCfjd1Mbrc1HlFxirzGJEy/lQd6FFDikkLumoh
PO3R4ykYX1vVB/w4BUgHRsQkzLDEkqAhbzq49+GAcJJPzNyfc1ovM8PiNHizOISDaZwP/b3eMBOb
XwjKXwf14ybsbOTqI38qtPFdZ63R84itp8+2xAhoKZh9HlxnKxRGCeceXs4uM/uL917PspBi0DHS
NPXwJMEFf+6+1jw/eMWmK2vxzH49j7vmiCrG7BtuUF7TItpH4Kw8LmPMqeLOxgaS+wHVtJvm+PjC
Nba6zA2496Yg8JIgU7UW9GKShPjVT8XQISNJdVDcgQSufc66tSU1mUqKmysmYw9dVq4JybfSNie4
DiK2zunlVUBBHbPp+OSAkMD+dultBRXWkDXULOG8g9MP4H8kRxD1tef75zoQQxQg5NENW6I6eDn5
Ly+mvgxx1zPNToL+kFkWsX2AuVkDVcfa4Y75JtgLoJkCUocg+ptfcXI4Lnkl0MDp9AgMGjqVjbj+
gZ66lKcI3uhDKzKTlmpqC698PGo/oY6QMMTFCcd5IPolqJ7BpwJZkZMh3E/O5EP/Vx6NvM0C5beq
HhWZdfsOJfEhmWAR60f6TroqR80i02NoPRRxd/9q98lk96zR7+3iBlDBtUUK9fL4NVS2qU1gy494
9I77UnPcN6drrKUShrsL9drWIn+J5nlfkjyMZRpEvqL77odjBuEIflcUYwVwVYW6rRVSEjGmjPGp
fdS2uHRG3JA8O7Twf3+ADsMNn7MWKxvA59MWdumzQrIElClapI5KrnYnpNBheoK4dLL48DfbIIkV
H1aFUWm1eEY786t2dPwV+YAer8o9PRUqd2GiMd8T5hRImFmr3igbUZL8442RsYvYHFHfvi9GLZPj
C7Tme5T3JJYhVZ8jjAlXE7zpXYnk7OLWR4/R9jVka8bLRq8aE98O82ykyg2qZfge3GWRYWpiIydc
4608fPTitKd8MrIkH4xN6t7MvZaZFBfEqyKLikrRtkkmbXb829cdwGpc9SPjQydkysKkRNtPN1Mo
LxmpCNExbGBBX1SRyUq2tLgEQ+BkcO8uDbomByZQ3gqUrOzNVi+aw2sYRljKs8KXrD/+NLDCX3hc
xzE74GDfPnMN1VldPssWJMKdrJlx82sH/5Quaa1qjnWLi0lTN1fxfU1NrUgUQODom44mjuKSrqin
jQPE81V63s70Wf+oHNRGSbXHCipNTZ4S5DSVMP08cu5kWIADsDF90HdXQibDu+6nqdBJfKbkT9Xw
6pZDNKqHdYGj1sH8hrg/7kdXBUcpVtqX14cFaVf1UxrpfcmtFYxbDGcE83ZMbWZ6MJvtTNKhLHyG
zBMj983s8QucGMNEuCtSxus1MNt0VS+4uIqZXi0awt98ztjLXFnUV6cl6Aa06zHYWsMTcaHc81mJ
qAkBee5KPCjF86O+/izG3V48nunO/LYTfbcvQPAT1/e0TapplZHJQB/8wNfUDb325HneNhXC0T4Z
sY7b4960dY69aQZiMlRQvq6s0HgiD/f/rB6T6jvg+XcWrgVz7zOG23yv38EKMR4i57POx/LTZRKx
I2EYDxzwkFVjUqST8u6ISNAU7/iSd0cEnXZsvHwgmwp7DV2PszKX0SEege8TkpdmDKamOnVEl0P8
MqBf9LdGRCOz6selCYeXT4xN5EmnzxcUdVyd3IPpkWS0T4Dd4PTUweTC5fLNBEJ6rULazod44QOB
klojcsVoJ+mERB10PivE7j4Uw32Nq/AUt2SXhHFDm1DlBRLOw9ivdGkGfGkwApvsG0nSCYYYfCta
kUYf+DN9YwPR3d3tHYuotTGc+a2jZlQjWNFbGq5SDo1CZD/4xgsFyKV5NwRllYvktkRY7Zg+qKtJ
l5VEbad7xYX+11AfZN5wfGs1Hq45Mjl9gcCcB8Z8ewVLfznMi0uiRjxKl5BNuqLVXuRn0pelsiNk
E9BVauYF+WiXnyuhKKGqYBMM43cih1nkoPCW5TQNmzERWLMkLEZk27a8oLBpm629HPvAare+Z8N+
z+dT84Yte24f8Hm4+XGHVXV09pC2uEXMK4eIeBcOHVjFS8k2eZgALNhL+qGd6qoek9PqQ05S8LdP
aYLsrVi3zXYURRZelvoWvAZ+RkPhD1idFyMUwapTSDQmsOIPetalwa7n/NDLFT6ejQMukFtrnIvF
EapTMDL2i4VsaOXg4khw0dB4GsGcKVnPXuVzMHF3K4DqK4PpAh/XHve7fd6xkoQdEy2jd7kR98w9
RRIIA9n18bOjNHUqLefJQD3MM2K41RPFCBMWEqxi13S2Fhn7dEuAoCFyvi6g2aPn7rmh0GR50dKr
FixmX7A0jBq21nu4ssOyXspJrX/gRaJIX0P41ONcaTjEM0kxulX7P9nvesimbGpp2CXOnT2Gmk1w
TDilSYwWO07Kv2kbchii4asVi/SZCyq9ZZyH+Fjk0JouVfggNVmc1UgZ3iB3lMlVUvLOTeXIxctC
uW2ySv82Wzl+RZ3sOo2muiPD/k35N3/dcU6kCqIYMsMxqKdeaXDqmxetuK2+N+zdy9UBDqtRrr12
C5g1cb86tbKfCLVay7i3QlpLmmSzdMLAYF9s2gYOZY7utcHjekXzMRr+nHhLJNIJv93es03Ej5BA
BNDHNstPUcnnXlBJ72hNc2txIdc3zvHFw2d3/k5E24K+B8wqE3sL758pZZvQkEfBh2hTJxiJsa90
C/Xm8cMxRDeAGYtQX+0fkB7vYK0qaNLChNUJmqVo2u0PzLSBRWAW3XwQqOookZkP6Ble8/frnWNj
jf7h5dcVWSySpJlAwi5vzkH5skwLPSb+EUeEYE1e+h6iCPkhuz4S/eKzou8a2Eir1MoNosu4/J/X
wp90P392NCJ2GFktdv9YAIOfYYZEDA9CeD+25K5J7QeWwdGCB6lnkLsOpn6t9GSuijo4Zi04K9cu
sZlPwIeRb79Fn1GDqanMYAAdomeExZEINcl823ZEO+Zc5tRBnreTRmBFVdxtHuTGMuRuW5vvRpKw
gJsCU56FJPGXa+2+zc3EjGAPbPUlF+sPzdj5jAORYY7Nur9M9yjcm9omt4WUNhkwcvtOx3InVG2r
TcKlmDIPq7RmYkPt7tZfqvCXprkhtg6ouBrddKz03gCdXPDaLP9lzh6dMjtcP51m2A1W3cNccuB4
ITMb/6M0aB95Q6Yxfu9GC43qsMvLJh3U+LnamfqbdM+gTwcf0gGUc+HXjtz4xsX2QBSEbeUSyEiI
Jwsi3uybqbqKOrWsTOQJnFPJOlkDCPQD+f1hbe5AWA5NoVHJH+j/9XGsLkSBN74B7Di3dhOg1l64
fRufp3La90RjZjbBqhFcxace7tXtVn0SJmj7qaroxLZaZ4uiHdag3oTbFB755L+/4kM1O5H2gzLG
oqEbricEgcHa/WGjuwv+7xpg4l3Q5D5BVekbzlg6UfwZ48jwD7W3lCBHkFhOVVm195iBET48mnHZ
CD2IntCiy2ZFikVkxsyUBB0Zbtma0mQpljfFapv5JOwighssd8LKGAdd8OiQUVWtUTgGnclLQngm
C9eyIYy1ffXIvdlvEifOfgRE5U35E6Tk2dxONgPsYKLf5W9rJEre4LkDIYHZEY5O72aqpivrrwYz
wEw5A7QlDFx7wR1FLPFgg4giZqi5K8Sf8XOjjJ5/SJknbQTjSTcyBsS9MFGbuNxnBhD4l28bDSjZ
9vN77KOifcfPSEuCPQ/SS7ME/SniuI1foQym+tAlqBc1OJ2werNrzKrQWW61CO1EJ3n95cYXR4ee
LEKRQ3F0CSqTrxqBw2sTL/ANBTK5+8z2cwF+EFn7/FCBiFbvHg6psN0sgpKHdUm7xXyhgaMheDSg
vN5xYIjBg/cVyoP/9wn/9k9J3NjsKOHYsf4lkQh7QNBIzob7Ywt2jkByPsmgoWxYmQ4tyRc/nzLK
zp6MiTyJ/bh82uQnpCdA+so9o+wzlfjd3j6zR4T7ry2gwf6O+MTD8KDJ64t9Vt2WvqnNSDZoJ05e
EdBE0BYMycjAt5yEhEC85xSG9efwRdIEdkmbVd8DoDJfbI2ZKnz1NC4/EP7+6+6J2A/YQivTe3ZM
eIR6yUCLTfxE+ZCyK0riROBd9eaXToH9hQH6IztXNiO9zabAf6jaWVleDqo/oYTn19riMsTW7yqX
RsLOK0bx+e6yMAhBG1BfQZyhLf9v5XefZHJdmtJmvE4sMH9Oim7lzdIQ3TzsQWcV8NnEtzTvXN3G
B5VNPO2zIT6biTk9vJnBakAzKbKYgoFstAU47UbvO2/TGrQxJYG3YtP7NKqmw/LBTXpec6y6/D61
akdpGaOdDtf9R1zQxsMSQhGCU1moC4+tsLS9v25qSs2bie47VnbtSPmwvohnmnLt3XyjfKL6Dqya
qLiKFIKZ0kfYYZWdvckzvE2DM0ap6fVPRhQlWTpBF4xx1B+yrnaJoFsalz20CLoWi13gTpG7DLNL
bWr2j4wQVOn/fUi04IBc0CqK96uVu/+8Gc368mkDGmKR/wQ1AwUe7pwqSD6hVuoE4X7SuMKT6q8f
KPJOJqAkfEwpUTAPhaDN8rR95o8cFzcPodTwfszYkqLch5qYwh6jrti2epvaqaAODuGHujDgR9bE
qfoR4Ss6D0hB7jR43b1F28flI3C2JCq0rlHy7GuMNFCMWLlDT8fIVhf8ep3G1pXu8hSJz1PGiQvN
Uz7bs+b7whqZwFWWtPaNbleAUQ44ooCElY86YkOY/E40U3t6A9fZP7MOTVEU5S7d2gk8lKbI63WJ
bCXR20D5lZ5UWxqp5kaaFgMrdEO89meQJC1FwuoLnC7t6x7oAwsNEaGfhZRMxwck6ZsvaDPhS+2C
QtxXobuAWWws/NYapSS3u713mZgGz77zek4IkCQDTomrvshUEcdOPaz7UnKxY6aElMusvTf3Q1pR
g1TyvSUPg/oH0Uqb+gMJ5GARnZEOC2iLfA/efp3AljTlLAd8po1/zu0DiIXkPtCe1xrEa3+77hDy
QQ4ndfarzasi/GpLnYZkzV+/+CL5kwHQFVRWfvX0HFtAb6RFyESe1JVj813OW22haaduNBJJ85UE
N5+y+yEAVitjLbPHi0gnhvIh0GPXgBCuLtyQkx8SJf5ELeHY/h9U4mp8N2hMdKDF3aX3PJTuGkSU
/2XZskgWo8ppp4QSzZ8rQtcU1uD6Fc4tFkSIwJMscm5hbkxP4Wr+LNrpQrUPdCVPbMpouJQVsFjX
YGbhD9pGfhYGfffrnWD+dAM48Fx4DG5VNaCzjra/+8qnT8DsvJO7QP9WCMzJKWjcrsDwvzmRnjMd
IKxAC5UUuE2jMBxBWVYsmgFAYHvQEN+TqsLP9eOJ6lHaLFnw3OWwfDt7nEoWlcnzOeFT04oh6JBs
M/b/DX9KXqwtVxlzsmdkVQl6nf1AmIzhEPo67XcTWwfWi01icMoIhzaMol11mkrRruf4CmfsxVZm
qIWDlgtz2KjpcnEpAHzlJ87Qr0wWPHBhVRC92106EFMESEBBy5T7XqM696h7QOLON3EH3fo4XxFk
u0dvXAlddS+uq7yyLZsKg3GxbcaRB9Aau6a8iiwsk4Zg5HW0cCEX60HD/1hz+Aeu/2xIQeqaY8EZ
PhfZUUi4aOdwiX7rDuD8vj18G62Nm7aqOP4ktlMeoU/Z0HoMeer7vUfHmqn0vqmCcCoccHr4rQ3L
EF1vJ2+luEtNe1bX/VyjEY1WzUSfAwYOWBjKEoa1tfk4pQ1gW3Tv1IWqw/tpQCtSEsLyVZeAnVLo
kyrpVs/Km8UcHXhEr/GwIdX518LDrlnXPirXnq/FJHDJgry2QcXiLtsqxZrI+k43vDOWz4/0bKs8
esy9EIRg68igB3YeR0dEct6cxLHewEfcOpqyPA+Qn5uE38QuktFc3zky9Xz5OLbncUcnPvH75v6L
UGQMWIoVZT8djl3ESdVcouV3NwMCX1ksRNQbrkQ3COBQ5dz0zMFlOQUQ6IbJ1d+dy8Q9vZ1MYZjr
o7GUKUVnr90eza0/k1y/6wwurx1PaBB5lABeyU3FKdFKRiwSVdcQsPRRd778b433yBGCIbI86d4a
UMlaSg0QBGNn3hKZic06cjnsJhzgQ09vXgaaYXL5mFzCagl4dN+K3+oAcO4bo2D843YGd+i/Twst
P51xBmBXyuWj3mg1OPY0T6CI2POQU4gM5K7asvvDwftX2n2LaVPB0/w39Nqv/XqvEHPS2ZqGGxEE
D5CN+Bkrx2LlXQzMtqXx7EV7KY5v+AOCc/QTVuL2TAyv5/IxMMRc9TyDTeJuWzhXoQtmJ9Ob7WbH
jbR6o0Ga4HbEOqkCxXqc3vbsD1K5Fv9WUjm8Po/6vNJvV6xxsUxFNH3lsFavvGOM7erAcATjNCGC
gz2pfvuQFtyJBDNo2PSM2ZF1SO/aM83WkVSfUeblU9NSfXfQz3RHJ61i2nXbk/KDvGzTA3D8K0Rm
cbg/JRfRP+UT/w+DSCw6QY4HAuHTg+pBrRzsTLM8AJCIx2UTc1yixBkcq7j3sJjjPUmyoSPt3hbC
VAEYc0GafYanOw1fzEJ/8bGNb0491MoMch1MOhNwQe0yiSRrhRuEa9VqS4AJjUbDLg67oG6Oby4C
2l2+hurOFVwVqQeNLaszbftUXYupQVyqrF4k
`protect end_protected
|
architecture RTl of FIFO is
component fifo is
end component fifo;
-- Failures below
component fifo is
end component fifo;
component fifo is
end component fifo;
begin
end architecture RTL;
|
Library Ieee;
Use Ieee.Std_Logic_1164.all;
Use Work.MIPS8B_Base.all;
Package MIPS8B_Components is
-- Inteface para o PC.
Component PC_System is
Generic(N: Natural := 8);
Port(clock: in Std_Logic;
Reset_n: in Std_Logic;
en_Out_PC: in Std_Logic;
load_PC: in Std_Logic;
inc_PC: in Std_Logic;
in_PC: in Std_Logic_Vector(N-3 downto 0);
out_PC: out Std_Logic_Vector(N-3 downto 0);
address_PC: out Std_Logic_Vector(N-3 downto 0));
End Component;
-- Interface para o sistema de I/O.
Component MIPS8B_IO_System is
Generic(N: Natural := 8);
Port(clock: in Std_Logic;
Reset_n: in Std_Logic;
-- Controle do endereço fornecido pelo sistema
en_RMem: in Std_Logic;
en_RMem_Inc: in Std_Logic;
crt_Mux_IO: in Std_Logic;
crt_MEM: in MemoryOP;
-- Controle dos Dados de I/O.
en_RData_in: in Std_Logic;
en_RData_out: in Std_Logic;
-- Valores de endereço para transações de I/O.
out_PC: in Std_Logic_Vector(N-3 downto 0);
out_DPath: in Std_Logic_Vector(N-1 downto 0);
in_Data: in Std_Logic_Vector(N-1 downto 0);
-- Registradores para dados de I/O.
RMem: out Std_Logic_Vector(N-1 downto 0);
RData_in: out Std_Logic_Vector(N-1 downto 0);
RData_out: out Std_Logic_Vector(N-1 downto 0);
-- Interface de controle.
Cmd: out Std_Logic_Vector(1 downto 0);
CmdAccept: in Std_Logic;
IO_OK: out Std_Logic);
End Component;
-- Interface para o controlador principal.
Component MIPS8B_DP_Control is
Generic(N: Natural := 8;
SH_SIZE: Natural := 3;
RF_ADDR_SIZE: Natural := 3);
Port(clock: in Std_Logic;
Reset_n: in Std_Logic;
IO_OK: in Std_Logic;
eq_Flag: in Std_Logic;
Opcode: in Std_Logic_Vector(4 downto 0);
in_Bus: in Std_Logic_Vector(N-1 downto 0);
-- Controle para o Registrer File.
crt_RFile: out Std_Logic;
en_Raddress_RF: out Std_Logic;
address_RF: out Std_Logic_Vector(RF_ADDR_SIZE-1 downto 0);
-- Controle para os registradores Intermediarios.
en_R1A_ULA: out Std_Logic;
en_R1B_ULA: out Std_Logic;
en_R2_ULA: out Std_Logic;
en_Reg_SH: out Std_Logic;
-- Controle para os multiplexadores.
crt_Mux_ULA: out Std_Logic_Vector(1 downto 0);
crt_Mux_Acc: out Std_Logic;
crt_Mux_RF: out Std_Logic;
-- Controle das unidades funcionais.
crt_ULA: out Std_Logic_Vector(2 downto 0);
crt_SH: out Std_Logic_Vector(1 downto 0);
crt_Acc: out Std_Logic_Vector(1 downto 0);
-- Controle do PC.
en_Out_PC: out Std_Logic;
load_PC: out Std_Logic;
inc_PC: out Std_Logic;
-- Controle para o sistema de IO.
en_ROpcode: out Std_Logic;
en_RMem: out Std_Logic;
en_RMem_Inc: out Std_Logic;
en_RData_in: out Std_Logic;
en_RData_out: out Std_Logic;
crt_Mux_IO: out Std_Logic;
crt_MEM: out MemoryOP;
-- Valor do comprimento do shift.
S_SH: out Std_Logic_Vector(SH_SIZE-1 downto 0);
-- Valor do campo imediato
out_IMM: out Std_Logic_Vector(N-1 downto 0));
End Component;
-- Interface para o Datapath.
Component Mips8B_DataPath is
Generic( N: Natural := 8;
RF_SIZE: Natural := 8;
SH_SIZE: Natural := 3;
RF_ADDR_SIZE: Natural := 3);
Port(clock: in Std_Logic;
-- Controle dos Registradores do Shift Register.
en_Reg_SH: in Std_Logic;
-- Controle para Shifter.
crt_SH: in Std_Logic_Vector(1 downto 0);
S_SH: in Std_Logic_Vector(SH_SIZE-1 downto 0);
-- Controle dos Registradores da ULA.
en_R1A_ULA: in Std_Logic;
en_R1B_ULA: in Std_Logic;
en_R2_ULA: in Std_Logic;
-- Controle para ULA.
crt_ULA: in Std_Logic_Vector(2 downto 0);
crt_Mux_ULA: in Std_Logic_Vector(1 downto 0);
-- Controle para Register File.
crt_RFile: in Std_Logic;
crt_Mux_RF: in Std_Logic;
address_RF: in Std_Logic_Vector(RF_ADDR_SIZE-1 downto 0);
en_Raddress_RF: in Std_logic;
-- Controle para o Acumulador.
crt_Acc: in Std_Logic_Vector(1 downto 0);
crt_Mux_Acc: in Std_Logic;
-- Entradas do Datapath.
in_PC: in Std_Logic_Vector(N-3 downto 0);
in_IMM: in Std_Logic_Vector(N-1 downto 0);
-- Flag de Igualdade de Operandos.
eq_Flag: out Std_Logic;
-- Saida do resultado do Acumulador.
out_Acc: out Std_Logic_Vector(N-1 downto 0));
End Component;
End Package MIPS8B_Components;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of cyclone3_pll is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY"
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
-- Must use operation_mode other than "ZERO_DELAY_BUFFER" due to
-- tool issues with ZERO_DELAY_BUFFER and non-existent output clock
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 5,
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_cycloneiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_cycloneiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component cyclone3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : cyclone3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_cycloneiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
sync_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
async_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux2 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux2;
architecture mux2 of dspba_mux2 is
begin
mux2genclk: if depth = 1 generate
mux2proc: PROCESS (xin0, xin1, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "0" => xout <= xin0;
WHEN "1" => xout <= xin1;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux2proc;
end generate mux2genclk;
mux2gencomb: if depth = 0 generate
mux2proc2: process(xin0, xin1, xinsel)
begin
CASE (xinsel) IS
WHEN "0" => xout <= xin0;
WHEN "1" => xout <= xin1;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux2proc2;
end generate mux2gencomb;
end mux2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux3 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux3;
architecture mux3 of dspba_mux3 is
begin
mux3genclk: if depth = 1 generate
mux3proc: PROCESS (xin0, xin1, xin2, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux3proc;
end generate mux3genclk;
mux3gencomb: if depth = 0 generate
mux3proc2: process(xin0, xin1, xin2, xinsel)
begin
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux3proc2;
end generate mux3gencomb;
end mux3;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux4 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xin3 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux4;
architecture mux4 of dspba_mux4 is
begin
mux4genclk: if depth = 1 generate
mux4proc: PROCESS (xin0, xin1, xin2, xin3, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN "11" => xout <= xin3;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux4proc;
end generate mux4genclk;
mux4gencomb: if depth = 0 generate
mux4proc2: process(xin0, xin1, xin2, xin3, xinsel)
begin
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN "11" => xout <= xin3;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux4proc2;
end generate mux4gencomb;
end mux4;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intadd_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intadd_u;
architecture intadd_u of dspba_intadd_u is
begin
intadd_u_genclk: if depth = 1 generate
intadd_u_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
end if;
end if;
END PROCESS intadd_u_proc;
end generate intadd_u_genclk;
intadd_u_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
end generate intadd_u_gencomb;
end intadd_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intadd_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intadd_s;
architecture intadd_s of dspba_intadd_s is
begin
intadd_s_genclk: if depth = 1 generate
intadd_s_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
end if;
end if;
END PROCESS intadd_s_proc;
end generate intadd_s_genclk;
intadd_s_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
end generate intadd_s_gencomb;
end intadd_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intsub_u;
architecture intsub_u of dspba_intsub_u is
begin
intsub_u_genclk: if depth = 1 generate
intsub_u_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
end if;
end if;
END PROCESS intsub_u_proc;
end generate intsub_u_genclk;
intsub_u_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
end generate intsub_u_gencomb;
end intsub_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intsub_s;
architecture intsub_s of dspba_intsub_s is
begin
intsub_s_genclk: if depth = 1 generate
intsub_s_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
end if;
end if;
END PROCESS intsub_s_proc;
end generate intsub_s_genclk;
intsub_s_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
end generate intsub_s_gencomb;
end intsub_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intaddsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intaddsub_u;
architecture intaddsub_u of dspba_intaddsub_u is
begin
intaddsub_u_genclk: if depth = 1 generate
intaddsub_u_proc: PROCESS (xin0, xin1, xins, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
END IF;
end if;
end if;
END PROCESS intaddsub_u_proc;
end generate intaddsub_u_genclk;
intaddsub_u_gencomb: if depth = 0 generate
intaddsub_u_proc_comb: PROCESS (xin0, xin1, xins)
BEGIN
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
END IF;
END PROCESS;
end generate intaddsub_u_gencomb;
end intaddsub_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intaddsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intaddsub_s;
architecture intaddsub_s of dspba_intaddsub_s is
begin
intaddsub_s_genclk: if depth = 1 generate
intaddsub_s_proc: PROCESS (xin0, xin1, xins, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
END IF;
end if;
end if;
END PROCESS intaddsub_s_proc;
end generate intaddsub_s_genclk;
intaddsub_s_gencomb: if depth = 0 generate
intaddsub_s_proc_comb: PROCESS (xin0, xin1, xins)
BEGIN
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
END IF;
END PROCESS;
end generate intaddsub_s_gencomb;
end intaddsub_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- (C) 2012 Altera Corporation. All rights reserved.
-- Your use of Altera Corporation's design tools, logic functions and other
-- software and tools, and its AMPP partner logic functions, and any output
-- files any of the foregoing (including device programming or simulation
-- files), and any associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License Subscription
-- Agreement, Altera MegaCore Function License Agreement, or other applicable
-- license agreement, including, without limitation, that your use is for the
-- sole purpose of programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the applicable
-- agreement for further details.
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_delay is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_delay;
architecture delay of dspba_delay is
type delay_array is array (depth downto 0) of std_logic_vector(width-1 downto 0);
signal delay_signals : delay_array;
begin
delay_signals(depth) <= xin;
delay_block: if 0 < depth generate
begin
delay_loop: for i in depth-1 downto 0 generate
begin
sync_reset: if reset_kind = "ASYNC" generate
process(clk, aclr)
begin
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
async_reset: if reset_kind = "SYNC" generate
process(clk)
begin
if clk'event and clk='1' then
if aclr=reset_high then
delay_signals(i) <= (others => '0');
elsif ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
no_reset: if reset_kind = "NONE" generate
process(clk)
begin
if clk'event and clk='1' then
if ena='1' then
delay_signals(i) <= delay_signals(i + 1);
end if;
end if;
end process;
end generate;
end generate;
end generate;
xout <= delay_signals(0);
end delay;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux2 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux2;
architecture mux2 of dspba_mux2 is
begin
mux2genclk: if depth = 1 generate
mux2proc: PROCESS (xin0, xin1, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "0" => xout <= xin0;
WHEN "1" => xout <= xin1;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux2proc;
end generate mux2genclk;
mux2gencomb: if depth = 0 generate
mux2proc2: process(xin0, xin1, xinsel)
begin
CASE (xinsel) IS
WHEN "0" => xout <= xin0;
WHEN "1" => xout <= xin1;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux2proc2;
end generate mux2gencomb;
end mux2;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux3 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux3;
architecture mux3 of dspba_mux3 is
begin
mux3genclk: if depth = 1 generate
mux3proc: PROCESS (xin0, xin1, xin2, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux3proc;
end generate mux3genclk;
mux3gencomb: if depth = 0 generate
mux3proc2: process(xin0, xin1, xin2, xinsel)
begin
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux3proc2;
end generate mux3gencomb;
end mux3;
library IEEE;
use IEEE.std_logic_1164.all;
use work.dspba_library_package.all;
entity dspba_mux4 is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xin2 : in std_logic_vector(width-1 downto 0);
xin3 : in std_logic_vector(width-1 downto 0);
xinsel : in std_logic_vector(1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_mux4;
architecture mux4 of dspba_mux4 is
begin
mux4genclk: if depth = 1 generate
mux4proc: PROCESS (xin0, xin1, xin2, xin3, xinsel, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN "11" => xout <= xin3;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end if;
end if;
END PROCESS mux4proc;
end generate mux4genclk;
mux4gencomb: if depth = 0 generate
mux4proc2: process(xin0, xin1, xin2, xin3, xinsel)
begin
CASE (xinsel) IS
WHEN "00" => xout <= xin0;
WHEN "01" => xout <= xin1;
WHEN "10" => xout <= xin2;
WHEN "11" => xout <= xin3;
WHEN OTHERS => xout <= (others => '0');
END CASE;
end process mux4proc2;
end generate mux4gencomb;
end mux4;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intadd_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intadd_u;
architecture intadd_u of dspba_intadd_u is
begin
intadd_u_genclk: if depth = 1 generate
intadd_u_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
end if;
end if;
END PROCESS intadd_u_proc;
end generate intadd_u_genclk;
intadd_u_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
end generate intadd_u_gencomb;
end intadd_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intadd_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intadd_s;
architecture intadd_s of dspba_intadd_s is
begin
intadd_s_genclk: if depth = 1 generate
intadd_s_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
end if;
end if;
END PROCESS intadd_s_proc;
end generate intadd_s_genclk;
intadd_s_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
end generate intadd_s_gencomb;
end intadd_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intsub_u;
architecture intsub_u of dspba_intsub_u is
begin
intsub_u_genclk: if depth = 1 generate
intsub_u_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
end if;
end if;
END PROCESS intsub_u_proc;
end generate intsub_u_genclk;
intsub_u_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
end generate intsub_u_gencomb;
end intsub_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intsub_s;
architecture intsub_s of dspba_intsub_s is
begin
intsub_s_genclk: if depth = 1 generate
intsub_s_proc: PROCESS (xin0, xin1, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
end if;
end if;
END PROCESS intsub_s_proc;
end generate intsub_s_genclk;
intsub_s_gencomb: if depth = 0 generate
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
end generate intsub_s_gencomb;
end intsub_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intaddsub_u is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intaddsub_u;
architecture intaddsub_u of dspba_intaddsub_u is
begin
intaddsub_u_genclk: if depth = 1 generate
intaddsub_u_proc: PROCESS (xin0, xin1, xins, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
END IF;
end if;
end if;
END PROCESS intaddsub_u_proc;
end generate intaddsub_u_genclk;
intaddsub_u_gencomb: if depth = 0 generate
intaddsub_u_proc_comb: PROCESS (xin0, xin1, xins)
BEGIN
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) + UNSIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(UNSIGNED(xin0) - UNSIGNED(xin1));
END IF;
END PROCESS;
end generate intaddsub_u_gencomb;
end intaddsub_u;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_intaddsub_s is
generic (
width : natural := 8;
depth : natural := 1;
reset_high : std_logic := '1'
);
port (
clk : in std_logic;
aclr : in std_logic;
ena : in std_logic := '1';
xin0 : in std_logic_vector(width-1 downto 0);
xin1 : in std_logic_vector(width-1 downto 0);
xins : in std_logic_vector(0 downto 0);
xout : out std_logic_vector(width-1 downto 0)
);
end dspba_intaddsub_s;
architecture intaddsub_s of dspba_intaddsub_s is
begin
intaddsub_s_genclk: if depth = 1 generate
intaddsub_s_proc: PROCESS (xin0, xin1, xins, clk, aclr, ena)
BEGIN
if (aclr=reset_high) then
xout <= (others => '0');
elsif (clk'event and clk='1') then
if (ena = '1') then
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
END IF;
end if;
end if;
END PROCESS intaddsub_s_proc;
end generate intaddsub_s_genclk;
intaddsub_s_gencomb: if depth = 0 generate
intaddsub_s_proc_comb: PROCESS (xin0, xin1, xins)
BEGIN
IF (xins = "1") THEN
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) + SIGNED(xin1));
ELSE
xout <= STD_LOGIC_VECTOR(SIGNED(xin0) - SIGNED(xin1));
END IF;
END PROCESS;
end generate intaddsub_s_gencomb;
end intaddsub_s;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
use work.dspba_library_package.all;
entity dspba_sync_reg is
generic (
width1 : natural := 8;
init_value : std_logic_vector;
width2 : natural := 8;
depth : natural := 2;
pulse_multiplier : natural := 1;
counter_width : natural := 8;
reset1_high : std_logic := '1';
reset2_high : std_logic := '1';
reset_kind : string := "ASYNC"
);
port (
clk1 : in std_logic;
aclr1 : in std_logic;
ena : in std_logic_vector(0 downto 0);
xin : in std_logic_vector(width1-1 downto 0);
xout : out std_logic_vector(width1-1 downto 0);
clk2 : in std_logic;
aclr2 : in std_logic;
sxout : out std_logic_vector(width2-1 downto 0)
);
end entity;
architecture sync_reg of dspba_sync_reg is
type bit_array is array (depth-1 downto 0) of std_logic;
signal iclk_enable : std_logic;
signal iclk_data : std_logic_vector(width1-1 downto 0);
signal oclk_data : std_logic_vector(width2-1 downto 0);
-- For Synthesis this means: preserve this registers and do not merge any other flip-flops with synchronizer flip-flops
-- For TimeQuest this means: identify these flip-flops as synchronizer to enable aitomatic MTBF analysis
signal sync_regs : bit_array;
attribute altera_attribute : string;
attribute altera_attribute of sync_regs : signal is "-name SYNCHRONIZER_IDENTIFICATION FORCED_IF_ASYNCHRONOUS; -name DONT_MERGE_REGISTER ON; -name PRESERVE_REGISTER ON";
signal oclk_enable : std_logic;
constant init_value_internal : std_logic_vector(width1-1 downto 0) := init_value;
signal counter : UNSIGNED(counter_width-1 downto 0);
signal ena_internal : std_logic;
begin
oclk_enable <= sync_regs(depth-1);
no_multiplication: if pulse_multiplier=1 generate
ena_internal <= ena(0);
end generate;
async_reset: if reset_kind="ASYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if aclr1=reset1_high then
counter <= (others => '0');
elsif clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1, aclr1)
begin
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
elsif clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2, aclr2)
begin
if aclr2=reset2_high then
sync_regs(i) <= '0';
elsif clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2, aclr2)
begin
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
sync_reset: if reset_kind="SYNC" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
counter <= (others => '0');
else
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
if aclr1=reset1_high then
iclk_enable <= '0';
iclk_data <= init_value_internal;
else
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
sync_regs(i) <= '0';
else
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if aclr2=reset2_high then
oclk_data <= init_value_internal(width2-1 downto 0);
elsif oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
none_reset: if reset_kind="NONE" generate
multiply_ena: if pulse_multiplier>1 generate
ena_internal <= '1' when counter>0 else ena(0);
process (clk1, aclr1)
begin
if clk1'event and clk1='1' then
if counter>0 then
if counter=pulse_multiplier-1 then
counter <= (others => '0');
else
counter <= counter + TO_UNSIGNED(1, counter_width);
end if;
else
if ena(0)='1' then
counter <= TO_UNSIGNED(1, counter_width);
end if;
end if;
end if;
end process;
end generate;
process (clk1)
begin
if clk1'event and clk1='1' then
iclk_enable <= ena_internal;
if ena(0)='1' then
iclk_data <= xin;
end if;
end if;
end process;
sync_reg_loop: for i in 0 to depth-1 generate
process (clk2)
begin
if clk2'event and clk2='1' then
if i>0 then
sync_regs(i) <= sync_regs(i-1);
else
sync_regs(i) <= iclk_enable;
end if;
end if;
end process;
end generate;
process (clk2)
begin
if clk2'event and clk2='1' then
if oclk_enable='1' then
oclk_data <= iclk_data(width2-1 downto 0);
end if;
end if;
end process;
end generate;
xout <= iclk_data;
sxout <= oclk_data;
end sync_reg;
|
-- VHDL Entity r65c02_tc.reg_sp.symbol
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:04:08 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
entity reg_sp is
port(
adr_low_i : in std_logic_vector (7 downto 0);
clk_clk_i : in std_logic;
ld_low_i : in std_logic;
ld_sp_i : in std_logic;
rst_rst_n_i : in std_logic;
sel_sp_as_i : in std_logic;
sel_sp_in_i : in std_logic;
adr_sp_o : out std_logic_vector (15 downto 0)
);
-- Declarations
end reg_sp ;
-- (C) 2008 - 2018 Jens Gutschmidt
-- (email: [email protected])
--
-- Versions:
-- Revision 1.7 2013/07/21 11:11:00 jens
-- - Changing the title block and internal revision history
--
-- Revision 1.6 2009/01/04 10:20:47 eda
-- Changes for cosmetic issues only
--
-- Revision 1.5 2009/01/04 09:23:10 eda
-- - Delete unused nets and blocks (same as R6502_TC)
-- - Rename blocks
--
-- Revision 1.4 2009/01/03 16:53:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.3 2009/01/03 16:42:02 eda
-- - Unused nets and blocks deleted
-- - Renamed blocks
--
-- Revision 1.2 2008/12/31 19:31:24 eda
-- Production Release
--
--
--
-- VHDL Architecture r65c02_tc.reg_sp.struct
--
-- Created:
-- by - eda.UNKNOWN (ENTW-7HPZ200)
-- at - 12:04:08 06.09.2018
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2016.2 (Build 5)
--
-- COPYRIGHT (C) 2008 - 2018 by Jens Gutschmidt
--
-- This program is free software: you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, either version 3 of the License, or any later version.
--
-- This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along with this program. If not, see <http://www.gnu.org/licenses/>.
--
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
architecture struct of reg_sp is
-- Architecture declarations
-- Internal signal declarations
signal adr_sp_low_o_i : std_logic_vector(7 downto 0);
signal load_o_i : std_logic;
signal result_low1_o_i : std_logic_vector(7 downto 0);
signal result_low_o_i : std_logic_vector(7 downto 0);
signal sp_as_n_o_i : std_logic;
signal val_one : std_logic_vector(7 downto 0);
-- Implicit buffer signal declarations
signal adr_sp_o_internal : std_logic_vector (15 downto 0);
-- ModuleWare signal declarations(v1.12) for instance 'U_0' of 'adff'
signal mw_U_0reg_cval : std_logic_vector(7 downto 0);
begin
-- ModuleWare code(v1.12) for instance 'U_11' of 'addsub'
u_11combo_proc: process (adr_sp_low_o_i, val_one, sp_as_n_o_i)
variable temp_din0 : std_logic_vector(8 downto 0);
variable temp_din1 : std_logic_vector(8 downto 0);
variable temp_sum : unsigned(8 downto 0);
variable temp_carry : std_logic;
begin
temp_din0 := '0' & adr_sp_low_o_i;
temp_din1 := '0' & val_one;
temp_carry := '0';
if (sp_as_n_o_i = '1') then
temp_sum := unsigned(temp_din0) + unsigned(temp_din1) + temp_carry;
else
temp_sum := unsigned(temp_din0) - unsigned(temp_din1) - temp_carry;
end if;
result_low_o_i <= conv_std_logic_vector(temp_sum(7 downto 0),8);
end process u_11combo_proc;
-- ModuleWare code(v1.12) for instance 'U_0' of 'adff'
adr_sp_o_internal(7 DOWNTO 0) <= mw_U_0reg_cval;
u_0seq_proc: process (clk_clk_i, rst_rst_n_i)
begin
if (rst_rst_n_i = '0') then
mw_U_0reg_cval <= "00000000";
elsif (clk_clk_i'event and clk_clk_i='1') then
if (load_o_i = '1') then
mw_U_0reg_cval <= result_low1_o_i;
end if;
end if;
end process u_0seq_proc;
-- ModuleWare code(v1.12) for instance 'U_6' of 'and'
load_o_i <= ld_sp_i and ld_low_i;
-- ModuleWare code(v1.12) for instance 'U_3' of 'buff'
adr_sp_o_internal(15 DOWNTO 8) <= val_one;
-- ModuleWare code(v1.12) for instance 'U_4' of 'constval'
val_one <= "00000001";
-- ModuleWare code(v1.12) for instance 'U_2' of 'inv'
sp_as_n_o_i <= not(sel_sp_as_i);
-- ModuleWare code(v1.12) for instance 'U_8' of 'mux'
u_8combo_proc: process(result_low_o_i, adr_low_i, sel_sp_in_i)
begin
case sel_sp_in_i is
when '0' => result_low1_o_i <= result_low_o_i;
when '1' => result_low1_o_i <= adr_low_i;
when others => result_low1_o_i <= (others => 'X');
end case;
end process u_8combo_proc;
-- ModuleWare code(v1.12) for instance 'U_10' of 'tap'
adr_sp_low_o_i <= adr_sp_o_internal(7 downto 0);
-- Instance port mappings.
-- Implicit buffered output assignments
adr_sp_o <= adr_sp_o_internal;
end struct;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_dst_cols_V_shiftReg;
architecture rtl of FIFO_image_filter_p_dst_cols_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_cols_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_dst_cols_V is
component FIFO_image_filter_p_dst_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_dst_cols_V_shiftReg : FIFO_image_filter_p_dst_cols_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_p_dst_cols_V_shiftReg;
architecture rtl of FIFO_image_filter_p_dst_cols_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_p_dst_cols_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_p_dst_cols_V is
component FIFO_image_filter_p_dst_cols_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_p_dst_cols_V_shiftReg : FIFO_image_filter_p_dst_cols_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:47:26 09/30/2014
-- Design Name:
-- Module Name: /home/jpiat/development/FPGA/logi-family/logi-hard/test_bench/ADCS7446_ctrl_tb.vhd
-- Project Name: control_bot
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: ADCS7476_ctrl
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY ADCS7446_ctrl_tb IS
END ADCS7446_ctrl_tb;
ARCHITECTURE behavior OF ADCS7446_ctrl_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ADCS7476_ctrl
generic(clk_period_ns : positive := 10;
sclk_period_ns : positive := 40;
time_between_sample_ns : positive :=20_833
);
PORT(
clk : IN std_logic;
resetn : IN std_logic;
sclk : OUT std_logic;
ss : OUT std_logic;
miso : IN std_logic;
sample_out : OUT std_logic_vector(11 downto 0);
sample_valid : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal resetn : std_logic := '0';
signal miso : std_logic := '0';
--Outputs
signal sclk : std_logic;
signal ss : std_logic;
signal sample_out : std_logic_vector(11 downto 0);
signal sample_valid : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
constant sclk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: ADCS7476_ctrl
generic map(clk_period_ns => 10,
sclk_period_ns =>100,
time_between_sample_ns => 20833-- 48Khz ...
)
PORT MAP (
clk => clk,
resetn => resetn,
sclk => sclk,
ss => ss,
miso => miso,
sample_out => sample_out,
sample_valid => sample_valid
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
resetn <= '0' ;
wait for 100 ns;
resetn <= '1' ;
miso <= '1' ;
for i in 0 to 16 loop
wait until sclk = '0';
miso <= not miso;
wait until sclk = '1';
end loop ;
-- insert stimulus here
wait;
end process;
END;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_mask_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_mask_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_mask_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_mask_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_mask_rows_V is
component FIFO_image_filter_mask_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_mask_rows_V_shiftReg : FIFO_image_filter_mask_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2014.4
-- Copyright (C) 2014 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity FIFO_image_filter_mask_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end FIFO_image_filter_mask_rows_V_shiftReg;
architecture rtl of FIFO_image_filter_mask_rows_V_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity FIFO_image_filter_mask_rows_V is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of FIFO_image_filter_mask_rows_V is
component FIFO_image_filter_mask_rows_V_shiftReg is
generic (
DATA_WIDTH : integer := 12;
ADDR_WIDTH : integer := 2;
DEPTH : integer := 3);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr -1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr +1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH -2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_FIFO_image_filter_mask_rows_V_shiftReg : FIFO_image_filter_mask_rows_V_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
----------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2010 Aeroflex Gaisler
----------------------------------------------------------------------------
-- Entity: ahbrom
-- File: ahbrom.vhd
-- Author: Jiri Gaisler - Gaisler Research
-- Description: AHB rom. 0/1-waitstate read
----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
entity ahbrom is
generic (
hindex : integer := 0;
haddr : integer := 0;
hmask : integer := 16#fff#;
pipe : integer := 0;
tech : integer := 0;
kbytes : integer := 1);
port (
rst : in std_ulogic;
clk : in std_ulogic;
ahbsi : in ahb_slv_in_type;
ahbso : out ahb_slv_out_type
);
end;
architecture rtl of ahbrom is
constant abits : integer := 10;
constant bytes : integer := 560;
constant hconfig : ahb_config_type := (
0 => ahb_device_reg ( VENDOR_GAISLER, GAISLER_AHBROM, 0, 0, 0),
4 => ahb_membar(haddr, '1', '1', hmask), others => zero32);
signal romdata : std_logic_vector(31 downto 0);
signal addr : std_logic_vector(abits-1 downto 2);
signal hsel, hready : std_ulogic;
begin
ahbso.hresp <= "00";
ahbso.hsplit <= (others => '0');
ahbso.hirq <= (others => '0');
ahbso.hconfig <= hconfig;
ahbso.hindex <= hindex;
reg : process (clk)
begin
if rising_edge(clk) then
addr <= ahbsi.haddr(abits-1 downto 2);
end if;
end process;
p0 : if pipe = 0 generate
ahbso.hrdata <= ahbdrivedata(romdata);
ahbso.hready <= '1';
end generate;
p1 : if pipe = 1 generate
reg2 : process (clk)
begin
if rising_edge(clk) then
hsel <= ahbsi.hsel(hindex) and ahbsi.htrans(1);
hready <= ahbsi.hready;
ahbso.hready <= (not rst) or (hsel and hready) or
(ahbsi.hsel(hindex) and not ahbsi.htrans(1) and ahbsi.hready);
ahbso.hrdata <= ahbdrivedata(romdata);
end if;
end process;
end generate;
comb : process (addr)
begin
case conv_integer(addr) is
when 16#00000# => romdata <= X"81D82000";
when 16#00001# => romdata <= X"03000004";
when 16#00002# => romdata <= X"821060E0";
when 16#00003# => romdata <= X"81884000";
when 16#00004# => romdata <= X"81900000";
when 16#00005# => romdata <= X"81980000";
when 16#00006# => romdata <= X"81800000";
when 16#00007# => romdata <= X"A1800000";
when 16#00008# => romdata <= X"01000000";
when 16#00009# => romdata <= X"03002040";
when 16#0000A# => romdata <= X"8210600F";
when 16#0000B# => romdata <= X"C2A00040";
when 16#0000C# => romdata <= X"84100000";
when 16#0000D# => romdata <= X"01000000";
when 16#0000E# => romdata <= X"01000000";
when 16#0000F# => romdata <= X"01000000";
when 16#00010# => romdata <= X"01000000";
when 16#00011# => romdata <= X"01000000";
when 16#00012# => romdata <= X"80108002";
when 16#00013# => romdata <= X"01000000";
when 16#00014# => romdata <= X"01000000";
when 16#00015# => romdata <= X"01000000";
when 16#00016# => romdata <= X"01000000";
when 16#00017# => romdata <= X"01000000";
when 16#00018# => romdata <= X"87444000";
when 16#00019# => romdata <= X"8608E01F";
when 16#0001A# => romdata <= X"88100000";
when 16#0001B# => romdata <= X"8A100000";
when 16#0001C# => romdata <= X"8C100000";
when 16#0001D# => romdata <= X"8E100000";
when 16#0001E# => romdata <= X"A0100000";
when 16#0001F# => romdata <= X"A2100000";
when 16#00020# => romdata <= X"A4100000";
when 16#00021# => romdata <= X"A6100000";
when 16#00022# => romdata <= X"A8100000";
when 16#00023# => romdata <= X"AA100000";
when 16#00024# => romdata <= X"AC100000";
when 16#00025# => romdata <= X"AE100000";
when 16#00026# => romdata <= X"90100000";
when 16#00027# => romdata <= X"92100000";
when 16#00028# => romdata <= X"94100000";
when 16#00029# => romdata <= X"96100000";
when 16#0002A# => romdata <= X"98100000";
when 16#0002B# => romdata <= X"9A100000";
when 16#0002C# => romdata <= X"9C100000";
when 16#0002D# => romdata <= X"9E100000";
when 16#0002E# => romdata <= X"86A0E001";
when 16#0002F# => romdata <= X"16BFFFEF";
when 16#00030# => romdata <= X"81E00000";
when 16#00031# => romdata <= X"82102002";
when 16#00032# => romdata <= X"81904000";
when 16#00033# => romdata <= X"03000004";
when 16#00034# => romdata <= X"821060E0";
when 16#00035# => romdata <= X"81884000";
when 16#00036# => romdata <= X"01000000";
when 16#00037# => romdata <= X"01000000";
when 16#00038# => romdata <= X"01000000";
when 16#00039# => romdata <= X"83480000";
when 16#0003A# => romdata <= X"8330600C";
when 16#0003B# => romdata <= X"80886001";
when 16#0003C# => romdata <= X"02800024";
when 16#0003D# => romdata <= X"01000000";
when 16#0003E# => romdata <= X"07000000";
when 16#0003F# => romdata <= X"8610E178";
when 16#00040# => romdata <= X"C108C000";
when 16#00041# => romdata <= X"C118C000";
when 16#00042# => romdata <= X"C518C000";
when 16#00043# => romdata <= X"C918C000";
when 16#00044# => romdata <= X"CD18C000";
when 16#00045# => romdata <= X"D118C000";
when 16#00046# => romdata <= X"D518C000";
when 16#00047# => romdata <= X"D918C000";
when 16#00048# => romdata <= X"DD18C000";
when 16#00049# => romdata <= X"E118C000";
when 16#0004A# => romdata <= X"E518C000";
when 16#0004B# => romdata <= X"E918C000";
when 16#0004C# => romdata <= X"ED18C000";
when 16#0004D# => romdata <= X"F118C000";
when 16#0004E# => romdata <= X"F518C000";
when 16#0004F# => romdata <= X"F918C000";
when 16#00050# => romdata <= X"FD18C000";
when 16#00051# => romdata <= X"01000000";
when 16#00052# => romdata <= X"01000000";
when 16#00053# => romdata <= X"01000000";
when 16#00054# => romdata <= X"01000000";
when 16#00055# => romdata <= X"01000000";
when 16#00056# => romdata <= X"89A00842";
when 16#00057# => romdata <= X"01000000";
when 16#00058# => romdata <= X"01000000";
when 16#00059# => romdata <= X"01000000";
when 16#0005A# => romdata <= X"01000000";
when 16#0005B# => romdata <= X"10800005";
when 16#0005C# => romdata <= X"01000000";
when 16#0005D# => romdata <= X"01000000";
when 16#0005E# => romdata <= X"00000000";
when 16#0005F# => romdata <= X"00000000";
when 16#00060# => romdata <= X"87444000";
when 16#00061# => romdata <= X"8730E01C";
when 16#00062# => romdata <= X"8688E00F";
when 16#00063# => romdata <= X"12800016";
when 16#00064# => romdata <= X"03200000";
when 16#00065# => romdata <= X"05040E00";
when 16#00066# => romdata <= X"8410A033";
when 16#00067# => romdata <= X"C4204000";
when 16#00068# => romdata <= X"0539A81B";
when 16#00069# => romdata <= X"8410A260";
when 16#0006A# => romdata <= X"C4206004";
when 16#0006B# => romdata <= X"050003FC";
when 16#0006C# => romdata <= X"C4206008";
when 16#0006D# => romdata <= X"82103860";
when 16#0006E# => romdata <= X"C4004000";
when 16#0006F# => romdata <= X"8530A00C";
when 16#00070# => romdata <= X"03000004";
when 16#00071# => romdata <= X"82106009";
when 16#00072# => romdata <= X"80A04002";
when 16#00073# => romdata <= X"12800006";
when 16#00074# => romdata <= X"033FFC00";
when 16#00075# => romdata <= X"82106100";
when 16#00076# => romdata <= X"0538201B";
when 16#00077# => romdata <= X"8410A260";
when 16#00078# => romdata <= X"C4204000";
when 16#00079# => romdata <= X"05000008";
when 16#0007A# => romdata <= X"82100000";
when 16#0007B# => romdata <= X"80A0E000";
when 16#0007C# => romdata <= X"02800005";
when 16#0007D# => romdata <= X"01000000";
when 16#0007E# => romdata <= X"82004002";
when 16#0007F# => romdata <= X"10BFFFFC";
when 16#00080# => romdata <= X"8620E001";
when 16#00081# => romdata <= X"3D100FFF";
when 16#00082# => romdata <= X"BC17A3E0";
when 16#00083# => romdata <= X"BC278001";
when 16#00084# => romdata <= X"9C27A060";
when 16#00085# => romdata <= X"03100000";
when 16#00086# => romdata <= X"81C04000";
when 16#00087# => romdata <= X"01000000";
when 16#00088# => romdata <= X"00000000";
when 16#00089# => romdata <= X"00000000";
when 16#0008A# => romdata <= X"00000000";
when 16#0008B# => romdata <= X"00000000";
when 16#0008C# => romdata <= X"00000000";
when others => romdata <= (others => '-');
end case;
end process;
-- pragma translate_off
bootmsg : report_version
generic map ("ahbrom" & tost(hindex) &
": 32-bit AHB ROM Module, " & tost(bytes/4) & " words, " & tost(abits-2) & " address bits" );
-- pragma translate_on
end;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fdiv_14_no_dsp_32;
ARCHITECTURE feedforward_ap_fdiv_14_no_dsp_32_arch OF feedforward_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fdiv_14_no_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fdiv_14_no_dsp_32;
ARCHITECTURE feedforward_ap_fdiv_14_no_dsp_32_arch OF feedforward_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fdiv_14_no_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fdiv_14_no_dsp_32;
ARCHITECTURE feedforward_ap_fdiv_14_no_dsp_32_arch OF feedforward_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fdiv_14_no_dsp_32_arch;
|
-- (c) Copyright 1995-2016 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:floating_point:7.1
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY floating_point_v7_1_1;
USE floating_point_v7_1_1.floating_point_v7_1_1;
ENTITY feedforward_ap_fdiv_14_no_dsp_32 IS
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
END feedforward_ap_fdiv_14_no_dsp_32;
ARCHITECTURE feedforward_ap_fdiv_14_no_dsp_32_arch OF feedforward_ap_fdiv_14_no_dsp_32 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "yes";
COMPONENT floating_point_v7_1_1 IS
GENERIC (
C_XDEVICEFAMILY : STRING;
C_HAS_ADD : INTEGER;
C_HAS_SUBTRACT : INTEGER;
C_HAS_MULTIPLY : INTEGER;
C_HAS_DIVIDE : INTEGER;
C_HAS_SQRT : INTEGER;
C_HAS_COMPARE : INTEGER;
C_HAS_FIX_TO_FLT : INTEGER;
C_HAS_FLT_TO_FIX : INTEGER;
C_HAS_FLT_TO_FLT : INTEGER;
C_HAS_RECIP : INTEGER;
C_HAS_RECIP_SQRT : INTEGER;
C_HAS_ABSOLUTE : INTEGER;
C_HAS_LOGARITHM : INTEGER;
C_HAS_EXPONENTIAL : INTEGER;
C_HAS_FMA : INTEGER;
C_HAS_FMS : INTEGER;
C_HAS_ACCUMULATOR_A : INTEGER;
C_HAS_ACCUMULATOR_S : INTEGER;
C_A_WIDTH : INTEGER;
C_A_FRACTION_WIDTH : INTEGER;
C_B_WIDTH : INTEGER;
C_B_FRACTION_WIDTH : INTEGER;
C_C_WIDTH : INTEGER;
C_C_FRACTION_WIDTH : INTEGER;
C_RESULT_WIDTH : INTEGER;
C_RESULT_FRACTION_WIDTH : INTEGER;
C_COMPARE_OPERATION : INTEGER;
C_LATENCY : INTEGER;
C_OPTIMIZATION : INTEGER;
C_MULT_USAGE : INTEGER;
C_BRAM_USAGE : INTEGER;
C_RATE : INTEGER;
C_ACCUM_INPUT_MSB : INTEGER;
C_ACCUM_MSB : INTEGER;
C_ACCUM_LSB : INTEGER;
C_HAS_UNDERFLOW : INTEGER;
C_HAS_OVERFLOW : INTEGER;
C_HAS_INVALID_OP : INTEGER;
C_HAS_DIVIDE_BY_ZERO : INTEGER;
C_HAS_ACCUM_OVERFLOW : INTEGER;
C_HAS_ACCUM_INPUT_OVERFLOW : INTEGER;
C_HAS_ACLKEN : INTEGER;
C_HAS_ARESETN : INTEGER;
C_THROTTLE_SCHEME : INTEGER;
C_HAS_A_TUSER : INTEGER;
C_HAS_A_TLAST : INTEGER;
C_HAS_B : INTEGER;
C_HAS_B_TUSER : INTEGER;
C_HAS_B_TLAST : INTEGER;
C_HAS_C : INTEGER;
C_HAS_C_TUSER : INTEGER;
C_HAS_C_TLAST : INTEGER;
C_HAS_OPERATION : INTEGER;
C_HAS_OPERATION_TUSER : INTEGER;
C_HAS_OPERATION_TLAST : INTEGER;
C_HAS_RESULT_TUSER : INTEGER;
C_HAS_RESULT_TLAST : INTEGER;
C_TLAST_RESOLUTION : INTEGER;
C_A_TDATA_WIDTH : INTEGER;
C_A_TUSER_WIDTH : INTEGER;
C_B_TDATA_WIDTH : INTEGER;
C_B_TUSER_WIDTH : INTEGER;
C_C_TDATA_WIDTH : INTEGER;
C_C_TUSER_WIDTH : INTEGER;
C_OPERATION_TDATA_WIDTH : INTEGER;
C_OPERATION_TUSER_WIDTH : INTEGER;
C_RESULT_TDATA_WIDTH : INTEGER;
C_RESULT_TUSER_WIDTH : INTEGER;
C_FIXED_DATA_UNSIGNED : INTEGER
);
PORT (
aclk : IN STD_LOGIC;
aclken : IN STD_LOGIC;
aresetn : IN STD_LOGIC;
s_axis_a_tvalid : IN STD_LOGIC;
s_axis_a_tready : OUT STD_LOGIC;
s_axis_a_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_a_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_a_tlast : IN STD_LOGIC;
s_axis_b_tvalid : IN STD_LOGIC;
s_axis_b_tready : OUT STD_LOGIC;
s_axis_b_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_b_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_b_tlast : IN STD_LOGIC;
s_axis_c_tvalid : IN STD_LOGIC;
s_axis_c_tready : OUT STD_LOGIC;
s_axis_c_tdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
s_axis_c_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_c_tlast : IN STD_LOGIC;
s_axis_operation_tvalid : IN STD_LOGIC;
s_axis_operation_tready : OUT STD_LOGIC;
s_axis_operation_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
s_axis_operation_tuser : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
s_axis_operation_tlast : IN STD_LOGIC;
m_axis_result_tvalid : OUT STD_LOGIC;
m_axis_result_tready : IN STD_LOGIC;
m_axis_result_tdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
m_axis_result_tuser : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
m_axis_result_tlast : OUT STD_LOGIC
);
END COMPONENT floating_point_v7_1_1;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "floating_point_v7_1_1,Vivado 2015.4.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF feedforward_ap_fdiv_14_no_dsp_32_arch : ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF feedforward_ap_fdiv_14_no_dsp_32_arch: ARCHITECTURE IS "feedforward_ap_fdiv_14_no_dsp_32,floating_point_v7_1_1,{x_ipProduct=Vivado 2015.4.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=floating_point,x_ipVersion=7.1,x_ipCoreRevision=1,x_ipLanguage=VHDL,x_ipSimLanguage=MIXED,C_XDEVICEFAMILY=virtex7,C_HAS_ADD=0,C_HAS_SUBTRACT=0,C_HAS_MULTIPLY=0,C_HAS_DIVIDE=1,C_HAS_SQRT=0,C_HAS_COMPARE=0,C_HAS_FIX_TO_FLT=0,C_HAS_FLT_TO_FIX=0,C_HAS_FLT_TO_FLT=0,C_HAS_RECIP=0,C_HAS_RECIP_SQRT=0,C_HAS_ABSOLUTE=0,C_HAS_LOGARITHM=0,C_HAS_EXPONENTIAL=0,C_HAS_FMA=0,C_HAS_FMS=0,C_HAS_ACCUMULATOR_A=0,C_HAS_ACCUMULATOR_S=0,C_A_WIDTH=32,C_A_FRACTION_WIDTH=24,C_B_WIDTH=32,C_B_FRACTION_WIDTH=24,C_C_WIDTH=32,C_C_FRACTION_WIDTH=24,C_RESULT_WIDTH=32,C_RESULT_FRACTION_WIDTH=24,C_COMPARE_OPERATION=8,C_LATENCY=14,C_OPTIMIZATION=1,C_MULT_USAGE=0,C_BRAM_USAGE=0,C_RATE=1,C_ACCUM_INPUT_MSB=32,C_ACCUM_MSB=32,C_ACCUM_LSB=-31,C_HAS_UNDERFLOW=0,C_HAS_OVERFLOW=0,C_HAS_INVALID_OP=0,C_HAS_DIVIDE_BY_ZERO=0,C_HAS_ACCUM_OVERFLOW=0,C_HAS_ACCUM_INPUT_OVERFLOW=0,C_HAS_ACLKEN=1,C_HAS_ARESETN=0,C_THROTTLE_SCHEME=3,C_HAS_A_TUSER=0,C_HAS_A_TLAST=0,C_HAS_B=1,C_HAS_B_TUSER=0,C_HAS_B_TLAST=0,C_HAS_C=0,C_HAS_C_TUSER=0,C_HAS_C_TLAST=0,C_HAS_OPERATION=0,C_HAS_OPERATION_TUSER=0,C_HAS_OPERATION_TLAST=0,C_HAS_RESULT_TUSER=0,C_HAS_RESULT_TLAST=0,C_TLAST_RESOLUTION=0,C_A_TDATA_WIDTH=32,C_A_TUSER_WIDTH=1,C_B_TDATA_WIDTH=32,C_B_TUSER_WIDTH=1,C_C_TDATA_WIDTH=32,C_C_TUSER_WIDTH=1,C_OPERATION_TDATA_WIDTH=8,C_OPERATION_TUSER_WIDTH=1,C_RESULT_TDATA_WIDTH=32,C_RESULT_TUSER_WIDTH=1,C_FIXED_DATA_UNSIGNED=0}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF aclk: SIGNAL IS "xilinx.com:signal:clock:1.0 aclk_intf CLK";
ATTRIBUTE X_INTERFACE_INFO OF aclken: SIGNAL IS "xilinx.com:signal:clockenable:1.0 aclken_intf CE";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_a_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_A TDATA";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TVALID";
ATTRIBUTE X_INTERFACE_INFO OF s_axis_b_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 S_AXIS_B TDATA";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tvalid: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TVALID";
ATTRIBUTE X_INTERFACE_INFO OF m_axis_result_tdata: SIGNAL IS "xilinx.com:interface:axis:1.0 M_AXIS_RESULT TDATA";
BEGIN
U0 : floating_point_v7_1_1
GENERIC MAP (
C_XDEVICEFAMILY => "virtex7",
C_HAS_ADD => 0,
C_HAS_SUBTRACT => 0,
C_HAS_MULTIPLY => 0,
C_HAS_DIVIDE => 1,
C_HAS_SQRT => 0,
C_HAS_COMPARE => 0,
C_HAS_FIX_TO_FLT => 0,
C_HAS_FLT_TO_FIX => 0,
C_HAS_FLT_TO_FLT => 0,
C_HAS_RECIP => 0,
C_HAS_RECIP_SQRT => 0,
C_HAS_ABSOLUTE => 0,
C_HAS_LOGARITHM => 0,
C_HAS_EXPONENTIAL => 0,
C_HAS_FMA => 0,
C_HAS_FMS => 0,
C_HAS_ACCUMULATOR_A => 0,
C_HAS_ACCUMULATOR_S => 0,
C_A_WIDTH => 32,
C_A_FRACTION_WIDTH => 24,
C_B_WIDTH => 32,
C_B_FRACTION_WIDTH => 24,
C_C_WIDTH => 32,
C_C_FRACTION_WIDTH => 24,
C_RESULT_WIDTH => 32,
C_RESULT_FRACTION_WIDTH => 24,
C_COMPARE_OPERATION => 8,
C_LATENCY => 14,
C_OPTIMIZATION => 1,
C_MULT_USAGE => 0,
C_BRAM_USAGE => 0,
C_RATE => 1,
C_ACCUM_INPUT_MSB => 32,
C_ACCUM_MSB => 32,
C_ACCUM_LSB => -31,
C_HAS_UNDERFLOW => 0,
C_HAS_OVERFLOW => 0,
C_HAS_INVALID_OP => 0,
C_HAS_DIVIDE_BY_ZERO => 0,
C_HAS_ACCUM_OVERFLOW => 0,
C_HAS_ACCUM_INPUT_OVERFLOW => 0,
C_HAS_ACLKEN => 1,
C_HAS_ARESETN => 0,
C_THROTTLE_SCHEME => 3,
C_HAS_A_TUSER => 0,
C_HAS_A_TLAST => 0,
C_HAS_B => 1,
C_HAS_B_TUSER => 0,
C_HAS_B_TLAST => 0,
C_HAS_C => 0,
C_HAS_C_TUSER => 0,
C_HAS_C_TLAST => 0,
C_HAS_OPERATION => 0,
C_HAS_OPERATION_TUSER => 0,
C_HAS_OPERATION_TLAST => 0,
C_HAS_RESULT_TUSER => 0,
C_HAS_RESULT_TLAST => 0,
C_TLAST_RESOLUTION => 0,
C_A_TDATA_WIDTH => 32,
C_A_TUSER_WIDTH => 1,
C_B_TDATA_WIDTH => 32,
C_B_TUSER_WIDTH => 1,
C_C_TDATA_WIDTH => 32,
C_C_TUSER_WIDTH => 1,
C_OPERATION_TDATA_WIDTH => 8,
C_OPERATION_TUSER_WIDTH => 1,
C_RESULT_TDATA_WIDTH => 32,
C_RESULT_TUSER_WIDTH => 1,
C_FIXED_DATA_UNSIGNED => 0
)
PORT MAP (
aclk => aclk,
aclken => aclken,
aresetn => '1',
s_axis_a_tvalid => s_axis_a_tvalid,
s_axis_a_tdata => s_axis_a_tdata,
s_axis_a_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_a_tlast => '0',
s_axis_b_tvalid => s_axis_b_tvalid,
s_axis_b_tdata => s_axis_b_tdata,
s_axis_b_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_b_tlast => '0',
s_axis_c_tvalid => '0',
s_axis_c_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
s_axis_c_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_c_tlast => '0',
s_axis_operation_tvalid => '0',
s_axis_operation_tdata => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
s_axis_operation_tuser => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
s_axis_operation_tlast => '0',
m_axis_result_tvalid => m_axis_result_tvalid,
m_axis_result_tready => '0',
m_axis_result_tdata => m_axis_result_tdata
);
END feedforward_ap_fdiv_14_no_dsp_32_arch;
|
-- Output FIR.
-- 4 channels, with input strobe. [might become 8...]
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.all;
use work.defs.all;
entity lowfir is
generic(acc_width : integer := 37;
out_width : integer := 18);
port(d : in signed18;
d_last : in std_logic;
q : out signed(out_width - 1 downto 0);
q_strobe : out std_logic; -- Asserted on the first cycle with new data.
q_last : out std_logic;
clk : in std_logic);
end lowfir;
architecture lowfir of lowfir is
constant index_sample_strobe : integer := 18;
constant index_out_strobe : integer := 19;
constant index_pc_reset : integer := 20;
constant index_read_reset : integer := 21;
constant index_mac_accum : integer := 22;
constant program_size : integer := 400;
-- Min coeff is -28805
-- Max coeff is 131071
-- Sum of coeffs is 594566
-- Number of coeffs is 400
constant program : program_t(0 to program_size - 1) := (
x"07fff8", x"4bfff3", x"43ffef", x"43fff3", x"400005",
x"400026", x"400053", x"400084", x"4000aa", x"4000b9",
x"4000a7", x"400075", x"40002f", x"43ffe9", x"43ffb8",
x"43ffad", x"43ffc8", x"43fffd", x"400034", x"400054",
x"40004e", x"400024", x"43ffe7", x"43ffb4", x"43ffa2",
x"43ffbd", x"43fffa", x"40003d", x"400067", x"400062",
x"40002d", x"43ffde", x"43ff9a", x"43ff83", x"43ffa7",
x"43fff9", x"400055", x"40008d", x"400085", x"40003b",
x"43ffcf", x"43ff73", x"43ff56", x"43ff8a", x"43fffb",
x"400077", x"4000c2", x"4000b2", x"40004a", x"43ffb7",
x"43ff3d", x"43ff1b", x"43ff66", x"400003", x"4000a8",
x"400106", x"4000ea", x"400058", x"43ff92", x"43fef5",
x"43fed1", x"43ff40", x"400014", x"4000eb", x"40015d",
x"40012a", x"400061", x"43ff5d", x"43fe98", x"43fe79",
x"43ff18", x"400033", x"400145", x"4001c8", x"400172",
x"400061", x"43ff10", x"43fe22", x"43fe11", x"43fef3",
x"400066", x"4001bc", x"40024a", x"4001c0", x"400051",
x"43fea6", x"43fd8e", x"43fd9b", x"43fed6", x"4000b5",
x"400254", x"4002e4", x"40020f", x"40002b", x"43fe18",
x"43fcd9", x"43fd17", x"43fec7", x"400127", x"400316",
x"400399", x"40025d", x"43ffe7", x"43fd5d", x"43fbfe",
x"43fc87", x"43fecd", x"4001c7", x"400408", x"400469",
x"4002a2", x"43ff79", x"43fc69", x"43faf8", x"43fbef",
x"43fef3", x"4002a2", x"400534", x"400555", x"4002d7",
x"43fed3", x"43fb31", x"43f9c0", x"43fb52", x"43ff47",
x"4003c9", x"4006a6", x"400660", x"4002f1", x"43fde3",
x"43f99f", x"43f84b", x"43fab4", x"43ffd9", x"400553",
x"400873", x"40078f", x"4002e4", x"43fc8e", x"43f799",
x"43f68a", x"43fa1a", x"4000c3", x"400766", x"400ab8",
x"4008eb", x"40029b", x"43faab", x"43f4f0", x"43f45f",
x"43f989", x"400231", x"400a3f", x"400dae", x"400a87",
x"4001f8", x"43f7ee", x"43f14c", x"43f192", x"43f907",
x"40046b", x"400e56", x"4011c1", x"400c8e", x"4000c1",
x"43f3c4", x"43ebfb", x"43eda4", x"43f899", x"400814",
x"4014b3", x"4017f1", x"400f6e", x"43fe74", x"43ecca",
x"43e33b", x"43e74f", x"43f842", x"400ed1", x"402034",
x"40231a", x"40146f", x"43f98f", x"43de96", x"43d132",
x"43da16", x"43f805", x"401f0a", x"403cb1", x"403ffb",
x"4021ce", x"43ea2d", x"43af81", x"438f7b", x"43a3f5",
x"43f7e7", x"408100", x"4120d3", x"41ada7", x"41ffff",
x"41ffff", x"41ada7", x"4120d3", x"408100", x"43f7e7",
x"43a3f5", x"438f7b", x"43af81", x"43ea2d", x"4021ce",
x"403ffb", x"403cb1", x"401f0a", x"43f805", x"43da16",
x"43d132", x"43de96", x"43f98f", x"40146f", x"40231a",
x"402034", x"400ed1", x"43f842", x"43e74f", x"43e33b",
x"43ecca", x"43fe74", x"400f6e", x"4017f1", x"4014b3",
x"400814", x"43f899", x"43eda4", x"43ebfb", x"43f3c4",
x"4000c1", x"400c8e", x"4011c1", x"400e56", x"40046b",
x"43f907", x"43f192", x"43f14c", x"43f7ee", x"4001f8",
x"400a87", x"400dae", x"400a3f", x"400231", x"43f989",
x"43f45f", x"43f4f0", x"43faab", x"40029b", x"4008eb",
x"400ab8", x"400766", x"4000c3", x"43fa1a", x"43f68a",
x"43f799", x"43fc8e", x"4002e4", x"40078f", x"400873",
x"400553", x"43ffd9", x"43fab4", x"43f84b", x"43f99f",
x"43fde3", x"4002f1", x"400660", x"4006a6", x"4003c9",
x"43ff47", x"43fb52", x"43f9c0", x"43fb31", x"43fed3",
x"4002d7", x"400555", x"400534", x"4002a2", x"43fef3",
x"43fbef", x"43faf8", x"43fc69", x"43ff79", x"4002a2",
x"400469", x"400408", x"4001c7", x"43fecd", x"43fc87",
x"43fbfe", x"43fd5d", x"43ffe7", x"40025d", x"400399",
x"400316", x"400127", x"43fec7", x"43fd17", x"43fcd9",
x"43fe18", x"40002b", x"40020f", x"4002e4", x"400254",
x"4000b5", x"43fed6", x"43fd9b", x"43fd8e", x"43fea6",
x"400051", x"4001c0", x"40024a", x"4001bc", x"400066",
x"43fef3", x"43fe11", x"43fe22", x"43ff10", x"400061",
x"400172", x"4001c8", x"400145", x"400033", x"43ff18",
x"43fe79", x"43fe98", x"43ff5d", x"400061", x"40012a",
x"40015d", x"4000eb", x"400014", x"43ff40", x"43fed1",
x"43fef5", x"43ff92", x"400058", x"4000ea", x"400106",
x"4000a8", x"400003", x"43ff66", x"43ff1b", x"43ff3d",
x"43ffb7", x"40004a", x"4000b2", x"4000c2", x"400077",
x"43fffb", x"43ff8a", x"43ff56", x"43ff73", x"43ffcf",
x"40003b", x"400085", x"40008d", x"400055", x"43fff9",
x"43ffa7", x"43ff83", x"43ff9a", x"43ffde", x"40002d",
x"400062", x"400067", x"40003d", x"43fffa", x"43ffbd",
x"43ffa2", x"43ffb4", x"43ffe7", x"400024", x"40004e",
x"400054", x"400034", x"43fffd", x"43ffc8", x"43ffad",
x"43ffb8", x"43ffe9", x"40002f", x"400075", x"4000a7",
x"4000b9", x"4000aa", x"400084", x"400053", x"400026",
x"400005", x"43fff3", x"53ffef", x"63fff3", x"43fff8",
others => x"000000");
begin
fir : entity quadfir
generic map (acc_width, out_width, false,
index_sample_strobe,
index_out_strobe,
index_pc_reset,
index_read_reset,
index_mac_accum,
program_size,
program)
port map (d, d_last, q, q_strobe, q_last, clk);
end lowfir;
|
-------------------------------------------------------------------------------
-- emac - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- NODE_MAC -- EMACLite MAC address
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_adr -- Tx buffer address
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Tx_done -- Transmit done
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- Transmit idle
-- Rx_idle -- Receive idle
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_adr -- RX buffer address
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write/read enable
-- Rx_done -- Receive done
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Tx_packet_length -- Transmit packet length
-- Transmit_start -- Transmit Start
-- Mac_program_start -- MAC Program start
-- Rx_buffer_ready -- RX Buffer ready indicator
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac is
generic (
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
NODE_MAC : bit_vector := x"00005e00FACE";
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Phy_rx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_col : in std_logic;
Phy_rx_er : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_DPM_ce : out std_logic;
Tx_DPM_adr : out std_logic_vector (0 to 11);
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Rx_idle : out std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_adr : out std_logic_vector (0 to 11);
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Tx_packet_length : in std_logic_vector(0 to 15);
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Rx_buffer_ready : in std_logic
);
end emac;
architecture imp of emac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
signal phy_col_d1 : std_logic; -- added 3-03-05 MSH
signal phy_crs_d1 : std_logic; -- added 3-03-05 MSH
signal phy_col_d2 : std_logic; -- added 27-jul-2011
signal phy_crs_d2 : std_logic; -- added 27-jul-2011
signal rxbuffer_addr : std_logic_vector(0 to 11);
signal rx_addr_en : std_logic;
signal rx_start : std_logic;
signal txbuffer_addr : std_logic_vector(0 to 11);
signal tx_addr_en : std_logic;
signal tx_start : std_logic;
signal mac_addr_ram_addr : std_logic_vector(0 to 3);
signal mac_addr_ram_addr_rd : std_logic_vector(0 to 3);
signal mac_addr_ram_we : std_logic;
signal mac_addr_ram_addr_wr : std_logic_vector(0 to 3);
signal mac_addr_ram_data : std_logic_vector(0 to 3);
signal txClkEn : std_logic;
signal tx_clk_reg_d1 : std_logic;
signal tx_clk_reg_d2 : std_logic;
signal tx_clk_reg_d3 : std_logic;
signal mac_tx_frame_length : std_logic_vector(0 to 15);
signal nibbleLength : std_logic_vector(0 to 11);
signal nibbleLength_orig : std_logic_vector(0 to 11);
signal en_pad : std_logic;
signal Phy_tx_clk_axi_d : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- Receive Interface
----------------------------------------------------------------------------
RX: entity axi_ethernetlite_v3_0.receive
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
Phy_rx_clk => Phy_rx_clk,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Phy_rx_col => phy_col_d2,
Phy_rx_er => Phy_rx_er,
Rx_addr_en => rx_addr_en,
Rx_start => rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => mac_addr_ram_addr_rd,
Mac_addr_ram_data => mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
----------------------------------------------------------------------------
-- Transmit Interface
----------------------------------------------------------------------------
TX: entity axi_ethernetlite_v3_0.transmit
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
NibbleLength => nibbleLength,
NibbleLength_orig => nibbleLength_orig,
En_pad => en_pad,
TxClkEn => txClkEn,
Phy_tx_clk => Phy_tx_clk,
Phy_crs => phy_crs_d2,
Phy_col => phy_col_d2,
Phy_tx_en => phy_tx_en,
Phy_tx_data => phy_tx_data,
Tx_addr_en => tx_addr_en,
Tx_start => tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => Tx_idle,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_rd_data => Tx_DPM_rd_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => mac_addr_ram_we,
Mac_addr_ram_addr_wr => mac_addr_ram_addr_wr
);
----------------------------------------------------------------------------
-- Registerign PHY Col
----------------------------------------------------------------------------
COLLISION_SYNC_1: FDR
port map
(
Q => phy_col_d1, --[out]
C => Clk, --[in]
D => Phy_col, --[in]
R => Rst --[in]
);
COLLISION_SYNC_2: FDR
port map
(
Q => phy_col_d2, --[out]
C => Clk, --[in]
D => phy_col_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Registerign PHY CRs
----------------------------------------------------------------------------
C_SENSE_SYNC_1: FDR
port map
(
Q => phy_crs_d1, --[out]
C => Clk, --[in]
D => Phy_crs, --[in]
R => Rst --[in]
);
C_SENSE_SYNC_2: FDR
port map
(
Q => phy_crs_d2, --[out]
C => Clk, --[in]
D => phy_crs_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- MAC Address RAM
----------------------------------------------------------------------------
NODEMACADDRRAMI: entity axi_ethernetlite_v3_0.MacAddrRAM
generic map
(
MACAddr => NODE_MAC
)
port map
(
addr => mac_addr_ram_addr,
dout => mac_addr_ram_data,
din => Tx_DPM_rd_data,
we => mac_addr_ram_we,
Clk => Clk
);
mac_addr_ram_addr <= mac_addr_ram_addr_rd when mac_addr_ram_we = '0' else
mac_addr_ram_addr_wr;
----------------------------------------------------------------------------
-- RX Address Counter for the RxBuffer
----------------------------------------------------------------------------
RXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_start = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_addr_en = '1' then
rxbuffer_addr <= rxbuffer_addr + 1;
end if;
end if;
end process RXADDRCNT;
Rx_DPM_adr <= rxbuffer_addr;
----------------------------------------------------------------------------
-- TX Address Counter for the TxBuffer (To Read)
----------------------------------------------------------------------------
TXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
txbuffer_addr <= (others => '0');
elsif tx_start = '1' then
txbuffer_addr <= (others => '0');
elsif tx_addr_en = '1' then
txbuffer_addr <= txbuffer_addr + 1;
end if;
end if;
end process TXADDRCNT;
Tx_DPM_adr <= txbuffer_addr;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_clk in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_CLK: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Phy_tx_clk,
prmry_ack => open,
scndry_out => Phy_tx_clk_axi_d,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_clk_sync_PROCESS
----------------------------------------------------------------------------
-- This process syncronizes the tx Clk and generates an enable pulse
----------------------------------------------------------------------------
INT_TX_CLK_SYNC_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
tx_clk_reg_d1 <= '0';
tx_clk_reg_d2 <= '0';
tx_clk_reg_d3 <= '0';
else
tx_clk_reg_d1 <= Phy_tx_clk_axi_d;
tx_clk_reg_d2 <= tx_clk_reg_d1;
tx_clk_reg_d3 <= tx_clk_reg_d2;
end if;
end if;
end process INT_TX_CLK_SYNC_PROCESS;
txClkEn <= '1' when tx_clk_reg_d2 = '1' and tx_clk_reg_d3 = '0' else
'0';
----------------------------------------------------------------------------
-- ADJP
----------------------------------------------------------------------------
-- Adjust the packet length is it is less than minimum
----------------------------------------------------------------------------
ADJP : process(mac_tx_frame_length)
begin
if mac_tx_frame_length > MinimumPacketLength then
nibbleLength <= mac_tx_frame_length(5 to 15) & '0';
en_pad <= '0';
else
nibbleLength <= MinimumPacketLength(5 to 15) & '0';
en_pad <= '1';
end if;
end process ADJP;
nibbleLength_orig <= mac_tx_frame_length(5 to 15) & '0';
mac_tx_frame_length <= Tx_packet_length;
----------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------------------
-- emac - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- NODE_MAC -- EMACLite MAC address
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_adr -- Tx buffer address
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Tx_done -- Transmit done
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- Transmit idle
-- Rx_idle -- Receive idle
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_adr -- RX buffer address
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write/read enable
-- Rx_done -- Receive done
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Tx_packet_length -- Transmit packet length
-- Transmit_start -- Transmit Start
-- Mac_program_start -- MAC Program start
-- Rx_buffer_ready -- RX Buffer ready indicator
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac is
generic (
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
NODE_MAC : bit_vector := x"00005e00FACE";
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Phy_rx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_col : in std_logic;
Phy_rx_er : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_DPM_ce : out std_logic;
Tx_DPM_adr : out std_logic_vector (0 to 11);
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Rx_idle : out std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_adr : out std_logic_vector (0 to 11);
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Tx_packet_length : in std_logic_vector(0 to 15);
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Rx_buffer_ready : in std_logic
);
end emac;
architecture imp of emac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
signal phy_col_d1 : std_logic; -- added 3-03-05 MSH
signal phy_crs_d1 : std_logic; -- added 3-03-05 MSH
signal phy_col_d2 : std_logic; -- added 27-jul-2011
signal phy_crs_d2 : std_logic; -- added 27-jul-2011
signal rxbuffer_addr : std_logic_vector(0 to 11);
signal rx_addr_en : std_logic;
signal rx_start : std_logic;
signal txbuffer_addr : std_logic_vector(0 to 11);
signal tx_addr_en : std_logic;
signal tx_start : std_logic;
signal mac_addr_ram_addr : std_logic_vector(0 to 3);
signal mac_addr_ram_addr_rd : std_logic_vector(0 to 3);
signal mac_addr_ram_we : std_logic;
signal mac_addr_ram_addr_wr : std_logic_vector(0 to 3);
signal mac_addr_ram_data : std_logic_vector(0 to 3);
signal txClkEn : std_logic;
signal tx_clk_reg_d1 : std_logic;
signal tx_clk_reg_d2 : std_logic;
signal tx_clk_reg_d3 : std_logic;
signal mac_tx_frame_length : std_logic_vector(0 to 15);
signal nibbleLength : std_logic_vector(0 to 11);
signal nibbleLength_orig : std_logic_vector(0 to 11);
signal en_pad : std_logic;
signal Phy_tx_clk_axi_d : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- Receive Interface
----------------------------------------------------------------------------
RX: entity axi_ethernetlite_v3_0.receive
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
Phy_rx_clk => Phy_rx_clk,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Phy_rx_col => phy_col_d2,
Phy_rx_er => Phy_rx_er,
Rx_addr_en => rx_addr_en,
Rx_start => rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => mac_addr_ram_addr_rd,
Mac_addr_ram_data => mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
----------------------------------------------------------------------------
-- Transmit Interface
----------------------------------------------------------------------------
TX: entity axi_ethernetlite_v3_0.transmit
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
NibbleLength => nibbleLength,
NibbleLength_orig => nibbleLength_orig,
En_pad => en_pad,
TxClkEn => txClkEn,
Phy_tx_clk => Phy_tx_clk,
Phy_crs => phy_crs_d2,
Phy_col => phy_col_d2,
Phy_tx_en => phy_tx_en,
Phy_tx_data => phy_tx_data,
Tx_addr_en => tx_addr_en,
Tx_start => tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => Tx_idle,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_rd_data => Tx_DPM_rd_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => mac_addr_ram_we,
Mac_addr_ram_addr_wr => mac_addr_ram_addr_wr
);
----------------------------------------------------------------------------
-- Registerign PHY Col
----------------------------------------------------------------------------
COLLISION_SYNC_1: FDR
port map
(
Q => phy_col_d1, --[out]
C => Clk, --[in]
D => Phy_col, --[in]
R => Rst --[in]
);
COLLISION_SYNC_2: FDR
port map
(
Q => phy_col_d2, --[out]
C => Clk, --[in]
D => phy_col_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Registerign PHY CRs
----------------------------------------------------------------------------
C_SENSE_SYNC_1: FDR
port map
(
Q => phy_crs_d1, --[out]
C => Clk, --[in]
D => Phy_crs, --[in]
R => Rst --[in]
);
C_SENSE_SYNC_2: FDR
port map
(
Q => phy_crs_d2, --[out]
C => Clk, --[in]
D => phy_crs_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- MAC Address RAM
----------------------------------------------------------------------------
NODEMACADDRRAMI: entity axi_ethernetlite_v3_0.MacAddrRAM
generic map
(
MACAddr => NODE_MAC
)
port map
(
addr => mac_addr_ram_addr,
dout => mac_addr_ram_data,
din => Tx_DPM_rd_data,
we => mac_addr_ram_we,
Clk => Clk
);
mac_addr_ram_addr <= mac_addr_ram_addr_rd when mac_addr_ram_we = '0' else
mac_addr_ram_addr_wr;
----------------------------------------------------------------------------
-- RX Address Counter for the RxBuffer
----------------------------------------------------------------------------
RXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_start = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_addr_en = '1' then
rxbuffer_addr <= rxbuffer_addr + 1;
end if;
end if;
end process RXADDRCNT;
Rx_DPM_adr <= rxbuffer_addr;
----------------------------------------------------------------------------
-- TX Address Counter for the TxBuffer (To Read)
----------------------------------------------------------------------------
TXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
txbuffer_addr <= (others => '0');
elsif tx_start = '1' then
txbuffer_addr <= (others => '0');
elsif tx_addr_en = '1' then
txbuffer_addr <= txbuffer_addr + 1;
end if;
end if;
end process TXADDRCNT;
Tx_DPM_adr <= txbuffer_addr;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_clk in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_CLK: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Phy_tx_clk,
prmry_ack => open,
scndry_out => Phy_tx_clk_axi_d,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_clk_sync_PROCESS
----------------------------------------------------------------------------
-- This process syncronizes the tx Clk and generates an enable pulse
----------------------------------------------------------------------------
INT_TX_CLK_SYNC_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
tx_clk_reg_d1 <= '0';
tx_clk_reg_d2 <= '0';
tx_clk_reg_d3 <= '0';
else
tx_clk_reg_d1 <= Phy_tx_clk_axi_d;
tx_clk_reg_d2 <= tx_clk_reg_d1;
tx_clk_reg_d3 <= tx_clk_reg_d2;
end if;
end if;
end process INT_TX_CLK_SYNC_PROCESS;
txClkEn <= '1' when tx_clk_reg_d2 = '1' and tx_clk_reg_d3 = '0' else
'0';
----------------------------------------------------------------------------
-- ADJP
----------------------------------------------------------------------------
-- Adjust the packet length is it is less than minimum
----------------------------------------------------------------------------
ADJP : process(mac_tx_frame_length)
begin
if mac_tx_frame_length > MinimumPacketLength then
nibbleLength <= mac_tx_frame_length(5 to 15) & '0';
en_pad <= '0';
else
nibbleLength <= MinimumPacketLength(5 to 15) & '0';
en_pad <= '1';
end if;
end process ADJP;
nibbleLength_orig <= mac_tx_frame_length(5 to 15) & '0';
mac_tx_frame_length <= Tx_packet_length;
----------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------------------
-- emac - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- NODE_MAC -- EMACLite MAC address
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_adr -- Tx buffer address
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Tx_done -- Transmit done
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- Transmit idle
-- Rx_idle -- Receive idle
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_adr -- RX buffer address
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write/read enable
-- Rx_done -- Receive done
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Tx_packet_length -- Transmit packet length
-- Transmit_start -- Transmit Start
-- Mac_program_start -- MAC Program start
-- Rx_buffer_ready -- RX Buffer ready indicator
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac is
generic (
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
NODE_MAC : bit_vector := x"00005e00FACE";
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Phy_rx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_col : in std_logic;
Phy_rx_er : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_DPM_ce : out std_logic;
Tx_DPM_adr : out std_logic_vector (0 to 11);
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Rx_idle : out std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_adr : out std_logic_vector (0 to 11);
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Tx_packet_length : in std_logic_vector(0 to 15);
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Rx_buffer_ready : in std_logic
);
end emac;
architecture imp of emac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
signal phy_col_d1 : std_logic; -- added 3-03-05 MSH
signal phy_crs_d1 : std_logic; -- added 3-03-05 MSH
signal phy_col_d2 : std_logic; -- added 27-jul-2011
signal phy_crs_d2 : std_logic; -- added 27-jul-2011
signal rxbuffer_addr : std_logic_vector(0 to 11);
signal rx_addr_en : std_logic;
signal rx_start : std_logic;
signal txbuffer_addr : std_logic_vector(0 to 11);
signal tx_addr_en : std_logic;
signal tx_start : std_logic;
signal mac_addr_ram_addr : std_logic_vector(0 to 3);
signal mac_addr_ram_addr_rd : std_logic_vector(0 to 3);
signal mac_addr_ram_we : std_logic;
signal mac_addr_ram_addr_wr : std_logic_vector(0 to 3);
signal mac_addr_ram_data : std_logic_vector(0 to 3);
signal txClkEn : std_logic;
signal tx_clk_reg_d1 : std_logic;
signal tx_clk_reg_d2 : std_logic;
signal tx_clk_reg_d3 : std_logic;
signal mac_tx_frame_length : std_logic_vector(0 to 15);
signal nibbleLength : std_logic_vector(0 to 11);
signal nibbleLength_orig : std_logic_vector(0 to 11);
signal en_pad : std_logic;
signal Phy_tx_clk_axi_d : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- Receive Interface
----------------------------------------------------------------------------
RX: entity axi_ethernetlite_v3_0.receive
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
Phy_rx_clk => Phy_rx_clk,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Phy_rx_col => phy_col_d2,
Phy_rx_er => Phy_rx_er,
Rx_addr_en => rx_addr_en,
Rx_start => rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => mac_addr_ram_addr_rd,
Mac_addr_ram_data => mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
----------------------------------------------------------------------------
-- Transmit Interface
----------------------------------------------------------------------------
TX: entity axi_ethernetlite_v3_0.transmit
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
NibbleLength => nibbleLength,
NibbleLength_orig => nibbleLength_orig,
En_pad => en_pad,
TxClkEn => txClkEn,
Phy_tx_clk => Phy_tx_clk,
Phy_crs => phy_crs_d2,
Phy_col => phy_col_d2,
Phy_tx_en => phy_tx_en,
Phy_tx_data => phy_tx_data,
Tx_addr_en => tx_addr_en,
Tx_start => tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => Tx_idle,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_rd_data => Tx_DPM_rd_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => mac_addr_ram_we,
Mac_addr_ram_addr_wr => mac_addr_ram_addr_wr
);
----------------------------------------------------------------------------
-- Registerign PHY Col
----------------------------------------------------------------------------
COLLISION_SYNC_1: FDR
port map
(
Q => phy_col_d1, --[out]
C => Clk, --[in]
D => Phy_col, --[in]
R => Rst --[in]
);
COLLISION_SYNC_2: FDR
port map
(
Q => phy_col_d2, --[out]
C => Clk, --[in]
D => phy_col_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Registerign PHY CRs
----------------------------------------------------------------------------
C_SENSE_SYNC_1: FDR
port map
(
Q => phy_crs_d1, --[out]
C => Clk, --[in]
D => Phy_crs, --[in]
R => Rst --[in]
);
C_SENSE_SYNC_2: FDR
port map
(
Q => phy_crs_d2, --[out]
C => Clk, --[in]
D => phy_crs_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- MAC Address RAM
----------------------------------------------------------------------------
NODEMACADDRRAMI: entity axi_ethernetlite_v3_0.MacAddrRAM
generic map
(
MACAddr => NODE_MAC
)
port map
(
addr => mac_addr_ram_addr,
dout => mac_addr_ram_data,
din => Tx_DPM_rd_data,
we => mac_addr_ram_we,
Clk => Clk
);
mac_addr_ram_addr <= mac_addr_ram_addr_rd when mac_addr_ram_we = '0' else
mac_addr_ram_addr_wr;
----------------------------------------------------------------------------
-- RX Address Counter for the RxBuffer
----------------------------------------------------------------------------
RXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_start = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_addr_en = '1' then
rxbuffer_addr <= rxbuffer_addr + 1;
end if;
end if;
end process RXADDRCNT;
Rx_DPM_adr <= rxbuffer_addr;
----------------------------------------------------------------------------
-- TX Address Counter for the TxBuffer (To Read)
----------------------------------------------------------------------------
TXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
txbuffer_addr <= (others => '0');
elsif tx_start = '1' then
txbuffer_addr <= (others => '0');
elsif tx_addr_en = '1' then
txbuffer_addr <= txbuffer_addr + 1;
end if;
end if;
end process TXADDRCNT;
Tx_DPM_adr <= txbuffer_addr;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_clk in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_CLK: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Phy_tx_clk,
prmry_ack => open,
scndry_out => Phy_tx_clk_axi_d,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_clk_sync_PROCESS
----------------------------------------------------------------------------
-- This process syncronizes the tx Clk and generates an enable pulse
----------------------------------------------------------------------------
INT_TX_CLK_SYNC_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
tx_clk_reg_d1 <= '0';
tx_clk_reg_d2 <= '0';
tx_clk_reg_d3 <= '0';
else
tx_clk_reg_d1 <= Phy_tx_clk_axi_d;
tx_clk_reg_d2 <= tx_clk_reg_d1;
tx_clk_reg_d3 <= tx_clk_reg_d2;
end if;
end if;
end process INT_TX_CLK_SYNC_PROCESS;
txClkEn <= '1' when tx_clk_reg_d2 = '1' and tx_clk_reg_d3 = '0' else
'0';
----------------------------------------------------------------------------
-- ADJP
----------------------------------------------------------------------------
-- Adjust the packet length is it is less than minimum
----------------------------------------------------------------------------
ADJP : process(mac_tx_frame_length)
begin
if mac_tx_frame_length > MinimumPacketLength then
nibbleLength <= mac_tx_frame_length(5 to 15) & '0';
en_pad <= '0';
else
nibbleLength <= MinimumPacketLength(5 to 15) & '0';
en_pad <= '1';
end if;
end process ADJP;
nibbleLength_orig <= mac_tx_frame_length(5 to 15) & '0';
mac_tx_frame_length <= Tx_packet_length;
----------------------------------------------------------------------------
end imp;
|
-------------------------------------------------------------------------------
-- emac - entity/architecture pair
-------------------------------------------------------------------------------
-- ***************************************************************************
-- ** DISCLAIMER OF LIABILITY **
-- ** **
-- ** This file contains proprietary and confidential information of **
-- ** Xilinx, Inc. ("Xilinx"), that is distributed under a license **
-- ** from Xilinx, and may be used, copied and/or disclosed only **
-- ** pursuant to the terms of a valid license agreement with Xilinx. **
-- ** **
-- ** XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION **
-- ** ("MATERIALS") "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER **
-- ** EXPRESSED, IMPLIED, OR STATUTORY, INCLUDING WITHOUT **
-- ** LIMITATION, ANY WARRANTY WITH RESPECT TO NONINFRINGEMENT, **
-- ** MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE. Xilinx **
-- ** does not warrant that functions included in the Materials will **
-- ** meet the requirements of Licensee, or that the operation of the **
-- ** Materials will be uninterrupted or error-free, or that defects **
-- ** in the Materials will be corrected. Furthermore, Xilinx does **
-- ** not warrant or make any representations regarding use, or the **
-- ** results of the use, of the Materials in terms of correctness, **
-- ** accuracy, reliability or otherwise. **
-- ** **
-- ** Xilinx products are not designed or intended to be fail-safe, **
-- ** or for use in any application requiring fail-safe performance, **
-- ** such as life-support or safety devices or systems, Class III **
-- ** medical devices, nuclear facilities, applications related to **
-- ** the deployment of airbags, or any other applications that could **
-- ** lead to death, personal injury or severe property or **
-- ** environmental damage (individually and collectively, "critical **
-- ** applications"). Customer assumes the sole risk and liability **
-- ** of any use of Xilinx products in critical applications, **
-- ** subject only to applicable laws and regulations governing **
-- ** limitations on product liability. **
-- ** **
-- ** Copyright 2010 Xilinx, Inc. **
-- ** All rights reserved. **
-- ** **
-- ** This disclaimer and copyright notice must be retained as part **
-- ** of this file at all times. **
-- ***************************************************************************
--
-------------------------------------------------------------------------------
-- Filename : emac.vhd
-- Version : v2.0
-- Description : Design file for the Ethernet Lite MAC.
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
--
-- axi_ethernetlite.vhd
-- \
-- \-- axi_interface.vhd
-- \-- xemac.vhd
-- \
-- \-- mdio_if.vhd
-- \-- emac_dpram.vhd
-- \ \
-- \ \-- RAMB16_S4_S36
-- \
-- \
-- \-- emac.vhd
-- \
-- \-- MacAddrRAM
-- \-- receive.vhd
-- \ rx_statemachine.vhd
-- \ rx_intrfce.vhd
-- \ async_fifo_fg.vhd
-- \ crcgenrx.vhd
-- \
-- \-- transmit.vhd
-- crcgentx.vhd
-- crcnibshiftreg
-- tx_intrfce.vhd
-- async_fifo_fg.vhd
-- tx_statemachine.vhd
-- deferral.vhd
-- cntr5bit.vhd
-- defer_state.vhd
-- bocntr.vhd
-- lfsr16.vhd
-- msh_cnt.vhd
-- ld_arith_reg.vhd
--
-------------------------------------------------------------------------------
-- Author: PVK
-- History:
-- PVK 06/07/2010 First Version
-- ^^^^^^
-- First version.
-- ~~~~~~
-------------------------------------------------------------------------------
-- Naming Conventions:
-- active low signals: "*_n"
-- clock signals: "Clk", "clk_div#", "clk_#x"
-- reset signals: "Rst", "rst_n"
-- generics: "C_*"
-- user defined types: "*_TYPE"
-- state machine next state: "*_ns"
-- state machine current state: "*_cs"
-- combinatorial signals: "*_com"
-- pipelined or register delay signals: "*_d#"
-- counter signals: "*cnt*"
-- clock enable signals: "*_ce"
-- internal version of output port "*_i"
-- device pins: "*_pin"
-- ports: - Names begin with Uppercase
-- processes: "*_PROCESS"
-- component instantiations: "<ENTITY_>I_<#|FUNC>
-------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-------------------------------------------------------------------------------
-- axi_ethernetlite_v3_0 library is used for axi_ethernetlite_v3_0
-- component declarations
-------------------------------------------------------------------------------
library axi_ethernetlite_v3_0;
use axi_ethernetlite_v3_0.mac_pkg.all;
use axi_ethernetlite_v3_0.all;
-------------------------------------------------------------------------------
-- Vcomponents from unisim library is used for FIFO instatiation
-- function declarations
-------------------------------------------------------------------------------
library unisim;
use unisim.Vcomponents.all;
library lib_cdc_v1_0;
use lib_cdc_v1_0.all;
-------------------------------------------------------------------------------
-- Definition of Generics:
-------------------------------------------------------------------------------
-- C_DUPLEX -- 1 = full duplex, 0 = half duplex
-- NODE_MAC -- EMACLite MAC address
-- C_FAMILY -- Target device family
-------------------------------------------------------------------------------
-- Definition of Ports:
--
-- Clk -- System Clock
-- Rst -- System Reset
-- PHY_tx_clk -- Ethernet tranmit clock
-- PHY_rx_clk -- Ethernet receive clock
-- PHY_crs -- Ethernet carrier sense
-- PHY_dv -- Ethernet receive data valid
-- PHY_rx_data -- Ethernet receive data
-- PHY_col -- Ethernet collision indicator
-- PHY_rx_er -- Ethernet receive error
-- PHY_rst_n -- Ethernet PHY Reset
-- PHY_tx_en -- Ethernet transmit enable
-- PHY_tx_data -- Ethernet transmit data
-- Tx_DPM_ce -- TX buffer chip enable
-- Tx_DPM_adr -- Tx buffer address
-- Tx_DPM_wr_data -- TX buffer write data
-- Tx_DPM_rd_data -- TX buffer read data
-- Tx_DPM_wr_rd_n -- TX buffer write/read enable
-- Tx_done -- Transmit done
-- Tx_pong_ping_l -- TX Ping/Pong buffer enable
-- Tx_idle -- Transmit idle
-- Rx_idle -- Receive idle
-- Rx_DPM_ce -- RX buffer chip enable
-- Rx_DPM_adr -- RX buffer address
-- Rx_DPM_wr_data -- RX buffer write data
-- Rx_DPM_rd_data -- RX buffer read data
-- Rx_DPM_wr_rd_n -- RX buffer write/read enable
-- Rx_done -- Receive done
-- Rx_pong_ping_l -- RX Ping/Pong buffer enable
-- Tx_packet_length -- Transmit packet length
-- Transmit_start -- Transmit Start
-- Mac_program_start -- MAC Program start
-- Rx_buffer_ready -- RX Buffer ready indicator
-------------------------------------------------------------------------------
-- ENTITY
-------------------------------------------------------------------------------
entity emac is
generic (
C_DUPLEX : integer := 1;
-- 1 = full duplex, 0 = half duplex
NODE_MAC : bit_vector := x"00005e00FACE";
C_FAMILY : string := "virtex6"
);
port (
Clk : in std_logic;
Rst : in std_logic;
Phy_tx_clk : in std_logic;
Phy_rx_clk : in std_logic;
Phy_crs : in std_logic;
Phy_dv : in std_logic;
Phy_rx_data : in std_logic_vector (0 to 3);
Phy_col : in std_logic;
Phy_rx_er : in std_logic;
Phy_tx_en : out std_logic;
Phy_tx_data : out std_logic_vector (0 to 3);
Tx_DPM_ce : out std_logic;
Tx_DPM_adr : out std_logic_vector (0 to 11);
Tx_DPM_wr_data : out std_logic_vector (0 to 3);
Tx_DPM_rd_data : in std_logic_vector (0 to 3);
Tx_DPM_wr_rd_n : out std_logic;
Tx_done : out std_logic;
Tx_pong_ping_l : in std_logic;
Tx_idle : out std_logic;
Rx_idle : out std_logic;
Rx_DPM_ce : out std_logic;
Rx_DPM_adr : out std_logic_vector (0 to 11);
Rx_DPM_wr_data : out std_logic_vector (0 to 3);
Rx_DPM_rd_data : in std_logic_vector (0 to 3);
Rx_DPM_wr_rd_n : out std_logic;
Rx_done : out std_logic;
Rx_pong_ping_l : in std_logic;
Tx_packet_length : in std_logic_vector(0 to 15);
Transmit_start : in std_logic;
Mac_program_start : in std_logic;
Rx_buffer_ready : in std_logic
);
end emac;
architecture imp of emac is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of imp : architecture is "yes";
-------------------------------------------------------------------------------
-- Constant Declarations
-------------------------------------------------------------------------------
signal phy_col_d1 : std_logic; -- added 3-03-05 MSH
signal phy_crs_d1 : std_logic; -- added 3-03-05 MSH
signal phy_col_d2 : std_logic; -- added 27-jul-2011
signal phy_crs_d2 : std_logic; -- added 27-jul-2011
signal rxbuffer_addr : std_logic_vector(0 to 11);
signal rx_addr_en : std_logic;
signal rx_start : std_logic;
signal txbuffer_addr : std_logic_vector(0 to 11);
signal tx_addr_en : std_logic;
signal tx_start : std_logic;
signal mac_addr_ram_addr : std_logic_vector(0 to 3);
signal mac_addr_ram_addr_rd : std_logic_vector(0 to 3);
signal mac_addr_ram_we : std_logic;
signal mac_addr_ram_addr_wr : std_logic_vector(0 to 3);
signal mac_addr_ram_data : std_logic_vector(0 to 3);
signal txClkEn : std_logic;
signal tx_clk_reg_d1 : std_logic;
signal tx_clk_reg_d2 : std_logic;
signal tx_clk_reg_d3 : std_logic;
signal mac_tx_frame_length : std_logic_vector(0 to 15);
signal nibbleLength : std_logic_vector(0 to 11);
signal nibbleLength_orig : std_logic_vector(0 to 11);
signal en_pad : std_logic;
signal Phy_tx_clk_axi_d : std_logic;
-------------------------------------------------------------------------------
-- Component Declarations
-------------------------------------------------------------------------------
-- The following components are the building blocks of the EMAC
component FDR
port (
Q : out std_logic;
C : in std_logic;
D : in std_logic;
R : in std_logic
);
end component;
begin
----------------------------------------------------------------------------
-- Receive Interface
----------------------------------------------------------------------------
RX: entity axi_ethernetlite_v3_0.receive
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
Phy_rx_clk => Phy_rx_clk,
Phy_dv => Phy_dv,
Phy_rx_data => Phy_rx_data,
Phy_rx_col => phy_col_d2,
Phy_rx_er => Phy_rx_er,
Rx_addr_en => rx_addr_en,
Rx_start => rx_start,
Rx_done => Rx_done,
Rx_pong_ping_l => Rx_pong_ping_l,
Rx_DPM_ce => Rx_DPM_ce,
Rx_DPM_wr_data => Rx_DPM_wr_data,
Rx_DPM_rd_data => Rx_DPM_rd_data,
Rx_DPM_wr_rd_n => Rx_DPM_wr_rd_n,
Rx_idle => Rx_idle,
Mac_addr_ram_addr_rd => mac_addr_ram_addr_rd,
Mac_addr_ram_data => mac_addr_ram_data,
Rx_buffer_ready => Rx_buffer_ready
);
----------------------------------------------------------------------------
-- Transmit Interface
----------------------------------------------------------------------------
TX: entity axi_ethernetlite_v3_0.transmit
generic map
(
C_DUPLEX => C_DUPLEX,
C_FAMILY => C_FAMILY
)
port map
(
Clk => Clk,
Rst => Rst,
NibbleLength => nibbleLength,
NibbleLength_orig => nibbleLength_orig,
En_pad => en_pad,
TxClkEn => txClkEn,
Phy_tx_clk => Phy_tx_clk,
Phy_crs => phy_crs_d2,
Phy_col => phy_col_d2,
Phy_tx_en => phy_tx_en,
Phy_tx_data => phy_tx_data,
Tx_addr_en => tx_addr_en,
Tx_start => tx_start,
Tx_done => Tx_done,
Tx_pong_ping_l => Tx_pong_ping_l,
Tx_idle => Tx_idle,
Tx_DPM_ce => Tx_DPM_ce,
Tx_DPM_wr_data => Tx_DPM_wr_data,
Tx_DPM_rd_data => Tx_DPM_rd_data,
Tx_DPM_wr_rd_n => Tx_DPM_wr_rd_n,
Transmit_start => Transmit_start,
Mac_program_start => Mac_program_start,
Mac_addr_ram_we => mac_addr_ram_we,
Mac_addr_ram_addr_wr => mac_addr_ram_addr_wr
);
----------------------------------------------------------------------------
-- Registerign PHY Col
----------------------------------------------------------------------------
COLLISION_SYNC_1: FDR
port map
(
Q => phy_col_d1, --[out]
C => Clk, --[in]
D => Phy_col, --[in]
R => Rst --[in]
);
COLLISION_SYNC_2: FDR
port map
(
Q => phy_col_d2, --[out]
C => Clk, --[in]
D => phy_col_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- Registerign PHY CRs
----------------------------------------------------------------------------
C_SENSE_SYNC_1: FDR
port map
(
Q => phy_crs_d1, --[out]
C => Clk, --[in]
D => Phy_crs, --[in]
R => Rst --[in]
);
C_SENSE_SYNC_2: FDR
port map
(
Q => phy_crs_d2, --[out]
C => Clk, --[in]
D => phy_crs_d1, --[in]
R => Rst --[in]
);
----------------------------------------------------------------------------
-- MAC Address RAM
----------------------------------------------------------------------------
NODEMACADDRRAMI: entity axi_ethernetlite_v3_0.MacAddrRAM
generic map
(
MACAddr => NODE_MAC
)
port map
(
addr => mac_addr_ram_addr,
dout => mac_addr_ram_data,
din => Tx_DPM_rd_data,
we => mac_addr_ram_we,
Clk => Clk
);
mac_addr_ram_addr <= mac_addr_ram_addr_rd when mac_addr_ram_we = '0' else
mac_addr_ram_addr_wr;
----------------------------------------------------------------------------
-- RX Address Counter for the RxBuffer
----------------------------------------------------------------------------
RXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_start = '1' then
rxbuffer_addr <= (others => '0');
elsif rx_addr_en = '1' then
rxbuffer_addr <= rxbuffer_addr + 1;
end if;
end if;
end process RXADDRCNT;
Rx_DPM_adr <= rxbuffer_addr;
----------------------------------------------------------------------------
-- TX Address Counter for the TxBuffer (To Read)
----------------------------------------------------------------------------
TXADDRCNT: process (Clk)
begin
if Clk'event and Clk = '1' then
if Rst = '1' then
txbuffer_addr <= (others => '0');
elsif tx_start = '1' then
txbuffer_addr <= (others => '0');
elsif tx_addr_en = '1' then
txbuffer_addr <= txbuffer_addr + 1;
end if;
end if;
end process TXADDRCNT;
Tx_DPM_adr <= txbuffer_addr;
----------------------------------------------------------------------------
-- CDC module for syncing phy_tx_clk in PHY_tx_clk domain
----------------------------------------------------------------------------
CDC_TX_CLK: entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_FLOP_INPUT => 0,
C_VECTOR_WIDTH => 1,
C_MTBF_STAGES => 4
)
port map(
prmry_aclk => '1',
prmry_resetn => '1',
prmry_in => Phy_tx_clk,
prmry_ack => open,
scndry_out => Phy_tx_clk_axi_d,
scndry_aclk => Clk,
scndry_resetn => '1',
prmry_vect_in => (OTHERS => '0'),
scndry_vect_out => open
);
----------------------------------------------------------------------------
-- INT_tx_clk_sync_PROCESS
----------------------------------------------------------------------------
-- This process syncronizes the tx Clk and generates an enable pulse
----------------------------------------------------------------------------
INT_TX_CLK_SYNC_PROCESS : process (Clk)
begin --
if (Clk'event and Clk = '1') then
if (Rst = RESET_ACTIVE) then
tx_clk_reg_d1 <= '0';
tx_clk_reg_d2 <= '0';
tx_clk_reg_d3 <= '0';
else
tx_clk_reg_d1 <= Phy_tx_clk_axi_d;
tx_clk_reg_d2 <= tx_clk_reg_d1;
tx_clk_reg_d3 <= tx_clk_reg_d2;
end if;
end if;
end process INT_TX_CLK_SYNC_PROCESS;
txClkEn <= '1' when tx_clk_reg_d2 = '1' and tx_clk_reg_d3 = '0' else
'0';
----------------------------------------------------------------------------
-- ADJP
----------------------------------------------------------------------------
-- Adjust the packet length is it is less than minimum
----------------------------------------------------------------------------
ADJP : process(mac_tx_frame_length)
begin
if mac_tx_frame_length > MinimumPacketLength then
nibbleLength <= mac_tx_frame_length(5 to 15) & '0';
en_pad <= '0';
else
nibbleLength <= MinimumPacketLength(5 to 15) & '0';
en_pad <= '1';
end if;
end process ADJP;
nibbleLength_orig <= mac_tx_frame_length(5 to 15) & '0';
mac_tx_frame_length <= Tx_packet_length;
----------------------------------------------------------------------------
end imp;
|
----------------------------------------------------------------------------------
-- Project Name: Frecuency Counter
-- Target Devices: Spartan 3
-- Engineers: Ángel Larrañaga Muro
-- Nicolás Jurado Jiménez
-- Gonzalo Matarrubia Gonzalez
-- License: All files included in this proyect are licensed under a Creative Commons Attribution-ShareAlike 4.0 International License
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY CountEventsUP IS
END CountEventsUP;
ARCHITECTURE behavior OF CountEventsUP IS
COMPONENT CountEvents
PORT(
Entrada : IN std_logic;
Reset : IN std_logic;
Output : OUT std_logic_vector(0 to 31)
);
END COMPONENT;
--Inputs
signal Entrada : std_logic := '0';
signal Reset : std_logic := '0';
--Outputs
signal Output : std_logic_vector(0 to 31);
constant Entrada_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: CountEvents PORT MAP (
Entrada => Entrada,
Reset => Reset,
Output => Output
);
-- Clock process definitions
Entrada_process :process
begin
Entrada <= '0';
wait for Entrada_period/2;
Entrada <= '1';
wait for Entrada_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
Reset <= '1';
wait for 100 ns;
Reset <= '0';
wait for Entrada_period*10;
-- insert stimulus here
wait;
end process;
END;
|
-- This file is part of easyFPGA.
-- Copyright 2013-2015 os-cillation GmbH
--
-- easyFPGA is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- easyFPGA is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with easyFPGA. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
-- R E C E I V E F R A M E B U F F E R (receive_frame_buffer.vhd)
--
-- Statemachine using two-process-pattern
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use work.constants.all;
-------------------------------------------------------------------------------
ENTITY receive_frame_buffer is
-------------------------------------------------------------------------------
generic (
WIDTH : natural := FIFO_WIDTH -- width of a data word
);
port (
clk_i : in std_logic; -- clock input
clear_i : in std_logic; -- synchronous clear input
store_i : in std_logic; -- asserted when valid word is applied
frame_complete_o : out std_logic; -- frame complete detected
word_i : in std_logic_vector(WIDTH - 1 downto 0); -- word input
frame_o : out std_logic_vector((WIDTH * PROTO_WC_RX_MAX) - 1 downto 0); -- frame output
busy_o : out std_logic -- asserted when forwarding to frame controller
);
end receive_frame_buffer;
-------------------------------------------------------------------------------
ARCHITECTURE two_proc of receive_frame_buffer is
-------------------------------------------------------------------------------
-- frame buffer type
type buffer_type is array (0 to PROTO_WC_RX_MAX - 1) of std_logic_vector(WIDTH -1 downto 0);
-- state type
type state_type is (
init,
-- states for reception of frames that fit into the buffer
receive,
increment,
clear,
-- for partial reception (mwr/awr)
receive_part,
increment_part,
clear_part
);
-- register type (includes frame buffer and state)
type reg_type is record
state : state_type;
frame : buffer_type;
buffer_ptr : integer range 0 to PROTO_WC_RX_MAX; -- position of the next word
-- if PROTO_WC_RX_MAX, buffer is full
receive_cnt : integer range 0 to PROTO_WC_MAX; -- counts the number of received bytes
length : integer range 0 to PROTO_WC_MAX; -- number of bytes to receive in total
end record;
signal reg_out, reg_in : reg_type;
signal frame_complete_s : std_logic;
-------------------------------------------------------------------------------
begin -- architecture
-------------------------------------------------------------------------------
-------------------------------------------------------------------------------
-- STRUCTURAL
-------------------------------------------------------------------------------
-- complete and busy output
frame_complete_o <= frame_complete_s;
busy_o <= frame_complete_s or clear_i;
-------------------------------------------------------------------------------
COMBINATIONAL : process(reg_out, clear_i, store_i, word_i)
-------------------------------------------------------------------------------
variable tmp : reg_type;
begin
-- default assignments
tmp := reg_out;
-- state machine
case tmp.state is
----------------------------------------
when init =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- init register
tmp.buffer_ptr := 0;
tmp.state := receive;
tmp.receive_cnt := 0;
tmp.length := 0;
----------------------------------------
when receive =>
----------------------------------------
-- output frame
for word_index in 0 to (PROTO_WC_RX_MAX - 1) loop
frame_o(((word_index * WIDTH) + (WIDTH - 1)) downto word_index * WIDTH) <= tmp.frame(word_index);
end loop;
-- if the opcode is received
if (tmp.buffer_ptr >= 1) then
-- assert frame_complete depending on opcode.
case tmp.frame(0) is
when MCU_SEL_OPC =>
if (tmp.buffer_ptr = MCU_SEL_LEN) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when SOC_INT_EN_OPC =>
if (tmp.buffer_ptr = SOC_INT_EN_LEN) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when REGISTER_WR_OPC =>
if (tmp.buffer_ptr = REGISTER_WR_LEN ) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when REGISTER_RD_OPC =>
if (tmp.buffer_ptr = REGISTER_RD_LEN ) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when REGISTER_MRD_OPC =>
if (tmp.buffer_ptr = REGISTER_MRD_LEN ) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when REGISTER_ARD_OPC =>
if (tmp.buffer_ptr = REGISTER_ARD_LEN ) then
frame_complete_s <= '1';
else
frame_complete_s <= '0';
end if;
when DETECT_OPC =>
frame_complete_s <= '1';
-- OPC unknown
when others =>
frame_complete_s <= '1';
end case;
-- if pointer is zero
else
frame_complete_s <= '0';
frame_o <= (others => '-');
end if;
-- next state
if (clear_i = '1') then
tmp.state := clear;
-- enter increment_part when storing mwr/awr opcode
elsif (tmp.buffer_ptr = 0 and store_i = '1' and (word_i = REGISTER_MWR_OPC or word_i = REGISTER_AWR_OPC)) then
tmp.state := increment_part;
tmp.frame(0) := word_i;
-- enter increment when storing other opcode
elsif (store_i = '1') then
tmp.frame(tmp.buffer_ptr) := word_i;
tmp.state := increment;
end if;
----------------------------------------
when increment =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- increment pointer and counter
tmp.buffer_ptr := tmp.buffer_ptr + 1;
tmp.receive_cnt := tmp.receive_cnt + 1;
-- next state
tmp.state := receive;
----------------------------------------
when clear =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- clear
tmp.buffer_ptr := 0;
tmp.receive_cnt := 0;
-- next state
if (clear_i = '0') then
tmp.state := receive;
else
tmp.state := clear;
end if;
----------------------------------------
when receive_part =>
----------------------------------------
-- output frame
for word_index in 0 to (PROTO_WC_RX_MAX - 1) loop
frame_o(((word_index * WIDTH) + (WIDTH - 1)) downto word_index * WIDTH) <= tmp.frame(word_index);
end loop;
-- complete when full
if (tmp.buffer_ptr = PROTO_WC_RX_MAX) then
frame_complete_s <= '1';
-- complete when completely received
elsif (tmp.receive_cnt = tmp.length) then
frame_complete_s <= '1';
-- incomplete
else
frame_complete_s <= '0';
end if;
-- store length (header and parity inclusive) when 5 bytes received
if (tmp.receive_cnt = 5) then
-- MWR length
if (tmp.frame(0) = REGISTER_MWR_OPC) then
tmp.length := to_integer(unsigned(tmp.frame(4))) + REGISTER_MWR_LEN;
-- AWR length
elsif (tmp.frame(0) = REGISTER_AWR_OPC) then
tmp.length := to_integer(unsigned(tmp.frame(4))) + REGISTER_AWR_LEN;
end if;
end if;
-- next state
-- if fully received enter clear to return to receive state
if (clear_i = '1' and tmp.receive_cnt = tmp.length) then
tmp.state := clear;
-- if clear enter clear_part to prepare for next partial buffering
elsif (clear_i = '1') then
tmp.state := clear_part;
-- store and enter increment_part
elsif (store_i = '1') then
tmp.frame(tmp.buffer_ptr) := word_i;
tmp.state := increment_part;
end if;
----------------------------------------
when increment_part =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- increment pointer and counter
tmp.buffer_ptr := tmp.buffer_ptr + 1;
tmp.receive_cnt := tmp.receive_cnt + 1;
-- next state
tmp.state := receive_part;
----------------------------------------
when clear_part =>
----------------------------------------
-- outputs
frame_complete_s <= '0';
frame_o <= (others => '-');
-- clear
tmp.buffer_ptr := 0;
-- next state
if (clear_i = '0') then
tmp.state := receive_part;
else
tmp.state := clear_part;
end if;
end case;
-- drive register inputs
reg_in <= tmp;
end process COMBINATIONAL;
-------------------------------------------------------------------------------
REGISTERS : process(clk_i) -- sequential process
-------------------------------------------------------------------------------
begin
if rising_edge(clk_i) then
reg_out <= reg_in;
end if;
end process REGISTERS;
end two_proc;
|
-- Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2017.2 (win64) Build 1909853 Thu Jun 15 18:39:09 MDT 2017
-- Date : Tue Sep 19 00:31:33 2017
-- Host : DarkCube running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub
-- c:/Users/markb/Source/Repos/FPGA_Sandbox/RecComp/Lab1/embedded_lab_1/embedded_lab_1.srcs/sources_1/bd/zynq_design_1/ip/zynq_design_1_auto_pc_1/zynq_design_1_auto_pc_1_stub.vhdl
-- Design : zynq_design_1_auto_pc_1
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity zynq_design_1_auto_pc_1 is
Port (
aclk : in STD_LOGIC;
aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 11 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
end zynq_design_1_auto_pc_1;
architecture stub of zynq_design_1_auto_pc_1 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "aclk,aresetn,s_axi_awid[11:0],s_axi_awaddr[31:0],s_axi_awlen[3:0],s_axi_awsize[2:0],s_axi_awburst[1:0],s_axi_awlock[1:0],s_axi_awcache[3:0],s_axi_awprot[2:0],s_axi_awqos[3:0],s_axi_awvalid,s_axi_awready,s_axi_wid[11:0],s_axi_wdata[31:0],s_axi_wstrb[3:0],s_axi_wlast,s_axi_wvalid,s_axi_wready,s_axi_bid[11:0],s_axi_bresp[1:0],s_axi_bvalid,s_axi_bready,s_axi_arid[11:0],s_axi_araddr[31:0],s_axi_arlen[3:0],s_axi_arsize[2:0],s_axi_arburst[1:0],s_axi_arlock[1:0],s_axi_arcache[3:0],s_axi_arprot[2:0],s_axi_arqos[3:0],s_axi_arvalid,s_axi_arready,s_axi_rid[11:0],s_axi_rdata[31:0],s_axi_rresp[1:0],s_axi_rlast,s_axi_rvalid,s_axi_rready,m_axi_awid[11:0],m_axi_awaddr[31:0],m_axi_awlen[7:0],m_axi_awsize[2:0],m_axi_awburst[1:0],m_axi_awlock[0:0],m_axi_awcache[3:0],m_axi_awprot[2:0],m_axi_awregion[3:0],m_axi_awqos[3:0],m_axi_awvalid,m_axi_awready,m_axi_wdata[31:0],m_axi_wstrb[3:0],m_axi_wlast,m_axi_wvalid,m_axi_wready,m_axi_bid[11:0],m_axi_bresp[1:0],m_axi_bvalid,m_axi_bready,m_axi_arid[11:0],m_axi_araddr[31:0],m_axi_arlen[7:0],m_axi_arsize[2:0],m_axi_arburst[1:0],m_axi_arlock[0:0],m_axi_arcache[3:0],m_axi_arprot[2:0],m_axi_arregion[3:0],m_axi_arqos[3:0],m_axi_arvalid,m_axi_arready,m_axi_rid[11:0],m_axi_rdata[31:0],m_axi_rresp[1:0],m_axi_rlast,m_axi_rvalid,m_axi_rready";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of stub : architecture is "axi_protocol_converter_v2_1_13_axi_protocol_converter,Vivado 2017.2";
begin
end;
|
architecture rtl of fifo is
begin
my_signal <= '1' when input = "00" else
my_signal2 or my_sig3 when input = "01" else
my_sig4 and my_sig5 when input = "10" else
'0';
my_signal <= '1' when input = "0000" else
my_signal2 or my_sig3 when input = "0100" and input = "1100" else
my_sig4 when input = "0010" else
'0';
my_signal <= '1' when input(1 downto 0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
'0' when input(3 downto 0) = "0010" else
'Z';
my_signal <= '1' when a = "0000" and func1(345) or
b = "1000" and func2(567) and
c = "00" else
sig1 when a = "1000" and func2(560) and
b = "0010" else
'0';
my_signal <= '1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
-- Testing no code after assignment
my_signal <=
'1' when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
my_signal <=
(others => '0') when input(1 downto
0) = "00" and func1(func2(G_VALUE1),
to_integer(cons1(37 downto 0))) = 256 else
my_signal when input(3 downto 0) = "0010" else
'Z';
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
entity MemoryController is
generic (
clock_frec : integer := 50 -- MHz
);
port (
clock : in std_logic; -- 100MHz/50MHz
reset : in std_logic;
address_in : in std_logic_vector(22 downto 0); -- dirección RAM
go_in : in std_logic; -- if='1' starts the operation
write_in : in std_logic; -- if='0' => read; if='1' => write
data_in : in std_logic_vector(15 downto 0); -- datos a escribir
data_out : out std_logic_vector(15 downto 0); -- datos leídos
read_ready_out : out std_logic; -- if='1' valid data_out
busy : out std_logic; -- if='1' RAM is busy (go_in won't take effect)
-- Controladores de la memoria (externa):
clock_out : out std_logic;
ADDRESS : out std_logic_vector(22 downto 0);
ADV : out std_logic;
CRE : out std_logic;
CE : out std_logic;
OE : out std_logic;
WE : out std_logic;
LB : out std_logic;
UB : out std_logic;
DATA : inout std_logic_vector(15 downto 0)
);
end;
architecture Behavioral of MemoryController is
type state_t is (INIT, IDLE, WRITING, READING);
signal state : state_t := INIT;
constant clock_period_ns : integer := (1000/clock_frec); -- nanoseconds (50MHz => 20ns, 100MHz => 10ns)
constant init_period_us : integer := 151; -- microseconds (151 us)
constant init_counter : integer := (init_period_us * 1000 / clock_period_ns); -- 151 microseconds
constant timing_counter : integer := (80 / clock_period_ns); -- 80 nanoseconds (70ns)
signal counter : integer range 0 to init_counter := 0;
-- Controls the input data to write to the RAM
signal writing_out : STD_LOGIC := '0';
-- signal current_data_out, next_data_out : std_logic_vector(15 downto 0):= (others => '0');
-- Agregado:
signal address_aux : std_logic_vector(22 downto 0) := (others => '0');
signal data_in_aux : std_logic_vector(15 downto 0) := (others => '0');
begin
ADDRESS <= address_aux;
address_process: process (clock, reset)
begin
if reset = '1' then
address_aux <= (others => '0');
data_in_aux <= (others => '0');
elsif rising_edge(clock) then
if go_in = '1' then
address_aux <= address_in;
data_in_aux <= data_in;
end if;
end if;
end process;
clock_out <= '0'; -- always '0' since this controller operates in asynchronous mode
CRE <= '0'; -- always '0' because this controller uses the default configuration
-- DATA <= data_in when writing_out='1' else (others => 'Z');
DATA <= data_in_aux when writing_out='1' else (others => 'Z');
-- Señales de control
busy <= '1' when (state = WRITING OR state = READING OR state = INIT) else '0';
ADV <= '1' when state = INIT else '0';
CE <= '0' when (state = WRITING OR state = READING) else '1';
LB <= '0' when (state = WRITING OR state = READING) else '1';
UB <= '0' when (state = WRITING OR state = READING) else '1';
WE <= '0' when state = WRITING else '1';
OE <= '0' when state = READING else '1';
writing_out <= '1' when state = WRITING else '0';
-- FSM process
FSM: process (clock, reset)
begin
-- RESET
if reset = '1' then
state <= INIT;
elsif rising_edge(clock) then
case state is
when INIT =>
read_ready_out <= '0';
data_out <= (others => '0');
if (counter >= init_counter) then
counter <= 0;
state <= IDLE;
else
counter <= counter + 1;
end if;
when IDLE =>
read_ready_out <= '0';
data_out <= (others => '0');
if go_in = '1' then
if write_in = '1' then
state <= WRITING;
else
state <= READING;
end if;
end if;
when WRITING =>
if (counter >= timing_counter - 1) then
counter <= 0;
state <= IDLE;
else
counter <= counter + 1;
end if;
when READING =>
-- En el último ciclo de la cuenta
if (counter = timing_counter - 2) then
data_out <= DATA;
counter <= counter + 1;
-- Adelanto el read_ready_out para leer en el 5to flanco
read_ready_out <= '1';
-- Cuando termina de contar
elsif (counter >= timing_counter - 1) then
counter <= 0;
state <= IDLE;
data_out <= DATA;
--read_ready_out <= '1';
read_ready_out <= '0';
else
counter <= counter + 1;
end if;
when others =>
state <= IDLE;
end case;
end if;
end process; -- FSM
end;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
-- Create Date: 16:49:16 09/21/2017
-- VHDL Test Bench Created by ISE for module: registro
-- Dependencies:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY registro_tb IS
END registro_tb;
ARCHITECTURE behavior OF registro_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT registro
PORT(
reset : IN std_logic;
data_in : IN std_logic_vector(31 downto 0);
clk : IN std_logic;
data_out : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal reset : std_logic := '0';
signal data_in : std_logic_vector(31 downto 0) := (others => '0');
signal clk : std_logic := '0';
--Outputs
signal data_out : std_logic_vector(31 downto 0);
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: registro PORT MAP (
reset => reset,
data_in => data_in,
clk => clk,
data_out => data_out
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
data_in <= "00000000000000001110000000000111";
wait for clk_period*10;
reset <= '1';
wait for clk_period*10;
reset <= '0';
data_in <= "00000000000111101110000000000111";
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
-- Engineer: Cesar Avalos B
-- Create Date: 01/28/2018 07:53:02 PM
-- Module Name: MMU_stub - Behavioral
-- Description: Full flegded MMU to feed instructions and store data, supports SV39
--
-- Additional Comments: Mk. VIII
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library config;
use work.config.all;
use IEEE.NUMERIC_STD.ALL;
library unisim;
use unisim.VCOMPONENTS.ALL;
entity MMU is
Port(
clk: in std_logic; -- 100 Mhz Clock
rst: in std_logic; -- Active high reset
addr_in: in doubleword; -- 64-bits address in
data_in: in doubleword; -- 64-bits data in
satp: in doubleword; -- Control register
mode: in std_logic_vector(1 downto 0); -- Current mode (Machine, Supervisor, Etc)
store: in std_logic; -- High to toggle store
load: in std_logic; -- High to toggle load
busy: out std_logic := '0'; -- High when busy
ready_instr: in std_logic; -- Can fetch next instruction (might be redundant)
addr_instr: in doubleword; -- Instruction Address (AKA PC)
alignment: in std_logic_vector(3 downto 0); --Mask
data_out: out doubleword; -- 64-Bits data out
instr_out: out doubleword; -- 64-Bits instruction out
error: out std_logic_vector(5 downto 0);-- Error
page_fault: out std_logic; -- High when page fault
-- LEDS out
LED: out std_logic_vector(15 downto 0);
-- UART out
UART_TXD: out std_logic;
UART_RXD: in std_logic;
-- DDR2 Signals
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0);
-- Debug Signals
-- This pragma crap is the equivalent of ifdef in C
--pragma synthesis_off
fkuck_vivado_so_much: out std_logic_vector(5 downto 0);
s_internal_address_out: out doubleword;
--pragma synthesis_on
-- ROM SPI signals
sck: out std_logic; -- Special gated sck for the ROM STARTUPE2 generic
cs_n: out STD_LOGIC;
dq: inout std_logic_vector(3 downto 0));
end MMU;
architecture Behavioral of MMU is
-- Components
component ram_controller is
Port ( clk_200,clk_100 : in STD_LOGIC;
rst : in STD_LOGIC;
data_in : in STD_LOGIC_VECTOR(15 DOWNTO 0);
data_out : out STD_LOGIC_VECTOR(15 DOWNTO 0);
write, read: in STD_LOGIC;
done: out STD_LOGIC;
contr_addr_in : in STD_LOGIC_VECTOR(26 DOWNTO 0);
ddr2_addr : out STD_LOGIC_VECTOR (12 downto 0);
ddr2_ba : out STD_LOGIC_VECTOR (2 downto 0);
ddr2_ras_n : out STD_LOGIC;
ddr2_cas_n : out STD_LOGIC;
ddr2_we_n : out STD_LOGIC;
ddr2_ck_p : out std_logic_vector(0 downto 0);
ddr2_ck_n : out std_logic_vector(0 downto 0);
ddr2_cke : out std_logic_vector(0 downto 0);
ddr2_cs_n : out std_logic_vector(0 downto 0);
ddr2_dm : out STD_LOGIC_VECTOR (1 downto 0);
ddr2_odt : out std_logic_vector(0 downto 0);
ddr2_dq : inout STD_LOGIC_VECTOR (15 downto 0);
ddr2_dqs_p : inout STD_LOGIC_VECTOR (1 downto 0);
ddr2_dqs_n : inout STD_LOGIC_VECTOR (1 downto 0));
end component;
component ROM_controller_SPI is
Port (clk_25, rst, read: in STD_LOGIC;
si_i: out STD_LOGIC;
cs_n: out STD_LOGIC;
wp: out std_logic;
si_t: out std_logic;
wp_t: out std_logic;
address_in: in STD_LOGIC_VECTOR(23 downto 0);
qd: in STD_LOGIC_VECTOR(3 downto 0);
data_out: out STD_LOGIC_VECTOR(31 downto 0);
--pragma synthesis_off
counter: out integer;
--pragma synthesis_on
-- command_int, address_int, reg_one_int, reg_two_int: inout integer;
done: out STD_LOGIC
);
end component;
component clk_wiz_0
port(
clk_in1 : in std_logic;
clk_100MHz_o: out std_logic;
clk_200MHz_o: out std_logic;
clk_25MHz_o: out std_logic;
locked: out std_logic);
end component;
component UART_RX_CTRL is
port (UART_RX: in STD_LOGIC;
CLK: in STD_LOGIC;
DATA: out STD_LOGIC_VECTOR (7 downto 0);
READ_DATA: out STD_LOGIC;
RESET_READ: in STD_LOGIC
);
end component;
component UART_TX_CTRL is
port( SEND : in STD_LOGIC;
DATA : in STD_LOGIC_VECTOR (7 downto 0);
CLK : in STD_LOGIC;
READY : out STD_LOGIC;
UART_TX : out STD_LOGIC);
end component;
type instsmem is array(0 to 100) of doubleword;
signal instr_mem: instsmem := (0 => X"00000000480017b7", 1 => "0000000000000000000000000000000000000000000101111001011100010011", 2 => "0000000000000000000000000000000000000000101100000000010110010011", 3 => "0000000000000000000000000000000000000000101101110011000000100011", 4 => "0000000000000000000000000000000000000000101100000000010110010011", 5 => "0000000000000000000000000000000000000000101100000000010110010011", 6=> X"0000000005200513", others => (others => '0'));
-- SPI signals
signal io_flash_en: std_logic;
signal io_flash_write: std_logic;
signal io_quad_io: std_logic_vector(3 downto 0);
signal io_flash_addr: std_logic_vector(23 downto 0);
signal io_flash_data_in: std_logic_vector(31 downto 0);
signal io_flash_data_out: std_logic_vector(31 downto 0);
signal io_read_id: std_logic;
signal io_state_to_cpu: std_logic_vector(11 downto 0);
signal io_SI, io_WP, io_tri_si, io_tri_wp, io_cs, io_ready: std_logic;
signal io_srl, io_cr : std_logic_vector(7 downto 0);
signal io_sckgate: std_logic;
signal io_rst: std_logic;
type MMU_state is (idle, loading, storing, fetching, decode_state,page_walk,loading_ram_page_walk, loading_ram, loading_rom, done_uart_rx, done_uart_tx, storing_ram);
signal curr_state: MMU_state := idle;
signal next_state: MMU_state := idle;
--signal paused_state : MMU_state := idle; --Bit of a misnomer, this is
signal LED_reg: std_logic_vector(15 downto 0);
-- RAM signals
signal w_en: std_logic := '0';
signal RAM_en, ROM_en: std_logic := '0';
type RAM_state is (idle, read_low, read_low_mid, read_upper_mid, read_upper,write_low, write_low_mid, write_upper_mid, write_upper, done);
signal RAM_curr_state : RAM_state := idle;
signal RAM_next_state : RAM_state := idle;
signal RAM_masks: std_logic_vector(7 downto 0);
signal RAM_timeout_counter: integer:= 0;
signal RAM_data_in: std_logic_vector(15 downto 0);
signal RAM_data_out: std_logic_vector(15 downto 0);
signal RAM_address_in: std_logic_vector(26 downto 0);
signal s_RAM_data_out: doubleword := (others => '0'); -- The register holding the ram doubleword
signal ROM_done, RAM_done: std_logic := '0';
signal BRAM_toggle : std_logic_vector(1 downto 0) := "00";
--32 Bits acceses for ROM, either, too slow
type ROM_state is (idle, reading_lower, reading_higher, done);
signal ROM_curr_state : ROM_state := idle;
signal ROM_next_state : ROM_state := idle;
signal gated_clk: std_logic := '0';
signal s_ROM_data_out: doubleword := (others => '0'); --Register holding the rom doubleword
signal ROM_address_in : std_logic_vector(23 downto 0);
signal s_ROM_done: std_logic;
-- UART out data signal, for reading UART registers
signal UART_out: STD_LOGIC_VECTOR(7 downto 0);
signal UART_toggle : std_logic := '0';
signal SATP_mode: std_logic_vector(63 downto 0) := (others => '0');
signal SATP_PPN: std_logic_vector(63 downto 0) := (others => '0');
signal s_internal_data : std_logic_vector(63 downto 0);
signal s_internal_address: doubleword;
signal clk_100, clk_200, clk_25, locked: std_logic;
signal page_address_in: doubleword := (others => '0');
signal uart_data_in, uart_data_out: std_logic_vector(7 downto 0);
signal uart_data_available, uart_ready: std_logic;
signal uart_reset_read, uart_send: std_logic;
signal UART_data: doubleword;
signal m_timer: integer := 0;
Type PAGE_WALK_STATE is (idle,level_i_read, level_i_decode, done);
signal PAGE_WALK_next_state, PAGE_WALK_current_state: PAGE_WALK_STATE := idle;
signal s_page_walk,page_walk_request_read, page_walk_done: std_logic := '0';
signal page_walk_address_out, page_address_final: doubleword;
signal Intermitent_Address_In: doubleword;
signal addr_in_latch: doubleword;
-- Debugging
signal s_fuck_vivado_so_much: std_logic_vector(5 downto 0);
signal qd: std_logic_vector(3 downto 0);
signal gated_clock, clock_gate: std_logic;
begin
clk_wizard: clk_wiz_0
port map(
clk_in1 =>clk,
clk_100MHz_o => clk_100,
clk_200MHz_o => clk_200,
clk_25MHz_o => clk_25,
locked => locked
);
myRAMController: ram_controller port map
(
clk_200 => clk_200,
clk_100 => clk_100,
rst => rst,
data_in => RAM_data_in,
data_out => RAM_data_out,
done => RAM_done,
write => w_en,
read => RAM_en,
contr_addr_in => RAM_address_in,
ddr2_addr => ddr2_addr ,
ddr2_ba => ddr2_ba ,
ddr2_ras_n => ddr2_ras_n,
ddr2_cas_n => ddr2_cas_n,
ddr2_we_n => ddr2_we_n ,
ddr2_ck_p => ddr2_ck_p ,
ddr2_ck_n => ddr2_ck_n ,
ddr2_cke => ddr2_cke ,
ddr2_cs_n => ddr2_cs_n ,
ddr2_dm => ddr2_dm ,
ddr2_odt => ddr2_odt ,
ddr2_dq => ddr2_dq ,
ddr2_dqs_p => ddr2_dqs_p,
ddr2_dqs_n => ddr2_dqs_n
);
myROMController: ROM_controller_SPI port map(clk_25 => clk_25, rst => io_rst, read =>io_flash_en,
address_in => ROM_address_in, data_out => io_flash_data_out,
si_i =>io_SI, wp => io_WP, si_t => io_tri_si, wp_t => io_tri_wp,
cs_n => io_cs, qd => io_quad_io, done =>s_ROM_done);
myUARTTX: UART_TX_CTRL port map
(
SEND => uart_send,
DATA => uart_data_out,
CLK => CLK,
READY => uart_ready,
UART_TX => UART_TXD
);
myUARTRX: UART_RX_CTRL port map
(
UART_RX => UART_RXD,
CLK => CLK,
DATA => uart_data_in,
READ_DATA => uart_data_available,
RESET_READ => uart_reset_read
);
-- Advance state
STATE_ADVANCE: process(clk, rst, RAM_done, ROM_done)
begin
if('1' = rst) then
curr_state <= idle;
ROM_curr_state <= idle;
RAM_curr_state <= idle;
PAGE_WALK_current_state <= idle;
m_timer <= 0;
elsif(rising_edge(clk)) then
curr_state <= next_state;
RAM_curr_state <= RAM_next_state;
ROM_curr_state <= ROM_next_state;
PAGE_WALK_current_state <= PAGE_WALK_next_state;
m_timer <= m_timer + 1;
end if;
end process;
MMU_FSM: process(clk, rst, curr_state)
-- variable s_internal_address: doubleword := (others => '0'); --Realized Physical Address
variable paused_state: MMU_state; -- When we find the mode from SATP, we resume from the state saved here
begin
if rst = '1' then
instr_out <= (others => '0');
error <= (others => '0');
io_flash_write <= '0';
io_read_id <= '0';
next_state <= idle;
-- LED <= (others => '0');
busy <= '0';
BRAM_toggle <= "11";
elsif(rising_edge(clk)) then
busy <= '1';
next_state <= curr_state;
case curr_state is
-- Idling by like the leech you are MMU arent U
when idle =>
busy <= '1';
s_fuck_vivado_so_much <= "000000";
s_internal_address <= addr_in;
if(load = '1') then
next_state <= decode_state;
paused_state := loading;
elsif(store = '1') then
next_state <= decode_state;
paused_state := storing;
elsif(ready_instr = '1') then
next_state <= decode_state;
s_internal_address <= addr_instr;
paused_state := fetching;
else
busy <= '0';
end if;
-- Figure out what state are we at
when decode_state =>
s_fuck_vivado_so_much <= "000001";
case satp_mode(3 downto 0) is
when x"0" => -- No translation is assumed
next_state <= paused_state;
when others =>
next_state <= page_walk; --SV39 is assumed whenever anything else is written, no SV48 shenanigans
end case;
-- Walk the thing blue page walk line
when page_walk =>
s_fuck_vivado_so_much <= "000010";
s_page_walk <= '1'; --We enable the page walk process
if(page_walk_done = '1') then --Page walk is done
s_internal_address <= page_walk_address_out; -- We assign the newly discovered address
next_state <= paused_state; --Resume wherever we left off matey
elsif(page_walk_request_read = '1') then
RAM_en <= '1';
end if;
-- Intermediate fetching state, just check if there is any misalignment errors
when fetching =>
busy <= '1';
s_fuck_vivado_so_much <= "000011";
--Fetches have to be aligned
if(unsigned(s_internal_address) mod 8 > 0) then
error(4) <= '1'; -- Misaligned error, geback geback
next_state <= idle;
elsif( s_internal_address(31 downto 16) = x"0000" ) then
next_state <= idle;
instr_out <= instr_mem(to_integer(unsigned(addr_instr))/8);
else
next_state <= loading; --Loading instructions from elsewhere
end if;
-- Loading states
when loading =>
s_fuck_vivado_so_much <= "000100";
if(s_internal_address(31 downto 16) = x"0000" ) then --BRAM
next_state <= idle; --Instruction already goes out here, so no need to do anything,
-- We do this to preserve the instr_out port, even though it's really not necesary.
elsif(s_internal_address(31 downto 16) = x"9801") then --UART Registers
next_state <= idle; -- By default go to idle
busy <= '0';
case s_internal_address(3 downto 0) is
when X"0" => UART_data(7 downto 0) <= uart_data_in;
when X"1" => UART_data(0) <= uart_data_available;
when X"2" => UART_data(0) <= uart_reset_read;
when X"3" => UART_data(7 downto 0) <= uart_data_out;
when X"4" => UART_data(0) <= uart_ready;
when X"5" => UART_data(0) <= uart_send;
when others => UART_data <= (others => '0');
end case;
elsif(s_internal_address(31 downto 24) = x"98") then --LEDS Registers
LED_reg <= data_in(15 downto 0);
next_state <= idle;
elsif(s_internal_address(31 downto 24) = x"97") then --m_clock Register
next_state <= idle;
elsif(s_internal_address(31 downto 28) = x"9") then --ROM
next_state <= loading_ram;
elsif(s_internal_address(31 downto 28) = x"8") then --RAM
next_state <= loading_rom;
else
next_state <= idle;
end if;
-- Special load cases
when loading_rom =>
s_fuck_vivado_so_much <= "000101";
ROM_en <= '1';
if(ROM_done = '1') then
if(paused_state = fetching) then
instr_out <= zero_word & s_ROM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
when loading_ram =>
s_fuck_vivado_so_much <= "000110";
RAM_en <= '1';
if(ROM_done = '1') then
if(paused_state = fetching) then
instr_out <= zero_word & s_RAM_data_out(31 downto 0);
end if;
next_state <= idle;
end if;
-- Stores and such
when storing =>
s_fuck_vivado_so_much <= "000111";
next_state <= idle; -- By default go back
if(s_internal_address(31 downto 16) = x"9801") then --UART
case s_internal_address(3 downto 0) is
when X"0" => NULL; -- Nothing here really, why would you write to buffer in?
when X"1" => NULL; -- Why?
when X"2" => uart_reset_read <= '1';
next_state <= done_uart_rx;
when X"3" => uart_data_out <= data_in(7 downto 0);
when X"4" => NULL; -- No no no write
when X"5" => uart_send <= '1'; -- Assuming if you are writing is to send something
next_state <= done_uart_tx; -- After writing to this register we reset it automatically
when others => UART_data <= (others => '0');
end case;
elsif(s_internal_address(31 downto 28) = x"9") then --LEDS
LED_reg <= data_in(15 downto 0);
next_state <= idle;
elsif(s_internal_address(31 downto 24) = x"97") then --m_clock
next_state <= idle;
-- elsif(addr_in(31 downto 28) = x"9") then --ROM
-- next_state <= idle; --Can't write to ROM, I mean you could, but hwhy? Don't write to ROM
elsif(s_internal_address(31 downto 28) = x"8") then --RAM
next_state <= storing_ram;
end if;
-- Special stores section
when storing_ram =>
s_fuck_vivado_so_much <= "001000";
w_en <= '1';
if(RAM_done = '1') then
w_en <= '0';
next_state <= idle;
end if;
-- Special done states, to reset whatever needs to be reset
when done_uart_tx =>
uart_send <= '0'; --Reset UART send
next_state <= idle;
when done_uart_rx =>
uart_reset_read <= '0';
next_state <= idle;
when others =>
end case;
end if;
end process;
-- Walk the page
PAGE_WALK_FSM: process(clk, rst, s_page_walk)
variable level: Integer := 0;
begin
if(rst = '1') then
page_fault <= '0';
elsif(rising_edge(clk)) then
PAGE_WALK_next_state <= PAGE_WALK_current_state;
case PAGE_WALK_current_state is
when idle =>
if(s_page_walk = '1') then
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & addr_in(31 downto 22) & "00";--SATP PPN will give us the root page table location
PAGE_WALK_next_state <= level_i_read;
level := 0; --Start at level 0
end if;
when level_i_read =>
if(level < 3) then
page_walk_request_read <= '1';
if(RAM_done = '1') then
level := level + 1;
PAGE_WALK_next_state <= level_i_decode;
end if;
else
--Raise exception here
PAGE_WALK_next_state <= idle;
end if;
when level_i_decode =>
PAGE_WALK_next_state <= idle;
if(s_RAM_data_out(0) = '0') then --Invalid PTE Raise the roof
NULL;
elsif(s_RAM_data_out(1) = '0' and s_RAM_data_out(7) = '1') then -- Other exception
NULL;
elsif(s_RAM_data_out(1) = '1' or s_RAM_data_out(3) = '1') then --All gucci, this address is final
page_walk_next_state <= done;
page_address_final <= s_RAM_data_out(63 downto 13) & s_internal_address(12 downto 0);
page_walk_done <= '1';
else -- We still have to go deeper son
page_walk_next_state <= level_i_read;
page_address_in <= "00000000" & SATP_PPN(43 downto 0) & s_internal_address(31 downto 22) & "00";
end if;
when done =>
PAGE_WALK_next_state <= idle;
end case;
end if;
end process;
--busy <= '0' when curr_state = idle else '1';
-- Z high impedance
dq(0) <= 'Z' when io_tri_si = '1' else io_SI;
dq(1) <= 'Z';
dq(2) <= 'Z' when io_tri_wp = '1' else io_WP;
dq(3) <= 'Z';
qd(0) <= dq(0) when io_tri_si = '1' else 'Z';
qd(1) <= dq(1);
qd(2) <= dq(2) when io_tri_wp = '1' else 'Z';
qd(3) <= dq(3);
sck <= '0' when gated_clk = '1' else not(clk_25);
-- ROM SPI Clock Generation
ROM_CLK: process(clk_25, rst) begin
if(rst = '1') then
gated_clk <= '1';
elsif(rising_edge(clk_25)) then
if (io_cs = '0') then
gated_clk <= '0';
else
gated_clk <= '1';
end if;
end if;
end process;
-- ROM State Machine
-- To enable rom set ROM_en high
-- Will wait for 600 cycles and give back a 64 bit word
ROM_FSM: process(clk,rst, ROM_en)
variable ROM_counter: integer := 0;
begin
if(rst = '1') then
io_rst <= '1';
io_flash_en <= '0';
elsif(rising_edge(clk)) then
-- ROM_next_state <= ROM_curr_state;
case ROM_curr_state is
when idle =>
ROM_next_state <= idle;
io_flash_en <= '0';
ROM_counter := 0;
io_rst <= '1';
if(ROM_en = '1') then
ROM_done <= '0';
io_rst <= '0';
io_flash_addr <= s_internal_address(23 downto 0); --24 Bits in
io_flash_en <= '1'; --Enable the device
ROM_next_state <= reading_lower;
end if;
when reading_lower =>
ROM_next_state <= reading_lower;
ROM_counter := ROM_counter + 1; -- Wait a good amount of time to let the device react
if(ROM_counter > 300) then
s_ROM_data_out(31 downto 0) <= io_flash_data_out;
ROM_next_state <= reading_higher;
ROM_counter := 0;
end if;
when reading_higher =>
ROM_next_state <= reading_higher;
ROM_counter := ROM_counter + 1;
if(ROM_counter > 300) then
s_ROM_data_out(63 downto 32) <= io_flash_data_out;
ROM_next_state <= done;
end if;
when done =>
ROM_done <= '1';
ROM_next_state <= idle;
end case;
end if;
end process;
-- RAM State Machine
-- For reading from RAM, the ideal waiting time is of 230 ns
-- For writing into RAM, the ideal waiting time is of 270 ns
-- To make things easier we use 300 ns for both cases.
RAM_FSM: process(clk, RAM_en, w_en)
variable RAM_counter :integer := 0;
begin
if(rising_edge(clk)) then
if(RAM_curr_state /= idle) then
RAM_counter := RAM_counter + 1;
else
RAM_counter := 0;
end if;
RAM_next_state <= RAM_curr_state;
-- Forget about it
-- If for whatever reason we take long than
-- 1200 cycles, timeout and throw some error
if(RAM_timeout_counter >= 1200) then
RAM_next_state <= idle;
else
case RAM_curr_state is
-- Idle state, read before write
when idle =>
if(RAM_en = '1') then
RAM_next_state <= read_low;
elsif(w_en = '1') then
RAM_next_state <= write_low;
end if;
-- Load States
when read_low =>
if(RAM_counter > 30) then
s_RAM_data_out(15 downto 0) <= RAM_data_out;
RAM_next_state <= read_low_mid;
RAM_counter := 0;
end if;
when read_low_mid =>
if(RAM_counter > 30) then --Valid Data
s_RAM_data_out(31 downto 16) <= RAM_data_out;
RAM_next_state <= read_upper_mid;
RAM_counter := 0;
end if;
when read_upper_mid =>
if(RAM_counter > 30) then
s_RAM_data_out(47 downto 32) <= RAM_data_out;
RAM_next_state <= read_upper;
RAM_counter := 0;
end if;
when read_upper =>
if(RAM_counter > 30) then
s_RAM_data_out(63 downto 48) <= RAM_data_out;
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- Store States
when write_low =>
if(RAM_counter > 30) then
RAM_next_state <= write_low_mid;
RAM_counter := 0;
end if;
when write_low_mid =>
if(RAM_counter > 30) then --Valid Data
RAM_next_state <= write_upper_mid;
RAM_counter := 0;
end if;
when write_upper_mid =>
if(RAM_counter > 30) then
RAM_next_state <= write_upper;
RAM_counter := 0;
end if;
when write_upper =>
if(RAM_counter > 30) then
RAM_next_state <= done;
RAM_counter := 0;
end if;
-- We are done here
when others =>
RAM_next_state <= idle;
end case;
end if;
end if;
end process;
-- Latches the last obtained datas (dati, datum? datae?)
LAST_OBTAINED_DATA: process(clk,rst) begin
if(rst = '1') then
data_out <= (others => '0');
elsif(rising_edge(clk)) then
if(RAM_curr_state = done) then
data_out <= s_RAM_data_out;
elsif(ROM_curr_state = done) then
data_out <= s_ROM_data_out;
elsif(UART_toggle = '1') then
data_out(7 downto 0) <= UART_out;
data_out(63 downto 8) <= (others => '0');
end if;
end if;
end process;
-- Muxes for addresses and data
-- Intermitent address is internal RAM address, whenever we need to use the RAM
-- to access something else, we will make use of this intermitent_address_in signal
Intermitent_Address_In <= addr_in when s_page_walk = '0' else page_address_in;
s_internal_data <= data_in; --For the moment this is right
-- Might change this to sequential logic if needed, I don't think it necessary
RAM_address_in <= std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 0) when RAM_curr_state = idle or RAM_curr_state = read_low or RAM_curr_state = write_low else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 2) when RAM_curr_state = read_low_mid or RAM_curr_state = write_low_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 4) when RAM_curr_state = read_upper_mid or RAM_curr_state = write_upper_mid else
std_logic_vector(unsigned(Intermitent_Address_In(26 downto 0)) + 6) when RAM_curr_state = read_upper or RAM_curr_state = write_upper
else (others => '0');
RAM_data_in <= s_internal_data(15 downto 0 ) when RAM_curr_state = idle or RAM_curr_state = write_low else
s_internal_data(31 downto 16) when RAM_curr_state = write_low_mid else
s_internal_data(47 downto 32) when RAM_curr_state = write_upper_mid else
s_internal_data(63 downto 48) when RAM_curr_state = write_upper else
(others => '0');
-- The CSR telling us where the page table start
SATP_mode(3 downto 0) <= satp(63 downto 60);
SATP_PPN(43 downto 0) <= satp(43 downto 0);
LED <= LED_reg;
--pragma synthesis_off
fkuck_vivado_so_much <= s_fuck_vivado_so_much;
s_internal_address_out <= s_internal_address;
--pragma synthesis_on
end Behavioral; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 16:05:44 03/25/2016
-- Design Name:
-- Module Name: REG_CTL - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity REG_CTL is
Port ( CLK : in STD_LOGIC;
OPC : in STD_LOGIC_VECTOR (3 downto 0);
OPC4 : in STD_LOGIC_VECTOR (3 downto 0);
RD_EN : out STD_LOGIC;
WR_EN : out STD_LOGIC);
end REG_CTL;
architecture Behavioral of REG_CTL is
begin
process(CLK)
begin
if (rising_edge(CLK)) then
case OPC is
when "0000" => RD_EN <= '1';
when "0001" => RD_EN <= '1';
when "0010" => RD_EN <= '1';
when "0011" => RD_EN <= '1';
when "0100" => RD_EN <= '1';
when "0101" => RD_EN <= '1';
when "0110" => RD_EN <= '1';
when "0111" => RD_EN <= '1';
when "1000" => RD_EN <= '1';
when "1001" => RD_EN <= '1';
when others => RD_EN <= '0';
end case;
end if;
-- if (OPC = "1001") then
-- RD_EN <= '0';
-- else
-- RD_EN <= '1';
-- end if;
if (falling_edge(CLK)) then
case OPC4 is
when "0000" => WR_EN <= '1';
when "0001" => WR_EN <= '1';
when "0010" => WR_EN <= '1';
when "0011" => WR_EN <= '1';
when "0100" => WR_EN <= '1';
when "0101" => WR_EN <= '1';
when "0110" => WR_EN <= '1';
when "0111" => WR_EN <= '1';
when "1000" => WR_EN <= '1';
when "1010" => WR_EN <= '1';
when others => WR_EN <= '0';
end case;
-- if (OPC4 = "1010") then
-- WR_EN <= '0';
-- else
-- WR_EN <= '1';
-- end if;
end if;
end process;
end Behavioral;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.STD_LOGIC_ARITH.all;
USE IEEE.STD_LOGIC_UNSIGNED.all;
ENTITY SRAM_CONTROLLER IS
PORT(
--controls
clk : in std_logic;
rst : in std_logic;
--wishbone
bus_d : in std_logic_vector(15 downto 0);
bus_q : out std_logic_vector(15 downto 0);
bus_addr : in std_logic_vector(19 downto 0);
bus_rw : in std_logic;
bus_req : in std_logic;
bus_ack : out std_logic;
--sram
sram_dq : inout std_logic_vector(15 downto 0);
sram_addr : out std_logic_vector(19 downto 0);
sram_ce_n : out std_logic;
sram_oe_n : out std_logic;
sram_we_n : out std_logic;
sram_ub_n : out std_logic;
sram_lb_n : out std_logic
);
END SRAM_CONTROLLER;
ARCHITECTURE behavioral OF SRAM_CONTROLLER IS
type States is (idle, r0, r1, w0, w1);
signal current_state : States;
signal next_state : States;
signal sram_addr_r : std_logic_vector(19 downto 0) := (others => '0');
signal sram_dq_r : std_logic_vector(15 downto 0) := (others => '0');
signal sram_we_n_r : std_logic := '0';
signal sram_oe_n_r : std_logic := '0';
signal addr_r : std_logic_vector(19 downto 0);
signal dat_o_r : std_logic_vector(15 downto 0);
signal ack_o_r : std_logic;
signal dat_i_r : std_logic_vector(15 downto 0) := x"0000";
signal we_i_r : std_logic;
signal oe : std_logic;
signal stb_i_r : std_logic;
signal oe_r : std_logic;
begin
-- register command
process (clk, rst) begin
if(rst = '0' and rising_edge(clk)) then
if ((stb_i_r='1') and (current_state = w0 or current_state = r0)) then
stb_i_r <= '0';
elsif (bus_req = '1') then
addr_r <= bus_addr;
if(bus_rw = '1') then
dat_i_r <= bus_d;
end if;
we_i_r <= bus_rw;
stb_i_r <= bus_req;
end if;
end if;
end process;
process(clk,rst) begin
if (rst='1') then
current_state <= idle;
elsif(rising_edge(clk)) then
current_state <= next_state;
end if;
end process;
process (next_state, current_state, clk) begin
if(rst = '1') then
next_state <= idle;
else
case (current_state) is
when idle =>
if (stb_i_r='1' and we_i_r='1') then next_state <= w0;
elsif (stb_i_r='1' and we_i_r='0') then next_state <= r0;
else next_state <= Idle;
end if;
when w0 =>
next_state <= w1;
when w1 =>
next_state <= idle;
when r0 =>
next_state <= r1;
when r1 =>
next_state <= idle;
when others =>
next_state <= idle;
end case;
end if;
end process;
-- ack_o signal
process(clk, rst) begin
if (rst='1') then
ack_o_r <= '0';
elsif(rising_edge(clk)) then
if (current_state = idle) then
ack_o_r <= '0';
elsif (current_state = r1 or
current_state = w1) then
ack_o_r <= '1';
end if;
end if;
end process;
-- data
process(clk, rst) begin
if (rst='1') then
dat_o_r <= (others => '0');
sram_dq_r <= (others => '0');
oe_r <= '0';
elsif(rising_edge(clk)) then
if (current_state = W0) then
dat_o_r <= dat_i_r;
sram_dq_r <= dat_i_r;
oe_r <= '1';
elsif (current_state = W1) then
sram_dq_r <= dat_i_r;
dat_o_r <= dat_i_r;
oe_r <= '1';
elsif (current_state = R0) then
sram_dq_r <= (others => 'Z');
dat_o_r <= sram_dq;
oe_r <= '0';
elsif (current_state = R1) then
dat_o_r <= sram_dq;
sram_dq_r <= (others => 'Z');
oe_r <= '0';
else
sram_dq_r <= (others => 'Z');
oe_r <= '0';
end if;
end if;
end process;
-- address
process(clk) begin
if(rising_edge(clk)) then
if (current_state = W0 or current_state = R0) then
sram_addr_r <= addr_r;
end if;
end if;
end process;
-- commands
process(clk) begin
if(rising_edge(clk)) then
if (current_state = R0 or current_state = R1) then
sram_oe_n_r <= '0' ;
else
sram_oe_n_r <= '1';
end if;
if (current_state = W0 or current_state = W1)then
sram_we_n_r <= '0' ;
else
sram_we_n_r <= '1';
end if;
end if;
end process;
sram_addr <= sram_addr_r;
sram_we_n <= sram_we_n_r;
sram_oe_n <= sram_oe_n_r;
sram_ub_n <= '0';
sram_lb_n <= '0';
sram_ce_n <= '0';
sram_dq <= sram_dq_r when oe_r = '1' else
(others => 'Z');
bus_q <= dat_o_r ;
bus_ack <= ack_o_r;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc151.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p16n01i00151ent_a IS
port (signal input_1 : in bit;
signal input_2 : in bit_vector;
signal output : out bit);
END c04s03b02x02p16n01i00151ent_a;
ARCHITECTURE c04s03b02x02p16n01i00151arch_a OF c04s03b02x02p16n01i00151ent_a IS
BEGIN
END c04s03b02x02p16n01i00151arch_a;
ENTITY c04s03b02x02p16n01i00151ent IS
port (X: in BIT; Z: out BIT);
END c04s03b02x02p16n01i00151ent;
ARCHITECTURE c04s03b02x02p16n01i00151arch OF c04s03b02x02p16n01i00151ent IS
component input2
port (signal input_1 : in bit;
signal input_2 : in bit_vector;
signal output : out bit);
end component;
for G1 : input2 use entity work.ch04030202_p01601_02_ent_a(ch04030202_p01601_02_arch_a);
type bit_vector is array (positive range <>) of bit;
signal A1 : bit_vector;
BEGIN
G1: input2 port map (X, A1, Z); -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n01i00151 - The type of an actual should be same as that of the formal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n01i00151arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc151.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p16n01i00151ent_a IS
port (signal input_1 : in bit;
signal input_2 : in bit_vector;
signal output : out bit);
END c04s03b02x02p16n01i00151ent_a;
ARCHITECTURE c04s03b02x02p16n01i00151arch_a OF c04s03b02x02p16n01i00151ent_a IS
BEGIN
END c04s03b02x02p16n01i00151arch_a;
ENTITY c04s03b02x02p16n01i00151ent IS
port (X: in BIT; Z: out BIT);
END c04s03b02x02p16n01i00151ent;
ARCHITECTURE c04s03b02x02p16n01i00151arch OF c04s03b02x02p16n01i00151ent IS
component input2
port (signal input_1 : in bit;
signal input_2 : in bit_vector;
signal output : out bit);
end component;
for G1 : input2 use entity work.ch04030202_p01601_02_ent_a(ch04030202_p01601_02_arch_a);
type bit_vector is array (positive range <>) of bit;
signal A1 : bit_vector;
BEGIN
G1: input2 port map (X, A1, Z); -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n01i00151 - The type of an actual should be same as that of the formal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n01i00151arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc151.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p16n01i00151ent_a IS
port (signal input_1 : in bit;
signal input_2 : in bit_vector;
signal output : out bit);
END c04s03b02x02p16n01i00151ent_a;
ARCHITECTURE c04s03b02x02p16n01i00151arch_a OF c04s03b02x02p16n01i00151ent_a IS
BEGIN
END c04s03b02x02p16n01i00151arch_a;
ENTITY c04s03b02x02p16n01i00151ent IS
port (X: in BIT; Z: out BIT);
END c04s03b02x02p16n01i00151ent;
ARCHITECTURE c04s03b02x02p16n01i00151arch OF c04s03b02x02p16n01i00151ent IS
component input2
port (signal input_1 : in bit;
signal input_2 : in bit_vector;
signal output : out bit);
end component;
for G1 : input2 use entity work.ch04030202_p01601_02_ent_a(ch04030202_p01601_02_arch_a);
type bit_vector is array (positive range <>) of bit;
signal A1 : bit_vector;
BEGIN
G1: input2 port map (X, A1, Z); -- Failure_here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c04s03b02x02p16n01i00151 - The type of an actual should be same as that of the formal."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p16n01i00151arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1576.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01576ent IS
END c08s10b00x00p04n01i01576ent;
ARCHITECTURE c08s10b00x00p04n01i01576arch OF c08s10b00x00p04n01i01576ent IS
BEGIN
TESTING: PROCESS
-- Local variables
variable DIDIT : BOOLEAN;
variable CONSTONE : INTEGER := 1;
variable k : integer := 0;
BEGIN
-- The following loop should never fail its assertion.
DIDIT := FALSE;
for I in 0 to 10 loop
-- Make sure that the last statement of loop is executed.
if (I /= 0) then
if (DIDIT /= true) then
k := 1;
end if;
assert (DIDIT)
report "Did not execute statement after 'next when FALSE'";
DIDIT := FALSE;
end if;
-- This condition is NEVER true.
next when FALSE;
-- This statement should always be executed.
DIDIT := TRUE;
end loop;
-- The following loop should never fail its assertion.
DIDIT := FALSE;
for I in 0 to 10 loop
-- Make sure that the last statement of loop is executed.
if (I /= 0) then
if (DIDIT /= true) then
k := 1;
end if;
assert (DIDIT)
report "Did not execute statement after 'next when FALSE'";
DIDIT := FALSE;
end if;
-- This condition is NEVER true.
next when (CONSTONE /= 1);
-- This statement should always be executed.
DIDIT := TRUE;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p04n01i01576"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s10b00x00p04n01i01576 - If the condition in the next statement is FALSE, it should execute the sequence of statements enclosed within the loop condition with the next statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01576arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1576.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01576ent IS
END c08s10b00x00p04n01i01576ent;
ARCHITECTURE c08s10b00x00p04n01i01576arch OF c08s10b00x00p04n01i01576ent IS
BEGIN
TESTING: PROCESS
-- Local variables
variable DIDIT : BOOLEAN;
variable CONSTONE : INTEGER := 1;
variable k : integer := 0;
BEGIN
-- The following loop should never fail its assertion.
DIDIT := FALSE;
for I in 0 to 10 loop
-- Make sure that the last statement of loop is executed.
if (I /= 0) then
if (DIDIT /= true) then
k := 1;
end if;
assert (DIDIT)
report "Did not execute statement after 'next when FALSE'";
DIDIT := FALSE;
end if;
-- This condition is NEVER true.
next when FALSE;
-- This statement should always be executed.
DIDIT := TRUE;
end loop;
-- The following loop should never fail its assertion.
DIDIT := FALSE;
for I in 0 to 10 loop
-- Make sure that the last statement of loop is executed.
if (I /= 0) then
if (DIDIT /= true) then
k := 1;
end if;
assert (DIDIT)
report "Did not execute statement after 'next when FALSE'";
DIDIT := FALSE;
end if;
-- This condition is NEVER true.
next when (CONSTONE /= 1);
-- This statement should always be executed.
DIDIT := TRUE;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p04n01i01576"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s10b00x00p04n01i01576 - If the condition in the next statement is FALSE, it should execute the sequence of statements enclosed within the loop condition with the next statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01576arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1576.vhd,v 1.2 2001-10-26 16:29:42 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s10b00x00p04n01i01576ent IS
END c08s10b00x00p04n01i01576ent;
ARCHITECTURE c08s10b00x00p04n01i01576arch OF c08s10b00x00p04n01i01576ent IS
BEGIN
TESTING: PROCESS
-- Local variables
variable DIDIT : BOOLEAN;
variable CONSTONE : INTEGER := 1;
variable k : integer := 0;
BEGIN
-- The following loop should never fail its assertion.
DIDIT := FALSE;
for I in 0 to 10 loop
-- Make sure that the last statement of loop is executed.
if (I /= 0) then
if (DIDIT /= true) then
k := 1;
end if;
assert (DIDIT)
report "Did not execute statement after 'next when FALSE'";
DIDIT := FALSE;
end if;
-- This condition is NEVER true.
next when FALSE;
-- This statement should always be executed.
DIDIT := TRUE;
end loop;
-- The following loop should never fail its assertion.
DIDIT := FALSE;
for I in 0 to 10 loop
-- Make sure that the last statement of loop is executed.
if (I /= 0) then
if (DIDIT /= true) then
k := 1;
end if;
assert (DIDIT)
report "Did not execute statement after 'next when FALSE'";
DIDIT := FALSE;
end if;
-- This condition is NEVER true.
next when (CONSTONE /= 1);
-- This statement should always be executed.
DIDIT := TRUE;
end loop;
assert NOT( k=0 )
report "***PASSED TEST: c08s10b00x00p04n01i01576"
severity NOTE;
assert ( k=0 )
report "***FAILED TEST: c08s10b00x00p04n01i01576 - If the condition in the next statement is FALSE, it should execute the sequence of statements enclosed within the loop condition with the next statement."
severity ERROR;
wait;
END PROCESS TESTING;
END c08s10b00x00p04n01i01576arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc508.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n02i00508ent IS
END c03s02b02x00p06n02i00508ent;
ARCHITECTURE c03s02b02x00p06n02i00508arch OF c03s02b02x00p06n02i00508ent IS
type date is
record
day : integer range 1 to 31;
month : integer range 1 to 12;
-- -- Failure_here: duplicate record field declaration
day : integer range -6000 to 6000;
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n02i00508 -The identifiers of all elements of a record type must be distinct."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n02i00508arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc508.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n02i00508ent IS
END c03s02b02x00p06n02i00508ent;
ARCHITECTURE c03s02b02x00p06n02i00508arch OF c03s02b02x00p06n02i00508ent IS
type date is
record
day : integer range 1 to 31;
month : integer range 1 to 12;
-- -- Failure_here: duplicate record field declaration
day : integer range -6000 to 6000;
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n02i00508 -The identifiers of all elements of a record type must be distinct."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n02i00508arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc508.vhd,v 1.2 2001-10-26 16:30:26 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s02b02x00p06n02i00508ent IS
END c03s02b02x00p06n02i00508ent;
ARCHITECTURE c03s02b02x00p06n02i00508arch OF c03s02b02x00p06n02i00508ent IS
type date is
record
day : integer range 1 to 31;
month : integer range 1 to 12;
-- -- Failure_here: duplicate record field declaration
day : integer range -6000 to 6000;
end record;
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c03s02b02x00p06n02i00508 -The identifiers of all elements of a record type must be distinct."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b02x00p06n02i00508arch;
|
--! @author Trip Richert
library ieee;
use ieee.std_logic_1164.all;
package LinkedListPkg is
generic (
type elem_type
);
type LinkedList;
type LinkedListPtr is access LinkedList;
type LinkedList is record
elem : elem_type;
nextPtr : LinkedListPtr;
end record LinkedList;
end package LinkedListPkg;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package alu_types is
constant data_width : positive := 32;
end package alu_types;
package io_types is
constant data_width : positive := 32;
end package io_types;
entity controller_system is
end entity controller_system;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
use work.alu_types.all, work.io_types.all;
architecture structural of controller_system is
alias alu_data_width is work.alu_types.data_width;
alias io_data_width is work.io_types.data_width;
signal alu_in1, alu_in2,
alu_result : std_logic_vector(0 to alu_data_width - 1);
signal io_data : std_logic_vector(0 to io_data_width - 1);
-- . . .
-- not in book
-- following should not analyze: data_width not directly visible
-- constant test : positive := data_width;
-- end not in book
begin
-- . . .
end architecture structural;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package alu_types is
constant data_width : positive := 32;
end package alu_types;
package io_types is
constant data_width : positive := 32;
end package io_types;
entity controller_system is
end entity controller_system;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
use work.alu_types.all, work.io_types.all;
architecture structural of controller_system is
alias alu_data_width is work.alu_types.data_width;
alias io_data_width is work.io_types.data_width;
signal alu_in1, alu_in2,
alu_result : std_logic_vector(0 to alu_data_width - 1);
signal io_data : std_logic_vector(0 to io_data_width - 1);
-- . . .
-- not in book
-- following should not analyze: data_width not directly visible
-- constant test : positive := data_width;
-- end not in book
begin
-- . . .
end architecture structural;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book
package alu_types is
constant data_width : positive := 32;
end package alu_types;
package io_types is
constant data_width : positive := 32;
end package io_types;
entity controller_system is
end entity controller_system;
-- end not in book
library ieee; use ieee.std_logic_1164.all;
use work.alu_types.all, work.io_types.all;
architecture structural of controller_system is
alias alu_data_width is work.alu_types.data_width;
alias io_data_width is work.io_types.data_width;
signal alu_in1, alu_in2,
alu_result : std_logic_vector(0 to alu_data_width - 1);
signal io_data : std_logic_vector(0 to io_data_width - 1);
-- . . .
-- not in book
-- following should not analyze: data_width not directly visible
-- constant test : positive := data_width;
-- end not in book
begin
-- . . .
end architecture structural;
|
-------------------------------------------------------------------------------
-- Entity: fmc_chn
-- Author: Waj
-------------------------------------------------------------------------------
-- Description:
-- Floppy-Music Controller (1 channel)
-------------------------------------------------------------------------------
-- Total # of FFs: ... tbd ...
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mcu_pkg.all;
entity fmc_chn is
generic(N : natural := 0 -- channel number
);
port(rst : in std_logic;
clk : in std_logic;
-- control inputs
tick_dur : in std_logic; -- nominal period = 1 ms
tick_nco : in std_logic; -- nominal period = 1 us
chn_enb : in std_logic;
-- outputs to pins
fmc_enb : out std_logic;
fmc_dir : out std_logic;
fmc_stp : out std_logic
);
end fmc_chn;
architecture rtl of fmc_chn is
-- output signals
signal stp_cnt : unsigned(6 downto 0);
constant MAX_STP : unsigned(6 downto 0) := to_unsigned(79-1,7);
signal stp_reg : std_logic;
signal dir_reg : std_logic;
-- ROM and addressing
signal rom_addr : std_logic_vector(FMC_ROM_AW-1 downto 0);
signal rom_data : std_logic_vector(FMC_ROM_DW-1 downto 0);
signal duration_cnt : unsigned(FMC_DUR_WW-1 downto 0);
signal tone_duration : unsigned(FMC_DUR_WW-1 downto 0);
signal tone_number : unsigned(FMC_TON_WW-1 downto 0);
signal tone_end_evt : std_logic;
-- LUT: tone number ==> NCO seed
type t_nco_lut is array (2**FMC_TON_WW-1 downto 0) of natural;
constant nco_lut : t_nco_lut := (
0,0,0,0,0,0,0,0,0,0,0,0,0,0,7382,6968,6577,6207,5859,5530,5220,4927,4650,4389,4143,3910,3691,
3484,3288,3104,2930,2765,2610,2463,2325,2195,2071,1955,1845,1742,1644,1552,1465,1383,1305,1232,
1163,1097,1036,978,923,871,822,776,732,691,652,616,581,549,518,489,461,0);
-- NCO signals
signal seed : unsigned(12 downto 0); -- 13 bit seed
signal nco_reg : unsigned(23 downto 0); -- 24 bit NCO
begin
-----------------------------------------------------------------------------
-- output assignments
-----------------------------------------------------------------------------
fmc_stp <= stp_reg;
fmc_dir <= dir_reg;
-----------------------------------------------------------------------------
-- generate and register FMC outputs
-----------------------------------------------------------------------------
P_out: process(rst, clk)
begin
if rst = '1' then
fmc_enb <= '1';
stp_reg <= '0';
dir_reg <= '0';
stp_cnt <= (others => '0');
elsif rising_edge(clk) then
-- set enable active during times when any tone is played
if tone_number > 0 then
-- enable is low-active
fmc_enb <= '0';
else
fmc_enb <= '1';
end if;
-- connect step output to NCO output (MSB) to generate desired frequency
stp_reg <= std_logic(nco_reg(nco_reg'left));
-- toggle direction output after every 80 steps (rising edges on fmc_stp)
if stp_reg = '0' and std_logic(nco_reg(nco_reg'left)) = '1' then
-- rising edge on step output
if stp_cnt = MAX_STP then
stp_cnt <= (others => '0');
dir_reg <= not dir_reg;
else
stp_cnt <= stp_cnt + 1;
end if;
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- ROM addressing and tick counting
-----------------------------------------------------------------------------
P_read: process(rst, clk)
begin
if rst = '1' then
duration_cnt <= (others => '0');
tone_end_evt <= '0';
rom_addr <= (others => '0');
elsif rising_edge(clk) then
-- default assignment
tone_end_evt <= '0';
-- maintain tone duration counter
if tick_dur = '1' then
if duration_cnt = tone_duration-1 then
duration_cnt <= (others => '0');
tone_end_evt <= '1';
else
duration_cnt <= duration_cnt + 1;
end if;
end if;
-- maintain ROM address
if chn_enb = '0' or tone_duration = FMC_LAST_TONE then
-- restart playing from 1st tone
rom_addr <= (others => '0');
duration_cnt <= (others => '0');
elsif tone_end_evt = '1' then
rom_addr <= std_logic_vector(unsigned(rom_addr)+1);
end if;
end if;
end process;
-----------------------------------------------------------------------------
-- channel number dependent FMC ROM instance
-----------------------------------------------------------------------------
rom : entity work.fmc_rom
generic map(N => N)
port map (clk => clk,
addr => rom_addr,
data => rom_data
);
tone_duration <= unsigned(rom_data(FMC_DUR_WW+FMC_TON_WW-1 downto FMC_TON_WW));
tone_number <= unsigned(rom_data(FMC_TON_WW-1 downto 0));
-----------------------------------------------------------------------------
-- NCO (tone frequency generation)
-----------------------------------------------------------------------------
P_nco: process(rst, clk)
begin
if rst = '1' then
seed <= (others => '0');
nco_reg <= (others => '0');
elsif rising_edge(clk) then
seed <= to_unsigned(nco_lut(to_integer(tone_number)),13);
if tick_nco = '1' then
nco_reg <= nco_reg + seed;
end if;
end if;
end process;
end rtl;
|
-------------------------------------------------------------------------------
--! @file openfilter-rtl-ea.vhd
--
--! @brief OpenFILTER
--
--! @details This is the openFILTER used for blocking failures on the RMII lines.
--! Note: RxDv and RxDat have to be synchron to iClk
--! The following Conditions are checked:
--! * RxDV >163.64µsec HIGH -> invalid
--! * RxDV <0.64µsec LOW -> invalid
--! * RxDV 4x <5.12µsec HIGH -> invalid
--! * RxDV >5.12µsec HIGH -> valid
--! * iRxError HIGH -> invalid
--! If invalid deactivation of port, until RxDv and iRxError > 10.24µsec low
-------------------------------------------------------------------------------
--
-- (c) B&R Industrial Automation GmbH, 2014
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--! Common library
library libcommon;
--! Use common library global package
use libcommon.global.all;
--! Work library
library work;
--! use openmac package
use work.openmacPkg.all;
entity openfilter is
port (
--! Reset
iRst : in std_logic;
--! RMII Clock
iClk : in std_logic;
--! RMII receive path in
iRx : in tRmiiPath;
--! RMII receive path out
oRx : out tRmiiPath;
--! RMII transmit path in
iTx : in tRmiiPath;
--! RMII transmit path out
oTx : out tRmiiPath;
--! RMII receive error
iRxError : in std_logic
);
end entity openfilter;
architecture rtl of openfilter is
--! Filter FSM type
type tFiltState is (
fs_init,
fs_GAP2short, fs_GAPext, fs_GAPok,
fs_FRMnopre, fs_FRMpre2short, fs_FRMpreOk,
fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll
);
signal FiltState : tFiltState;
signal RxDel : tRmiiPathArray(3 downto 0);
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
begin
---------------------------------------------------------------------------
-- INPUT
---------------------------------------------------------------------------
RxDel(0) <= iRx;
BlockRxPort <= cActivated when (FiltState = fs_FRMnopre or
FiltState = fs_BlockAll or
LastFrameNOK = cActivated) else
cInactivated;
---------------------------------------------------------------------------
-- OUTPUT MUX
---------------------------------------------------------------------------
oRx <= cRmiiPathInit when BlockRxPort = cActivated else
RxDel(3) when FrameShift = cActivated else
RxDel(1);
oTx <= iTx;
doFsm : process(iRst, iClk)
variable RstStCnt : std_logic;
begin
if iRst = cActivated then
StCnt <= (others => cInactivated);
FiltState <= fs_init;
FrameShift <= cInactivated;
RxDel(3 downto 1) <= (others => cRmiiPathInit);
LastFrameNOK <= cInactivated;
elsif rising_edge(iClk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := cInactivated;
case FiltState is
---------------------------------------------------------------
-- INIT
---------------------------------------------------------------
when fs_init =>
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
---------------------------------------------------------------
-- GAP 2 SHORT
---------------------------------------------------------------
when fs_GAP2short =>
FrameShift <= cInactivated;
if StCnt(4) = cActivated then
-- 360ns
FiltState <= fs_GAPext;
end if;
if RxDel(0).enable = cActivated then
-- Gap < 360 ns -> too short -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- GAP EXTend
---------------------------------------------------------------
when fs_GAPext =>
if StCnt(5 downto 0) = "101110" then
FiltState <= fs_GAPok;
end if;
if RxDel(0).enable = cActivated then
-- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := cActivated;
FrameShift <= cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- GAP OK
---------------------------------------------------------------
when fs_GAPok =>
if RxDel(0).enable = cActivated then
RstStCnt := cActivated;
if RxDel(0).data = "01" then
-- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
FiltState <= fs_FRMpre2short;
else
-- GAP > 960ns -> OK -> Start Frame and wait of preamble
FiltState <= fs_FRMnopre;
end if;
end if;
---------------------------------------------------------------
-- FRAME, BUT STILL NO PREAMBLE
---------------------------------------------------------------
when fs_FRMnopre =>
if (StCnt(5) = cActivated or
RxDel(0).data = "11" or RxDel(0).data = "10" or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- no preamble for >=660 ns or preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif RxDel(0).data = "01" then
-- preamble starts -> Check Preamble
FiltState <= fs_FRMpre2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE TOO SHORT
---------------------------------------------------------------
when fs_FRMpre2short =>
if (RxDel(0).data /= "01" or (RxDel(0).enable = cInactivated and
RxDel(1).enable = cInactivated)) then
-- preamble wrong -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
elsif StCnt(3) = cActivated then
-- preamble ok for 180 ns -> Preamble OK
FiltState <= fs_FRMpreOk;
end if;
---------------------------------------------------------------
-- FRAME CHECK PREAMBLE OK
---------------------------------------------------------------
when fs_FRMpreOk =>
if RxDel(0).data /= "01" then
-- preamble done -> Start Frame
FiltState <= fs_FRMok;
end if;
if ((StCnt(5) = cActivated and StCnt(2) = cActivated) or
(RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated)) then
-- preamble to long for 740 ns -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- preamble is OK
LastFrameNOK <= cInactivated;
---------------------------------------------------------------
-- FRAME OK
---------------------------------------------------------------
when fs_FRMok =>
if StCnt(13) = cActivated then
-- FRAME > 163,842 us -> too long -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cInactivated and RxDel(1).enable = cInactivated then
-- FRAME [163,842 us] -> OK -> Start GAP
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
---------------------------------------------------------------
-- BLOCK FILTER
---------------------------------------------------------------
when fs_BlockAll =>
if StCnt(2) = cActivated then
-- Block for 100 nsec
FiltState <= fs_GAP2short;
RstStCnt := cActivated;
end if;
if RxDel(0).enable = cActivated then
-- Rxdv != cInactivated -> Reset Wait Period
RstStCnt := cActivated;
end if;
-- block next rx frame (until receive a valid preamble)
LastFrameNOK <= cActivated;
when others =>
FiltState <= fs_init;
end case;
if iRxError = cActivated then
-- iRxError -> Block Filter
FiltState <= fs_BlockAll;
RstStCnt := cActivated;
end if;
-- State Counter --
StCnt <= std_logic_vector(unsigned(StCnt) + 1);
if RstStCnt = cActivated then
StCnt <= (others => cInactivated);
end if;
end if;
end process;
end rtl;
|
----------------------------------------------------------------------------------
-- Company: University of Washington
-- Engineer: Lev Kurilenko
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Lev Kurilenko
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 08/18/2016 11:27:16 AM
-- Design Name:
-- Module Name: AXI4_SPI_top - Behavioral
-- Project Name:
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Micron SPI Flash Documentation (n25q256 1.8V): https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_1_8v.pdf
-- axi_quad_spi Documentation: http://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AXI4_SPI is
port(
clk_200 : in std_logic;
clk_125 : in std_logic;
clk_50 : in std_logic;
myIP : out std_logic_vector(31 downto 0); -- Signal going out to mmfe8_top and used as main IP
myMAC : out std_logic_vector(47 downto 0); -- Signal going out to mmfe8_top and used as main MAC
destIP : out std_logic_vector(31 downto 0); -- Signal going out to mmfe8_top and used as main destIP
default_IP : in std_logic_vector(31 downto 0);
default_MAC : in std_logic_vector(47 downto 0);
default_destIP : in std_logic_vector(31 downto 0);
myIP_set : in std_logic_vector(31 downto 0); -- Signal coming from config_logic. Used to set myIP
myMAC_set : in std_logic_vector(47 downto 0); -- Signal coming from config_logic. Used to set myMAC
destIP_set : in std_logic_vector(31 downto 0); -- Signal coming from config_logic. Used to set destIP
newip_start : in std_logic; -- Flag that initiates the process for setting newIP
flash_busy : out std_logic; -- Flag that indicates the module is busy setting IP
-- refer to Micron documentation for the signals below: https://www.micron.com/~/media/documents/products/data-sheet/nor-flash/serial-nor/n25q/n25q_256mb_1_8v.pdf
io0_i : IN STD_LOGIC; -- Signals for DQ0 (MOSI)
io0_o : OUT STD_LOGIC;
io0_t : OUT STD_LOGIC;
io1_i : IN STD_LOGIC; -- Signals for DQ1 (MISO)
io1_o : OUT STD_LOGIC;
io1_t : OUT STD_LOGIC;
ss_i : IN STD_LOGIC_VECTOR(0 DOWNTO 0); -- Slave Select
ss_o : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
ss_t : OUT STD_LOGIC
--SPI_CLK : in std_logic
);
end AXI4_SPI;
architecture Behavioral of AXI4_SPI is
-------------------------------------------------
-- Flow FSM signals
-------------------------------------------------
type state_spi is (SETUP, IDLE, WAIT_WRITE, WRITE, FINISH_WRITE, WAIT_READ, READ, FINISH_READ);
signal spi_state : state_spi; -- State machine that handles the signals necessary to perform a single write to or read to and from a core register in the axi_quad_spi
type state_spi_control is (CLEAR_FIFO, WRITE_CMD_ADDR_DATA, ASSERT_SS, DEASSERT_INHIB, CLEAR_SS, ASSERT_INHIB, READ_SPI_DATA, RESET);
signal spi_state_control : state_spi_control; -- State machine that handles the higher level flow (above spi_state) in order to execute a proper transaction via the axi_quad_spi (Nested within spi_state = IDLE)
type config_ip_state is (IDLE, CHECK_IP_SET, SET_IP, NEW_IP, RESET);
signal ip_config_state : config_ip_state; -- State machine that handles Dynamic IP Configuration. Can be though of as wrapper that allows proper function of Dynamic IP Configuration
type spi_write_state is (WRITE_ENABLE, SUBSECTOR_ERASE, PAGE_PROGRAM, RESET);
signal write_spi_state : spi_write_state; -- State machine nested within ip_config_state = NEW_IP. Handles the necessary logic in order to execute a write to the SPI Flash. (Specific logic flow needed)
-------------------------------------------------
-- FSM Automation signals
-------------------------------------------------
signal araddr_set : std_logic_vector(6 downto 0); -- Sets read address for registers in axi_quad_spi
signal awaddr_set : std_logic_vector(6 downto 0); -- Sets write address for registers in axi_quad_spi
signal wdata_set : std_logic_vector(31 downto 0); -- Sets write data for registers in axi_quad_spi
signal byte_transfer_counter : integer := 0; -- Counts how many bytes are being transferred/read to or from Rx or Tx FIFO in axi_quad_spi
signal page_prog_counter : integer := 0; -- Used to see what page program iteration (command to SPI Flash) FSM is at
signal set_ip_counter : integer := 0; -- Counter used to delay some signals within FSM for proper transactions
signal check_ip_counter : integer := 0; -- Counts how many times the check_ip_flag was checked
shared variable cmdaddrdata : bit_vector(79 downto 0); -- Stores command, address, and data needed for transactions with the SPI Flash
signal start_transaction : std_logic := '0'; -- Flag that initiates a transaction with the SPI Flash
signal transaction_finished : std_logic := '1'; -- Flag letting the FSM know that transaction is finished
signal second_transaction : std_logic := '0'; -- Flag used when performing 2 transaction to read the proper data from SPI Flash
signal page_prog : std_logic := '0'; -- Page program flag lets the spi_write_state = WRITE_ENABLE state know whether to perform a SUBESCTOR_ERASE or a PAGE_PROGRAM
signal system_start : std_logic := '0'; -- Flag used to check if the system has just started. Used to configure the proper IP, MAC, and destIP
-------------------------------------------------
-- Dynamic IP signals
-------------------------------------------------
signal cmdaddrdata_set : std_logic_vector(79 downto 0);
signal byte_count_set : std_logic_vector(31 downto 0);
signal ip_set_flag : std_logic_vector(7 downto 0) := x"FF";
signal new_ip_set : std_logic := '0';
signal set_default_ip : std_logic := '0';
-------------------------------------------------
-- Debugging Signals
-------------------------------------------------
signal read_out : std_logic_vector(244 downto 0);
-------------------------------------------------
-- Quad SPI Signals
-- refer to quad_spi_documentation: http://www.xilinx.com/support/documentation/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf
-------------------------------------------------
signal ip2intc_irpt : std_logic:= '0';
signal spi_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others => '0');
signal spi_arready : std_logic:= '0';
signal spi_rresp : STD_LOGIC_VECTOR(1 DOWNTO 0):=(others => '0');
signal spi_rvalid : std_logic:= '1';
signal spi_counter : integer := 0;
signal spi_slct_cmd : integer := 0;
signal spi_cnt : STD_LOGIC_VECTOR(31 DOWNTO 0):=(others => '0');
signal spi_awready : std_logic := '1';
signal spi_bresp : STD_LOGIC_vector(1 downto 0) := "00";
signal spi_bvalid : std_logic := '0';
signal spi_awaddr : std_logic_vector(6 downto 0) := "0000000";
signal spi_wdata : std_logic_vector(31 downto 0) := x"00000000";
signal spi_wstrb : std_logic_vector(3 downto 0) := "0000";
signal spi_aresetn : std_logic := '0';
signal spi_awvalid : std_logic := '0';
signal spi_wvalid : std_logic := '0';
signal spi_bready : std_logic := '0';
signal spi_wready : std_logic := '0';
signal spi_arvalid : std_logic := '0';
signal spi_rready : std_logic := '0';
signal spi_araddr : std_logic_vector(6 downto 0) := "0000000";
signal spi_state_is : std_logic_vector(3 downto 0) := "0000";
signal spi_state_control_is : std_logic_vector(3 downto 0) := "0000";
signal spi_ip_config_state_is : std_logic_vector(3 downto 0) := "0000";
signal write_spi_state_is : std_logic_vector(3 downto 0) := "0000";
signal startupe2_eos : std_logic;
-------------------------------------------------------------------
-- CDCC signals
-------------------------------------------------------------------
signal flash_busy_i : std_logic := '0';
signal myIP_i : std_logic_vector(31 downto 0) := (others => '0');
signal myMAC_i : std_logic_vector(47 downto 0) := (others => '0');
signal destIP_i : std_logic_vector(31 downto 0) := (others => '0');
signal newIP_start_s50 : std_logic := '0';
signal myIP_set_s50 : std_logic_vector(31 downto 0) := (others => '0');
signal myMAC_set_s50 : std_logic_vector(47 downto 0) := (others => '0');
signal destIP_set_s50 : std_logic_vector(31 downto 0) := (others => '0');
-------------------------------------------------------------------
-- Keep signals for ILA
-------------------------------------------------------------------
-- attribute keep : string;
-- attribute dont_touch : string;
-------------------------------------------------------------------
-- Other
-------------------------------------------------------------------
-- attribute keep of ip_set_flag : signal is "TRUE";
-- attribute dont_touch of ip_set_flag : signal is "TRUE";
-- attribute keep of spi_arready : signal is "TRUE";
-- attribute dont_touch of spi_arready : signal is "TRUE";
-- attribute keep of spi_rresp : signal is "TRUE";
-- attribute dont_touch of spi_rresp : signal is "TRUE";
-- attribute keep of spi_rvalid : signal is "TRUE";
-- attribute dont_touch of spi_rvalid : signal is "TRUE";
-- attribute keep of spi_cnt : signal is "TRUE";
-- attribute dont_touch of spi_cnt : signal is "TRUE";
-- attribute keep of spi_awready : signal is "TRUE";
-- attribute dont_touch of spi_awready : signal is "TRUE";
-- attribute keep of spi_bresp : signal is "TRUE";
-- attribute dont_touch of spi_bresp : signal is "TRUE";
-- attribute keep of spi_bvalid : signal is "TRUE";
-- attribute dont_touch of spi_bvalid : signal is "TRUE";
-- attribute keep of spi_awaddr : signal is "TRUE";
-- attribute dont_touch of spi_awaddr : signal is "TRUE";
-- attribute keep of spi_wdata : signal is "TRUE";
-- attribute dont_touch of spi_wdata : signal is "TRUE";
-- attribute keep of spi_wstrb : signal is "TRUE";
-- attribute dont_touch of spi_wstrb : signal is "TRUE";
-- attribute keep of spi_aresetn : signal is "TRUE";
-- attribute dont_touch of spi_aresetn : signal is "TRUE";
-- attribute keep of spi_awvalid : signal is "TRUE";
-- attribute dont_touch of spi_awvalid : signal is "TRUE";
-- attribute keep of spi_wvalid : signal is "TRUE";
-- attribute dont_touch of spi_wvalid : signal is "TRUE";
-- attribute keep of spi_bready : signal is "TRUE";
-- attribute dont_touch of spi_bready : signal is "TRUE";
-- attribute keep of spi_wready : signal is "TRUE";
-- attribute dont_touch of spi_wready : signal is "TRUE";
-- attribute keep of spi_arvalid : signal is "TRUE";
-- attribute dont_touch of spi_arvalid : signal is "TRUE";
-- attribute keep of spi_rready : signal is "TRUE";
-- attribute dont_touch of spi_rready : signal is "TRUE";
-- attribute keep of spi_araddr : signal is "TRUE";
-- attribute dont_touch of spi_araddr : signal is "TRUE";
-- attribute keep of spi_rdata : signal is "TRUE";
-- attribute dont_touch of spi_rdata : signal is "TRUE";
-- attribute keep of araddr_set : signal is "TRUE";
-- attribute dont_touch of araddr_set : signal is "TRUE";
-- attribute keep of awaddr_set : signal is "TRUE";
-- attribute dont_touch of awaddr_set : signal is "TRUE";
-- attribute keep of wdata_set : signal is "TRUE";
-- attribute dont_touch of wdata_set : signal is "TRUE";
-- attribute keep of spi_state_control_is : signal is "TRUE";
-- attribute dont_touch of spi_state_control_is : signal is "TRUE";
-- attribute keep of io0_i : signal is "TRUE";
-- attribute dont_touch of io0_i : signal is "TRUE";
-- attribute keep of io0_o : signal is "TRUE";
-- attribute dont_touch of io0_o : signal is "TRUE";
-- attribute keep of io0_t : signal is "TRUE";
-- attribute dont_touch of io0_t : signal is "TRUE";
-- attribute keep of io1_i : signal is "TRUE";
-- attribute dont_touch of io1_i : signal is "TRUE";
-- attribute keep of io1_o : signal is "TRUE";
-- attribute dont_touch of io1_o : signal is "TRUE";
-- attribute keep of io1_t : signal is "TRUE";
-- attribute dont_touch of io1_t : signal is "TRUE";
-- attribute keep of ss_i : signal is "TRUE";
-- attribute dont_touch of ss_i : signal is "TRUE";
-- attribute keep of ss_o : signal is "TRUE";
-- attribute dont_touch of ss_o : signal is "TRUE";
-- attribute keep of ss_t : signal is "TRUE";
-- attribute dont_touch of ss_t : signal is "TRUE";
-- attribute keep of cmdaddrdata_set : signal is "TRUE";
-- attribute dont_touch of cmdaddrdata_set : signal is "TRUE";
-- attribute keep of cmdaddrdata : variable is "TRUE";
-- attribute dont_touch of cmdaddrdata : variable is "TRUE";
-- attribute keep of start_transaction : signal is "TRUE";
-- attribute dont_touch of start_transaction : signal is "TRUE";
-- attribute keep of transaction_finished : signal is "TRUE";
-- attribute dont_touch of transaction_finished : signal is "TRUE";
-- attribute keep of spi_ip_config_state_is : signal is "TRUE";
-- attribute dont_touch of spi_ip_config_state_is : signal is "TRUE";
-- attribute keep of newip_start : signal is "TRUE";
-- attribute dont_touch of newip_start : signal is "TRUE";
-- attribute keep of write_spi_state_is : signal is "TRUE";
-- attribute dont_touch of write_spi_state_is : signal is "TRUE";
-- attribute keep of byte_transfer_counter : signal is "true";
-- attribute keep of set_ip_counter : signal is "true";
-- attribute keep of page_prog_counter : signal is "true";
-- attribute keep of second_transaction : signal is "true";
-- attribute keep of page_prog : signal is "true";
-- attribute keep of system_start : signal is "true";
-- attribute keep of check_ip_counter : signal is "true";
-- attribute keep of set_default_ip : signal is "true";
-- attribute keep of myIP_set : signal is "true";
-- attribute keep of myMAC_set : signal is "true";
-- attribute keep of destIP_set : signal is "true";
-- attribute dont_touch of myIP_set : signal is "true";
-- attribute dont_touch of myMAC_set : signal is "true";
-- attribute dont_touch of destIP_set : signal is "true";
component ila_spi_flash
PORT ( clk : IN std_logic;
probe0 : IN std_logic_vector(244 DOWNTO 0)
);
end component;
component CDCC
generic(
NUMBER_OF_BITS : integer := 8); -- number of signals to be synced
port(
clk_src : in std_logic; -- input clk (source clock)
clk_dst : in std_logic; -- input clk (dest clock)
data_in : in std_logic_vector(NUMBER_OF_BITS - 1 downto 0); -- data to be synced
data_out_s : out std_logic_vector(NUMBER_OF_BITS - 1 downto 0) -- synced data to clk_dst
);
end component;
-- component vio_0
-- PORT ( clk : IN std_logic;
-- probe_out0 : OUT std_logic;
-- probe_out1 : OUT std_logic;
-- probe_out2 : OUT std_logic_vector(79 DOWNTO 0);
-- probe_out3 : OUT std_logic_vector(31 DOWNTO 0);
-- probe_out4 : OUT std_logic;
-- probe_out5 : OUT std_logic
-- );
-- end component;
component axi_quad_spi_0 is
Port (
ext_spi_clk : in std_logic;
s_axi_aclk : in std_logic;
s_axi_aresetn : in std_logic;
s_axi_awaddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_awvalid : in std_logic;
s_axi_awready : out std_logic;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wvalid : in std_logic;
s_axi_wready : out std_logic;
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out std_logic;
s_axi_bready : in std_logic;
s_axi_araddr : in STD_LOGIC_VECTOR ( 6 downto 0 );
s_axi_arvalid : in std_logic;
s_axi_arready : out std_logic;
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rvalid : out std_logic;
s_axi_rready : in std_logic;
io0_i : in std_logic;
io0_o : out std_logic;
io0_t : out std_logic;
io1_i : in std_logic;
io1_o : out std_logic;
io1_t : out std_logic;
ss_i : in STD_LOGIC_VECTOR ( 0 to 0 );
ss_o : out STD_LOGIC_VECTOR ( 0 to 0 );
ss_t : out std_logic;
ip2intc_irpt : out std_logic;
cfgclk : out std_logic;
cfgmclk : out std_logic;
eos : out std_logic;
preq : out std_logic
);
end component;
begin
axi_SPI: axi_quad_spi_0
Port map(
ext_spi_clk => clk_50, --V22
--ext_spi_clk => SPI_CLK, --V22
s_axi_aclk => clk_50,
s_axi_aresetn => spi_aresetn,
s_axi_awaddr => spi_awaddr,
s_axi_awvalid => spi_wvalid,
s_axi_awready => spi_awready,
s_axi_wdata => spi_wdata,
s_axi_wstrb => spi_wstrb,
s_axi_wvalid => spi_wvalid,
s_axi_wready => spi_wready,
s_axi_bresp => spi_bresp,
s_axi_bvalid => spi_bvalid,
s_axi_bready => spi_bready,
s_axi_araddr => spi_araddr,
s_axi_arvalid => spi_arvalid,
s_axi_arready => spi_arready,
s_axi_rdata => spi_rdata,
s_axi_rresp => spi_rresp,
s_axi_rvalid => spi_rvalid,
s_axi_rready => spi_rready,
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t,
ip2intc_irpt => ip2intc_irpt,
cfgclk => open,
cfgmclk => open,
eos => startupe2_eos,
preq => open
);
spi_ip_config: process(clk_50) -- Process that handles Dynamic IP Configuration
begin
if rising_edge(clk_50) then
case ip_config_state is -- State machine that handles Dynamic IP Configuration. Can be though of as wrapper that allows proper function of Dynamic IP Configuration
when IDLE =>
spi_ip_config_state_is <= "0000";
flash_busy_i <= '0';
if (system_start = '0') then -- Checked when system is started to set IP
ip_config_state <= CHECK_IP_SET;
elsif (newip_start_s50 = '1') then -- This is set when UDP dest port 6604 receives data
ip_config_state <= NEW_IP;
else
ip_config_state <= IDLE;
end if;
when CHECK_IP_SET =>
spi_ip_config_state_is <= "0001";
flash_busy_i <= '1';
cmdaddrdata_set <= x"03F0_0000_0000_0000_0000"; -- Command to read ipset_flag in address x"F0_0000"
byte_count_set <= x"0000_0004"; -- Byte count required for proper read: 4 bytes (starts at 0)
set_ip_counter <= 0;
start_transaction <= '0';
if (transaction_finished = '1') then -- Checks if ipset_flag = x"01" and sets the flag accordingly
if (ip_set_flag = x"01") then
system_start <= '1';
ip_config_state <= SET_IP;
check_ip_counter <= 0;
elsif ((ip_set_flag /= x"01") and (check_ip_counter > 5)) then -- Must iterate
ip_config_state <= IDLE;
set_default_ip <= '1';
system_start <= '1';
check_ip_counter <= 0;
else
start_transaction <= '1';
check_ip_counter <= check_ip_counter + 1;
end if;
end if;
when SET_IP => -- Performs necessary operations to read SPI Flash and set the current IP, MAC, and destIP
spi_ip_config_state_is <= "0010";
if ( set_ip_counter <= 50) then
set_ip_counter <= set_ip_counter + 1;
end if;
if ((transaction_finished = '1') and (set_ip_counter < 10)) then
second_transaction <= '0';
cmdaddrdata_set <= x"03F0_0001_0000_0000_0000";
byte_count_set <= x"0000_000F";
start_transaction <= '1';
elsif ((transaction_finished = '1') and (set_ip_counter >= 40)) then
second_transaction <= '1';
cmdaddrdata_set <= x"03F0_000D_0000_0000_0000";
byte_count_set <= x"0000_0005";
set_ip_counter <= set_ip_counter + 1;
start_transaction <= '1';
if( set_ip_counter = 70) then
ip_config_state <= RESET;
set_ip_counter <= 0;
end if;
else
start_transaction <= '0';
end if;
when NEW_IP => -- Writes new IP, MAC, and destIP into SPI Flash and sets the new IP as the current active IP, MAC, and destIP
spi_ip_config_state_is <= "0011";
flash_busy_i <= '1';
case write_spi_state is -- State machine nested within ip_config_state = NEW_IP. Handles the necessary logic in order to execute a write to the SPI Flash. (Uses logic flow described in Micron Documentation)
when WRITE_ENABLE =>
write_spi_state_is <= "0000";
start_transaction <= '0';
if (set_ip_counter < 3) then --Wait 3 Clock cycles before beginning next transaction
set_ip_counter <= set_ip_counter + 1;
elsif ((transaction_finished = '1') and (set_ip_counter = 3)) then
cmdaddrdata_set <= x"0600_0000_0000_0000_0000"; --SPI WRITE ENABLE
byte_count_set <= x"0000_0000";
start_transaction <= '1';
set_ip_counter <= 0;
if (page_prog = '0') then
write_spi_state <= SUBSECTOR_ERASE;
page_prog <= '1';
elsif (page_prog = '1') then
write_spi_state <= PAGE_PROGRAM;
end if;
end if;
when SUBSECTOR_ERASE =>
write_spi_state_is <= "0001";
start_transaction <= '0';
if (set_ip_counter < 3) then --Wait 3 Clock cycles before beginning next transaction
set_ip_counter <= set_ip_counter + 1;
elsif ((transaction_finished = '1') and (set_ip_counter = 3)) then
cmdaddrdata_set <= x"20F0_0000_0000_0000_0000"; --SPI SUBSECTOR ERASE 4kB
byte_count_set <= x"0000_0003";
start_transaction <= '1';
set_ip_counter <= 0;
write_spi_state <= WRITE_ENABLE;
end if;
when PAGE_PROGRAM =>
write_spi_state_is <= "0010";
start_transaction <= '0';
if (set_ip_counter < 3) then --Wait 3 Clock cycles before beginning next transaction
set_ip_counter <= set_ip_counter + 1;
elsif ((transaction_finished = '1') and (set_ip_counter = 3)) then
set_ip_counter <= 0;
if (page_prog_counter = 0) then
page_prog_counter <= page_prog_counter + 1;
--myIP_set -- 32 bits
--myMAC_set -- 48 bits
--destIP_set -- 32 bits
cmdaddrdata_set(79 downto 40) <= x"02F0_0000_01"; --SPI PAGE PROGRAM 256 BYTES
cmdaddrdata_set(39 downto 8) <= myIP_set_s50(31 downto 0);
cmdaddrdata_set(7 downto 0) <= myMAC_set_s50(47 downto 40);
byte_count_set <= x"0000_0009";
write_spi_state <= WRITE_ENABLE; -- Write enable must be issued before every write operation
start_transaction <= '1';
elsif (page_prog_counter = 1) then
page_prog_counter <= page_prog_counter + 1;
cmdaddrdata_set(79 downto 48) <= x"02F0_0006"; --SPI PAGE PROGRAM 256 BYTES
cmdaddrdata_set(47 downto 8) <= myMAC_set_s50(39 downto 0);
cmdaddrdata_set(7 downto 0) <= destIP_set_s50(31 downto 24);
byte_count_set <= x"0000_0009";
write_spi_state <= WRITE_ENABLE; -- Write enable must be issued before every write operation
start_transaction <= '1';
elsif (page_prog_counter = 2) then
page_prog_counter <= page_prog_counter + 1;
cmdaddrdata_set(79 downto 48) <= x"02F0_000C"; --SPI PAGE PROGRAM 256 BYTES
cmdaddrdata_set(47 downto 24) <= destIP_set_s50(23 downto 0);
cmdaddrdata_set(23 downto 0) <= x"0000_00";
byte_count_set <= x"0000_0006";
start_transaction <= '1';
elsif (page_prog_counter = 3) then
page_prog_counter <= 0;
write_spi_state <= RESET;
page_prog <= '0';
set_default_ip <= '0';
system_start <= '0'; -- This will 'reset' the system_start flag and the FSM will check for the IP in SPI Flash again
end if;
end if;
when RESET =>
write_spi_state_is <= "0011";
start_transaction <= '0';
set_ip_counter <= set_ip_counter + 1;
if( set_ip_counter = 10) then
ip_config_state <= RESET;
set_ip_counter <= 0;
write_spi_state <= WRITE_ENABLE;
end if;
end case;
when RESET =>
page_prog_counter <= 0;
start_transaction <= '0';
spi_ip_config_state_is <= "0100";
if (transaction_finished = '1') then
cmdaddrdata_set <= x"0000_0000_0000_0000_0000";
byte_count_set <= x"0000_0000";
ip_config_state <= IDLE;
end if;
when others =>
spi_ip_config_state_is <= "0101";
ip_config_state <= RESET;
end case;
end if;
end process;
spi_read_write_core_registers: process(clk_50) -- State machine that handles the signals necessary to write to or read from a core register
begin
if rising_edge(clk_50) then
if (set_default_ip = '1') then
myIP_i <= default_IP;
myMAC_i <= default_MAC;
destIP_i <= default_destIP;
end if;
case spi_state is -- State machine that handles the signals necessary to perform a single write to or read to and from a core register in the axi_quad_spi
when SETUP =>
spi_aresetn <= '0';
if (start_transaction = '1') then
transaction_finished <= '0';
spi_state <= IDLE;
spi_counter <= 0;
spi_aresetn <= '1';
end if;
when IDLE =>
spi_awvalid <= '0';
spi_wvalid <= '0';
spi_bready <= '0';
spi_counter <= 0;
spi_rready <= '0';
spi_state_is <= "0000";
case spi_state_control is -- State machine that handles the higher level flow (above spi_state) in order to execute a proper transaction via the axi_quad_spi (Nested within spi_state = IDLE)
when CLEAR_FIFO => -- Clear Rx and Tx FIFO's in axi_quad_spi
spi_state_control_is <= "0000";
araddr_set <= "1100100"; --x"64";
awaddr_set <= "1100000"; --x"60";
wdata_set <= x"00000186";
spi_state <= WAIT_WRITE;
spi_state_control <= WRITE_CMD_ADDR_DATA;
byte_transfer_counter <= to_integer(unsigned(byte_count_set));
cmdaddrdata := to_bitvector(cmdaddrdata_set);
when WRITE_CMD_ADDR_DATA => -- Write the command, address, and data into the Tx FIFO in axi_quad_spi
spi_state_control_is <= "0001";
araddr_set <= "1110100"; --x"74";
awaddr_set <= "1101000"; --x"68";
wdata_set <= x"000000" & to_stdlogicvector(cmdaddrdata(79 downto 72));
byte_transfer_counter <= byte_transfer_counter - 1;
cmdaddrdata := cmdaddrdata sll 8;
spi_state <= WAIT_WRITE;
if (byte_transfer_counter = 0) then
spi_state_control <= ASSERT_SS;
end if;
when ASSERT_SS => -- Assert Slave Select by writing x"00" into the x"70" registers in axi_quad_spi
spi_state_control_is <= "0010";
araddr_set <= "1100100"; --x"64"
awaddr_set <= "1110000"; --x"70";
wdata_set <= x"00000000";
spi_state <= WAIT_WRITE;
spi_state_control <= DEASSERT_INHIB;
when DEASSERT_INHIB => -- Deassert inhibit bit in order to allow the Master (FPGA) to communicate with the Slave (SPI Flash)
spi_state_control_is <= "0011";
araddr_set <= "1100100"; --x"64"
awaddr_set <= "1100000"; --x"60";
wdata_set <= x"00000086";
spi_counter <= 0;
spi_state <= WAIT_WRITE;
spi_state_control <= CLEAR_SS;
when CLEAR_SS => -- Clear Slave Select by pulling the SS line high after 400 clock cycles (default)
spi_state_control_is <= "0100";
araddr_set <= "1100100"; --x"64"
awaddr_set <= "1110000"; --x"70";
spi_counter <= spi_counter + 1;
if (spi_counter > 400) then
wdata_set <= x"00000001";
spi_counter <= 0;
spi_state <= WAIT_WRITE;
spi_state_control <= ASSERT_INHIB;
end if;
when ASSERT_INHIB => -- Assert inhibit bit in order to inhibit the Master (FPGA) to communicate with the Slave (SPI Flash)
spi_state_control_is <= "0101";
araddr_set <= "1111000"; --x"78"
awaddr_set <= "1100000"; --x"60";
wdata_set <= x"00000186";
spi_counter <= spi_counter + 1;
if((cmdaddrdata_set(79 downto 72) = x"20") and (spi_counter = 25_000_000)) then -- Need to wait 0.5 s for successful SUBSECTOR_ERASE operation after SS is pulled high
spi_state <= WAIT_WRITE;
spi_state_control <= READ_SPI_DATA;
byte_transfer_counter <= to_integer(unsigned(byte_count_set)) + 1;
spi_counter <= 0;
elsif ((cmdaddrdata_set(79 downto 72) = x"02") and (spi_counter = 7500))then -- Need to wait 0.15 ms for successful PAGE_PROGRAM operation after SS is pulled high
spi_state <= WAIT_WRITE;
spi_state_control <= READ_SPI_DATA;
byte_transfer_counter <= to_integer(unsigned(byte_count_set)) + 1;
spi_counter <= 0;
elsif ((cmdaddrdata_set(79 downto 72) /= x"20") and (cmdaddrdata_set(79 downto 72) /= x"02")) then
spi_state <= WAIT_WRITE;
spi_state_control <= READ_SPI_DATA;
byte_transfer_counter <= to_integer(unsigned(byte_count_set)) + 1;
spi_counter <= 0;
end if;
when READ_SPI_DATA => -- Read SPI data in the Rx FIFO in axi_quad_spi
spi_state_control_is <= "0110";
araddr_set <= "1101100"; --x"6C";
awaddr_set <= "1111111"; --x"7F"; --Address does not exist. Just there so core registers are not written too
wdata_set <= x"00000000"; --Dummy data
byte_transfer_counter <= byte_transfer_counter - 1; --Read occupancy register
spi_state <= WAIT_READ;
if ((ip_config_state = CHECK_IP_SET) and (byte_transfer_counter = 0)) then
ip_set_flag <= spi_rdata(7 downto 0);
end if;
if (ip_config_state = SET_IP) then
if (second_transaction = '0') then
if ((byte_transfer_counter >= 8) and (byte_transfer_counter <= 11)) then
myIP_i((byte_transfer_counter-8)*8+7 downto (byte_transfer_counter-8)*8) <= spi_rdata(7 downto 0);
elsif ((byte_transfer_counter >= 2) and (byte_transfer_counter <= 7)) then
myMAC_i((byte_transfer_counter-2)*8+7 downto (byte_transfer_counter-2)*8) <= spi_rdata(7 downto 0);
elsif ((byte_transfer_counter >= 0) and (byte_transfer_counter <= 1)) then
destIP_i((byte_transfer_counter+2)*8+7 downto (byte_transfer_counter+2)*8) <= spi_rdata(7 downto 0);
end if;
elsif (second_transaction = '1') then
if ((byte_transfer_counter >= 0) and (byte_transfer_counter <= 1)) then
destIP_i((byte_transfer_counter)*8+7 downto (byte_transfer_counter)*8) <= spi_rdata(7 downto 0);
end if;
end if;
end if;
if (byte_transfer_counter = 0) then
spi_state_control <= RESET;
end if;
when RESET =>
spi_state_control_is <= "0111";
transaction_finished <= '1';
spi_state <= SETUP;
spi_state_control <= CLEAR_FIFO;
--end if;
when others =>
araddr_set <= "0000000";
awaddr_set <= "0000000";
wdata_set <= x"00000000";
transaction_finished <= '1';
spi_state_control_is <= "1111"; --Error State
spi_state <= SETUP;
spi_state_control <= CLEAR_FIFO;
end case;
when WAIT_WRITE => -- State for writing to the axi_quad_spi register
spi_state_is <= "0001";
spi_counter <= spi_counter + 1;
spi_wstrb <= "0000";
if spi_counter = 5 then
spi_state <= WRITE;
spi_counter <= 0;
end if;
when WRITE => -- State for writing to the axi_quad_spi register
spi_state_is <= "0010";
spi_awaddr <= awaddr_set;
spi_wdata <= wdata_set;
spi_awvalid <= '1';
spi_wvalid <= '1';
spi_wstrb <= "1111";
spi_bready <= '1';
if spi_awready = '1' or spi_wready = '1' then
spi_state <= FINISH_WRITE;
spi_wstrb <= "0000";
spi_awaddr <= "0000000";
spi_wdata <= x"00000000";
spi_awvalid <= '0';
spi_wvalid <= '0';
end if;
when FINISH_WRITE => -- State for writing to the axi_quad_spi register
spi_state_is <= "0011";
spi_awaddr <= "0000000";
spi_wdata <= x"00000000";
spi_awvalid <= '0';
spi_wvalid <= '0';
if spi_bvalid = '1' then
spi_bready <= '0';
spi_state <= IDLE;
end if;
when WAIT_READ => -- State for reading from the axi_quad_spi register
spi_state_is <= "0100";
spi_counter <= spi_counter + 1;
if spi_counter = 10 then
spi_state <= READ;
spi_counter <= 0;
end if;
when READ => -- State for reading from the axi_quad_spi register
spi_state_is <= "0101";
spi_counter <= spi_counter + 1;
spi_araddr <= araddr_set;
spi_arvalid <= '1';
spi_rready <= '1';
if spi_counter = 10 then
spi_state <= FINISH_READ;
spi_counter <= 0;
end if;
when FINISH_READ => -- State for reading from the axi_quad_spi register
spi_state_is <= "0110";
if spi_arready = '1' then
spi_araddr <= "0000000";
spi_arvalid <= '0';
spi_arvalid <= '0';
spi_counter <= 0;
end if;
spi_state <= IDLE;
end case;
end if;
end process;
--spi_cnt <= std_logic_vector(to_unsigned(spi_counter, spi_cnt'length));
spi_cnt <= std_logic_vector(to_unsigned(spi_counter, 32));
---------------------------------------------------------
--------- Clock Domain Crossing Sync Block --------------
---------------------------------------------------------
-- sync output signals to 125 Mhz clock
CDCC_50to125: CDCC
generic map(NUMBER_OF_BITS => 113)
port map(
clk_src => clk_50,
clk_dst => clk_125,
data_in(112) => flash_busy_i,
data_in(111 downto 80) => myIP_i,
data_in(79 downto 32) => myMAC_i,
data_in(31 downto 0) => destIP_i,
data_out_s(112) => flash_busy,
data_out_s(111 downto 80) => myIP,
data_out_s(79 downto 32) => myMAC,
data_out_s(31 downto 0) => destIP
);
-- sync input signals to 50 Mhz clock
CDCC_125to50: CDCC
generic map(NUMBER_OF_BITS => 113)
port map(
clk_src => clk_125,
clk_dst => clk_50,
data_in(112) => newIP_start,
data_in(111 downto 80) => myIP_set,
data_in(79 downto 32) => myMAC_set,
data_in(31 downto 0) => destIP_set,
data_out_s(112) => newIP_start_s50,
data_out_s(111 downto 80) => myIP_set_s50,
data_out_s(79 downto 32) => myMAC_set_s50,
data_out_s(31 downto 0) => destIP_set_s50
);
---------------------------------------------------------
---------------------------------------------------------
---------------------------------------------------------
--ila_top: ila_spi_flash
-- port map (
-- clk => clk_50,
-- probe0 => read_out
-- );
-- read_out(31 downto 0) <= spi_rdata;
-- read_out(38 downto 32) <= (others => '0');
-- read_out(40 downto 39) <= spi_rresp;
-- read_out(41) <= spi_awready;
-- read_out(43 downto 42) <= spi_bresp;
-- read_out(44) <= spi_bvalid;
-- read_out(45) <= spi_awvalid;
-- read_out(46) <= spi_wvalid;
-- read_out(47) <= spi_aresetn;
-- read_out(51 downto 48) <= spi_wstrb;
-- read_out(83 downto 52) <= spi_wdata;
-- read_out(90 downto 84) <= spi_awaddr;
-- read_out(91) <= spi_bready;
-- read_out(92) <= spi_wready;
-- read_out(93) <= spi_arvalid;
-- read_out(94) <= spi_rready;
-- read_out(98 downto 95) <= spi_state_is;
-- read_out(99) <= spi_rvalid;
-- read_out(100) <= spi_arready;
-- read_out(107 downto 101) <= spi_araddr;
-- read_out(108) <= '0';
-- read_out(109) <= '0';
-- read_out(110) <= '0';
-- read_out(114 downto 111) <= spi_state_control_is;
-- read_out(115) <= transaction_finished;
-- read_out(119 downto 116) <= spi_ip_config_state_is;
-- read_out(127 downto 120) <= ip_set_flag;
-- read_out(128) <= newip_start;
-- read_out(208 downto 129) <= cmdaddrdata_set;
-- read_out(212 downto 209) <= write_spi_state_is;
-- read_out(244 downto 213) <= spi_cnt;
--vio_top: vio_0
-- port map (
-- clk => clk_200,
-- probe_out0 => start_vio,
-- probe_out1 => system_start_vio,
-- probe_out2 => cmdaddrdata_vio,
-- probe_out3 => byte_count_vio,
-- probe_out4 => new_ip_vio,
-- probe_out5 => set_ip_vio
-- );
end Behavioral;
|
------------------------------------------------------------------------------
-- Copyright (c) 2009 Xilinx, Inc.
-- This design is confidential and proprietary of Xilinx, All Rights Reserved.
------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version: 1.0
-- \ \ Filename: serdes_1_to_n_data_s8_se.vhd
-- / / Date Last Modified: November 5 2009
-- /___/ /\ Date Created: August 1 2008
-- \ \ / \
-- \___\/\___\
--
--Device: Spartan 6
--Purpose: D-bit generic 1:n data receiver module with se inputs
-- Takes in 1 bit of se data and deserialises this to n bits
-- data is received LSB first
-- Serial input words
-- Line0 : 0, ...... DS-(S+1)
-- Line1 : 1, ...... DS-(S+2)
-- Line(D-1) : . .
-- Line0(D) : D-1, ...... DS
-- Parallel output word
-- DS, DS-1 ..... 1, 0
--
-- Includes state machine to control CAL and the phase detector
-- Data inversion can be accomplished via the RX_RX_SWAP_MASK
-- parameter if required
--
--Reference:
--
--Revision History:
-- Rev 1.0 - First created (nicks)
------------------------------------------------------------------------------
--
-- Disclaimer:
--
-- This disclaimer is not a license and does not grant any rights to the materials
-- distributed herewith. Except as otherwise provided in a valid license issued to you
-- by Xilinx, and to the maximum extent permitted by applicable law:
-- (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND WITH ALL FAULTS,
-- AND XILINX HEREBY DISCLAIMS ALL WARRANTIES AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY,
-- INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-INFRINGEMENT, OR
-- FITNESS FOR ANY PARTICULAR PURPOSE; and (2) Xilinx shall not be liable (whether in contract
-- or tort, including negligence, or under any other theory of liability) for any loss or damage
-- of any kind or nature related to, arising under or in connection with these materials,
-- including for any direct, or any indirect, special, incidental, or consequential loss
-- or damage (including loss of data, profits, goodwill, or any type of loss or damage suffered
-- as a result of any action brought by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the possibility of the same.
--
-- Critical Applications:
--
-- Xilinx products are not designed or intended to be fail-safe, or for use in any application
-- requiring fail-safe performance, such as life-support or safety devices or systems,
-- Class III medical devices, nuclear facilities, applications related to the deployment of airbags,
-- or any other applications that could lead to death, personal injury, or severe property or
-- environmental damage (individually and collectively, "Critical Applications"). Customer assumes
-- the sole risk and liability of any use of Xilinx products in Critical Applications, subject only
-- to applicable laws and regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all ;
library unisim ;
use unisim.vcomponents.all ;
entity serdes_1_to_n_data_s8_se is generic (
S : integer := 8 ; -- Parameter to set the serdes factor 1..8
D : integer := 16) ; -- Set the number of inputs and outputs
port (
use_phase_detector : in std_logic ; -- Set generation of phase detector logic
datain : in std_logic_vector(D-1 downto 0) ; -- Input from se receiver pin
rxioclk : in std_logic ; -- IO Clock network
rxserdesstrobe : in std_logic ; -- Parallel data capture strobe
reset : in std_logic ; -- Reset line
gclk : in std_logic ; -- Global clock
bitslip : in std_logic ; -- Bitslip control line
debug_in : in std_logic_vector(1 downto 0) ; -- input debug data
data_out : out std_logic_vector((D*S)-1 downto 0) ; -- Output data
debug : out std_logic_vector((2*D)+6 downto 0)) ; -- Debug bus, 2D+6 = 2 lines per input (from mux and ce) + 7, leave nc if debug not required
end serdes_1_to_n_data_s8_se ;
architecture arch_serdes_1_to_n_data_s8_se of serdes_1_to_n_data_s8_se is
signal ddly_m : std_logic_vector(D-1 downto 0) ; -- Master output from IODELAY1
signal ddly_s : std_logic_vector(D-1 downto 0) ; -- Slave output from IODELAY1
signal cascade : std_logic_vector(D-1 downto 0) ;
signal busys : std_logic_vector(D-1 downto 0) ;
signal rx_data_in : std_logic_vector(D-1 downto 0) ;
signal rx_data_in_fix : std_logic_vector(D-1 downto 0) ;
signal state : integer range 0 to 8 ;
signal busyd : std_logic_vector(D-1 downto 0) ;
signal cal_data_sint : std_logic ;
signal ce_data_inta : std_logic ;
signal busy_data : std_logic_vector(D-1 downto 0) ;
signal busy_data_d : std_logic ;
signal counter : std_logic_vector(8 downto 0) ;
signal enable : std_logic ;
signal pd_edge : std_logic_vector(D-1 downto 0) ;
signal cal_data_slave : std_logic ;
signal cal_data_master : std_logic ;
signal valid_data : std_logic_vector(D-1 downto 0) ;
signal valid_data_d : std_logic ;
signal rst_data : std_logic ;
signal mdataout : std_logic_vector((8*D)-1 downto 0) ;
signal pdcounter : std_logic_vector(4 downto 0) ;
signal inc_data : std_logic ;
signal ce_data : std_logic_vector(D-1 downto 0) ;
signal inc_data_int : std_logic ;
signal incdec_data : std_logic_vector(D-1 downto 0) ;
signal incdec_data_d : std_logic ;
signal flag : std_logic ;
signal mux : std_logic_vector(D-1 downto 0) ;
signal incdec_data_or : std_logic_vector(D downto 0) ;
signal valid_data_or : std_logic_vector(D downto 0) ;
signal busy_data_or : std_logic_vector(D downto 0) ;
signal incdec_data_im : std_logic_vector(D-1 downto 0) ;
signal valid_data_im : std_logic_vector(D-1 downto 0) ;
signal all_ce : std_logic_vector(D-1 downto 0) ;
constant RX_SWAP_MASK : std_logic_vector(D-1 downto 0) := (others => '0') ; -- pinswap mask for input bits (0 = no swap (default), 1 = swap). Allows inputs to be connected the wrong way round to ease PCB routing.
begin
busy_data <= busys ;
debug <= mux & cal_data_master & rst_data & cal_data_slave & busy_data_d & inc_data & ce_data & valid_data_d & incdec_data_d ;
cal_data_slave <= cal_data_sint ;
process (gclk, reset)
begin
if reset = '1' then
state <= 0 ;
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
counter <= (others => '0') ;
enable <= '0' ;
counter <= (others => '0') ;
mux <= (0 => '1', others => '0') ;
elsif gclk'event and gclk = '1' then
counter <= counter + 1 ;
if counter(8) = '1' then
counter <= "000000000" ;
end if ;
if counter(5) = '1' then
enable <= '1' ;
end if ;
if state = 0 and enable = '1' then -- Wait for all IODELAYs to be available
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 1 ;
end if ;
elsif state = 1 then -- Issue calibrate command to both master and slave
cal_data_master <= '1' ;
cal_data_sint <= '1' ;
if busy_data_d = '1' then -- and wait for command to be accepted
state <= 2 ;
end if ;
elsif state = 2 then -- Now RST all master and slave IODELAYs
cal_data_master <= '0' ;
cal_data_sint <= '0' ;
if busy_data_d = '0' then
rst_data <= '1' ;
state <= 3 ;
end if ;
elsif state = 3 then -- Wait for all IODELAYs to be available
rst_data <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
elsif state = 4 then -- Hang around
if counter(8) = '1' then
state <= 5 ;
end if ;
elsif state = 5 then -- Calibrate slave only
if busy_data_d = '0' then
cal_data_sint <= '1' ;
state <= 6 ;
if D /= 1 then
mux <= mux(D-2 downto 0) & mux(D-1) ;
end if ;
end if ;
elsif state = 6 then -- Wait for command to be accepted
if busy_data_d = '1' then
cal_data_sint <= '0' ;
state <= 7 ;
end if ;
elsif state = 7 then -- Wait for all IODELAYs to be available, ie CAL command finished
cal_data_sint <= '0' ;
if busy_data_d = '0' then
state <= 4 ;
end if ;
end if ;
end if ;
end process ;
process (gclk, reset)
begin
if reset = '1' then
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
flag <= '0' ;
elsif gclk'event and gclk = '1' then
busy_data_d <= busy_data_or(D) ;
if use_phase_detector = '1' then -- decide whther pd is used
incdec_data_d <= incdec_data_or(D) ;
valid_data_d <= valid_data_or(D) ;
if ce_data_inta = '1' then
ce_data <= mux ;
else
ce_data <= (others => '0') ;
end if ;
if state = 7 then
flag <= '0' ;
elsif state /= 4 or busy_data_d = '1' then -- Reset filter if state machine issues a cal command or unit is busy
pdcounter <= "10000" ;
ce_data_inta <= '0' ;
elsif pdcounter = "11111" and flag = '0' then -- Filter has reached positive max - increment the tap count
ce_data_inta <= '1' ;
inc_data_int <= '1' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif pdcounter = "00000" and flag = '0' then -- Filter has reached negative max - decrement the tap count
ce_data_inta <= '1' ;
inc_data_int <= '0' ;
pdcounter <= "10000" ;
flag <= '0' ;
elsif valid_data_d = '1' then -- increment filter
ce_data_inta <= '0' ;
if incdec_data_d = '1' and pdcounter /= "11111" then
pdcounter <= pdcounter + 1 ;
elsif incdec_data_d = '0' and pdcounter /= "00000" then -- decrement filter
pdcounter <= pdcounter - 1 ;
end if ;
else
ce_data_inta <= '0' ;
end if ;
else
ce_data <= all_ce ;
inc_data_int <= debug_in(1) ;
end if ;
end if ;
end process ;
inc_data <= inc_data_int ;
incdec_data_or(0) <= '0' ; -- Input Mux - Initialise generate loop OR gates
valid_data_or(0) <= '0' ;
busy_data_or(0) <= '0' ;
loop0 : for i in 0 to (D - 1) generate
incdec_data_im(i) <= incdec_data(i) and mux(i) ; -- Input muxes
incdec_data_or(i+1) <= incdec_data_im(i) or incdec_data_or(i) ; -- AND gates to allow just one signal through at a tome
valid_data_im(i) <= valid_data(i) and mux(i) ; -- followed by an OR
valid_data_or(i+1) <= valid_data_im(i) or valid_data_or(i) ; -- for the three inputs from each PD
busy_data_or(i+1) <= busy_data(i) or busy_data_or(i) ; -- The busy signals just need an OR gate
all_ce(i) <= debug_in(0) ;
rx_data_in_fix(i) <= rx_data_in(i) xor RX_SWAP_MASK(i) ; -- Invert signals as required
iob_clk_in : IBUF port map (
I => datain(i),
O => rx_data_in(i));
iodelay_m : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL" , -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND", -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN", -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "MASTER", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_m(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_master, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i), -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => open) ; -- output signal indicating sync circuit has finished / calibration has finished
iodelay_s : IODELAY2 generic map(
DATA_RATE => "SDR", -- <SDR>, DDR
IDELAY_VALUE => 0, -- {0 ... 255}
IDELAY2_VALUE => 0, -- {0 ... 255}
IDELAY_MODE => "NORMAL", -- NORMAL, PCI
ODELAY_VALUE => 0, -- {0 ... 255}
IDELAY_TYPE => "DIFF_PHASE_DETECTOR",-- "DEFAULT", "DIFF_PHASE_DETECTOR", "FIXED", "VARIABLE_FROM_HALF_MAX", "VARIABLE_FROM_ZERO"
COUNTER_WRAPAROUND => "WRAPAROUND" , -- <STAY_AT_LIMIT>, WRAPAROUND
DELAY_SRC => "IDATAIN" , -- "IO", "IDATAIN", "ODATAIN"
SERDES_MODE => "SLAVE", -- <NONE>, MASTER, SLAVE
SIM_TAPDELAY_VALUE => 49) --
port map (
IDATAIN => rx_data_in_fix(i), -- data from primary IOB
TOUT => open, -- tri-state signal to IOB
DOUT => open, -- output data to IOB
T => '1', -- tri-state control from OLOGIC/OSERDES2
ODATAIN => '0', -- data from OLOGIC/OSERDES2
DATAOUT => ddly_s(i), -- Output data 1 to ILOGIC/ISERDES2
DATAOUT2 => open, -- Output data 2 to ILOGIC/ISERDES2
IOCLK0 => rxioclk, -- High speed clock for calibration
IOCLK1 => '0', -- High speed clock for calibration
CLK => gclk, -- Fabric clock (GCLK) for control signals
CAL => cal_data_slave, -- Calibrate control signal
INC => inc_data, -- Increment counter
CE => ce_data(i) , -- Clock Enable
RST => rst_data, -- Reset delay line
BUSY => busys(i)) ; -- output signal indicating sync circuit has finished / calibration has finished
iserdes_m : ISERDES2 generic map (
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "MASTER", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_m(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => pd_edge(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+7),
Q3 => mdataout((8*i)+6),
Q2 => mdataout((8*i)+5),
Q1 => mdataout((8*i)+4),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => valid_data(i),
INCDEC => incdec_data(i),
SHIFTOUT => cascade(i));
iserdes_s : ISERDES2 generic map(
DATA_WIDTH => S, -- SERDES word width. This should match the setting is BUFPLL
DATA_RATE => "SDR", -- <SDR>, DDR
BITSLIP_ENABLE => TRUE, -- <FALSE>, TRUE
SERDES_MODE => "SLAVE", -- <DEFAULT>, MASTER, SLAVE
INTERFACE_TYPE => "RETIMED") -- NETWORKING, NETWORKING_PIPELINED, <RETIMED>
port map (
D => ddly_s(i),
CE0 => '1',
CLK0 => rxioclk,
CLK1 => '0',
IOCE => rxserdesstrobe,
RST => reset,
CLKDIV => gclk,
SHIFTIN => cascade(i),
BITSLIP => bitslip,
FABRICOUT => open,
Q4 => mdataout((8*i)+3),
Q3 => mdataout((8*i)+2),
Q2 => mdataout((8*i)+1),
Q1 => mdataout((8*i)+0),
DFB => open,
CFB0 => open,
CFB1 => open,
VALID => open,
INCDEC => open,
SHIFTOUT => pd_edge(i));
loop1 : for j in 7 downto (8-S) generate
data_out(((D*(j+S-8))+i)) <= mdataout((8*i)+j) ;
end generate ;
end generate ;
end arch_serdes_1_to_n_data_s8_se ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1590.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01590ent IS
END c08s11b00x00p03n01i01590ent;
ARCHITECTURE c08s11b00x00p03n01i01590arch OF c08s11b00x00p03n01i01590ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
exit K when i = 3;
end loop L;
assert FALSE
report "***FAILED TEST: c08s11b00x00p03n01i01590 - The exit label does not match the loop label"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01590arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1590.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01590ent IS
END c08s11b00x00p03n01i01590ent;
ARCHITECTURE c08s11b00x00p03n01i01590arch OF c08s11b00x00p03n01i01590ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
exit K when i = 3;
end loop L;
assert FALSE
report "***FAILED TEST: c08s11b00x00p03n01i01590 - The exit label does not match the loop label"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01590arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1590.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s11b00x00p03n01i01590ent IS
END c08s11b00x00p03n01i01590ent;
ARCHITECTURE c08s11b00x00p03n01i01590arch OF c08s11b00x00p03n01i01590ent IS
BEGIN
TESTING: PROCESS
BEGIN
L : for i in 1 to 10 loop
exit K when i = 3;
end loop L;
assert FALSE
report "***FAILED TEST: c08s11b00x00p03n01i01590 - The exit label does not match the loop label"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s11b00x00p03n01i01590arch;
|
--------------------------------------------------------------------------------
-- ion_wishbone_arbiter.vhdl -- Simple arbiter for ION refill ports.
--------------------------------------------------------------------------------
--
-- This is not a general purpose WB arbiter; it is meant to share a single
-- external memory interface between the two refill ports of the ION core,
-- data and code.
--
-- The data port is given priority: when a cycle is requested on the data port,
-- it will be given control as as soon as any ongoing cycle on the code
-- port is finished (as signalled by deassertion of the WB CYC signal).
-- The data port will lose control as soon as its cycle is over.
-- This scheme has no memory: the above is the only rule.
-- This works because both ports will have gaps between successive refills,
-- and because the ports are not going to lock each other: if the code bus
-- starved, the data cache would eventually stop issuing data cycles.
--
-- REFERENCES
-- [1] ion_design_notes.pdf -- ION project design notes.
--------------------------------------------------------------------------------
--
--------------------------------------------------------------------------------
-- This source file may be used and distributed without
-- restriction provided that this copyright statement is not
-- removed from the file and that any derivative work contains
-- the original copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.opencores.org/lgpl.shtml
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.ION_INTERFACES_PKG.all;
use work.ION_INTERNAL_PKG.all;
entity ION_WISHBONE_ARBITER is
port(
CLK_I : in std_logic;
RESET_I : in std_logic;
-- Connect to core code refill port.
CODE_MOSI_I : in t_wishbone_mosi;
CODE_MISO_O : out t_wishbone_miso;
-- Connect to core data refill port.
DATA_MOSI_I : in t_wishbone_mosi;
DATA_MISO_O : out t_wishbone_miso;
-- Connect to memory interface.
MEM_MOSI_0 : out t_wishbone_mosi;
MEM_MISO_I : in t_wishbone_miso
);
end;
architecture rtl of ION_WISHBONE_ARBITER is
signal data_port_selected : std_logic;
begin
----------------------------------------------------------------------------
-- Arbitration state machine.
-- Perhaps calling this a "state machine" is giving it too much credit
-- but the simplicity is intended.
-- We know there are going to be inactive gaps in both buses as cache hits
-- are served; we rely on those gaps to switch masters.
selection_register:
process(CLK_I)
begin
if CLK_I'event and CLK_I='1' then
if RESET_I='1' then
data_port_selected <= '0';
else
if data_port_selected = '0' then
-- Select data port as soon as there is a data cycle pending
-- AND the code port is inactive.
-- (So we won't break an ongoing CODE cycle.)
if DATA_MOSI_I.cyc = '1' and CODE_MOSI_I.cyc = '0' then
data_port_selected <= '1';
end if;
else
-- Deselect data port as soon as an ongoing data cycle ends.
-- (So we won't break an ongoing DATA cycle.)
if DATA_MOSI_I.cyc = '0' then
data_port_selected <= '0';
end if;
end if;
end if;
end if;
end process selection_register;
----------------------------------------------------------------------------
-- Bus multiplexors.
-- The memory MOSI is multiplexed according to the selected master port.
with data_port_selected select MEM_MOSI_0 <=
DATA_MOSI_I when '1',
CODE_MOSI_I when others;
-- The DATA master port MISO will be connected to the memory MISO as long
-- as it is selected, otherwise it is stalled.
with data_port_selected select DATA_MISO_O.ack <=
MEM_MISO_I.ack when '1',
'0' when others;
with data_port_selected select DATA_MISO_O.stall <=
MEM_MISO_I.stall when '1',
'1' when others;
DATA_MISO_O.dat <= MEM_MISO_I.dat;
-- The CODE master port MISO will be connected to the memory MISO as long
-- as it is selected, otherwise it is stalled.
with data_port_selected select CODE_MISO_O.ack <=
MEM_MISO_I.ack when '0',
'0' when others;
with data_port_selected select CODE_MISO_O.stall <=
MEM_MISO_I.stall when '0',
'1' when others;
CODE_MISO_O.dat <= MEM_MISO_I.dat;
end architecture rtl;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
laxJRyS5HJ4VjLZ6SLEhy6y9rQ97V9ETzBs2CD5dycdXfou6SvFxjArGYzf2pKG8QLwYO/GTNPcN
59ceFsge2w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MYhcnm6l+ijlIA57hrd5WmP9CgROtPL+YH2qO26oI5HJuu5S0+Y0XD1CE2G7pcp6MPAXHXWjU++d
ckWIg6QCgeqo8Od3EGyOdoiO3jUyQYycuSvkyk89ugG9zKpf4Cz6m2TodCYFkPhJLkeDKm2W8Z4a
9hihQe5dhXSrzJMRRWE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
vYuRQZCN/s5fjhYe9cBmFqfzc49DQUR+Te2EI/HfYRPptfOaAwtT/WcPVk1UJSJn67kTQMJhB5Jr
jJMsADd4UhLRK1PyefmIT7QwW9iXTLAiD41n71U5MqHOd8Y/kexzlnK5QHe9HHY1WcWijPKvfHIk
NC1cBDsfdCHnM3gJNed1pKbgGULZ4s/8TDrwdS8DcdjcV9KrQqwOPyqb8WBroG9hb5IZQwjlHmW3
sGaSPVowNj3ZOHbhKjY5vmTvSnA4EI9/CvX6pe+lGuT+IkxYdxQFtMSoK4PKJAKuIfXgPSBF1nuH
EbXxlSzkS1Hon+Gc+xV25zwNhDqWk6x2nzf76g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Wj0sJOL/jMfIMAmSR09ZI5R3Bq237dMI1g0IrYupz8bWHPmSQOX/OjEv+QdA96AeTtH+1FI1kE5z
40AVammBYc7JEO2n7RFCd/knT3/VOoo08bAb1mcmpl9Ow7FntGvrrJnOXhVUf/P+2yDNPy2VWH9m
Gr5+hOa1FJ9Ste+RGR4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mwrgqgpOMzzfdw9X05v9POtDXZmE219tS/ZkK+Dx62aBwxAC51Njfyr/RWAkUsNigl+yjtuP2LVF
vCgXwXupcuwS4z8EOSzv47XmaF+I62OLaWaiUDw/5266HGvDcQs1VAdxWkml/2lc4Vr6j6UZVGD4
Yl0vIgImA2+dkDxh8dM3a01BUf/TXyjhX7U6+lZIbALY0h9N1rhYzjm0NB2MiBES2LxT1W8p3q0f
Y5Npjv1d17w06SRq6q2+LMIfczXz3GAlplRW/L0vZIaodgEbwoIfjmvrR1PEHpG+f4E++XfC34jI
ph7+Iw18vX+UK1b4nMV0qUrCvMzAPGtccJ5EuA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15072)
`protect data_block
sfWcr4Jo4G7b5yd1sb0woknEGskdoD2IE7GyxxKBl7PnYLzmL2eVCOroWQfhdnxtf18e4trlDyax
0YAc8a+lMOxMP61YfUbn1+JHQxDiNlB7x5fP6IQE9BRUt1zhviFVsOY2jTgmKOq+txh7JbaLqI4/
LWCufZTfkCjqW2SqbXl66ns1Gzi2BxX+4YQtryU5LCeJrQdvqxFiutbZhTDQ7ci/9RGj3umkreBX
F/2sex9YAi728skXg7r+2iuFfFgFsrajHR9Q8DNVPH8rW3ner0Du6OwWrbgypDl4fcWy3FW0SYvI
bfi2AsVpbMKH6CR9fC09EAYkI6bSp5JNPN/4yLBNpXCMLrMXIS9BePgPtfO7OJmSz84AlpQ6Y744
KA2idKq1tNikyDhX9GwDY6dEQPkbVkbr1V7Wj3D0qRAbt+T8lSjA6zAwVrtqLCsw6WpsIY6l0vee
rbZhjI5WcrR/0/cUykPY5ECaR5Hjz5AJOPZkzEsOqaXSge5uqKyzXP7kSr2oaGjEX7nLKWp607HL
SPoQqZfn5LIdrIRUAh/YInD7CC2DqlqftXKryHej30Ra9Ep3H/jgLv5KGNFoDzUkowtF4UXdU1oj
miZ1QAleHBekKiWDOABKvYPKsbTcCQrbs5WJVrUKsuZbq0GtkZnzmAoUV+duOSVvNFHgyndU+cXt
6K7hfNFdNOyivAlzrqNnVnat6EZuLt5qDnid87hxeLoizfN4/N2v7crhxMisYbSHccIn/LXynLs6
D8eGnIy6OO0CQa41Ocj11+o9y/n8PWpdrwStP+n1P56KQMQlVajivnQgMUvY4xYF7zgKt8iGgR7J
Q56kJ8xLhpJBaNlRKmJDAWd5LtDhr/kDBgBQSnKmo5e6Taw6Gkda6LMOfYPMPgK1ykxP9ima8mh3
MYqeVeWBG3P/MHnlUIp/7D50dfhEqIuikgqS84kfwL/zTgvxmF5E8IREIgn2XIo0VyrvOY2qpzTx
eMm5/tdL1olEwhm7hXwyWn5tzfCksEPEpUfPjBaatM4dLIMGcXAwlQJDtP8FIpH94YB3VJTAqwZf
pndwhznkMhjaz7K2vgwBnBeweZkz/qmQ3q8zfcW23RgWGsETHVFP/Q29R1VdOQe19TeibeHHX5pj
cazSeExEwRzJ0m4AioBfDD4J5aBhdVK41Lbg1m0nagtR8pnyaGkYLxpSvVbvJ9HgV0p1Z9Z2l2PZ
6W8CFs6SS7Zr2eD3SWqVZYobxpeIHOIdqrParqqIILUoKmXLt7WFohabuhZHHefeoul+8L6FlSqQ
eyTttiTvwgz2W+nGXjQ3I+JA0qTlNLxGpu0veSRXaPTD3e+xBsXdzSXAcBzyGUyG76m9XUFBDMSV
V4Zil9hs/SYAcvKnvJQQDXsWb8YL3s4BY/insDPGzz2vG+dZmLCUe71F8VqQWtT5N8k3v1nOMnEH
BrOYwdlyiBtrTk7GQs696L3Q6WLMQQ8gyab//idL4KOTTkbOal81gWSq9fe9XaAFapuZEnOssSSe
5bVkwPOgR44m7hYgqtrB9I7nFbSb6bzPg3C3XaNTkKFhji8UGqv5Yupborl0UGgSMe2iXhDssuwg
n07X7eogNRV1zqBHokm64slW1sDn6RXmwzj4Z9FWMh/sqgjfelwiTZ2dsqI9k3WW77kh7kWS4cgZ
TNskAIUikF6MV0lpntybTWDTM0adxaOR4dHetPa3wF3ZNwF2p7fjjYDObi/Rs9l9FuZqLIgq76Ni
DB5e9GsP3+556Hc0oN5Ya3oRAauvYTdh4IbyBFdOIFz7eMaMPbKfa5clWNEPpmhFcX2dFh8tOz0l
xZI7fbZLNZ9Tvj5BGPngQScKnpNUr62VVUoLr5zVMBjZk+ol2rczctIIV5j/aYysCJPFimCdll6p
lVNgVkTjtyD2YvKLAd9z+FLzu4VxdfVj0TYm8Wb7Sw8ro83gIHeteSELf11By2mSC0lPyYv63GhD
YYR1veHGi1thNq+DM6GfXoQO2PGwK3G7HtQHEMFtYWvw8XdKxux2c7E2dXsmnCy8SD1hmsZ5Ow+P
QvZwVPSRP2tTAhoABFABWl9m6rkYJnOF9AQbu2hNSVwL22zpLaks+eR8P30xcs0/ssQRRTxIeHu5
/WeiPpOXuRYh2FPa2ik3/53R4l6/D9/7RrXXtVb/WNnrZuz2FASeUul8zy78Xx5REpkTqA4Mtjil
EiXcNcO3MKwVyfW0wsbI7UBv7tAJ2MyMV+VnEP4228avDmIp5/l9kOytFvTeJdBXG1O2vylvKcvv
NyBgx89iP9QpcG4BoAHe1LuayMWVq/RMXzaIk9IU1bF8CZhK7T56zqzAbDpm9sQfQPugXgnqiN6l
UgHx/CsXMIZjGX+CoTA7PYzrhgDzh5oHh9AwE8ZowmTdhj+ZURA5eo+BpHeKgB/7qQKbDz6Fm3fo
zMDBl6e9ft50mnFiC+kILC47KcWr+VjX1OscJabKOzc9itC1WVvhvBcUh0Z7RTGVOukdTaffmwKl
WXzyioGyYiCKp2oAj+fMYN33SM2k93nxCdyhpaZPMaB5tyPXdaEyLfhlMSpQBelN82oBMOnKxtI/
2f4ImhQMPYpllAaGXHGXtN6tIGEF+YsQqJ+KhM9d+M/jffJurFR5nZbl/v7E79oXNJrCehwyYvGS
EQcQkKckaVQwUeTy7xGyTBxdRAdS5q22R1RqDTU/jUVw0I4QaesQ6G4Ddwxs0u236RCIGEIiIEWl
saNUt9igLX8S7zp3Qxm01ZvQbuAW4oKQwUu8cBJJhuBLgqPC4E78trz7hJWp0t6MLYefnD5RWuFh
/deVmrt4ajcKMzTrBkvfO8jQcRUbF619lLhJts5YEn4j05kgUzHakQ6RxxgvNSe7SSLqmSN/RRLj
Q2jo6BzKrg3YNkWZIDmYpHypnAdSTM370iUM1az4i0E0xGbbcmHOSDchUbBIZdp/SfamNV9xiTCW
nmG81v/hROtiqacF1YWhU2PTfJv0RlwyCS2puZ6DJAanj16DKbbyv/HfoG8W32qFoEcbCPxpse6m
SIehFhDiD8s1J4a189mmJTIwhYb4Sa0qOwH1BUWpTB814FZ05Ayh1wkfVMOzC9yCo3/equ0enRdp
qSeBnV0ys0/aHii8VhN9qf5GGBSdPn7iw8diugoeFZBYFZeN458B3DUkUaXv6D/f7z4J06WVWV25
PpiF/85tJSf+HUzupemSSDJ4GRIIjJwISn5tyQWmv8WWfoxBzbqvKgkuadGnptSP3790H5+53YA4
TxhPkdxcdQeBY+TS6GpPmRHRYKpt39o91wHMfdf2mg4aWoJ2Wz7VySLsLrPuzeFn9M/pTK3uAlUH
vLOj7TSGJ9hzzPjhmg8Z304dia9tm7rJOymDK5YKk6ROfN+2+kZSagXgINEcj2Ix5CKHXhC45PtC
q9TSlXuTzTZIH0S2zpqnIZL9vsNMQDmnxYWue1mFLF0/xIBaHWAj0vYXQQ/DMg7sHP9vEq65LOGE
SWoL+fma3MISIXOe4x6cWZ6N8fRyQ43eR0VUqIvtcHp69VHuhcVDujZLNixH6DLwmaFAbhjvWnpJ
w8vqeMfAGrme/pDLe18w1HrzWDV4QDwu9dcYXYUDAYPzFv9/ngU0VNtyrSgMzXiIDUf1tIt7H/py
Z9HaboZy1vILevHiBXCw5I2+wirOU99WlcfvMVRk+u5NToTTMoJ4haAxCZ14nC7VUZEeUKMACuNI
hZCTwbIlVEAnr826Q4DKAwX1xrYnntElCR4wEq89MbINU7fXj+lpGGleuTbKCDh/YoOF4juH6lHN
ATK8UfvJuCEVdQD6RdRiEczYV4u0QUEM8Oa8pGfiYk+IQSKi9uyDTZena5KCHy/YudnCifLQEHQR
4bjy8qrz10QvXH50QdFlHKKodT1mOu4OYE4AyftoZXgZx4635F3N8MUleqjz+fq0yUbb/kMcelo1
Z071vElIXuImPlZyaq2cljBgCayFAhzdpDIerrC4uirkzWv3U+ZErw4apokGQUWH4DrB6hKuDTfR
iklHn04liA4U0A1SdntEPrJZQh0T04gMFb4+ZEqlTFtEyYSXY9j9QQGvhFL2Avpa6FT7JaZ+QTlG
BrXTUedkAMreTsJA1SPUqbYreV6D/zVrNPlRlv4ILdrtMbXwKDm5KSKnzuAun9F/jqfVz2cYR3VS
ttLDrsQsuNZ/eZ/sedZCUun+540uKdSJwwLobfORu4/d3+oztmonQevo3pVHCw7mekAoqKmsOJm4
mz/ZiEIr3KlevXmHtQmGXxawvLRASooPoj95POIAX7I8D7QqHcbsWsSPSeb7K5Qz5iqZvCXN1pL1
EPh5CcaGnso6Dw9Lyp42go6/hGl+jY0z+bGJGVNMzZSrCJ8lETQFySg0aEA8pChQ8QYCE5C9uhet
tKq526guRM/9C+VVEGH4CG1nSAK8t9k1W/1BYw2N2dtthW7UkCesUaZ4kUQxNLHhbr9V1cjyplt1
6hHAnKrSqZEhdDju59+sj5703/evB55hhT28kyOPaYEvlVFkvRBG7busmYrsIwSCCG4MjMyVhSf1
G+seBZNBF5RJ0w/69q5sEaQsjUq+HZYn+HoCcDR8lDj8X8gmrue7Kh31kcXybn9E5MeJs74LPYCn
ZLYT28hTFy9IbGWqmnatJR5ck5HoSRUUzTvqsXwYSYBu6em0uTISaFngyVu7r1DErVs2FMBVcW1W
aeLWFiM+KKreXjh7o/S4i8ZkhtkLvY/P+UWkOST0GjQoM/cuOM7jglbPO5hbKCWUPBJtjB4ey/rh
Dx5xlih2V6PDnNBeIZxYTv7oQaKBa8CHifHWpGMqkfnBSt8Y0BJVbyoxZu/fSRTVKOor1fsmhNu8
yzUYB7AuFYh5+EpmtDxWL36VdUUv2SVzl+rsz1O2j1GuQ+6N1b90t3yqOgWdlVts1EvKHcg3TU9W
HLxgoky7w66DCGAc7rC7Tz5TV5h58ihHfBcS2XY9llzgQDKodBsc9ntBhguP7Qg6AlclsauIMph5
S/9Ww3C8L30yNP/02ImOaNOSGyeI2QvIV5DlAUm96fR6Y9Ff0NmnQUplg8VJtOCKhVw8Jo0XslSI
B0STEzIocYl5MtLcLrLvt2FQ29LgDZHujZj0KGErCQn2zC+Fglbph/hbbdbzSoIPf3qYsyb9LbEL
zj2t7yOBEhBDYrstEhViPUpTKSTDastio1BVMT6HThwCHZHpFeYJKwUi4vhZCgdUCXh9Y9rrBhSo
vRLrWwP1++Xcsl0aVvvYZDLAficsK+oArHcvf07MI/16j47s9ar27GrJPq8O9T0n8n/aO6q3Wlza
kU2hfZ6Fohov7phmFRl8Pl14470iTTC6CvQnPGKe7E3ODjCj8C0hhpUzu5FsaaBn6XB+Asv7RitZ
Y1273AaiYkrgBBRdeGNaguDZzzGubRh013uwFKLvDMkUwIXfYNgUmFU1tiMK7eUT949eoML1va4b
gIDzhcDt2Fc2DYzJzteHr2kxibhfgF/YwJ2s6U6tA5OoFg1qFUzNSehhlnnpmbw3MvK5rC0HsbLO
3kiDeBZp6Qkuc688ZCWP8xJQce8I/JXChbadh9wqr4kIPaFyeIXKaEpuvJMWLQTstJ0E4l6jgVgA
CCCV56z4ybEJrmM169XM2gEkbV+zXtW1Ipf7QsLKNFIy6T5k061TWOxUOamwL0Gy+Pk07OIl5Uf0
FZMv1JQtrKYkJQ8RFFDO7gnbEVNwJjnDcWzkSAD4lJQ9IStaDljS16EkXDqHrvHTLuJWWlo6p16g
aSE2a+jw493eKiQJJ2PJXL4bke+utnbACqXgPWaWFamno3rHQEG7iqG5UYrmYCvaAqAKzFht9uFw
46E1k2zuccKYXU6o3yqwAYmET3Mlm+nWe/+SKL22XPOttaCeUtOPoulI9svKiDk+JQg7y1quMhVj
81VoLFE7GcDSmRgqS0DBxcvFr6rE+ia9YdrASkjKRLSUdrO+ztdYsRAACBN/lbmvXs0Wm8MJ9e7y
GSE0WgpqXJ9X9YJMWzlutuoHmvEUI90DoKe3PG0eiENYAMy06CoU0bKeKGoeo9AP9BEBa89vhk45
MhyDNZ4IwUbRFHO0dtf+mtNDTi16HAbZnU3IOJC5/iq5rCZRl49uteeUr8hd1J4jlwJ1EisShcgx
5XCzEj6Q74f6dFbPpE/AcJUqyeBYBNc7LRHiJu7w6Eti69H/o6zD4nDFfVyv2U3dGmwdWi0Npl2G
87ICmo8FJPpp8oJ8/ljqpSufsMz1WLNxCZGnKrnpxYVtn8k2Xtgy5X/bdbtkBZoDOGfRYhTl0TXC
Trlj+atGU6YgI8Ql3eUH5UEbuzR5WPHZCDRO/Y3uVtXQsnYHLdoNzQ1k0r9C4qMGoSsrutyR3E4R
RwWEHV8jmuYzBneCMewQF6NaS+UvRLEGEs2uL+Rr3aJMiO7wcCTe+jD4ULLXXVsH1j4Gv9YBPpJj
V1/irv2cEUMdqapXe1GOQ25J4YXgK94xxyIj2NuselIC7r4D2+RF6VSBb3s9wsbY4toamvRmHJYf
3v42Xf8ZOccxTMpxJTqw0ivqHmXes0wrxMQqgHY8odsJdoFI6TrB22CU0+saMKQJVunLAUegHZVg
aFJTN7Rkxk7+f6W2P6AJq65KUEnc2WaTGSRXUflhY1745yQPRQgDk0u1EROKDDNN74jpxbNRJ0st
6zl0nzppyKFCgwaKCqhHXMwJjTwu416KYxIGcqsEj1XvoLK571opJBKz8vQbXc4+t85skRRFlHBU
oDRqW1IVyxPbXEvMrz0Vqoqx11elyNLQMlLR0Y8cmxgKFtpKgtwquDDF23tPtQmivd74NZ/7qSOW
sF6XwvyKewwpaoHN5iLuoWYBOpjR/Qw5wDAXxFJaKpuianR4lGAlsB0zB6U8MyUcYU0NWFvdXg7n
sCUNKJ3Dt6xzd3yuI/gn7USbJwGJaY3hZYIb0CcMzOUT6L9F04Z/30V4tcNgZQ1MjLonQS+c9X5M
ekp49X0yn9W3A3jvqimtNrzi1BMGHFz/A0OzGyv4Agzw6STxi8FEo7+mRreJ5Vm3/Y3LSIsXIzbV
EFMeM2qDl683gH0o/Gu/y7FrCa1DKOE6fZn68GcmLOBpHll6iHldn/35sIU58L7on4FCc6DD+BoX
EBhvCkxko+k4atDI/EEIE6SVoywl+bDHyF7BzCui2HzgF48DjWCPwUvpAk3CMPLoDlIPX5ANKYqR
pt3gBk89p4NxWCFWQvJfDE/2+pjfk80CvXJ6SOQyOpmCjGZ4cOhP8KZi634ciXIn/MegbyQvQRVi
6Z/mqqP5j37Ymm7sGJJZ7WSvHAru/GoV8VfDb190FxVT17SdkiGjDYs0nFcX1JxzDXDtoxY/Hxzk
LXnR5v18+XQO3OX0yOCdniSSr2yoPqfIqr8apNl7mNE3nFMP1VKc+s/iRIIQNiIsxYBlh/MegnYH
Pv/vpswrukAPiFKILyHHS0kHaGKtHvVpzrIfktoVVw5E+l5/AR0cK59eYIB+YV1e1buP144rPME5
nVK7x4rksbuV1zBAn8wgETCPjJuH3T+f9nmCftE0Y13w9neNs+oBHzJ7GWd/ayqVUjCNl96cira1
U3kVC8VzYAdneSHuAr5oQPeC1r+jbEzqZxzs4bdub86hz5sg8ihs3gHUnjQ1x0UpwKgGGonXO3O1
gjRtFg5z/ecOu8k2UTsjxRnJ65qZyf1im9IrrwEbuaaf9D1Y8QJ+ojGBNft/mmu8pkQqNm8TXzjm
h1iB1NRWlc7ccP1m4Baxa6KizK160WtF0VbGICSsWAsreP7l9H+CrDYZ1g2rqmdyV1j8zdpeZI8c
WT/5W/IpM5bA/z+mHixGAN1Mz+ymMFJNJ/Sc9CuhRq0b81eKzhGFn6dDMoimElytjuHtiA5vbehY
puTGFrEtQwDuVAUtQl1AyGFBjiSM74BV49H/2i5NaMIq7d82seWtInivTB7f36HZu2iFa6WUzJgI
FMlDzQwQqu2TYsajE2vUCbklMd324kohMGbcwn9fT4krT2WdZrk4rrOuMxuWW8/4YM60sns8HdrK
l6KZkpEwShkwq3ftpGTP9zImsDDfrpSjSRr76l6k9nfyIV/sq9muB7vdUbxmNtpSygExaOWUV8B7
Nw5YZ9mETNpoKoLCVyXhjiFaPi+TjiJbYeh0OGdBgp+S2G+x5X3DoptE4mmi4s1KnNjqg6GDDtxV
TJqzfNBfrJd1S0xH3rz1T1H0idXGmAZyl0NaxjGA59+8FbCbR5nHM9RvQ81z7iDsY/DgwzoBf5OT
OtUnwd9F2uyG0PtbROsnIN00qlVnbvBRY1Y/8cYCkeHMWGKJ+Pxt97FXhHHb9944xtJzNJD2wWVG
iBdIi77rBk+ir0nB8fxTrUkYq0T8AfrRfzClwhzHPYa3PTtU86gMY/hKzImWbZK1vwyHnxXzsNJ7
zaEbc5bew3Lt3HW0QtnGbXImluCYLOquxtupQRomxe2Wm35X32YtkKWtBscNE2IomYU5X6brBUCJ
UVJgHBN7cL9HQAKcX9KzBzpsWYrPOH694LKqV2mjIpdws2RoEU6InW8fl7lYnDztPhyiNDv9P0Nj
IAwgmiLiGGEhdGDMd72o/O7J0u208bHSHkJc0BELG8qm3/cg/titL/YTh8aZ8G5F+LeSZcv0Z/7Z
YLUSQLzEdU1aCu7Fg6f/p5Lj9LM06WGUikJxjlbpNN3ZK2mr4rPWXRa04YL/g2iBY6se0BiwTPyZ
wEinv+/f35BCgHzGA9aRv1FD9A20nqrtvr76hHPqfMmFrOlQonwiA4u/56y476BSAOuMFK6bTWgb
luOne0ETG1ywmkk+fTcWQmE74Yk5Bt+HeuIHY2h5HcE86Yak6BVS+/uSIJfYbQdu/u0xvOVmxghm
6CIrdnhzikewWK7FSPD4UGRyQONU33FprEj3A2+OkNxt7nPXMU1djoW9x1/8YNDl5ujnzQRBt97W
uPhrAvSewOFLJ9ApmcpWruDg2zvbPEjhB0DUsx8bb5/Dr1xWCJ/Dr+GUTqR8a3oJSbQzq9nC7aet
ErT/rD7R5S3KgpAXaCsrJgp4bla2Ixl9mWn0/Efltfd7L1PR6NT36DO9tWS29cpPVfzH+DR6Xb98
Q2AsCrFfqRHOxb+0rKKTPvI4U2RJVMH4lCyvcaje7rX9ZiE8cLJ5rFDYk5yPrvjWhNduu9BlAzpW
23pguDTNpK8b0/GaNPQRDQLaC6ARr7cVGtFTtlWzRF8Yr4U05Efib/oiNA7V3v5T6YAXBMJ815rv
5yghZnYWKqtqCjgxb2wWr/bn/zp0JMjNxkqry3l9zGenNJ80n5TE8mCyHC1gpcyr2yFLtq65QvHn
EijS/7y5St/mswgX1iwcLLrIoZyCisVqqS0OaFC64BrJU23e4NegEgxqc0tEdJOIoGBBCks8qgul
ByEjlQQX6ArrPdbs03ufmI1Jd584HWuhzNhomgWDSteNdZn0AQd/WcySKZP+AEH+DMxXiRUEH0Lc
nFqYjN7Mydsmj9YcOhcnAO0oHZRjWIhEgmtf3X9doG68v2g9RZXOYwFR/Mw6DUFJzh+O85DiKCrX
hWjCtL5HNuCmVkkmYhagOHyw7UWKt6knVjDhpG6GDkG3DGgHZgIU1cXB701+iHwB/BjP2Q1gToyn
fwd0Aqtif9SY07FwaiC8ojmFzxAnKBR8+Mw6AdbQxvZxRS/xirqIqQgUDCfTOh5MGnL/XybzSUsN
euH7jXl5Y7do9xlSYrViXN2t9Mb6xugxtkeEK8HNavvj9oQrXmeyxMQXKX8bXE9swsBcBjg3Wi+H
JT4Qm+R7hILu0YoVHMpDd/bjZSZR5Xnl+CYiK8o5mYWzLfu+F9QkmJmmg0rQKL3Y23HPkUExerQG
pDLe/tyqjgZFcTz0XfFbqg33RjeiW/IJjE6QDav0cR3dmtGB3Fm+LOX1BGzRvgF+Qs76ZlMowWGt
S+pSt+C8vfOAzcOVKkPoBwrB77GWSRa+TXM4GCgxKkkWZYE+emXyhlyzt7D/xIfUb5/5okwc++YY
G2ekmzy7oaQNxyonWFgRmEhxrSIv/6d8wSvLlipieA19uxBQQFxKtGxzr12GDvxbdnxzr738yZxM
yk5XsxH4YcgeTR/iIQnSl7mzaHDZqvncd2pQPuyrKs/TuSC07NSgYfAGn8F+EfMifN4kFrkO9hdU
CkWmk+4pGSMOuMU1/ItkKsm7n3VJb1hD2TvEcwEuaZk/PYX6IbQhEZbEHVcEJqkAx5pNEltQrjSB
p1SizI2a9GTcYny0egyD8ifcZJl1NpggC0Oes6AhDqM0n2YCOqw9ZVtMP8A329Yy77prXEmSZAQ3
ib5qmoTRoB88TJBT67ejhaSi9/JOCfNtbbY9oaOPlqBPJbExm9FznYvclhNbgKm7gg74PBzplrAV
xuYGep4+apeW/1zOM6Scx8JG97pzV2J5yKtCLY3gy5NOGykksisy6A66zdELdLDo/mKeoolzcSQm
TP68EBssuiqdZJM58afZHAi9Ab0E8InJbQVqIJge14x1j/YfbZ0aBZHI4lq+OQUZ8UA5Qy7lngZS
KdHGpYLD1vUJqPIFTEwzPSpiJyLF1NJvcQVg4ThKKkwOCCgqqmQQwJWSa+FN83Z68UoqxGdYj9sh
+8SObkLPFrfpqR8iwMkSiCCwSnO77DkhAX2sLC7dkG8GebUl63lwnbDUpYR5dB2R3MUg6FFquapy
4UBmfkVEQT4KkE5VL71+LRwljxp5a8PRncJRTnB+SmntbEqGx6oB7OMp5bWtNE29fZsAS0fxpvwe
WnD11dWaSuk8U/j1HO0cZGlGhMErlRI/yfAjDqqwrRwjBdVhyk+Ycq8EvQV5aOe/LbLOL6udAnHX
Uf74zydM7Sqas3ld3dTaAbXJcuCZfunqX4AHSowYVm/Pbd6CijYgWW54t4FkWNsc5G+HnZFTSrxv
67Vsalouak2eC1549gvqXd3fh0y+Yq6nlT2DJC7MxLiP7L7ZIcASkoIYZHzpXpdUChl9xdDoA1Zy
aTXz/Z3jnwyA2YJRLppvDllXmXGKGsl8YPV0M0pzmUMTUECiclx+ideJYBPBck65Wv5RrI1pkHGz
roPaQ74LsJKo3wZUVkP3Z+urvdQHcMyb9vxVhV48g0/u3SlPLNnUVORFvkCf07i9TIOWDUn1QFDE
Ghpp9Zgqrz3DHGs+9Hvd+8Iyn5Sdypwhqz9rMBtffjZXu2Is3bjOQeQ19n5DD4MuL6jUkUm21CuO
FDFpZ9VQTmV4Y9d09dPzkzRynxEr+bR+YuwqQ/R9glB+d7EvwJNic6EMXdaJwpcKBF9bZ8UsCBVd
bTeGEQqgAkVYlKV3nuQcjOR3PELXOeOZnpBHmFZETZogiZ+9l2KXfAWzD8+zBCO1P/hyfWrLW3YD
dYGJOE/Sj2gZMJmH9pyyBVy37qbe9LuW/kshnIzsiudPSb9+wpgJlVPmh3gGQWrCY4ez9eRKIV+G
IVX14sFV4t7/ov+uzP13zbwXk8+2LnA0MCZxbg1LO27IGX2KtqeetyBv9+iS3sYYz1hZikos1IxP
wBuuXBvfMk8HZczddpLc3ODQj4rW8Si/572OgxjmcDRvDoCWqq5YO4i5qUG7WvuAkBDuub13Q0q7
8TRTRQ2pd5AoWSXAKSC+O+t2m0qpf1Rvw57QJ+Ztlp34tnIbeDnjngbhrwcFAc1JJU6oYVD+YpFf
luilFod0kKk7x8aSNViEtkcD3fdf8N1sveNtXQPAykJ0AW5PTnmiL+1GEJfX1krCVHQBkgD/11H1
rVjubn51f+qZXfKcMpmBBBqq0yNf0acKhtsT56RjkuZ5h1iv969hsl07OCegPn2zCCyi6r06SqOX
JrjeqxhdpE6ibUZ6It2laHR9ElUol7XSQyei86g+gOVK4aRXerUqN/MYKK9Om8sXaZke8IkYI0/V
pvBc8r6rDk5bWTJraC32pn8yzH5mO56oAHC6rQntAttdgqK9NsLqJriQo1vMDSD1kcFIv5kNJZFf
WcuV9cf8fVYk+0veS7mgf47JDpMrl/rn4i8nA/kPM26JHcC5W0dsmcG9x2JPSaVzXrYWZZvkZVrq
0beVSm+jQY8RXU5f/CvePlNCuByA2zV529jGDUkeqQzKV1MR6OytoMFUTWJP/9t2WLoPDgAoRgKQ
9WE3wbUkiG3SNj8JILiAse6wF3hZ3fgsqHCyGQyh25M57vAAAa50FP62TtMCX+tQVk/tfrvTur0q
cjRsEZLXzY5I6vOF+/mP9Tea/GyHQI8mBllCu7pUzKDiQAcjjjPfqWwOIG+5Ouqyc6y5O+JQfVEA
Vr6jR9DU8gttY5mDCkHtZCb6KMn/my/uw1ab29BX6Yypyy7j+G3gSOBUJjPpZcZ0KVGh9yAhv67R
Bhx2bHa6iIbQT6G1ZUUvQIIkXE+x3bIU6KnaWbZgjEJ7cMDhzHq4MwlwQraHFAZGde47ZWo08ama
8b8fxc39NggALDMLgZVAUzbsAKCN8Nx9MHA7Yl4iPCvRjfHUeOX4eRy+P3GgWV/4DH4OcStdxJZk
8zGkIJiBV6TGDLrifWVDN83RsLnTkjWwEkEIZtre3Mc0mj18bzGAu4AT5FBDjUMC78U4wIhjSZAC
X1jiDfsld4EcfsimsbaxbkGL6IpH0et8QBMGQNz3gvPE/XjiD9NvjHJ6DWOHyuk0LiMWKZNlU/IH
uPMFpAK+8hbCoAE0Fd8R3GFtQbNkpp+F/ldF15TifSl9SYiuNZ3sV5ZAxVV8LB5OAYkAv9azDnYI
byvTBd+pyIaWkDCxNgET7R1tyvTYuNGwF9Hw5blXMHOQn/IUsi1I8QHzQwmgsr4mGbaa51DKe9db
e9mCHcZAzLkJIoCvDy6JDmGOYX9UUyVJvF/rhgX4ThTUOVGd0LSrews5T0qZisriQooedux82iM6
Q243PsX8PUH4EsM9IwL/kI4N4t0O3rPTYxoCs3JZaeR0BgbOa9Dz29Uxlaj8ZWqTdmRbz71d4DHz
NLgPfdQo8W2Lugn9htF0wol0qDn9Z8szO/QaGAynAlYzr2h4l5zxAaLsC8ET0Naar/+9f9fHz1M6
1jrJBU81M7XBrrIO3rbQktK2d4ZURdLyGh5Vt0Wp+KKv5zAeDAl6E5U+UQJdz+06usEppAjQ7B46
0lwmW12++Lq21TsIiHAawvzXija2mWJ7XRK3Fef/9dj+pRJDYsg6WTSVaGa1sggQl98fTllQkTev
8s3BWhpeDYuBHqueyW1sVa93umcm5c9s5iV919neibg1wes7zXEQPbklMB7S+ME7eS452yFiaRLU
EcyyiNTvRtVHIV2Bi5VrLNdg0B/j4sg1v4BMcrbTYKV8/oRNc73V7C5VCyb+SM3q6BqBXjlyLpar
TykpywUo1/otewrOykPNvU05ckAWLufiAL+3hOnJP2kdh6UND9nXGyd3i8gNjQ6uyl8TtNLtfIUV
UfrXPKRXRIQw8eeDpI2fN+BE0NUNJQMQU8RWuviEVHPJHNVR2oTW+to8Y6zvYWX7YME6oI0jCQj0
rXLN3Yfyrn4S3pGrnM7+hg+Q1B9e64eo3Kwdt+UBHHlUQN+U6GEFjX6LF5C3Zqrty9jknM4VaUtL
mkk1SKLLGJd6p1mQT2mqU61c1Geq0RuNAJVjG2HYJ4j8RbpKmOQeGd6t/W8nGHjNbv36+QeY0dT4
u2MNl6xseNxZVSmxbZgXNrCjWyFlBg6CGxySSmyGJOgMjY6pcLB/AH4D9ixuhLNrjlZk21L2Nv24
JiZLdh2AAb8E4AKNvQTyQHM1TlFz2Ur2bJoyY1R03WnzSFdxc0dYnXkFU8fnI17e2kU1odPRNBGx
M8lRO8sszjyX6GHSjdAmRqe3TjvkfHqpXHhCPOdBK0LVqw/gz+N83LPKbZ6TcqKapSVhNGmpCNO4
Xe6QHJ/24ZxZWNzC/TL857pLaM115fjuTxOT5IcsqPBndzNDvTK+vG1rRNtqo6iYXy8mrSxn328F
gZzSufqu+buNDfmiuQdllarfqEdykgRxw35AZQpK86pKP8LyEbAy5vsUKhcSp6n11dJ4sYmRKm6x
uLB8HRuThTx88J1NSv4uH47RNdSeX4WsiFM0dgcZ+WJ60nJqZPbQRDVgh1Td/SItxRjVnY95ryEz
HncahAkBhoWDfkM/3/e2twndZmP0F6JcgaFxEhjJ2qdhsSjaRChNh7+cXj5WuDy8RdLXhcN2ERmV
uHw4EX/HKOVi16aAfsNlXTrlyO3k6VSAeCi7czlixYk28kj+M2Hu03bbEQ/hO7rhQSUrsWJsW5e3
fV1sJxhfNnzr0k6E42RA9z/0XDmfzr8PnXo7jUsYvgPAhhSg9sHrGhVt6ot5H9/uZHjoSscKRkBE
aj0PQ4aLOQ/g36A++GVQkjt7WYAFLs1tUsEaO0+jBRo6WpmKKrgnckMSBuOsbIoT7a782LlpJF43
HFA4EMOAiPKI1mQVXeO7J4Gzhj9tA6IoAjs+nKq9psEBgLsgipuEuoNPJSu/UQwzWxRTVwhyU7Jo
Wxvy7DBIYL2fb2052APLTqx+JSYks3VpPs+Cz1tJ+zz2sZ+mt3ikbgZwZv8eP9QV8qSw03AaJMBC
9uW2l0F7JU0GENd7Ho6LrwR3kBhAg9dMwLvgPom3xM///6ZCleTxsfcIrzhMDtRiWYZceXksmIH2
Kowc+19FZxDPvzFqopg7hg6c/kwAkSZuagjJ1mdkYa6/+EtsvXm4o8mUrjEoBYekN5SXgLvqQDMr
SiRCCNI0gKKHkHG1gBDri1htluv2cO82joLu0YTg5HW4nq4nwAfdXgsVbGTk+JNSpnUfk1wxXFfc
cLF4opg3vLutPAmLS3lbZdHjTooDoDUaFeqlPy5cEgEFVKn8xNo6j1+pia/fOC9cLcdtYFhBncZo
PG0mTgLynIHKl5hin+JuDYyslvtKkbIr0Tt89XVgjK4hsGfUfsDivkZ+EBrqr7y9mox+iXPyyX17
vU5Ek897yEFJf/fj/Iv1A5uRp4UoSFF0eoDdhpxt9EErbDdA29P2nuc58CxbT+kk27cKro2THCjJ
W15/6LAFP8YEm34H9QpmADEt33LQM0EcsWLnRsrwsmjL/kj83IrY4oC2/pjRWm6Bg+LOR8TfmbyN
hZ3NSBKG3dY6uGtVCEcLSbrKhg4PnQAwZ1tRFhsE5eWsVyPOGzHPVFo97zMFCAyYf8rD9zhgN55G
XiGp6JgwUJGTha+EM6iyPiqgvY0BwEC/maxzSsWLeRDy5mD5PFO0XbVRRBR3wrL8al+TCJXqVMXq
+dyqzEuaoL5z9bsO28yiuPA+rGgwNQrQBq0pgMKXZo9AEw8+Rbq7dAC15WAqL0bFjFYUj0Vb3z3A
QU4gHdNZQvfxf8dgAiMngMnX4+Ayxzb2j2/PxZiIDKStMSA9q1ESOMUnO18UbRbIWoM8wsuqHlDh
3STk96E3Imy8Vp3rl/HdnYn9rrJwFE6CqNRWxsuWaAVt3f9wz9nwlOuRR+ooLFJ7TWWHivbSll8w
Enyo/cJKperhZkHwSTHkuP2iyS9b3HujF2G/LsCQ+wrg2wmFfmkhlLJgL0now+j7tQr3cijgQoZ+
v4un1E0rz4tIur3EfByZQlMrXeYa3ZQAUBUW3IGFpyqj5FJenyq4gWrlT2jAAz68vnW1IJQ3K9Xa
Cwm2FyXbP+HZ6d2WC1n5YBJzS/6OIHpw3uZYcNwk4ldTzZdr5gw03vAHlPTNotycCnIvuQZb+qSZ
pA8Q4A9cNe2JzDJotLxtSZASco6ydjrcXPoUEm+DyUOD/uLDwvWbf/yK8U4owukN5lbFIFNGl3eo
D7Dd4GJKpdjcpzJi15zspWAAGxlVxc5hn/GlMUhzlWyGAe/P7bAsUcZaLxNV57qhJZVczD7rk6mC
KT8OQPU9M7ZL10CStWdAgQlFt1eZ82qOAcyOs+yMc81rnWu7MvhjcTBOqGuIQnwVJjZaasczXvYr
Ze9pKf5w9UnL6C3mzIezSWHBc6i9++DHvzOvxVvJvCIwowCWoB+qvK3vkoaUQL+2LuxCd/PWF1+8
5eTUH7JP13vtQxsgl4vRRH+U5QYkTu9Iv67HR8NF1LW7cLYp8/siy+k8jlUkrC53g6vZN196PUu3
um5HRF0kO1BPcdLTYeHulQV3UkDCqexPdS8BUa2csbEqXnS7qUCxAEt8k38RDV3J6OUvLWVSSfad
njqnz7Rt8TMGfsh/3vZGnhTsfRKqszdP3YcdcX61UATHe8OWxzDW5oUDGHnPVUZEdAoaSqW87HxU
1yA/6Yl5IEpFNE8v7f5Mt3Ed1w7yvg81mtuMwLu/XreLf5Wup2sM07Wm5eJZBwm/QKLLCpQ9Ys7K
z1Vg9czw1xFs9S+iyyN+5HtbUt7zmu9Bjc7Bw3G47NBzGa/Y95MzWsvKNibaFsLCjh63AXvlUekw
DcrBNAC4DaP+Kksc7PWgM8lZBwCX5XHvfCPA0s29s4+4etsSF/t1tnOKkbi38TUX/HzKwtE6E9yz
e2kVYumRcs3RzHVxRIPzaBTTrhbAZwjm2KbaaLOH61u249vFseJyMQxpQXvJiqHSvq6h2YllYd7X
FzLo0ce8DW2AZe/pq+qtD5Y/jF1uyPzEX2s70aGJ1+Qvk8DNNfaTtRN7QwXZ5IqAYSmp+E/aEfMB
tQ34ATyP9g0tuWkF4GjQP+kzS0OjktOai8zd5SWyI9j25XpQ0EbBeJIWiTsXLQU0BROgr/vl1ERe
BqB7njsPTy64Z5PmHOXj5hxbqA6GiMsdV85MIP7xiariYnGfCZaG2QeXTxaR/P5kVdvl4EuGOhOO
uK6o51IjHW+wWxLAB2rzGk8XXd4nq7zyPZNA9pXW+uEgrQlxLkxMCRddYNwhrm9WXuP9h/NXLNuP
8AJ0f2SOLqbhEGJrHTc45WLUxekBE58AayfsJz/w6BWqfJg7LgDrl+j2wzFIqsIgtzO+zJmqUTXW
vKl+ZOTRRBCI1TQj9WYmAGlsvX6yIVbkOB0i5gxWRdkszNzk2y83oJ/LrIDvR7o1Fm/XzzDkJUIf
zjy7PoAXj7vZqc73mx0skCNp7Fl6qtadPDG3UUS55uaFQdU895Lm5FbJe3anid0unDOJTwN5JleK
D0V5t4jx5t7oeJd1zFqHHFlmBWnGCrwGap2trMN0ZFIzQINnMdQHrajjVDWFE+cRvca5mVrmPWi/
DZaOwr39VyUj3t1XrB0POB/+ybcL5nugYLpjOCSrr1vuGdi3bAJli1jqoEBymWqWkmlxr7AIPrOm
f5dpgpXLO5zx6Zta2bH7Bo2CF6y6hXyOlyaqsyPR53GvpIOht86TuLuRDf/vmqsx7jZusu4OdIZd
nYTSeKo0AeexqM5xfFYhD7END+uxi9KxZSc45VMGP0oaNyJO7WylaU7uDIw+HcbBE1V+5ByFVg+M
vhEmYI3geQAqzFMyrXuqvbQ/fWHjrZl1wOY8Q9+e2zvilqNZH7OqFyEG1movG4WsOf+Lffxo4Jhw
W110fdYlH+doSKWtXtHIyms8fHOeNeQHn/NZrZQZr3YY5Q7Ru9kgIFDKvqBBdxBw2fGrxJyJeVVa
jIh/5yq5PEQcBzLlj0p90vum0ldesA8IQrBJslAEchiiIdb3sF3hZ4T7faSX/qBaB2fBO6ikrMdx
kpGvjWjYShaeTruKtbfUK83Sf+Q2ZcyvXUiI2fFyNoY93zPyNTEBPjF71pwPgjmGi2xMW/Q8AUb4
RO+NTJZR8YEzNGO2wU5t/i91LetMSgNCzODExTfBxx5Z8EjDrabmTE1I5G96AgKv4uls0PqGKDtA
lux1GNIIJSHE6yk+pw7ZDnBRAfzroPpZD8joes3WJPTsiNWGlH0+Mnu/bPypi/66U4h3RBMjM0Li
YSSk1BLv4xsuHXR0eo2G5XEwnWfO1Wi5zTQUYiZaKCAZ9vecEHqHeFWln5xPa72RS9vi2r3fmUPP
3lkd084pdxWaTcAmf6pLTeINeLrxCQPhLljS0pQewBPkSk19dAA9jTicoDStQ3pZJj0Uc9HflLPx
mXdrnQbRg3mc45hqajtrQRRS5/nIlDDiKPUc8sZT0SsWE0+Lb+lKyAsGGzKypWGXxUjH9K5egQCB
k5WQyskYNI+UHDWIACCK2wYIYm0ICIBEf9URZW90CQyOuCpS2AbQwRqx6s7515txbCtnpEiTrMvX
XqH2ds0inETlVduYs9STPLAOnzhXax9AMJF9MusTVswIfhWdnRJW7vva4gMhAarrn3Zi3sjK3Cv6
bJQquMFg8vs8nLyPHp2zKvW9b7rVA1HU407Fx9lFkxiU9g1+4BfrRwGrmJ95Cj2alCtk8vFsQQFt
LndnhPJhQA19qk22bucWwriPeIR6kCnmL5XNyA2+VYofdewsMzE409r8ocyNwVRVk54abXahhM9K
vk+LrAX5ZQyXGtwt4x3/rf6L4LW7Zx8SJY8QsBGtKopV2faJbKRMuMCVaKHjhYw2hUJyiwZyldBz
93D1pxrx+T+tP2UrBrXq7qgtq24puuispTUL+XjaubpmFRSKr7SoCIXQFv+zCmIQNxIyYV4xLDCe
srVpyfyAhOuFwVKKggRa3EIw2KUWd8+HfTK+r5qqWHHjTHAiULG+71FOiaWQGgwn+w5MtPl1s/Yu
LifQasSFI1xWmrtmpD+15ZwNBk9+vXkPycKQrGeEvvQEd7thIbQ2t7wEw9WE7X8P2y3iKUoc+u3X
ALFLW2EFXFYajJF/bcKJui5caWPxRcgFyXMZoTOKQBpfh+7FOJ6x79G6DLNjlJsZFNeqkStqwfAR
naSZmsifbqTssUfgtkdvTsEHyHrzOWIjEVSaCA8Bc9drNH6qA4b+rv+hUWpjJ11jOJiQU2IIEj4R
kJEUbfoKGnkHjnyMQ/khQn57Pk8et+Cb+nGxZI1AmUjL/krXpo+3dp3EHgD+8CcGEL2b2UkqnkoE
otbNVWQyJu/noK0LCDp1q+FsDII7Y7h6PejAo63SRO6oIty6XApsFMiJQ6+Z/fdsNZ7Ksnn6sm/j
YG1rfANuFkTCA1JDhLVADNu3GpjO96j3hCQv8TC/TiCTSHmjDil/KPK6fHxLJYGy22KkL1gqtCxH
3B4yr2U71+/Uc3HZtns+c1ar2eA5czdzlfqkm2ndVmB/ReWDAep6vzfeQI6kjQfVsKaQSHAafbAX
kahc6AeP3bwzHh7z2ki/ql+yzD3DBAVrj5AxEvS/yo/Q+FspIBDMJxDQMDZduXFEGJ4lI8JAaXK2
J7+baieUSCgudeDcMHZld/+MXQhxXU21o35n/PH64PQioEnDGKVqbPsFEgvecbe4RkPmxYLk3hJ9
jdA8/3bf7Hs7w7iHP33oxzE+Uw8/6uAkwWc3dfG0Fhiu07aXxKDklyA5Oilr4ekN2G1b98tXAymX
1eSoYQBJ1zGNsbFtf8U61QqMmG8zAu38kgjK72MOEH/kyTOv1b5B+lz2vXZVNguEIKXK8KZmLAN+
oPdZKuPLuHLfnSmoJd+2MaMHODJFImVldE/IaR2Pka86FGB/1vXDLZyO9bFMx/GdKj0X30hrdH4F
nwvFPJjjhNfz5Qvcn6IfGavbwUhG6Rucl56Kf1YfQ1lQ2ayVEbZxNM7DQ2hUT/tHKybdJtt+Uvu7
5tUtRnFpti/KD+MWmH3Y3O15EGDQ63e+74y5SiAoqHTJ0vVNoj8g4agegoXG/SFCgZ7f4w6/mAJR
mXwHhUkxUX+yodF9erOEazoMGJqzDhPeyRKVb7/uSdH/Uf5CVWL6D181sSZ1R3bs2L0BPvW2u2/7
Uma7vZnk3GGS8Aah6tlPndkIjNFo6hU5+2VmOJiPxuSVi8lIHuHRRG5Xk+y82cMHXaL+kqyfJW8c
6ry1zIZIDXS954b1OixiBLjZbopAd0ILdn5eLX7YrVpBoyc38iVZqJSxmWxaKgrws91MWGhFVvM7
+kHdSxbTyC7EzvkcTm+LFC7Ny+89qtFA0GeAdQoAjUfFfGsEU+1yeUA4YXn5PzVR/1WX2GSilwg5
o+cKk8v7hvfMCVk28d7JHTvHC4fSRWHmEyePnPLcxs4QytkTz6p5/K3JXy4sSGrYhET5KJsQmg+a
bUtgCJLmzigsX7duYydEo4eXQdwQaped
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
laxJRyS5HJ4VjLZ6SLEhy6y9rQ97V9ETzBs2CD5dycdXfou6SvFxjArGYzf2pKG8QLwYO/GTNPcN
59ceFsge2w==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MYhcnm6l+ijlIA57hrd5WmP9CgROtPL+YH2qO26oI5HJuu5S0+Y0XD1CE2G7pcp6MPAXHXWjU++d
ckWIg6QCgeqo8Od3EGyOdoiO3jUyQYycuSvkyk89ugG9zKpf4Cz6m2TodCYFkPhJLkeDKm2W8Z4a
9hihQe5dhXSrzJMRRWE=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
vYuRQZCN/s5fjhYe9cBmFqfzc49DQUR+Te2EI/HfYRPptfOaAwtT/WcPVk1UJSJn67kTQMJhB5Jr
jJMsADd4UhLRK1PyefmIT7QwW9iXTLAiD41n71U5MqHOd8Y/kexzlnK5QHe9HHY1WcWijPKvfHIk
NC1cBDsfdCHnM3gJNed1pKbgGULZ4s/8TDrwdS8DcdjcV9KrQqwOPyqb8WBroG9hb5IZQwjlHmW3
sGaSPVowNj3ZOHbhKjY5vmTvSnA4EI9/CvX6pe+lGuT+IkxYdxQFtMSoK4PKJAKuIfXgPSBF1nuH
EbXxlSzkS1Hon+Gc+xV25zwNhDqWk6x2nzf76g==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
Wj0sJOL/jMfIMAmSR09ZI5R3Bq237dMI1g0IrYupz8bWHPmSQOX/OjEv+QdA96AeTtH+1FI1kE5z
40AVammBYc7JEO2n7RFCd/knT3/VOoo08bAb1mcmpl9Ow7FntGvrrJnOXhVUf/P+2yDNPy2VWH9m
Gr5+hOa1FJ9Ste+RGR4=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
mwrgqgpOMzzfdw9X05v9POtDXZmE219tS/ZkK+Dx62aBwxAC51Njfyr/RWAkUsNigl+yjtuP2LVF
vCgXwXupcuwS4z8EOSzv47XmaF+I62OLaWaiUDw/5266HGvDcQs1VAdxWkml/2lc4Vr6j6UZVGD4
Yl0vIgImA2+dkDxh8dM3a01BUf/TXyjhX7U6+lZIbALY0h9N1rhYzjm0NB2MiBES2LxT1W8p3q0f
Y5Npjv1d17w06SRq6q2+LMIfczXz3GAlplRW/L0vZIaodgEbwoIfjmvrR1PEHpG+f4E++XfC34jI
ph7+Iw18vX+UK1b4nMV0qUrCvMzAPGtccJ5EuA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15072)
`protect data_block
sfWcr4Jo4G7b5yd1sb0woknEGskdoD2IE7GyxxKBl7PnYLzmL2eVCOroWQfhdnxtf18e4trlDyax
0YAc8a+lMOxMP61YfUbn1+JHQxDiNlB7x5fP6IQE9BRUt1zhviFVsOY2jTgmKOq+txh7JbaLqI4/
LWCufZTfkCjqW2SqbXl66ns1Gzi2BxX+4YQtryU5LCeJrQdvqxFiutbZhTDQ7ci/9RGj3umkreBX
F/2sex9YAi728skXg7r+2iuFfFgFsrajHR9Q8DNVPH8rW3ner0Du6OwWrbgypDl4fcWy3FW0SYvI
bfi2AsVpbMKH6CR9fC09EAYkI6bSp5JNPN/4yLBNpXCMLrMXIS9BePgPtfO7OJmSz84AlpQ6Y744
KA2idKq1tNikyDhX9GwDY6dEQPkbVkbr1V7Wj3D0qRAbt+T8lSjA6zAwVrtqLCsw6WpsIY6l0vee
rbZhjI5WcrR/0/cUykPY5ECaR5Hjz5AJOPZkzEsOqaXSge5uqKyzXP7kSr2oaGjEX7nLKWp607HL
SPoQqZfn5LIdrIRUAh/YInD7CC2DqlqftXKryHej30Ra9Ep3H/jgLv5KGNFoDzUkowtF4UXdU1oj
miZ1QAleHBekKiWDOABKvYPKsbTcCQrbs5WJVrUKsuZbq0GtkZnzmAoUV+duOSVvNFHgyndU+cXt
6K7hfNFdNOyivAlzrqNnVnat6EZuLt5qDnid87hxeLoizfN4/N2v7crhxMisYbSHccIn/LXynLs6
D8eGnIy6OO0CQa41Ocj11+o9y/n8PWpdrwStP+n1P56KQMQlVajivnQgMUvY4xYF7zgKt8iGgR7J
Q56kJ8xLhpJBaNlRKmJDAWd5LtDhr/kDBgBQSnKmo5e6Taw6Gkda6LMOfYPMPgK1ykxP9ima8mh3
MYqeVeWBG3P/MHnlUIp/7D50dfhEqIuikgqS84kfwL/zTgvxmF5E8IREIgn2XIo0VyrvOY2qpzTx
eMm5/tdL1olEwhm7hXwyWn5tzfCksEPEpUfPjBaatM4dLIMGcXAwlQJDtP8FIpH94YB3VJTAqwZf
pndwhznkMhjaz7K2vgwBnBeweZkz/qmQ3q8zfcW23RgWGsETHVFP/Q29R1VdOQe19TeibeHHX5pj
cazSeExEwRzJ0m4AioBfDD4J5aBhdVK41Lbg1m0nagtR8pnyaGkYLxpSvVbvJ9HgV0p1Z9Z2l2PZ
6W8CFs6SS7Zr2eD3SWqVZYobxpeIHOIdqrParqqIILUoKmXLt7WFohabuhZHHefeoul+8L6FlSqQ
eyTttiTvwgz2W+nGXjQ3I+JA0qTlNLxGpu0veSRXaPTD3e+xBsXdzSXAcBzyGUyG76m9XUFBDMSV
V4Zil9hs/SYAcvKnvJQQDXsWb8YL3s4BY/insDPGzz2vG+dZmLCUe71F8VqQWtT5N8k3v1nOMnEH
BrOYwdlyiBtrTk7GQs696L3Q6WLMQQ8gyab//idL4KOTTkbOal81gWSq9fe9XaAFapuZEnOssSSe
5bVkwPOgR44m7hYgqtrB9I7nFbSb6bzPg3C3XaNTkKFhji8UGqv5Yupborl0UGgSMe2iXhDssuwg
n07X7eogNRV1zqBHokm64slW1sDn6RXmwzj4Z9FWMh/sqgjfelwiTZ2dsqI9k3WW77kh7kWS4cgZ
TNskAIUikF6MV0lpntybTWDTM0adxaOR4dHetPa3wF3ZNwF2p7fjjYDObi/Rs9l9FuZqLIgq76Ni
DB5e9GsP3+556Hc0oN5Ya3oRAauvYTdh4IbyBFdOIFz7eMaMPbKfa5clWNEPpmhFcX2dFh8tOz0l
xZI7fbZLNZ9Tvj5BGPngQScKnpNUr62VVUoLr5zVMBjZk+ol2rczctIIV5j/aYysCJPFimCdll6p
lVNgVkTjtyD2YvKLAd9z+FLzu4VxdfVj0TYm8Wb7Sw8ro83gIHeteSELf11By2mSC0lPyYv63GhD
YYR1veHGi1thNq+DM6GfXoQO2PGwK3G7HtQHEMFtYWvw8XdKxux2c7E2dXsmnCy8SD1hmsZ5Ow+P
QvZwVPSRP2tTAhoABFABWl9m6rkYJnOF9AQbu2hNSVwL22zpLaks+eR8P30xcs0/ssQRRTxIeHu5
/WeiPpOXuRYh2FPa2ik3/53R4l6/D9/7RrXXtVb/WNnrZuz2FASeUul8zy78Xx5REpkTqA4Mtjil
EiXcNcO3MKwVyfW0wsbI7UBv7tAJ2MyMV+VnEP4228avDmIp5/l9kOytFvTeJdBXG1O2vylvKcvv
NyBgx89iP9QpcG4BoAHe1LuayMWVq/RMXzaIk9IU1bF8CZhK7T56zqzAbDpm9sQfQPugXgnqiN6l
UgHx/CsXMIZjGX+CoTA7PYzrhgDzh5oHh9AwE8ZowmTdhj+ZURA5eo+BpHeKgB/7qQKbDz6Fm3fo
zMDBl6e9ft50mnFiC+kILC47KcWr+VjX1OscJabKOzc9itC1WVvhvBcUh0Z7RTGVOukdTaffmwKl
WXzyioGyYiCKp2oAj+fMYN33SM2k93nxCdyhpaZPMaB5tyPXdaEyLfhlMSpQBelN82oBMOnKxtI/
2f4ImhQMPYpllAaGXHGXtN6tIGEF+YsQqJ+KhM9d+M/jffJurFR5nZbl/v7E79oXNJrCehwyYvGS
EQcQkKckaVQwUeTy7xGyTBxdRAdS5q22R1RqDTU/jUVw0I4QaesQ6G4Ddwxs0u236RCIGEIiIEWl
saNUt9igLX8S7zp3Qxm01ZvQbuAW4oKQwUu8cBJJhuBLgqPC4E78trz7hJWp0t6MLYefnD5RWuFh
/deVmrt4ajcKMzTrBkvfO8jQcRUbF619lLhJts5YEn4j05kgUzHakQ6RxxgvNSe7SSLqmSN/RRLj
Q2jo6BzKrg3YNkWZIDmYpHypnAdSTM370iUM1az4i0E0xGbbcmHOSDchUbBIZdp/SfamNV9xiTCW
nmG81v/hROtiqacF1YWhU2PTfJv0RlwyCS2puZ6DJAanj16DKbbyv/HfoG8W32qFoEcbCPxpse6m
SIehFhDiD8s1J4a189mmJTIwhYb4Sa0qOwH1BUWpTB814FZ05Ayh1wkfVMOzC9yCo3/equ0enRdp
qSeBnV0ys0/aHii8VhN9qf5GGBSdPn7iw8diugoeFZBYFZeN458B3DUkUaXv6D/f7z4J06WVWV25
PpiF/85tJSf+HUzupemSSDJ4GRIIjJwISn5tyQWmv8WWfoxBzbqvKgkuadGnptSP3790H5+53YA4
TxhPkdxcdQeBY+TS6GpPmRHRYKpt39o91wHMfdf2mg4aWoJ2Wz7VySLsLrPuzeFn9M/pTK3uAlUH
vLOj7TSGJ9hzzPjhmg8Z304dia9tm7rJOymDK5YKk6ROfN+2+kZSagXgINEcj2Ix5CKHXhC45PtC
q9TSlXuTzTZIH0S2zpqnIZL9vsNMQDmnxYWue1mFLF0/xIBaHWAj0vYXQQ/DMg7sHP9vEq65LOGE
SWoL+fma3MISIXOe4x6cWZ6N8fRyQ43eR0VUqIvtcHp69VHuhcVDujZLNixH6DLwmaFAbhjvWnpJ
w8vqeMfAGrme/pDLe18w1HrzWDV4QDwu9dcYXYUDAYPzFv9/ngU0VNtyrSgMzXiIDUf1tIt7H/py
Z9HaboZy1vILevHiBXCw5I2+wirOU99WlcfvMVRk+u5NToTTMoJ4haAxCZ14nC7VUZEeUKMACuNI
hZCTwbIlVEAnr826Q4DKAwX1xrYnntElCR4wEq89MbINU7fXj+lpGGleuTbKCDh/YoOF4juH6lHN
ATK8UfvJuCEVdQD6RdRiEczYV4u0QUEM8Oa8pGfiYk+IQSKi9uyDTZena5KCHy/YudnCifLQEHQR
4bjy8qrz10QvXH50QdFlHKKodT1mOu4OYE4AyftoZXgZx4635F3N8MUleqjz+fq0yUbb/kMcelo1
Z071vElIXuImPlZyaq2cljBgCayFAhzdpDIerrC4uirkzWv3U+ZErw4apokGQUWH4DrB6hKuDTfR
iklHn04liA4U0A1SdntEPrJZQh0T04gMFb4+ZEqlTFtEyYSXY9j9QQGvhFL2Avpa6FT7JaZ+QTlG
BrXTUedkAMreTsJA1SPUqbYreV6D/zVrNPlRlv4ILdrtMbXwKDm5KSKnzuAun9F/jqfVz2cYR3VS
ttLDrsQsuNZ/eZ/sedZCUun+540uKdSJwwLobfORu4/d3+oztmonQevo3pVHCw7mekAoqKmsOJm4
mz/ZiEIr3KlevXmHtQmGXxawvLRASooPoj95POIAX7I8D7QqHcbsWsSPSeb7K5Qz5iqZvCXN1pL1
EPh5CcaGnso6Dw9Lyp42go6/hGl+jY0z+bGJGVNMzZSrCJ8lETQFySg0aEA8pChQ8QYCE5C9uhet
tKq526guRM/9C+VVEGH4CG1nSAK8t9k1W/1BYw2N2dtthW7UkCesUaZ4kUQxNLHhbr9V1cjyplt1
6hHAnKrSqZEhdDju59+sj5703/evB55hhT28kyOPaYEvlVFkvRBG7busmYrsIwSCCG4MjMyVhSf1
G+seBZNBF5RJ0w/69q5sEaQsjUq+HZYn+HoCcDR8lDj8X8gmrue7Kh31kcXybn9E5MeJs74LPYCn
ZLYT28hTFy9IbGWqmnatJR5ck5HoSRUUzTvqsXwYSYBu6em0uTISaFngyVu7r1DErVs2FMBVcW1W
aeLWFiM+KKreXjh7o/S4i8ZkhtkLvY/P+UWkOST0GjQoM/cuOM7jglbPO5hbKCWUPBJtjB4ey/rh
Dx5xlih2V6PDnNBeIZxYTv7oQaKBa8CHifHWpGMqkfnBSt8Y0BJVbyoxZu/fSRTVKOor1fsmhNu8
yzUYB7AuFYh5+EpmtDxWL36VdUUv2SVzl+rsz1O2j1GuQ+6N1b90t3yqOgWdlVts1EvKHcg3TU9W
HLxgoky7w66DCGAc7rC7Tz5TV5h58ihHfBcS2XY9llzgQDKodBsc9ntBhguP7Qg6AlclsauIMph5
S/9Ww3C8L30yNP/02ImOaNOSGyeI2QvIV5DlAUm96fR6Y9Ff0NmnQUplg8VJtOCKhVw8Jo0XslSI
B0STEzIocYl5MtLcLrLvt2FQ29LgDZHujZj0KGErCQn2zC+Fglbph/hbbdbzSoIPf3qYsyb9LbEL
zj2t7yOBEhBDYrstEhViPUpTKSTDastio1BVMT6HThwCHZHpFeYJKwUi4vhZCgdUCXh9Y9rrBhSo
vRLrWwP1++Xcsl0aVvvYZDLAficsK+oArHcvf07MI/16j47s9ar27GrJPq8O9T0n8n/aO6q3Wlza
kU2hfZ6Fohov7phmFRl8Pl14470iTTC6CvQnPGKe7E3ODjCj8C0hhpUzu5FsaaBn6XB+Asv7RitZ
Y1273AaiYkrgBBRdeGNaguDZzzGubRh013uwFKLvDMkUwIXfYNgUmFU1tiMK7eUT949eoML1va4b
gIDzhcDt2Fc2DYzJzteHr2kxibhfgF/YwJ2s6U6tA5OoFg1qFUzNSehhlnnpmbw3MvK5rC0HsbLO
3kiDeBZp6Qkuc688ZCWP8xJQce8I/JXChbadh9wqr4kIPaFyeIXKaEpuvJMWLQTstJ0E4l6jgVgA
CCCV56z4ybEJrmM169XM2gEkbV+zXtW1Ipf7QsLKNFIy6T5k061TWOxUOamwL0Gy+Pk07OIl5Uf0
FZMv1JQtrKYkJQ8RFFDO7gnbEVNwJjnDcWzkSAD4lJQ9IStaDljS16EkXDqHrvHTLuJWWlo6p16g
aSE2a+jw493eKiQJJ2PJXL4bke+utnbACqXgPWaWFamno3rHQEG7iqG5UYrmYCvaAqAKzFht9uFw
46E1k2zuccKYXU6o3yqwAYmET3Mlm+nWe/+SKL22XPOttaCeUtOPoulI9svKiDk+JQg7y1quMhVj
81VoLFE7GcDSmRgqS0DBxcvFr6rE+ia9YdrASkjKRLSUdrO+ztdYsRAACBN/lbmvXs0Wm8MJ9e7y
GSE0WgpqXJ9X9YJMWzlutuoHmvEUI90DoKe3PG0eiENYAMy06CoU0bKeKGoeo9AP9BEBa89vhk45
MhyDNZ4IwUbRFHO0dtf+mtNDTi16HAbZnU3IOJC5/iq5rCZRl49uteeUr8hd1J4jlwJ1EisShcgx
5XCzEj6Q74f6dFbPpE/AcJUqyeBYBNc7LRHiJu7w6Eti69H/o6zD4nDFfVyv2U3dGmwdWi0Npl2G
87ICmo8FJPpp8oJ8/ljqpSufsMz1WLNxCZGnKrnpxYVtn8k2Xtgy5X/bdbtkBZoDOGfRYhTl0TXC
Trlj+atGU6YgI8Ql3eUH5UEbuzR5WPHZCDRO/Y3uVtXQsnYHLdoNzQ1k0r9C4qMGoSsrutyR3E4R
RwWEHV8jmuYzBneCMewQF6NaS+UvRLEGEs2uL+Rr3aJMiO7wcCTe+jD4ULLXXVsH1j4Gv9YBPpJj
V1/irv2cEUMdqapXe1GOQ25J4YXgK94xxyIj2NuselIC7r4D2+RF6VSBb3s9wsbY4toamvRmHJYf
3v42Xf8ZOccxTMpxJTqw0ivqHmXes0wrxMQqgHY8odsJdoFI6TrB22CU0+saMKQJVunLAUegHZVg
aFJTN7Rkxk7+f6W2P6AJq65KUEnc2WaTGSRXUflhY1745yQPRQgDk0u1EROKDDNN74jpxbNRJ0st
6zl0nzppyKFCgwaKCqhHXMwJjTwu416KYxIGcqsEj1XvoLK571opJBKz8vQbXc4+t85skRRFlHBU
oDRqW1IVyxPbXEvMrz0Vqoqx11elyNLQMlLR0Y8cmxgKFtpKgtwquDDF23tPtQmivd74NZ/7qSOW
sF6XwvyKewwpaoHN5iLuoWYBOpjR/Qw5wDAXxFJaKpuianR4lGAlsB0zB6U8MyUcYU0NWFvdXg7n
sCUNKJ3Dt6xzd3yuI/gn7USbJwGJaY3hZYIb0CcMzOUT6L9F04Z/30V4tcNgZQ1MjLonQS+c9X5M
ekp49X0yn9W3A3jvqimtNrzi1BMGHFz/A0OzGyv4Agzw6STxi8FEo7+mRreJ5Vm3/Y3LSIsXIzbV
EFMeM2qDl683gH0o/Gu/y7FrCa1DKOE6fZn68GcmLOBpHll6iHldn/35sIU58L7on4FCc6DD+BoX
EBhvCkxko+k4atDI/EEIE6SVoywl+bDHyF7BzCui2HzgF48DjWCPwUvpAk3CMPLoDlIPX5ANKYqR
pt3gBk89p4NxWCFWQvJfDE/2+pjfk80CvXJ6SOQyOpmCjGZ4cOhP8KZi634ciXIn/MegbyQvQRVi
6Z/mqqP5j37Ymm7sGJJZ7WSvHAru/GoV8VfDb190FxVT17SdkiGjDYs0nFcX1JxzDXDtoxY/Hxzk
LXnR5v18+XQO3OX0yOCdniSSr2yoPqfIqr8apNl7mNE3nFMP1VKc+s/iRIIQNiIsxYBlh/MegnYH
Pv/vpswrukAPiFKILyHHS0kHaGKtHvVpzrIfktoVVw5E+l5/AR0cK59eYIB+YV1e1buP144rPME5
nVK7x4rksbuV1zBAn8wgETCPjJuH3T+f9nmCftE0Y13w9neNs+oBHzJ7GWd/ayqVUjCNl96cira1
U3kVC8VzYAdneSHuAr5oQPeC1r+jbEzqZxzs4bdub86hz5sg8ihs3gHUnjQ1x0UpwKgGGonXO3O1
gjRtFg5z/ecOu8k2UTsjxRnJ65qZyf1im9IrrwEbuaaf9D1Y8QJ+ojGBNft/mmu8pkQqNm8TXzjm
h1iB1NRWlc7ccP1m4Baxa6KizK160WtF0VbGICSsWAsreP7l9H+CrDYZ1g2rqmdyV1j8zdpeZI8c
WT/5W/IpM5bA/z+mHixGAN1Mz+ymMFJNJ/Sc9CuhRq0b81eKzhGFn6dDMoimElytjuHtiA5vbehY
puTGFrEtQwDuVAUtQl1AyGFBjiSM74BV49H/2i5NaMIq7d82seWtInivTB7f36HZu2iFa6WUzJgI
FMlDzQwQqu2TYsajE2vUCbklMd324kohMGbcwn9fT4krT2WdZrk4rrOuMxuWW8/4YM60sns8HdrK
l6KZkpEwShkwq3ftpGTP9zImsDDfrpSjSRr76l6k9nfyIV/sq9muB7vdUbxmNtpSygExaOWUV8B7
Nw5YZ9mETNpoKoLCVyXhjiFaPi+TjiJbYeh0OGdBgp+S2G+x5X3DoptE4mmi4s1KnNjqg6GDDtxV
TJqzfNBfrJd1S0xH3rz1T1H0idXGmAZyl0NaxjGA59+8FbCbR5nHM9RvQ81z7iDsY/DgwzoBf5OT
OtUnwd9F2uyG0PtbROsnIN00qlVnbvBRY1Y/8cYCkeHMWGKJ+Pxt97FXhHHb9944xtJzNJD2wWVG
iBdIi77rBk+ir0nB8fxTrUkYq0T8AfrRfzClwhzHPYa3PTtU86gMY/hKzImWbZK1vwyHnxXzsNJ7
zaEbc5bew3Lt3HW0QtnGbXImluCYLOquxtupQRomxe2Wm35X32YtkKWtBscNE2IomYU5X6brBUCJ
UVJgHBN7cL9HQAKcX9KzBzpsWYrPOH694LKqV2mjIpdws2RoEU6InW8fl7lYnDztPhyiNDv9P0Nj
IAwgmiLiGGEhdGDMd72o/O7J0u208bHSHkJc0BELG8qm3/cg/titL/YTh8aZ8G5F+LeSZcv0Z/7Z
YLUSQLzEdU1aCu7Fg6f/p5Lj9LM06WGUikJxjlbpNN3ZK2mr4rPWXRa04YL/g2iBY6se0BiwTPyZ
wEinv+/f35BCgHzGA9aRv1FD9A20nqrtvr76hHPqfMmFrOlQonwiA4u/56y476BSAOuMFK6bTWgb
luOne0ETG1ywmkk+fTcWQmE74Yk5Bt+HeuIHY2h5HcE86Yak6BVS+/uSIJfYbQdu/u0xvOVmxghm
6CIrdnhzikewWK7FSPD4UGRyQONU33FprEj3A2+OkNxt7nPXMU1djoW9x1/8YNDl5ujnzQRBt97W
uPhrAvSewOFLJ9ApmcpWruDg2zvbPEjhB0DUsx8bb5/Dr1xWCJ/Dr+GUTqR8a3oJSbQzq9nC7aet
ErT/rD7R5S3KgpAXaCsrJgp4bla2Ixl9mWn0/Efltfd7L1PR6NT36DO9tWS29cpPVfzH+DR6Xb98
Q2AsCrFfqRHOxb+0rKKTPvI4U2RJVMH4lCyvcaje7rX9ZiE8cLJ5rFDYk5yPrvjWhNduu9BlAzpW
23pguDTNpK8b0/GaNPQRDQLaC6ARr7cVGtFTtlWzRF8Yr4U05Efib/oiNA7V3v5T6YAXBMJ815rv
5yghZnYWKqtqCjgxb2wWr/bn/zp0JMjNxkqry3l9zGenNJ80n5TE8mCyHC1gpcyr2yFLtq65QvHn
EijS/7y5St/mswgX1iwcLLrIoZyCisVqqS0OaFC64BrJU23e4NegEgxqc0tEdJOIoGBBCks8qgul
ByEjlQQX6ArrPdbs03ufmI1Jd584HWuhzNhomgWDSteNdZn0AQd/WcySKZP+AEH+DMxXiRUEH0Lc
nFqYjN7Mydsmj9YcOhcnAO0oHZRjWIhEgmtf3X9doG68v2g9RZXOYwFR/Mw6DUFJzh+O85DiKCrX
hWjCtL5HNuCmVkkmYhagOHyw7UWKt6knVjDhpG6GDkG3DGgHZgIU1cXB701+iHwB/BjP2Q1gToyn
fwd0Aqtif9SY07FwaiC8ojmFzxAnKBR8+Mw6AdbQxvZxRS/xirqIqQgUDCfTOh5MGnL/XybzSUsN
euH7jXl5Y7do9xlSYrViXN2t9Mb6xugxtkeEK8HNavvj9oQrXmeyxMQXKX8bXE9swsBcBjg3Wi+H
JT4Qm+R7hILu0YoVHMpDd/bjZSZR5Xnl+CYiK8o5mYWzLfu+F9QkmJmmg0rQKL3Y23HPkUExerQG
pDLe/tyqjgZFcTz0XfFbqg33RjeiW/IJjE6QDav0cR3dmtGB3Fm+LOX1BGzRvgF+Qs76ZlMowWGt
S+pSt+C8vfOAzcOVKkPoBwrB77GWSRa+TXM4GCgxKkkWZYE+emXyhlyzt7D/xIfUb5/5okwc++YY
G2ekmzy7oaQNxyonWFgRmEhxrSIv/6d8wSvLlipieA19uxBQQFxKtGxzr12GDvxbdnxzr738yZxM
yk5XsxH4YcgeTR/iIQnSl7mzaHDZqvncd2pQPuyrKs/TuSC07NSgYfAGn8F+EfMifN4kFrkO9hdU
CkWmk+4pGSMOuMU1/ItkKsm7n3VJb1hD2TvEcwEuaZk/PYX6IbQhEZbEHVcEJqkAx5pNEltQrjSB
p1SizI2a9GTcYny0egyD8ifcZJl1NpggC0Oes6AhDqM0n2YCOqw9ZVtMP8A329Yy77prXEmSZAQ3
ib5qmoTRoB88TJBT67ejhaSi9/JOCfNtbbY9oaOPlqBPJbExm9FznYvclhNbgKm7gg74PBzplrAV
xuYGep4+apeW/1zOM6Scx8JG97pzV2J5yKtCLY3gy5NOGykksisy6A66zdELdLDo/mKeoolzcSQm
TP68EBssuiqdZJM58afZHAi9Ab0E8InJbQVqIJge14x1j/YfbZ0aBZHI4lq+OQUZ8UA5Qy7lngZS
KdHGpYLD1vUJqPIFTEwzPSpiJyLF1NJvcQVg4ThKKkwOCCgqqmQQwJWSa+FN83Z68UoqxGdYj9sh
+8SObkLPFrfpqR8iwMkSiCCwSnO77DkhAX2sLC7dkG8GebUl63lwnbDUpYR5dB2R3MUg6FFquapy
4UBmfkVEQT4KkE5VL71+LRwljxp5a8PRncJRTnB+SmntbEqGx6oB7OMp5bWtNE29fZsAS0fxpvwe
WnD11dWaSuk8U/j1HO0cZGlGhMErlRI/yfAjDqqwrRwjBdVhyk+Ycq8EvQV5aOe/LbLOL6udAnHX
Uf74zydM7Sqas3ld3dTaAbXJcuCZfunqX4AHSowYVm/Pbd6CijYgWW54t4FkWNsc5G+HnZFTSrxv
67Vsalouak2eC1549gvqXd3fh0y+Yq6nlT2DJC7MxLiP7L7ZIcASkoIYZHzpXpdUChl9xdDoA1Zy
aTXz/Z3jnwyA2YJRLppvDllXmXGKGsl8YPV0M0pzmUMTUECiclx+ideJYBPBck65Wv5RrI1pkHGz
roPaQ74LsJKo3wZUVkP3Z+urvdQHcMyb9vxVhV48g0/u3SlPLNnUVORFvkCf07i9TIOWDUn1QFDE
Ghpp9Zgqrz3DHGs+9Hvd+8Iyn5Sdypwhqz9rMBtffjZXu2Is3bjOQeQ19n5DD4MuL6jUkUm21CuO
FDFpZ9VQTmV4Y9d09dPzkzRynxEr+bR+YuwqQ/R9glB+d7EvwJNic6EMXdaJwpcKBF9bZ8UsCBVd
bTeGEQqgAkVYlKV3nuQcjOR3PELXOeOZnpBHmFZETZogiZ+9l2KXfAWzD8+zBCO1P/hyfWrLW3YD
dYGJOE/Sj2gZMJmH9pyyBVy37qbe9LuW/kshnIzsiudPSb9+wpgJlVPmh3gGQWrCY4ez9eRKIV+G
IVX14sFV4t7/ov+uzP13zbwXk8+2LnA0MCZxbg1LO27IGX2KtqeetyBv9+iS3sYYz1hZikos1IxP
wBuuXBvfMk8HZczddpLc3ODQj4rW8Si/572OgxjmcDRvDoCWqq5YO4i5qUG7WvuAkBDuub13Q0q7
8TRTRQ2pd5AoWSXAKSC+O+t2m0qpf1Rvw57QJ+Ztlp34tnIbeDnjngbhrwcFAc1JJU6oYVD+YpFf
luilFod0kKk7x8aSNViEtkcD3fdf8N1sveNtXQPAykJ0AW5PTnmiL+1GEJfX1krCVHQBkgD/11H1
rVjubn51f+qZXfKcMpmBBBqq0yNf0acKhtsT56RjkuZ5h1iv969hsl07OCegPn2zCCyi6r06SqOX
JrjeqxhdpE6ibUZ6It2laHR9ElUol7XSQyei86g+gOVK4aRXerUqN/MYKK9Om8sXaZke8IkYI0/V
pvBc8r6rDk5bWTJraC32pn8yzH5mO56oAHC6rQntAttdgqK9NsLqJriQo1vMDSD1kcFIv5kNJZFf
WcuV9cf8fVYk+0veS7mgf47JDpMrl/rn4i8nA/kPM26JHcC5W0dsmcG9x2JPSaVzXrYWZZvkZVrq
0beVSm+jQY8RXU5f/CvePlNCuByA2zV529jGDUkeqQzKV1MR6OytoMFUTWJP/9t2WLoPDgAoRgKQ
9WE3wbUkiG3SNj8JILiAse6wF3hZ3fgsqHCyGQyh25M57vAAAa50FP62TtMCX+tQVk/tfrvTur0q
cjRsEZLXzY5I6vOF+/mP9Tea/GyHQI8mBllCu7pUzKDiQAcjjjPfqWwOIG+5Ouqyc6y5O+JQfVEA
Vr6jR9DU8gttY5mDCkHtZCb6KMn/my/uw1ab29BX6Yypyy7j+G3gSOBUJjPpZcZ0KVGh9yAhv67R
Bhx2bHa6iIbQT6G1ZUUvQIIkXE+x3bIU6KnaWbZgjEJ7cMDhzHq4MwlwQraHFAZGde47ZWo08ama
8b8fxc39NggALDMLgZVAUzbsAKCN8Nx9MHA7Yl4iPCvRjfHUeOX4eRy+P3GgWV/4DH4OcStdxJZk
8zGkIJiBV6TGDLrifWVDN83RsLnTkjWwEkEIZtre3Mc0mj18bzGAu4AT5FBDjUMC78U4wIhjSZAC
X1jiDfsld4EcfsimsbaxbkGL6IpH0et8QBMGQNz3gvPE/XjiD9NvjHJ6DWOHyuk0LiMWKZNlU/IH
uPMFpAK+8hbCoAE0Fd8R3GFtQbNkpp+F/ldF15TifSl9SYiuNZ3sV5ZAxVV8LB5OAYkAv9azDnYI
byvTBd+pyIaWkDCxNgET7R1tyvTYuNGwF9Hw5blXMHOQn/IUsi1I8QHzQwmgsr4mGbaa51DKe9db
e9mCHcZAzLkJIoCvDy6JDmGOYX9UUyVJvF/rhgX4ThTUOVGd0LSrews5T0qZisriQooedux82iM6
Q243PsX8PUH4EsM9IwL/kI4N4t0O3rPTYxoCs3JZaeR0BgbOa9Dz29Uxlaj8ZWqTdmRbz71d4DHz
NLgPfdQo8W2Lugn9htF0wol0qDn9Z8szO/QaGAynAlYzr2h4l5zxAaLsC8ET0Naar/+9f9fHz1M6
1jrJBU81M7XBrrIO3rbQktK2d4ZURdLyGh5Vt0Wp+KKv5zAeDAl6E5U+UQJdz+06usEppAjQ7B46
0lwmW12++Lq21TsIiHAawvzXija2mWJ7XRK3Fef/9dj+pRJDYsg6WTSVaGa1sggQl98fTllQkTev
8s3BWhpeDYuBHqueyW1sVa93umcm5c9s5iV919neibg1wes7zXEQPbklMB7S+ME7eS452yFiaRLU
EcyyiNTvRtVHIV2Bi5VrLNdg0B/j4sg1v4BMcrbTYKV8/oRNc73V7C5VCyb+SM3q6BqBXjlyLpar
TykpywUo1/otewrOykPNvU05ckAWLufiAL+3hOnJP2kdh6UND9nXGyd3i8gNjQ6uyl8TtNLtfIUV
UfrXPKRXRIQw8eeDpI2fN+BE0NUNJQMQU8RWuviEVHPJHNVR2oTW+to8Y6zvYWX7YME6oI0jCQj0
rXLN3Yfyrn4S3pGrnM7+hg+Q1B9e64eo3Kwdt+UBHHlUQN+U6GEFjX6LF5C3Zqrty9jknM4VaUtL
mkk1SKLLGJd6p1mQT2mqU61c1Geq0RuNAJVjG2HYJ4j8RbpKmOQeGd6t/W8nGHjNbv36+QeY0dT4
u2MNl6xseNxZVSmxbZgXNrCjWyFlBg6CGxySSmyGJOgMjY6pcLB/AH4D9ixuhLNrjlZk21L2Nv24
JiZLdh2AAb8E4AKNvQTyQHM1TlFz2Ur2bJoyY1R03WnzSFdxc0dYnXkFU8fnI17e2kU1odPRNBGx
M8lRO8sszjyX6GHSjdAmRqe3TjvkfHqpXHhCPOdBK0LVqw/gz+N83LPKbZ6TcqKapSVhNGmpCNO4
Xe6QHJ/24ZxZWNzC/TL857pLaM115fjuTxOT5IcsqPBndzNDvTK+vG1rRNtqo6iYXy8mrSxn328F
gZzSufqu+buNDfmiuQdllarfqEdykgRxw35AZQpK86pKP8LyEbAy5vsUKhcSp6n11dJ4sYmRKm6x
uLB8HRuThTx88J1NSv4uH47RNdSeX4WsiFM0dgcZ+WJ60nJqZPbQRDVgh1Td/SItxRjVnY95ryEz
HncahAkBhoWDfkM/3/e2twndZmP0F6JcgaFxEhjJ2qdhsSjaRChNh7+cXj5WuDy8RdLXhcN2ERmV
uHw4EX/HKOVi16aAfsNlXTrlyO3k6VSAeCi7czlixYk28kj+M2Hu03bbEQ/hO7rhQSUrsWJsW5e3
fV1sJxhfNnzr0k6E42RA9z/0XDmfzr8PnXo7jUsYvgPAhhSg9sHrGhVt6ot5H9/uZHjoSscKRkBE
aj0PQ4aLOQ/g36A++GVQkjt7WYAFLs1tUsEaO0+jBRo6WpmKKrgnckMSBuOsbIoT7a782LlpJF43
HFA4EMOAiPKI1mQVXeO7J4Gzhj9tA6IoAjs+nKq9psEBgLsgipuEuoNPJSu/UQwzWxRTVwhyU7Jo
Wxvy7DBIYL2fb2052APLTqx+JSYks3VpPs+Cz1tJ+zz2sZ+mt3ikbgZwZv8eP9QV8qSw03AaJMBC
9uW2l0F7JU0GENd7Ho6LrwR3kBhAg9dMwLvgPom3xM///6ZCleTxsfcIrzhMDtRiWYZceXksmIH2
Kowc+19FZxDPvzFqopg7hg6c/kwAkSZuagjJ1mdkYa6/+EtsvXm4o8mUrjEoBYekN5SXgLvqQDMr
SiRCCNI0gKKHkHG1gBDri1htluv2cO82joLu0YTg5HW4nq4nwAfdXgsVbGTk+JNSpnUfk1wxXFfc
cLF4opg3vLutPAmLS3lbZdHjTooDoDUaFeqlPy5cEgEFVKn8xNo6j1+pia/fOC9cLcdtYFhBncZo
PG0mTgLynIHKl5hin+JuDYyslvtKkbIr0Tt89XVgjK4hsGfUfsDivkZ+EBrqr7y9mox+iXPyyX17
vU5Ek897yEFJf/fj/Iv1A5uRp4UoSFF0eoDdhpxt9EErbDdA29P2nuc58CxbT+kk27cKro2THCjJ
W15/6LAFP8YEm34H9QpmADEt33LQM0EcsWLnRsrwsmjL/kj83IrY4oC2/pjRWm6Bg+LOR8TfmbyN
hZ3NSBKG3dY6uGtVCEcLSbrKhg4PnQAwZ1tRFhsE5eWsVyPOGzHPVFo97zMFCAyYf8rD9zhgN55G
XiGp6JgwUJGTha+EM6iyPiqgvY0BwEC/maxzSsWLeRDy5mD5PFO0XbVRRBR3wrL8al+TCJXqVMXq
+dyqzEuaoL5z9bsO28yiuPA+rGgwNQrQBq0pgMKXZo9AEw8+Rbq7dAC15WAqL0bFjFYUj0Vb3z3A
QU4gHdNZQvfxf8dgAiMngMnX4+Ayxzb2j2/PxZiIDKStMSA9q1ESOMUnO18UbRbIWoM8wsuqHlDh
3STk96E3Imy8Vp3rl/HdnYn9rrJwFE6CqNRWxsuWaAVt3f9wz9nwlOuRR+ooLFJ7TWWHivbSll8w
Enyo/cJKperhZkHwSTHkuP2iyS9b3HujF2G/LsCQ+wrg2wmFfmkhlLJgL0now+j7tQr3cijgQoZ+
v4un1E0rz4tIur3EfByZQlMrXeYa3ZQAUBUW3IGFpyqj5FJenyq4gWrlT2jAAz68vnW1IJQ3K9Xa
Cwm2FyXbP+HZ6d2WC1n5YBJzS/6OIHpw3uZYcNwk4ldTzZdr5gw03vAHlPTNotycCnIvuQZb+qSZ
pA8Q4A9cNe2JzDJotLxtSZASco6ydjrcXPoUEm+DyUOD/uLDwvWbf/yK8U4owukN5lbFIFNGl3eo
D7Dd4GJKpdjcpzJi15zspWAAGxlVxc5hn/GlMUhzlWyGAe/P7bAsUcZaLxNV57qhJZVczD7rk6mC
KT8OQPU9M7ZL10CStWdAgQlFt1eZ82qOAcyOs+yMc81rnWu7MvhjcTBOqGuIQnwVJjZaasczXvYr
Ze9pKf5w9UnL6C3mzIezSWHBc6i9++DHvzOvxVvJvCIwowCWoB+qvK3vkoaUQL+2LuxCd/PWF1+8
5eTUH7JP13vtQxsgl4vRRH+U5QYkTu9Iv67HR8NF1LW7cLYp8/siy+k8jlUkrC53g6vZN196PUu3
um5HRF0kO1BPcdLTYeHulQV3UkDCqexPdS8BUa2csbEqXnS7qUCxAEt8k38RDV3J6OUvLWVSSfad
njqnz7Rt8TMGfsh/3vZGnhTsfRKqszdP3YcdcX61UATHe8OWxzDW5oUDGHnPVUZEdAoaSqW87HxU
1yA/6Yl5IEpFNE8v7f5Mt3Ed1w7yvg81mtuMwLu/XreLf5Wup2sM07Wm5eJZBwm/QKLLCpQ9Ys7K
z1Vg9czw1xFs9S+iyyN+5HtbUt7zmu9Bjc7Bw3G47NBzGa/Y95MzWsvKNibaFsLCjh63AXvlUekw
DcrBNAC4DaP+Kksc7PWgM8lZBwCX5XHvfCPA0s29s4+4etsSF/t1tnOKkbi38TUX/HzKwtE6E9yz
e2kVYumRcs3RzHVxRIPzaBTTrhbAZwjm2KbaaLOH61u249vFseJyMQxpQXvJiqHSvq6h2YllYd7X
FzLo0ce8DW2AZe/pq+qtD5Y/jF1uyPzEX2s70aGJ1+Qvk8DNNfaTtRN7QwXZ5IqAYSmp+E/aEfMB
tQ34ATyP9g0tuWkF4GjQP+kzS0OjktOai8zd5SWyI9j25XpQ0EbBeJIWiTsXLQU0BROgr/vl1ERe
BqB7njsPTy64Z5PmHOXj5hxbqA6GiMsdV85MIP7xiariYnGfCZaG2QeXTxaR/P5kVdvl4EuGOhOO
uK6o51IjHW+wWxLAB2rzGk8XXd4nq7zyPZNA9pXW+uEgrQlxLkxMCRddYNwhrm9WXuP9h/NXLNuP
8AJ0f2SOLqbhEGJrHTc45WLUxekBE58AayfsJz/w6BWqfJg7LgDrl+j2wzFIqsIgtzO+zJmqUTXW
vKl+ZOTRRBCI1TQj9WYmAGlsvX6yIVbkOB0i5gxWRdkszNzk2y83oJ/LrIDvR7o1Fm/XzzDkJUIf
zjy7PoAXj7vZqc73mx0skCNp7Fl6qtadPDG3UUS55uaFQdU895Lm5FbJe3anid0unDOJTwN5JleK
D0V5t4jx5t7oeJd1zFqHHFlmBWnGCrwGap2trMN0ZFIzQINnMdQHrajjVDWFE+cRvca5mVrmPWi/
DZaOwr39VyUj3t1XrB0POB/+ybcL5nugYLpjOCSrr1vuGdi3bAJli1jqoEBymWqWkmlxr7AIPrOm
f5dpgpXLO5zx6Zta2bH7Bo2CF6y6hXyOlyaqsyPR53GvpIOht86TuLuRDf/vmqsx7jZusu4OdIZd
nYTSeKo0AeexqM5xfFYhD7END+uxi9KxZSc45VMGP0oaNyJO7WylaU7uDIw+HcbBE1V+5ByFVg+M
vhEmYI3geQAqzFMyrXuqvbQ/fWHjrZl1wOY8Q9+e2zvilqNZH7OqFyEG1movG4WsOf+Lffxo4Jhw
W110fdYlH+doSKWtXtHIyms8fHOeNeQHn/NZrZQZr3YY5Q7Ru9kgIFDKvqBBdxBw2fGrxJyJeVVa
jIh/5yq5PEQcBzLlj0p90vum0ldesA8IQrBJslAEchiiIdb3sF3hZ4T7faSX/qBaB2fBO6ikrMdx
kpGvjWjYShaeTruKtbfUK83Sf+Q2ZcyvXUiI2fFyNoY93zPyNTEBPjF71pwPgjmGi2xMW/Q8AUb4
RO+NTJZR8YEzNGO2wU5t/i91LetMSgNCzODExTfBxx5Z8EjDrabmTE1I5G96AgKv4uls0PqGKDtA
lux1GNIIJSHE6yk+pw7ZDnBRAfzroPpZD8joes3WJPTsiNWGlH0+Mnu/bPypi/66U4h3RBMjM0Li
YSSk1BLv4xsuHXR0eo2G5XEwnWfO1Wi5zTQUYiZaKCAZ9vecEHqHeFWln5xPa72RS9vi2r3fmUPP
3lkd084pdxWaTcAmf6pLTeINeLrxCQPhLljS0pQewBPkSk19dAA9jTicoDStQ3pZJj0Uc9HflLPx
mXdrnQbRg3mc45hqajtrQRRS5/nIlDDiKPUc8sZT0SsWE0+Lb+lKyAsGGzKypWGXxUjH9K5egQCB
k5WQyskYNI+UHDWIACCK2wYIYm0ICIBEf9URZW90CQyOuCpS2AbQwRqx6s7515txbCtnpEiTrMvX
XqH2ds0inETlVduYs9STPLAOnzhXax9AMJF9MusTVswIfhWdnRJW7vva4gMhAarrn3Zi3sjK3Cv6
bJQquMFg8vs8nLyPHp2zKvW9b7rVA1HU407Fx9lFkxiU9g1+4BfrRwGrmJ95Cj2alCtk8vFsQQFt
LndnhPJhQA19qk22bucWwriPeIR6kCnmL5XNyA2+VYofdewsMzE409r8ocyNwVRVk54abXahhM9K
vk+LrAX5ZQyXGtwt4x3/rf6L4LW7Zx8SJY8QsBGtKopV2faJbKRMuMCVaKHjhYw2hUJyiwZyldBz
93D1pxrx+T+tP2UrBrXq7qgtq24puuispTUL+XjaubpmFRSKr7SoCIXQFv+zCmIQNxIyYV4xLDCe
srVpyfyAhOuFwVKKggRa3EIw2KUWd8+HfTK+r5qqWHHjTHAiULG+71FOiaWQGgwn+w5MtPl1s/Yu
LifQasSFI1xWmrtmpD+15ZwNBk9+vXkPycKQrGeEvvQEd7thIbQ2t7wEw9WE7X8P2y3iKUoc+u3X
ALFLW2EFXFYajJF/bcKJui5caWPxRcgFyXMZoTOKQBpfh+7FOJ6x79G6DLNjlJsZFNeqkStqwfAR
naSZmsifbqTssUfgtkdvTsEHyHrzOWIjEVSaCA8Bc9drNH6qA4b+rv+hUWpjJ11jOJiQU2IIEj4R
kJEUbfoKGnkHjnyMQ/khQn57Pk8et+Cb+nGxZI1AmUjL/krXpo+3dp3EHgD+8CcGEL2b2UkqnkoE
otbNVWQyJu/noK0LCDp1q+FsDII7Y7h6PejAo63SRO6oIty6XApsFMiJQ6+Z/fdsNZ7Ksnn6sm/j
YG1rfANuFkTCA1JDhLVADNu3GpjO96j3hCQv8TC/TiCTSHmjDil/KPK6fHxLJYGy22KkL1gqtCxH
3B4yr2U71+/Uc3HZtns+c1ar2eA5czdzlfqkm2ndVmB/ReWDAep6vzfeQI6kjQfVsKaQSHAafbAX
kahc6AeP3bwzHh7z2ki/ql+yzD3DBAVrj5AxEvS/yo/Q+FspIBDMJxDQMDZduXFEGJ4lI8JAaXK2
J7+baieUSCgudeDcMHZld/+MXQhxXU21o35n/PH64PQioEnDGKVqbPsFEgvecbe4RkPmxYLk3hJ9
jdA8/3bf7Hs7w7iHP33oxzE+Uw8/6uAkwWc3dfG0Fhiu07aXxKDklyA5Oilr4ekN2G1b98tXAymX
1eSoYQBJ1zGNsbFtf8U61QqMmG8zAu38kgjK72MOEH/kyTOv1b5B+lz2vXZVNguEIKXK8KZmLAN+
oPdZKuPLuHLfnSmoJd+2MaMHODJFImVldE/IaR2Pka86FGB/1vXDLZyO9bFMx/GdKj0X30hrdH4F
nwvFPJjjhNfz5Qvcn6IfGavbwUhG6Rucl56Kf1YfQ1lQ2ayVEbZxNM7DQ2hUT/tHKybdJtt+Uvu7
5tUtRnFpti/KD+MWmH3Y3O15EGDQ63e+74y5SiAoqHTJ0vVNoj8g4agegoXG/SFCgZ7f4w6/mAJR
mXwHhUkxUX+yodF9erOEazoMGJqzDhPeyRKVb7/uSdH/Uf5CVWL6D181sSZ1R3bs2L0BPvW2u2/7
Uma7vZnk3GGS8Aah6tlPndkIjNFo6hU5+2VmOJiPxuSVi8lIHuHRRG5Xk+y82cMHXaL+kqyfJW8c
6ry1zIZIDXS954b1OixiBLjZbopAd0ILdn5eLX7YrVpBoyc38iVZqJSxmWxaKgrws91MWGhFVvM7
+kHdSxbTyC7EzvkcTm+LFC7Ny+89qtFA0GeAdQoAjUfFfGsEU+1yeUA4YXn5PzVR/1WX2GSilwg5
o+cKk8v7hvfMCVk28d7JHTvHC4fSRWHmEyePnPLcxs4QytkTz6p5/K3JXy4sSGrYhET5KJsQmg+a
bUtgCJLmzigsX7duYydEo4eXQdwQaped
`protect end_protected
|
--============================================================================
--!
--! \file generic_ocram_tb
--!
--! \project generic_ocram
--!
--! \langv VHDL-2008
--!
--! \brief Testbench for component generic_ocram.
--!
--! \details -
--!
--! \bug -
--!
--! \see -
--!
--! \copyright GPLv2
--!
--! Revision history:
--!
--! \version 0.1
--! \date 2016-03-23
--! \author Andreas Mueller
--! \brief Create file.
--!
--============================================================================
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library work;
use work.generic_ocram_pkg;
entity generic_ocram_tb is
end entity generic_ocram_tb;
architecture tb of generic_ocram_tb is
-- DUT generics.
constant WIDTH : integer := 8;
constant DEPTH : integer := 1024;
constant READ_FIRST : boolean := TRUE;
-- DUT port signals.
signal clk : std_logic := '0';
signal rst : std_logic := '1';
signal addr : std_logic_vector(generic_ocram_pkg.log2c(DEPTH)-1 downto 0);
signal wren : std_logic;
signal datai : std_logic_vector(WIDTH-1 downto 0);
signal datao : std_logic_vector(WIDTH-1 downto 0);
-- Testbench.
constant CLK_PERIOD : time := 10 ns;
procedure sim_generic_ocram_write(
constant C_ADDR : in std_logic_vector(addr'range);
constant C_DATA : in std_logic_vector(WIDTH-1 downto 0);
signal clk_i : in std_logic;
signal addr_o : out std_logic_vector(addr'range);
signal wren_o : out std_logic;
signal data_o : out std_logic_vector(WIDTH-1 downto 0)
) is
begin
wait until rising_edge(clk_i);
addr_o <= C_ADDR;
wren_o <= '1';
data_o <= C_DATA;
wait until rising_edge(clk_i);
wren_o <= '0';
report "Wrote "&integer'image(to_integer(unsigned(C_DATA)))&
" to address "&integer'image(to_integer(unsigned(C_ADDR)));
end procedure sim_generic_ocram_write;
procedure sim_generic_ocram_read(
constant C_ADDR : in std_logic_vector(addr'range);
signal clk_i : in std_logic;
signal addr_o : out std_logic_vector(addr'range);
signal data_i : in std_logic_vector(WIDTH-1 downto 0)
) is
begin
wait until rising_edge(clk_i);
addr_o <= C_ADDR;
wait until rising_edge(clk_i);
wait until rising_edge(clk_i);
report "Read "&integer'image(to_integer(unsigned(data_i)))&
" from address "&integer'image(to_integer(unsigned(C_ADDR)));
end procedure sim_generic_ocram_read;
begin
p_testbench: process is
begin
report "### Simulation started.";
rst <= '1';
addr <= (others => '0');
wren <= '0';
datai <= (others => '1');
wait for 100 ns;
sim_generic_ocram_write(
C_ADDR => "0000000001",
C_DATA => X"39",
clk_i => clk,
addr_o => addr,
wren_o => wren,
data_o => datai
);
sim_generic_ocram_write(
C_ADDR => "1111111111",
C_DATA => X"72",
clk_i => clk,
addr_o => addr,
wren_o => wren,
data_o => datai
);
sim_generic_ocram_read(
C_ADDR => "0000000001",
clk_i => clk,
addr_o => addr,
data_i => datao
);
sim_generic_ocram_read(
C_ADDR => "1111111111",
clk_i => clk,
addr_o => addr,
data_i => datao
);
assert FALSE
report "### Simulation finished."
severity note;
wait;
end process p_testbench;
clk <= not clk after CLK_PERIOD/2;
i_generic_ocram_dut: generic_ocram_pkg.generic_ocram
generic map (
WIDTH => WIDTH,
DEPTH => DEPTH,
READ_FIRST => READ_FIRST
)
port map (
clk_i => clk,
rst_i => rst,
addr_i => addr,
wren_i => wren,
data_i => datai,
data_o => datao
);
end architecture tb;
|
architecture RTL of FIFO is begin end architecture FIFO;
-- Violations below
architecture RTL of FIFO is begin end architecture FIFO;
library ieee;
-- Last line in the file is okay
architecture RTL of FIFO is begin end architecture FIFO;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_7 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_7 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 7, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_7 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_7 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 7, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_7 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_7 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 7, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_7 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_7 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 7, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity function_7 is
port(
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_2 : in std_logic_vector(31 downto 0);
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of function_7 is
begin
-------------------------------------------------------------------------
computation : process (INPUT_1, INPUT_2)
variable rTemp1 : UNSIGNED(31 downto 0);
variable rTemp2 : UNSIGNED(31 downto 0);
variable rTemp3 : UNSIGNED(31 downto 0);
begin
rTemp1 := UNSIGNED( INPUT_1 );
rTemp2 := UNSIGNED( INPUT_2 );
rTemp3 := rTemp1 + rTemp2 + TO_UNSIGNED( 7, 32);
OUTPUT_1 <= STD_LOGIC_VECTOR( rTemp3 );
end process;
-------------------------------------------------------------------------
end; --architecture logic
|
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00598
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 6.3 (5)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00598)
-- ENT00598_Test_Bench(ARCH00598_Test_Bench)
--
-- REVISION HISTORY:
--
-- 21-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES; use STANDARD_TYPES.all ;
architecture ARCH00598 of E00000 is
begin
P :
process
function f ( x : integer ) return STANDARD_TYPES.st_rec3 is
variable a : STANDARD_TYPES.st_rec3 := c_st_rec3_2 ;
begin
return a ;
end f ;
function "+" ( a,b : STANDARD_TYPES.st_rec3 )
return STANDARD_TYPES.st_rec3 is
variable c : STANDARD_TYPES.st_rec3 ;
begin
"+".c := a ; -- prefix is an operator symbol
return c ;
end "+" ;
variable b1,b2,b3,b4,b5 : boolean := c_boolean_1 ;
variable j : integer := 3 ;
variable a : STANDARD_TYPES.st_rec3 := c_st_rec3_2;
variable b : STANDARD_TYPES.st_arr3 := c_st_arr3_2;
attribute rec_attr : STANDARD_TYPES.st_rec3 ;
attribute rec_attr of a : variable is c_st_rec3_2 ;
begin
b1 := a.f1 ; -- prefix is a simple name
b2 := a.f2.f1 ; -- prefix is a selected name
b3 := b(b'left(1),b'left(2)).f1 ; -- prefix is an indexed name
b4 := f(j).f1 ; -- prefix is a function call
b5 := a'rec_attr.f1 ; -- prefix is an attribute name
test_report ( "ARCH00598" ,
"Prefixes of selected names" ,
(b1 = c_boolean_2) and
(b2 = c_boolean_2) and
(b3 = c_boolean_2) and
(b4 = c_boolean_2) and
(b5 = c_boolean_2)
) ;
wait ;
end process P ;
end ARCH00598 ;
--
entity ENT00598_Test_Bench is
end ENT00598_Test_Bench ;
architecture ARCH00598_Test_Bench of ENT00598_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00598 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00598_Test_Bench ;
--
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Multiplier_GF_2_M
-- Module Name: Multiplier_GF_2_M
-- Project Name: GF_2_M Arithmetic
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The multiplier for GF(2^m) arithmetic.
-- This circuit works through a pure combinatorial strategy.
-- This circuit generates all partial products and them XOR them altogether.
--
-- The circuits parameters
--
-- gf_2_m :
--
-- The size of the field used in this circuit.
--
-- Dependencies:
-- VHDL-93
--
-- product_generator_gf_2_m Rev 1.0
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity mult_gf_2_m is
Generic(gf_2_m : integer range 1 to 20);
Port(
a : in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
b: in STD_LOGIC_VECTOR((gf_2_m - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end mult_gf_2_m;
architecture Behavioral of mult_gf_2_m is
component product_generator_gf_2_m
Generic(
value : integer;
m : integer range 2 to 20
);
Port (
a : in STD_LOGIC_VECTOR ((m - 1) downto 0);
o : out STD_LOGIC_VECTOR ((m - 1) downto 0)
);
end component;
type vector is array(integer range <>) of std_logic_vector((gf_2_m - 1) downto 0);
signal a_mult : vector(0 to (gf_2_m - 1));
signal b_mult : vector(0 to (gf_2_m - 1));
signal a_product_b : vector(0 to (gf_2_m - 1));
--for all : product_generator_gf_2_m use entity work.product_generator_gf_2_m(Software_POLYNOMIAL);
begin
x : for I in 0 to (gf_2_m - 1) generate
PGx : entity work.product_generator_gf_2_m(Software_POLYNOMIAL)
Generic Map(
value => I,
m => gf_2_m)
Port Map(
a => a,
o => a_mult(I)
);
b_mult(I) <= (others => b(I));
a_product_b(I) <= a_mult(I) and b_mult(I);
end generate;
GF_2_1 : if gf_2_m = 1 generate
o <= a and b;
end generate;
GF_2_2 : if gf_2_m = 2 generate
o <= a_product_b(1) xor a_product_b(0);
end generate;
GF_2_3 : if gf_2_m = 3 generate
o <= a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_4 : if gf_2_m = 4 generate
o <= a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_5 : if gf_2_m = 5 generate
o <= a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_6 : if gf_2_m = 6 generate
o <= a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_7 : if gf_2_m = 7 generate
o <= a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_8 : if gf_2_m = 8 generate
o <= a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_9 : if gf_2_m = 9 generate
o <= a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_10 : if gf_2_m = 10 generate
o <= a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_11 : if gf_2_m = 11 generate
o <= a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_12 : if gf_2_m = 12 generate
o <= a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_13 : if gf_2_m = 13 generate
o <= a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_14 : if gf_2_m = 14 generate
o <= a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_15 : if gf_2_m = 15 generate
o <= a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_16 : if gf_2_m = 16 generate
o <= a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_17 : if gf_2_m = 17 generate
o <= a_product_b(16) xor a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_18 : if gf_2_m = 18 generate
o <= a_product_b(17) xor a_product_b(16) xor a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_19 : if gf_2_m = 19 generate
o <= a_product_b(18) xor a_product_b(17) xor a_product_b(16) xor a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
GF_2_20 : if gf_2_m = 20 generate
o <= a_product_b(19) xor a_product_b(18) xor a_product_b(17) xor a_product_b(16) xor a_product_b(15) xor a_product_b(14) xor a_product_b(13) xor a_product_b(12) xor a_product_b(11) xor a_product_b(10) xor a_product_b(9) xor a_product_b(8) xor a_product_b(7) xor a_product_b(6) xor a_product_b(5) xor a_product_b(4) xor a_product_b(3) xor a_product_b(2) xor a_product_b(1) xor a_product_b(0);
end generate;
end Behavioral;
|
entity staticwait is
end entity;
architecture test of staticwait is
signal x : integer;
begin
process (x) is
begin
x <= 0;
end process;
end architecture;
|
entity staticwait is
end entity;
architecture test of staticwait is
signal x : integer;
begin
process (x) is
begin
x <= 0;
end process;
end architecture;
|
entity staticwait is
end entity;
architecture test of staticwait is
signal x : integer;
begin
process (x) is
begin
x <= 0;
end process;
end architecture;
|
entity staticwait is
end entity;
architecture test of staticwait is
signal x : integer;
begin
process (x) is
begin
x <= 0;
end process;
end architecture;
|
-------------------------------------------------------------------------------
--! @file axiLiteMasterWrapper-rtl-ea.vhd
--
--! @brief AXI lite master wrapper on avalon master interface signals
--
--! @details This will convert avalon master interface signals to AXI master
--! interface signals.
--
-------------------------------------------------------------------------------
--
-- Copyright (c) 2014, Bernecker+Rainer Industrie-Elektronik Ges.m.b.H. (B&R)
-- Copyright (c) 2014, Kalycito Infotech Private Limited.
--- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--! Use standard ieee library
library ieee;
--! Use logic elements
use ieee.std_logic_1164.all;
--! Use libcommon library
library libcommon;
--! Use Global Library
use libcommon.global.all;
entity axiLiteMasterWrapper is
generic (
--! Address width for AXI bus interface
gAddrWidth : integer := 32;
--! Data width for AXI bus interface
gDataWidth : integer := 32
);
port (
--! Global Clock for AXI
iAclk : in std_logic;
--! Global Reset for AXI
inAReset : in std_logic;
--! Address for Write Address Channel
oAwaddr : out std_logic_vector(gAddrWidth-1 downto 0);
--! Protection for Write Address Channel
oAwprot : out std_logic_vector(2 downto 0);
--! AddressValid for Write Address Channel
oAwvalid : out std_logic;
--! AddressReady for Write Address Channel
iAwready : in std_logic;
--! WriteData for Write Data Channel
oWdata : out std_logic_vector(gDataWidth-1 downto 0);
--! WriteStrobe for Write Data Channel
oWstrb : out std_logic_vector(gDataWidth/8-1 downto 0);
--! WriteValid for Write Data Channel
oWvalid : out std_logic;
--! WriteReady for Write Data Channel
iWready : in std_logic;
--! WriteLast for Write Data Channel to indicate last write operations
oWlast : out std_logic;
--! WriteResponse for Write Response Channel
iBresp : in std_logic_vector(1 downto 0); --unused input
--! ResponseValid for Write Response Channel
iBvalid : in std_logic;
--! ResponaseReady for Write Response Channel
oBready : out std_logic;
--! ReadAddress for Read Address Channel
oAraddr : out std_logic_vector(gAddrWidth-1 downto 0);
--! ReadAddressProtection for Read Address Channel
oArprot : out std_logic_vector(2 downto 0);
--! ReadAddressValid for Read Address Channel
oArvalid : out std_logic;
--! ReadAddressReady for Read Address Channel
iArready : in std_logic;
--! ReadData for Read Data Channel
iRdata : in std_logic_vector(gDataWidth-1 downto 0);
--TODO: Remove unused input pin
--! ReadResponse for Read Data Channel
iRresp : in std_logic_vector(1 downto 0);
--! ReadValid for Read Data Channel
iRvalid : in std_logic;
--! ReadReady for Read Data Channel
oRready : out std_logic;
--! Host Interface IP Clock
iAvalonClk : in std_logic;
--! Host Interface Reset
iAvalonReset : in std_logic;
--! Read signal for Avalon Master Interface
iAvalonRead : in std_logic;
--! Write Signal for Avalon Master interface
iAvalonWrite : in std_logic;
--! Address for Avalon Master Interface
iAvalonAddr : in std_logic_vector(gAddrWidth-1 downto 0);
--! Byte Enable for Avalon Master interface
iAvalonBE : in std_logic_vector(3 downto 0);
--! Wait request for Avalon Master Interface
oAvalonWaitReq : out std_logic;
--! Wait Request for Avalon Master Interface
oAvalonReadValid : out std_logic;
--! Read Data for Avalon Master Interface
oAvalonReadData : out std_logic_vector(gDataWidth-1 downto 0);
--! Write Data for Avaon Master Interface
iAvalonWriteData : in std_logic_vector(gDataWidth-1 downto 0)
);
end axiLiteMasterWrapper;
architecture rtl of axiLiteMasterWrapper is
--! Axi-lite master FSM type
type tFsm is (
sINIT,
sAWVALID,
sWVALID,
sBREADY,
sARVALID,
sRREADY,
sWRITE_DONE,
sREAD_DONE
);
--! synchronized fsm state
signal fsm : tFsm;
--! combinational fsm state
signal fsm_next : tFsm;
--! Avalon Interface sync FSM
type tAvalonFsm is (
sStart,
sWait,
sDone
);
--! synchronized Avalon fsm state
signal avmFsm : tAvalonFsm ;
--! combinational fsm sate for Avalon fsm
signal avmFsm_next : tAvalonFsm ;
--Handle Avalon Master
--! Avalon Address
signal avmAddress : std_logic_vector (31 downto 0);
--! Avalon Address temporary signal
signal avmAddress_next : std_logic_vector (31 downto 0);
--! Avalon Read Signal
signal avmRead : std_logic;
--! Avalon Read Signal temporary signal
signal avmRead_next : std_logic;
--! Avalon Write Signal
signal avmWrite : std_logic;
--! Avalon Write Signal temporary signal
signal avmWrite_next : std_logic;
--! Avalon Write Data
signal avmWdata : std_logic_vector (31 downto 0);
--! Avalon Write Data Signal temporary signal
signal avmWdata_next : std_logic_vector (31 downto 0);
--! Avalon Read Data
signal avmRdata : std_logic_vector (31 downto 0);
--! Avalon Read Data temporary Signal
signal avmRdata_next : std_logic_vector (31 downto 0);
--! Avalon start operation
signal avmStart : std_logic;
--! Avalon start operation temporary signal
signal avmStart_next : std_logic;
--! Avalon Byte Enable
signal avmBE : std_logic_vector (3 downto 0);
--! Avalon Byte Enable Signal temporary signal
signal avmBE_next : std_logic_vector (3 downto 0);
--! Avalon Wait Signal
signal avmWait : std_logic;
-- Handle Avalon Master
--! Complete transfer between AXI and Avalon
signal done_transfer : std_logic;
--! Read Ready for Valid Read operations
signal RReady : std_logic;
--! Write operation complete
signal writeOp_done : std_logic;
--! Read operation complete
signal readOp_done : std_logic;
--! Read Data latch for hold data
signal readData : std_logic_vector(31 downto 0);
begin
--AXI Master Signals
-- Secure write is not enabled for read/write operations
oAwprot <= "000";
oArprot <= "000";
--Master signal for AXI interface
oAwaddr <= avmAddress;
oAraddr <= avmAddress;
oWdata <= avmWdata;
-- Only read or write at a time and Read will always 32bit
oWstrb <= avmBE;
-- Memory operations (AXI4) demands presence of WLAST (active for last data)
oWlast <= cActivated;
oAwvalid <= cActivated when fsm = sINIT and avmWrite = cActivated else
cActivated when fsm = sAWVALID else
cInactivated;
oWvalid <= cActivated when fsm = sINIT and avmWrite = cActivated else
cActivated when fsm = sAWVALID else
cActivated when fsm = sWVALID else
cInactivated;
oBready <= cActivated when fsm = sWRITE_DONE and iBvalid = cActivated else
cActivated when fsm = sBREADY else
cInactivated;
oArvalid <= cActivated when fsm = sINIT and avmRead = cActivated else
cActivated when fsm = sARVALID else
cInactivated;
RReady <= cActivated when fsm = sREAD_DONE and iRvalid = cActivated else
cInactivated;
oRready <= RReady;
-- Flop with Enable pin? Anyway passed through a register on Avalon side to
-- avoid latch issues.
--FIXME: bring into fsm
--! Hold the data while it is valid
REG_RDATA: process(iAclk)
begin
if rising_edge (iAclk) then
if inAReset = cnActivated then
readData <= x"00000000";
elsif(iRvalid = cActivated) then
readData <= iRdata;
end if;
end if;
end process REG_RDATA;
RReady <= cActivated when fsm = sREAD_DONE and iRvalid = cActivated else
cInactivated;
-- Completion of Read/Write Operations
done_transfer <= writeOp_done or readOp_done;
writeOp_done <= cActivated when fsm = sWRITE_DONE else
cInactivated;
readOp_done <= cActivated when fsm = sREAD_DONE else
cInactivated;
-- Master FSM
--TODO: Explain logic if possible with Diagram in doxygen
--! Clock Based Process for tFsm changes
SEQ_LOGIC : process(iAclk)
begin
if rising_edge (iAclk) then
if inAReset = cnActivated then
fsm <= sINIT;
else
fsm <= fsm_next;
end if;
end if;
end process SEQ_LOGIC;
-- Combinational Logics
--TODO: Explain logic if possible with Diagram in doxygen
--! Master FSM for AXI-lite interface
COMB_LOGIC : process (
fsm,
avmRead,
avmWrite,
avmStart,
iAwready,
iWready,
iBvalid,
iArready,
iRvalid
)
begin
-- Default Values for signals
fsm_next <= fsm;
case fsm is
when sINIT =>
-- Read Operations
if avmRead = cActivated then
fsm_next <= sARVALID;
if iArready = cActivated then
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
else
fsm_next <= sARVALID;
end if;
-- Write Operations
elsif avmWrite = cActivated then
fsm_next <= sAWVALID;
if iAwready = cActivated then
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
else
fsm_next <= sAWVALID;
end if;
else
fsm_next <= sINIT;
end if;
when sAWVALID =>
if iAwready = cActivated then
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
else
fsm_next <= sAWVALID;
end if;
when sWVALID =>
if iWready = cActivated then
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
else
fsm_next <= sWVALID;
end if;
when sBREADY =>
if iBvalid = cActivated then
fsm_next <= sWRITE_DONE;
else
fsm_next <= sBREADY;
end if;
when sARVALID =>
if iArready = cActivated then
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
else
fsm_next <= sARVALID;
end if;
when sRREADY =>
if iRvalid = cActivated then
fsm_next <= sREAD_DONE;
else
fsm_next <= sRREADY;
end if;
when sWRITE_DONE =>
--Wait for Complete activity at avalon side
if(avmStart = cInactivated) then
fsm_next <= sINIT;
else
fsm_next <= sWRITE_DONE;
end if;
when sREAD_DONE =>
--Wait for Complete activity at avalon side
if(avmStart = cInactivated) then
fsm_next <= sINIT;
else
fsm_next <= sREAD_DONE;
end if;
when others =>
null;
end case;
end process COMB_LOGIC;
-- Avalon Interface signal crossing through FSM Register the inputs from
-- Avalon and Pass to AXI to avoid glitches on Master side due to different
-- clock domains
--! Sync Clock domains between Avalon & AXI through a handshaking system
AVM_SYNC: process (iAvalonClk)
begin
if rising_edge (iAvalonClk) then
if iAvalonReset = cActivated then
avmFsm <= sStart;
avmAddress <= x"00000000";
avmRead <= cInactivated;
avmWrite <= cInactivated;
avmRdata <= x"00000000";
avmWdata <= x"00000000";
avmStart <= cInactivated;
avmBE <= x"0";
else
avmFsm <= avmFsm_next ;
avmAddress <= avmAddress_next;
avmRead <= avmRead_next;
avmWrite <= avmWrite_next;
avmRdata <= avmRdata_next;
avmWdata <= avmWdata_next;
avmStart <= avmStart_next;
avmBE <= avmBE_next;
end if;
end if;
end process AVM_SYNC;
-- Split the design for better timing
--! Combinational logic part for FSM
AVM_COM: process ( iAvalonRead,
iAvalonWrite,
iAvalonWriteData,
iAvalonAddr,
iAvalonBE,
readData,
done_transfer,
avmFsm,
avmRead,
avmWrite,
avmStart,
avmAddress,
avmRdata,
avmWdata,
avmBE
)
begin
--Default/Initialization of temporary registers
avmFsm_next <= avmFsm ;
avmAddress_next <= avmAddress;
avmRead_next <= avmRead;
avmWrite_next <= avmWrite;
avmRdata_next <= avmRdata;
avmWdata_next <= avmWdata;
avmStart_next <= avmStart;
avmBE_next <= avmBE;
case avmFsm is
when sStart =>
avmAddress_next <= iAvalonAddr ;
avmBE_next <= iAvalonBE ;
if iAvalonRead = cActivated then
avmFsm_next <= sWait;
avmStart_next <= cActivated ;
avmRead_next <= cActivated ;
elsif iAvalonWrite = cActivated then
avmFsm_next <= sWait;
avmStart_next <= cActivated ;
avmWrite_next <= cActivated;
avmWdata_next <= iAvalonWriteData;
else
avmFsm_next <= sStart;
avmStart_next <= cInactivated ;
avmRead_next <= cInactivated ;
avmWrite_next <= cInactivated;
avmWdata_next <= x"00000000";
end if;
--Wait until the transfer get completed at AXI
when sWait =>
avmStart_next <= avmStart;
avmRead_next <= avmRead ;
avmWrite_next <= avmWrite;
if(done_transfer = cActivated) then
avmFsm_next <= sDone;
-- Only for Read operations
if(iAvalonRead = cActivated) then
avmRdata_next <= readData;
else
avmRdata_next <= avmRdata;
end if;
else
avmFsm_next <= sWait;
end if;
-- Handshake between two FSM domains
when sDone =>
if (done_transfer = cActivated) then
avmRead_next <= cInactivated ;
avmWrite_next <= cInactivated;
avmStart_next <= cInactivated ;
avmFsm_next <= sStart;
else
avmRead_next <= avmRead ;
avmWrite_next <= avmWrite;
avmStart_next <= avmStart;
avmFsm_next <= sDone;
end if;
end case;
end process AVM_COM;
--Avalon Interface signals
oAvalonReadData <= readData;
oAvalonReadValid <= not avmWait;
oAvalonWaitReq <= avmWait;
avmWait <= cInactivated when avmFsm = sDone else
cActivated ;
end rtl;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test limited length strings in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_string_lim is
port (start : in std_logic;
res : out std_logic);
end entity vhdl_string_lim;
architecture test of vhdl_string_lim is
begin
process (start)
variable a : string;
variable b : string(1 to 1);
variable c : string(1 to 5);
begin
a := "test string";
b := "a";
c := "abcde";
res <= (a = "test string") and (b = "a") and (c = "abcde");
end process;
end architecture test;
|
-- Copyright (c) 2015 CERN
-- Maciej Suminski <[email protected]>
--
-- This source code is free software; you can redistribute it
-- and/or modify it in source code form under the terms of the GNU
-- General Public License as published by the Free Software
-- Foundation; either version 2 of the License, or (at your option)
-- any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA
-- Test limited length strings in VHDL.
library ieee;
use ieee.std_logic_1164.all;
entity vhdl_string_lim is
port (start : in std_logic;
res : out std_logic);
end entity vhdl_string_lim;
architecture test of vhdl_string_lim is
begin
process (start)
variable a : string;
variable b : string(1 to 1);
variable c : string(1 to 5);
begin
a := "test string";
b := "a";
c := "abcde";
res <= (a = "test string") and (b = "a") and (c = "abcde");
end process;
end architecture test;
|
----------------------------------------------------------------------------------
-- dac_mkid_interface : DAC board with two DAC5681 for I and Q signals
----------------------------------------------------------------------------------
-- Authors: Sean McHugh, Bruno Serfass, Ran Duan
-- Create Date: 09/02/09
-- modification:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.vcomponents.all;
--------------------------------------------------------------------------------
-- Entity section
--------------------------------------------------------------------------------
entity dac_mkid_interface is
Generic (
OUTPUT_CLK : INTEGER := 0;
CTRL_CLK_PHASE : INTEGER := 0
);
Port (
--------------------------------------
-- differential signals from/to DAC
--------------------------------------
-- clock from DAC
dac_clk_p : in STD_LOGIC;
dac_clk_n : in STD_LOGIC;
-- clock to DAC
dac_smpl_clk_i_p : out STD_LOGIC;
dac_smpl_clk_i_n : out STD_LOGIC;
dac_smpl_clk_q_p : out STD_LOGIC;
dac_smpl_clk_q_n : out STD_LOGIC;
-- enable analog output for DAC
dac_sync_i_p : out STD_LOGIC;
dac_sync_i_n : out STD_LOGIC;
dac_sync_q_p : out STD_LOGIC;
dac_sync_q_n : out STD_LOGIC;
-- data written to DAC
dac_data_i_p : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_i_n : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_q_p : out STD_LOGIC_VECTOR (15 downto 0);
dac_data_q_n : out STD_LOGIC_VECTOR (15 downto 0);
-- configuration ports of DAC
dac_not_sdenb_i : out STD_LOGIC;
dac_not_sdenb_q : out STD_LOGIC;
dac_sclk : out STD_LOGIC;
dac_sdi : out STD_LOGIC;
dac_not_reset : out STD_LOGIC;
-- dac_phase : in STD_LOGIC;
--------------------------------------
-- signals from/to design
--------------------------------------
-- defined in xps_dac_mkid.m
dac_smpl_clk : in STD_LOGIC;
-- defined in dac_mkid yellow block and dac_mkid_mask.m
dac_data_i0 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_i1 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_q0 : in STD_LOGIC_VECTOR (15 downto 0);
dac_data_q1 : in STD_LOGIC_VECTOR (15 downto 0);
dac_sync_i : in STD_LOGIC;
dac_sync_q : in STD_LOGIC;
-- serial ports
not_sdenb_i : in STD_LOGIC;
not_sdenb_q : in STD_LOGIC;
sclk : in STD_LOGIC;
sdi : in STD_LOGIC;
not_reset : in STD_LOGIC;
-- phase : out STD_LOGIC
-- clock to FPGA
dac_clk_out : out STD_LOGIC;
dac_clk90_out : out STD_LOGIC;
dac_clk180_out : out STD_LOGIC;
dac_clk270_out : out STD_LOGIC;
-- dcm lock
dac_dcm_locked : out STD_LOGIC
);
end dac_mkid_interface;
--------------------------------------------------------------------------------
-- Architecture section
--------------------------------------------------------------------------------
architecture Structural of dac_mkid_interface is
signal data_i : STD_LOGIC_VECTOR (15 downto 0);
signal data_q : STD_LOGIC_VECTOR (15 downto 0);
signal smpl_clk : STD_LOGIC;
signal dac_clk_in : STD_LOGIC;
signal dac_clk : STD_LOGIC;
signal dcm_clk : STD_LOGIC;
signal dcm_clk90 : STD_LOGIC;
signal dcm_clk180 : STD_LOGIC;
signal dcm_clk270 : STD_LOGIC;
signal clk : STD_LOGIC;
signal clk90 : STD_LOGIC;
signal clk180 : STD_LOGIC;
signal clk270 : STD_LOGIC;
begin
-----------------------------------------------------------------------
-- Serial input (DAC configuration)
-----------------------------------------------------------------------
OBUF_inst_not_sdenb_i : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_sdenb_i,
I => not_sdenb_i
);
OBUF_inst_not_sdenb_q : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_sdenb_q,
I => not_sdenb_q
);
OBUF_inst_sclk : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_sclk,
I => sclk
);
OBUF_inst_sdi : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_sdi,
I => sdi
);
OBUF_inst_not_reset : OBUF
generic map (
IOSTANDARD => "DEFAULT")
Port map (
O => dac_not_reset,
I => not_reset
);
-------------------------------------------------------------------
-- Sample clock in to DAC. "dac_smpl_clk_i_p/n" is a DDR clock. --
-------------------------------------------------------------------
BUFG_inst : BUFG
port map (O => smpl_clk,I => dac_smpl_clk);
OBUFDS_inst_smpl_clk_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_smpl_clk_i_p,
OB => dac_smpl_clk_i_n,
I => smpl_clk
);
OBUFDS_inst_smpl_clk_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_smpl_clk_q_p,
OB => dac_smpl_clk_q_n,
I => smpl_clk
);
----------------------------------
-- Enable analog output for DAC --
----------------------------------
OBUFDS_inst_dac_sync_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_sync_i_p,
OB => dac_sync_i_n,
I => dac_sync_i
);
OBUFDS_inst_dac_sync_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_sync_q_p,
OB => dac_sync_q_n,
I => dac_sync_q
);
-----------------------------------------------------------------------
-- DAC data outputs
-- Requires an ODDR to double the data rate, and an
-- OBUFDS to convert to differential signal.
-----------------------------------------------------------------------
-- DAC output I --
ODDR_inst_generate_data_i : for j in 0 to 15 generate
ODDR_inst_data_i : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => data_i(j),
C => smpl_clk,
CE => '1',
D1 => dac_data_i0(j),
D2 => dac_data_i1(j),
R => '0',
S => '0'
);
end generate;
OBUFDS_inst_generate_data_i : for j in 0 to 15 generate
OBUFDS_inst_data1_i : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_data_i_p(j),
OB => dac_data_i_n(j),
I => data_i(j)
);
end generate;
-- DAC output Q --
ODDR_inst_generate_data_q : for j in 0 to 15 generate
ODDR_inst_data_q : ODDR
generic map (
DDR_CLK_EDGE => "SAME_EDGE",
INIT => '0',
SRTYPE => "SYNC")
port map (
Q => data_q(j),
C => smpl_clk,
CE => '1',
D1 => dac_data_q0(j),
D2 => dac_data_q1(j),
R => '0',
S => '0'
);
end generate;
OBUFDS_inst_generate_data1_q : for j in 0 to 15 generate
OBUFDS_inst_data1_q : OBUFDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_data_q_p(j),
OB => dac_data_q_n(j),
I => data_q(j)
);
end generate;
-----------------------------------------------------------------------
-- Clock Management
-----------------------------------------------------------------------
GEN_DCM : if OUTPUT_CLK = 1 generate
IBUFDS_inst_dac_clk : IBUFGDS
generic map (
IOSTANDARD => "LVDS_25")
port map (
O => dac_clk_in,
I => dac_clk_p,
IB => dac_clk_n
);
BUFG_clk_dac : BUFG
port map (I => dac_clk_in, O => dac_clk);
BUFG_clk : BUFG
port map (I => dcm_clk, O => clk);
BUFG_clk90 : BUFG
port map (I => dcm_clk90, O => clk90);
BUFG_clk180 : BUFG
port map (I => dcm_clk180, O => clk180);
BUFG_clk270 : BUFG
port map (I => dcm_clk270, O => clk270);
-- out clock to fpga
dac_clk_out <= clk;
dac_clk90_out <= clk90;
dac_clk180_out <= clk180;
dac_clk270_out <= clk270;
-- DCM
CLK_DCM : DCM
generic map(
CLK_FEEDBACK => "1X",
CLKDV_DIVIDE => 2.000000,
CLKFX_DIVIDE => 1,
CLKFX_MULTIPLY => 4,
CLKIN_DIVIDE_BY_2 => FALSE,
CLKIN_PERIOD => 0.000000,
CLKOUT_PHASE_SHIFT => "NONE",
DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
DFS_FREQUENCY_MODE => "HIGH",
DLL_FREQUENCY_MODE => "HIGH",
DUTY_CYCLE_CORRECTION => TRUE,
FACTORY_JF => x"F0F0",
PHASE_SHIFT => 0,
STARTUP_WAIT => FALSE)
port map (
CLKFB => clk,
CLKIN => dac_clk,
DSSEN => '0',
PSCLK => '0',
PSEN => '0',
PSINCDEC => '0',
RST => '0',
CLKDV => open,
CLKFX => open,
CLKFX180 => open,
CLK0 => dcm_clk,
CLK2X => open,
CLK2X180 => open,
CLK90 => dcm_clk90,
CLK180 => dcm_clk180,
CLK270 => dcm_clk270,
LOCKED => dac_dcm_locked,
PSDONE => open,
STATUS => open
);
end generate;
end Structural;
|
--
-- Copyright (C) 2011 Chris McClelland
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity TopLevel is
port(
-- Main 50MHz clock
clk : in std_logic;
-- Reset button (BTN0)
reset : in std_logic;
-- Host interface signals
eppDataBus : inout std_logic_vector(7 downto 0);
eppAddrStrobe : in std_logic;
eppDataStrobe : in std_logic;
eppReadNotWrite : in std_logic;
eppAck : out std_logic
);
end TopLevel;
architecture Behavioural of TopLevel is
type State is (
STATE_IDLE,
STATE_ADDR_WRITE_EXEC,
STATE_ADDR_WRITE_ACK,
STATE_DATA_WRITE_EXEC,
STATE_DATA_WRITE_ACK,
STATE_DATA_READ_EXEC,
STATE_DATA_READ_ACK
);
-- State and next-state
signal iThisState, iNextState : State;
-- Synchronised versions of asynchronous inputs
signal iSyncAddrStrobe : std_logic;
signal iSyncDataStrobe : std_logic;
signal iSyncReadNotWrite : std_logic;
-- Data to be mux'd back to host
signal iDataOutput : std_logic_vector(7 downto 0);
-- Registers
signal iThisRegAddr, iNextRegAddr : std_logic_vector(1 downto 0);
signal iThisAck, iNextAck : std_logic;
signal iThisR0, iNextR0 : std_logic_vector(7 downto 0);
signal iThisR1, iNextR1 : std_logic_vector(7 downto 0);
signal iThisR2, iNextR2 : std_logic_vector(7 downto 0);
signal iThisR3, iNextR3 : std_logic_vector(7 downto 0);
begin
-- Drive the outputs
eppAck <= iThisAck;
-- EPP operation
eppDataBus <=
iDataOutput when ( eppReadNotWrite = '1' ) else
"ZZZZZZZZ";
with ( iThisRegAddr ) select
iDataOutput <=
iThisR0 when "00",
iThisR1 when "01",
iThisR2 when "10",
iThisR3 when others;
-- Infer registers
process(clk, reset)
begin
if ( reset = '1' ) then
iThisState <= STATE_IDLE;
iThisRegAddr <= (others => '0');
iThisR0 <= (others => '0');
iThisR1 <= (others => '0');
iThisR2 <= (others => '0');
iThisR3 <= (others => '0');
iThisAck <= '0';
iSyncAddrStrobe <= '1';
iSyncDataStrobe <= '1';
iSyncReadNotWrite <= '1';
elsif ( clk'event and clk = '1' ) then
iThisState <= iNextState;
iThisRegAddr <= iNextRegAddr;
iThisR0 <= iNextR0;
iThisR1 <= iNextR1;
iThisR2 <= iNextR2;
iThisR3 <= iNextR3;
iThisAck <= iNextAck;
iSyncAddrStrobe <= eppAddrStrobe;
iSyncDataStrobe <= eppDataStrobe;
iSyncReadNotWrite <= eppReadNotWrite;
end if;
end process;
-- Next state logic
process(
eppDataBus, iThisState, iThisRegAddr,
iSyncAddrStrobe, iSyncDataStrobe, iSyncReadNotWrite,
iThisR0, iThisR1, iThisR2, iThisR3)
begin
iNextAck <= '0';
iNextState <= STATE_IDLE;
iNextRegAddr <= iThisRegAddr;
iNextR0 <= iThisR0;
iNextR1 <= iThisR1;
iNextR2 <= iThisR2;
iNextR3 <= iThisR3;
case iThisState is
when STATE_IDLE =>
if ( iSyncAddrStrobe = '0' ) then
-- Address can only be written, not read
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_ADDR_WRITE_EXEC;
end if;
elsif ( iSyncDataStrobe = '0' ) then
-- Register read or write
if ( iSyncReadNotWrite = '0' ) then
iNextState <= STATE_DATA_WRITE_EXEC;
else
iNextState <= STATE_DATA_READ_EXEC;
end if;
end if;
-- Write address register
when STATE_ADDR_WRITE_EXEC =>
iNextRegAddr <= eppDataBus(1 downto 0);
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '0';
when STATE_ADDR_WRITE_ACK =>
if ( iSyncAddrStrobe = '0' ) then
iNextState <= STATE_ADDR_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Write data register
when STATE_DATA_WRITE_EXEC =>
case iThisRegAddr is
when "00" =>
iNextR0 <= eppDataBus;
when "01" =>
iNextR1 <= eppDataBus;
when "10" =>
iNextR2 <= eppDataBus;
when others =>
iNextR3 <= eppDataBus;
end case;
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
when STATE_DATA_WRITE_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_WRITE_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Read data register
when STATE_DATA_READ_EXEC =>
iNextAck <= '1';
iNextState <= STATE_DATA_READ_ACK;
when STATE_DATA_READ_ACK =>
if ( iSyncDataStrobe = '0' ) then
iNextState <= STATE_DATA_READ_ACK;
iNextAck <= '1';
else
iNextState <= STATE_IDLE;
iNextAck <= '0';
end if;
-- Some unknown state
when others =>
iNextState <= STATE_IDLE;
end case;
end process;
end Behavioural;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for struct of dac
--
-- Generated
-- by: wig
-- on: Thu Feb 10 19:03:15 2005
-- cmd: H:/work/eclipse/MIX/mix_0.pl -strip -nodelta ../../bugver.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: dac-struct-a.vhd,v 1.2 2005/04/14 06:52:59 wig Exp $
-- $Date: 2005/04/14 06:52:59 $
-- $Log: dac-struct-a.vhd,v $
-- Revision 1.2 2005/04/14 06:52:59 wig
-- Updates: fixed import errors and adjusted I2C parser
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.49 2005/01/27 08:20:30 wig Exp
--
-- Generator: mix_0.pl Revision: 1.33 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture struct of dac
--
architecture struct of dac is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component dac_ctrl --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for i_dac_ctrl
i_dac_ctrl: dac_ctrl
;
-- End of Generated Instance Port Map for i_dac_ctrl
end struct;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity foo is
port ( encoded : in integer);
end;
architecture foo of foo is
type some_type is (foo, bar, baz);
function decode( constant v : integer ) return some_type is
begin
return some_type'val(v);
end;
function decode( constant v : string ) return some_type is
begin
return some_type'value(v);
end;
signal decoded_from_slv : some_type;
signal decoded_from_string : some_type;
begin
decoded_from_slv <= decode(encoded);
decoded_from_string <= decode(string'("foo"));
end;
|
-------------------------------------------------------------------------------
-- axi_sg_ftch_queue
-------------------------------------------------------------------------------
--
-- *************************************************************************
--
-- (c) Copyright 2010, 2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_ftch_queue.vhd
-- Description: This entity is the descriptor fetch queue interface
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_sg.vhd
-- axi_sg_pkg.vhd
-- |- axi_sg_ftch_mngr.vhd
-- | |- axi_sg_ftch_sm.vhd
-- | |- axi_sg_ftch_pntr.vhd
-- | |- axi_sg_ftch_cmdsts_if.vhd
-- |- axi_sg_updt_mngr.vhd
-- | |- axi_sg_updt_sm.vhd
-- | |- axi_sg_updt_cmdsts_if.vhd
-- |- axi_sg_ftch_q_mngr.vhd
-- | |- axi_sg_ftch_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_ftch_noqueue.vhd
-- |- axi_sg_updt_q_mngr.vhd
-- | |- axi_sg_updt_queue.vhd
-- | | |- proc_common_v4_0.sync_fifo_fg.vhd
-- | |- proc_common_v4_0.axi_sg_afifo_autord.vhd
-- | |- axi_sg_updt_noqueue.vhd
-- |- axi_sg_intrpt.vhd
-- |- axi_datamover_v5_0.axi_datamover.vhd
--
-------------------------------------------------------------------------------
-- Author: Gary Burch
-- History:
-- GAB 3/19/10 v1_00_a
-- ^^^^^^
-- - Initial Release
-- ~~~~~~
-- GAB 7/27/10 v1_00_a
-- ^^^^^^
-- CR569609
-- Remove double driven signal for exclude update engine mode
-- ~~~~~~
-- GAB 8/26/10 v2_00_a
-- ^^^^^^
-- Rolled axi_sg library version to version v2_00_a
-- ~~~~~~
-- GAB 10/21/10 v4_03
-- ^^^^^^
-- Rolled version to v4_03
-- ~~~~~~
-- GAB 11/15/10 v2_01_a
-- ^^^^^^
-- CR582800
-- Converted all stream paraters ***_DATA_WIDTH to ***_TDATA_WIDTH
-- ~~~~~~
-- GAB 6/13/11 v4_03
-- ^^^^^^
-- Update to AXI Datamover v4_03
-- Added aynchronous operation
-- ~~~~~~
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_vdma_v6_2;
use axi_vdma_v6_2.axi_sg_pkg.all;
library lib_pkg_v1_0;
library lib_fifo_v1_0;
use lib_fifo_v1_0.sync_fifo_fg;
use lib_pkg_v1_0.lib_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_ftch_q_mngr is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width
C_M_AXIS_SG_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Stream Data width
C_AXIS_IS_ASYNC : integer range 0 to 1 := 0;
-- Channel 1 is async to sg_aclk
-- 0 = Synchronous to SG ACLK
-- 1 = Asynchronous to SG ACLK
C_SG_FTCH_DESC2QUEUE : integer range 0 to 8 := 0;
-- Number of descriptors to fetch and queue for each channel.
-- A value of zero excludes the fetch queues.
C_SG_CH1_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH2_WORDS_TO_FETCH : integer range 4 to 16 := 8;
-- Number of words to fetch for channel 1
C_SG_CH1_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_SG_CH2_ENBL_STALE_ERROR : integer range 0 to 1 := 1;
-- Enable or disable stale descriptor check
-- 0 = Disable stale descriptor error check
-- 1 = Enable stale descriptor error check
C_INCLUDE_CH1 : integer range 0 to 1 := 1;
-- Include or Exclude channel 1 scatter gather engine
-- 0 = Exclude Channel 1 SG Engine
-- 1 = Include Channel 1 SG Engine
C_INCLUDE_CH2 : integer range 0 to 1 := 1;
-- Include or Exclude channel 2 scatter gather engine
-- 0 = Exclude Channel 2 SG Engine
-- 1 = Include Channel 2 SG Engine
C_FAMILY : string := "virtex6"
-- Device family used for proper BRAM selection
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
ch1_desc_flush : in std_logic ; --
ch1_ftch_active : in std_logic ; --
ch1_nxtdesc_wren : out std_logic ; --
ch1_ftch_queue_empty : out std_logic ; --
ch1_ftch_queue_full : out std_logic ; --
ch1_ftch_pause : out std_logic ; --
--
-- Channel 2 Control --
ch2_desc_flush : in std_logic ; --
ch2_ftch_active : in std_logic ; --
ch2_nxtdesc_wren : out std_logic ; --
ch2_ftch_queue_empty : out std_logic ; --
ch2_ftch_queue_full : out std_logic ; --
ch2_ftch_pause : out std_logic ; --
nxtdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
-- DataMover Command --
ftch_cmnd_wr : in std_logic ; --
ftch_cmnd_data : in std_logic_vector --
((C_M_AXI_SG_ADDR_WIDTH+CMD_BASE_WIDTH)-1 downto 0); --
ftch_stale_desc : out std_logic ; --
--
-- MM2S Stream In from DataMover --
m_axis_mm2s_tdata : in std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_mm2s_tkeep : in std_logic_vector --
((C_M_AXIS_SG_TDATA_WIDTH/8)-1 downto 0); --
m_axis_mm2s_tlast : in std_logic ; --
m_axis_mm2s_tvalid : in std_logic ; --
m_axis_mm2s_tready : out std_logic ; --
--
--
-- Channel 1 AXI Fetch Stream Out --
m_axis_ch1_ftch_aclk : in std_logic ;
m_axis_ch1_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0); --
m_axis_ch1_ftch_tvalid : out std_logic ; --
m_axis_ch1_ftch_tready : in std_logic ; --
m_axis_ch1_ftch_tlast : out std_logic ; --
--
--
-- Channel 2 AXI Fetch Stream Out --
m_axis_ch2_ftch_aclk : in std_logic ; --
m_axis_ch2_ftch_tdata : out std_logic_vector --
(C_M_AXIS_SG_TDATA_WIDTH-1 downto 0) ; --
m_axis_ch2_ftch_tvalid : out std_logic ; --
m_axis_ch2_ftch_tready : in std_logic ; --
m_axis_ch2_ftch_tlast : out std_logic --
);
end axi_sg_ftch_q_mngr;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_ftch_q_mngr is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Determine the maximum word count for use in setting the word counter width
-- Set bit width on max num words to fetch
constant FETCH_COUNT : integer := max2(C_SG_CH1_WORDS_TO_FETCH
,C_SG_CH2_WORDS_TO_FETCH);
-- LOG2 to get width of counter
constant WORDS2FETCH_BITWIDTH : integer := clog2(FETCH_COUNT);
-- Zero value for counter
constant WORD_ZERO : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= (others => '0');
-- One value for counter
constant WORD_ONE : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(1,WORDS2FETCH_BITWIDTH));
-- Seven value for counter
constant WORD_SEVEN : std_logic_vector(WORDS2FETCH_BITWIDTH-1 downto 0)
:= std_logic_vector(to_unsigned(7,WORDS2FETCH_BITWIDTH));
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
signal m_axis_mm2s_tready_i : std_logic := '0';
signal ch1_ftch_tready : std_logic := '0';
signal ch2_ftch_tready : std_logic := '0';
-- Misc Signals
signal writing_curdesc : std_logic := '0';
signal fetch_word_count : std_logic_vector
(WORDS2FETCH_BITWIDTH-1 downto 0) := (others => '0');
signal msb_curdesc : std_logic_vector(31 downto 0) := (others => '0');
signal lsbnxtdesc_tready : std_logic := '0';
signal msbnxtdesc_tready : std_logic := '0';
signal nxtdesc_tready : std_logic := '0';
signal ch1_writing_curdesc : std_logic := '0';
signal ch2_writing_curdesc : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
---------------------------------------------------------------------------
-- For 32-bit SG addresses then drive zero on msb
---------------------------------------------------------------------------
GEN_CURDESC_32 : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
msb_curdesc <= (others => '0');
end generate GEN_CURDESC_32;
---------------------------------------------------------------------------
-- For 64-bit SG addresses then capture upper order adder to msb
---------------------------------------------------------------------------
GEN_CURDESC_64 : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
CAPTURE_CURADDR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
msb_curdesc <= (others => '0');
elsif(ftch_cmnd_wr = '1')then
msb_curdesc <= ftch_cmnd_data(DATAMOVER_CMD_ADDRMSB_BOFST
+ C_M_AXI_SG_ADDR_WIDTH
downto DATAMOVER_CMD_ADDRMSB_BOFST
+ DATAMOVER_CMD_ADDRLSB_BIT + 1);
end if;
end if;
end process CAPTURE_CURADDR;
end generate GEN_CURDESC_64;
-------------------------------------------------------------------------------
-- Fetch Stream Word Counter
-- The process is used to determine when to strip off NextDesc pointer from
-- stream and when to look at control word for complete bit set.
-------------------------------------------------------------------------------
REG_WORD_COUNTER : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
-- Clear on reset and on datamover command write
if(m_axi_sg_aresetn = '0' or ftch_cmnd_wr = '1'
or (m_axis_mm2s_tlast = '1' and m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tready_i = '1'))then
fetch_word_count <= (others => '0');
-- If both tvalid=1 and tready = 1 then count
elsif(m_axis_mm2s_tvalid = '1' and m_axis_mm2s_tready_i = '1')then
fetch_word_count <= std_logic_vector(unsigned(fetch_word_count
(WORDS2FETCH_BITWIDTH-1 downto 0)) + 1);
end if;
end if;
end process REG_WORD_COUNTER;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc(31 downto 0) <= (others => '0');
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and fetch_word_count = WORD_ZERO)then
nxtdesc(31 downto 0) <= m_axis_mm2s_tdata;
end if;
end if;
end process REG_LSB_NXTPNTR;
lsbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and fetch_word_count = WORD_ZERO
else '0';
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
nxtdesc(63 downto 32) <= (others => '0');
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Capture upper pointer, drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and fetch_word_count = WORD_ONE)then
nxtdesc(63 downto 32) <= m_axis_mm2s_tdata;
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert tready/wren for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and fetch_word_count = WORD_ONE
else '0';
end generate GEN_UPPER_MSB_NXTDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_NXTDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_NXTPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
-- Throw away second word but drive ready to progress DataMover
-- and also write nxtdesc out
elsif(m_axis_mm2s_tvalid = '1' and fetch_word_count = WORD_ONE)then
ch1_nxtdesc_wren <= ch1_ftch_active;
ch2_nxtdesc_wren <= ch2_ftch_active;
-- Assert for only 1 clock
else
ch1_nxtdesc_wren <= '0';
ch2_nxtdesc_wren <= '0';
end if;
end if;
end process REG_MSB_NXTPNTR;
msbnxtdesc_tready <= '1' when m_axis_mm2s_tvalid = '1'
and fetch_word_count = WORD_ONE
else '0';
end generate GEN_NO_UPR_MSB_NXTDESC;
-- Drive ready to DataMover for ether lsb or msb capture
nxtdesc_tready <= msbnxtdesc_tready or lsbnxtdesc_tready;
-- Generate logic for checking stale descriptor
GEN_STALE_DESC_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 1 or C_SG_CH2_ENBL_STALE_ERROR = 1 generate
begin
---------------------------------------------------------------------------
-- Examine Completed BIT to determine if stale descriptor fetched
---------------------------------------------------------------------------
CMPLTD_CHECK : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
ftch_stale_desc <= '0';
-- On valid and word count at 0 and channel active capture LSB next pointer
elsif(m_axis_mm2s_tvalid = '1' and fetch_word_count = WORD_SEVEN
and m_axis_mm2s_tready_i = '1'
and m_axis_mm2s_tdata(DESC_STS_CMPLTD_BIT) = '1' )then
ftch_stale_desc <= '1';
else
ftch_stale_desc <= '0';
end if;
end if;
end process CMPLTD_CHECK;
end generate GEN_STALE_DESC_CHECK;
-- No needed logic for checking stale descriptor
GEN_NO_STALE_CHECK : if C_SG_CH1_ENBL_STALE_ERROR = 0 and C_SG_CH2_ENBL_STALE_ERROR = 0 generate
begin
ftch_stale_desc <= '0';
end generate GEN_NO_STALE_CHECK;
-------------------------------------------------------------------------------
-- If channel 1 is included then generate ch1 logic
-------------------------------------------------------------------------------
GEN_CH1_FTCH_Q_IF : if C_INCLUDE_CH1 = 1 generate
begin
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_CH1_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_vdma_v6_2.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH1_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
ftch_pause => ch1_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axis_ch1_ftch_aclk ,
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast
);
end generate GEN_CH1_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_CH1_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_vdma_v6_2.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel Control
desc_flush => ch1_desc_flush ,
ftch_active => ch1_ftch_active ,
ftch_queue_empty => ch1_ftch_queue_empty ,
ftch_queue_full => ch1_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch1_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch1_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch1_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch1_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch1_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch1_ftch_tlast
);
ch1_ftch_pause <= '0';
end generate GEN_NO_CH1_QUEUE;
end generate GEN_CH1_FTCH_Q_IF;
-------------------------------------------------------------------------------
-- Channel 1 excluded so tie outputs low
-------------------------------------------------------------------------------
GEN_NO_CH1_FTCH_Q_IF : if C_INCLUDE_CH1 = 0 generate
begin
ch1_ftch_queue_empty <= '0';
ch1_ftch_queue_full <= '0';
ch1_ftch_pause <= '0';
ch1_writing_curdesc <= '0';
ch1_ftch_tready <= '0';
m_axis_ch1_ftch_tdata <= (others => '0');
m_axis_ch1_ftch_tlast <= '0';
m_axis_ch1_ftch_tvalid <= '0';
end generate GEN_NO_CH1_FTCH_Q_IF;
-------------------------------------------------------------------------------
-- If channel 2 is included then generate ch1 logic
-------------------------------------------------------------------------------
GEN_CH2_FTCH_Q_IF : if C_INCLUDE_CH2 = 1 generate
begin
---------------------------------------------------------------------------
-- SG Queueing therefore pass stream signals to
-- FIFO
---------------------------------------------------------------------------
GEN_CH2_QUEUE : if C_SG_FTCH_DESC2QUEUE /= 0 generate
begin
-- Instantiate the queue version
FTCH_QUEUE_I : entity axi_vdma_v6_2.axi_sg_ftch_queue
generic map(
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH ,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH ,
C_SG_FTCH_DESC2QUEUE => C_SG_FTCH_DESC2QUEUE ,
C_SG_WORDS_TO_FETCH => C_SG_CH2_WORDS_TO_FETCH ,
C_AXIS_IS_ASYNC => C_AXIS_IS_ASYNC ,
C_FAMILY => C_FAMILY
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel Control
desc_flush => ch2_desc_flush ,
ftch_active => ch2_ftch_active ,
ftch_queue_empty => ch2_ftch_queue_empty ,
ftch_queue_full => ch2_ftch_queue_full ,
ftch_pause => ch2_ftch_pause ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch2_ftch_tready ,
-- Channel 1 AXI Fetch Stream Out
m_axis_ftch_aclk => m_axis_ch2_ftch_aclk ,
m_axis_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch2_ftch_tlast
);
end generate GEN_CH2_QUEUE;
-- No SG Queueing therefore pass stream signals straight
-- out channel port
GEN_NO_CH2_QUEUE : if C_SG_FTCH_DESC2QUEUE = 0 generate
begin
-- Instantiate the No queue version
NO_FTCH_QUEUE_I : entity axi_vdma_v6_2.axi_sg_ftch_noqueue
generic map (
C_M_AXI_SG_ADDR_WIDTH => C_M_AXI_SG_ADDR_WIDTH,
C_M_AXIS_SG_TDATA_WIDTH => C_M_AXIS_SG_TDATA_WIDTH
)
port map(
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk => m_axi_sg_aclk ,
m_axi_sg_aresetn => m_axi_sg_aresetn ,
-- Channel Control
desc_flush => ch2_desc_flush ,
ftch_active => ch2_ftch_active ,
ftch_queue_empty => ch2_ftch_queue_empty ,
ftch_queue_full => ch2_ftch_queue_full ,
writing_nxtdesc_in => nxtdesc_tready ,
writing_curdesc_out => ch2_writing_curdesc ,
-- DataMover Command
ftch_cmnd_wr => ftch_cmnd_wr ,
ftch_cmnd_data => ftch_cmnd_data ,
-- MM2S Stream In from DataMover
m_axis_mm2s_tdata => m_axis_mm2s_tdata ,
m_axis_mm2s_tlast => m_axis_mm2s_tlast ,
m_axis_mm2s_tvalid => m_axis_mm2s_tvalid ,
m_axis_mm2s_tready => ch2_ftch_tready ,
-- Channel 2 AXI Fetch Stream Out
m_axis_ftch_tdata => m_axis_ch2_ftch_tdata ,
m_axis_ftch_tvalid => m_axis_ch2_ftch_tvalid ,
m_axis_ftch_tready => m_axis_ch2_ftch_tready ,
m_axis_ftch_tlast => m_axis_ch2_ftch_tlast
);
ch2_ftch_pause <= '0';
end generate GEN_NO_CH2_QUEUE;
end generate GEN_CH2_FTCH_Q_IF;
-------------------------------------------------------------------------------
-- Channel 2 excluded so tie outputs low
-------------------------------------------------------------------------------
GEN_NO_CH2_FTCH_Q_IF : if C_INCLUDE_CH2 = 0 generate
begin
ch2_ftch_queue_empty <= '0';
ch2_ftch_queue_full <= '0';
ch2_ftch_pause <= '0';
ch2_writing_curdesc <= '0';
ch2_ftch_tready <= '0';
m_axis_ch2_ftch_tdata <= (others => '0');
m_axis_ch2_ftch_tlast <= '0';
m_axis_ch2_ftch_tvalid <= '0';
end generate GEN_NO_CH2_FTCH_Q_IF;
-------------------------------------------------------------------------------
-- DataMover TREADY MUX
-------------------------------------------------------------------------------
writing_curdesc <= ch1_writing_curdesc or ch2_writing_curdesc or ftch_cmnd_wr;
TREADY_MUX : process(writing_curdesc,
fetch_word_count,
nxtdesc_tready,
-- channel 1 signals
ch1_ftch_active,
ch1_desc_flush,
ch1_ftch_tready,
-- channel 2 signals
ch2_ftch_active,
ch2_desc_flush,
ch2_ftch_tready)
begin
-- If commmanded to flush descriptor then assert ready
-- to datamover until active de-asserts. this allows
-- any commanded fetches to complete.
if( (ch1_desc_flush = '1' and ch1_ftch_active = '1')
or(ch2_desc_flush = '1' and ch2_ftch_active = '1'))then
m_axis_mm2s_tready_i <= '1';
-- NOT ready if cmnd being written because
-- curdesc gets written to queue
elsif(writing_curdesc = '1')then
m_axis_mm2s_tready_i <= '0';
-- First two words drive ready from internal logic
elsif(fetch_word_count = WORD_ZERO or fetch_word_count = WORD_ONE)then
m_axis_mm2s_tready_i <= nxtdesc_tready;
-- Remainder stream words drive ready from channel input
else
m_axis_mm2s_tready_i <= (ch1_ftch_active and ch1_ftch_tready)
or (ch2_ftch_active and ch2_ftch_tready);
end if;
end process TREADY_MUX;
m_axis_mm2s_tready <= m_axis_mm2s_tready_i;
end implementation;
|
entity tb_dff09 is
end tb_dff09;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_dff09 is
signal clk : std_logic;
signal rstn : std_logic;
signal din : std_logic;
signal dout : std_logic;
begin
dut: entity work.dff09
port map (
q => dout,
d => din,
clk => clk,
rstn => rstn);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
rstn <= '0';
wait for 1 ns;
assert dout = '0' severity failure;
rstn <= '1';
din <= '1';
pulse;
assert dout = '1' severity failure;
din <= '0';
pulse;
assert dout = '0' severity failure;
din <= '1';
pulse;
assert dout = '1' severity failure;
rstn <= '0';
wait for 1 ns;
assert dout = '0' severity failure;
wait;
end process;
end behav;
|
------------------------------------------------------------------------------------
-- --
-- Copyright (c) 2004, Hangouet Samuel --
-- , Jan Sebastien --
-- , Mouton Louis-Marie --
-- , Schneider Olivier all rights reserved --
-- --
-- This file is part of miniMIPS. --
-- --
-- miniMIPS is free software; you can redistribute it and/or modify --
-- it under the terms of the GNU Lesser General Public License as published by --
-- the Free Software Foundation; either version 2.1 of the License, or --
-- (at your option) any later version. --
-- --
-- miniMIPS is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU Lesser General Public License for more details. --
-- --
-- You should have received a copy of the GNU Lesser General Public License --
-- along with miniMIPS; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
------------------------------------------------------------------------------------
-- If you encountered any problem, please contact :
--
-- [email protected]
-- [email protected]
-- [email protected]
--
--------------------------------------------------------------------------
-- --
-- --
-- Processor miniMIPS : Memory access stage --
-- --
-- --
-- --
-- Authors : Hangouet Samuel --
-- Jan Sébastien --
-- Mouton Louis-Marie --
-- Schneider Olivier --
-- --
-- june 2003 --
--------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library work;
use work.pack_mips.all;
entity pps_mem is
port
(
clock : in std_logic;
reset : in std_logic;
stop_all : in std_logic; -- Unconditionnal locking of the outputs
clear : in std_logic; -- Clear the pipeline stage
-- Interface with the control bus
MTC_data : out bus32; -- Data to write in memory
MTC_adr : out bus32; -- Address for memory
MTC_r_w : out std_logic; -- Read/Write in memory
MTC_req : out std_logic; -- Request access to memory
CTM_data : in bus32; -- Data from memory
-- Datas from Execution stage
EX_adr : in bus32; -- Instruction address
EX_data_ual : in bus32; -- Result of alu operation
EX_adresse : in bus32; -- Result of the calculation of the address
EX_adr_reg_dest : in adr_reg_type; -- Destination register address for the result
EX_ecr_reg : in std_logic; -- Effective writing of the result
EX_op_mem : in std_logic; -- Memory operation needed
EX_r_w : in std_logic; -- Type of memory operation (read or write)
EX_exc_cause : in bus32; -- Potential exception cause
EX_level : in level_type; -- Availability stage for the result for bypassing
EX_it_ok : in std_logic; -- Allow hardware interruptions
-- Synchronous outputs for bypass unit
MEM_adr : out bus32; -- Instruction address
MEM_adr_reg_dest : out adr_reg_type; -- Destination register address
MEM_ecr_reg : out std_logic; -- Writing of the destination register
MEM_data_ecr : out bus32; -- Data to write (from alu or memory)
MEM_exc_cause : out bus32; -- Potential exception cause
MEM_level : out level_type; -- Availability stage for the result for bypassing
MEM_it_ok : out std_logic -- Allow hardware interruptions
);
end pps_mem;
architecture rtl of pps_mem is
signal tmp_data_ecr : bus32; -- Selection of the data source (memory or alu)
begin
-- Bus controler connexions
MTC_adr <= EX_adresse; -- Connexion of the address
MTC_r_w <= EX_r_w; -- Connexion of R/W
MTC_data <= EX_data_ual; -- Connexion of the data bus
MTC_req <= EX_op_mem and not clear; -- Connexion of the request (if there is no clearing of the pipeline)
-- Preselection of the data source for the outputs
tmp_data_ecr <= CTM_data when EX_op_mem = '1' else EX_data_ual;
-- Set the synchronous outputs
process (clock)
begin
if clock = '1' and clock'event then
if reset = '1' then
MEM_adr <= (others => '0');
MEM_adr_reg_dest <= (others => '0');
MEM_ecr_reg <= '0';
MEM_data_ecr <= (others => '0');
MEM_exc_cause <= IT_NOEXC;
MEM_level <= LVL_DI;
MEM_it_ok <= '0';
elsif stop_all = '0' then
if clear = '1' then -- Clear the stage
MEM_adr <= EX_adr;
MEM_adr_reg_dest <= (others => '0');
MEM_ecr_reg <= '0';
MEM_data_ecr <= (others => '0');
MEM_exc_cause <= IT_NOEXC;
MEM_level <= LVL_DI;
MEM_it_ok <= '0';
else -- Normal evolution
MEM_adr <= EX_adr;
MEM_adr_reg_dest <= EX_adr_reg_dest;
MEM_ecr_reg <= EX_ecr_reg;
MEM_data_ecr <= tmp_data_ecr;
MEM_exc_cause <= EX_exc_cause;
MEM_level <= EX_level;
MEM_it_ok <= EX_it_ok;
end if;
end if;
end if;
end process;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2481.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p01n02i02481ent IS
END c07s03b03x00p01n02i02481ent;
ARCHITECTURE c07s03b03x00p01n02i02481arch OF c07s03b03x00p01n02i02481ent IS
function f(a, b : INTEGER) return INTEGER is
begin
return a + b;
end;
BEGIN
TESTING: PROCESS
variable v : INTEGER := 0;
BEGIN
v := f(1, 2);
wait for 5 ns;
assert NOT( v=3 )
report "***PASSED TEST: c07s03b03x00p01n02i02481"
severity NOTE;
assert ( v=3 )
report "***FAILED TEST: c07s03b03x00p01n02i02481 - Function call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p01n02i02481arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2481.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p01n02i02481ent IS
END c07s03b03x00p01n02i02481ent;
ARCHITECTURE c07s03b03x00p01n02i02481arch OF c07s03b03x00p01n02i02481ent IS
function f(a, b : INTEGER) return INTEGER is
begin
return a + b;
end;
BEGIN
TESTING: PROCESS
variable v : INTEGER := 0;
BEGIN
v := f(1, 2);
wait for 5 ns;
assert NOT( v=3 )
report "***PASSED TEST: c07s03b03x00p01n02i02481"
severity NOTE;
assert ( v=3 )
report "***FAILED TEST: c07s03b03x00p01n02i02481 - Function call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p01n02i02481arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2481.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b03x00p01n02i02481ent IS
END c07s03b03x00p01n02i02481ent;
ARCHITECTURE c07s03b03x00p01n02i02481arch OF c07s03b03x00p01n02i02481ent IS
function f(a, b : INTEGER) return INTEGER is
begin
return a + b;
end;
BEGIN
TESTING: PROCESS
variable v : INTEGER := 0;
BEGIN
v := f(1, 2);
wait for 5 ns;
assert NOT( v=3 )
report "***PASSED TEST: c07s03b03x00p01n02i02481"
severity NOTE;
assert ( v=3 )
report "***FAILED TEST: c07s03b03x00p01n02i02481 - Function call test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b03x00p01n02i02481arch;
|
-- NEED RESULT: ARCH00476: Functions can return user defined types passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00476
--
-- AUTHOR:
--
-- D. Hyman
--
-- TEST OBJECTIVES:
--
-- 2.1 (8)
-- 2.1 (10)
--
-- DESIGN UNIT ORDERING:
--
-- GENERIC_STANDARD_TYPES(ARCH00476)
-- ENT00476_Test_Bench(ARCH00476_Test_Bench)
--
-- REVISION HISTORY:
--
-- 6-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
-- The various types are taken from GENERIC_STANDARD_TYPES without the
-- explicit qualifier, as is the resolution function bf_rec3.
--
--
use WORK.STANDARD_TYPES.test_report ;
architecture ARCH00476 of GENERIC_STANDARD_TYPES is
function t_enum1_func ( i : integer ) return t_enum1 is
begin
return t_enum1'val(i) ;
end t_enum1_func ;
function st_enum1_func ( i : integer ) return st_enum1 is
begin
return st_enum1'val(i) ;
end st_enum1_func ;
function t_int1_func ( i : t_int1 ) return t_int1 is
begin
return i + 1 ;
end t_int1_func ;
function st_int1_func ( i : st_int1 ) return st_int1 is
begin
return i + 1 ;
end st_int1_func ;
function t_phys1_func ( i : integer ) return t_phys1 is
begin
return i * phys1_2;
end t_phys1_func ;
function st_phys1_func ( i : integer ) return st_phys1 is
begin
return i * phys1_2;
end st_phys1_func ;
function t_real1_func ( r : t_real1 ) return t_real1 is
begin
return r + 1.0;
end t_real1_func ;
function st_real1_func ( r : st_real1 ) return st_real1 is
begin
return r + 1.0;
end st_real1_func ;
function t_rec1_func ( r : real ) return t_rec1 is
variable rec : t_rec1 ;
begin
rec.f1 := lowb_i2 ;
rec.f2 := 0 ns ;
rec.f3 := true ;
rec.f4 := r + 1.0 ;
return rec ;
end t_rec1_func ;
function st_arr1_func ( i : integer ) return st_arr1 is
variable arr : st_arr1 ;
begin
for j in lowb to highb loop
arr(j) := t_int1(i + j);
end loop ;
return arr ;
end st_arr1_func ;
begin
P :
process
variable vec : rec3_vector (1 to 3) ;
begin
test_report ( "ARCH00476" ,
"Functions can return user defined types" ,
(t_enum1_func(1) = en2) and
(st_enum1_func(1) = en2) and
(t_int1_func(10) = 11 ) and
(st_int1_func(10) = 11 ) and
(t_phys1_func(2) = 2 phys1_2 ) and
(st_phys1_func(2) = 2 phys1_2 ) and
(t_real1_func(10.0) = 11.0 ) and
(st_real1_func(10.0) = 11.0 ) and
(t_rec1_func(10.0).f4 = 11.0 )
) ;
wait ;
end process P ;
end ARCH00476 ;
entity ENT00476_Test_Bench is
end ENT00476_Test_Bench ;
architecture ARCH00476_Test_Bench of ENT00476_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.GENERIC_STANDARD_TYPES ( ARCH00476 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00476_Test_Bench ;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- Configuration file for a Xilinx VC707 board.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
--
--
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "VC707"; -- VC707 - Xilinx Virtex 7 reference design board: XC7V485T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
--
constant MY_VERBOSE : boolean := FALSE; -- activate detailed report statements in functions and procedures
end package;
|
library IEEE;
use IEEE.Std_Logic_1164.all;
entity C2 is
port (A: in std_logic;
B: in std_logic;
F: out std_logic
);
end C2;
architecture c2_estr of C2 is
begin
F <= A xor B;
end c2_estr; |
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IRpgDt8BiqXecl3SIeLzuGdulfgvitJy38JD0kErvZ/PDjzBOFVfE2PrAT2xnGXVTShzZ0AoywBQ
PGsD+PrKqg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ffvuSd0RkCu0VwbxkEteIatf7Q/78Uh0Bi3BxKkzyZxTzFukdrJMNWOctZPR+VDK1KgGzsPbIT3Z
/jNBCLoopQSYWXX0eL77a99OOQfcY6cvLH0ET9zYNApWLR0kNmeEJmwLdSeBG8iGkmPisf3Wm+aQ
GDL7Tav+Oqx0sQ1AC5M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OcxzCjyYK5ZF8gnPitOf5t0iAzStDgc7At/EhKCUCUmOSmYmX7NRELVjN/X7ZCVpQpvqpM+mYVNl
/7Y2+h3RNru1tHeU0rb5WsiCbrtUOwbzPNGhJEfd5L2O8TqQQV5lR/wa8dhqOsXbZC1F6lXJf0ql
vqrp9e+IcJPUMgd8M73FvGH/nzxSnxQoeWRW5q3QElDMofnGVLxppQSFMNzW6nEfVX78T0JKs8tl
T9LIdQd29+dRlnr5QZcMG9Hpkh1cQ1XVUNKFDtQXsF1f338EPabLKCcdD8+8F/ucluO5OqvB0dPY
XJpvjtfdEsFt6hTxRrSegLzZ7aMV1s1tmZOjKw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
rLXNrS2fxiCVUKaX3PNyDChS/B8QJkJ04uCa1A7iW5GHUS8OS0Et/wHOXbfRoddWP8I9gRzGx5Ua
9u1Gp0Tq7EFCWMPoUYuZbAJI2Hv50vnrighWaLWByZJ+eay+UxyioKlE5k6Xq4oVz/28qt3Otvey
Q0wkW30CTsbclTS5zNE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cbjon8h+WbIL/8BhMk4t2gMX6VUMZKPXeqfuMDXEiiY1+MlkvJmqBtmYA3DHoWJZEh9o4z9xPuoN
JmmNF95+IJUhWhYZ/3PSTYQaa2j6jmlSzNmv3FiDb+kefoEFg2BM7TtfBuiphA2+uptHKlQR88DU
YPp6UH6PmFv9MGyZlrBCTexGQ+Om3gN8LacqRP2J0qor/vRRaAiAIfvHgInHAMP4z3gZ7FWBYzyR
17rSCCkcEJsFH5T7tUT+tuwSyNsnJIGEYqSPaxHnNAZ/C0+3mOobjCgrplLQ0jJUD9T4KNEc6Oyb
L+EO3U2HZ8Nvl0Gi4RoVvc215n0nneFWAEkSZg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8448)
`protect data_block
E3Dlx8rND4TMEKlMYdUVTf77EyzW05pWXJ6GBR/BpPyYo5fyuXkGwPHn86OIdqIOZjpQog0lPTTa
VPcG6DSTCc2NtcxDfAfswX8wTWFZPW5HBaHizBc2ICnE/EiRP43858rq8H+COlcEkI0ViFBILHma
4cGh7pJoi101j3ym6GDK34493gy7ZbxPEMhhn91pGEBWF7SdGHxdzf1j7qPJ+0k0sHsKgvAHcB5U
Z/m4QffSY6Ly8Itm1mIad+7F0Bn1OVFYy9bfR1SmQE85YSauotvd5dXX3Ypk3PwqaYiCi63Ojo4d
aTMvYUSVZWmhiKhGRnmYH9UNJb83u6zmdD6WLaIIPEWg3H+xQ2BW4WqiIFm5SPbzrWMTGjPCISPD
950NQvrv+nhmxbQVo+9NuBnNmrO1WOljoqN9DH+UNb/cFuKmJRNGwT6X/lCHkXy/qQqxCrBrGajm
4y/l1F02aIw6iHDFNPu8u339EviiHafwr6tii0CeNEe17SAAe2I2YipY9G84Xl+HvHJ4mC37I/Bn
qcV7rIM22dng3I5B2tmDYncBH92rdLLan0JzLDbDpG7qgwJ7CpxYzdEc1Jn8ldayPBE2sUVJqre/
/5fJdVW+68dxmaJmojzqb1QhW5+WP7uSk6Ui0/5gCM9CV3c95whkl/rfTW9yP8ko7yLsig1wjrT/
gX+oBSO8P+x5/zR2Fq0nrHX8bEzqqRvy+WoMpjx4HIphETWDl/w3ujLZo5GABPII0Wu7tqPd5v2m
xKma+duowqfHjpnG0o1Iv4K88sgBpZr19/5eq4kD1vPVZG0RinHghauy48sPcVHe6AbmdJKAaQFD
J1K6WcEZ9ewkEG0QSNBCVXAhZ/QYtWh0U/8ypzo8vpBfs6N5l03HFkDCWf7EfaPWQn2koQGyG1pG
qxlSMRbU2JDMNTeeamT91J5i24nY2D7B0KDeIlyW0985jo5r3vErEh2Ix4dSljTVG5cPAzVoJ7KX
i/snBI0rtg5cFWiqRldpwF043S0AJddY6WngP9sJyI4VNm+/gQCRyGtAg9QlKHhZyGNHLFSwXba/
u7BbUlapxWmVFE2hs2biktWqnONsEHDbJBcXQOm750BSwIc3oc4VritCqWlEQwCtjQ6iVEECjZ45
kll2kok6/B+zR6oqAxBUoNPbrBbikQbY4PeJh9mBAtMnWs9gNzRmxFNaZ/+0awmU/FyrIkst8Hne
plm2KVwjMrHymlzk8W3V6mLadejjfIzS1AolVWl+RUqrNjRGSsWdPC+5/hxrbKDLkuMupUkH3fQ4
i4ujvoZVdiCCZrxKvsJ44q1eCEocjBT9JLQWzU8wPPMT8E43BlnOwS+Hu7KlaKDB+kBrQB8NKnRE
mNpxhp98XVJBdZt115YuBTuGgJqcJEzq3xTujocAzxp9R2jrkGOjw/0vuSOK2UjMSTnp1ijqxte8
ZQey08/6I4xV2CE8e2e7hbksgIHZ/N7d/OBBIJxrIhyRoYeBN1UMRWJRES54O328OTjQWMJHI7Ru
0Nh4B6xmh5NFGDfCbui7/12kCKCk+mDx2EYdkCaHP100/YhDFeDFDETh8/lDXucg2HoBPYBKdIkw
KkzUIDKw2b9uyqB0f/cxXnv4J44GjGXPEqBYU/NytbocrQ0Fy9pxbufw7HyD0vxjB4XeTmoi8Lk4
aWf8BZ4lZhSUS7H5T3HmMW2n66bYDohyogLmNrVEKPkkjJvvOKiGA6fZQPxbwDYMAAjD30oyfT9g
XXZU5Y3R4VALYEOdjAZuZ3NUW7dwxF9tZ2hzXvPyPD6eXiDYpKEg6pdYavnH8TE0e0WUveWo/Bwb
IH/g5d6VIHwiMGB7bhvMNvEIHAF8ZbRFmNQVU89A438tzPAcnuLFfp0I5ihj2TXV6MOHvqvYSzsm
J1FoftqWEvVns46VjijRziMYvzLWanbgAvUm6sPnLJ28jXd/DMHxQeGi6FctSW9hLg2msyiW9ZBU
hIfHKUFZf3e3CkN6oSJTY16kuyxjCMXMc1v8trSKDQ2DKmEx8KjpPXbs6E9BtVcySue3GvExMhvX
3JLPyfpmsE9Iist6Y0wUnLmzOMQPcXlZkom0YPvugxQEtosE0aV3HXwPXrhHlrALHV3HZwhrha3y
q//HQjnstM58HP0jSczyzeJ7YzrTiecQZ5MyuAz19zOcodmw392ObL2h2hMwWBiO/DdL7seKhNe1
i7eX0bFtKg4gcliUnxMs9t10sJUr+F51zHsWimvc2vSa/Yp7lsJmtERjL3x0z8tkr60+Z46Q2OYw
VTTPM9B9F7ux8rxYqwCie/v/7lZ102kFywHUOEis7tWBEJswRl/eYP1DK8D5eu+znhoyflG6nzN7
qVv08a6nldywRAcRdTcKN71NOPys76zgRDz33wuJYXUlyjgXYlsnorPVXtjP/r1xNHM+SiLU7LlR
dskM24cq+n/DKxCOjJDussU0MR+zUfTkldu4ALveIJA1LK9BuTD1eHA2pn+MN81lZTnOoSY+/08M
AU3hNSCxO2eLVFduyHGMn22PmYSTcoFzkDtPAFYsVlMPez7Wd6wSfuPb3TyfDQtN4WR34EoAaQDx
ZiFvKMHLN8nnXQEksflV1Atax9i0PwY56tsjHf0FAwoqXQMNK/HXj39Yy3wjiCXpFw/LyBngDzJ8
ARKb+B96FpJvcGIdjyCyhZkJAuiB987LIY6YMoRWeZIAl/Hrhii3W96dd/OmBEyr6AUns+a8+m+7
9ANYabaATzGGrLxZZmM1qE5rGxnhSe/fHDRQQaM1gGlkQ5jOPeX3vvNQDdWL5kcn6Q169UoSP7oD
+qkV+5euQpQrq0e62GdcSpGRHzNSgZCv/1/RTbTZRzGQjP5/ovzu+sS+R1ls5YSf4DXs88OfF/Fu
OI2xmOfzx1asco4NCRdv7Y9mQ4gXGM84HqzJKf65wytTtxSIDa5t3/ahUKaWwhakvkS0musiv1qr
nZMuIaJ6nC+btzbviid1NohrBufU3oY32AUSUVl5/XMI9mLhuJbvfE1gwT9kbUuo9436svNgKKQK
5OkW1ISM9PXsp29X38ewI4gsx7tMHmntDw9vaMYflD74x7lyD+2KpSedvW0CgwlKCDqhGIB1x7U8
9uC9QiJCw3C9i6vLVstqyJEnHo2aA9xDBXlq37cGwdaDzchm8en/3YZhzogaXyJEZb8oHGHZFpTf
IaK5YQzY0LOHy3YVTeqYQhlTWEfIoLsdGSBo1bsvDsC8AN/GpPbWclNQsBVDShx2VXVptxWEJJcn
wlnM4f2vC8z8h8JJ+ZGE5FIRhHaF1M57B9iO43z6C+IK1q9lRdeczFf+RfWF4ZYHShaY2GksnJhE
GXO9hlM1/DENndrTYtKMTVZfH8cF2pZFuQb7RD44jlEVLYr7PvlfXzAcNY5QX+0r79lVECLmSv0c
Ekni4FCVwK2h1EMZIcOE/q/vD5UPsTsH5yCajNz4giKF3IY1Gtu/crhfMqvWEPFrqnUGyb7jZjwK
HACMc70qhYozamoFCOFYZFDFoTmwq1sY7ZBNlZkjDWwDqp062Cfawu1vn95X4cQ/iYq/R2jZN8t1
NSVFRaDw6Ee5k3mqeD5PXCy36bUtbTdvcS02s3/CCHqYHh2dpkbkft6JjSL/yzNlPEwN1mtsYRK9
P/qWBf4MXR/Zg79wELdY9sM6ljB6klLIsDa3IITPzwZeB/y+xR5f19GtDRNki8DqVdqx2NAs1ccP
K9viZhosrddaunKUxXMRJXgXYvMuR1NfD7j4bSopsE3QqqJZRYLYLJhXqg6H6y5FnXNdakcSqIMp
Avt0ZY1+rOqqENQ6kNw/KomowI/iKoZ/WI5ddjthhC3j2D1KRnSgHXxf1pNhNPrV64vHYl3733nG
RHFywzEVy50KAoCtWTSbAxsofSq5BXSRx28NQIUGbf8sSWKlYCn80tpBgLXlR1rQ6tt6nDEdoMTX
d0Ti6CdLll3NuAmT0LgaEWg7+sTRIM55vVtd4DmVlT0xP3Mzxs24SnGQFgDh0kaGpCdyyRaLbtjA
eR2052HNL+QU+lee8u9j+Id/GgW1awIoPxwm0CHCcXni/NtRwcmVjMIl/4SUEl1EeDkJTZy6gsWz
fISTqA7DBYzAHy+mq38zY3DbAUv4ayLnm9jAwlfJ/N+ok3McFVbqEWPk8VXJkYx29uVnlRcTdvCM
GWXk3W7UF6kMCNPtzk31Wgijo9IifWfSKKhLRz3XyuZjhLqneI1+XvQqFQ7r9wvPKMP30lme9DkT
Sx5ZdVqvb/kM7dUkqcbWkW8MAmRELy/ngEoAvHzzUDq++5qHXURLAjvt3OGDnChear3ZFUAUmnkG
9YWxMDCRezxeUYM19VOQb6j12LdmyBmI3myH7ITm0cmD0+e0g9/PZN5cWEPQtY8O6fN5OiuFBRoM
9mjDBS1uQIE1F0+SZSGOfeAR5sHLCx6o2fghPWAU3HneUBiDQhvtn/ALbTHpIDeTQTMCZj8k3j+U
NyCzrN1MpO24xxLDjAU30/jNumOl7P4WyAu+6Gdlr9bF0pJURbodhrWf+BT0TOTG/Tw825SeayNW
teKgx/hxzcR01UkuZiWHRovkkKeFu0KWoCRplfby7br8WAdnE3e2kp+3bEn7GAd4jClQe+syUwpL
wO9MBfK3jmQQHNul7XE1WMy+wyyL7s7e3bnjTVbrItqIiknfS/Lfcjqdq8jI28QUXzMmFaPVAycu
fL/kyYFyykqYfGIQdMatUfmy3wJa/vpl3tEefMj1zLUzS00EzJoEPXMpFimdgcse25l3pWAG6pba
lv2RZeDt4WGFcvabgEKS95Z73QdmL50Qvf5VGiiWoxWXVQX15+RXBPugptcZqLwBjgB5KABm2Usv
Qu/QJise1z4u34BSmt/KmGY7tTv8HItpgTyCJ6KAVDV88HB0C4as5rZ3JUi6oSUqFL+T5X3EXDoI
aGye6feYW0myhmsB5vhrSBDflIWhHBT6ic0oxsxY7aKKkdcmDKdPcY3qckiUo8y3c2QSFfDfrg0W
7xHXK0/PBc7Qw5+S0pct6dZqwX9oHR216YQo2P9QBuTDkkKM5ljg3DO2bf5P7ESWCr+exYb29HD/
rIet5LOIo8ofspQqN64nwlNQmr7HBuhA4ZOPeZdmqn8R/NcIwQav8o6vvjSWbaYzeCzZM9MQTf1m
z8QDRO9PKxzM0Ypny0PBLbmoXmGw7FO6vyIpSALzk679WetbdgmDvg9rxqOa2aI63fBy+NJRNCQn
xMGYjFW3of+wCtuXfEMq78wVX/WnCZpKuq2k3bSPPwuXzAoRRjksv4LNVPNbIx31WUgkC+v54xtK
Sz12jw5I4EZdP9dYgNpR0hZdwsukWIJ7Zr2+8O19M7WjzckCWAgep3agkiQG6YY5AOyZjyjSiEyb
VCYzl1+c5kpP8Ov5zk1U7L/IhQfJmwEm/W7dbjNBGicprJYiGddJkeU9OMcUlTxJ61Mxvs5NZHZa
XJCEdf8FfivmVE1QGwsHGYIQTa/CeYA5iBqQJr7uNG7vrlIPZzl0zdB4Iga63WaNZZAj36dEw4SS
OJBGVN4AD213YebZtHZm9I26vvCYKq3W/iVGh4bm4lDUgxyGjJKJ3E0QEh0LCCpyfh+q1x8BHGK/
mQt32E7/f3Ck2LZVCiUKUPYr74r9tYK/57nnciQRsx2cffzsHetNm8n7BGXR+tHLvhwwm+7sIKKU
ffvbN9hW2J4SGObEChsX5VSea+XKSdUAqbiOTtBrj74uYJ6NgmajsqOi8AWPnRnzCfT4cMkMLYJb
CK87K6JRAJG3ZG7zizaVS1wwDmPtTxUABVTiBDjBA79bMR+N0JxMDrsjl/j6EXjVG3mTP8nIPgus
0047Zb9uvR29Bs8r1qovTQKX4prZ7PK6UaRd9k6yE71jslrk7SCD+/5IyAG0xSsU5yXDn2Q/6ffR
oEzwpnKq7gKfhpmJ1VdFIj9Pktztkt9tVYXip3CeyS7OhTJEf4y7CKp5Lt0emaXKy9bAWYMBcFDu
ZGAjSQ97FkLaBSFWmOhzAAXwEcTlHcJOgjvL26QfvqJvcUgdlUrA+EB+md2Xd8eKIk/yPcP96H3d
n5jVn7vqCa3m8vR7jSh3vSDu3UIGxgPcNAp1lsydmumsps5lJJKnTQK4HcniJKnj9b1f/jYSWLfb
17sUE9niNOA0F32y1YHbghp9WJbiavPimloHhaGWfNEvewloOs6SA2oQQgJ/0sc8psi+E2Bo1RTT
MJQR7TC3vkb5O/ImqU/YWheW9uIHW1h3F9E+GAaCNB+8OC85divyUMUwvU2Fs1WvNI+ovKOZG28p
KiBJ5IY6WVEtpdjMk36RIt+d3WrVO9/1jzMroYmuRRNVgkK4mBOV4XKICZ08QhhxeLfem57xW3fp
ErXU4xBUqhIX/GqUpRbpwULIAj5mk6ugBFEF5xy+saiO14vhOfvo8tqPNs95DjXTZCgYR52tS7zy
2MWGlFnk5g1SfRid9Z78qQCy/O98s6fH4PLTubKrLS+C7zbiW6tx94Q10oXN6tl/B88leQ6a+/7T
JZMXoH+rl/vVjJGHBzKlwlmSiwe1UKfVrckvdZAZ26YgqkMlDo5mg2QOz5GHq2J/dd/wxlO6gjex
RwpIc0GAZm43DFug7p9nNNK0n44HJ7tiX49a3PtUG5K6wT8FTKpge0eZpIcMFpxMgaH55zElrC5E
Jz7UhXcnohD6m0r/gIo1d+Bb2KyHtHnHAvamCAymGV/A6VquFHTWndsH7ZxLuIDfUIkK/lIXiG2T
XtxDzO+Cud2/k/DAkaaOuhyO12w+sse5HCFPcczJME6IFvxB620fMB+dlVj9IdVAq8HDEmNAWWdl
Nndu/F8nlpp4imaL/0izogYPH0mU1z41A/Wp1ErZRg1PthGZbpR8WjtFP6ldKVthaB2mTiQQZ1W9
u+velp3OdNVuuoP2Fo2cdt3S6frjlP6/EhKGjSc53LipP605oh2FUdNg01+UCRdKK0WrEt5WFNjI
O3mf2SdxsIDSKpmNHB4D/8itdIBNrdOLj7OiVmNPEBzljW0vVBr8Pay643d5FBwvMYBPGc0YHsK0
R2Vcl+dg3vD84RjgbJV6mSnUhtitaUJzHEyY6RH/c+knYmtMvqIVBl9QGM7acnVaNjibk+SGjdnc
pl9fEw+CG7WQKvnKO+UPLRf91S9QJiqI9W/i/Cif7iv4aFndDWH3fU2fp11O1V77kwkeWtoxeJBV
fG2ucImnNp9xn8q6v67APJ2NTZX7nKU5hKd4QT4DJwC8/rZRmC+yYBHPIzr/vDkUvMxbdrmILTf/
IcBWExlfdn/KnJJEi+p29Tenbjnr1HRKdRixdUnPPI9pKn2H7jy/1FmYRcGMbzLrNAnDD/lw6DkK
4qkhByDFGoWrumNwvyNxRdg8tWfkESFHrDEcQxdELxJ1Z56dYz4SH/A/t9cQEkzGk6+bPoUXW7/1
rwSYIZ8ZjSOuxbvc+z+pj5Qjqdlf4bXAUTmAA3t+3AZsTiG0iXZ2QGXBw2HGpwpUMwibEKMPA6Kb
yUUwkuGGVLKhxH4U8q1PNGtQ14Mb2HW/QE9+Gahpomr6JX6zdtz+izN8Etb3n0lEP50nSP7j2PDl
HZLCwJWDQa0T1GkMaKHMuEHsx9D75p+1eDGfDOxJpLZ7l6H0R51KYAm/JvPeM9jc4FaNRyS8GjdT
+3yTNGIZTyrdLaauE3D4tEUu+sp3HgftrZiATVo3iYl3lvnBKBFlmPUJxnct/jnAYrfz0QyXohwd
2L3GYzd5uXpbuR5gzxcVZkTCLQND5wDlvzy1TmQ+Z6sZHw5WbJkT2vetSVFNmRMb7wQ4+Y932QUl
HL1iXGhwJIjLgsTJXUMQ5/X229k5wjbZTYdmgtbSM0d/Y4gRyy59uXG9NhwwrhkGgNgdg0nLJQRe
ib23wvwMCWc24xeL1zXZFjTBgHumDLJNEjfVjA9xJ2ExI22yHKH2eYR86GGY4HIJwsc0Ov+CrIRY
X1PsWxO7kUIeuqc2Y5eSaVwF5qXHf2ua19dVYUPtz4ooVGIMwWOhc7K+RIGvqeErt5wYMjvxMzRr
khJMy/jA310Jn528Tk3a+IR7A1V5mNLVkb9Dwyk7er6a31u1kTwbIfUWGTcGsK9zOBRKcAHvO9Jp
qW4bjA1ogG0yKbSRC0FZrUzvqFsCO1S2lcVrzOWgPXrYgrYPsTJIU+XBVamHOa1pGyfI6OviUY+V
LfTnpzi0SyimRgOgHTggn5/4azP0RbVGiUkVO/tqXnqk2AlWSWHJb8sPQ4vvC1T8rvvbmZbG2hLU
VcqReLZo7o1JecI6NJNLMftH9W4pdzhkXRmMBEv9RNlLbqP6pR1UsVEbBlSGZmznK8qSPYvlKuCe
8GU9Z5TO2JW9rEaQTHgI+TDxQok4cyfqToAFbvjmeVFcq36yCAb+nV2yz07vhZMhCtwxVTMZ+AxP
o2dwk0w7SLjx1Mw8I8GeuXM7I5LY1OMVAcu0W/Bonqnhf/+bQy5lEKqeVu7TT6maGhcNrhDnuxC3
vp9TmU3OjDtQQqAwsg4Gghtv7na8GBT0WX1DyxFCPW2Qwjltodb5TAIXvNtu7ng9k71rhSlnwiyn
4aO9ZQuckrdIpX8f4VIy2X3PuVsSwie5dQwB/EUbF2i6c/cz0JUFb0eAqyHKCSJIOP5sYDKEudPU
8+Kwy8WbbSnllV0/BhMETOP5SWaVhrLEste01rbpgtCo1C3VTBpUDcvH93UhDyDq7zpwvlGF/jcG
i7WLYyKlFmqD0XdPbFD817yNSWT+rCigPyU5NasU39yH65ZStRRfGAOjnPrIE1GxxLrb/Cm1Uecc
KU4DzseyGO51hBsxvKSfISyBbsUd8fBZ4/jFDZTffrOne/PV5nRs2YehEs4C9g9XRjC08YpKA+Ah
Z3XHTqrHmG/h1Xsk0XQ9pzCi7C37YQLOgFNW63QoiEQ8Ac/DDzCzkPm8xyG8hSqoZ5OmMEBQuJLC
9GnaINxkYWZtmpWY9D2bQzSLiqFbtS+o3bjtuIGiTcfnqz0PmpVxqOowG9IdToMsNO7jMYM6I8Qg
fTeEODc/fJ0Dci0vaOdvqiqEzpx89S9MWJt50Lfy/Crwqx3PlZIGpO416TxnxEeuCQI3J4Pduavl
oyNxSacFqzr9HL4EoQISJOUtljKd7BGOuxn5QDlyRonjnxBNeJsEMVRScPHhPgTJtRXcHG/2NNdZ
keZppjJC9bpFKyhpx7EQAoZaoP1jUgyckzrY3kfKKXXZIVt21mhKvDMnfwYygQ7DwwcnPROOrWZP
+nMZcSumIrfLr5p8HLFiS7C0r3+IDO2lsccsPNXmV5bRkidCzet9rcrkJ3+ROdiEmZlnq/czQMkp
80HWvjwFVt6mbzcQBwumqDUp0bAYNyUthTMah6FcqiqZMicF8D/YbP8ANAhF/NouTvJAjPDgkCGC
e4P8qFzKga67iLbXuGktn8kPB5UZzyqUSOc5rGTtlyMmzwSGoPtK9HOEHn+oM2gySIgRlEM0uHCO
9xxvx0GGDhqnYbgMUS9TnQIRTmHGTeGBTm9/EOV1ciKsmYIj4NuU4kh0bjgICQ91ki7KaHaD9pNH
yQV8xQXNeMO53Eh8gMsxKqoT6bzdmc97re0Gj3OqrarZWoylnR4mnEae3j5oNhmmUY2vhooYv5s0
pWpqiq8rndOH8B1u3MepGLA0VrZ/w4c7L0yYwDfXtlafOWbnSO66R5PyrUUfM4zjtvjm7B6PPDxr
QtQBz/bG8IbDCE6HCV0XVlJ1XP+tWWNGTzCJIg3ymd1cOSGicb8ENxrwyjty3LMcqfiJOMkgGGMR
vwZYQtRvB4GsGzFAjqRAcBGhFonldOYa0GOUj16LmxMwKLyYWUJtCrJHLfbai1EY9YtVHkQnVyUt
1goOIXCxovgWLzustiRksoso1hCAxSvzh3W7H5J/v/JPHpdoKgQdR4+LMMm/0qi+QIlaceKQ1WEd
xT+zKokvO4c9v0grIdfZ3aihtvRN0kbZnhmYBFnYD35YXtyswSInLxslyrLFbJ9s6HgKe6iDHQ/8
W8gjmyNu2EEMuU6XwFZl9zdhjNaGQxVyKSqtc3p4PH5PbdBvNBq9DpU1Oj2+aViqBBP3DUIXrJuW
WMLvFD3/34W/mDq31EnPgaXFsvyPaKpYj0JoOAdqDQmwA8gCukFw3zl5iXUmaUC7ZNRzLwOUO3i2
DUwTK1yKBNHLVUFvH7UWwWleXiPd82pXXFJyg7QSt+4b+YQKCGlftD8W1/m19YbZ9DwYwpfFpWJu
dS2fHU1jyybNDt3bpcizvTWEGge+uB/6Fk6PRNvgfo2wQDjp/Dc+HPdxHDcWP+hq/FVuuwCRxJIA
3v0F/6XT7VVJb6HE2olTPU6gjn3GYi+muWUk35G0hpket/G9rz9JtCKiBpIwJ5vPbillXIlOaCuI
vpeSJs/VbEcsVNYHB2nKksg7UoMSSTgKlO+GYIOAVJqgY+jVULOdpCbB9ryrDsjaS7AxU4IIczaf
noDPHi/mEfB5r3SpE7wcjsBTkdx44eoiTv49FjzU6v38zLMgJvft/HiUgcfCkRabvGs650A4am0B
F+yH7Xu7VuqrMwjiHL0VynST+CHgD+gPsRlfjbvIc3V3KoECt8j8q+KYZdf2jaot7HKc9/c9nMrG
he8z3YZaYey/OrbKj2E/EplyammR90HvYAZbWOOcslEQ8w8JNvaJowCkjQ03yqni4iFBhu/eHoew
qnbIWpB1fkVCVd5EC5Gd0eZfh3j+VvRgURBEimCEV8KJz5aVTYdW3peN76PJh+OIHE1tjZBWLjgS
QjxeOoCkqtjFabDydnb9LsPrSRc3VCgK2xGFMQT/YAnnJRioY0vTwSSoqVUvOiMNKu0aXPY9ZxAj
Hl7q0jA72HhG7nx7I90U/wCM/+uYe3qEiMdH+ydgPF1Vg+lIWNhwd1iTlNInayGO5IWTd54lKci9
HBKbR7kQBtJw8XrCI3RmLoZ7W2/rUTZwKt7HkC6Z3Xlcz/6TBg2zgQqw+bpJ8zmvLO+CoEVj6ZFp
qWGKLLXHKSLsusfBLDjD/1YGI/leG1D131i+/y1ZmQd+yQ574RgGshqDIYEyCbgS1hf8e9JVVq/n
FjxKlQgeiwuJOdkeTm1rkQ5L8+NhPSzwx80Ryr9HeE1FRM6Kn/VyERPr8qR1eNS7uwoaDgBtdDwo
QmlAzwjGJXJ554qS0HZ4eOrBmfSDQMOUa7RP8cdZ82pe5ShAgPR6pWUy+7u57MU4QPpZ4Ckl90+k
EViTXnUi2uQN3kBG
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IRpgDt8BiqXecl3SIeLzuGdulfgvitJy38JD0kErvZ/PDjzBOFVfE2PrAT2xnGXVTShzZ0AoywBQ
PGsD+PrKqg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ffvuSd0RkCu0VwbxkEteIatf7Q/78Uh0Bi3BxKkzyZxTzFukdrJMNWOctZPR+VDK1KgGzsPbIT3Z
/jNBCLoopQSYWXX0eL77a99OOQfcY6cvLH0ET9zYNApWLR0kNmeEJmwLdSeBG8iGkmPisf3Wm+aQ
GDL7Tav+Oqx0sQ1AC5M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OcxzCjyYK5ZF8gnPitOf5t0iAzStDgc7At/EhKCUCUmOSmYmX7NRELVjN/X7ZCVpQpvqpM+mYVNl
/7Y2+h3RNru1tHeU0rb5WsiCbrtUOwbzPNGhJEfd5L2O8TqQQV5lR/wa8dhqOsXbZC1F6lXJf0ql
vqrp9e+IcJPUMgd8M73FvGH/nzxSnxQoeWRW5q3QElDMofnGVLxppQSFMNzW6nEfVX78T0JKs8tl
T9LIdQd29+dRlnr5QZcMG9Hpkh1cQ1XVUNKFDtQXsF1f338EPabLKCcdD8+8F/ucluO5OqvB0dPY
XJpvjtfdEsFt6hTxRrSegLzZ7aMV1s1tmZOjKw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
rLXNrS2fxiCVUKaX3PNyDChS/B8QJkJ04uCa1A7iW5GHUS8OS0Et/wHOXbfRoddWP8I9gRzGx5Ua
9u1Gp0Tq7EFCWMPoUYuZbAJI2Hv50vnrighWaLWByZJ+eay+UxyioKlE5k6Xq4oVz/28qt3Otvey
Q0wkW30CTsbclTS5zNE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cbjon8h+WbIL/8BhMk4t2gMX6VUMZKPXeqfuMDXEiiY1+MlkvJmqBtmYA3DHoWJZEh9o4z9xPuoN
JmmNF95+IJUhWhYZ/3PSTYQaa2j6jmlSzNmv3FiDb+kefoEFg2BM7TtfBuiphA2+uptHKlQR88DU
YPp6UH6PmFv9MGyZlrBCTexGQ+Om3gN8LacqRP2J0qor/vRRaAiAIfvHgInHAMP4z3gZ7FWBYzyR
17rSCCkcEJsFH5T7tUT+tuwSyNsnJIGEYqSPaxHnNAZ/C0+3mOobjCgrplLQ0jJUD9T4KNEc6Oyb
L+EO3U2HZ8Nvl0Gi4RoVvc215n0nneFWAEkSZg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8448)
`protect data_block
E3Dlx8rND4TMEKlMYdUVTf77EyzW05pWXJ6GBR/BpPyYo5fyuXkGwPHn86OIdqIOZjpQog0lPTTa
VPcG6DSTCc2NtcxDfAfswX8wTWFZPW5HBaHizBc2ICnE/EiRP43858rq8H+COlcEkI0ViFBILHma
4cGh7pJoi101j3ym6GDK34493gy7ZbxPEMhhn91pGEBWF7SdGHxdzf1j7qPJ+0k0sHsKgvAHcB5U
Z/m4QffSY6Ly8Itm1mIad+7F0Bn1OVFYy9bfR1SmQE85YSauotvd5dXX3Ypk3PwqaYiCi63Ojo4d
aTMvYUSVZWmhiKhGRnmYH9UNJb83u6zmdD6WLaIIPEWg3H+xQ2BW4WqiIFm5SPbzrWMTGjPCISPD
950NQvrv+nhmxbQVo+9NuBnNmrO1WOljoqN9DH+UNb/cFuKmJRNGwT6X/lCHkXy/qQqxCrBrGajm
4y/l1F02aIw6iHDFNPu8u339EviiHafwr6tii0CeNEe17SAAe2I2YipY9G84Xl+HvHJ4mC37I/Bn
qcV7rIM22dng3I5B2tmDYncBH92rdLLan0JzLDbDpG7qgwJ7CpxYzdEc1Jn8ldayPBE2sUVJqre/
/5fJdVW+68dxmaJmojzqb1QhW5+WP7uSk6Ui0/5gCM9CV3c95whkl/rfTW9yP8ko7yLsig1wjrT/
gX+oBSO8P+x5/zR2Fq0nrHX8bEzqqRvy+WoMpjx4HIphETWDl/w3ujLZo5GABPII0Wu7tqPd5v2m
xKma+duowqfHjpnG0o1Iv4K88sgBpZr19/5eq4kD1vPVZG0RinHghauy48sPcVHe6AbmdJKAaQFD
J1K6WcEZ9ewkEG0QSNBCVXAhZ/QYtWh0U/8ypzo8vpBfs6N5l03HFkDCWf7EfaPWQn2koQGyG1pG
qxlSMRbU2JDMNTeeamT91J5i24nY2D7B0KDeIlyW0985jo5r3vErEh2Ix4dSljTVG5cPAzVoJ7KX
i/snBI0rtg5cFWiqRldpwF043S0AJddY6WngP9sJyI4VNm+/gQCRyGtAg9QlKHhZyGNHLFSwXba/
u7BbUlapxWmVFE2hs2biktWqnONsEHDbJBcXQOm750BSwIc3oc4VritCqWlEQwCtjQ6iVEECjZ45
kll2kok6/B+zR6oqAxBUoNPbrBbikQbY4PeJh9mBAtMnWs9gNzRmxFNaZ/+0awmU/FyrIkst8Hne
plm2KVwjMrHymlzk8W3V6mLadejjfIzS1AolVWl+RUqrNjRGSsWdPC+5/hxrbKDLkuMupUkH3fQ4
i4ujvoZVdiCCZrxKvsJ44q1eCEocjBT9JLQWzU8wPPMT8E43BlnOwS+Hu7KlaKDB+kBrQB8NKnRE
mNpxhp98XVJBdZt115YuBTuGgJqcJEzq3xTujocAzxp9R2jrkGOjw/0vuSOK2UjMSTnp1ijqxte8
ZQey08/6I4xV2CE8e2e7hbksgIHZ/N7d/OBBIJxrIhyRoYeBN1UMRWJRES54O328OTjQWMJHI7Ru
0Nh4B6xmh5NFGDfCbui7/12kCKCk+mDx2EYdkCaHP100/YhDFeDFDETh8/lDXucg2HoBPYBKdIkw
KkzUIDKw2b9uyqB0f/cxXnv4J44GjGXPEqBYU/NytbocrQ0Fy9pxbufw7HyD0vxjB4XeTmoi8Lk4
aWf8BZ4lZhSUS7H5T3HmMW2n66bYDohyogLmNrVEKPkkjJvvOKiGA6fZQPxbwDYMAAjD30oyfT9g
XXZU5Y3R4VALYEOdjAZuZ3NUW7dwxF9tZ2hzXvPyPD6eXiDYpKEg6pdYavnH8TE0e0WUveWo/Bwb
IH/g5d6VIHwiMGB7bhvMNvEIHAF8ZbRFmNQVU89A438tzPAcnuLFfp0I5ihj2TXV6MOHvqvYSzsm
J1FoftqWEvVns46VjijRziMYvzLWanbgAvUm6sPnLJ28jXd/DMHxQeGi6FctSW9hLg2msyiW9ZBU
hIfHKUFZf3e3CkN6oSJTY16kuyxjCMXMc1v8trSKDQ2DKmEx8KjpPXbs6E9BtVcySue3GvExMhvX
3JLPyfpmsE9Iist6Y0wUnLmzOMQPcXlZkom0YPvugxQEtosE0aV3HXwPXrhHlrALHV3HZwhrha3y
q//HQjnstM58HP0jSczyzeJ7YzrTiecQZ5MyuAz19zOcodmw392ObL2h2hMwWBiO/DdL7seKhNe1
i7eX0bFtKg4gcliUnxMs9t10sJUr+F51zHsWimvc2vSa/Yp7lsJmtERjL3x0z8tkr60+Z46Q2OYw
VTTPM9B9F7ux8rxYqwCie/v/7lZ102kFywHUOEis7tWBEJswRl/eYP1DK8D5eu+znhoyflG6nzN7
qVv08a6nldywRAcRdTcKN71NOPys76zgRDz33wuJYXUlyjgXYlsnorPVXtjP/r1xNHM+SiLU7LlR
dskM24cq+n/DKxCOjJDussU0MR+zUfTkldu4ALveIJA1LK9BuTD1eHA2pn+MN81lZTnOoSY+/08M
AU3hNSCxO2eLVFduyHGMn22PmYSTcoFzkDtPAFYsVlMPez7Wd6wSfuPb3TyfDQtN4WR34EoAaQDx
ZiFvKMHLN8nnXQEksflV1Atax9i0PwY56tsjHf0FAwoqXQMNK/HXj39Yy3wjiCXpFw/LyBngDzJ8
ARKb+B96FpJvcGIdjyCyhZkJAuiB987LIY6YMoRWeZIAl/Hrhii3W96dd/OmBEyr6AUns+a8+m+7
9ANYabaATzGGrLxZZmM1qE5rGxnhSe/fHDRQQaM1gGlkQ5jOPeX3vvNQDdWL5kcn6Q169UoSP7oD
+qkV+5euQpQrq0e62GdcSpGRHzNSgZCv/1/RTbTZRzGQjP5/ovzu+sS+R1ls5YSf4DXs88OfF/Fu
OI2xmOfzx1asco4NCRdv7Y9mQ4gXGM84HqzJKf65wytTtxSIDa5t3/ahUKaWwhakvkS0musiv1qr
nZMuIaJ6nC+btzbviid1NohrBufU3oY32AUSUVl5/XMI9mLhuJbvfE1gwT9kbUuo9436svNgKKQK
5OkW1ISM9PXsp29X38ewI4gsx7tMHmntDw9vaMYflD74x7lyD+2KpSedvW0CgwlKCDqhGIB1x7U8
9uC9QiJCw3C9i6vLVstqyJEnHo2aA9xDBXlq37cGwdaDzchm8en/3YZhzogaXyJEZb8oHGHZFpTf
IaK5YQzY0LOHy3YVTeqYQhlTWEfIoLsdGSBo1bsvDsC8AN/GpPbWclNQsBVDShx2VXVptxWEJJcn
wlnM4f2vC8z8h8JJ+ZGE5FIRhHaF1M57B9iO43z6C+IK1q9lRdeczFf+RfWF4ZYHShaY2GksnJhE
GXO9hlM1/DENndrTYtKMTVZfH8cF2pZFuQb7RD44jlEVLYr7PvlfXzAcNY5QX+0r79lVECLmSv0c
Ekni4FCVwK2h1EMZIcOE/q/vD5UPsTsH5yCajNz4giKF3IY1Gtu/crhfMqvWEPFrqnUGyb7jZjwK
HACMc70qhYozamoFCOFYZFDFoTmwq1sY7ZBNlZkjDWwDqp062Cfawu1vn95X4cQ/iYq/R2jZN8t1
NSVFRaDw6Ee5k3mqeD5PXCy36bUtbTdvcS02s3/CCHqYHh2dpkbkft6JjSL/yzNlPEwN1mtsYRK9
P/qWBf4MXR/Zg79wELdY9sM6ljB6klLIsDa3IITPzwZeB/y+xR5f19GtDRNki8DqVdqx2NAs1ccP
K9viZhosrddaunKUxXMRJXgXYvMuR1NfD7j4bSopsE3QqqJZRYLYLJhXqg6H6y5FnXNdakcSqIMp
Avt0ZY1+rOqqENQ6kNw/KomowI/iKoZ/WI5ddjthhC3j2D1KRnSgHXxf1pNhNPrV64vHYl3733nG
RHFywzEVy50KAoCtWTSbAxsofSq5BXSRx28NQIUGbf8sSWKlYCn80tpBgLXlR1rQ6tt6nDEdoMTX
d0Ti6CdLll3NuAmT0LgaEWg7+sTRIM55vVtd4DmVlT0xP3Mzxs24SnGQFgDh0kaGpCdyyRaLbtjA
eR2052HNL+QU+lee8u9j+Id/GgW1awIoPxwm0CHCcXni/NtRwcmVjMIl/4SUEl1EeDkJTZy6gsWz
fISTqA7DBYzAHy+mq38zY3DbAUv4ayLnm9jAwlfJ/N+ok3McFVbqEWPk8VXJkYx29uVnlRcTdvCM
GWXk3W7UF6kMCNPtzk31Wgijo9IifWfSKKhLRz3XyuZjhLqneI1+XvQqFQ7r9wvPKMP30lme9DkT
Sx5ZdVqvb/kM7dUkqcbWkW8MAmRELy/ngEoAvHzzUDq++5qHXURLAjvt3OGDnChear3ZFUAUmnkG
9YWxMDCRezxeUYM19VOQb6j12LdmyBmI3myH7ITm0cmD0+e0g9/PZN5cWEPQtY8O6fN5OiuFBRoM
9mjDBS1uQIE1F0+SZSGOfeAR5sHLCx6o2fghPWAU3HneUBiDQhvtn/ALbTHpIDeTQTMCZj8k3j+U
NyCzrN1MpO24xxLDjAU30/jNumOl7P4WyAu+6Gdlr9bF0pJURbodhrWf+BT0TOTG/Tw825SeayNW
teKgx/hxzcR01UkuZiWHRovkkKeFu0KWoCRplfby7br8WAdnE3e2kp+3bEn7GAd4jClQe+syUwpL
wO9MBfK3jmQQHNul7XE1WMy+wyyL7s7e3bnjTVbrItqIiknfS/Lfcjqdq8jI28QUXzMmFaPVAycu
fL/kyYFyykqYfGIQdMatUfmy3wJa/vpl3tEefMj1zLUzS00EzJoEPXMpFimdgcse25l3pWAG6pba
lv2RZeDt4WGFcvabgEKS95Z73QdmL50Qvf5VGiiWoxWXVQX15+RXBPugptcZqLwBjgB5KABm2Usv
Qu/QJise1z4u34BSmt/KmGY7tTv8HItpgTyCJ6KAVDV88HB0C4as5rZ3JUi6oSUqFL+T5X3EXDoI
aGye6feYW0myhmsB5vhrSBDflIWhHBT6ic0oxsxY7aKKkdcmDKdPcY3qckiUo8y3c2QSFfDfrg0W
7xHXK0/PBc7Qw5+S0pct6dZqwX9oHR216YQo2P9QBuTDkkKM5ljg3DO2bf5P7ESWCr+exYb29HD/
rIet5LOIo8ofspQqN64nwlNQmr7HBuhA4ZOPeZdmqn8R/NcIwQav8o6vvjSWbaYzeCzZM9MQTf1m
z8QDRO9PKxzM0Ypny0PBLbmoXmGw7FO6vyIpSALzk679WetbdgmDvg9rxqOa2aI63fBy+NJRNCQn
xMGYjFW3of+wCtuXfEMq78wVX/WnCZpKuq2k3bSPPwuXzAoRRjksv4LNVPNbIx31WUgkC+v54xtK
Sz12jw5I4EZdP9dYgNpR0hZdwsukWIJ7Zr2+8O19M7WjzckCWAgep3agkiQG6YY5AOyZjyjSiEyb
VCYzl1+c5kpP8Ov5zk1U7L/IhQfJmwEm/W7dbjNBGicprJYiGddJkeU9OMcUlTxJ61Mxvs5NZHZa
XJCEdf8FfivmVE1QGwsHGYIQTa/CeYA5iBqQJr7uNG7vrlIPZzl0zdB4Iga63WaNZZAj36dEw4SS
OJBGVN4AD213YebZtHZm9I26vvCYKq3W/iVGh4bm4lDUgxyGjJKJ3E0QEh0LCCpyfh+q1x8BHGK/
mQt32E7/f3Ck2LZVCiUKUPYr74r9tYK/57nnciQRsx2cffzsHetNm8n7BGXR+tHLvhwwm+7sIKKU
ffvbN9hW2J4SGObEChsX5VSea+XKSdUAqbiOTtBrj74uYJ6NgmajsqOi8AWPnRnzCfT4cMkMLYJb
CK87K6JRAJG3ZG7zizaVS1wwDmPtTxUABVTiBDjBA79bMR+N0JxMDrsjl/j6EXjVG3mTP8nIPgus
0047Zb9uvR29Bs8r1qovTQKX4prZ7PK6UaRd9k6yE71jslrk7SCD+/5IyAG0xSsU5yXDn2Q/6ffR
oEzwpnKq7gKfhpmJ1VdFIj9Pktztkt9tVYXip3CeyS7OhTJEf4y7CKp5Lt0emaXKy9bAWYMBcFDu
ZGAjSQ97FkLaBSFWmOhzAAXwEcTlHcJOgjvL26QfvqJvcUgdlUrA+EB+md2Xd8eKIk/yPcP96H3d
n5jVn7vqCa3m8vR7jSh3vSDu3UIGxgPcNAp1lsydmumsps5lJJKnTQK4HcniJKnj9b1f/jYSWLfb
17sUE9niNOA0F32y1YHbghp9WJbiavPimloHhaGWfNEvewloOs6SA2oQQgJ/0sc8psi+E2Bo1RTT
MJQR7TC3vkb5O/ImqU/YWheW9uIHW1h3F9E+GAaCNB+8OC85divyUMUwvU2Fs1WvNI+ovKOZG28p
KiBJ5IY6WVEtpdjMk36RIt+d3WrVO9/1jzMroYmuRRNVgkK4mBOV4XKICZ08QhhxeLfem57xW3fp
ErXU4xBUqhIX/GqUpRbpwULIAj5mk6ugBFEF5xy+saiO14vhOfvo8tqPNs95DjXTZCgYR52tS7zy
2MWGlFnk5g1SfRid9Z78qQCy/O98s6fH4PLTubKrLS+C7zbiW6tx94Q10oXN6tl/B88leQ6a+/7T
JZMXoH+rl/vVjJGHBzKlwlmSiwe1UKfVrckvdZAZ26YgqkMlDo5mg2QOz5GHq2J/dd/wxlO6gjex
RwpIc0GAZm43DFug7p9nNNK0n44HJ7tiX49a3PtUG5K6wT8FTKpge0eZpIcMFpxMgaH55zElrC5E
Jz7UhXcnohD6m0r/gIo1d+Bb2KyHtHnHAvamCAymGV/A6VquFHTWndsH7ZxLuIDfUIkK/lIXiG2T
XtxDzO+Cud2/k/DAkaaOuhyO12w+sse5HCFPcczJME6IFvxB620fMB+dlVj9IdVAq8HDEmNAWWdl
Nndu/F8nlpp4imaL/0izogYPH0mU1z41A/Wp1ErZRg1PthGZbpR8WjtFP6ldKVthaB2mTiQQZ1W9
u+velp3OdNVuuoP2Fo2cdt3S6frjlP6/EhKGjSc53LipP605oh2FUdNg01+UCRdKK0WrEt5WFNjI
O3mf2SdxsIDSKpmNHB4D/8itdIBNrdOLj7OiVmNPEBzljW0vVBr8Pay643d5FBwvMYBPGc0YHsK0
R2Vcl+dg3vD84RjgbJV6mSnUhtitaUJzHEyY6RH/c+knYmtMvqIVBl9QGM7acnVaNjibk+SGjdnc
pl9fEw+CG7WQKvnKO+UPLRf91S9QJiqI9W/i/Cif7iv4aFndDWH3fU2fp11O1V77kwkeWtoxeJBV
fG2ucImnNp9xn8q6v67APJ2NTZX7nKU5hKd4QT4DJwC8/rZRmC+yYBHPIzr/vDkUvMxbdrmILTf/
IcBWExlfdn/KnJJEi+p29Tenbjnr1HRKdRixdUnPPI9pKn2H7jy/1FmYRcGMbzLrNAnDD/lw6DkK
4qkhByDFGoWrumNwvyNxRdg8tWfkESFHrDEcQxdELxJ1Z56dYz4SH/A/t9cQEkzGk6+bPoUXW7/1
rwSYIZ8ZjSOuxbvc+z+pj5Qjqdlf4bXAUTmAA3t+3AZsTiG0iXZ2QGXBw2HGpwpUMwibEKMPA6Kb
yUUwkuGGVLKhxH4U8q1PNGtQ14Mb2HW/QE9+Gahpomr6JX6zdtz+izN8Etb3n0lEP50nSP7j2PDl
HZLCwJWDQa0T1GkMaKHMuEHsx9D75p+1eDGfDOxJpLZ7l6H0R51KYAm/JvPeM9jc4FaNRyS8GjdT
+3yTNGIZTyrdLaauE3D4tEUu+sp3HgftrZiATVo3iYl3lvnBKBFlmPUJxnct/jnAYrfz0QyXohwd
2L3GYzd5uXpbuR5gzxcVZkTCLQND5wDlvzy1TmQ+Z6sZHw5WbJkT2vetSVFNmRMb7wQ4+Y932QUl
HL1iXGhwJIjLgsTJXUMQ5/X229k5wjbZTYdmgtbSM0d/Y4gRyy59uXG9NhwwrhkGgNgdg0nLJQRe
ib23wvwMCWc24xeL1zXZFjTBgHumDLJNEjfVjA9xJ2ExI22yHKH2eYR86GGY4HIJwsc0Ov+CrIRY
X1PsWxO7kUIeuqc2Y5eSaVwF5qXHf2ua19dVYUPtz4ooVGIMwWOhc7K+RIGvqeErt5wYMjvxMzRr
khJMy/jA310Jn528Tk3a+IR7A1V5mNLVkb9Dwyk7er6a31u1kTwbIfUWGTcGsK9zOBRKcAHvO9Jp
qW4bjA1ogG0yKbSRC0FZrUzvqFsCO1S2lcVrzOWgPXrYgrYPsTJIU+XBVamHOa1pGyfI6OviUY+V
LfTnpzi0SyimRgOgHTggn5/4azP0RbVGiUkVO/tqXnqk2AlWSWHJb8sPQ4vvC1T8rvvbmZbG2hLU
VcqReLZo7o1JecI6NJNLMftH9W4pdzhkXRmMBEv9RNlLbqP6pR1UsVEbBlSGZmznK8qSPYvlKuCe
8GU9Z5TO2JW9rEaQTHgI+TDxQok4cyfqToAFbvjmeVFcq36yCAb+nV2yz07vhZMhCtwxVTMZ+AxP
o2dwk0w7SLjx1Mw8I8GeuXM7I5LY1OMVAcu0W/Bonqnhf/+bQy5lEKqeVu7TT6maGhcNrhDnuxC3
vp9TmU3OjDtQQqAwsg4Gghtv7na8GBT0WX1DyxFCPW2Qwjltodb5TAIXvNtu7ng9k71rhSlnwiyn
4aO9ZQuckrdIpX8f4VIy2X3PuVsSwie5dQwB/EUbF2i6c/cz0JUFb0eAqyHKCSJIOP5sYDKEudPU
8+Kwy8WbbSnllV0/BhMETOP5SWaVhrLEste01rbpgtCo1C3VTBpUDcvH93UhDyDq7zpwvlGF/jcG
i7WLYyKlFmqD0XdPbFD817yNSWT+rCigPyU5NasU39yH65ZStRRfGAOjnPrIE1GxxLrb/Cm1Uecc
KU4DzseyGO51hBsxvKSfISyBbsUd8fBZ4/jFDZTffrOne/PV5nRs2YehEs4C9g9XRjC08YpKA+Ah
Z3XHTqrHmG/h1Xsk0XQ9pzCi7C37YQLOgFNW63QoiEQ8Ac/DDzCzkPm8xyG8hSqoZ5OmMEBQuJLC
9GnaINxkYWZtmpWY9D2bQzSLiqFbtS+o3bjtuIGiTcfnqz0PmpVxqOowG9IdToMsNO7jMYM6I8Qg
fTeEODc/fJ0Dci0vaOdvqiqEzpx89S9MWJt50Lfy/Crwqx3PlZIGpO416TxnxEeuCQI3J4Pduavl
oyNxSacFqzr9HL4EoQISJOUtljKd7BGOuxn5QDlyRonjnxBNeJsEMVRScPHhPgTJtRXcHG/2NNdZ
keZppjJC9bpFKyhpx7EQAoZaoP1jUgyckzrY3kfKKXXZIVt21mhKvDMnfwYygQ7DwwcnPROOrWZP
+nMZcSumIrfLr5p8HLFiS7C0r3+IDO2lsccsPNXmV5bRkidCzet9rcrkJ3+ROdiEmZlnq/czQMkp
80HWvjwFVt6mbzcQBwumqDUp0bAYNyUthTMah6FcqiqZMicF8D/YbP8ANAhF/NouTvJAjPDgkCGC
e4P8qFzKga67iLbXuGktn8kPB5UZzyqUSOc5rGTtlyMmzwSGoPtK9HOEHn+oM2gySIgRlEM0uHCO
9xxvx0GGDhqnYbgMUS9TnQIRTmHGTeGBTm9/EOV1ciKsmYIj4NuU4kh0bjgICQ91ki7KaHaD9pNH
yQV8xQXNeMO53Eh8gMsxKqoT6bzdmc97re0Gj3OqrarZWoylnR4mnEae3j5oNhmmUY2vhooYv5s0
pWpqiq8rndOH8B1u3MepGLA0VrZ/w4c7L0yYwDfXtlafOWbnSO66R5PyrUUfM4zjtvjm7B6PPDxr
QtQBz/bG8IbDCE6HCV0XVlJ1XP+tWWNGTzCJIg3ymd1cOSGicb8ENxrwyjty3LMcqfiJOMkgGGMR
vwZYQtRvB4GsGzFAjqRAcBGhFonldOYa0GOUj16LmxMwKLyYWUJtCrJHLfbai1EY9YtVHkQnVyUt
1goOIXCxovgWLzustiRksoso1hCAxSvzh3W7H5J/v/JPHpdoKgQdR4+LMMm/0qi+QIlaceKQ1WEd
xT+zKokvO4c9v0grIdfZ3aihtvRN0kbZnhmYBFnYD35YXtyswSInLxslyrLFbJ9s6HgKe6iDHQ/8
W8gjmyNu2EEMuU6XwFZl9zdhjNaGQxVyKSqtc3p4PH5PbdBvNBq9DpU1Oj2+aViqBBP3DUIXrJuW
WMLvFD3/34W/mDq31EnPgaXFsvyPaKpYj0JoOAdqDQmwA8gCukFw3zl5iXUmaUC7ZNRzLwOUO3i2
DUwTK1yKBNHLVUFvH7UWwWleXiPd82pXXFJyg7QSt+4b+YQKCGlftD8W1/m19YbZ9DwYwpfFpWJu
dS2fHU1jyybNDt3bpcizvTWEGge+uB/6Fk6PRNvgfo2wQDjp/Dc+HPdxHDcWP+hq/FVuuwCRxJIA
3v0F/6XT7VVJb6HE2olTPU6gjn3GYi+muWUk35G0hpket/G9rz9JtCKiBpIwJ5vPbillXIlOaCuI
vpeSJs/VbEcsVNYHB2nKksg7UoMSSTgKlO+GYIOAVJqgY+jVULOdpCbB9ryrDsjaS7AxU4IIczaf
noDPHi/mEfB5r3SpE7wcjsBTkdx44eoiTv49FjzU6v38zLMgJvft/HiUgcfCkRabvGs650A4am0B
F+yH7Xu7VuqrMwjiHL0VynST+CHgD+gPsRlfjbvIc3V3KoECt8j8q+KYZdf2jaot7HKc9/c9nMrG
he8z3YZaYey/OrbKj2E/EplyammR90HvYAZbWOOcslEQ8w8JNvaJowCkjQ03yqni4iFBhu/eHoew
qnbIWpB1fkVCVd5EC5Gd0eZfh3j+VvRgURBEimCEV8KJz5aVTYdW3peN76PJh+OIHE1tjZBWLjgS
QjxeOoCkqtjFabDydnb9LsPrSRc3VCgK2xGFMQT/YAnnJRioY0vTwSSoqVUvOiMNKu0aXPY9ZxAj
Hl7q0jA72HhG7nx7I90U/wCM/+uYe3qEiMdH+ydgPF1Vg+lIWNhwd1iTlNInayGO5IWTd54lKci9
HBKbR7kQBtJw8XrCI3RmLoZ7W2/rUTZwKt7HkC6Z3Xlcz/6TBg2zgQqw+bpJ8zmvLO+CoEVj6ZFp
qWGKLLXHKSLsusfBLDjD/1YGI/leG1D131i+/y1ZmQd+yQ574RgGshqDIYEyCbgS1hf8e9JVVq/n
FjxKlQgeiwuJOdkeTm1rkQ5L8+NhPSzwx80Ryr9HeE1FRM6Kn/VyERPr8qR1eNS7uwoaDgBtdDwo
QmlAzwjGJXJ554qS0HZ4eOrBmfSDQMOUa7RP8cdZ82pe5ShAgPR6pWUy+7u57MU4QPpZ4Ckl90+k
EViTXnUi2uQN3kBG
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IRpgDt8BiqXecl3SIeLzuGdulfgvitJy38JD0kErvZ/PDjzBOFVfE2PrAT2xnGXVTShzZ0AoywBQ
PGsD+PrKqg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ffvuSd0RkCu0VwbxkEteIatf7Q/78Uh0Bi3BxKkzyZxTzFukdrJMNWOctZPR+VDK1KgGzsPbIT3Z
/jNBCLoopQSYWXX0eL77a99OOQfcY6cvLH0ET9zYNApWLR0kNmeEJmwLdSeBG8iGkmPisf3Wm+aQ
GDL7Tav+Oqx0sQ1AC5M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OcxzCjyYK5ZF8gnPitOf5t0iAzStDgc7At/EhKCUCUmOSmYmX7NRELVjN/X7ZCVpQpvqpM+mYVNl
/7Y2+h3RNru1tHeU0rb5WsiCbrtUOwbzPNGhJEfd5L2O8TqQQV5lR/wa8dhqOsXbZC1F6lXJf0ql
vqrp9e+IcJPUMgd8M73FvGH/nzxSnxQoeWRW5q3QElDMofnGVLxppQSFMNzW6nEfVX78T0JKs8tl
T9LIdQd29+dRlnr5QZcMG9Hpkh1cQ1XVUNKFDtQXsF1f338EPabLKCcdD8+8F/ucluO5OqvB0dPY
XJpvjtfdEsFt6hTxRrSegLzZ7aMV1s1tmZOjKw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
rLXNrS2fxiCVUKaX3PNyDChS/B8QJkJ04uCa1A7iW5GHUS8OS0Et/wHOXbfRoddWP8I9gRzGx5Ua
9u1Gp0Tq7EFCWMPoUYuZbAJI2Hv50vnrighWaLWByZJ+eay+UxyioKlE5k6Xq4oVz/28qt3Otvey
Q0wkW30CTsbclTS5zNE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cbjon8h+WbIL/8BhMk4t2gMX6VUMZKPXeqfuMDXEiiY1+MlkvJmqBtmYA3DHoWJZEh9o4z9xPuoN
JmmNF95+IJUhWhYZ/3PSTYQaa2j6jmlSzNmv3FiDb+kefoEFg2BM7TtfBuiphA2+uptHKlQR88DU
YPp6UH6PmFv9MGyZlrBCTexGQ+Om3gN8LacqRP2J0qor/vRRaAiAIfvHgInHAMP4z3gZ7FWBYzyR
17rSCCkcEJsFH5T7tUT+tuwSyNsnJIGEYqSPaxHnNAZ/C0+3mOobjCgrplLQ0jJUD9T4KNEc6Oyb
L+EO3U2HZ8Nvl0Gi4RoVvc215n0nneFWAEkSZg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8448)
`protect data_block
E3Dlx8rND4TMEKlMYdUVTf77EyzW05pWXJ6GBR/BpPyYo5fyuXkGwPHn86OIdqIOZjpQog0lPTTa
VPcG6DSTCc2NtcxDfAfswX8wTWFZPW5HBaHizBc2ICnE/EiRP43858rq8H+COlcEkI0ViFBILHma
4cGh7pJoi101j3ym6GDK34493gy7ZbxPEMhhn91pGEBWF7SdGHxdzf1j7qPJ+0k0sHsKgvAHcB5U
Z/m4QffSY6Ly8Itm1mIad+7F0Bn1OVFYy9bfR1SmQE85YSauotvd5dXX3Ypk3PwqaYiCi63Ojo4d
aTMvYUSVZWmhiKhGRnmYH9UNJb83u6zmdD6WLaIIPEWg3H+xQ2BW4WqiIFm5SPbzrWMTGjPCISPD
950NQvrv+nhmxbQVo+9NuBnNmrO1WOljoqN9DH+UNb/cFuKmJRNGwT6X/lCHkXy/qQqxCrBrGajm
4y/l1F02aIw6iHDFNPu8u339EviiHafwr6tii0CeNEe17SAAe2I2YipY9G84Xl+HvHJ4mC37I/Bn
qcV7rIM22dng3I5B2tmDYncBH92rdLLan0JzLDbDpG7qgwJ7CpxYzdEc1Jn8ldayPBE2sUVJqre/
/5fJdVW+68dxmaJmojzqb1QhW5+WP7uSk6Ui0/5gCM9CV3c95whkl/rfTW9yP8ko7yLsig1wjrT/
gX+oBSO8P+x5/zR2Fq0nrHX8bEzqqRvy+WoMpjx4HIphETWDl/w3ujLZo5GABPII0Wu7tqPd5v2m
xKma+duowqfHjpnG0o1Iv4K88sgBpZr19/5eq4kD1vPVZG0RinHghauy48sPcVHe6AbmdJKAaQFD
J1K6WcEZ9ewkEG0QSNBCVXAhZ/QYtWh0U/8ypzo8vpBfs6N5l03HFkDCWf7EfaPWQn2koQGyG1pG
qxlSMRbU2JDMNTeeamT91J5i24nY2D7B0KDeIlyW0985jo5r3vErEh2Ix4dSljTVG5cPAzVoJ7KX
i/snBI0rtg5cFWiqRldpwF043S0AJddY6WngP9sJyI4VNm+/gQCRyGtAg9QlKHhZyGNHLFSwXba/
u7BbUlapxWmVFE2hs2biktWqnONsEHDbJBcXQOm750BSwIc3oc4VritCqWlEQwCtjQ6iVEECjZ45
kll2kok6/B+zR6oqAxBUoNPbrBbikQbY4PeJh9mBAtMnWs9gNzRmxFNaZ/+0awmU/FyrIkst8Hne
plm2KVwjMrHymlzk8W3V6mLadejjfIzS1AolVWl+RUqrNjRGSsWdPC+5/hxrbKDLkuMupUkH3fQ4
i4ujvoZVdiCCZrxKvsJ44q1eCEocjBT9JLQWzU8wPPMT8E43BlnOwS+Hu7KlaKDB+kBrQB8NKnRE
mNpxhp98XVJBdZt115YuBTuGgJqcJEzq3xTujocAzxp9R2jrkGOjw/0vuSOK2UjMSTnp1ijqxte8
ZQey08/6I4xV2CE8e2e7hbksgIHZ/N7d/OBBIJxrIhyRoYeBN1UMRWJRES54O328OTjQWMJHI7Ru
0Nh4B6xmh5NFGDfCbui7/12kCKCk+mDx2EYdkCaHP100/YhDFeDFDETh8/lDXucg2HoBPYBKdIkw
KkzUIDKw2b9uyqB0f/cxXnv4J44GjGXPEqBYU/NytbocrQ0Fy9pxbufw7HyD0vxjB4XeTmoi8Lk4
aWf8BZ4lZhSUS7H5T3HmMW2n66bYDohyogLmNrVEKPkkjJvvOKiGA6fZQPxbwDYMAAjD30oyfT9g
XXZU5Y3R4VALYEOdjAZuZ3NUW7dwxF9tZ2hzXvPyPD6eXiDYpKEg6pdYavnH8TE0e0WUveWo/Bwb
IH/g5d6VIHwiMGB7bhvMNvEIHAF8ZbRFmNQVU89A438tzPAcnuLFfp0I5ihj2TXV6MOHvqvYSzsm
J1FoftqWEvVns46VjijRziMYvzLWanbgAvUm6sPnLJ28jXd/DMHxQeGi6FctSW9hLg2msyiW9ZBU
hIfHKUFZf3e3CkN6oSJTY16kuyxjCMXMc1v8trSKDQ2DKmEx8KjpPXbs6E9BtVcySue3GvExMhvX
3JLPyfpmsE9Iist6Y0wUnLmzOMQPcXlZkom0YPvugxQEtosE0aV3HXwPXrhHlrALHV3HZwhrha3y
q//HQjnstM58HP0jSczyzeJ7YzrTiecQZ5MyuAz19zOcodmw392ObL2h2hMwWBiO/DdL7seKhNe1
i7eX0bFtKg4gcliUnxMs9t10sJUr+F51zHsWimvc2vSa/Yp7lsJmtERjL3x0z8tkr60+Z46Q2OYw
VTTPM9B9F7ux8rxYqwCie/v/7lZ102kFywHUOEis7tWBEJswRl/eYP1DK8D5eu+znhoyflG6nzN7
qVv08a6nldywRAcRdTcKN71NOPys76zgRDz33wuJYXUlyjgXYlsnorPVXtjP/r1xNHM+SiLU7LlR
dskM24cq+n/DKxCOjJDussU0MR+zUfTkldu4ALveIJA1LK9BuTD1eHA2pn+MN81lZTnOoSY+/08M
AU3hNSCxO2eLVFduyHGMn22PmYSTcoFzkDtPAFYsVlMPez7Wd6wSfuPb3TyfDQtN4WR34EoAaQDx
ZiFvKMHLN8nnXQEksflV1Atax9i0PwY56tsjHf0FAwoqXQMNK/HXj39Yy3wjiCXpFw/LyBngDzJ8
ARKb+B96FpJvcGIdjyCyhZkJAuiB987LIY6YMoRWeZIAl/Hrhii3W96dd/OmBEyr6AUns+a8+m+7
9ANYabaATzGGrLxZZmM1qE5rGxnhSe/fHDRQQaM1gGlkQ5jOPeX3vvNQDdWL5kcn6Q169UoSP7oD
+qkV+5euQpQrq0e62GdcSpGRHzNSgZCv/1/RTbTZRzGQjP5/ovzu+sS+R1ls5YSf4DXs88OfF/Fu
OI2xmOfzx1asco4NCRdv7Y9mQ4gXGM84HqzJKf65wytTtxSIDa5t3/ahUKaWwhakvkS0musiv1qr
nZMuIaJ6nC+btzbviid1NohrBufU3oY32AUSUVl5/XMI9mLhuJbvfE1gwT9kbUuo9436svNgKKQK
5OkW1ISM9PXsp29X38ewI4gsx7tMHmntDw9vaMYflD74x7lyD+2KpSedvW0CgwlKCDqhGIB1x7U8
9uC9QiJCw3C9i6vLVstqyJEnHo2aA9xDBXlq37cGwdaDzchm8en/3YZhzogaXyJEZb8oHGHZFpTf
IaK5YQzY0LOHy3YVTeqYQhlTWEfIoLsdGSBo1bsvDsC8AN/GpPbWclNQsBVDShx2VXVptxWEJJcn
wlnM4f2vC8z8h8JJ+ZGE5FIRhHaF1M57B9iO43z6C+IK1q9lRdeczFf+RfWF4ZYHShaY2GksnJhE
GXO9hlM1/DENndrTYtKMTVZfH8cF2pZFuQb7RD44jlEVLYr7PvlfXzAcNY5QX+0r79lVECLmSv0c
Ekni4FCVwK2h1EMZIcOE/q/vD5UPsTsH5yCajNz4giKF3IY1Gtu/crhfMqvWEPFrqnUGyb7jZjwK
HACMc70qhYozamoFCOFYZFDFoTmwq1sY7ZBNlZkjDWwDqp062Cfawu1vn95X4cQ/iYq/R2jZN8t1
NSVFRaDw6Ee5k3mqeD5PXCy36bUtbTdvcS02s3/CCHqYHh2dpkbkft6JjSL/yzNlPEwN1mtsYRK9
P/qWBf4MXR/Zg79wELdY9sM6ljB6klLIsDa3IITPzwZeB/y+xR5f19GtDRNki8DqVdqx2NAs1ccP
K9viZhosrddaunKUxXMRJXgXYvMuR1NfD7j4bSopsE3QqqJZRYLYLJhXqg6H6y5FnXNdakcSqIMp
Avt0ZY1+rOqqENQ6kNw/KomowI/iKoZ/WI5ddjthhC3j2D1KRnSgHXxf1pNhNPrV64vHYl3733nG
RHFywzEVy50KAoCtWTSbAxsofSq5BXSRx28NQIUGbf8sSWKlYCn80tpBgLXlR1rQ6tt6nDEdoMTX
d0Ti6CdLll3NuAmT0LgaEWg7+sTRIM55vVtd4DmVlT0xP3Mzxs24SnGQFgDh0kaGpCdyyRaLbtjA
eR2052HNL+QU+lee8u9j+Id/GgW1awIoPxwm0CHCcXni/NtRwcmVjMIl/4SUEl1EeDkJTZy6gsWz
fISTqA7DBYzAHy+mq38zY3DbAUv4ayLnm9jAwlfJ/N+ok3McFVbqEWPk8VXJkYx29uVnlRcTdvCM
GWXk3W7UF6kMCNPtzk31Wgijo9IifWfSKKhLRz3XyuZjhLqneI1+XvQqFQ7r9wvPKMP30lme9DkT
Sx5ZdVqvb/kM7dUkqcbWkW8MAmRELy/ngEoAvHzzUDq++5qHXURLAjvt3OGDnChear3ZFUAUmnkG
9YWxMDCRezxeUYM19VOQb6j12LdmyBmI3myH7ITm0cmD0+e0g9/PZN5cWEPQtY8O6fN5OiuFBRoM
9mjDBS1uQIE1F0+SZSGOfeAR5sHLCx6o2fghPWAU3HneUBiDQhvtn/ALbTHpIDeTQTMCZj8k3j+U
NyCzrN1MpO24xxLDjAU30/jNumOl7P4WyAu+6Gdlr9bF0pJURbodhrWf+BT0TOTG/Tw825SeayNW
teKgx/hxzcR01UkuZiWHRovkkKeFu0KWoCRplfby7br8WAdnE3e2kp+3bEn7GAd4jClQe+syUwpL
wO9MBfK3jmQQHNul7XE1WMy+wyyL7s7e3bnjTVbrItqIiknfS/Lfcjqdq8jI28QUXzMmFaPVAycu
fL/kyYFyykqYfGIQdMatUfmy3wJa/vpl3tEefMj1zLUzS00EzJoEPXMpFimdgcse25l3pWAG6pba
lv2RZeDt4WGFcvabgEKS95Z73QdmL50Qvf5VGiiWoxWXVQX15+RXBPugptcZqLwBjgB5KABm2Usv
Qu/QJise1z4u34BSmt/KmGY7tTv8HItpgTyCJ6KAVDV88HB0C4as5rZ3JUi6oSUqFL+T5X3EXDoI
aGye6feYW0myhmsB5vhrSBDflIWhHBT6ic0oxsxY7aKKkdcmDKdPcY3qckiUo8y3c2QSFfDfrg0W
7xHXK0/PBc7Qw5+S0pct6dZqwX9oHR216YQo2P9QBuTDkkKM5ljg3DO2bf5P7ESWCr+exYb29HD/
rIet5LOIo8ofspQqN64nwlNQmr7HBuhA4ZOPeZdmqn8R/NcIwQav8o6vvjSWbaYzeCzZM9MQTf1m
z8QDRO9PKxzM0Ypny0PBLbmoXmGw7FO6vyIpSALzk679WetbdgmDvg9rxqOa2aI63fBy+NJRNCQn
xMGYjFW3of+wCtuXfEMq78wVX/WnCZpKuq2k3bSPPwuXzAoRRjksv4LNVPNbIx31WUgkC+v54xtK
Sz12jw5I4EZdP9dYgNpR0hZdwsukWIJ7Zr2+8O19M7WjzckCWAgep3agkiQG6YY5AOyZjyjSiEyb
VCYzl1+c5kpP8Ov5zk1U7L/IhQfJmwEm/W7dbjNBGicprJYiGddJkeU9OMcUlTxJ61Mxvs5NZHZa
XJCEdf8FfivmVE1QGwsHGYIQTa/CeYA5iBqQJr7uNG7vrlIPZzl0zdB4Iga63WaNZZAj36dEw4SS
OJBGVN4AD213YebZtHZm9I26vvCYKq3W/iVGh4bm4lDUgxyGjJKJ3E0QEh0LCCpyfh+q1x8BHGK/
mQt32E7/f3Ck2LZVCiUKUPYr74r9tYK/57nnciQRsx2cffzsHetNm8n7BGXR+tHLvhwwm+7sIKKU
ffvbN9hW2J4SGObEChsX5VSea+XKSdUAqbiOTtBrj74uYJ6NgmajsqOi8AWPnRnzCfT4cMkMLYJb
CK87K6JRAJG3ZG7zizaVS1wwDmPtTxUABVTiBDjBA79bMR+N0JxMDrsjl/j6EXjVG3mTP8nIPgus
0047Zb9uvR29Bs8r1qovTQKX4prZ7PK6UaRd9k6yE71jslrk7SCD+/5IyAG0xSsU5yXDn2Q/6ffR
oEzwpnKq7gKfhpmJ1VdFIj9Pktztkt9tVYXip3CeyS7OhTJEf4y7CKp5Lt0emaXKy9bAWYMBcFDu
ZGAjSQ97FkLaBSFWmOhzAAXwEcTlHcJOgjvL26QfvqJvcUgdlUrA+EB+md2Xd8eKIk/yPcP96H3d
n5jVn7vqCa3m8vR7jSh3vSDu3UIGxgPcNAp1lsydmumsps5lJJKnTQK4HcniJKnj9b1f/jYSWLfb
17sUE9niNOA0F32y1YHbghp9WJbiavPimloHhaGWfNEvewloOs6SA2oQQgJ/0sc8psi+E2Bo1RTT
MJQR7TC3vkb5O/ImqU/YWheW9uIHW1h3F9E+GAaCNB+8OC85divyUMUwvU2Fs1WvNI+ovKOZG28p
KiBJ5IY6WVEtpdjMk36RIt+d3WrVO9/1jzMroYmuRRNVgkK4mBOV4XKICZ08QhhxeLfem57xW3fp
ErXU4xBUqhIX/GqUpRbpwULIAj5mk6ugBFEF5xy+saiO14vhOfvo8tqPNs95DjXTZCgYR52tS7zy
2MWGlFnk5g1SfRid9Z78qQCy/O98s6fH4PLTubKrLS+C7zbiW6tx94Q10oXN6tl/B88leQ6a+/7T
JZMXoH+rl/vVjJGHBzKlwlmSiwe1UKfVrckvdZAZ26YgqkMlDo5mg2QOz5GHq2J/dd/wxlO6gjex
RwpIc0GAZm43DFug7p9nNNK0n44HJ7tiX49a3PtUG5K6wT8FTKpge0eZpIcMFpxMgaH55zElrC5E
Jz7UhXcnohD6m0r/gIo1d+Bb2KyHtHnHAvamCAymGV/A6VquFHTWndsH7ZxLuIDfUIkK/lIXiG2T
XtxDzO+Cud2/k/DAkaaOuhyO12w+sse5HCFPcczJME6IFvxB620fMB+dlVj9IdVAq8HDEmNAWWdl
Nndu/F8nlpp4imaL/0izogYPH0mU1z41A/Wp1ErZRg1PthGZbpR8WjtFP6ldKVthaB2mTiQQZ1W9
u+velp3OdNVuuoP2Fo2cdt3S6frjlP6/EhKGjSc53LipP605oh2FUdNg01+UCRdKK0WrEt5WFNjI
O3mf2SdxsIDSKpmNHB4D/8itdIBNrdOLj7OiVmNPEBzljW0vVBr8Pay643d5FBwvMYBPGc0YHsK0
R2Vcl+dg3vD84RjgbJV6mSnUhtitaUJzHEyY6RH/c+knYmtMvqIVBl9QGM7acnVaNjibk+SGjdnc
pl9fEw+CG7WQKvnKO+UPLRf91S9QJiqI9W/i/Cif7iv4aFndDWH3fU2fp11O1V77kwkeWtoxeJBV
fG2ucImnNp9xn8q6v67APJ2NTZX7nKU5hKd4QT4DJwC8/rZRmC+yYBHPIzr/vDkUvMxbdrmILTf/
IcBWExlfdn/KnJJEi+p29Tenbjnr1HRKdRixdUnPPI9pKn2H7jy/1FmYRcGMbzLrNAnDD/lw6DkK
4qkhByDFGoWrumNwvyNxRdg8tWfkESFHrDEcQxdELxJ1Z56dYz4SH/A/t9cQEkzGk6+bPoUXW7/1
rwSYIZ8ZjSOuxbvc+z+pj5Qjqdlf4bXAUTmAA3t+3AZsTiG0iXZ2QGXBw2HGpwpUMwibEKMPA6Kb
yUUwkuGGVLKhxH4U8q1PNGtQ14Mb2HW/QE9+Gahpomr6JX6zdtz+izN8Etb3n0lEP50nSP7j2PDl
HZLCwJWDQa0T1GkMaKHMuEHsx9D75p+1eDGfDOxJpLZ7l6H0R51KYAm/JvPeM9jc4FaNRyS8GjdT
+3yTNGIZTyrdLaauE3D4tEUu+sp3HgftrZiATVo3iYl3lvnBKBFlmPUJxnct/jnAYrfz0QyXohwd
2L3GYzd5uXpbuR5gzxcVZkTCLQND5wDlvzy1TmQ+Z6sZHw5WbJkT2vetSVFNmRMb7wQ4+Y932QUl
HL1iXGhwJIjLgsTJXUMQ5/X229k5wjbZTYdmgtbSM0d/Y4gRyy59uXG9NhwwrhkGgNgdg0nLJQRe
ib23wvwMCWc24xeL1zXZFjTBgHumDLJNEjfVjA9xJ2ExI22yHKH2eYR86GGY4HIJwsc0Ov+CrIRY
X1PsWxO7kUIeuqc2Y5eSaVwF5qXHf2ua19dVYUPtz4ooVGIMwWOhc7K+RIGvqeErt5wYMjvxMzRr
khJMy/jA310Jn528Tk3a+IR7A1V5mNLVkb9Dwyk7er6a31u1kTwbIfUWGTcGsK9zOBRKcAHvO9Jp
qW4bjA1ogG0yKbSRC0FZrUzvqFsCO1S2lcVrzOWgPXrYgrYPsTJIU+XBVamHOa1pGyfI6OviUY+V
LfTnpzi0SyimRgOgHTggn5/4azP0RbVGiUkVO/tqXnqk2AlWSWHJb8sPQ4vvC1T8rvvbmZbG2hLU
VcqReLZo7o1JecI6NJNLMftH9W4pdzhkXRmMBEv9RNlLbqP6pR1UsVEbBlSGZmznK8qSPYvlKuCe
8GU9Z5TO2JW9rEaQTHgI+TDxQok4cyfqToAFbvjmeVFcq36yCAb+nV2yz07vhZMhCtwxVTMZ+AxP
o2dwk0w7SLjx1Mw8I8GeuXM7I5LY1OMVAcu0W/Bonqnhf/+bQy5lEKqeVu7TT6maGhcNrhDnuxC3
vp9TmU3OjDtQQqAwsg4Gghtv7na8GBT0WX1DyxFCPW2Qwjltodb5TAIXvNtu7ng9k71rhSlnwiyn
4aO9ZQuckrdIpX8f4VIy2X3PuVsSwie5dQwB/EUbF2i6c/cz0JUFb0eAqyHKCSJIOP5sYDKEudPU
8+Kwy8WbbSnllV0/BhMETOP5SWaVhrLEste01rbpgtCo1C3VTBpUDcvH93UhDyDq7zpwvlGF/jcG
i7WLYyKlFmqD0XdPbFD817yNSWT+rCigPyU5NasU39yH65ZStRRfGAOjnPrIE1GxxLrb/Cm1Uecc
KU4DzseyGO51hBsxvKSfISyBbsUd8fBZ4/jFDZTffrOne/PV5nRs2YehEs4C9g9XRjC08YpKA+Ah
Z3XHTqrHmG/h1Xsk0XQ9pzCi7C37YQLOgFNW63QoiEQ8Ac/DDzCzkPm8xyG8hSqoZ5OmMEBQuJLC
9GnaINxkYWZtmpWY9D2bQzSLiqFbtS+o3bjtuIGiTcfnqz0PmpVxqOowG9IdToMsNO7jMYM6I8Qg
fTeEODc/fJ0Dci0vaOdvqiqEzpx89S9MWJt50Lfy/Crwqx3PlZIGpO416TxnxEeuCQI3J4Pduavl
oyNxSacFqzr9HL4EoQISJOUtljKd7BGOuxn5QDlyRonjnxBNeJsEMVRScPHhPgTJtRXcHG/2NNdZ
keZppjJC9bpFKyhpx7EQAoZaoP1jUgyckzrY3kfKKXXZIVt21mhKvDMnfwYygQ7DwwcnPROOrWZP
+nMZcSumIrfLr5p8HLFiS7C0r3+IDO2lsccsPNXmV5bRkidCzet9rcrkJ3+ROdiEmZlnq/czQMkp
80HWvjwFVt6mbzcQBwumqDUp0bAYNyUthTMah6FcqiqZMicF8D/YbP8ANAhF/NouTvJAjPDgkCGC
e4P8qFzKga67iLbXuGktn8kPB5UZzyqUSOc5rGTtlyMmzwSGoPtK9HOEHn+oM2gySIgRlEM0uHCO
9xxvx0GGDhqnYbgMUS9TnQIRTmHGTeGBTm9/EOV1ciKsmYIj4NuU4kh0bjgICQ91ki7KaHaD9pNH
yQV8xQXNeMO53Eh8gMsxKqoT6bzdmc97re0Gj3OqrarZWoylnR4mnEae3j5oNhmmUY2vhooYv5s0
pWpqiq8rndOH8B1u3MepGLA0VrZ/w4c7L0yYwDfXtlafOWbnSO66R5PyrUUfM4zjtvjm7B6PPDxr
QtQBz/bG8IbDCE6HCV0XVlJ1XP+tWWNGTzCJIg3ymd1cOSGicb8ENxrwyjty3LMcqfiJOMkgGGMR
vwZYQtRvB4GsGzFAjqRAcBGhFonldOYa0GOUj16LmxMwKLyYWUJtCrJHLfbai1EY9YtVHkQnVyUt
1goOIXCxovgWLzustiRksoso1hCAxSvzh3W7H5J/v/JPHpdoKgQdR4+LMMm/0qi+QIlaceKQ1WEd
xT+zKokvO4c9v0grIdfZ3aihtvRN0kbZnhmYBFnYD35YXtyswSInLxslyrLFbJ9s6HgKe6iDHQ/8
W8gjmyNu2EEMuU6XwFZl9zdhjNaGQxVyKSqtc3p4PH5PbdBvNBq9DpU1Oj2+aViqBBP3DUIXrJuW
WMLvFD3/34W/mDq31EnPgaXFsvyPaKpYj0JoOAdqDQmwA8gCukFw3zl5iXUmaUC7ZNRzLwOUO3i2
DUwTK1yKBNHLVUFvH7UWwWleXiPd82pXXFJyg7QSt+4b+YQKCGlftD8W1/m19YbZ9DwYwpfFpWJu
dS2fHU1jyybNDt3bpcizvTWEGge+uB/6Fk6PRNvgfo2wQDjp/Dc+HPdxHDcWP+hq/FVuuwCRxJIA
3v0F/6XT7VVJb6HE2olTPU6gjn3GYi+muWUk35G0hpket/G9rz9JtCKiBpIwJ5vPbillXIlOaCuI
vpeSJs/VbEcsVNYHB2nKksg7UoMSSTgKlO+GYIOAVJqgY+jVULOdpCbB9ryrDsjaS7AxU4IIczaf
noDPHi/mEfB5r3SpE7wcjsBTkdx44eoiTv49FjzU6v38zLMgJvft/HiUgcfCkRabvGs650A4am0B
F+yH7Xu7VuqrMwjiHL0VynST+CHgD+gPsRlfjbvIc3V3KoECt8j8q+KYZdf2jaot7HKc9/c9nMrG
he8z3YZaYey/OrbKj2E/EplyammR90HvYAZbWOOcslEQ8w8JNvaJowCkjQ03yqni4iFBhu/eHoew
qnbIWpB1fkVCVd5EC5Gd0eZfh3j+VvRgURBEimCEV8KJz5aVTYdW3peN76PJh+OIHE1tjZBWLjgS
QjxeOoCkqtjFabDydnb9LsPrSRc3VCgK2xGFMQT/YAnnJRioY0vTwSSoqVUvOiMNKu0aXPY9ZxAj
Hl7q0jA72HhG7nx7I90U/wCM/+uYe3qEiMdH+ydgPF1Vg+lIWNhwd1iTlNInayGO5IWTd54lKci9
HBKbR7kQBtJw8XrCI3RmLoZ7W2/rUTZwKt7HkC6Z3Xlcz/6TBg2zgQqw+bpJ8zmvLO+CoEVj6ZFp
qWGKLLXHKSLsusfBLDjD/1YGI/leG1D131i+/y1ZmQd+yQ574RgGshqDIYEyCbgS1hf8e9JVVq/n
FjxKlQgeiwuJOdkeTm1rkQ5L8+NhPSzwx80Ryr9HeE1FRM6Kn/VyERPr8qR1eNS7uwoaDgBtdDwo
QmlAzwjGJXJ554qS0HZ4eOrBmfSDQMOUa7RP8cdZ82pe5ShAgPR6pWUy+7u57MU4QPpZ4Ckl90+k
EViTXnUi2uQN3kBG
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
IRpgDt8BiqXecl3SIeLzuGdulfgvitJy38JD0kErvZ/PDjzBOFVfE2PrAT2xnGXVTShzZ0AoywBQ
PGsD+PrKqg==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
ffvuSd0RkCu0VwbxkEteIatf7Q/78Uh0Bi3BxKkzyZxTzFukdrJMNWOctZPR+VDK1KgGzsPbIT3Z
/jNBCLoopQSYWXX0eL77a99OOQfcY6cvLH0ET9zYNApWLR0kNmeEJmwLdSeBG8iGkmPisf3Wm+aQ
GDL7Tav+Oqx0sQ1AC5M=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
OcxzCjyYK5ZF8gnPitOf5t0iAzStDgc7At/EhKCUCUmOSmYmX7NRELVjN/X7ZCVpQpvqpM+mYVNl
/7Y2+h3RNru1tHeU0rb5WsiCbrtUOwbzPNGhJEfd5L2O8TqQQV5lR/wa8dhqOsXbZC1F6lXJf0ql
vqrp9e+IcJPUMgd8M73FvGH/nzxSnxQoeWRW5q3QElDMofnGVLxppQSFMNzW6nEfVX78T0JKs8tl
T9LIdQd29+dRlnr5QZcMG9Hpkh1cQ1XVUNKFDtQXsF1f338EPabLKCcdD8+8F/ucluO5OqvB0dPY
XJpvjtfdEsFt6hTxRrSegLzZ7aMV1s1tmZOjKw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
rLXNrS2fxiCVUKaX3PNyDChS/B8QJkJ04uCa1A7iW5GHUS8OS0Et/wHOXbfRoddWP8I9gRzGx5Ua
9u1Gp0Tq7EFCWMPoUYuZbAJI2Hv50vnrighWaLWByZJ+eay+UxyioKlE5k6Xq4oVz/28qt3Otvey
Q0wkW30CTsbclTS5zNE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
cbjon8h+WbIL/8BhMk4t2gMX6VUMZKPXeqfuMDXEiiY1+MlkvJmqBtmYA3DHoWJZEh9o4z9xPuoN
JmmNF95+IJUhWhYZ/3PSTYQaa2j6jmlSzNmv3FiDb+kefoEFg2BM7TtfBuiphA2+uptHKlQR88DU
YPp6UH6PmFv9MGyZlrBCTexGQ+Om3gN8LacqRP2J0qor/vRRaAiAIfvHgInHAMP4z3gZ7FWBYzyR
17rSCCkcEJsFH5T7tUT+tuwSyNsnJIGEYqSPaxHnNAZ/C0+3mOobjCgrplLQ0jJUD9T4KNEc6Oyb
L+EO3U2HZ8Nvl0Gi4RoVvc215n0nneFWAEkSZg==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8448)
`protect data_block
E3Dlx8rND4TMEKlMYdUVTf77EyzW05pWXJ6GBR/BpPyYo5fyuXkGwPHn86OIdqIOZjpQog0lPTTa
VPcG6DSTCc2NtcxDfAfswX8wTWFZPW5HBaHizBc2ICnE/EiRP43858rq8H+COlcEkI0ViFBILHma
4cGh7pJoi101j3ym6GDK34493gy7ZbxPEMhhn91pGEBWF7SdGHxdzf1j7qPJ+0k0sHsKgvAHcB5U
Z/m4QffSY6Ly8Itm1mIad+7F0Bn1OVFYy9bfR1SmQE85YSauotvd5dXX3Ypk3PwqaYiCi63Ojo4d
aTMvYUSVZWmhiKhGRnmYH9UNJb83u6zmdD6WLaIIPEWg3H+xQ2BW4WqiIFm5SPbzrWMTGjPCISPD
950NQvrv+nhmxbQVo+9NuBnNmrO1WOljoqN9DH+UNb/cFuKmJRNGwT6X/lCHkXy/qQqxCrBrGajm
4y/l1F02aIw6iHDFNPu8u339EviiHafwr6tii0CeNEe17SAAe2I2YipY9G84Xl+HvHJ4mC37I/Bn
qcV7rIM22dng3I5B2tmDYncBH92rdLLan0JzLDbDpG7qgwJ7CpxYzdEc1Jn8ldayPBE2sUVJqre/
/5fJdVW+68dxmaJmojzqb1QhW5+WP7uSk6Ui0/5gCM9CV3c95whkl/rfTW9yP8ko7yLsig1wjrT/
gX+oBSO8P+x5/zR2Fq0nrHX8bEzqqRvy+WoMpjx4HIphETWDl/w3ujLZo5GABPII0Wu7tqPd5v2m
xKma+duowqfHjpnG0o1Iv4K88sgBpZr19/5eq4kD1vPVZG0RinHghauy48sPcVHe6AbmdJKAaQFD
J1K6WcEZ9ewkEG0QSNBCVXAhZ/QYtWh0U/8ypzo8vpBfs6N5l03HFkDCWf7EfaPWQn2koQGyG1pG
qxlSMRbU2JDMNTeeamT91J5i24nY2D7B0KDeIlyW0985jo5r3vErEh2Ix4dSljTVG5cPAzVoJ7KX
i/snBI0rtg5cFWiqRldpwF043S0AJddY6WngP9sJyI4VNm+/gQCRyGtAg9QlKHhZyGNHLFSwXba/
u7BbUlapxWmVFE2hs2biktWqnONsEHDbJBcXQOm750BSwIc3oc4VritCqWlEQwCtjQ6iVEECjZ45
kll2kok6/B+zR6oqAxBUoNPbrBbikQbY4PeJh9mBAtMnWs9gNzRmxFNaZ/+0awmU/FyrIkst8Hne
plm2KVwjMrHymlzk8W3V6mLadejjfIzS1AolVWl+RUqrNjRGSsWdPC+5/hxrbKDLkuMupUkH3fQ4
i4ujvoZVdiCCZrxKvsJ44q1eCEocjBT9JLQWzU8wPPMT8E43BlnOwS+Hu7KlaKDB+kBrQB8NKnRE
mNpxhp98XVJBdZt115YuBTuGgJqcJEzq3xTujocAzxp9R2jrkGOjw/0vuSOK2UjMSTnp1ijqxte8
ZQey08/6I4xV2CE8e2e7hbksgIHZ/N7d/OBBIJxrIhyRoYeBN1UMRWJRES54O328OTjQWMJHI7Ru
0Nh4B6xmh5NFGDfCbui7/12kCKCk+mDx2EYdkCaHP100/YhDFeDFDETh8/lDXucg2HoBPYBKdIkw
KkzUIDKw2b9uyqB0f/cxXnv4J44GjGXPEqBYU/NytbocrQ0Fy9pxbufw7HyD0vxjB4XeTmoi8Lk4
aWf8BZ4lZhSUS7H5T3HmMW2n66bYDohyogLmNrVEKPkkjJvvOKiGA6fZQPxbwDYMAAjD30oyfT9g
XXZU5Y3R4VALYEOdjAZuZ3NUW7dwxF9tZ2hzXvPyPD6eXiDYpKEg6pdYavnH8TE0e0WUveWo/Bwb
IH/g5d6VIHwiMGB7bhvMNvEIHAF8ZbRFmNQVU89A438tzPAcnuLFfp0I5ihj2TXV6MOHvqvYSzsm
J1FoftqWEvVns46VjijRziMYvzLWanbgAvUm6sPnLJ28jXd/DMHxQeGi6FctSW9hLg2msyiW9ZBU
hIfHKUFZf3e3CkN6oSJTY16kuyxjCMXMc1v8trSKDQ2DKmEx8KjpPXbs6E9BtVcySue3GvExMhvX
3JLPyfpmsE9Iist6Y0wUnLmzOMQPcXlZkom0YPvugxQEtosE0aV3HXwPXrhHlrALHV3HZwhrha3y
q//HQjnstM58HP0jSczyzeJ7YzrTiecQZ5MyuAz19zOcodmw392ObL2h2hMwWBiO/DdL7seKhNe1
i7eX0bFtKg4gcliUnxMs9t10sJUr+F51zHsWimvc2vSa/Yp7lsJmtERjL3x0z8tkr60+Z46Q2OYw
VTTPM9B9F7ux8rxYqwCie/v/7lZ102kFywHUOEis7tWBEJswRl/eYP1DK8D5eu+znhoyflG6nzN7
qVv08a6nldywRAcRdTcKN71NOPys76zgRDz33wuJYXUlyjgXYlsnorPVXtjP/r1xNHM+SiLU7LlR
dskM24cq+n/DKxCOjJDussU0MR+zUfTkldu4ALveIJA1LK9BuTD1eHA2pn+MN81lZTnOoSY+/08M
AU3hNSCxO2eLVFduyHGMn22PmYSTcoFzkDtPAFYsVlMPez7Wd6wSfuPb3TyfDQtN4WR34EoAaQDx
ZiFvKMHLN8nnXQEksflV1Atax9i0PwY56tsjHf0FAwoqXQMNK/HXj39Yy3wjiCXpFw/LyBngDzJ8
ARKb+B96FpJvcGIdjyCyhZkJAuiB987LIY6YMoRWeZIAl/Hrhii3W96dd/OmBEyr6AUns+a8+m+7
9ANYabaATzGGrLxZZmM1qE5rGxnhSe/fHDRQQaM1gGlkQ5jOPeX3vvNQDdWL5kcn6Q169UoSP7oD
+qkV+5euQpQrq0e62GdcSpGRHzNSgZCv/1/RTbTZRzGQjP5/ovzu+sS+R1ls5YSf4DXs88OfF/Fu
OI2xmOfzx1asco4NCRdv7Y9mQ4gXGM84HqzJKf65wytTtxSIDa5t3/ahUKaWwhakvkS0musiv1qr
nZMuIaJ6nC+btzbviid1NohrBufU3oY32AUSUVl5/XMI9mLhuJbvfE1gwT9kbUuo9436svNgKKQK
5OkW1ISM9PXsp29X38ewI4gsx7tMHmntDw9vaMYflD74x7lyD+2KpSedvW0CgwlKCDqhGIB1x7U8
9uC9QiJCw3C9i6vLVstqyJEnHo2aA9xDBXlq37cGwdaDzchm8en/3YZhzogaXyJEZb8oHGHZFpTf
IaK5YQzY0LOHy3YVTeqYQhlTWEfIoLsdGSBo1bsvDsC8AN/GpPbWclNQsBVDShx2VXVptxWEJJcn
wlnM4f2vC8z8h8JJ+ZGE5FIRhHaF1M57B9iO43z6C+IK1q9lRdeczFf+RfWF4ZYHShaY2GksnJhE
GXO9hlM1/DENndrTYtKMTVZfH8cF2pZFuQb7RD44jlEVLYr7PvlfXzAcNY5QX+0r79lVECLmSv0c
Ekni4FCVwK2h1EMZIcOE/q/vD5UPsTsH5yCajNz4giKF3IY1Gtu/crhfMqvWEPFrqnUGyb7jZjwK
HACMc70qhYozamoFCOFYZFDFoTmwq1sY7ZBNlZkjDWwDqp062Cfawu1vn95X4cQ/iYq/R2jZN8t1
NSVFRaDw6Ee5k3mqeD5PXCy36bUtbTdvcS02s3/CCHqYHh2dpkbkft6JjSL/yzNlPEwN1mtsYRK9
P/qWBf4MXR/Zg79wELdY9sM6ljB6klLIsDa3IITPzwZeB/y+xR5f19GtDRNki8DqVdqx2NAs1ccP
K9viZhosrddaunKUxXMRJXgXYvMuR1NfD7j4bSopsE3QqqJZRYLYLJhXqg6H6y5FnXNdakcSqIMp
Avt0ZY1+rOqqENQ6kNw/KomowI/iKoZ/WI5ddjthhC3j2D1KRnSgHXxf1pNhNPrV64vHYl3733nG
RHFywzEVy50KAoCtWTSbAxsofSq5BXSRx28NQIUGbf8sSWKlYCn80tpBgLXlR1rQ6tt6nDEdoMTX
d0Ti6CdLll3NuAmT0LgaEWg7+sTRIM55vVtd4DmVlT0xP3Mzxs24SnGQFgDh0kaGpCdyyRaLbtjA
eR2052HNL+QU+lee8u9j+Id/GgW1awIoPxwm0CHCcXni/NtRwcmVjMIl/4SUEl1EeDkJTZy6gsWz
fISTqA7DBYzAHy+mq38zY3DbAUv4ayLnm9jAwlfJ/N+ok3McFVbqEWPk8VXJkYx29uVnlRcTdvCM
GWXk3W7UF6kMCNPtzk31Wgijo9IifWfSKKhLRz3XyuZjhLqneI1+XvQqFQ7r9wvPKMP30lme9DkT
Sx5ZdVqvb/kM7dUkqcbWkW8MAmRELy/ngEoAvHzzUDq++5qHXURLAjvt3OGDnChear3ZFUAUmnkG
9YWxMDCRezxeUYM19VOQb6j12LdmyBmI3myH7ITm0cmD0+e0g9/PZN5cWEPQtY8O6fN5OiuFBRoM
9mjDBS1uQIE1F0+SZSGOfeAR5sHLCx6o2fghPWAU3HneUBiDQhvtn/ALbTHpIDeTQTMCZj8k3j+U
NyCzrN1MpO24xxLDjAU30/jNumOl7P4WyAu+6Gdlr9bF0pJURbodhrWf+BT0TOTG/Tw825SeayNW
teKgx/hxzcR01UkuZiWHRovkkKeFu0KWoCRplfby7br8WAdnE3e2kp+3bEn7GAd4jClQe+syUwpL
wO9MBfK3jmQQHNul7XE1WMy+wyyL7s7e3bnjTVbrItqIiknfS/Lfcjqdq8jI28QUXzMmFaPVAycu
fL/kyYFyykqYfGIQdMatUfmy3wJa/vpl3tEefMj1zLUzS00EzJoEPXMpFimdgcse25l3pWAG6pba
lv2RZeDt4WGFcvabgEKS95Z73QdmL50Qvf5VGiiWoxWXVQX15+RXBPugptcZqLwBjgB5KABm2Usv
Qu/QJise1z4u34BSmt/KmGY7tTv8HItpgTyCJ6KAVDV88HB0C4as5rZ3JUi6oSUqFL+T5X3EXDoI
aGye6feYW0myhmsB5vhrSBDflIWhHBT6ic0oxsxY7aKKkdcmDKdPcY3qckiUo8y3c2QSFfDfrg0W
7xHXK0/PBc7Qw5+S0pct6dZqwX9oHR216YQo2P9QBuTDkkKM5ljg3DO2bf5P7ESWCr+exYb29HD/
rIet5LOIo8ofspQqN64nwlNQmr7HBuhA4ZOPeZdmqn8R/NcIwQav8o6vvjSWbaYzeCzZM9MQTf1m
z8QDRO9PKxzM0Ypny0PBLbmoXmGw7FO6vyIpSALzk679WetbdgmDvg9rxqOa2aI63fBy+NJRNCQn
xMGYjFW3of+wCtuXfEMq78wVX/WnCZpKuq2k3bSPPwuXzAoRRjksv4LNVPNbIx31WUgkC+v54xtK
Sz12jw5I4EZdP9dYgNpR0hZdwsukWIJ7Zr2+8O19M7WjzckCWAgep3agkiQG6YY5AOyZjyjSiEyb
VCYzl1+c5kpP8Ov5zk1U7L/IhQfJmwEm/W7dbjNBGicprJYiGddJkeU9OMcUlTxJ61Mxvs5NZHZa
XJCEdf8FfivmVE1QGwsHGYIQTa/CeYA5iBqQJr7uNG7vrlIPZzl0zdB4Iga63WaNZZAj36dEw4SS
OJBGVN4AD213YebZtHZm9I26vvCYKq3W/iVGh4bm4lDUgxyGjJKJ3E0QEh0LCCpyfh+q1x8BHGK/
mQt32E7/f3Ck2LZVCiUKUPYr74r9tYK/57nnciQRsx2cffzsHetNm8n7BGXR+tHLvhwwm+7sIKKU
ffvbN9hW2J4SGObEChsX5VSea+XKSdUAqbiOTtBrj74uYJ6NgmajsqOi8AWPnRnzCfT4cMkMLYJb
CK87K6JRAJG3ZG7zizaVS1wwDmPtTxUABVTiBDjBA79bMR+N0JxMDrsjl/j6EXjVG3mTP8nIPgus
0047Zb9uvR29Bs8r1qovTQKX4prZ7PK6UaRd9k6yE71jslrk7SCD+/5IyAG0xSsU5yXDn2Q/6ffR
oEzwpnKq7gKfhpmJ1VdFIj9Pktztkt9tVYXip3CeyS7OhTJEf4y7CKp5Lt0emaXKy9bAWYMBcFDu
ZGAjSQ97FkLaBSFWmOhzAAXwEcTlHcJOgjvL26QfvqJvcUgdlUrA+EB+md2Xd8eKIk/yPcP96H3d
n5jVn7vqCa3m8vR7jSh3vSDu3UIGxgPcNAp1lsydmumsps5lJJKnTQK4HcniJKnj9b1f/jYSWLfb
17sUE9niNOA0F32y1YHbghp9WJbiavPimloHhaGWfNEvewloOs6SA2oQQgJ/0sc8psi+E2Bo1RTT
MJQR7TC3vkb5O/ImqU/YWheW9uIHW1h3F9E+GAaCNB+8OC85divyUMUwvU2Fs1WvNI+ovKOZG28p
KiBJ5IY6WVEtpdjMk36RIt+d3WrVO9/1jzMroYmuRRNVgkK4mBOV4XKICZ08QhhxeLfem57xW3fp
ErXU4xBUqhIX/GqUpRbpwULIAj5mk6ugBFEF5xy+saiO14vhOfvo8tqPNs95DjXTZCgYR52tS7zy
2MWGlFnk5g1SfRid9Z78qQCy/O98s6fH4PLTubKrLS+C7zbiW6tx94Q10oXN6tl/B88leQ6a+/7T
JZMXoH+rl/vVjJGHBzKlwlmSiwe1UKfVrckvdZAZ26YgqkMlDo5mg2QOz5GHq2J/dd/wxlO6gjex
RwpIc0GAZm43DFug7p9nNNK0n44HJ7tiX49a3PtUG5K6wT8FTKpge0eZpIcMFpxMgaH55zElrC5E
Jz7UhXcnohD6m0r/gIo1d+Bb2KyHtHnHAvamCAymGV/A6VquFHTWndsH7ZxLuIDfUIkK/lIXiG2T
XtxDzO+Cud2/k/DAkaaOuhyO12w+sse5HCFPcczJME6IFvxB620fMB+dlVj9IdVAq8HDEmNAWWdl
Nndu/F8nlpp4imaL/0izogYPH0mU1z41A/Wp1ErZRg1PthGZbpR8WjtFP6ldKVthaB2mTiQQZ1W9
u+velp3OdNVuuoP2Fo2cdt3S6frjlP6/EhKGjSc53LipP605oh2FUdNg01+UCRdKK0WrEt5WFNjI
O3mf2SdxsIDSKpmNHB4D/8itdIBNrdOLj7OiVmNPEBzljW0vVBr8Pay643d5FBwvMYBPGc0YHsK0
R2Vcl+dg3vD84RjgbJV6mSnUhtitaUJzHEyY6RH/c+knYmtMvqIVBl9QGM7acnVaNjibk+SGjdnc
pl9fEw+CG7WQKvnKO+UPLRf91S9QJiqI9W/i/Cif7iv4aFndDWH3fU2fp11O1V77kwkeWtoxeJBV
fG2ucImnNp9xn8q6v67APJ2NTZX7nKU5hKd4QT4DJwC8/rZRmC+yYBHPIzr/vDkUvMxbdrmILTf/
IcBWExlfdn/KnJJEi+p29Tenbjnr1HRKdRixdUnPPI9pKn2H7jy/1FmYRcGMbzLrNAnDD/lw6DkK
4qkhByDFGoWrumNwvyNxRdg8tWfkESFHrDEcQxdELxJ1Z56dYz4SH/A/t9cQEkzGk6+bPoUXW7/1
rwSYIZ8ZjSOuxbvc+z+pj5Qjqdlf4bXAUTmAA3t+3AZsTiG0iXZ2QGXBw2HGpwpUMwibEKMPA6Kb
yUUwkuGGVLKhxH4U8q1PNGtQ14Mb2HW/QE9+Gahpomr6JX6zdtz+izN8Etb3n0lEP50nSP7j2PDl
HZLCwJWDQa0T1GkMaKHMuEHsx9D75p+1eDGfDOxJpLZ7l6H0R51KYAm/JvPeM9jc4FaNRyS8GjdT
+3yTNGIZTyrdLaauE3D4tEUu+sp3HgftrZiATVo3iYl3lvnBKBFlmPUJxnct/jnAYrfz0QyXohwd
2L3GYzd5uXpbuR5gzxcVZkTCLQND5wDlvzy1TmQ+Z6sZHw5WbJkT2vetSVFNmRMb7wQ4+Y932QUl
HL1iXGhwJIjLgsTJXUMQ5/X229k5wjbZTYdmgtbSM0d/Y4gRyy59uXG9NhwwrhkGgNgdg0nLJQRe
ib23wvwMCWc24xeL1zXZFjTBgHumDLJNEjfVjA9xJ2ExI22yHKH2eYR86GGY4HIJwsc0Ov+CrIRY
X1PsWxO7kUIeuqc2Y5eSaVwF5qXHf2ua19dVYUPtz4ooVGIMwWOhc7K+RIGvqeErt5wYMjvxMzRr
khJMy/jA310Jn528Tk3a+IR7A1V5mNLVkb9Dwyk7er6a31u1kTwbIfUWGTcGsK9zOBRKcAHvO9Jp
qW4bjA1ogG0yKbSRC0FZrUzvqFsCO1S2lcVrzOWgPXrYgrYPsTJIU+XBVamHOa1pGyfI6OviUY+V
LfTnpzi0SyimRgOgHTggn5/4azP0RbVGiUkVO/tqXnqk2AlWSWHJb8sPQ4vvC1T8rvvbmZbG2hLU
VcqReLZo7o1JecI6NJNLMftH9W4pdzhkXRmMBEv9RNlLbqP6pR1UsVEbBlSGZmznK8qSPYvlKuCe
8GU9Z5TO2JW9rEaQTHgI+TDxQok4cyfqToAFbvjmeVFcq36yCAb+nV2yz07vhZMhCtwxVTMZ+AxP
o2dwk0w7SLjx1Mw8I8GeuXM7I5LY1OMVAcu0W/Bonqnhf/+bQy5lEKqeVu7TT6maGhcNrhDnuxC3
vp9TmU3OjDtQQqAwsg4Gghtv7na8GBT0WX1DyxFCPW2Qwjltodb5TAIXvNtu7ng9k71rhSlnwiyn
4aO9ZQuckrdIpX8f4VIy2X3PuVsSwie5dQwB/EUbF2i6c/cz0JUFb0eAqyHKCSJIOP5sYDKEudPU
8+Kwy8WbbSnllV0/BhMETOP5SWaVhrLEste01rbpgtCo1C3VTBpUDcvH93UhDyDq7zpwvlGF/jcG
i7WLYyKlFmqD0XdPbFD817yNSWT+rCigPyU5NasU39yH65ZStRRfGAOjnPrIE1GxxLrb/Cm1Uecc
KU4DzseyGO51hBsxvKSfISyBbsUd8fBZ4/jFDZTffrOne/PV5nRs2YehEs4C9g9XRjC08YpKA+Ah
Z3XHTqrHmG/h1Xsk0XQ9pzCi7C37YQLOgFNW63QoiEQ8Ac/DDzCzkPm8xyG8hSqoZ5OmMEBQuJLC
9GnaINxkYWZtmpWY9D2bQzSLiqFbtS+o3bjtuIGiTcfnqz0PmpVxqOowG9IdToMsNO7jMYM6I8Qg
fTeEODc/fJ0Dci0vaOdvqiqEzpx89S9MWJt50Lfy/Crwqx3PlZIGpO416TxnxEeuCQI3J4Pduavl
oyNxSacFqzr9HL4EoQISJOUtljKd7BGOuxn5QDlyRonjnxBNeJsEMVRScPHhPgTJtRXcHG/2NNdZ
keZppjJC9bpFKyhpx7EQAoZaoP1jUgyckzrY3kfKKXXZIVt21mhKvDMnfwYygQ7DwwcnPROOrWZP
+nMZcSumIrfLr5p8HLFiS7C0r3+IDO2lsccsPNXmV5bRkidCzet9rcrkJ3+ROdiEmZlnq/czQMkp
80HWvjwFVt6mbzcQBwumqDUp0bAYNyUthTMah6FcqiqZMicF8D/YbP8ANAhF/NouTvJAjPDgkCGC
e4P8qFzKga67iLbXuGktn8kPB5UZzyqUSOc5rGTtlyMmzwSGoPtK9HOEHn+oM2gySIgRlEM0uHCO
9xxvx0GGDhqnYbgMUS9TnQIRTmHGTeGBTm9/EOV1ciKsmYIj4NuU4kh0bjgICQ91ki7KaHaD9pNH
yQV8xQXNeMO53Eh8gMsxKqoT6bzdmc97re0Gj3OqrarZWoylnR4mnEae3j5oNhmmUY2vhooYv5s0
pWpqiq8rndOH8B1u3MepGLA0VrZ/w4c7L0yYwDfXtlafOWbnSO66R5PyrUUfM4zjtvjm7B6PPDxr
QtQBz/bG8IbDCE6HCV0XVlJ1XP+tWWNGTzCJIg3ymd1cOSGicb8ENxrwyjty3LMcqfiJOMkgGGMR
vwZYQtRvB4GsGzFAjqRAcBGhFonldOYa0GOUj16LmxMwKLyYWUJtCrJHLfbai1EY9YtVHkQnVyUt
1goOIXCxovgWLzustiRksoso1hCAxSvzh3W7H5J/v/JPHpdoKgQdR4+LMMm/0qi+QIlaceKQ1WEd
xT+zKokvO4c9v0grIdfZ3aihtvRN0kbZnhmYBFnYD35YXtyswSInLxslyrLFbJ9s6HgKe6iDHQ/8
W8gjmyNu2EEMuU6XwFZl9zdhjNaGQxVyKSqtc3p4PH5PbdBvNBq9DpU1Oj2+aViqBBP3DUIXrJuW
WMLvFD3/34W/mDq31EnPgaXFsvyPaKpYj0JoOAdqDQmwA8gCukFw3zl5iXUmaUC7ZNRzLwOUO3i2
DUwTK1yKBNHLVUFvH7UWwWleXiPd82pXXFJyg7QSt+4b+YQKCGlftD8W1/m19YbZ9DwYwpfFpWJu
dS2fHU1jyybNDt3bpcizvTWEGge+uB/6Fk6PRNvgfo2wQDjp/Dc+HPdxHDcWP+hq/FVuuwCRxJIA
3v0F/6XT7VVJb6HE2olTPU6gjn3GYi+muWUk35G0hpket/G9rz9JtCKiBpIwJ5vPbillXIlOaCuI
vpeSJs/VbEcsVNYHB2nKksg7UoMSSTgKlO+GYIOAVJqgY+jVULOdpCbB9ryrDsjaS7AxU4IIczaf
noDPHi/mEfB5r3SpE7wcjsBTkdx44eoiTv49FjzU6v38zLMgJvft/HiUgcfCkRabvGs650A4am0B
F+yH7Xu7VuqrMwjiHL0VynST+CHgD+gPsRlfjbvIc3V3KoECt8j8q+KYZdf2jaot7HKc9/c9nMrG
he8z3YZaYey/OrbKj2E/EplyammR90HvYAZbWOOcslEQ8w8JNvaJowCkjQ03yqni4iFBhu/eHoew
qnbIWpB1fkVCVd5EC5Gd0eZfh3j+VvRgURBEimCEV8KJz5aVTYdW3peN76PJh+OIHE1tjZBWLjgS
QjxeOoCkqtjFabDydnb9LsPrSRc3VCgK2xGFMQT/YAnnJRioY0vTwSSoqVUvOiMNKu0aXPY9ZxAj
Hl7q0jA72HhG7nx7I90U/wCM/+uYe3qEiMdH+ydgPF1Vg+lIWNhwd1iTlNInayGO5IWTd54lKci9
HBKbR7kQBtJw8XrCI3RmLoZ7W2/rUTZwKt7HkC6Z3Xlcz/6TBg2zgQqw+bpJ8zmvLO+CoEVj6ZFp
qWGKLLXHKSLsusfBLDjD/1YGI/leG1D131i+/y1ZmQd+yQ574RgGshqDIYEyCbgS1hf8e9JVVq/n
FjxKlQgeiwuJOdkeTm1rkQ5L8+NhPSzwx80Ryr9HeE1FRM6Kn/VyERPr8qR1eNS7uwoaDgBtdDwo
QmlAzwjGJXJ554qS0HZ4eOrBmfSDQMOUa7RP8cdZ82pe5ShAgPR6pWUy+7u57MU4QPpZ4Ckl90+k
EViTXnUi2uQN3kBG
`protect end_protected
|
-- Configuration for Counter Exercise
library design_library;
configuration Cfg_CounterTB of CounterTB is
for Bench
for G1: Counter
use entity design_library.counter(rtl);
end for;
end for;
end;
|
-- Configuration for Counter Exercise
library design_library;
configuration Cfg_CounterTB of CounterTB is
for Bench
for G1: Counter
use entity design_library.counter(rtl);
end for;
end for;
end;
|
-- Иммитация передачи байта от устройства к хосту по протоколу PS/2
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity web_ps2_rx is
generic (
constant MAIN_FREQ: positive := 50_000_000;
constant FREQ_DIVIDER: positive := 20_000 -- 10 kHz, clock PS/2 = 10 - 16.7 kHz
);
port (
clk, reset: in std_logic;
ps2d, ps2c: out std_logic;
rx_en: in std_logic;
rx_done: out std_logic;
data_i: in std_logic_vector(7 downto 0)
);
end web_ps2_rx;
architecture Behavioral of web_ps2_rx is
constant max_ps2_counter : natural := MAIN_FREQ / FREQ_DIVIDER;
signal ps2_counter: natural range 0 to max_ps2_counter := 0; -- счетчик для генерации частоты устройства
type state_type is (s_wait, s_data, s_end);
signal state: state_type := s_wait;
signal bit_count: unsigned(3 downto 0); -- bit counter - data + parity + stop
signal buff: std_logic_vector(9 downto 0);
signal ris_edge, fall_edge, rx_en_edge: std_logic;
signal rx_en_reg: std_logic_vector(1 downto 0);
begin
inst_ps2_clk: entity work.web_ps2_clk
port map(
clk => clk,
reset => reset,
en => rx_en,
ps2_clk => ps2c,
rising => ris_edge,
falling => fall_edge
);
proc_detect_en: process(clk, reset)
begin
if reset = '1' then
rx_en_reg <= (others => '0');
elsif rising_edge(clk) then
rx_en_reg <= rx_en_reg(0) & rx_en;
end if;
end process;
rx_en_edge <= '1' when rx_en_reg(1) = '0' and rx_en_reg(0) = '1' else '0';
proc_rx: process(clk, reset)
begin
if reset = '1' then
state <= s_wait;
bit_count <= (others => '0');
rx_done <= '0';
elsif rising_edge(clk) then
rx_done <= '0';
case state is
when s_wait =>
-- ждем включения
if rx_en_edge = '1' then
state <= s_data;
buff <= '1' -- stop bit
& (not (data_i(0) xor data_i(1) xor data_i(2) xor data_i(3) -- parity
xor data_i(4) xor data_i(5) xor data_i(6) xor data_i(7)))
& data_i; -- data
ps2d <= '0'; -- start bit
bit_count <= "1001";
end if;
when s_data =>
-- по фронту клока пс/2 передаем бит данных
if ris_edge = '1' then
ps2d <= buff(0); -- data bit
buff <= '0' & buff(9 downto 1);
if bit_count = "000" then
state <= s_end;
else
bit_count <= bit_count - 1;
end if;
end if;
when s_end =>
if fall_edge = '1' then
rx_done <= '1';
state <= s_wait;
end if;
end case;
end if;
end process;
end Behavioral;
--------------------------------------------------------------------------------------------------------------------------------------------------
-- IDLE 100us IDLE
-- | | | |
-- ____|______| ____| ____ ____ ____ ____ ____ ____ ____ ____ ____ _|___
-- CLK | |____| |____| |____| |____| |____| |____| |____| |____| |____| |____| |____| |
-- ____| | ___|____ ________ ________ ________ ________ ________ ________ ________ ________ __________|____
-- DATA |______| S __<___|D0 _><___ D1 _><___ D2 _><___ D3 _><__ D4 __><__ D5 __><__ D6 __><__ D7 __><___ P __>/ S |
-- | | | |
-- _________________________________________________________________________________________________________________
-- TX_EN ____| |___
--------------------------------------------------------------------------------------------------------------------------------------------------- |
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
clock_vga : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0);
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0) -- blue output
);
end; --comb_alu_1
architecture logic of coproc_4 is
component VGA_bitmap_640x480 is
generic(bit_per_pixel : integer range 1 to 12:=1; -- number of bits per pixel
grayscale : boolean := false); -- should data be displayed in grayscale
port(clk : in std_logic;
clk_VGA : in std_logic;
reset : in std_logic;
VGA_hs : out std_logic; -- horisontal vga syncr.
VGA_vs : out std_logic; -- vertical vga syncr.
VGA_red : out std_logic_vector(3 downto 0); -- red output
VGA_green : out std_logic_vector(3 downto 0); -- green output
VGA_blue : out std_logic_vector(3 downto 0); -- blue output
ADDR : in std_logic_vector(18 downto 0);
data_in : in std_logic_vector(bit_per_pixel - 1 downto 0);
data_write : in std_logic;
data_out : out std_logic_vector(bit_per_pixel - 1 downto 0));
end component;
SIGNAL mem : UNSIGNED(31 downto 0);
signal tmp_addr : std_logic_vector(18 downto 0);
signal pixel, tmp_out : std_logic_vector(7 downto 0);
signal data_write : std_logic;
signal counter : integer range 0 to 307199:= 0;
begin
--tmp_addr <= INPUT_1(31 downto 13);
--pixel <= INPUT_1(7 downto 0);
--
process (clock)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
counter <= 0;
ELSE
IF INPUT_1_valid = '1' THEN
IF counter < 307199 THEN
counter <= counter + 1;
ELSE
counter <= 0;
END IF;
END IF;
END IF;
END IF;
end process;
--
--
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- tmp_addr <= (others => '1');
-- pixel <= (others => '0');
-- data_write <= '0';
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- tmp_addr <= INPUT_1(31 downto 13);
-- pixel <= INPUT_1(7 downto 0);
-- data_write <= '1';
-- else
-- data_write <= '0';
-- END IF;
-- END IF;
-- END IF;
-- end process;
--
tmp_addr <= std_logic_vector(to_signed(counter, 19));
--
vga : VGA_bitmap_640x480 generic map(8, false) -- should data be displayed in grayscale
port map(
clk => clock,
clk_vga => clock_vga,
reset => reset,
VGA_hs => VGA_hs,
VGA_vs => VGA_vs,
VGA_red => VGA_red,
VGA_green => VGA_green,
VGA_blue => VGA_blue,
ADDR => tmp_addr,
data_in => INPUT_1(7 downto 0),
data_write => INPUT_1_valid,
data_out => tmp_out);
OUTPUT_1 <= "0000000000000"&tmp_addr;
-- process (clock)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
---- assert INPUT_1_valid /= '1' severity failure;
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 3, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-------------------------------------------------------------------------
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
-------------------------------------------------------------------------
-- process (clock, reset)
-- begin
-- IF clock'event AND clock = '1' THEN
-- IF reset = '1' THEN
-- mem <= TO_UNSIGNED( 0, 32);
-- ELSE
-- IF INPUT_1_valid = '1' THEN
-- mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
-- ELSE
-- mem <= mem;
-- END IF;
-- END IF;
-- END IF;
-- end process;
-- -------------------------------------------------------------------------
--
-- OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:9.5
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v9_5;
USE microblaze_v9_5.MicroBlaze;
ENTITY design_1_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END design_1_microblaze_0_0;
ARCHITECTURE design_1_microblaze_0_0_arch OF design_1_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "MicroBlaze,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_0_arch : ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze,x_ipVersion=9.5,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_SCO=0,C_FREQ=100000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_ENDIANNESS=1,C_FAMILY=artix7,C_DATA_SIZE=32,C_INSTANCE=design_1_microblaze_0_0,C_AVOID_PRIMITIVES=0,C_AREA_OPTIMIZED=0,C_OPTIMIZATION=0,C_INTERCONNECT=2,C_BASE_VECTORS=0x00000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_M_AXI_D_BUS_EXCEPTION=0,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=0,C_D_LMB=1,C_D_AXI=1,C_I_LMB=1,C_I_AXI=0,C_USE_MSR_INSTR=0,C_USE_PCMP_INSTR=0,C_USE_BARREL=0,C_USE_DIV=0,C_USE_HW_MUL=0,C_USE_FPU=0,C_USE_REORDER_INSTR=1,C_UNALIGNED_EXCEPTIONS=0,C_ILL_OPCODE_EXCEPTION=0,C_DIV_ZERO_EXCEPTION=0,C_FPU_EXCEPTION=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=0,C_FSL_EXCEPTION=0,C_USE_STACK_PROTECTION=0,C_IMPRECISE_EXCEPTIONS=0,C_USE_INTERRUPT=2,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_USE_MMU=0,C_MMU_DTLB_SIZE=4,C_MMU_ITLB_SIZE=2,C_MMU_TLB_ACCESS=3,C_MMU_ZONES=16,C_MMU_PRIVILEGED_INSTR=0,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=32,C_PVR=0,C_PVR_USER1=0x00,C_PVR_USER2=0x00000000,C_DYNAMIC_BUS_SIZING=0,C_RESET_MSR=0x00000000,C_OPCODE_0x0_ILLEGAL=0,C_DEBUG_ENABLED=1,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=5,C_DEBUG_LATENCY_COUNTERS=1,C_DEBUG_COUNTER_WIDTH=32,C_DEBUG_TRACE_SIZE=8192,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WIDTH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x60000000,C_ICACHE_HIGHADDR=0x60ffffff,C_USE_ICACHE=1,C_ALLOW_ICACHE_WR=1,C_ADDR_TAG_BITS=10,C_CACHE_BYTE_SIZE=16384,C_ICACHE_LINE_LEN=4,C_ICACHE_ALWAYS_USED=1,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x60000000,C_DCACHE_HIGHADDR=0x60ffffff,C_USE_DCACHE=1,C_ALLOW_DCACHE_WR=1,C_DCACHE_ADDR_TAG=10,C_DCACHE_BYTE_SIZE=16384,C_DCACHE_LINE_LEN=4,C_DCACHE_ALWAYS_USED=1,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORCE_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTANCE => "design_1_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"00000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"60000000",
C_ICACHE_HIGHADDR => X"60ffffff",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 10,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"60000000",
C_DCACHE_HIGHADDR => X"60ffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 10,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
Dbg_Disable => '0',
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END design_1_microblaze_0_0_arch;
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.