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---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
-- * memory mapped addresses are added!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
-- memory mapped addresses
constant NI_reserved_data_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant NI_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant NI_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
constant NI_reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010";
constant NI_self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011";
constant uart_count_value_address : std_logic_vector(29 downto 0) := "000000000000000010000000000100";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
-- change this if you want to use behavioral ram!
--component ram
-- generic(memory_type : string := "DEFAULT";
-- stim_file: string :="code.txt");
-- port(clk : in std_logic;
-- enable : in std_logic;
-- reset : in std_logic;
-- write_byte_enable : in std_logic_vector(3 downto 0);
-- address : in std_logic_vector(31 downto 2);
-- data_write : in std_logic_vector(31 downto 0);
-- data_read : out std_logic_vector(31 downto 0));
-- end component; --ram
component ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end component; -- ram
component NI
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end component; --entity NI
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
-- remove this part if you are using behavioral memory
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
component memory
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end component; --entity memory
end; --package mlite_pack
package body mlite_pack is
--function bv_adder(a : in std_logic_vector;
-- b : in std_logic_vector;
-- do_add: in std_logic) return std_logic_vector is
-- variable carry_in : std_logic;
-- variable bb : std_logic_vector(a'length-1 downto 0);
-- variable result : std_logic_vector(a'length downto 0);
--begin
-- if do_add = '1' then
-- bb := b;
-- carry_in := '0';
-- else
-- bb := not b;
-- carry_in := '1';
-- end if;
-- for index in 0 to a'length-1 loop
-- result(index) := a(index) xor bb(index) xor carry_in;
-- carry_in := (carry_in and (a(index) or bb(index))) or
-- (a(index) and bb(index));
-- end loop;
-- result(a'length) := carry_in xnor do_add;
-- return result;
--end; --function
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable A1, B1, S : UNSIGNED(a'length downto 0);
begin
A1 := resize(unsigned(a), A1'length);
B1 := resize(unsigned(b), B1'length);
if do_add = '1' then
S := A1 + B1;
else
S := A1 - B1;
end if;
return std_logic_vector(S);
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
-- * memory mapped addresses are added!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
-- memory mapped addresses
constant NI_reserved_data_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant NI_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant NI_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
constant NI_reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010";
constant NI_self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011";
constant uart_count_value_address : std_logic_vector(29 downto 0) := "000000000000000010000000000100";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
-- change this if you want to use behavioral ram!
--component ram
-- generic(memory_type : string := "DEFAULT";
-- stim_file: string :="code.txt");
-- port(clk : in std_logic;
-- enable : in std_logic;
-- reset : in std_logic;
-- write_byte_enable : in std_logic_vector(3 downto 0);
-- address : in std_logic_vector(31 downto 2);
-- data_write : in std_logic_vector(31 downto 0);
-- data_read : out std_logic_vector(31 downto 0));
-- end component; --ram
component ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end component; -- ram
component NI
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end component; --entity NI
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
-- remove this part if you are using behavioral memory
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
component memory
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end component; --entity memory
end; --package mlite_pack
package body mlite_pack is
--function bv_adder(a : in std_logic_vector;
-- b : in std_logic_vector;
-- do_add: in std_logic) return std_logic_vector is
-- variable carry_in : std_logic;
-- variable bb : std_logic_vector(a'length-1 downto 0);
-- variable result : std_logic_vector(a'length downto 0);
--begin
-- if do_add = '1' then
-- bb := b;
-- carry_in := '0';
-- else
-- bb := not b;
-- carry_in := '1';
-- end if;
-- for index in 0 to a'length-1 loop
-- result(index) := a(index) xor bb(index) xor carry_in;
-- carry_in := (carry_in and (a(index) or bb(index))) or
-- (a(index) and bb(index));
-- end loop;
-- result(a'length) := carry_in xnor do_add;
-- return result;
--end; --function
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable A1, B1, S : UNSIGNED(a'length downto 0);
begin
A1 := resize(unsigned(a), A1'length);
B1 := resize(unsigned(b), B1'length);
if do_add = '1' then
S := A1 + B1;
else
S := A1 - B1;
end if;
return std_logic_vector(S);
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
--!
--! Copyright 2020 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library commonlib;
use commonlib.types_common.all;
library ambalib;
use ambalib.types_amba4.all;
library riverlib;
use riverlib.river_cfg.all;
use riverlib.types_river.all;
entity river_dummycpu is
port (
o_msto : out axi4_l1_out_type;
o_dport : out dport_out_type;
o_flush_l2 : out std_logic
);
end;
architecture arch_river_dummycpu of river_dummycpu is
begin
o_msto <= axi4_l1_out_none;
o_dport <= dport_out_none;
o_flush_l2 <= '0';
end;
|
-- opa: Open Processor Architecture
-- Copyright (C) 2014-2016 Wesley W. Terpstra
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--
-- To apply the GPL to my VHDL, please follow these definitions:
-- Program - The entire collection of VHDL in this project and any
-- netlist or floorplan derived from it.
-- System Library - Any macro that translates directly to hardware
-- e.g. registers, IO pins, or memory blocks
--
-- My intent is that if you include OPA into your project, all of the HDL
-- and other design files that go into the same physical chip must also
-- be released under the GPL. If this does not cover your usage, then you
-- must consult me directly to receive the code under a different license.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.opa_pkg.all;
use work.opa_functions_pkg.all;
use work.opa_components_pkg.all;
library altera_mf;
use altera_mf.altera_mf_components.all;
entity opa_syn_tb is
port(
osc : in std_logic;
dip : in std_logic_vector(1 to 3);
but : in std_logic_vector(1 to 2);
led : out std_logic_vector(7 downto 0) := (others => 'Z'));
end opa_syn_tb;
architecture rtl of opa_syn_tb is
constant c_config : t_opa_config := c_opa_large;
-- How many words to run it with?
constant c_log_ram : natural := 14; -- 4*2^14 = 64kB of memory
component pll is
port(
refclk : in std_logic := 'X'; -- clk
rst : in std_logic := 'X'; -- reset
outclk_0 : out std_logic; -- clk
locked : out std_logic); -- export
end component pll;
component jtag is
port(
addr_o : out std_logic_vector(31 downto 0);
data_o : out std_logic_vector(31 downto 0);
data_i : in std_logic_vector(31 downto 0);
gpio_o : out std_logic_vector( 3 downto 0);
we_xor_o : out std_logic;
rstn_o : out std_logic);
end component jtag;
component uart is
generic(
g_wide : natural := 8;
g_deep : natural := 10);
port(
clk_i : in std_logic;
rst_n_i : in std_logic;
stb_i : in std_logic;
stall_o : out std_logic;
dat_i : in std_logic_vector(g_wide-1 downto 0);
stb_o : out std_logic;
stall_i : in std_logic;
dat_o : out std_logic_vector(g_wide-1 downto 0));
end component uart;
-- Reset
signal clk_free : std_logic;
signal locked : std_logic;
signal r_delock : std_logic := '1';
signal s_rstin : std_logic;
signal r_rstin : std_logic_vector(2 downto 0) := (others => '0');
signal r_rsth : std_logic_vector(2 downto 0) := (others => '0');
signal r_rstc : unsigned(19 downto 0) := (others => '1');
signal r_rstn : std_logic := '0';
signal r_rsttg : std_logic_vector(4 downto 0) := (others => '0');
signal rstn : std_logic;
-- Clocking
signal clk_100m : std_logic;
signal r_dip2 : std_logic_vector(dip'range);
signal r_dip1 : std_logic_vector(dip'range);
signal r_dip : std_logic_vector(dip'range);
signal r_ena : std_logic;
signal r_div : unsigned(27 downto 0);
signal r_cnt : unsigned(27 downto 0);
signal r_gate : std_logic;
signal clk : std_logic;
signal r_clk : std_logic; -- pretty clock output (1/2 clk)
-- OPA signals
signal i_cyc : std_logic;
signal i_stb : std_logic;
signal i_stall: std_logic;
signal i_ack : std_logic;
signal i_addr : std_logic_vector(c_config.adr_width-1 downto 0);
signal i_dat : std_logic_vector(31 downto 0);
signal d_cyc : std_logic;
signal d_stb : std_logic;
signal d_stall: std_logic;
signal d_we : std_logic;
signal d_ack : std_logic;
signal d_addr : std_logic_vector(c_config.adr_width-1 downto 0);
signal d_sel : std_logic_vector( 3 downto 0);
signal d_dati : std_logic_vector(31 downto 0);
signal d_dato : std_logic_vector(31 downto 0);
signal p_cyc : std_logic;
signal p_stb : std_logic;
signal p_stall: std_logic;
signal p_we : std_logic;
signal p_ack : std_logic;
signal p_addr : std_logic_vector(c_config.adr_width-1 downto 0);
signal p_sel : std_logic_vector( 3 downto 0);
signal p_dati : std_logic_vector(31 downto 0);
signal p_dato : std_logic_vector(31 downto 0);
signal s_led : std_logic_vector(c_config.num_fast+c_config.num_slow-1 downto 0);
signal d_wem : std_logic;
-- JTAG connection
signal jtag_addr : std_logic_vector(31 downto 0);
signal jtag_data : std_logic_vector(31 downto 0);
signal gpio : std_logic_vector( 3 downto 0);
signal s_we_xor : std_logic;
signal jtag_rstn : std_logic;
signal s_a_addr : std_logic_vector(c_config.adr_width-1 downto 0);
signal r_we_xor2 : std_logic;
signal r_we_xor1 : std_logic;
signal r_we_xor0 : std_logic;
signal r_we : std_logic;
-- UART flow control
signal s_uart_we : std_logic;
signal s_uart_re : std_logic;
signal s_pin : std_logic_vector(8 downto 0);
signal r_pin : std_logic_vector(8 downto 0);
signal s_uart_stall : std_logic;
-- User button presed?
signal r_but2 : std_logic;
signal r_but1 : std_logic;
signal r_but0 : std_logic;
begin
-- The free running external clock
clk_free <= osc;
-- Derive an on-chip clock
clockpll : pll
port map(
refclk => clk_free,
rst => r_delock,
outclk_0 => clk_100m,
locked => locked);
-- If we lose lock, assert r_delock
delock : process(clk_free) is
begin
if rising_edge(clk_free) then
r_delock <= not locked and r_rstn;
end if;
end process;
-- Pulse extend any short/glitchy lock loss to at least one clock period
s_rstin <= locked and but(1) and jtag_rstn;
reset_in : process(clk_free, s_rstin) is
begin
if s_rstin = '0' then
r_rstin <= (others => '0');
elsif rising_edge(clk_free) then
r_rstin <= '1' & r_rstin(r_rstin'high downto r_rstin'low+1);
end if;
end process;
-- Safely transfer reset signal into free-running clock domain (meta-stable)
reset_meta : process(clk_free) is
begin
if rising_edge(clk_free) then
r_rsth <= r_rstin(r_rstin'low) & r_rsth(r_rsth'high downto r_rsth'low+1);
end if;
end process;
-- Derive a reasonable duration reset (debounce)
reset : process(clk_free, r_rsth(r_rsth'low)) is
begin
if r_rsth(r_rsth'low) = '0' then
r_rstn <= '0';
r_rstc <= (others => '1');
elsif rising_edge(clk_free) then
if r_rstc = 0 then
r_rstn <= '1';
r_rstc <= (others => '0');
else
r_rstn <= '0';
r_rstc <= r_rstc - 1;
end if;
end if;
end process;
-- Select clock divider
clocksel : process(clk_free) is
begin
if rising_edge(clk_free) then
-- Eliminate any meta-stability (still bounces, but does not matter)
r_dip2 <= dip;
r_dip1 <= r_dip2;
r_dip <= r_dip1;
-- Decode the target clock rate
if r_dip(1) = '0' then -- dip0 => 100MHz
r_ena <= '1';
r_div <= to_unsigned(1, r_div'length);
elsif r_dip(2) = '0' then -- dip1 => 10kHz
r_ena <= '1';
r_div <= to_unsigned(10000, r_div'length);
elsif r_dip(3) = '0' then -- dip2 => 1Hz
r_ena <= '1';
r_div <= to_unsigned(100000000, r_div'length);
else -- no dip => clock disabled
r_ena <= '0';
r_div <= (others => '-');
end if;
end if;
end process;
-- Gate the clock
gate : process(clk_100m) is
begin
if rising_edge(clk_100m) then
if r_cnt >= r_div then
r_gate <= r_ena;
r_cnt <= to_unsigned(1, r_cnt'length);
else
r_gate <= '0';
r_cnt <= r_cnt + 1;
end if;
end if;
end process;
-- Use a hardware clock gate at the clock network source
clockmux : altclkctrl
generic map(
number_of_clocks => 1)
port map(
ena => r_gate,
inclk(0) => clk_100m,
outclk => clk);
-- Inject reset from free running clock to target domain (remove meta-stability)
reset_target : process(clk) is
begin
if rising_edge(clk) then
r_rsttg <= r_rstn & r_rsttg(r_rsttg'high downto r_rsttg'low+1);
end if;
end process;
rstn <= r_rsttg(0);
opa_core : opa
generic map(
g_isa => T_OPA_LM32,
g_config => c_config,
g_target => c_opa_cyclone_v)
port map(
clk_i => clk,
rst_n_i => rstn,
i_cyc_o => i_cyc,
i_stb_o => i_stb,
i_stall_i => i_stall,
i_ack_i => i_ack,
i_err_i => '0',
i_addr_o => i_addr,
i_data_i => i_dat,
d_cyc_o => d_cyc,
d_stb_o => d_stb,
d_we_o => d_we,
d_stall_i => d_stall,
d_ack_i => d_ack,
d_err_i => '0',
d_addr_o => d_addr,
d_sel_o => d_sel,
d_data_o => d_dato,
d_data_i => d_dati,
p_cyc_o => p_cyc,
p_stb_o => p_stb,
p_we_o => p_we,
p_stall_i => p_stall,
p_ack_i => p_ack,
p_err_i => '0',
p_addr_o => p_addr,
p_sel_o => p_sel,
p_data_o => p_dato,
p_data_i => p_dati,
status_o => s_led);
led(7) <= '0' when r_clk ='1' else 'Z';
led(6) <= '0' when gpio(3) ='1' else 'Z';
led(5) <= '0' when gpio(2) ='1' else 'Z';
led(4) <= '0' when gpio(1) ='1' else 'Z';
led(3) <= '0' when gpio(0) ='1' else 'Z';
activity : for i in s_led'range generate
led(i) <= '0' when s_led(i)='1' else 'Z';
end generate;
d_wem <= d_cyc and d_stb and d_we;
ext : jtag
port map(
addr_o => jtag_addr,
data_o => jtag_data,
data_i => i_dat,
gpio_o => gpio,
we_xor_o => s_we_xor,
rstn_o => jtag_rstn);
a_we : process(clk) is
begin
if rising_edge(clk) then
r_we_xor0 <= s_we_xor;
r_we_xor1 <= r_we_xor0;
r_we_xor2 <= r_we_xor1;
r_we <= r_we_xor1 xor r_we_xor2;
end if;
end process;
s_a_addr <= jtag_addr(s_a_addr'range) when jtag_rstn='0' else i_addr;
i_stall <= '0';
d_stall <= '0';
ram : opa_tdpram
generic map(
g_width => 8,
g_size => 2**c_log_ram,
g_hunks => 4)
port map(
clk_i => clk,
rst_n_i => '1', -- run even while CPU reset
a_wen_i => r_we,
a_sel_i => (others => '1'),
a_addr_i => s_a_addr(c_log_ram+1 downto 2),
a_data_i => jtag_data,
a_data_o => i_dat,
b_wen_i => d_wem,
b_sel_i => d_sel,
b_addr_i => d_addr(c_log_ram+1 downto 2),
b_data_i => d_dato,
b_data_o => d_dati);
idpbus : process(clk) is
begin
if rising_edge(clk) then
i_ack <= i_cyc and i_stb and not i_stall;
d_ack <= d_cyc and d_stb and not d_stall;
p_ack <= p_cyc and p_stb and not p_stall;
r_pin <= s_pin;
r_clk <= not r_clk;
end if;
end process;
s_uart_we <= p_cyc and p_stb and p_we and p_sel(0);
s_uart_re <= p_cyc and p_stb and not p_we;
p_stall <= s_uart_stall and p_we;
io : uart
port map(
clk_i => clk,
rst_n_i => rstn,
stb_i => s_uart_we,
stall_o => s_uart_stall,
dat_i => p_dato(7 downto 0),
stb_o => s_pin(8),
stall_i => "not"(s_uart_re),
dat_o => s_pin(7 downto 0));
button : process(clk) is
begin
if rising_edge(clk) then
r_but2 <= but(2);
r_but1 <= r_but2;
r_but0 <= r_but1;
end if;
end process;
p_dati(31) <= not r_but0;
p_dati(30 downto 9) <= (others => '0');
p_dati( 8 downto 0) <= r_pin;
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:26:35 02/25/2015
-- Design Name:
-- Module Name: DEBUG_CONTROLLER - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEBUG_CONTROLLER is
Port( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0));
end DEBUG_CONTROLLER;
architecture Structural of DEBUG_CONTROLLER is
signal RD : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal KEY_DATA : STD_LOGIC_VECTOR (7 downto 0);
signal TO_SEG : STD_LOGIC_VECTOR(15 downto 0);
signal cen : STD_LOGIC := '0';
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
U1: entity work.KEYBOARD_CONTROLLER
Port MAP ( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
ASCII_OUT => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE);
U2: entity work.ASCII_BUFFER
port MAP(
ASCII_DATA => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE,
CLK => CLK,
RST => RST,
ASCII_BUFF => TO_SEG);
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => '0',
EN => enl,
SEG_0 => TO_SEG(15 downto 12),
SEG_1 => TO_SEG(11 downto 8),
SEG_2 => TO_SEG(7 downto 4),
SEG_3 => TO_SEG(3 downto 0),
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
end Structural;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 12:26:35 02/25/2015
-- Design Name:
-- Module Name: DEBUG_CONTROLLER - Structural
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity DEBUG_CONTROLLER is
Port( CLK : in STD_LOGIC;
RST : in STD_LOGIC;
PS2_CLK : inout STD_LOGIC;
PS2_DATA : inout STD_LOGIC;
SEG : out STD_LOGIC_VECTOR (6 downto 0);
DP : out STD_LOGIC;
AN : out STD_LOGIC_VECTOR (3 downto 0));
end DEBUG_CONTROLLER;
architecture Structural of DEBUG_CONTROLLER is
signal RD : STD_LOGIC := '0';
signal WE : STD_LOGIC := '0';
signal KEY_DATA : STD_LOGIC_VECTOR (7 downto 0);
signal TO_SEG : STD_LOGIC_VECTOR(15 downto 0);
signal cen : STD_LOGIC := '0';
signal enl : STD_LOGIC := '1';
signal dpc : STD_LOGIC_VECTOR (3 downto 0) := "1111";
begin
U1: entity work.KEYBOARD_CONTROLLER
Port MAP ( CLK => CLK,
RST => RST,
PS2_CLK => PS2_CLK,
PS2_DATA => PS2_DATA,
ASCII_OUT => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE);
U2: entity work.ASCII_BUFFER
port MAP(
ASCII_DATA => KEY_DATA,
ASCII_RD => RD,
ASCII_WE => WE,
CLK => CLK,
RST => RST,
ASCII_BUFF => TO_SEG);
SSeg: entity work.SSegDriver
port map( CLK => CLK,
RST => '0',
EN => enl,
SEG_0 => TO_SEG(15 downto 12),
SEG_1 => TO_SEG(11 downto 8),
SEG_2 => TO_SEG(7 downto 4),
SEG_3 => TO_SEG(3 downto 0),
DP_CTRL => dpc,
COL_EN => cen,
SEG_OUT => SEG,
DP_OUT => DP,
AN_OUT => AN);
end Structural;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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X+aHlkGCqQ==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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0o+Aohk6G+pMSODO+G0=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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er9BVocWwryEwtZ+yt7WIpHgGpzuUrIF4+jJGQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62832)
`protect data_block
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|
`protect begin_protected
`protect version = 1
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`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_block
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`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 62832)
`protect data_block
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iznuqg+0s/3oKJpz7LOsy6Pa
`protect end_protected
|
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- cMIPS, a VHDL model of the classical five stage MIPS pipeline.
-- Copyright (C) 2013 Roberto Andre Hexsel
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, version 3.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- To simplify (and accelerate) internal address decoding,
-- the BASE of the RAM addresses MUST be allocated at an
-- address that is larger the RAM capacity. Otherwise, the
-- base must be subtracted from the address on every reference,
-- which means having an adder in the critical path. Bad idea.
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous RAM for synthesis; NON-initialized, byte-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use work.p_wires.all;
use work.p_memory.all;
entity RAM is
generic (LOAD_FILE_NAME : string := "data.bin";
DUMP_FILE_NAME : string := "dump.data");
port (rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
rdy : out std_logic; -- active in '0'
wr : in std_logic; -- active in '0'
strobe : in std_logic; -- active in '1'
addr : in reg32;
data_inp : in reg32;
data_out : out reg32;
byte_sel : in reg4;
dump_ram : in std_logic); -- dump RAM contents
-- simulation version
constant DATA_ADDRS_BITS : natural := log2_ceil(DATA_MEM_SZ);
-- FPGA version
constant N_WORDS : natural := 8192;
constant ADDRS_BITS : natural := log2_ceil(N_WORDS);
subtype ram_address is integer range 0 to N_WORDS-1;
subtype ram_addr_bits is std_logic_vector(ADDRS_BITS-1 downto 0);
end entity RAM;
architecture rtl of RAM is
component mf_ram1port
generic (N_WORDS : integer; ADDRS_BITS : integer);
port (address : in std_logic_vector (ADDRS_BITS-1 downto 0);
clken : in std_logic;
clock : in std_logic;
data : in std_logic_vector (7 downto 0);
wren : in std_logic;
q : out std_logic_vector (7 downto 0));
end component mf_ram1port;
component wait_states is
generic (NUM_WAIT_STATES :integer);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
signal we0,we1,we2,we3 : std_logic := '0';
signal di,do : reg32;
signal r_addr : ram_address := 0;
signal r_address : ram_addr_bits;
signal waiting, enable : std_logic;
begin -- rtl
U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
enable <= not(sel);
-- CPU acesses are word-addressed; RAM is byte-addressed, 4-bytes wide
r_addr <= to_integer( unsigned(addr( (ADDRS_BITS-1+2) downto 2 ) ) );
r_address <= addr( ADDRS_BITS-1+2 downto 2 );
U_ram0: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(7 downto 0), we0, do(7 downto 0));
U_ram1: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(15 downto 8), we1, do(15 downto 8));
U_ram2: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(23 downto 16), we2, do(23 downto 16));
U_ram3: mf_ram1port generic map (N_WORDS, ADDRS_BITS) port map (
r_address, enable, strobe, di(31 downto 24), we3, do(31 downto 24));
accessRAM: process(sel, strobe, wr, r_addr, byte_sel, data_inp, do)
begin
if sel = '0' then
if wr = '0' then -- WRITE to MEM
assert (r_addr >= 0) and (r_addr < (DATA_MEM_SZ/4))
report "ramWR index out of bounds: " & natural'image(r_addr)
severity failure;
case byte_sel is -- partial word stores
when b"1111" => -- SW
we3 <= '1';
we2 <= '1';
we1 <= '1';
we0 <= '1';
di <= data_inp;
when b"1100" => -- SH, upper
we3 <= '1';
we2 <= '1';
we1 <= '0';
we0 <= '0';
di(31 downto 16) <= data_inp(15 downto 0);
di(15 downto 0) <= (others => 'X');
when b"0011" => -- SH. lower
we3 <= '0';
we2 <= '0';
we1 <= '1';
we0 <= '1';
di(15 downto 0) <= data_inp(15 downto 0);
di(31 downto 16) <= (others => 'X');
when b"0001" => -- SB
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '1';
di(7 downto 0) <= data_inp(7 downto 0);
di(31 downto 8) <= (others => 'X');
when b"0010" =>
we3 <= '0';
we2 <= '0';
we1 <= '1';
we0 <= '0';
di(31 downto 16) <= (others => 'X');
di(15 downto 8) <= data_inp(7 downto 0);
di(7 downto 0) <= (others => 'X');
when b"0100" =>
we3 <= '0';
we2 <= '1';
we1 <= '0';
we0 <= '0';
di(31 downto 24) <= (others => 'X');
di(23 downto 16) <= data_inp(7 downto 0);
di(15 downto 0) <= (others => 'X');
when b"1000" =>
we3 <= '1';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di(31 downto 24) <= data_inp(7 downto 0);
di(23 downto 0) <= (others => 'X');
when others =>
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
end case;
assert TRUE report "ramWR["& natural'image(r_addr) &"] "
& SLV32HEX(data_inp) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
data_out <= (others => 'X');
else -- READ from MEM, wr /= 0
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
assert (r_addr >= 0) and (r_addr < (DATA_MEM_SZ/4))
report "ramRD index out of bounds: " & natural'image(r_addr)
severity failure;
-- byte/half selection done at CPU
data_out(31 downto 24) <= do(31 downto 24);
data_out(23 downto 16) <= do(23 downto 16);
data_out(15 downto 8) <= do(15 downto 8);
data_out(7 downto 0) <= do(7 downto 0);
assert TRUE report "ramRD["& natural'image(r_addr) &"] "
& SLV32HEX(do) &" bySel="& SLV2STR(byte_sel); -- DEBUG
end if; -- wr
else -- sel /= 0
we3 <= '0';
we2 <= '0';
we1 <= '0';
we0 <= '0';
di <= (others => 'X');
data_out <= (others => 'X');
end if;
end process accessRAM;
end architecture rtl;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
-- syncronous RAM; initialization Data loaded at CPU reset, byte-indexed
-- ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
architecture simulation of RAM is
component wait_states is
generic (NUM_WAIT_STATES :integer := 0);
port(rst : in std_logic;
clk : in std_logic;
sel : in std_logic; -- active in '0'
waiting : out std_logic); -- active in '1'
end component wait_states;
component FFT is
port(clk, rst, T : in std_logic; Q : out std_logic);
end component FFT;
constant WAIT_COUNT : max_wait_states := NUM_MAX_W_STS - RAM_WAIT_STATES;
signal wait_counter, ram_current : integer;
subtype t_address is unsigned((DATA_ADDRS_BITS - 1) downto 0);
subtype word is std_logic_vector(7 downto 0);
type storage_array is
array (natural range 0 to (DATA_MEM_SZ - 1)) of word;
signal storage : storage_array;
signal enable, waiting, do_wait : std_logic;
begin -- simulation
U_BUS_WAIT: wait_states generic map (RAM_WAIT_STATES)
port map (rst, clk, sel, waiting);
rdy <= not(waiting);
enable <= not(sel); -- and not(waiting);
accessRAM: process(strobe,enable, wr,rst, addr,byte_sel, data_inp,dump_ram)
variable u_addr : t_address;
variable index, latched : natural;
type binary_file is file of integer;
file load_file: binary_file open read_mode is LOAD_FILE_NAME;
variable datum: integer;
variable s_datum: unsigned(31 downto 0);
file dump_file: binary_file open write_mode is DUMP_FILE_NAME;
variable d : reg32 := (others => 'X');
variable val, i : integer;
begin
if rst = '0' then -- reset, read-in binary initialized data
index := 0; -- byte indexed
for i in 0 to (DATA_MEM_SZ - 1) loop
if not endfile(load_file) then
read(load_file, datum);
s_datum := to_unsigned(datum, 32);
assert TRUE report "ramINIT["& natural'image(index*4)&"]= " &
SLV32HEX(std_logic_vector(s_datum)); -- DEBUG
storage(index+3) <= std_logic_vector(s_datum(31 downto 24));
storage(index+2) <= std_logic_vector(s_datum(23 downto 16));
storage(index+1) <= std_logic_vector(s_datum(15 downto 8));
storage(index+0) <= std_logic_vector(s_datum(7 downto 0));
index := index + 4;
end if;
end loop;
data_out <= (others=>'X');
else -- (rst = '1'), normal operation
if sel = '0' and wr = '0' and rising_edge(strobe) then
-- only access RAM if address is valid (sel = '0')
u_addr := unsigned(addr( (DATA_ADDRS_BITS-1) downto 0 ) );
index := to_integer(u_addr);
assert (index >= 0) and (index < DATA_MEM_SZ)
report "ramWR index out of bounds: " & natural'image(index)
severity failure;
case byte_sel is
when b"1111" => -- SW
storage(index+3) <= data_inp(31 downto 24);
storage(index+2) <= data_inp(23 downto 16);
storage(index+1) <= data_inp(15 downto 8);
storage(index+0) <= data_inp(7 downto 0);
when b"1100" | b"0011" => -- SH
storage(index+1) <= data_inp(15 downto 8);
storage(index+0) <= data_inp(7 downto 0);
when b"0001" | b"0010" | b"0100" | b"1000" => -- SB
storage(index+0) <= data_inp(7 downto 0);
when others => null;
end case;
assert TRUE report "ramWR["& natural'image(index) &"] "
& SLV32HEX(data_inp) &" bySel=" & SLV2STR(byte_sel); -- DEBUG
end if; -- is write?
if sel = '0' and wr = '1' then
-- only access RAM if address is valid (sel = '0')
u_addr := unsigned(addr( (DATA_ADDRS_BITS-1) downto 0 ) );
index := to_integer(u_addr);
assert (index >= 0) and (index < DATA_MEM_SZ)
report "ramRD index out of bounds: " & natural'image(index)
severity failure;
case byte_sel is
when b"1111" => -- LW
d(31 downto 24) := storage(index+3);
d(23 downto 16) := storage(index+2);
d(15 downto 8) := storage(index+1);
d(7 downto 0) := storage(index+0);
when b"1100" => -- LH top-half
d(31 downto 24) := storage(index+1);
d(23 downto 16) := storage(index+0);
d(15 downto 0) := (others => 'X');
when b"0011" => -- LH bottom-half
d(31 downto 16) := (others => 'X');
d(15 downto 8) := storage(index+1);
d(7 downto 0) := storage(index+0);
when b"0001" => -- LB top byte
d(31 downto 8) := (others => 'X');
d(7 downto 0) := storage(index+0);
when b"0010" => -- LB mid-top byte
d(31 downto 16) := (others => 'X');
d(15 downto 8) := storage(index+0);
d(7 downto 0) := (others => 'X');
when b"0100" => -- LB mid-bot byte
d(31 downto 24) := (others => 'X');
d(23 downto 16) := storage(index+0);
d(15 downto 0) := (others => 'X');
when b"1000" => -- LB bottom byte
d(31 downto 24) := storage(index+0);
d(23 downto 0) := (others => 'X');
when others => d := (others => 'X');
end case;
assert TRUE report "ramRD["& natural'image(index) &"] "
& SLV32HEX(d) &" bySel="& SLV2STR(byte_sel); -- DEBUG
elsif rising_edge(dump_ram) then
i := 0;
while i < DATA_MEM_SZ-4 loop
d(31 downto 24) := storage(i+3);
d(23 downto 16) := storage(i+2);
d(15 downto 8) := storage(i+1);
d(7 downto 0) := storage(i+0);
write( dump_file, to_integer(signed(d)) );
i := i+4;
end loop; -- i
else
d := (others=>'X');
end if; -- is read?
data_out <= d;
end if; -- is reset?
end process accessRAM; -- ---------------------------------------------
end architecture simulation;
-- +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
|
--!
--! @file: exercise6_7.vhd
--! @brief: Binary Sorter with Loop
--! @author: Antonio Gutierrez
--! @date: 2013-10-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
entity binary_sorter is
generic (N: integer := 5);
port (
input: in bit_vector(N-1 downto 0);
output: out bit_vector(N-1 downto 0));
end entity binary_sorter;
--------------------------------------
architecture circuit of binary_sorter is
begin
proc: process (input)
variable count: integer range 0 to N := 0;
variable output_buffer: std_logic_vector(N-1 downto 0);
begin
-- first loop: counts the number of 1's there are in the vector
forloop: for i in 0 to N-1 loop
if (input(i) = '1') then
count = count + 1;
end if;
end loop forloop;
-- second loop: assigns 1's at the beginning and then the rest is 0
forloop1: for i in N-1 downto (N-1)-count loop
if (count = 0) then
output(i) <= '0';
else
output(i) <= '1';
end if;
count = count - 1;
end loop forloop1;
end process proc;
end architecture circuit;
--------------------------------------
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:54:55 10/16/2016
-- Design Name:
-- Module Name: MainMemorySpartan6 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_arith.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
use work.util.all;
entity MainMemorySpartan6 is
generic (
NUMBANKS: natural:=1 -- number of RAM16B Banks, each Bank has 4*2K*8 BRAMS
);
Port ( DBOut : out STD_LOGIC_VECTOR (31 downto 0);
DBIn : in STD_LOGIC_VECTOR (31 downto 0);
AdrBus : in STD_LOGIC_VECTOR (10+log2(NUMBANKS) downto 0);
ENA : in STD_LOGIC;
WREN : in STD_LOGIC_VECTOR (3 downto 0);
CLK : in STD_LOGIC;
-- Second Port ( read only)
CLKB : in STD_LOGIC;
ENB : in STD_LOGIC;
AdrBusB : in STD_LOGIC_VECTOR (10+log2(NUMBANKS) downto 0);
DBOutB : out STD_LOGIC_VECTOR (31 downto 0)
);
end MainMemorySpartan6;
architecture Behavioral of MainMemorySpartan6 is
subtype word is STD_LOGIC_VECTOR (31 downto 0);
type tBusMux is array (0 to NUMBANKS-1) of STD_LOGIC_VECTOR (31 downto 0);
signal ena_v,enb_v : std_logic_vector (NUMBANKS-1 downto 0);
signal upper_adr_a,upper_adr_b : std_logic_vector (log2(NUMBANKS)-1 downto 0);
signal BusMuxA,BusMuxB : tBusMux;
COMPONENT ram2048x8
PORT(
DInA : IN std_logic_vector(7 downto 0);
AdrA : IN std_logic_vector(10 downto 0);
ENA : IN std_logic;
WRENA : IN std_logic;
CLKA : IN std_logic;
AdrB : IN std_logic_vector(10 downto 0);
ENB : IN std_logic;
CLKB : IN std_logic;
DOutA : OUT std_logic_vector(7 downto 0);
DoutB : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
begin
upper_adr_a <= AdrBus(AdrBus'length-1 downto 11);
upper_adr_b <= AdrBusB(AdrBusB'length-1 downto 11);
genmem: for i in 0 to NUMBANKS-1 generate
begin
Inst_ram2048x8_0: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(7 downto 0),
DInA => DBIn(7 downto 0),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(0),
CLKA => clk,
DoutB => BusMuxB(i)(7 downto 0),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_1: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(15 downto 8),
DInA => DBIn(15 downto 8),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(1),
CLKA => clk,
DoutB => BusMuxB(i)(15 downto 8),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_2: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(23 downto 16),
DInA => DBIn(23 downto 16),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(2),
CLKA => clk,
DoutB => BusMuxB(i)(23 downto 16),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
Inst_ram2048x8_3: ram2048x8 PORT MAP(
DOutA => BusMuxA(i)(31 downto 24),
DInA => DBIn(31 downto 24),
AdrA => AdrBus(10 downto 0),
ENA => ena_v(i),
WRENA => wren(3),
CLKA => clk,
DoutB => BusMuxB(i)(31 downto 24),
AdrB => AdrBusB(10 downto 0),
ENB => enb_v(i),
CLKB => clkb
);
end generate;
MuxA: process(upper_adr_a,ena,BusMuxA)
variable env: std_logic_vector (NUMBANKS-1 downto 0);
variable mux: std_logic_vector(31 downto 0);
begin
mux:=(others=>'0');
for i in 0 to NUMBANKS-1 loop
if upper_adr_a=CONV_STD_LOGIC_VECTOR(i,upper_adr_a'length) and ena='1' then
env(i):='1';
else
env(i):='0';
end if;
for k in DBOut'range loop
mux(k) := mux(k) or (BusMuxA(i)(k) and env(i));
end loop;
end loop;
ena_v<=env;
DBOut<=mux;
end process;
MuxB: process(upper_adr_b,enb,BusMuxB)
variable env: std_logic_vector (NUMBANKS-1 downto 0);
variable mux: std_logic_vector(31 downto 0);
begin
mux:=(others=>'0');
for i in 0 to NUMBANKS-1 loop
if upper_adr_b=CONV_STD_LOGIC_VECTOR(i,upper_adr_b'length) and enb='1' then
env(i):='1';
else
env(i):='0';
end if;
for k in DBOut'range loop
mux(k) := mux(k) or (BusMuxB(i)(k) and env(i));
end loop;
end loop;
enb_v<=env;
DBOutB<=mux;
end process;
end Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_delay_GNC4JNSRBA is
generic ( ClockPhase : string := "1";
delay : positive := 1;
use_init : natural := 1;
BitPattern : string := "0000000100101100";
width : positive := 16);
port(
aclr : in std_logic;
clock : in std_logic;
ena : in std_logic;
input : in std_logic_vector((width)-1 downto 0);
output : out std_logic_vector((width)-1 downto 0);
sclr : in std_logic);
end entity;
architecture rtl of alt_dspbuilder_delay_GNC4JNSRBA is
Begin
-- Delay Element, with reset value
DelayWithInit : alt_dspbuilder_SInitDelay generic map (
LPM_WIDTH => 16,
LPM_DELAY => 1,
SequenceLength => 1,
SequenceValue => "1",
ResetValue => "0000000100101100")
port map (
dataa => input,
clock => clock,
ena => ena,
sclr => sclr,
aclr => aclr,
user_aclr => '0',
result => output);
end architecture; |
library ieee;
use ieee.std_logic_1164.all;
-- 15-bit carry look-ahead adder
entity carry_lookahead_adder is
port (
a : in std_logic_vector (14 downto 0);
b : in std_logic_vector (14 downto 0);
ci : in std_logic;
s : out std_logic_vector (14 downto 0);
co : out std_logic
);
end carry_lookahead_adder;
architecture behavioral of carry_lookahead_adder is
signal t : std_logic_vector(14 DOWNTO 0);
signal g : std_logic_vector(14 DOWNTO 0);
signal p : std_logic_vector(14 DOWNTO 0);
signal c : std_logic_vector(14 DOWNTO 1);
begin
-- Product stage
g <= a and b;
p <= a or b;
-- Sum stage
t <= a xor b;
-- Carry stage
c(1) <= g(0) or (p(0) and ci);
carry_loop: for i in 1 to 13 generate
c(i+1) <= g(i) or (p(i) and c(i));
end generate;
co <= g(14) or (p(14) and c(14));
s(0) <= t(0) xor ci;
s(14 downto 1) <= t(14 downto 1) xor c(14 downto 1);
end behavioral;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
-- Entity: svga2ch7301c
-- File: svga2ch7301c.vhd
-- Author: Jan Andersson - Aeroflex Gaisler AB
-- [email protected]
--
-- Description: Converter inteneded to connect a SVGACTRL core to a Chrontel
-- CH7301C DVI transmitter. Multiplexes data and generates clocks.
-- Tailored for use on the Xilinx ML50x boards with Leon3/GRLIB
-- template designs.
--
-- This multiplexer has been developed for use with the Chrontel CH7301C DVI
-- transmitter. Supported multiplexed formats are, as in the CH7301 datasheet:
--
-- IDF Description
-- 0 12-bit multiplexed RGB input (24-bit color), (scheme 1)
-- 1 12-bit multiplexed RGB2 input (24-bit color), (scheme 2)
-- 2 8-bit multiplexed RGB input (16-bit color, 565)
-- 3 8-bit multiplexed RGB input (15-bit color, 555)
--
-- This core assumes a 100 MHz input clock on the 'clk' input.
--
-- If the generic 'dynamic' is non-zero the core uses the value vgao.bitdepth
-- to decide if multiplexing should be done according to IDF 0 or IDF 2.
-- vago.bitdepth = "11" gives IDF 0, others give IDF2.
-- The 'idf' generic is not used when the 'dynamic' generic is non-zero.
-- Note that if dynamic selection is enabled you will need to reconfigure
-- the DVI transmitter when the VGA core changes bit depth.
--
library ieee;
use ieee.std_logic_1164.all;
library gaisler;
use gaisler.misc.all;
library grlib;
use grlib.stdlib.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.DCM;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity svga2ch7301c is
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk100 : in std_ulogic;
clk125 : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
clkvga : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end svga2ch7301c;
architecture rtl of svga2ch7301c is
component BUFG port (O : out std_logic; I : in std_logic); end component;
constant VERSION : integer := 1;
signal vcc, gnd : std_logic;
signal d0, d1 : std_logic_vector(11 downto 0);
signal red, green, blue : std_logic_vector(7 downto 0);
signal lvgaclk, vgaclk, clk40, clk65, clk50, clk25 : std_ulogic;
signal clkval : std_logic_vector(1 downto 0);
signal clkval40 : std_logic_vector(1 downto 0);
signal clkval65 : std_logic_vector(1 downto 0);
begin -- rtl
vcc <= '1'; gnd <= '0';
-----------------------------------------------------------------------------
-- RGB data multiplexer
-----------------------------------------------------------------------------
red <= vgao.video_out_r;
green <= vgao.video_out_g;
blue <= vgao.video_out_b;
clkvga <= vgaclk;
static: if dynamic = 0 generate
idf0: if (idf = 0) generate
d0 <= green(3 downto 0) & blue(7 downto 0);
d1 <= red(7 downto 0) & green(7 downto 4);
end generate;
idf1: if (idf = 1) generate
d0 <= green(4 downto 2) & blue(7 downto 3) & green(0) & blue(2 downto 0);
d1 <= red(7 downto 3) & green(7 downto 5) & red(2 downto 0) & green(1);
end generate;
idf2: if (idf = 2) generate
d0(11 downto 4) <= green(4 downto 2) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= red(7 downto 3) & green(7 downto 5);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate;
idf3: if (idf = 3) generate
d0(11 downto 4) <= green(5 downto 3) & blue(7 downto 3);
d0(3 downto 0) <= (others => '0');
d1(11 downto 4) <= '0' & red(7 downto 3) & green(7 downto 6);
d1(3 downto 0) <= (others => '0');
data(3 downto 0) <= (others => '0');
end generate idf3;
-- DDR regs
dataregs: for i in 11 downto (4*(idf/2)) generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
nostatic: if dynamic /= 0 generate
d0 <= green(3 downto 0) & blue(7 downto 0) when vgao.bitdepth = "11" else
green(4 downto 2) & blue(7 downto 3) & "0000";
d1 <= red(7 downto 0) & green(7 downto 4) when vgao.bitdepth = "11" else
red(7 downto 3) & green(7 downto 5) & "0000";
dataregs: for i in 11 downto 0 generate
ddr_oreg0 : ddr_oreg generic map (tech)
port map (q => data(i), c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => d0(i), d2 => d1(i), r => gnd, s => gnd);
end generate;
end generate;
-----------------------------------------------------------------------------
-- Sync signals
-----------------------------------------------------------------------------
process (vgaclk)
begin -- process
if rising_edge(vgaclk) then
hsync <= vgao.hsync;
vsync <= vgao.vsync;
de <= vgao.blank;
end if;
end process;
-----------------------------------------------------------------------------
-- Clock generation
-----------------------------------------------------------------------------
ddroreg_p : ddr_oreg generic map (tech)
port map (q => dclk_p, c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => vcc, d2 => gnd, r => gnd, s => gnd);
ddroreg_n : ddr_oreg generic map (tech)
port map (q => dclk_n, c1 => vgaclk, c2 => gnd, ce => vcc,
d1 => gnd, d2 => vcc, r => gnd, s => gnd);
-- Clock selection
bufg00 : BUFG port map (I => lvgaclk, O => vgaclk);
lvgaclk <= clk25 when clksel = "00" else clk40 when clksel = "01"
else clk50 when clksel = "10" else clk65;
-- Generate clocks
clkdiv : process(clk100, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk100) then
clkval <= clkval + 1;
end if;
end process;
clkdiv65 : process(clk125, rstn)
begin
if rstn = '0' then clkval65 <= "00"; clkval40 <= "00";
elsif rising_edge(clk125) then
clkval65 <= clkval65 + 1;
if clkval40 = "10" then clkval40 <= "00";
else clkval40 <= clkval40 + 1; end if;
end if;
end process;
clk25 <= clkval(1);
clk50 <= clkval(0);
clk40 <= clkval40(1);
clk65 <= clkval65(0);
end rtl;
|
---------------------------------------------------------
---
-- Test Bench for Four Bit Up-Down Counter
-- File name : counter_sig_tb.vhd
---------------------------------------------------------
---
Library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.std_logic_signed.ALL;
architecture tb_counter_var of test is
component counter_sig
port( UP, CLK, RESET : in std_logic;
OUT1 : out std_logic;
OUT2 : out std_logic_vector(3 downto 0)
);
end component;
signal UP : std_logic := '1';
signal RESET : std_logic := '0';
signal CLK : std_logic := '0';
signal Out1 : std_logic := '0';
signal Out2 : std_logic_vector(3 downto 0):=(others=>'0');
for U1:counter_sig use entity work.counter_sig(Arch_counter_var);
begin
U1: counter_sig port map ( UP, CLK, RESET, OUT1, OUT2);
RESET <= '1' after 125 ns;
CLK <= not(CLK) after 50 ns;
-----------------------------------------------------
tb: process
begin
UP <= transport '0' after 945 ns;
UP <= transport '1' after 1825 ns;
UP <= transport '0' after 2025 ns;
wait;
end process; --tb
-----------------------------------------------------
end; -- tb_counter_var
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1525.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01525ent IS
END c08s09b00x00p08n01i01525ent;
ARCHITECTURE c08s09b00x00p08n01i01525arch OF c08s09b00x00p08n01i01525ent IS
BEGIN
TESTING: PROCESS
BEGIN
while not '0' loop
end loop;
assert FALSE
report "***FAILED TEST: c08s09b00x00p08n01i01525 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01525arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1525.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01525ent IS
END c08s09b00x00p08n01i01525ent;
ARCHITECTURE c08s09b00x00p08n01i01525arch OF c08s09b00x00p08n01i01525ent IS
BEGIN
TESTING: PROCESS
BEGIN
while not '0' loop
end loop;
assert FALSE
report "***FAILED TEST: c08s09b00x00p08n01i01525 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01525arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1525.vhd,v 1.2 2001-10-26 16:30:10 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s09b00x00p08n01i01525ent IS
END c08s09b00x00p08n01i01525ent;
ARCHITECTURE c08s09b00x00p08n01i01525arch OF c08s09b00x00p08n01i01525ent IS
BEGIN
TESTING: PROCESS
BEGIN
while not '0' loop
end loop;
assert FALSE
report "***FAILED TEST: c08s09b00x00p08n01i01525 - while condition is not boolean expression"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s09b00x00p08n01i01525arch;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grfpwx
-- File: grfpwx.vhd
-- Author: Edvin Catovic - Gaisler Research
-- Description: GRFPU/GRFPC wrapper and FP register file
------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
use techmap.netcomp.all;
library gaisler;
use gaisler.leon3.all;
use gaisler.libleon3.all;
use gaisler.libfpu.all;
entity grfpwx is
generic (fabtech : integer := 0;
memtech : integer := 0;
mul : integer range 0 to 3 := 0;
pclow : integer range 0 to 2 := 2;
dsu : integer range 0 to 1 := 0;
disas : integer range 0 to 2 := 0;
netlist : integer := 0;
index : integer := 0);
port (
rst : in std_ulogic; -- Reset
clk : in std_ulogic;
holdn : in std_ulogic; -- pipeline hold
cpi : in fpc_in_type;
cpo : out fpc_out_type
);
end;
architecture rtl of grfpwx is
signal rfi1, rfi2 : fp_rf_in_type;
signal rfo1, rfo2 : fp_rf_out_type;
signal rf1rd1, rf1rd2, rf2rd1, rf2rd2, rf1wd, rf2wd : std_logic_vector(38 downto 0);
begin
x1 : if true generate
grfpw0 : grfpw_net generic map (fabtech, pclow, dsu, disas)
port map (
rst ,
clk ,
holdn ,
cpi.flush ,
cpi.exack ,
cpi.a_rs1 ,
cpi.d.pc ,
cpi.d.inst ,
cpi.d.cnt ,
cpi.d.trap ,
cpi.d.annul ,
cpi.d.pv ,
cpi.a.pc ,
cpi.a.inst ,
cpi.a.cnt ,
cpi.a.trap ,
cpi.a.annul ,
cpi.a.pv ,
cpi.e.pc ,
cpi.e.inst ,
cpi.e.cnt ,
cpi.e.trap ,
cpi.e.annul ,
cpi.e.pv ,
cpi.m.pc ,
cpi.m.inst ,
cpi.m.cnt ,
cpi.m.trap ,
cpi.m.annul ,
cpi.m.pv ,
cpi.x.pc ,
cpi.x.inst ,
cpi.x.cnt ,
cpi.x.trap ,
cpi.x.annul ,
cpi.x.pv ,
cpi.lddata ,
cpi.dbg.enable ,
cpi.dbg.write ,
cpi.dbg.fsr ,
cpi.dbg.addr ,
cpi.dbg.data ,
cpo.data ,
cpo.exc ,
cpo.cc ,
cpo.ccv ,
cpo.ldlock ,
cpo.holdn ,
cpo.dbg.data ,
rfi1.rd1addr ,
rfi1.rd2addr ,
rfi1.wraddr ,
rfi1.wrdata ,
rfi1.ren1 ,
rfi1.ren2 ,
rfi1.wren ,
rfi2.rd1addr ,
rfi2.rd2addr ,
rfi2.wraddr ,
rfi2.wrdata ,
rfi2.ren1 ,
rfi2.ren2 ,
rfi2.wren ,
rfo1.data1 ,
rfo1.data2 ,
rfo2.data1 ,
rfo2.data2
);
end generate;
rf1 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16
)
port map (clk, rfi1.wraddr, rfi1.wrdata, rfi1.wren, clk, rfi1.rd1addr,
rfi1.ren1, rfo1.data1, rfi1.rd2addr, rfi1.ren2, rfo1.data2
);
rf2 : regfile_3p_l3 generic map (memtech, 4, 32, 1, 16
)
port map (clk, rfi2.wraddr, rfi2.wrdata, rfi2.wren, clk, rfi2.rd1addr,
rfi2.ren1, rfo2.data1, rfi2.rd2addr, rfi2.ren2, rfo2.data2
);
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clock_divisor is
Port (
clk_in : in STD_LOGIC;
reset : in STD_LOGIC;
clk_out: out STD_LOGIC
);
end clock_divisor;
architecture behavioral of clock_divisor is
signal temporal: STD_LOGIC;
signal counter : integer range 0 to 833333 := 0;
begin
frequency_divider: process (reset, clk_in) begin
if (reset = '1') then
temporal <= '0';
counter <= 0;
elsif rising_edge(clk_in) then
if (counter = 833333) then
temporal <= NOT(temporal);
counter <= 0;
else
counter <= counter + 1;
end if;
end if;
end process;
clk_out <= temporal;
end behavioral; |
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
if L.all'length*4 < recdata'length then
hread(l, recdata(0 to L.all'length*4-1));
else
hread(l, recdata);
end if;
if index < 32 then
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
else
Bank_Load := recaddr(26 downto 25);
Rows_Load := recaddr(24 downto 12);
Cols_Load := recaddr(11 downto 3);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 1 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 1 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 1 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
|
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
if L.all'length*4 < recdata'length then
hread(l, recdata(0 to L.all'length*4-1));
else
hread(l, recdata);
end if;
if index < 32 then
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
else
Bank_Load := recaddr(26 downto 25);
Rows_Load := recaddr(24 downto 12);
Cols_Load := recaddr(11 downto 3);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 1 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 1 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 1 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
|
--*****************************************************************************
--
-- Micron Semiconductor Products, Inc.
--
-- Copyright 1997, Micron Semiconductor Products, Inc.
-- All rights reserved.
--
--*****************************************************************************
-- pragma translate_off
library ieee;
use ieee.std_logic_1164.ALL;
use std.textio.all;
PACKAGE mti_pkg IS
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC;
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER;
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER;
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER;
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR);
END mti_pkg;
PACKAGE BODY mti_pkg IS
-- Convert BIT to STD_LOGIC
FUNCTION To_StdLogic (s : BIT) RETURN STD_LOGIC IS
BEGIN
CASE s IS
WHEN '0' => RETURN ('0');
WHEN '1' => RETURN ('1');
WHEN OTHERS => RETURN ('0');
END CASE;
END;
-- Convert STD_LOGIC to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
IF input = '1' THEN
result := weight;
ELSE
result := 0; -- if unknowns, default to logic 0
END IF;
RETURN result;
END TO_INTEGER;
-- Convert BIT_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : BIT_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Convert STD_LOGIC_VECTOR to INTEGER
FUNCTION TO_INTEGER (input : STD_LOGIC_VECTOR) RETURN INTEGER IS
VARIABLE result : INTEGER := 0;
VARIABLE weight : INTEGER := 1;
BEGIN
FOR i IN input'LOW TO input'HIGH LOOP
IF input(i) = '1' THEN
result := result + weight;
ELSE
result := result + 0; -- if unknowns, default to logic 0
END IF;
weight := weight * 2;
END LOOP;
RETURN result;
END TO_INTEGER;
-- Conver INTEGER to BIT_VECTOR
PROCEDURE TO_BITVECTOR (VARIABLE input : IN INTEGER; VARIABLE output : OUT BIT_VECTOR) IS
VARIABLE work,offset,outputlen,j : INTEGER := 0;
BEGIN
--length of vector
IF output'LENGTH > 32 THEN --'
outputlen := 32;
offset := output'LENGTH - 32; --'
IF input >= 0 THEN
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '0'; --'
END LOOP;
ELSE
FOR i IN offset-1 DOWNTO 0 LOOP
output(output'HIGH - i) := '1'; --'
END LOOP;
END IF;
ELSE
outputlen := output'LENGTH; --'
END IF;
--positive value
IF (input >= 0) THEN
work := input;
j := outputlen - 1;
FOR i IN 1 to 32 LOOP
IF j >= 0 then
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '0'; --'
ELSE
output(output'HIGH-j-offset) := '1'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '0'; --'
END IF;
--negative value
ELSE
work := (-input) - 1;
j := outputlen - 1;
FOR i IN 1 TO 32 LOOP
IF j>= 0 THEN
IF (work MOD 2) = 0 THEN
output(output'HIGH-j-offset) := '1'; --'
ELSE
output(output'HIGH-j-offset) := '0'; --'
END IF;
END IF;
work := work / 2;
j := j - 1;
END LOOP;
IF outputlen = 32 THEN
output(output'HIGH) := '1'; --'
END IF;
END IF;
END TO_BITVECTOR;
END mti_pkg;
-----------------------------------------------------------------------------------------
--
-- File Name: MT48LC16M16A2.VHD
-- Version: 0.0g
-- Date: June 29th, 2000
-- Model: Behavioral
-- Simulator: Model Technology (PC version 5.3 PE)
--
-- Dependencies: None
--
-- Author: Son P. Huynh
-- Email: [email protected]
-- Phone: (208) 368-3825
-- Company: Micron Technology, Inc.
-- Part Number: MT48LC16M16A2 (4Mb x 16 x 4 Banks)
--
-- Description: Micron 256Mb SDRAM
--
-- Limitation: - Doesn't check for 4096-cycle refresh --'
--
-- Note: - Set simulator resolution to "ps" accuracy
--
-- Disclaimer: THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
-- WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
-- IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
-- A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
--
-- Copyright (c) 1998 Micron Semiconductor Products, Inc.
-- All rights researved
--
-- Rev Author Phone Date Changes
-- ---- ---------------------------- ---------- -------------------------------------
-- 0.0g Son Huynh 208-368-3825 06/29/2000 Add Load/Dump memory array
-- Micron Technology Inc. Modify tWR + tRAS timing check
--
-- 0.0f Son Huynh 208-368-3825 07/08/1999 Fix tWR = 1 Clk + 7.5 ns (Auto)
-- Micron Technology Inc. Fix tWR = 15 ns (Manual)
-- Fix tRP (Autoprecharge to AutoRefresh)
--
-- 0.0c Son P. Huynh 208-368-3825 04/08/1999 Fix tWR + tRP in Write with AP
-- Micron Technology Inc. Fix tRC check in Load Mode Register
--
-- 0.0b Son P. Huynh 208-368-3825 01/06/1998 Derive from 64Mb SDRAM model
-- Micron Technology Inc.
--
-----------------------------------------------------------------------------------------
LIBRARY STD;
USE STD.TEXTIO.ALL;
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
LIBRARY WORK;
USE WORK.MTI_PKG.ALL;
use std.textio.all;
library grlib;
use grlib.stdlib.all;
use grlib.stdio.all;
ENTITY mt48lc16m16a2 IS
GENERIC (
-- Timing Parameters for -75 (PC133) and CAS Latency = 2
tAC : TIME := 6.0 ns;
tHZ : TIME := 7.0 ns;
tOH : TIME := 2.7 ns;
tMRD : INTEGER := 2; -- 2 Clk Cycles
tRAS : TIME := 44.0 ns;
tRC : TIME := 66.0 ns;
tRCD : TIME := 20.0 ns;
tRP : TIME := 20.0 ns;
tRRD : TIME := 15.0 ns;
tWRa : TIME := 7.5 ns; -- A2 Version - Auto precharge mode only (1 Clk + 7.5 ns)
tWRp : TIME := 15.0 ns; -- A2 Version - Precharge mode only (15 ns)
tAH : TIME := 0.8 ns;
tAS : TIME := 1.5 ns;
tCH : TIME := 2.5 ns;
tCL : TIME := 2.5 ns;
tCK : TIME := 10.0 ns;
tDH : TIME := 0.8 ns;
tDS : TIME := 1.5 ns;
tCKH : TIME := 0.8 ns;
tCKS : TIME := 1.5 ns;
tCMH : TIME := 0.8 ns;
tCMS : TIME := 1.5 ns;
addr_bits : INTEGER := 13;
data_bits : INTEGER := 16;
col_bits : INTEGER := 9;
index : INTEGER := 0;
fname : string := "ram.srec" -- File to read from
);
PORT (
Dq : INOUT STD_LOGIC_VECTOR (data_bits - 1 DOWNTO 0) := (OTHERS => 'Z');
Addr : IN STD_LOGIC_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
Ba : IN STD_LOGIC_VECTOR := "00";
Clk : IN STD_LOGIC := '0';
Cke : IN STD_LOGIC := '1';
Cs_n : IN STD_LOGIC := '1';
Ras_n : IN STD_LOGIC := '1';
Cas_n : IN STD_LOGIC := '1';
We_n : IN STD_LOGIC := '1';
Dqm : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := "00"
);
END mt48lc16m16a2;
ARCHITECTURE behave OF mt48lc16m16a2 IS
TYPE State IS (ACT, A_REF, BST, LMR, NOP, PRECH, READ, READ_A, WRITE, WRITE_A, LOAD_FILE, DUMP_FILE);
TYPE Array4xI IS ARRAY (3 DOWNTO 0) OF INTEGER;
TYPE Array4xT IS ARRAY (3 DOWNTO 0) OF TIME;
TYPE Array4xB IS ARRAY (3 DOWNTO 0) OF BIT;
TYPE Array4x2BV IS ARRAY (3 DOWNTO 0) OF BIT_VECTOR (1 DOWNTO 0);
TYPE Array4xCBV IS ARRAY (4 DOWNTO 0) OF BIT_VECTOR (Col_bits - 1 DOWNTO 0);
TYPE Array_state IS ARRAY (4 DOWNTO 0) OF State;
SIGNAL Operation : State := NOP;
SIGNAL Mode_reg : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Active_enable, Aref_enable, Burst_term : BIT := '0';
SIGNAL Mode_reg_enable, Prech_enable, Read_enable, Write_enable : BIT := '0';
SIGNAL Burst_length_1, Burst_length_2, Burst_length_4, Burst_length_8 : BIT := '0';
SIGNAL Cas_latency_2, Cas_latency_3 : BIT := '0';
SIGNAL Ras_in, Cas_in, We_in : BIT := '0';
SIGNAL Write_burst_mode : BIT := '0';
SIGNAL RAS_clk, Sys_clk, CkeZ : BIT := '0';
-- Checking internal wires
SIGNAL Pre_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Act_chk : BIT_VECTOR (3 DOWNTO 0) := "0000";
SIGNAL Dq_in_chk, Dq_out_chk : BIT := '0';
SIGNAL Bank_chk : BIT_VECTOR (1 DOWNTO 0) := "00";
SIGNAL Row_chk : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
SIGNAL Col_chk : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- CS# Decode
WITH Cs_n SELECT
Cas_in <= TO_BIT (Cas_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
Ras_in <= TO_BIT (Ras_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
WITH Cs_n SELECT
We_in <= TO_BIT (We_n, '1') WHEN '0',
'1' WHEN '1',
'1' WHEN OTHERS;
-- Commands Decode
Active_enable <= NOT(Ras_in) AND Cas_in AND We_in;
Aref_enable <= NOT(Ras_in) AND NOT(Cas_in) AND We_in;
Burst_term <= Ras_in AND Cas_in AND NOT(We_in);
Mode_reg_enable <= NOT(Ras_in) AND NOT(Cas_in) AND NOT(We_in);
Prech_enable <= NOT(Ras_in) AND Cas_in AND NOT(We_in);
Read_enable <= Ras_in AND NOT(Cas_in) AND We_in;
Write_enable <= Ras_in AND NOT(Cas_in) AND NOT(We_in);
-- Burst Length Decode
Burst_length_1 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND NOT(Mode_reg(0));
Burst_length_2 <= NOT(Mode_reg(2)) AND NOT(Mode_reg(1)) AND Mode_reg(0);
Burst_length_4 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND NOT(Mode_reg(0));
Burst_length_8 <= NOT(Mode_reg(2)) AND Mode_reg(1) AND Mode_reg(0);
-- CAS Latency Decode
Cas_latency_2 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND NOT(Mode_reg(4));
Cas_latency_3 <= NOT(Mode_reg(6)) AND Mode_reg(5) AND Mode_reg(4);
-- Write Burst Mode
Write_burst_mode <= Mode_reg(9);
-- RAS Clock for checking tWR and tRP
PROCESS
variable Clk0, Clk1 : integer := 0;
begin
RAS_clk <= '1';
wait for 0.5 ns;
RAS_clk <= '0';
wait for 0.5 ns;
if Clk0 > 100 or Clk1 > 100 then
wait;
else
if Clk = '1' and Cke = '1' then
Clk0 := 0;
Clk1 := Clk1 + 1;
elsif Clk = '0' and Cke = '1' then
Clk0 := Clk0 + 1;
Clk1 := 0;
end if;
end if;
END PROCESS;
-- System Clock
int_clk : PROCESS (Clk)
begin
IF Clk'LAST_VALUE = '0' AND Clk = '1' THEN --'
CkeZ <= TO_BIT(Cke, '1');
END IF;
Sys_clk <= CkeZ AND TO_BIT(Clk, '0');
END PROCESS;
state_register : PROCESS
-- NOTE: The extra bits in RAM_TYPE is for checking memory access. A logic 1 means
-- the location is in use. This will be checked when doing memory DUMP.
TYPE ram_type IS ARRAY (2**col_bits - 1 DOWNTO 0) OF BIT_VECTOR (data_bits DOWNTO 0);
TYPE ram_pntr IS ACCESS ram_type;
TYPE ram_stor IS ARRAY (2**addr_bits - 1 DOWNTO 0) OF ram_pntr;
VARIABLE Bank0 : ram_stor;
VARIABLE Bank1 : ram_stor;
VARIABLE Bank2 : ram_stor;
VARIABLE Bank3 : ram_stor;
VARIABLE Row_index, Col_index : INTEGER := 0;
VARIABLE Dq_temp : BIT_VECTOR (data_bits DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_addr : Array4xCBV;
VARIABLE Bank_addr : Array4x2BV;
VARIABLE Dqm_reg0, Dqm_reg1 : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Bank, Previous_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col_brst : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Row : BIT_VECTOR (addr_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Col : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
VARIABLE Burst_counter : INTEGER := 0;
VARIABLE Command : Array_state;
VARIABLE Bank_precharge : Array4x2BV;
VARIABLE A10_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Auto_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Read_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE Write_precharge : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_read : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_write : Array4xB := ('0' & '0' & '0' & '0');
VARIABLE RW_interrupt_bank : BIT_VECTOR (1 DOWNTO 0) := "00";
VARIABLE Count_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE Count_precharge : Array4xI := (0 & 0 & 0 & 0);
VARIABLE Data_in_enable, Data_out_enable : BIT := '0';
VARIABLE Pc_b0, Pc_b1, Pc_b2, Pc_b3 : BIT := '0';
VARIABLE Act_b0, Act_b1, Act_b2, Act_b3 : BIT := '0';
-- Timing Check
VARIABLE MRD_chk : INTEGER := 0;
VARIABLE WR_counter : Array4xI := (0 & 0 & 0 & 0);
VARIABLE WR_time : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE WR_chkp : Array4xT := (0 ns & 0 ns & 0 ns & 0 ns);
VARIABLE RC_chk, RRD_chk : TIME := 0 ns;
VARIABLE RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3 : TIME := 0 ns;
VARIABLE RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3 : TIME := 0 ns;
VARIABLE RP_chk0, RP_chk1, RP_chk2, RP_chk3 : TIME := 0 ns;
-- Load and Dumb variables
FILE file_load : TEXT open read_mode is fname; -- Data load
FILE file_dump : TEXT open write_mode is "dumpdata.txt"; -- Data dump
VARIABLE bank_load : bit_vector ( 1 DOWNTO 0);
VARIABLE rows_load : BIT_VECTOR (12 DOWNTO 0);
VARIABLE cols_load : BIT_VECTOR ( 8 DOWNTO 0);
VARIABLE data_load : BIT_VECTOR (15 DOWNTO 0);
VARIABLE i, j : INTEGER;
VARIABLE good_load : BOOLEAN;
VARIABLE l : LINE;
variable load : std_logic := '1';
variable dump : std_logic := '0';
variable ch : character;
variable rectype : bit_vector(3 downto 0);
variable recaddr : bit_vector(31 downto 0);
variable reclen : bit_vector(7 downto 0);
variable recdata : bit_vector(0 to 16*8-1);
-- Initialize empty rows
PROCEDURE Init_mem (Bank : bit_vector (1 DOWNTO 0); Row_index : INTEGER) IS
VARIABLE i, j : INTEGER := 0;
BEGIN
IF Bank = "00" THEN
IF Bank0 (Row_index) = NULL THEN -- Check to see if row empty
Bank0 (Row_index) := NEW ram_type; -- Open new row for access
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP -- Filled row with zeros
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank0 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "01" THEN
IF Bank1 (Row_index) = NULL THEN
Bank1 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank1 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "10" THEN
IF Bank2 (Row_index) = NULL THEN
Bank2 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank2 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
ELSIF Bank = "11" THEN
IF Bank3 (Row_index) = NULL THEN
Bank3 (Row_index) := NEW ram_type;
FOR i IN (2**col_bits - 1) DOWNTO 0 LOOP
FOR j IN (data_bits) DOWNTO 0 LOOP
Bank3 (Row_index) (i) (j) := '0';
END LOOP;
END LOOP;
END IF;
END IF;
END;
-- Burst Counter
PROCEDURE Burst_decode IS
VARIABLE Col_int : INTEGER := 0;
VARIABLE Col_vec, Col_temp : BIT_VECTOR (col_bits - 1 DOWNTO 0) := (OTHERS => '0');
BEGIN
-- Advance Burst Counter
Burst_counter := Burst_counter + 1;
-- Burst Type
IF Mode_reg (3) = '0' THEN
Col_int := TO_INTEGER(Col);
Col_int := Col_int + 1;
TO_BITVECTOR (Col_int, Col_temp);
ELSIF Mode_reg (3) = '1' THEN
TO_BITVECTOR (Burst_counter, Col_vec);
Col_temp (2) := Col_vec (2) XOR Col_brst (2);
Col_temp (1) := Col_vec (1) XOR Col_brst (1);
Col_temp (0) := Col_vec (0) XOR Col_brst (0);
END IF;
-- Burst Length
IF Burst_length_2 = '1' THEN
Col (0) := Col_temp (0);
ELSIF Burst_length_4 = '1' THEN
Col (1 DOWNTO 0) := Col_temp (1 DOWNTO 0);
ELSIF Burst_length_8 = '1' THEN
Col (2 DOWNTO 0) := Col_temp (2 DOWNTO 0);
ELSE
Col := Col_temp;
END IF;
-- Burst Read Single Write
IF Write_burst_mode = '1' AND Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Data counter
IF Burst_length_1 = '1' THEN
IF Burst_counter >= 1 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_2 = '1' THEN
IF Burst_counter >= 2 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_4 = '1' THEN
IF Burst_counter >= 4 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Burst_length_8 = '1' THEN
IF Burst_counter >= 8 THEN
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
ELSIF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
END IF;
END;
BEGIN
WAIT ON Sys_clk, RAS_clk;
IF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '0' THEN --'
-- Internal Command Pipeline
Command(0) := Command(1);
Command(1) := Command(2);
Command(2) := Command(3);
Command(3) := NOP;
Col_addr(0) := Col_addr(1);
Col_addr(1) := Col_addr(2);
Col_addr(2) := Col_addr(3);
Col_addr(3) := (OTHERS => '0');
Bank_addr(0) := Bank_addr(1);
Bank_addr(1) := Bank_addr(2);
Bank_addr(2) := Bank_addr(3);
Bank_addr(3) := "00";
Bank_precharge(0) := Bank_precharge(1);
Bank_precharge(1) := Bank_precharge(2);
Bank_precharge(2) := Bank_precharge(3);
Bank_precharge(3) := "00";
A10_precharge(0) := A10_precharge(1);
A10_precharge(1) := A10_precharge(2);
A10_precharge(2) := A10_precharge(3);
A10_precharge(3) := '0';
-- Operation Decode (Optional for showing current command on posedge clock / debug feature)
IF Active_enable = '1' THEN
Operation <= ACT;
ELSIF Aref_enable = '1' THEN
Operation <= A_REF;
ELSIF Burst_term = '1' THEN
Operation <= BST;
ELSIF Mode_reg_enable = '1' THEN
Operation <= LMR;
ELSIF Prech_enable = '1' THEN
Operation <= PRECH;
ELSIF Read_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= READ;
ELSE
Operation <= READ_A;
END IF;
ELSIF Write_enable = '1' THEN
IF Addr(10) = '0' THEN
Operation <= WRITE;
ELSE
Operation <= WRITE_A;
END IF;
ELSE
Operation <= NOP;
END IF;
-- Dqm pipeline for Read
Dqm_reg0 := Dqm_reg1;
Dqm_reg1 := TO_BITVECTOR(Dqm);
-- Read or Write with Auto Precharge Counter
IF Auto_precharge (0) = '1' THEN
Count_precharge (0) := Count_precharge (0) + 1;
END IF;
IF Auto_precharge (1) = '1' THEN
Count_precharge (1) := Count_precharge (1) + 1;
END IF;
IF Auto_precharge (2) = '1' THEN
Count_precharge (2) := Count_precharge (2) + 1;
END IF;
IF Auto_precharge (3) = '1' THEN
Count_precharge (3) := Count_precharge (3) + 1;
END IF;
-- Auto Precharge Timer for tWR
if (Burst_length_1 = '1' OR Write_burst_mode = '1') then
if (Count_precharge(0) = 1) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 1) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 1) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 1) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_2 = '1') then
if (Count_precharge(0) = 2) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 2) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 2) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 2) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_4 = '1') then
if (Count_precharge(0) = 4) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 4) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 4) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 4) then
Count_time(3) := NOW;
end if;
elsif (Burst_length_8 = '1') then
if (Count_precharge(0) = 8) then
Count_time(0) := NOW;
end if;
if (Count_precharge(1) = 8) then
Count_time(1) := NOW;
end if;
if (Count_precharge(2) = 8) then
Count_time(2) := NOW;
end if;
if (Count_precharge(3) = 8) then
Count_time(3) := NOW;
end if;
end if;
-- tMRD Counter
MRD_chk := MRD_chk + 1;
-- tWR Counter
WR_counter(0) := WR_counter(0) + 1;
WR_counter(1) := WR_counter(1) + 1;
WR_counter(2) := WR_counter(2) + 1;
WR_counter(3) := WR_counter(3) + 1;
-- Auto Refresh
IF Aref_enable = '1' THEN
-- Auto Refresh to Auto Refresh
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Auto Refresh"
SEVERITY WARNING;
-- Precharge to Auto Refresh
ASSERT (NOW - RP_chk0 >= tRP OR NOW - RP_chk1 >= tRP OR NOW - RP_chk2 >= tRP OR NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Auto Refresh"
SEVERITY WARNING;
-- All banks must be idle before refresh
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All banks must be Precharge before Auto Refresh"
SEVERITY WARNING;
END IF;
-- Record current tRC time
RC_chk := NOW;
END IF;
-- Load Mode Register
IF Mode_reg_enable = '1' THEN
Mode_reg <= TO_BITVECTOR (Addr);
IF (Pc_b3 ='0' OR Pc_b2 = '0' OR Pc_b1 ='0' OR Pc_b0 = '0') THEN
ASSERT (FALSE)
REPORT "All bank must be Precharge before Load Mode Register"
SEVERITY WARNING;
END IF;
-- REF to LMR
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Load Mode Register"
SEVERITY WARNING;
-- LMR to LMR
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Load Mode Register"
SEVERITY WARNING;
-- Record current tMRD time
MRD_chk := 0;
END IF;
-- Active Block (latch Bank and Row Address)
IF Active_enable = '1' THEN
IF Ba = "00" AND Pc_b0 = '1' THEN
Act_b0 := '1';
Pc_b0 := '0';
B0_row_addr := TO_BITVECTOR (Addr);
RCD_chk0 := NOW;
RAS_chk0 := NOW;
-- Precharge to Active Bank 0
ASSERT (NOW - RP_chk0 >= tRP)
REPORT "tRP violation during Activate Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '1' THEN
Act_b1 := '1';
Pc_b1 := '0';
B1_row_addr := TO_BITVECTOR (Addr);
RCD_chk1 := NOW;
RAS_chk1 := NOW;
-- Precharge to Active Bank 1
ASSERT (NOW - RP_chk1 >= tRP)
REPORT "tRP violation during Activate Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '1' THEN
Act_b2 := '1';
Pc_b2 := '0';
B2_row_addr := TO_BITVECTOR (Addr);
RCD_chk2 := NOW;
RAS_chk2 := NOW;
-- Precharge to Active Bank 2
ASSERT (NOW - RP_chk2 >= tRP)
REPORT "tRP violation during Activate Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '1' THEN
Act_b3 := '1';
Pc_b3 := '0';
B3_row_addr := TO_BITVECTOR (Addr);
RCD_chk3 := NOW;
RAS_chk3 := NOW;
-- Precharge to Active Bank 3
ASSERT (NOW - RP_chk3 >= tRP)
REPORT "tRP violation during Activate Bank 3"
SEVERITY WARNING;
ELSIF Ba = "00" AND Pc_b0 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 0 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "01" AND Pc_b1 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 1 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "10" AND Pc_b2 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 2 is not Precharged"
SEVERITY WARNING;
ELSIF Ba = "11" AND Pc_b3 = '0' THEN
ASSERT (FALSE)
REPORT "Bank 3 is not Precharged"
SEVERITY WARNING;
END IF;
-- Active Bank A to Active Bank B
IF ((Previous_bank /= TO_BITVECTOR (Ba)) AND (NOW - RRD_chk < tRRD)) THEN
ASSERT (FALSE)
REPORT "tRRD violation during Activate"
SEVERITY WARNING;
END IF;
-- LMR to ACT
ASSERT (MRD_chk >= tMRD)
REPORT "tMRD violation during Activate"
SEVERITY WARNING;
-- AutoRefresh to Activate
ASSERT (NOW - RC_chk >= tRC)
REPORT "tRC violation during Activate"
SEVERITY WARNING;
-- Record variable for checking violation
RRD_chk := NOW;
Previous_bank := TO_BITVECTOR (Ba);
END IF;
-- Precharge Block
IF Prech_enable = '1' THEN
IF Addr(10) = '1' THEN
Pc_b0 := '1';
Pc_b1 := '1';
Pc_b2 := '1';
Pc_b3 := '1';
Act_b0 := '0';
Act_b1 := '0';
Act_b2 := '0';
Act_b3 := '0';
RP_chk0 := NOW;
RP_chk1 := NOW;
RP_chk2 := NOW;
RP_chk3 := NOW;
-- Activate to Precharge all banks
ASSERT ((NOW - RAS_chk0 >= tRAS) OR (NOW - RAS_chk1 >= tRAS))
REPORT "tRAS violation during Precharge all banks"
SEVERITY WARNING;
-- tWR violation check for Write
IF ((NOW - WR_chkp(0) < tWRp) OR (NOW - WR_chkp(1) < tWRp) OR
(NOW - WR_chkp(2) < tWRp) OR (NOW - WR_chkp(3) < tWRp)) THEN
ASSERT (FALSE)
REPORT "tWR violation during Precharge ALL banks"
SEVERITY WARNING;
END IF;
ELSIF Addr(10) = '0' THEN
IF Ba = "00" THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
-- Activate to Precharge bank 0
ASSERT (NOW - RAS_chk0 >= tRAS)
REPORT "tRAS violation during Precharge bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
-- Activate to Precharge bank 1
ASSERT (NOW - RAS_chk1 >= tRAS)
REPORT "tRAS violation during Precharge bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
-- Activate to Precharge bank 2
ASSERT (NOW - RAS_chk2 >= tRAS)
REPORT "tRAS violation during Precharge bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
-- Activate to Precharge bank 3
ASSERT (NOW - RAS_chk3 >= tRAS)
REPORT "tRAS violation during Precharge bank 3"
SEVERITY WARNING;
END IF;
-- tWR violation check for Write
ASSERT (NOW - WR_chkp(TO_INTEGER(Ba)) >= tWRp)
REPORT "tWR violation during Precharge"
SEVERITY WARNING;
END IF;
-- Terminate a Write Immediately (if same bank or all banks)
IF (Data_in_enable = '1' AND (Bank = TO_BITVECTOR(Ba) OR Addr(10) = '1')) THEN
Data_in_enable := '0';
END IF;
-- Precharge Command Pipeline for READ
IF CAS_latency_3 = '1' THEN
Command(2) := PRECH;
Bank_precharge(2) := TO_BITVECTOR (Ba);
A10_precharge(2) := TO_BIT(Addr(10));
ELSIF CAS_latency_2 = '1' THEN
Command(1) := PRECH;
Bank_precharge(1) := TO_BITVECTOR (Ba);
A10_precharge(1) := TO_BIT(Addr(10));
END IF;
END IF;
-- Burst Terminate
IF Burst_term = '1' THEN
-- Terminate a Write immediately
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Terminate a Read depend on CAS Latency
IF CAS_latency_3 = '1' THEN
Command(2) := BST;
ELSIF CAS_latency_2 = '1' THEN
Command(1) := BST;
END IF;
END IF;
-- Read, Write, Column Latch
IF Read_enable = '1' OR Write_enable = '1' THEN
-- Check to see if bank is open (ACT) for Read or Write
IF ((Ba="00" AND Pc_b0='1') OR (Ba="01" AND Pc_b1='1') OR (Ba="10" AND Pc_b2='1') OR (Ba="11" AND Pc_b3='1')) THEN
ASSERT (FALSE)
REPORT "Cannot Read or Write - Bank is not Activated"
SEVERITY WARNING;
END IF;
-- Activate to Read or Write
IF Ba = "00" THEN
ASSERT (NOW - RCD_chk0 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 0"
SEVERITY WARNING;
ELSIF Ba = "01" THEN
ASSERT (NOW - RCD_chk1 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 1"
SEVERITY WARNING;
ELSIF Ba = "10" THEN
ASSERT (NOW - RCD_chk2 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 2"
SEVERITY WARNING;
ELSIF Ba = "11" THEN
ASSERT (NOW - RCD_chk3 >= tRCD)
REPORT "tRCD violation during Read or Write to Bank 3"
SEVERITY WARNING;
END IF;
-- Read Command
IF Read_enable = '1' THEN
-- CAS Latency Pipeline
IF Cas_latency_3 = '1' THEN
IF Addr(10) = '1' THEN
Command(2) := READ_A;
ELSE
Command(2) := READ;
END IF;
Col_addr (2) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (2) := TO_BITVECTOR (Ba);
ELSIF Cas_latency_2 = '1' THEN
IF Addr(10) = '1' THEN
Command(1) := READ_A;
ELSE
Command(1) := READ;
END IF;
Col_addr (1) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (1) := TO_BITVECTOR (Ba);
END IF;
-- Read intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write Command
ELSIF Write_enable = '1' THEN
IF Addr(10) = '1' THEN
Command(0) := WRITE_A;
ELSE
Command(0) := WRITE;
END IF;
Col_addr (0) := TO_BITVECTOR (Addr(col_bits - 1 DOWNTO 0));
Bank_addr (0) := TO_BITVECTOR (Ba);
-- Write intterupt a Write (terminate Write immediately)
IF Data_in_enable = '1' THEN
Data_in_enable := '0';
END IF;
-- Write interrupt a Read (terminate Read immediately)
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
-- Interrupt a Write with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Write_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_write(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Interrupt a Read with Auto Precharge
IF Auto_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' AND Read_precharge(TO_INTEGER(RW_Interrupt_Bank)) = '1' THEN
RW_interrupt_read(TO_INTEGER(RW_Interrupt_Bank)) := '1';
END IF;
-- Read or Write with Auto Precharge
IF Addr(10) = '1' THEN
Auto_precharge (TO_INTEGER(Ba)) := '1';
Count_precharge (TO_INTEGER(Ba)) := 0;
RW_Interrupt_Bank := TO_BitVector(Ba);
IF Read_enable = '1' THEN
Read_precharge (TO_INTEGER(Ba)) := '1';
ELSIF Write_enable = '1' THEN
Write_precharge (TO_INTEGER(Ba)) := '1';
END IF;
END IF;
END IF;
-- Read with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. BL/2 cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Read_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(0) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8))) OR
(RW_interrupt_read(0) = '1')) THEN
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
Auto_precharge(0) := '0';
Read_precharge(0) := '0';
RW_interrupt_read(0) := '0';
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Read_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(1) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8))) OR
(RW_interrupt_read(1) = '1')) THEN
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
Auto_precharge(1) := '0';
Read_precharge(1) := '0';
RW_interrupt_read(1) := '0';
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Read_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(2) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8))) OR
(RW_interrupt_read(2) = '1')) THEN
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
Auto_precharge(2) := '0';
Read_precharge(2) := '0';
RW_interrupt_read(2) := '0';
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Read_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
((Burst_length_1 = '1' AND Count_precharge(3) >= 1) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8))) OR
(RW_interrupt_read(3) = '1')) THEN
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
Auto_precharge(3) := '0';
Read_precharge(3) := '0';
RW_interrupt_read(3) := '0';
END IF;
END IF;
-- Internal Precharge or Bst
IF Command(0) = PRECH THEN -- PRECH terminate a read if same bank or all banks
IF Bank_precharge(0) = Bank OR A10_precharge(0) = '1' THEN
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
ELSIF Command(0) = BST THEN -- BST terminate a read regardless of bank
IF Data_out_enable = '1' THEN
Data_out_enable := '0';
END IF;
END IF;
IF Data_out_enable = '0' THEN
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tOH;
END IF;
-- Detect Read or Write Command
IF Command(0) = READ OR Command(0) = READ_A THEN
Bank := Bank_addr (0);
Col := Col_addr (0);
Col_brst := Col_addr (0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '0';
Data_out_enable := '1';
ELSIF Command(0) = WRITE OR Command(0) = WRITE_A THEN
Bank := Bank_addr(0);
Col := Col_addr(0);
Col_brst := Col_addr(0);
IF Bank_addr (0) = "00" THEN
Row := B0_row_addr;
ELSIF Bank_addr (0) = "01" THEN
Row := B1_row_addr;
ELSIF Bank_addr (0) = "10" THEN
Row := B2_row_addr;
ELSE
Row := B3_row_addr;
END IF;
Burst_counter := 0;
Data_in_enable := '1';
Data_out_enable := '0';
END IF;
-- DQ (Driver / Receiver)
Row_index := TO_INTEGER (Row);
Col_index := TO_INTEGER (Col);
IF Data_in_enable = '1' THEN
IF Dqm /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank0 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank1 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank2 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm = "01" THEN
Dq_temp (15 DOWNTO 8) := TO_BITVECTOR (Dq (15 DOWNTO 8));
ELSIF Dqm = "10" THEN
Dq_temp (7 DOWNTO 0) := TO_BITVECTOR (Dq (7 DOWNTO 0));
ELSE
Dq_temp (15 DOWNTO 0) := TO_BITVECTOR (Dq (15 DOWNTO 0));
END IF;
Bank3 (Row_index) (Col_index) := ('1' & Dq_temp(data_bits - 1 DOWNTO 0));
END IF;
WR_chkp(TO_INTEGER(Bank)) := NOW;
WR_counter(TO_INTEGER(Bank)) := 0;
END IF;
Burst_decode;
ELSIF Data_out_enable = '1' THEN
IF Dqm_reg0 /= "11" THEN
Init_mem (Bank, Row_index);
IF Bank = "00" THEN
Dq_temp := Bank0 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "01" THEN
Dq_temp := Bank1 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "10" THEN
Dq_temp := Bank2 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
ELSIF Bank = "11" THEN
Dq_temp := Bank3 (Row_index) (Col_index);
IF Dqm_reg0 = "00" THEN
Dq (15 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 0)) AFTER tAC;
ELSIF Dqm_reg0 = "01" THEN
Dq (15 DOWNTO 8) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (15 DOWNTO 8)) AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
ELSIF Dqm_reg0 = "10" THEN
Dq (15 DOWNTO 8) <= TRANSPORT (OTHERS => 'Z') AFTER tAC;
Dq (7 DOWNTO 0) <= TRANSPORT TO_STDLOGICVECTOR (Dq_temp (7 DOWNTO 0)) AFTER tAC;
END IF;
END IF;
ELSE
Dq <= TRANSPORT (OTHERS => 'Z') AFTER tHZ;
END IF;
Burst_decode;
END IF;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '1' AND Dump = '0' THEN --'
Operation <= LOAD_FILE;
load := '0';
-- ASSERT (FALSE) REPORT "Reading memory array from file. This operation may take several minutes. Please wait..."
-- SEVERITY NOTE;
WHILE NOT endfile(file_load) LOOP
readline(file_load, l);
read(l, ch);
if (ch /= 'S') or (ch /= 's') then
hread(l, rectype);
hread(l, reclen);
recaddr := (others => '0');
case rectype is
when "0001" =>
hread(l, recaddr(15 downto 0));
when "0010" =>
hread(l, recaddr(23 downto 0));
when "0011" =>
hread(l, recaddr);
recaddr(31 downto 24) := (others => '0');
when others => next;
end case;
if L.all'length*4 < recdata'length then
hread(l, recdata(0 to L.all'length*4-1));
else
hread(l, recdata);
end if;
if index < 32 then
Bank_Load := recaddr(25 downto 24);
Rows_Load := recaddr(23 downto 11);
Cols_Load := recaddr(10 downto 2);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 3 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 3 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 3 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 3 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*32+index to i*32+index+15));
end loop;
END IF;
else
Bank_Load := recaddr(26 downto 25);
Rows_Load := recaddr(24 downto 12);
Cols_Load := recaddr(11 downto 3);
Init_Mem (Bank_Load, To_Integer(Rows_Load));
IF Bank_Load = "00" THEN
for i in 0 to 1 loop
Bank0 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "01" THEN
for i in 0 to 1 loop
Bank1 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "10" THEN
for i in 0 to 1 loop
Bank2 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
ELSIF Bank_Load = "11" THEN
for i in 0 to 1 loop
Bank3 (To_Integer(Rows_Load)) (To_Integer(Cols_Load)+i) := ('1' & recdata(i*64+index-32 to i*64+index-32+15));
end loop;
END IF;
END IF;
END IF;
END LOOP;
ELSIF Sys_clk'event AND Sys_clk = '1' AND Load = '0' AND Dump = '1' THEN --'
Operation <= DUMP_FILE;
ASSERT (FALSE) REPORT "Writing memory array to file. This operation may take several minutes. Please wait..."
SEVERITY NOTE;
WRITE (l, string'("# Micron Technology, Inc. (FILE DUMP / MEMORY DUMP)")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# BA ROWS COLS DQ")); --'
WRITELINE (file_dump, l);
WRITE (l, string'("# -- ------------- --------- ----------------")); --'
WRITELINE (file_dump, l);
-- Dumping Bank 0
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank0 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank0 (i) (j) (data_bits) = '0';
WRITE (l, string'("00"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank0 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 1
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank1 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank1 (i) (j) (data_bits) = '0';
WRITE (l, string'("01"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank1 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 2
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank2 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank2 (i) (j) (data_bits) = '0';
WRITE (l, string'("10"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank2 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
-- Dumping Bank 3
FOR i IN 0 TO 2**addr_bits -1 LOOP
-- Check if ROW is NULL
IF Bank3 (i) /= NULL THEN
For j IN 0 TO 2**col_bits - 1 LOOP
-- Check if COL is NULL
NEXT WHEN Bank3 (i) (j) (data_bits) = '0';
WRITE (l, string'("11"), right, 4); --'
WRITE (l, To_BitVector(Conv_Std_Logic_Vector(i, addr_bits)), right, addr_bits+1);
WRITE (l, To_BitVector(Conv_std_Logic_Vector(j, col_bits)), right, col_bits+1);
WRITE (l, Bank3 (i) (j) (data_bits -1 DOWNTO 0), right, data_bits+1);
WRITELINE (file_dump, l);
END LOOP;
END IF;
END LOOP;
END IF;
-- Write with AutoPrecharge Calculation
-- The device start internal precharge when:
-- 1. tWR cycles after command
-- and 2. Meet tRAS requirement
-- or 3. Interrupt by a Read or Write (with or without Auto Precharge)
IF ((Auto_precharge(0) = '1') AND (Write_precharge(0) = '1')) THEN
IF (((NOW - RAS_chk0 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(0) >= 1 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(0) >= 2 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(0) >= 4 AND NOW - Count_time(0) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(0) >= 8 AND NOW - Count_time(0) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(0) >= tWRa)) THEN
Auto_precharge(0) := '0';
Write_precharge(0) := '0';
RW_interrupt_write(0) := '0';
Pc_b0 := '1';
Act_b0 := '0';
RP_chk0 := NOW;
ASSERT FALSE REPORT "Start Internal Precharge Bank 0" SEVERITY NOTE;
END IF;
END IF;
IF ((Auto_precharge(1) = '1') AND (Write_precharge(1) = '1')) THEN
IF (((NOW - RAS_chk1 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(1) >= 1 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(1) >= 2 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(1) >= 4 AND NOW - Count_time(1) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(1) >= 8 AND NOW - Count_time(1) >= tWRa))) OR
(RW_interrupt_write(1) = '1' AND WR_counter(1) >= 1 AND NOW - WR_time(1) >= tWRa)) THEN
Auto_precharge(1) := '0';
Write_precharge(1) := '0';
RW_interrupt_write(1) := '0';
Pc_b1 := '1';
Act_b1 := '0';
RP_chk1 := NOW;
END IF;
END IF;
IF ((Auto_precharge(2) = '1') AND (Write_precharge(2) = '1')) THEN
IF (((NOW - RAS_chk2 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(2) >= 1 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(2) >= 2 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(2) >= 4 AND NOW - Count_time(2) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(2) >= 8 AND NOW - Count_time(2) >= tWRa))) OR
(RW_interrupt_write(2) = '1' AND WR_counter(2) >= 1 AND NOW - WR_time(2) >= tWRa)) THEN
Auto_precharge(2) := '0';
Write_precharge(2) := '0';
RW_interrupt_write(2) := '0';
Pc_b2 := '1';
Act_b2 := '0';
RP_chk2 := NOW;
END IF;
END IF;
IF ((Auto_precharge(3) = '1') AND (Write_precharge(3) = '1')) THEN
IF (((NOW - RAS_chk3 >= tRAS) AND
(((Burst_length_1 = '1' OR Write_burst_mode = '1' ) AND Count_precharge(3) >= 1 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_2 = '1' AND Count_precharge(3) >= 2 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_4 = '1' AND Count_precharge(3) >= 4 AND NOW - Count_time(3) >= tWRa) OR
(Burst_length_8 = '1' AND Count_precharge(3) >= 8 AND NOW - Count_time(3) >= tWRa))) OR
(RW_interrupt_write(0) = '1' AND WR_counter(0) >= 1 AND NOW - WR_time(3) >= tWRa)) THEN
Auto_precharge(3) := '0';
Write_precharge(3) := '0';
RW_interrupt_write(3) := '0';
Pc_b3 := '1';
Act_b3 := '0';
RP_chk3 := NOW;
END IF;
END IF;
-- Checking internal wires (Optional for debug purpose)
Pre_chk (0) <= Pc_b0;
Pre_chk (1) <= Pc_b1;
Pre_chk (2) <= Pc_b2;
Pre_chk (3) <= Pc_b3;
Act_chk (0) <= Act_b0;
Act_chk (1) <= Act_b1;
Act_chk (2) <= Act_b2;
Act_chk (3) <= Act_b3;
Dq_in_chk <= Data_in_enable;
Dq_out_chk <= Data_out_enable;
Bank_chk <= Bank;
Row_chk <= Row;
Col_chk <= Col;
END PROCESS;
-- Clock timing checks
-- Clock_check : PROCESS
-- VARIABLE Clk_low, Clk_high : TIME := 0 ns;
-- BEGIN
-- WAIT ON Clk;
-- IF (Clk = '1' AND NOW >= 10 ns) THEN
-- ASSERT (NOW - Clk_low >= tCL)
-- REPORT "tCL violation"
-- SEVERITY WARNING;
-- ASSERT (NOW - Clk_high >= tCK)
-- REPORT "tCK violation"
-- SEVERITY WARNING;
-- Clk_high := NOW;
-- ELSIF (Clk = '0' AND NOW /= 0 ns) THEN
-- ASSERT (NOW - Clk_high >= tCH)
-- REPORT "tCH violation"
-- SEVERITY WARNING;
-- Clk_low := NOW;
-- END IF;
-- END PROCESS;
-- Setup timing checks
Setup_check : PROCESS
BEGIN
wait;
WAIT ON Clk;
IF Clk = '1' THEN
ASSERT(Cke'LAST_EVENT >= tCKS) --'
REPORT "CKE Setup time violation -- tCKS"
SEVERITY WARNING;
ASSERT(Cs_n'LAST_EVENT >= tCMS) --'
REPORT "CS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT >= tCMS) --'
REPORT "CAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT >= tCMS) --'
REPORT "RAS# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT >= tCMS) --'
REPORT "WE# Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT >= tCMS) --'
REPORT "Dqm Setup time violation -- tCMS"
SEVERITY WARNING;
ASSERT(Addr'LAST_EVENT >= tAS) --'
REPORT "ADDR Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT >= tAS) --'
REPORT "BA Setup time violation -- tAS"
SEVERITY WARNING;
ASSERT(Dq'LAST_EVENT >= tDS) --'
REPORT "Dq Setup time violation -- tDS"
SEVERITY WARNING;
END IF;
END PROCESS;
-- Hold timing checks
Hold_check : PROCESS
BEGIN
wait;
WAIT ON Clk'DELAYED (tCKH), Clk'DELAYED (tCMH), Clk'DELAYED (tAH), Clk'DELAYED (tDH);
IF Clk'DELAYED (tCKH) = '1' THEN --'
ASSERT(Cke'LAST_EVENT > tCKH) --'
REPORT "CKE Hold time violation -- tCKH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tCMH) = '1' THEN --'
ASSERT(Cs_n'LAST_EVENT > tCMH) --'
REPORT "CS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Cas_n'LAST_EVENT > tCMH) --'
REPORT "CAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Ras_n'LAST_EVENT > tCMH) --'
REPORT "RAS# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(We_n'LAST_EVENT > tCMH) --'
REPORT "WE# Hold time violation -- tCMH"
SEVERITY WARNING;
ASSERT(Dqm'LAST_EVENT > tCMH) --'
REPORT "Dqm Hold time violation -- tCMH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tAH) = '1' THEN --'
ASSERT(Addr'LAST_EVENT > tAH) --'
REPORT "ADDR Hold time violation -- tAH"
SEVERITY WARNING;
ASSERT(Ba'LAST_EVENT > tAH) --'
REPORT "BA Hold time violation -- tAH"
SEVERITY WARNING;
END IF;
IF Clk'DELAYED (tDH) = '1' THEN --'
ASSERT(Dq'LAST_EVENT > tDH) --'
REPORT "Dq Hold time violation -- tDH"
SEVERITY WARNING;
END IF;
END PROCESS;
END behave;
-- pragma translate_on
|
library IEEE;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity memory is
port(
address, writeData : in std_logic_vector(31 downto 0);
clk, memRead, memWrite : in std_logic;
memData : out std_logic_vector(31 downto 0)
);
end memory;
architecture behav of memory is
type ram is array (65536 downto 0) of std_logic_vector(7 downto 0);
signal inByte0, inByte1, inByte2, inByte3, outByte0, outByte1, outByte2, outByte3 : std_logic_vector(7 downto 0);
signal writeDataBuf : std_logic_vector(31 downto 0);
signal mem : ram;
signal addr : integer range 0 to 65536;
begin
inByte0(0) <= writeData(0);
inByte0(1) <= writeData(1);
inByte0(2) <= writeData(2);
inByte0(3) <= writeData(3);
inByte0(4) <= writeData(4);
inByte0(5) <= writeData(5);
inByte0(6) <= writeData(6);
inByte0(7) <= writeData(7);
inByte1(0) <= writeData(8);
inByte1(1) <= writeData(9);
inByte1(2) <= writeData(10);
inByte1(3) <= writeData(11);
inByte1(4) <= writeData(12);
inByte1(5) <= writeData(13);
inByte1(6) <= writeData(14);
inByte1(7) <= writeData(15);
inByte2(0) <= writeData(16);
inByte2(1) <= writeData(17);
inByte2(2) <= writeData(18);
inByte2(3) <= writeData(19);
inByte2(4) <= writeData(20);
inByte2(5) <= writeData(21);
inByte2(6) <= writeData(22);
inByte2(7) <= writeData(23);
inByte3(0) <= writeData(24);
inByte3(1) <= writeData(25);
inByte3(2) <= writeData(26);
inByte3(3) <= writeData(27);
inByte3(4) <= writeData(28);
inByte3(5) <= writeData(29);
inByte3(6) <= writeData(30);
inByte3(7) <= writeData(31);
outByte0 <= mem(addr);
outByte1 <= mem(addr+1);
outByte2 <= mem(addr+2);
outByte3 <= mem(addr+3);
writeDataBuf(0) <= outByte0(0);
writeDataBuf(1) <= outByte0(1);
writeDataBuf(2) <= outByte0(2);
writeDataBuf(3) <= outByte0(3);
writeDataBuf(4) <= outByte0(4);
writeDataBuf(5) <= outByte0(5);
writeDataBuf(6) <= outByte0(6);
writeDataBuf(7) <= outByte0(7);
writeDataBuf(8) <= outByte1(0);
writeDataBuf(9) <= outByte1(1);
writeDataBuf(10) <= outByte1(2);
writeDataBuf(11) <= outByte1(3);
writeDataBuf(12) <= outByte1(4);
writeDataBuf(13) <= outByte1(5);
writeDataBuf(14) <= outByte1(6);
writeDataBuf(15) <= outByte1(7);
writeDataBuf(16) <= outByte2(0);
writeDataBuf(17) <= outByte2(1);
writeDataBuf(18) <= outByte2(2);
writeDataBuf(19) <= outByte2(3);
writeDataBuf(20) <= outByte2(4);
writeDataBuf(21) <= outByte2(5);
writeDataBuf(22) <= outByte2(6);
writeDataBuf(23) <= outByte2(7);
writeDataBuf(24) <= outByte3(0);
writeDataBuf(25) <= outByte3(1);
writeDataBuf(26) <= outByte3(2);
writeDataBuf(27) <= outByte3(3);
writeDataBuf(28) <= outByte3(4);
writeDataBuf(29) <= outByte3(5);
writeDataBuf(30) <= outByte3(6);
writeDataBuf(31) <= outByte3(7);
process(address, writeData, clk, memRead, memWrite)
begin
addr <= to_integer(unsigned(address));
if rising_edge(clk) then
if (memWrite='1') and (memRead='0') then
mem(addr)<=inByte0;
mem(addr+1)<=inByte1;
mem(addr+2)<=inByte2;
mem(addr+3)<=inByte3;
end if;
end if;
if falling_edge(clk) then
if (memWrite='0') and (memRead='1') then
memData<=writeDataBuf;
end if;
end if;
end process;
end behav;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: grgpreg
-- File: grgpreg.vhd
-- Author: Kristoffer Glembo - Aeroflex Gaisler
-- Description: General purpose register
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
library gaisler;
use gaisler.misc.all;
--pragma translate_off
use std.textio.all;
--pragma translate_on
entity grgpreg is
generic (
pindex : integer := 0;
paddr : integer := 0;
pmask : integer := 16#fff#;
nbits : integer range 1 to 64 := 16;
rstval : integer := 0;
rstval2 : integer := 0;
extrst : integer := 0
);
port (
rst : in std_ulogic;
clk : in std_ulogic;
apbi : in apb_slv_in_type;
apbo : out apb_slv_out_type;
gprego : out std_logic_vector(nbits-1 downto 0);
resval : in std_logic_vector(nbits-1 downto 0) := (others => '0')
);
end;
architecture rtl of grgpreg is
constant REVISION : integer := 0;
constant pconfig : apb_config_type := (
0 => ahb_device_reg (VENDOR_GAISLER, GAISLER_GPREG, 0, REVISION, 0),
1 => apb_iobar(paddr, pmask));
type registers is record
reg : std_logic_vector(nbits-1 downto 0);
end record;
signal r, rin : registers;
begin
comb : process(rst, r, apbi, resval)
variable readdata : std_logic_vector(31 downto 0);
variable v : registers;
begin
v := r;
-- read register
readdata := (others => '0');
case apbi.paddr(4 downto 2) is
when "000" =>
if nbits > 32 then
readdata := r.reg(31 downto 0);
else
readdata(nbits-1 downto 0) := r.reg;
end if;
when "001" =>
if nbits > 32 then
readdata(nbits-33 downto 0) := r.reg(nbits-1 downto 32);
end if;
when others =>
end case;
-- write registers
if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
case apbi.paddr(4 downto 2) is
when "000" =>
if nbits > 32 then
v.reg(31 downto 0) := apbi.pwdata;
else
v.reg := apbi.pwdata(nbits-1 downto 0);
end if;
when "001" =>
if nbits > 32 then
v.reg(nbits-1 downto 32) := apbi.pwdata(nbits-33 downto 0);
end if;
when others =>
end case;
end if;
if rst = '0' then
if extrst = 0 then
v.reg := conv_std_logic_vector(rstval, nbits);
if nbits > 32 then
v.reg(nbits-1 downto 32) := conv_std_logic_vector(rstval2, nbits-32);
end if;
else
v.reg := resval;
end if;
end if;
rin <= v;
apbo.prdata <= readdata; -- drive apb read bus
end process;
gprego <= r.reg;
apbo.pirq <= (others => '0');
apbo.pindex <= pindex;
apbo.pconfig <= pconfig;
-- registers
regs : process(clk)
begin
if rising_edge(clk) then r <= rin; end if;
end process;
-- boot message
-- pragma translate_off
bootmsg : report_version
generic map ("grgpreg" & tost(pindex) &
": " & tost(nbits) & "-bit GPREG Unit rev " & tost(REVISION));
-- pragma translate_on
end;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY segregfile IS
PORT(
selsreg : IN std_logic_vector (1 DOWNTO 0);
sibus : IN std_logic_vector (15 DOWNTO 0);
wrs : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
sdbus : OUT std_logic_vector (15 DOWNTO 0);
dimux : IN std_logic_vector (2 DOWNTO 0);
es_s : OUT std_logic_vector (15 DOWNTO 0);
cs_s : OUT std_logic_vector (15 DOWNTO 0);
ss_s : OUT std_logic_vector (15 DOWNTO 0);
ds_s : OUT std_logic_vector (15 DOWNTO 0)
);
END segregfile ;
architecture rtl of segregfile is
signal esreg_s : std_logic_vector(15 downto 0);
signal csreg_s : std_logic_vector(15 downto 0);
signal ssreg_s : std_logic_vector(15 downto 0);
signal dsreg_s : std_logic_vector(15 downto 0);
signal sdbus_s : std_logic_vector (15 downto 0); -- internal sdbus
signal dimux_s : std_logic_vector (2 downto 0); -- replaced dimux
begin
----------------------------------------------------------------------------
-- 4 registers of 16 bits each
----------------------------------------------------------------------------
process (clk,reset)
begin
if reset='1' then
esreg_s <= RESET_ES_C;
csreg_s <= RESET_CS_C; -- Only CS set after reset
ssreg_s <= RESET_SS_C;
dsreg_s <= RESET_DS_C;
elsif rising_edge(clk) then
if (wrs='1') then
case selsreg is
when "00" => esreg_s <= sibus;
when "01" => csreg_s <= sibus;
when "10" => ssreg_s <= sibus;
when others => dsreg_s <= sibus;
end case;
end if;
end if;
end process;
dimux_s <= dimux;
process (dimux_s,esreg_s,csreg_s,ssreg_s,dsreg_s)
begin
case dimux_s is -- Only 2 bits required
when "100" => sdbus_s <= esreg_s;
when "101" => sdbus_s <= csreg_s;
when "110" => sdbus_s <= ssreg_s;
when others => sdbus_s <= dsreg_s;
end case;
end process;
sdbus <= sdbus_s; -- Connect to entity
es_s <= esreg_s;
cs_s <= csreg_s;
ss_s <= ssreg_s;
ds_s <= dsreg_s;
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY segregfile IS
PORT(
selsreg : IN std_logic_vector (1 DOWNTO 0);
sibus : IN std_logic_vector (15 DOWNTO 0);
wrs : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
sdbus : OUT std_logic_vector (15 DOWNTO 0);
dimux : IN std_logic_vector (2 DOWNTO 0);
es_s : OUT std_logic_vector (15 DOWNTO 0);
cs_s : OUT std_logic_vector (15 DOWNTO 0);
ss_s : OUT std_logic_vector (15 DOWNTO 0);
ds_s : OUT std_logic_vector (15 DOWNTO 0)
);
END segregfile ;
architecture rtl of segregfile is
signal esreg_s : std_logic_vector(15 downto 0);
signal csreg_s : std_logic_vector(15 downto 0);
signal ssreg_s : std_logic_vector(15 downto 0);
signal dsreg_s : std_logic_vector(15 downto 0);
signal sdbus_s : std_logic_vector (15 downto 0); -- internal sdbus
signal dimux_s : std_logic_vector (2 downto 0); -- replaced dimux
begin
----------------------------------------------------------------------------
-- 4 registers of 16 bits each
----------------------------------------------------------------------------
process (clk,reset)
begin
if reset='1' then
esreg_s <= RESET_ES_C;
csreg_s <= RESET_CS_C; -- Only CS set after reset
ssreg_s <= RESET_SS_C;
dsreg_s <= RESET_DS_C;
elsif rising_edge(clk) then
if (wrs='1') then
case selsreg is
when "00" => esreg_s <= sibus;
when "01" => csreg_s <= sibus;
when "10" => ssreg_s <= sibus;
when others => dsreg_s <= sibus;
end case;
end if;
end if;
end process;
dimux_s <= dimux;
process (dimux_s,esreg_s,csreg_s,ssreg_s,dsreg_s)
begin
case dimux_s is -- Only 2 bits required
when "100" => sdbus_s <= esreg_s;
when "101" => sdbus_s <= csreg_s;
when "110" => sdbus_s <= ssreg_s;
when others => sdbus_s <= dsreg_s;
end case;
end process;
sdbus <= sdbus_s; -- Connect to entity
es_s <= esreg_s;
cs_s <= csreg_s;
ss_s <= ssreg_s;
ds_s <= dsreg_s;
end rtl;
|
-------------------------------------------------------------------------------
-- CPU86 - VHDL CPU8088 IP core --
-- Copyright (C) 2002-2008 HT-LAB --
-- --
-- Contact/bugs : http://www.ht-lab.com/misc/feedback.html --
-- Web : http://www.ht-lab.com --
-- --
-- CPU86 is released as open-source under the GNU GPL license. This means --
-- that designs based on CPU86 must be distributed in full source code --
-- under the same license. Contact HT-Lab for commercial applications where --
-- source-code distribution is not desirable. --
-- --
-------------------------------------------------------------------------------
-- --
-- This library is free software; you can redistribute it and/or --
-- modify it under the terms of the GNU Lesser General Public --
-- License as published by the Free Software Foundation; either --
-- version 2.1 of the License, or (at your option) any later version. --
-- --
-- This library is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU --
-- Lesser General Public License for more details. --
-- --
-- Full details of the license can be found in the file "copying.txt". --
-- --
-- You should have received a copy of the GNU Lesser General Public --
-- License along with this library; if not, write to the Free Software --
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA --
-- --
-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
USE ieee.std_logic_arith.ALL;
USE work.cpu86pack.ALL;
ENTITY segregfile IS
PORT(
selsreg : IN std_logic_vector (1 DOWNTO 0);
sibus : IN std_logic_vector (15 DOWNTO 0);
wrs : IN std_logic;
reset : IN std_logic;
clk : IN std_logic;
sdbus : OUT std_logic_vector (15 DOWNTO 0);
dimux : IN std_logic_vector (2 DOWNTO 0);
es_s : OUT std_logic_vector (15 DOWNTO 0);
cs_s : OUT std_logic_vector (15 DOWNTO 0);
ss_s : OUT std_logic_vector (15 DOWNTO 0);
ds_s : OUT std_logic_vector (15 DOWNTO 0)
);
END segregfile ;
architecture rtl of segregfile is
signal esreg_s : std_logic_vector(15 downto 0);
signal csreg_s : std_logic_vector(15 downto 0);
signal ssreg_s : std_logic_vector(15 downto 0);
signal dsreg_s : std_logic_vector(15 downto 0);
signal sdbus_s : std_logic_vector (15 downto 0); -- internal sdbus
signal dimux_s : std_logic_vector (2 downto 0); -- replaced dimux
begin
----------------------------------------------------------------------------
-- 4 registers of 16 bits each
----------------------------------------------------------------------------
process (clk,reset)
begin
if reset='1' then
esreg_s <= RESET_ES_C;
csreg_s <= RESET_CS_C; -- Only CS set after reset
ssreg_s <= RESET_SS_C;
dsreg_s <= RESET_DS_C;
elsif rising_edge(clk) then
if (wrs='1') then
case selsreg is
when "00" => esreg_s <= sibus;
when "01" => csreg_s <= sibus;
when "10" => ssreg_s <= sibus;
when others => dsreg_s <= sibus;
end case;
end if;
end if;
end process;
dimux_s <= dimux;
process (dimux_s,esreg_s,csreg_s,ssreg_s,dsreg_s)
begin
case dimux_s is -- Only 2 bits required
when "100" => sdbus_s <= esreg_s;
when "101" => sdbus_s <= csreg_s;
when "110" => sdbus_s <= ssreg_s;
when others => sdbus_s <= dsreg_s;
end case;
end process;
sdbus <= sdbus_s; -- Connect to entity
es_s <= esreg_s;
cs_s <= csreg_s;
ss_s <= ssreg_s;
ds_s <= dsreg_s;
end rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2579.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s02b00x00p12n01i02579ent IS
port (PT:BOOLEAN) ;
ty
pe ONE is range 1 to 1;
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
END c13s02b00x00p12n01i02579ent;
ARCHITECTURE c13s02b00x00p12n01i02579arch OF c13s02b00x00p12n01i02579ent IS
b
egin
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s02b00x00p12n01i02579 - Reserved words must fit on one line."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s02b00x00p12n01i02579arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2579.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s02b00x00p12n01i02579ent IS
port (PT:BOOLEAN) ;
ty
pe ONE is range 1 to 1;
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
END c13s02b00x00p12n01i02579ent;
ARCHITECTURE c13s02b00x00p12n01i02579arch OF c13s02b00x00p12n01i02579ent IS
b
egin
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s02b00x00p12n01i02579 - Reserved words must fit on one line."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s02b00x00p12n01i02579arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2579.vhd,v 1.2 2001-10-26 16:30:20 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s02b00x00p12n01i02579ent IS
port (PT:BOOLEAN) ;
ty
pe ONE is range 1 to 1;
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
END c13s02b00x00p12n01i02579ent;
ARCHITECTURE c13s02b00x00p12n01i02579arch OF c13s02b00x00p12n01i02579ent IS
b
egin
--ERROR: RESERVED WORDS MUST FIT ON ONE LINE
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c13s02b00x00p12n01i02579 - Reserved words must fit on one line."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s02b00x00p12n01i02579arch;
|
-------------------------------------------------------------------
-- (c) Copyright 1984 - 2012 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
-------------------------------------------------------------------
-- Filename: axi_master_burst_wrdata_cntl.vhd
--
-- Description:
-- This file implements the AXI Master Burst Write Data Controller module.
--
--
--
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
-- Structure:
-- axi_master_burst_wrdata_cntl.vhd
--
-------------------------------------------------------------------------------
-- Revision History:
--
--
-- Author: DET
-- Revision: $Revision: 1.0 $
-- Date: $1/19/2011$
--
-- History:
-- DET 1/19/2011 Initial
-- ~~~~~~
-- - Adapted from AXI DataMover V2_00_a axi_datamover_wrdata_cntl.vhd
-- - Disabled the sig_end_stbs_match_err detection
-- ^^^^^^
--
-- DET 2/15/2011 Initial for EDk 13.2
-- ~~~~~~
-- -- Per CR593812
-- - Modifications to remove unused features to improve Code coverage.
-- Used "-- coverage off" and "-- coverage on" strings.
-- ^^^^^^
--
-- DET 2/22/2011 Initial
-- ~~~~~~
-- -- Per CR594443
-- - Change to allow for posted AXI Write Commands to complete before
--- stopping the pushes to the Write Status controller on a undrrun or
-- overrun condition.
-- ^^^^^^
-- ~~~~~~
-- SK 12/16/12 -- v2.0
-- 1. up reved to major version for 2013.1 Vivado release. No logic updates.
-- 2. Updated the version of AXI MASTER BURST to v2.0 in X.Y format
-- 3. updated the proc common version to proc_common_v4_0
-- 4. No Logic Updates
-- ^^^^^^
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library axi_master_burst_v2_0;
use axi_master_burst_v2_0.axi_master_burst_fifo;
use axi_master_burst_v2_0.axi_master_burst_strb_gen;
-------------------------------------------------------------------------------
entity axi_master_burst_wrdata_cntl is
generic (
C_REALIGNER_INCLUDED : Integer range 0 to 1 := 0;
C_ENABLE_STORE_FORWARD : Integer range 0 to 1 := 0;
C_SF_BYTES_RCVD_WIDTH : Integer range 1 to 23 := 1;
C_SEL_ADDR_WIDTH : Integer range 1 to 8 := 5;
C_DATA_CNTL_FIFO_DEPTH : Integer range 1 to 32 := 4;
C_MMAP_DWIDTH : Integer range 32 to 256 := 32;
C_STREAM_DWIDTH : Integer range 8 to 256 := 32;
C_TAG_WIDTH : Integer range 1 to 8 := 4;
C_FAMILY : String := "virtex7"
);
port (
-- Clock input
primary_aclk : in std_logic;
-- Primary synchronization clock for the Master side
-- interface and internal logic. It is also used
-- for the User interface synchronization when
-- C_STSCMD_IS_ASYNC = 0.
-- Reset input
mmap_reset : in std_logic;
-- Reset used for the internal master logic
-- Soft Shutdown internal interface ---------------------------
rst2data_stop_request : in std_logic;
-- Active high soft stop request to modules
data2addr_stop_req : Out std_logic;
-- Active high signal requesting the Address Controller
-- to stop posting commands to the AXI Read Address Channel
data2rst_stop_cmplt : Out std_logic;
-- Active high indication that the Data Controller has completed
-- any pending transfers committed by the Address Controller
-- after a stop has been requested by the Reset module.
-- Store and Forward support signals for external User logic -------------
wr_xfer_cmplt : Out std_logic;
-- Active high indication that the Data Controller has completed
-- a single write data transfer on the AXI4 Write Data Channel.
-- This signal is escentially echos the assertion of wlast sent
-- to the AXI4.
s2mm_ld_nxt_len : out std_logic;
-- Active high pulse indicating a new xfer length has been queued
-- to the WDC Cmd FIFO
s2mm_wr_len : out std_logic_vector(7 downto 0);
-- Bus indicating the AXI LEN value associated with the xfer command
-- loaded into the WDC Command FIFO.
-- AXI Write Data Channel Skid buffer I/O -------------------------------
data2skid_saddr_lsb : out std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0);
-- Write DATA output to skid buffer
data2skid_wdata : Out std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- Write DATA output to skid buffer
data2skid_wstrb : Out std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- Write DATA output to skid buffer
data2skid_wlast : Out std_logic;
-- Write LAST output to skid buffer
data2skid_wvalid : Out std_logic;
-- Write VALID output to skid buffer
skid2data_wready : In std_logic;
-- Write READY input from skid buffer
-- AXI Slave Stream In -----------------------------------
s2mm_strm_wvalid : In std_logic;
-- AXI Stream VALID input
s2mm_strm_wready : Out Std_logic;
-- AXI Stream READY Output
s2mm_strm_wdata : In std_logic_vector(C_STREAM_DWIDTH-1 downto 0);
-- AXI Stream data input
s2mm_strm_wstrb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- AXI Stream STRB input
s2mm_strm_wlast : In std_logic;
-- AXI Stream LAST input
-- Stream input sideband signal from Store and Forward and/or DRE
s2mm_strm_eop : In std_logic;
-- Stream End of Packet marker input
s2mm_stbs_asserted : in std_logic_vector(7 downto 0);
-- Indicates the number of asserted WSTRB bits for the
-- associated input stream data beat
-- Realigner Underrun/overrun error flag used in non Store and Forward
-- Mode
realign2wdc_eop_error : In std_logic ;
-- asserted active high and will only clear with reset
-- Command Calculator Interface --------------------------
mstr2data_tag : In std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The next command tag
mstr2data_saddr_lsb : In std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0);
-- The next command start address LSbs to use for the write strb
-- demux (only used if Stream data width is less than the MMap Dwidth).
mstr2data_len : In std_logic_vector(7 downto 0);
-- The LEN value output to the Address Channel
mstr2data_strt_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- The starting strobe value to use for the first stream data beat
mstr2data_last_strb : In std_logic_vector((C_STREAM_DWIDTH/8)-1 downto 0);
-- The endiing (LAST) strobe value to use for the last stream
-- data beat
mstr2data_drr : In std_logic;
-- The starting tranfer of a sequence of transfers
mstr2data_eof : In std_logic;
-- The endiing tranfer of a sequence of transfers
mstr2data_sequential : In std_logic;
-- The next sequential tranfer of a sequence of transfers
-- spawned from a single parent command
mstr2data_calc_error : In std_logic;
-- Indication if the next command in the calculation pipe
-- has a calculation error
mstr2data_cmd_cmplt : In std_logic;
-- The final child tranfer of a parent command fetched from
-- the Command FIFO (not necessarily an EOF command)
mstr2data_cmd_valid : In std_logic;
-- The next command valid indication to the Data Channel
-- Controller for the AXI MMap
data2mstr_cmd_ready : Out std_logic ;
-- Indication from the Data Channel Controller that the
-- command is being accepted on the AXI Address
-- Channel
-- Address Controller Interface --------------------------
addr2data_addr_posted : In std_logic ;
-- Indication from the Address Channel Controller to the
-- Data Controller that an address has been posted to the
-- AXI Address Channel
data2addr_data_rdy : out std_logic;
-- Indication that the Data Channel is ready to send the first
-- databeat of the next command on the write data channel.
-- This is used for the "wait for data" feature which keeps the
-- address controller from issuing a transfer request until the
-- corresponding data valid is asserted on the stream input. The
-- WDC will continue to assert the output until an assertion on
-- the addr2data_addr_posted is received.
-- Premature TLAST assertion error flag
data2all_tlast_error : Out std_logic;
-- When asserted, this indicates the data controller detected
-- a premature TLAST assertion on the incoming data stream.
-- Data Controller Halted Status
data2all_dcntlr_halted : Out std_logic;
-- When asserted, this indicates the data controller has satisfied
-- all pending transfers queued by the Address Controller and is halted.
-- Input Stream Skid Buffer Halt control
data2skid_halt : Out std_logic;
-- The data controller asserts this output for 1 primary clock period
-- The pulse commands the MM2S Stream skid buffer to tun off outputs
-- at the next tlast transmission.
-- Write Status Controller Interface --------------------------
data2wsc_tag : Out std_logic_vector(C_TAG_WIDTH-1 downto 0);
-- The command tag
data2wsc_calc_err : Out std_logic ;
-- Indication that the current command out from the Cntl FIFO
-- has a calculation error
data2wsc_last_err : Out std_logic ;
-- Indication that the current write transfer encountered a premature
-- TLAST assertion on the incoming Stream Channel
data2wsc_cmd_cmplt : Out std_logic ;
-- Indication by the Data Channel Controller that the
-- corresponding status is the last status for a command
-- pulled from the command FIFO
wsc2data_ready : in std_logic;
-- Input from the Write Status Module indicating that the
-- Status Reg/FIFO is ready to accept data
data2wsc_valid : Out std_logic;
-- Output to the Command/Status Module indicating that the
-- Data Controller has valid tag and err indicators to write
-- to the Status module
data2wsc_eop : Out std_logic;
-- Output to the Write Status Controller indicating that the
-- associated command status also corresponds to a End of Packet
-- marker for the input Stream. This is only used when Store and
-- Forward is enabled in the S2MM.
data2wsc_bytes_rcvd : Out std_logic_vector(C_SF_BYTES_RCVD_WIDTH-1 downto 0);
-- Output to the Write Status Controller indicating the actual
-- number of bytes received from the Stream input for the
-- corresponding command status. This is only used when Store and
-- Forward is enabled in the S2MM.
wsc2mstr_halt_pipe : In std_logic
-- Indication to Halt the Data and Address Command pipeline due
-- to the Status FIFO going full or an internal error being logged
);
end entity axi_master_burst_wrdata_cntl;
architecture implementation of axi_master_burst_wrdata_cntl is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-- Function declaration ----------------------------------------
-- coverage off
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_get_dbeat_residue_width
--
-- Function Description:
-- Calculates the number of Least significant bits of the BTT field
-- that are unused for the LEN calculation
--
-------------------------------------------------------------------
function funct_get_dbeat_residue_width (bytes_per_beat : integer) return integer is
Variable temp_dbeat_residue_width : Integer := 0; -- 8-bit stream
begin
case bytes_per_beat is
when 32 =>
temp_dbeat_residue_width := 5;
when 16 =>
temp_dbeat_residue_width := 4;
when 8 =>
temp_dbeat_residue_width := 3;
when 4 =>
temp_dbeat_residue_width := 2;
when 2 =>
temp_dbeat_residue_width := 1;
when others => -- assume 1-byte transfers
temp_dbeat_residue_width := 0;
end case;
Return (temp_dbeat_residue_width);
end function funct_get_dbeat_residue_width;
-- coverage on
-------------------------------------------------------------------
-- Function
--
-- Function Name: funct_set_cnt_width
--
-- Function Description:
-- Sets a count width based on a fifo depth. A depth of 4 or less
-- is a special case which requires a minimum count width of 3 bits.
--
-------------------------------------------------------------------
function funct_set_cnt_width (fifo_depth : integer) return integer is
Variable temp_cnt_width : Integer := 4;
begin
if (fifo_depth <= 4) then
temp_cnt_width := 3;
elsif (fifo_depth <= 8) then
temp_cnt_width := 4;
elsif (fifo_depth <= 16) then
temp_cnt_width := 5;
-- coverage off
elsif (fifo_depth <= 32) then
temp_cnt_width := 6;
else -- fifo depth <= 64
temp_cnt_width := 7;
-- coverage on
end if;
Return (temp_cnt_width);
end function funct_set_cnt_width;
-- Constant Declarations --------------------------------------------
Constant STRM_STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant LEN_OF_ZERO : std_logic_vector(7 downto 0) := (others => '0');
Constant USE_SYNC_FIFO : integer := 0;
Constant REG_FIFO_PRIM : integer := 0;
Constant BRAM_FIFO_PRIM : integer := 1;
Constant SRL_FIFO_PRIM : integer := 2;
Constant FIFO_PRIM_TYPE : integer := SRL_FIFO_PRIM;
Constant TAG_WIDTH : integer := C_TAG_WIDTH;
Constant SADDR_LSB_WIDTH : integer := C_SEL_ADDR_WIDTH;
Constant LEN_WIDTH : integer := 8;
Constant STRB_WIDTH : integer := C_STREAM_DWIDTH/8;
Constant DRR_WIDTH : integer := 1;
Constant EOF_WIDTH : integer := 1;
Constant CALC_ERR_WIDTH : integer := 1;
Constant CMD_CMPLT_WIDTH : integer := 1;
Constant SEQUENTIAL_WIDTH : integer := 1;
Constant DCTL_FIFO_WIDTH : Integer := TAG_WIDTH + -- Tag field
SADDR_LSB_WIDTH + -- LS Address field width
LEN_WIDTH + -- LEN field
STRB_WIDTH + -- Starting Strobe field
STRB_WIDTH + -- Ending Strobe field
DRR_WIDTH + -- DRE Re-alignment Request Flag Field
EOF_WIDTH + -- EOF flag field
SEQUENTIAL_WIDTH + -- Sequential command flag
CMD_CMPLT_WIDTH + -- Command Complete Flag
CALC_ERR_WIDTH; -- Calc error flag
Constant TAG_STRT_INDEX : integer := 0;
Constant SADDR_LSB_STRT_INDEX : integer := TAG_STRT_INDEX + TAG_WIDTH;
Constant LEN_STRT_INDEX : integer := SADDR_LSB_STRT_INDEX + SADDR_LSB_WIDTH;
Constant STRT_STRB_STRT_INDEX : integer := LEN_STRT_INDEX + LEN_WIDTH;
Constant LAST_STRB_STRT_INDEX : integer := STRT_STRB_STRT_INDEX + STRB_WIDTH;
Constant DRR_STRT_INDEX : integer := LAST_STRB_STRT_INDEX + STRB_WIDTH;
Constant EOF_STRT_INDEX : integer := DRR_STRT_INDEX + DRR_WIDTH;
Constant SEQUENTIAL_STRT_INDEX : integer := EOF_STRT_INDEX + EOF_WIDTH;
Constant CMD_CMPLT_STRT_INDEX : integer := SEQUENTIAL_STRT_INDEX+SEQUENTIAL_WIDTH;
Constant CALC_ERR_STRT_INDEX : integer := CMD_CMPLT_STRT_INDEX+CMD_CMPLT_WIDTH;
Constant ADDR_INCR_VALUE : integer := C_STREAM_DWIDTH/8;
--Constant ADDR_POSTED_CNTR_WIDTH : integer := 5; -- Allows for 32 address entry queue
Constant ADDR_POSTED_CNTR_WIDTH : integer := funct_set_cnt_width(C_DATA_CNTL_FIFO_DEPTH);
Constant ADDR_POSTED_ZERO : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '0');
Constant ADDR_POSTED_ONE : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= TO_UNSIGNED(1, ADDR_POSTED_CNTR_WIDTH);
Constant ADDR_POSTED_MAX : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0)
:= (others => '1');
-- Signal Declarations --------------------------------------------
signal sig_get_next_dqual : std_logic := '0';
signal sig_last_mmap_dbeat : std_logic := '0';
signal sig_last_mmap_dbeat_reg : std_logic := '0';
signal sig_mmap2data_ready : std_logic := '0';
signal sig_data2mmap_valid : std_logic := '0';
signal sig_data2mmap_last : std_logic := '0';
signal sig_data2mmap_data : std_logic_vector(C_STREAM_DWIDTH-1 downto 0) := (others => '0');
signal sig_ld_new_cmd : std_logic := '0';
signal sig_ld_new_cmd_reg : std_logic := '0';
signal sig_cmd_cmplt_reg : std_logic := '0';
signal sig_calc_error_reg : std_logic := '0';
signal sig_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_lsb_reg : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted : std_logic := '0';
signal sig_dqual_rdy : std_logic := '0';
signal sig_good_mmap_dbeat : std_logic := '0';
signal sig_first_dbeat : std_logic := '0';
signal sig_last_dbeat : std_logic := '0';
signal sig_single_dbeat : std_logic := '0';
signal sig_new_len_eq_0 : std_logic := '0';
signal sig_dbeat_cntr : unsigned(7 downto 0) := (others => '0');
Signal sig_dbeat_cntr_int : Integer range 0 to 255 := 0;
signal sig_dbeat_cntr_eq_0 : std_logic := '0';
signal sig_dbeat_cntr_eq_1 : std_logic := '0';
signal sig_wsc_ready : std_logic := '0';
signal sig_push_to_wsc : std_logic := '0';
signal sig_push_to_wsc_cmplt : std_logic := '0';
signal sig_set_push2wsc : std_logic := '0';
signal sig_data2wsc_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_data2wsc_calc_err : std_logic := '0';
signal sig_data2wsc_last_err : std_logic := '0';
signal sig_data2wsc_cmd_cmplt : std_logic := '0';
signal sig_tlast_error : std_logic := '0';
signal sig_tlast_error_strbs : std_logic := '0';
signal sig_end_stbs_match_err : std_logic := '0';
signal sig_tlast_error_reg : std_logic := '0';
signal sig_cmd_is_eof : std_logic := '0';
signal sig_push_err2wsc : std_logic := '0';
signal sig_tlast_error_ovrrun : std_logic := '0';
signal sig_tlast_error_undrrun : std_logic := '0';
signal sig_next_tag_reg : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_next_strt_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_last_strb_reg : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_next_eof_reg : std_logic := '0';
signal sig_next_sequential_reg : std_logic := '0';
signal sig_next_cmd_cmplt_reg : std_logic := '0';
signal sig_next_calc_error_reg : std_logic := '0';
signal sig_pop_dqual_reg : std_logic := '0';
signal sig_push_dqual_reg : std_logic := '0';
signal sig_dqual_reg_empty : std_logic := '0';
signal sig_dqual_reg_full : std_logic := '0';
signal sig_addr_posted_cntr : unsigned(ADDR_POSTED_CNTR_WIDTH-1 downto 0) := (others => '0');
signal sig_addr_posted_cntr_eq_0 : std_logic := '0';
signal sig_addr_posted_cntr_max : std_logic := '0';
signal sig_decr_addr_posted_cntr : std_logic := '0';
signal sig_incr_addr_posted_cntr : std_logic := '0';
signal sig_addr_posted_cntr_eq_1 : std_logic := '0';
signal sig_apc_going2zero : std_logic := '0';
signal sig_aposted_cntr_ready : std_logic := '0';
signal sig_addr_chan_rdy : std_logic := '0';
Signal sig_no_posted_cmds : std_logic := '0';
signal sig_ls_addr_cntr : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_incr_ls_addr_cntr : std_logic := '0';
signal sig_addr_incr_unsgnd : unsigned(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_in : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
Signal sig_cmd_fifo_data_out : std_logic_vector(DCTL_FIFO_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_tag : std_logic_vector(TAG_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_sadddr_lsb : std_logic_vector(C_SEL_ADDR_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_fifo_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_last_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_fifo_next_drr : std_logic := '0';
signal sig_fifo_next_eof : std_logic := '0';
signal sig_fifo_next_cmd_cmplt : std_logic := '0';
signal sig_fifo_next_sequential : std_logic := '0';
signal sig_fifo_next_calc_error : std_logic := '0';
signal sig_cmd_fifo_empty : std_logic := '0';
signal sig_fifo_wr_cmd_valid : std_logic := '0';
signal sig_fifo_wr_cmd_ready : std_logic := '0';
signal sig_fifo_rd_cmd_valid : std_logic := '0';
signal sig_fifo_rd_cmd_ready : std_logic := '0';
signal sig_sequential_push : std_logic := '0';
signal sig_clr_dqual_reg : std_logic := '0';
signal sig_tlast_err_stop : std_logic := '0';
signal sig_halt_reg : std_logic := '0';
signal sig_halt_reg_dly1 : std_logic := '0';
signal sig_halt_reg_dly2 : std_logic := '0';
signal sig_halt_reg_dly3 : std_logic := '0';
signal sig_data2skid_halt : std_logic := '0';
signal sig_stop_wvalid : std_logic := '0';
signal sig_data2rst_stop_cmplt : std_logic := '0';
signal sig_s2mm_strm_wready : std_logic := '0';
signal sig_good_strm_dbeat : std_logic := '0';
signal sig_halt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_sfhalt_next_strt_strb : std_logic_vector(STRM_STRB_WIDTH-1 downto 0) := (others => '0');
signal sig_wfd_simult_clr_set : std_logic := '0';
signal sig_wr_xfer_cmplt : std_logic := '0';
signal sig_s2mm_ld_nxt_len : std_logic := '0';
signal sig_s2mm_wr_len : std_logic_vector(7 downto 0) := (others => '0');
signal sig_data2mstr_cmd_ready : std_logic := '0';
begin --(architecture implementation)
-- Command calculator handshake
data2mstr_cmd_ready <= sig_data2mstr_cmd_ready;
-- Write Data Channel Skid Buffer Port assignments
sig_mmap2data_ready <= skid2data_wready ;
data2skid_wvalid <= sig_data2mmap_valid ;
data2skid_wlast <= sig_data2mmap_last ;
data2skid_wdata <= sig_data2mmap_data ;
data2skid_saddr_lsb <= sig_addr_lsb_reg ;
-- AXI MM2S Stream Channel Port assignments
sig_data2mmap_data <= s2mm_strm_wdata ;
-- Premature TLAST assertion indication
data2all_tlast_error <= sig_tlast_error_reg ;
-- Stream Input Ready Handshake
s2mm_strm_wready <= sig_s2mm_strm_wready ;
sig_good_strm_dbeat <= s2mm_strm_wvalid and
sig_s2mm_strm_wready;
sig_data2mmap_last <= sig_dbeat_cntr_eq_0 and
sig_dqual_rdy;
-- Write Status Block interface signals
data2wsc_valid <= sig_push_to_wsc and
not(sig_tlast_err_stop) ; -- only allow 1 status write on TLAST errror
sig_wsc_ready <= wsc2data_ready ;
data2wsc_tag <= sig_data2wsc_tag ;
data2wsc_calc_err <= sig_data2wsc_calc_err ;
data2wsc_last_err <= sig_data2wsc_last_err ;
data2wsc_cmd_cmplt <= sig_data2wsc_cmd_cmplt ;
-- Address Channel Controller synchro pulse input
sig_addr_posted <= addr2data_addr_posted;
-- Request to halt the Address Channel Controller
data2addr_stop_req <= sig_halt_reg or
sig_tlast_error_reg;
-- Halted flag to the reset module
data2rst_stop_cmplt <= sig_data2rst_stop_cmplt;
-- Indicate the Write Data Controller is always ready
data2addr_data_rdy <= '1';
-- Write Transfer Completed Status output
wr_xfer_cmplt <= sig_wr_xfer_cmplt ;
-- New LEN value is being loaded
s2mm_ld_nxt_len <= sig_s2mm_ld_nxt_len;
-- The new LEN value
s2mm_wr_len <= sig_s2mm_wr_len;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_WR_CMPLT_FLAG
--
-- Process Description:
-- Implements the status flag indicating that a write data
-- transfer has completed. This is an echo of a wlast assertion
-- and a qualified data beat on the AXI4 Write Data Channel.
--
-------------------------------------------------------------
IMP_WR_CMPLT_FLAG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_wr_xfer_cmplt <= '0';
else
sig_wr_xfer_cmplt <= sig_data2mmap_last and
sig_good_strm_dbeat;
end if;
end if;
end process IMP_WR_CMPLT_FLAG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_OMIT_STORE_FORWARD
--
-- If Generate Description:
-- Omits any Store and Forward Support logic and includes
-- any error detection needed in Non Store and Forward mode.
--
------------------------------------------------------------
GEN_OMIT_STORE_FORWARD : if (C_ENABLE_STORE_FORWARD = 0) generate
begin
sig_sfhalt_next_strt_strb <= sig_fifo_next_strt_strb;
-- Just housekeep the output port signals
data2wsc_eop <= '0';
data2wsc_bytes_rcvd <= (others => '0');
-- WRSTRB logic ------------------------------
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the non Store and Forward Case
data2skid_wstrb <= sig_strt_strb_reg
When (sig_first_dbeat = '1')
Else sig_last_strb_reg
When (sig_last_dbeat = '1')
Else (others => '1');
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and
sig_addr_chan_rdy and -- This puts combinational logic in the stream WREADY path
sig_dqual_rdy and
not(sig_calc_error_reg) and
not(sig_tlast_error_reg)); -- Stop the stream channel at a overrun/underrun detection
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or
sig_tlast_error_reg or -- force valid if TLAST error
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and
not(sig_stop_wvalid); -- gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_LOCAL_ERR_DETECT
--
-- If Generate Description:
-- Implements the local overrun and underrun detection when
-- the S2MM Realigner is not included.
--
--
------------------------------------------------------------
GEN_LOCAL_ERR_DETECT : if (C_REALIGNER_INCLUDED = 0) generate
begin
------- Input Stream TLAST assertion error -------------------------------
sig_tlast_error_ovrrun <= sig_cmd_is_eof and
sig_dbeat_cntr_eq_0 and
sig_good_mmap_dbeat and
not(s2mm_strm_wlast);
sig_tlast_error_undrrun <= s2mm_strm_wlast and
sig_good_mmap_dbeat and
(not(sig_dbeat_cntr_eq_0) or
not(sig_cmd_is_eof));
sig_end_stbs_match_err <= '0'; -- Disable this for aAXI Master burst
-- sig_end_stbs_match_err <= '1' -- Set flag if the calculated end strobe value
-- When ((s2mm_strm_wstrb /= sig_next_last_strb_reg) and -- does not match the received strobe value
-- (s2mm_strm_wlast = '1') and -- at TLAST assertion
-- (sig_good_mmap_dbeat = '1')) -- Qualified databeat
-- Else '0';
sig_tlast_error <= (sig_tlast_error_ovrrun or
sig_tlast_error_undrrun or
sig_end_stbs_match_err) and
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
end generate GEN_LOCAL_ERR_DETECT;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_EXTERN_ERR_DETECT
--
-- If Generate Description:
-- Omits the local overrun and underrun detection and relies
-- on the S2MM Realigner for the detection.
--
------------------------------------------------------------
GEN_EXTERN_ERR_DETECT : if (C_REALIGNER_INCLUDED = 1) generate
begin
sig_tlast_error_undrrun <= '0'; -- not used here
sig_tlast_error_ovrrun <= '0'; -- not used here
sig_end_stbs_match_err <= '0'; -- not used here
sig_tlast_error <= realign2wdc_eop_error and -- External error detection asserted
not(sig_halt_reg); -- Suppress TLAST error when in soft shutdown
end generate GEN_EXTERN_ERR_DETECT;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERR_REG
--
-- Process Description:
-- Implements a sample and hold flop for the flag indicating
-- that the input Stream TLAST assertion was not at the expected
-- data beat relative to the commanded number of databeats
-- from the associated command from the SCC or PCC.
-------------------------------------------------------------
IMP_TLAST_ERR_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_error_reg <= '0';
elsif (sig_tlast_error = '1') then
sig_tlast_error_reg <= '1';
else
null; -- hold current state
end if;
end if;
end process IMP_TLAST_ERR_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_TLAST_ERROR_STOP
--
-- Process Description:
-- Implements the flop to generate a stop flag once the TLAST
-- error condition has been relayed to the Write Status
-- Controller. This stop flag is used to prevent any more
-- pushes to the Write Status Controller.
--
-- However, if transfer requests have already been posted to
-- the AXI bus, they must be allowed to complete before stopping.
-------------------------------------------------------------
IMP_TLAST_ERROR_STOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_tlast_err_stop <= '0';
-- elsif (sig_tlast_error_reg = '1' and
-- sig_push_to_wsc_cmplt = '1') then
elsif (sig_tlast_error_reg = '1' and
sig_push_to_wsc_cmplt = '1' and
(sig_no_posted_cmds = '1' or
sig_apc_going2zero = '1')) then
sig_tlast_err_stop <= '1';
else
null; -- Hold State
end if;
end if;
end process IMP_TLAST_ERROR_STOP;
end generate GEN_OMIT_STORE_FORWARD;
-- coverage off
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_STORE_FORWARD
--
-- If Generate Description:
-- Includes any Store and Forward Support logic. Primarily
-- this is a counter for the input stream bytes received. The
-- received byte count is relayed to the Write Status Controller
-- for each parent command completed.
-- When a packet completion is indicated via the EOP marker
-- assertion, the status to the Write Status Controller also
-- indicates the EOP condition.
-- Note that underrun and overrun detection/error flagging
-- is disabled in Store and Forward Mode.
--
------------------------------------------------------------
GEN_STORE_FORWARD : if (C_ENABLE_STORE_FORWARD = 1) generate
-- local constants
Constant BYTE_CNTR_WIDTH : integer := C_SF_BYTES_RCVD_WIDTH;
Constant NUM_ZEROS_WIDTH : integer := 8;
Constant BYTES_PER_DBEAT : integer := C_STREAM_DWIDTH/8;
Constant STRBGEN_ADDR_SLICE_WIDTH : integer :=
funct_get_dbeat_residue_width(BYTES_PER_DBEAT);
-- local signals
signal lsig_byte_cntr : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_byte_cntr_incr_value : unsigned(BYTE_CNTR_WIDTH-1 downto 0) := (others => '0');
signal lsig_ld_byte_cntr : std_logic := '0';
signal lsig_incr_byte_cntr : std_logic := '0';
signal lsig_clr_byte_cntr : std_logic := '0';
signal lsig_end_of_cmd_reg : std_logic := '0';
signal lsig_eop_s_h_reg : std_logic := '0';
signal lsig_eop_reg : std_logic := '0';
signal sig_strbgen_addr : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH-1 downto 0) := (others => '0');
signal sig_strbgen_bytes : std_logic_vector(STRBGEN_ADDR_SLICE_WIDTH downto 0) := (others => '0');
begin
-- Assign the outputs to the Write Status Controller
data2wsc_eop <= lsig_eop_reg and
not(sig_next_calc_error_reg);
data2wsc_bytes_rcvd <= STD_LOGIC_VECTOR(lsig_byte_cntr);
-- WRSTRB logic ------------------------------
sig_strbgen_bytes <= (others => '1'); -- set to the max value
sig_strbgen_addr <= STD_LOGIC_VECTOR(RESIZE(UNSIGNED(sig_fifo_next_sadddr_lsb),
STRBGEN_ADDR_SLICE_WIDTH)) ;
------------------------------------------------------------
-- Instance: I_STRT_STRB_GEN
--
-- Description:
-- Strobe generator used to generate the starting databeat
-- strobe value for soft shutdown case where the S2MM has to
-- flush out all of the transfers that have been committed
-- to the AXI Write address channel. Starting Strobes must
-- match the committed address offest for each transfer.
--
------------------------------------------------------------
I_STRT_STRB_GEN : entity axi_master_burst_v2_0.axi_master_burst_strb_gen
generic map (
C_ADDR_MODE => 0 , -- 0 = normal, 1 = Address only
C_STRB_WIDTH => BYTES_PER_DBEAT ,
C_OFFSET_WIDTH => STRBGEN_ADDR_SLICE_WIDTH ,
C_NUM_BYTES_WIDTH => STRBGEN_ADDR_SLICE_WIDTH+1
)
port map (
start_addr_offset => sig_strbgen_addr ,
num_valid_bytes => sig_strbgen_bytes ,
strb_out => sig_sfhalt_next_strt_strb
);
-- Generate the WSTRB to use during soft shutdown
sig_halt_strb <= sig_strt_strb_reg
When (sig_first_dbeat = '1' or
sig_single_dbeat = '1')
Else (others => '1');
-- Generate the Write Strobes for the MMap Write Data Channel
-- for the Store and Forward case. Strobes come from the Stream
-- input from the Store and forward module during normal operation.
-- However, during soft shutdown, those strobes become unpredictable
-- so generated strobes have to be used.
data2skid_wstrb <= sig_halt_strb
When (sig_halt_reg = '1')
Else s2mm_strm_wstrb;
-- Generate the Stream Ready for the Stream input side
sig_s2mm_strm_wready <= sig_halt_reg or -- force tready if a halt requested
(sig_mmap2data_ready and -- MMap is accepting the xfers
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid)); -- Gate off stream ready immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- MMap Write Data Channel Valid Handshaking
sig_data2mmap_valid <= (s2mm_strm_wvalid or -- Normal Stream input valid
sig_halt_reg ) and -- force valid if halt requested
sig_addr_chan_rdy and -- xfers are commited on the address channel and
sig_dqual_rdy and -- there are commands in the command fifo
not(sig_calc_error_reg) and -- No internal error
not(sig_stop_wvalid); -- Gate off wvalid immediately after a wlast for 1 clk
-- or when the soft shutdown has completed
-- TLAST Error housekeeping for Store and Forward Mode
-- There is no Underrun/overrun in Stroe and Forward mode
sig_tlast_error_ovrrun <= '0'; -- Not used with Store and Forward
sig_tlast_error_undrrun <= '0'; -- Not used with Store and Forward
sig_end_stbs_match_err <= '0'; -- Not used with Store and Forward
sig_tlast_error <= '0'; -- Not used with Store and Forward
sig_tlast_error_reg <= '0'; -- Not used with Store and Forward
sig_tlast_err_stop <= '0'; -- Not used with Store and Forward
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_EOP_REG_FLOP
--
-- Process Description:
-- Register the End of Packet marker.
--
-------------------------------------------------------------
IMP_EOP_REG_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
lsig_end_of_cmd_reg <= '0';
lsig_eop_reg <= '0';
Elsif (sig_good_strm_dbeat = '1') Then
lsig_end_of_cmd_reg <= sig_next_cmd_cmplt_reg and
s2mm_strm_wlast;
lsig_eop_reg <= s2mm_strm_eop;
else
null; -- hold current state
end if;
end if;
end process IMP_EOP_REG_FLOP;
----- Byte Counter Logic -----------------------------------------------
-- The Byte counter reflects the actual byte count received on the
-- Stream input for each parent command loaded into the S2MM command
-- FIFO. Thus it counts input bytes until the command complete qualifier
-- is set and the TLAST input from the Stream input.
lsig_clr_byte_cntr <= lsig_end_of_cmd_reg and -- Clear if a new stream packet does not start
not(sig_good_strm_dbeat); -- immediately after the previous one finished.
lsig_ld_byte_cntr <= lsig_end_of_cmd_reg and -- Only load if a new stream packet starts
sig_good_strm_dbeat; -- immediately after the previous one finished.
lsig_incr_byte_cntr <= sig_good_strm_dbeat;
lsig_byte_cntr_incr_value <= RESIZE(UNSIGNED(s2mm_stbs_asserted),
BYTE_CNTR_WIDTH);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_BYTE_CMTR
--
-- Process Description:
-- Keeps a running byte count per burst packet loaded into the
-- xfer FIFO. It is based on the strobes set on the incoming
-- Stream dbeat.
--
-------------------------------------------------------------
IMP_BYTE_CMTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
lsig_clr_byte_cntr = '1') then
lsig_byte_cntr <= (others => '0');
elsif (lsig_ld_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr_incr_value;
elsif (lsig_incr_byte_cntr = '1') then
lsig_byte_cntr <= lsig_byte_cntr + lsig_byte_cntr_incr_value;
else
null; -- hold current value
end if;
end if;
end process IMP_BYTE_CMTR;
end generate GEN_STORE_FORWARD;
-- coverage on
-- Internal logic ------------------------------
sig_good_mmap_dbeat <= sig_mmap2data_ready and
sig_data2mmap_valid;
sig_last_mmap_dbeat <= sig_good_mmap_dbeat and
sig_data2mmap_last;
sig_get_next_dqual <= sig_last_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: REG_LAST_DBEAT
--
-- Process Description:
-- This implements a FLOP that creates a pulse
-- indicating the LAST signal for an outgoing write data channel
-- has been sent. Note that it is possible to have back to
-- back LAST databeats.
--
-------------------------------------------------------------
REG_LAST_DBEAT : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_last_mmap_dbeat_reg <= '0';
else
sig_last_mmap_dbeat_reg <= sig_last_mmap_dbeat;
end if;
end if;
end process REG_LAST_DBEAT;
----- Write Status Interface Stuff --------------------------
sig_push_to_wsc_cmplt <= sig_push_to_wsc and sig_wsc_ready;
sig_set_push2wsc <= (sig_good_mmap_dbeat and
sig_dbeat_cntr_eq_0) or
sig_push_err2wsc;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_INTERR_PUSH_FLOP
--
-- Process Description:
-- Generate a 1 clock wide pulse when a calc error has propagated
-- from the Command Calculator. This pulse is used to force a
-- push of the error status to the Write Status Controller
-- without a AXI transfer completion.
--
-------------------------------------------------------------
IMP_INTERR_PUSH_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_push_err2wsc = '1') then
sig_push_err2wsc <= '0';
elsif (sig_ld_new_cmd_reg = '1' and
sig_calc_error_reg = '1') then
sig_push_err2wsc <= '1';
else
null; -- hold state
end if;
end if;
end process IMP_INTERR_PUSH_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_PUSH2WSC_FLOP
--
-- Process Description:
-- Implements a Sample and hold register for the outbound status
-- signals to the Write Status Controller (WSC). This register
-- has to support back to back transfer completions.
--
-------------------------------------------------------------
IMP_PUSH2WSC_FLOP : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_push_to_wsc_cmplt = '1' and
sig_set_push2wsc = '0')) then
sig_push_to_wsc <= '0';
sig_data2wsc_tag <= (others => '0');
sig_data2wsc_calc_err <= '0';
sig_data2wsc_last_err <= '0';
sig_data2wsc_cmd_cmplt <= '0';
elsif (sig_set_push2wsc = '1' and
sig_tlast_err_stop = '0') then
sig_push_to_wsc <= '1';
sig_data2wsc_tag <= sig_tag_reg ;
sig_data2wsc_calc_err <= sig_calc_error_reg ;
sig_data2wsc_last_err <= sig_tlast_error_reg or
sig_tlast_error ;
-- sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
-- sig_tlast_error_reg or
-- sig_tlast_error ;
sig_data2wsc_cmd_cmplt <= sig_cmd_cmplt_reg or
(sig_tlast_error_reg and
(sig_no_posted_cmds or
sig_apc_going2zero ));
else
null; -- hold current state
end if;
end if;
end process IMP_PUSH2WSC_FLOP;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_LD_NEW_CMD_REG
--
-- Process Description:
-- Registers the flag indicating a new command has been
-- loaded. Needs to be a 1 clk wide pulse.
--
-------------------------------------------------------------
IMP_LD_NEW_CMD_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
sig_ld_new_cmd_reg = '1') then
sig_ld_new_cmd_reg <= '0';
else
sig_ld_new_cmd_reg <= sig_ld_new_cmd;
end if;
end if;
end process IMP_LD_NEW_CMD_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_NXT_LEN_REG
--
-- Process Description:
-- Registers the load control and length value for a command
-- passed to the WDC input command interface. The registered
-- signals are used for the external Store and forward support
-- ports.
--
-------------------------------------------------------------
IMP_NXT_LEN_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_s2mm_ld_nxt_len <= '0';
sig_s2mm_wr_len <= (others => '0');
else
sig_s2mm_ld_nxt_len <= mstr2data_cmd_valid and
sig_data2mstr_cmd_ready;
sig_s2mm_wr_len <= mstr2data_len;
end if;
end if;
end process IMP_NXT_LEN_REG;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_NO_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Omits the input data control FIFO if the requested FIFO
-- depth is 1. The Data Qualifier Register serves as a
-- 1 deep FIFO by itself.
--
------------------------------------------------------------
GEN_NO_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH = 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready ;
sig_fifo_rd_cmd_valid <= mstr2data_cmd_valid ;
sig_fifo_wr_cmd_ready <= sig_push_dqual_reg ;
sig_fifo_next_tag <= mstr2data_tag ;
sig_fifo_next_sadddr_lsb <= mstr2data_saddr_lsb ;
sig_fifo_next_len <= mstr2data_len ;
sig_fifo_next_strt_strb <= mstr2data_strt_strb ;
sig_fifo_next_last_strb <= mstr2data_last_strb ;
sig_fifo_next_drr <= mstr2data_drr ;
sig_fifo_next_eof <= mstr2data_eof ;
sig_fifo_next_sequential <= mstr2data_sequential ;
sig_fifo_next_cmd_cmplt <= mstr2data_cmd_cmplt ;
sig_fifo_next_calc_error <= mstr2data_calc_error ;
end generate GEN_NO_DATA_CNTL_FIFO;
------------------------------------------------------------
-- If Generate
--
-- Label: GEN_DATA_CNTL_FIFO
--
-- If Generate Description:
-- Includes the input data control FIFO if the requested
-- FIFO depth is more than 1.
--
------------------------------------------------------------
GEN_DATA_CNTL_FIFO : if (C_DATA_CNTL_FIFO_DEPTH > 1) generate
begin
-- Command Calculator Handshake output
sig_data2mstr_cmd_ready <= sig_fifo_wr_cmd_ready;
sig_fifo_wr_cmd_valid <= mstr2data_cmd_valid ;
-- pop the fifo when dqual reg is pushed
sig_fifo_rd_cmd_ready <= sig_push_dqual_reg;
-- Format the input fifo data word
sig_cmd_fifo_data_in <= mstr2data_calc_error &
mstr2data_cmd_cmplt &
mstr2data_sequential &
mstr2data_eof &
mstr2data_drr &
mstr2data_last_strb &
mstr2data_strt_strb &
mstr2data_len &
mstr2data_saddr_lsb &
mstr2data_tag ;
-- Rip the output fifo data word
sig_fifo_next_tag <= sig_cmd_fifo_data_out((TAG_STRT_INDEX+TAG_WIDTH)-1 downto
TAG_STRT_INDEX);
sig_fifo_next_sadddr_lsb <= sig_cmd_fifo_data_out((SADDR_LSB_STRT_INDEX+SADDR_LSB_WIDTH)-1 downto
SADDR_LSB_STRT_INDEX);
sig_fifo_next_len <= sig_cmd_fifo_data_out((LEN_STRT_INDEX+LEN_WIDTH)-1 downto
LEN_STRT_INDEX);
sig_fifo_next_strt_strb <= sig_cmd_fifo_data_out((STRT_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
STRT_STRB_STRT_INDEX);
sig_fifo_next_last_strb <= sig_cmd_fifo_data_out((LAST_STRB_STRT_INDEX+STRB_WIDTH)-1 downto
LAST_STRB_STRT_INDEX);
sig_fifo_next_drr <= sig_cmd_fifo_data_out(DRR_STRT_INDEX);
sig_fifo_next_eof <= sig_cmd_fifo_data_out(EOF_STRT_INDEX);
sig_fifo_next_sequential <= sig_cmd_fifo_data_out(SEQUENTIAL_STRT_INDEX);
sig_fifo_next_cmd_cmplt <= sig_cmd_fifo_data_out(CMD_CMPLT_STRT_INDEX);
sig_fifo_next_calc_error <= sig_cmd_fifo_data_out(CALC_ERR_STRT_INDEX);
------------------------------------------------------------
-- Instance: I_DATA_CNTL_FIFO
--
-- Description:
-- Instance for the Command Qualifier FIFO
--
------------------------------------------------------------
I_DATA_CNTL_FIFO : entity axi_master_burst_v2_0.axi_master_burst_fifo
generic map (
C_DWIDTH => DCTL_FIFO_WIDTH ,
C_DEPTH => C_DATA_CNTL_FIFO_DEPTH ,
C_IS_ASYNC => USE_SYNC_FIFO ,
C_PRIM_TYPE => FIFO_PRIM_TYPE ,
C_FAMILY => C_FAMILY
)
port map (
-- Write Clock and reset
fifo_wr_reset => mmap_reset ,
fifo_wr_clk => primary_aclk ,
-- Write Side
fifo_wr_tvalid => sig_fifo_wr_cmd_valid ,
fifo_wr_tready => sig_fifo_wr_cmd_ready ,
fifo_wr_tdata => sig_cmd_fifo_data_in ,
fifo_wr_full => open ,
-- Read Clock and reset
fifo_async_rd_reset => mmap_reset ,
fifo_async_rd_clk => primary_aclk ,
-- Read Side
fifo_rd_tvalid => sig_fifo_rd_cmd_valid ,
fifo_rd_tready => sig_fifo_rd_cmd_ready ,
fifo_rd_tdata => sig_cmd_fifo_data_out ,
fifo_rd_empty => sig_cmd_fifo_empty
);
end generate GEN_DATA_CNTL_FIFO;
-- Data Qualifier Register ------------------------------------
sig_ld_new_cmd <= sig_push_dqual_reg ;
sig_dqual_rdy <= sig_dqual_reg_full ;
sig_strt_strb_reg <= sig_next_strt_strb_reg ;
sig_last_strb_reg <= sig_next_last_strb_reg ;
sig_tag_reg <= sig_next_tag_reg ;
sig_cmd_cmplt_reg <= sig_next_cmd_cmplt_reg ;
sig_calc_error_reg <= sig_next_calc_error_reg ;
sig_cmd_is_eof <= sig_next_eof_reg ;
-- new for no bubbles between child requests
sig_sequential_push <= sig_good_mmap_dbeat and -- MMap handshake qualified
sig_last_dbeat and -- last data beat of transfer
sig_next_sequential_reg;-- next queued command is sequential
-- to the current command
sig_push_dqual_reg <= (sig_sequential_push or
sig_dqual_reg_empty) and
sig_fifo_rd_cmd_valid and
sig_aposted_cntr_ready and
not(sig_calc_error_reg) and -- 13.1 addition => An error has not been propagated
not(wsc2mstr_halt_pipe); -- The Wr Status Controller is not
-- stalling the command execution pipe
sig_pop_dqual_reg <= not(sig_next_calc_error_reg) and
sig_get_next_dqual and
sig_dqual_reg_full ;
-- new for no bubbles between child requests
sig_clr_dqual_reg <= mmap_reset or
(sig_pop_dqual_reg and
not(sig_push_dqual_reg));
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_DQUAL_REG
--
-- Process Description:
-- This process implements a register for the Data
-- Control and qualifiers. It operates like a 1 deep Sync FIFO.
--
-------------------------------------------------------------
IMP_DQUAL_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (sig_clr_dqual_reg = '1') then
sig_next_tag_reg <= (others => '0');
sig_next_strt_strb_reg <= (others => '0');
sig_next_last_strb_reg <= (others => '0');
sig_next_eof_reg <= '0' ;
sig_next_sequential_reg <= '0' ;
sig_next_cmd_cmplt_reg <= '0' ;
sig_next_calc_error_reg <= '0' ;
sig_dqual_reg_empty <= '1' ;
sig_dqual_reg_full <= '0' ;
elsif (sig_push_dqual_reg = '1') then
sig_next_tag_reg <= sig_fifo_next_tag ;
sig_next_strt_strb_reg <= sig_sfhalt_next_strt_strb ;
sig_next_last_strb_reg <= sig_fifo_next_last_strb ;
sig_next_eof_reg <= sig_fifo_next_eof ;
sig_next_sequential_reg <= sig_fifo_next_sequential ;
sig_next_cmd_cmplt_reg <= sig_fifo_next_cmd_cmplt ;
sig_next_calc_error_reg <= sig_fifo_next_calc_error ;
sig_dqual_reg_empty <= '0';
sig_dqual_reg_full <= '1';
else
null; -- don't change state
end if;
end if;
end process IMP_DQUAL_REG;
-- Address LS Cntr logic --------------------------
sig_addr_lsb_reg <= STD_LOGIC_VECTOR(sig_ls_addr_cntr);
sig_addr_incr_unsgnd <= TO_UNSIGNED(ADDR_INCR_VALUE, C_SEL_ADDR_WIDTH);
sig_incr_ls_addr_cntr <= sig_good_mmap_dbeat;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_ADDR_LSB_CNTR
--
-- Process Description:
-- Implements the LS Address Counter used for controlling
-- the Write STRB DeMux during Burst transfers
--
-------------------------------------------------------------
DO_ADDR_LSB_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1' or
(sig_pop_dqual_reg = '1'and
sig_push_dqual_reg = '0')) then -- Clear the Counter
sig_ls_addr_cntr <= (others => '0');
elsif (sig_push_dqual_reg = '1') then -- Load the Counter
sig_ls_addr_cntr <= unsigned(sig_fifo_next_sadddr_lsb);
elsif (sig_incr_ls_addr_cntr = '1') then -- Increment the Counter
sig_ls_addr_cntr <= sig_ls_addr_cntr + sig_addr_incr_unsgnd;
else
null; -- Hold Current value
end if;
end if;
end process DO_ADDR_LSB_CNTR;
-- Address Posted Counter Logic --------------------------------------
sig_addr_chan_rdy <= not(sig_addr_posted_cntr_eq_0 or
sig_apc_going2zero) ; -- Gates data channel xfer handshake
sig_aposted_cntr_ready <= not(sig_addr_posted_cntr_max) ; -- Gates new command fetching
sig_no_posted_cmds <= sig_addr_posted_cntr_eq_0 ; -- Used for flushing cmds that are posted
sig_incr_addr_posted_cntr <= sig_addr_posted ;
sig_decr_addr_posted_cntr <= sig_last_mmap_dbeat_reg ;
sig_addr_posted_cntr_eq_0 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ZERO)
Else '0';
sig_addr_posted_cntr_max <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_MAX)
Else '0';
sig_addr_posted_cntr_eq_1 <= '1'
when (sig_addr_posted_cntr = ADDR_POSTED_ONE)
Else '0';
sig_apc_going2zero <= sig_addr_posted_cntr_eq_1 and
sig_decr_addr_posted_cntr and
not(sig_incr_addr_posted_cntr);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_ADDR_POSTED_FIFO_CNTR
--
-- Process Description:
-- This process implements a counter for the tracking
-- if an Address has been posted on the AXI address channel.
-- The Data Controller must wait for an address to be posted
-- before proceeding with the corresponding data transfer on
-- the Data Channel. The counter is also used to track flushing
-- operations where all transfers commited on the AXI Address
-- Channel have to be completed before a halt can occur.
-------------------------------------------------------------
IMP_ADDR_POSTED_FIFO_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_addr_posted_cntr <= ADDR_POSTED_ZERO;
elsif (sig_incr_addr_posted_cntr = '1' and
sig_decr_addr_posted_cntr = '0' and
sig_addr_posted_cntr_max = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr + ADDR_POSTED_ONE ;
elsif (sig_incr_addr_posted_cntr = '0' and
sig_decr_addr_posted_cntr = '1' and
sig_addr_posted_cntr_eq_0 = '0') then
sig_addr_posted_cntr <= sig_addr_posted_cntr - ADDR_POSTED_ONE ;
else
null; -- don't change state
end if;
end if;
end process IMP_ADDR_POSTED_FIFO_CNTR;
------- First/Middle/Last Dbeat detimination -------------------
sig_new_len_eq_0 <= '1'
When (sig_fifo_next_len = LEN_OF_ZERO)
else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_FIRST_MID_LAST
--
-- Process Description:
-- Implements the detection of the First/Mid/Last databeat of
-- a transfer.
--
-------------------------------------------------------------
DO_FIRST_MID_LAST : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
elsif (sig_ld_new_cmd = '1') then
sig_first_dbeat <= not(sig_new_len_eq_0);
sig_last_dbeat <= sig_new_len_eq_0;
sig_single_dbeat <= sig_new_len_eq_0;
Elsif (sig_dbeat_cntr_eq_1 = '1' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '1';
sig_single_dbeat <= '0';
Elsif (sig_dbeat_cntr_eq_0 = '0' and
sig_dbeat_cntr_eq_1 = '0' and
sig_good_mmap_dbeat = '1') Then
sig_first_dbeat <= '0';
sig_last_dbeat <= '0';
sig_single_dbeat <= '0';
else
null; -- hold current state
end if;
end if;
end process DO_FIRST_MID_LAST;
------- Data Controller Halted Indication -------------------------------
data2all_dcntlr_halted <= sig_no_posted_cmds or
sig_calc_error_reg;
------- Data Beat counter logic -------------------------------
sig_dbeat_cntr_int <= TO_INTEGER(sig_dbeat_cntr);
sig_dbeat_cntr_eq_0 <= '1'
when (sig_dbeat_cntr_int = 0)
Else '0';
sig_dbeat_cntr_eq_1 <= '1'
when (sig_dbeat_cntr_int = 1)
Else '0';
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: DO_DBEAT_CNTR
--
-- Process Description:
-- Implements the transfer data beat counter used to track
-- progress of the transfer.
--
-------------------------------------------------------------
DO_DBEAT_CNTR : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_dbeat_cntr <= (others => '0');
elsif (sig_ld_new_cmd = '1') then
sig_dbeat_cntr <= unsigned(sig_fifo_next_len);
Elsif (sig_good_mmap_dbeat = '1' and
sig_dbeat_cntr_eq_0 = '0') Then
sig_dbeat_cntr <= sig_dbeat_cntr-1;
else
null; -- Hold current state
end if;
end if;
end process DO_DBEAT_CNTR;
------- Soft Shutdown Logic -------------------------------
-- Formulate the soft shutdown complete flag
sig_data2rst_stop_cmplt <= (sig_halt_reg_dly3 and -- Normal Mode shutdown
sig_no_posted_cmds and
not(sig_calc_error_reg)) or
(sig_halt_reg_dly3 and -- Shutdown after error trap
sig_calc_error_reg);
-- Generate a gate signal to deassert the WVALID output
-- for 1 clock cycle after a WLAST is issued. This only
-- occurs when in soft shutdown mode.
sig_stop_wvalid <= (sig_last_mmap_dbeat_reg and
sig_halt_reg) or
sig_data2rst_stop_cmplt;
-- Assign the output port skid buf control for the
-- input Stream skid buffer
data2skid_halt <= sig_data2skid_halt;
-- Create a 1 clock wide pulse to tell the input
-- stream skid buffer to shut down.
sig_data2skid_halt <= sig_halt_reg_dly2 and
not(sig_halt_reg_dly3);
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG
--
-- Process Description:
-- Implements the flop for capturing the Halt request from
-- the Reset module.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg <= '0';
-- coverage off
elsif (rst2data_stop_request = '1') then
sig_halt_reg <= '1';
-- coverage on
else
null; -- Hold current State
end if;
end if;
end process IMP_HALT_REQ_REG;
-------------------------------------------------------------
-- Synchronous Process with Sync Reset
--
-- Label: IMP_HALT_REQ_REG_DLY
--
-- Process Description:
-- Implements the flops for delaying the halt request by 3
-- clocks to allow the Address Controller to halt before the
-- Data Contoller can safely indicate it has exhausted all
-- transfers committed to the AXI Address Channel by the Address
-- Controller.
--
-------------------------------------------------------------
IMP_HALT_REQ_REG_DLY : process (primary_aclk)
begin
if (primary_aclk'event and primary_aclk = '1') then
if (mmap_reset = '1') then
sig_halt_reg_dly1 <= '0';
sig_halt_reg_dly2 <= '0';
sig_halt_reg_dly3 <= '0';
else
sig_halt_reg_dly1 <= sig_halt_reg;
sig_halt_reg_dly2 <= sig_halt_reg_dly1;
sig_halt_reg_dly3 <= sig_halt_reg_dly2;
end if;
end if;
end process IMP_HALT_REQ_REG_DLY;
end implementation;
|
--*****************************************************************************
-- @Copyright 2010 by guyoubao, All rights reserved.
-- Module name : Pulse control
-- Call by :
-- Description :
-- IC : EP3C16F484C6
-- Version : A
-- Note: :
-- Author : Weibao Qiu
-- Date : 2010.08.28
-- Update :
--
--
--
--*****************************************************************************
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity pulse is
port
(
I_clk : in std_logic;
I_reset : in std_logic;
I_pulse_trig : in std_logic;
O_pulse : out std_logic_vector(3 downto 0)
);
end pulse;
architecture ARC_pulse of pulse is
signal S_cnt : std_logic_vector(7 downto 0);
signal s_case : std_logic_vector(1 downto 0);
signal s_pulse_buf : std_logic;
signal s_pulse : std_logic_vector(3 downto 0);
begin
O_pulse <= s_pulse;
process(I_reset,I_clk)
begin
if I_reset = '0' then
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '1';
s_pulse_buf <= '0';
elsif rising_edge(I_clk) then
s_pulse_buf <= I_pulse_trig;
case s_case is
when "00" =>
if(s_pulse_buf = '0' and I_pulse_trig = '1')then
s_case <= "01";
S_cnt <= S_cnt + '1';
else
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '1';
end if;
when "01" =>
S_cnt <= S_cnt + '1';
if(S_cnt >= 4 and S_cnt <= 5)then
s_pulse(1) <= '0';
else
s_pulse(1) <= '1';
end if;
if(S_cnt >= 2 and S_cnt <= 3)then
s_pulse(0) <= '1';
else
s_pulse(0) <= '0';
end if;
if(S_cnt = 0)then
s_case <= (others=>'0');
end if;
when others =>
s_case <= (others=>'0');
S_cnt <= (others=>'0');
s_pulse(0) <= '0';
s_pulse(1) <= '1';
end case;
end if;
end process;
end ARC_pulse; |
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Fri Jan 13 17:33:49 2017
-- Host : KLight-PC running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim
-- D:/Document/Verilog/VGA/VGA.srcs/sources_1/ip/bg_low_1/bg_low_sim_netlist.vhdl
-- Design : bg_low
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a35tcpg236-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_prim_wrapper_init is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_prim_wrapper_init : entity is "blk_mem_gen_prim_wrapper_init";
end bg_low_blk_mem_gen_prim_wrapper_init;
architecture STRUCTURE of bg_low_blk_mem_gen_prim_wrapper_init is
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\ : STD_LOGIC;
signal \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\ : STD_LOGIC;
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 16 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 2 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\ : STD_LOGIC_VECTOR ( 8 downto 0 );
attribute CLOCK_DOMAINS : string;
attribute CLOCK_DOMAINS of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "COMMON";
attribute box_type : string;
attribute box_type of \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\ : label is "PRIMITIVE";
begin
\DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram\: unisim.vcomponents.RAMB36E1
generic map(
DOA_REG => 1,
DOB_REG => 0,
EN_ECC_READ => false,
EN_ECC_WRITE => false,
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INITP_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
INITP_0F => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_19 => X"371D371D371D0400371D371D371D371D371D371D371D371D371D371D371D0000",
INIT_1A => X"371D371D371D371D371D371D00003F3F00003F3800003F3800003F383F381400",
INIT_1B => X"3F383F383F383F383F383F38371D371D371D371D371D371D371D371D371D371D",
INIT_1C => X"3E083E083F383F383F383E083F383E083F383F383F383F383F3800003F3F0001",
INIT_1D => X"3E083F383F383F3800003F3F3F3F3F383F383F383F383F383F383F383F383E08",
INIT_1E => X"3E083F383F383F383E083F383F383E083E083F383F383F383F383F383F383F38",
INIT_1F => X"3E0800013E083E083F383F383E083F383F383E083F3800003F3F00013F380001",
INIT_20 => X"3F383F3800003F3F00013F303F383F383F383F383E083F383E083F383F383E08",
INIT_21 => X"3F383F3F3F383F383F3F3F383F383F383F383F383F3F3F383F383F383F3F3F38",
INIT_22 => X"3F383F383F303E083F303F383F383E083F383F3F3F3F000114003F383F3F3F38",
INIT_23 => X"00003F3F00003F383F383F383F303E083F303F383F303F383F383E083F383F38",
INIT_24 => X"3F383F383F303F303F383F303F303F383F303F303F303F383F303F383F303F38",
INIT_25 => X"000100000001000000000000000000003F3F00003F303F383F303F303F383F38",
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INIT_28 => X"3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F",
INIT_29 => X"3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F3F",
INIT_2A => X"3E083F3F3E083F383E083F383F383F383E083F3F3F3F3F383F3F3F3F3F3F3F3F",
INIT_2B => X"3F3F3F383F3F3F383E083F3F3E083F383E083F383F383F383E083F3F3F3F3F38",
INIT_2C => X"3F383F383F383F383F3F3F383F383F383F383F383F3F3F383F383F383F383F38",
INIT_2D => X"3F383F3F3F383F383F3F3F383E083F383F3F3F383F383F383F383F383F3F3F38",
INIT_2E => X"3F383F383F383F383F383F3F3F383F383F3F3F383E083F383F383F383F383F38",
INIT_2F => X"3F3F3F383F383F383F383F3F3F383F3F3F383E083F3814003F3F3F383E083F38",
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INIT_32 => X"3F383E083F3F3F3F3F3F3F383F3F3F383F383F3F3E083F383E083F383F383F38",
INIT_33 => X"3F383F3F3F383E083F383E083F3F3F3F3F3F3F383F3F3F383F383F3F3F383E08",
INIT_34 => X"3F383F383F3F14003F3F3E083F383F383F383F383F3F3F3F3F383F383F3F1400",
INIT_35 => X"3E083F3F3F383F383F383F383F3F14003F3F3E083F383F383F383F383F3F3F3F",
INIT_36 => X"3E083F383F383F383E083F3F3F383F383F383F383F3F3F383E083F383F383F38",
INIT_37 => X"3F383F3F3F3F3F383F3F3F383F383F383F383F3F3F383F3F3F383F383F3F3F38",
INIT_38 => X"3F383F3F3F3F3F3F3F383F3F3F3F3F3F3F3F3F383F383F3F3F383F3F3F3F3F3F",
INIT_39 => X"3F383F3F000D3F383F38000D3F383F3F3F3F3F3F3F3F3F3F3F383F3F3F3F3F38",
INIT_3A => X"3F3F3F3F3F3F3F3F3F3F3F383F3F3F383F38000D3F383F3F3F3F3F3F3F3F3F3F",
INIT_3B => X"3E083F3F3F38000D371D3F3F3F3F3F3F3F3F1D373F3F3F383E083E083F383F3F",
INIT_3C => X"3F383F3F3F383F383F3F3F3F3F3F3F3F3F383F3F000D3F383F38000D3F3F3F38",
INIT_3D => X"3F3F3E083F383F3F3F383F3F3F383F38233F3F3F3F3F000D3F383F3F3F3F3F38",
INIT_3E => X"3F38233F3E083E08233F3E083F38233F3F383E08233F3F3F3F38000D3E083E08",
INIT_3F => X"3E08233F3E083F38233F3F383E08233F233F3F383F38233F3F383E08000D3F3F",
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INIT_41 => X"233F3F383F3F371D3F383F38000D3F383F3F233F3F383F38233F3F383F3F233F",
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INIT_43 => X"3F38233F3F383F3F3F3F220F220F233F233F3F38371D233F3F38233F371D3F3F",
INIT_44 => X"000000000000000000000000000000000000000000000000233F3F38371D233F",
INIT_45 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_59 => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_5B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_5C => X"0000000000000000000000000000000000000000000000000000000000000000",
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INIT_64 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_65 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_66 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_67 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_68 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_69 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_6F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_70 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_71 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_72 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_73 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_74 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_75 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_76 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_77 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_78 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_79 => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7A => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7B => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7C => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7D => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7E => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_7F => X"0000000000000000000000000000000000000000000000000000000000000000",
INIT_A => X"000000000",
INIT_B => X"000000000",
INIT_FILE => "NONE",
IS_CLKARDCLK_INVERTED => '0',
IS_CLKBWRCLK_INVERTED => '0',
IS_ENARDEN_INVERTED => '0',
IS_ENBWREN_INVERTED => '0',
IS_RSTRAMARSTRAM_INVERTED => '0',
IS_RSTRAMB_INVERTED => '0',
IS_RSTREGARSTREG_INVERTED => '0',
IS_RSTREGB_INVERTED => '0',
RAM_EXTENSION_A => "NONE",
RAM_EXTENSION_B => "NONE",
RAM_MODE => "TDP",
RDADDR_COLLISION_HWCONFIG => "PERFORMANCE",
READ_WIDTH_A => 18,
READ_WIDTH_B => 18,
RSTREG_PRIORITY_A => "REGCE",
RSTREG_PRIORITY_B => "REGCE",
SIM_COLLISION_CHECK => "ALL",
SIM_DEVICE => "7SERIES",
SRVAL_A => X"000000000",
SRVAL_B => X"000000000",
WRITE_MODE_A => "WRITE_FIRST",
WRITE_MODE_B => "WRITE_FIRST",
WRITE_WIDTH_A => 18,
WRITE_WIDTH_B => 18
)
port map (
ADDRARDADDR(15) => '1',
ADDRARDADDR(14 downto 4) => addra(10 downto 0),
ADDRARDADDR(3 downto 0) => B"1111",
ADDRBWRADDR(15 downto 0) => B"0000000000000000",
CASCADEINA => '0',
CASCADEINB => '0',
CASCADEOUTA => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTA_UNCONNECTED\,
CASCADEOUTB => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_CASCADEOUTB_UNCONNECTED\,
CLKARDCLK => clka,
CLKBWRCLK => clka,
DBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DBITERR_UNCONNECTED\,
DIADI(31 downto 14) => B"000000000000000000",
DIADI(13 downto 8) => dina(11 downto 6),
DIADI(7 downto 6) => B"00",
DIADI(5 downto 0) => dina(5 downto 0),
DIBDI(31 downto 0) => B"00000000000000000000000000000000",
DIPADIP(3 downto 0) => B"0000",
DIPBDIP(3 downto 0) => B"0000",
DOADO(31 downto 16) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOADO_UNCONNECTED\(31 downto 16),
DOADO(15) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_37\,
DOADO(14) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_38\,
DOADO(13 downto 8) => douta(11 downto 6),
DOADO(7) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_45\,
DOADO(6) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_46\,
DOADO(5 downto 0) => douta(5 downto 0),
DOBDO(31 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOBDO_UNCONNECTED\(31 downto 0),
DOPADOP(3 downto 2) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPADOP_UNCONNECTED\(3 downto 2),
DOPADOP(1) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_87\,
DOPADOP(0) => \DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_n_88\,
DOPBDOP(3 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_DOPBDOP_UNCONNECTED\(3 downto 0),
ECCPARITY(7 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_ECCPARITY_UNCONNECTED\(7 downto 0),
ENARDEN => '1',
ENBWREN => '0',
INJECTDBITERR => '0',
INJECTSBITERR => '0',
RDADDRECC(8 downto 0) => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_RDADDRECC_UNCONNECTED\(8 downto 0),
REGCEAREGCE => '1',
REGCEB => '0',
RSTRAMARSTRAM => '0',
RSTRAMB => '0',
RSTREGARSTREG => '0',
RSTREGB => '0',
SBITERR => \NLW_DEVICE_7SERIES.NO_BMM_INFO.SP.SIMPLE_PRIM36.ram_SBITERR_UNCONNECTED\,
WEA(3) => wea(0),
WEA(2) => wea(0),
WEA(1) => wea(0),
WEA(0) => wea(0),
WEBWE(7 downto 0) => B"00000000"
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_prim_width is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_prim_width : entity is "blk_mem_gen_prim_width";
end bg_low_blk_mem_gen_prim_width;
architecture STRUCTURE of bg_low_blk_mem_gen_prim_width is
begin
\prim_init.ram\: entity work.bg_low_blk_mem_gen_prim_wrapper_init
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_generic_cstr is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_generic_cstr : entity is "blk_mem_gen_generic_cstr";
end bg_low_blk_mem_gen_generic_cstr;
architecture STRUCTURE of bg_low_blk_mem_gen_generic_cstr is
begin
\ramloop[0].ram.r\: entity work.bg_low_blk_mem_gen_prim_width
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_top is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_top : entity is "blk_mem_gen_top";
end bg_low_blk_mem_gen_top;
architecture STRUCTURE of bg_low_blk_mem_gen_top is
begin
\valid.cstr\: entity work.bg_low_blk_mem_gen_generic_cstr
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_v8_3_5_synth is
port (
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clka : in STD_LOGIC;
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
wea : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_v8_3_5_synth : entity is "blk_mem_gen_v8_3_5_synth";
end bg_low_blk_mem_gen_v8_3_5_synth;
architecture STRUCTURE of bg_low_blk_mem_gen_v8_3_5_synth is
begin
\gnbram.gnativebmg.native_blk_mem_gen\: entity work.bg_low_blk_mem_gen_top
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low_blk_mem_gen_v8_3_5 is
port (
clka : in STD_LOGIC;
rsta : in STD_LOGIC;
ena : in STD_LOGIC;
regcea : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 );
clkb : in STD_LOGIC;
rstb : in STD_LOGIC;
enb : in STD_LOGIC;
regceb : in STD_LOGIC;
web : in STD_LOGIC_VECTOR ( 0 to 0 );
addrb : in STD_LOGIC_VECTOR ( 10 downto 0 );
dinb : in STD_LOGIC_VECTOR ( 11 downto 0 );
doutb : out STD_LOGIC_VECTOR ( 11 downto 0 );
injectsbiterr : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
eccpipece : in STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 );
sleep : in STD_LOGIC;
deepsleep : in STD_LOGIC;
shutdown : in STD_LOGIC;
rsta_busy : out STD_LOGIC;
rstb_busy : out STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 11 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_axi_injectsbiterr : in STD_LOGIC;
s_axi_injectdbiterr : in STD_LOGIC;
s_axi_sbiterr : out STD_LOGIC;
s_axi_dbiterr : out STD_LOGIC;
s_axi_rdaddrecc : out STD_LOGIC_VECTOR ( 10 downto 0 )
);
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of bg_low_blk_mem_gen_v8_3_5 : entity is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of bg_low_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of bg_low_blk_mem_gen_v8_3_5 : entity is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of bg_low_blk_mem_gen_v8_3_5 : entity is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of bg_low_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of bg_low_blk_mem_gen_v8_3_5 : entity is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of bg_low_blk_mem_gen_v8_3_5 : entity is "Estimated Power for IP : 2.5912999999999999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of bg_low_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of bg_low_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of bg_low_blk_mem_gen_v8_3_5 : entity is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of bg_low_blk_mem_gen_v8_3_5 : entity is "bg_low.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of bg_low_blk_mem_gen_v8_3_5 : entity is "bg_low.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of bg_low_blk_mem_gen_v8_3_5 : entity is 1092;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of bg_low_blk_mem_gen_v8_3_5 : entity is 1092;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of bg_low_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of bg_low_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of bg_low_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of bg_low_blk_mem_gen_v8_3_5 : entity is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of bg_low_blk_mem_gen_v8_3_5 : entity is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of bg_low_blk_mem_gen_v8_3_5 : entity is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of bg_low_blk_mem_gen_v8_3_5 : entity is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of bg_low_blk_mem_gen_v8_3_5 : entity is 1092;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of bg_low_blk_mem_gen_v8_3_5 : entity is 1092;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of bg_low_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of bg_low_blk_mem_gen_v8_3_5 : entity is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of bg_low_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of bg_low_blk_mem_gen_v8_3_5 : entity is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of bg_low_blk_mem_gen_v8_3_5 : entity is "artix7";
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bg_low_blk_mem_gen_v8_3_5 : entity is "blk_mem_gen_v8_3_5";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_low_blk_mem_gen_v8_3_5 : entity is "yes";
end bg_low_blk_mem_gen_v8_3_5;
architecture STRUCTURE of bg_low_blk_mem_gen_v8_3_5 is
signal \<const0>\ : STD_LOGIC;
begin
dbiterr <= \<const0>\;
doutb(11) <= \<const0>\;
doutb(10) <= \<const0>\;
doutb(9) <= \<const0>\;
doutb(8) <= \<const0>\;
doutb(7) <= \<const0>\;
doutb(6) <= \<const0>\;
doutb(5) <= \<const0>\;
doutb(4) <= \<const0>\;
doutb(3) <= \<const0>\;
doutb(2) <= \<const0>\;
doutb(1) <= \<const0>\;
doutb(0) <= \<const0>\;
rdaddrecc(10) <= \<const0>\;
rdaddrecc(9) <= \<const0>\;
rdaddrecc(8) <= \<const0>\;
rdaddrecc(7) <= \<const0>\;
rdaddrecc(6) <= \<const0>\;
rdaddrecc(5) <= \<const0>\;
rdaddrecc(4) <= \<const0>\;
rdaddrecc(3) <= \<const0>\;
rdaddrecc(2) <= \<const0>\;
rdaddrecc(1) <= \<const0>\;
rdaddrecc(0) <= \<const0>\;
rsta_busy <= \<const0>\;
rstb_busy <= \<const0>\;
s_axi_arready <= \<const0>\;
s_axi_awready <= \<const0>\;
s_axi_bid(3) <= \<const0>\;
s_axi_bid(2) <= \<const0>\;
s_axi_bid(1) <= \<const0>\;
s_axi_bid(0) <= \<const0>\;
s_axi_bresp(1) <= \<const0>\;
s_axi_bresp(0) <= \<const0>\;
s_axi_bvalid <= \<const0>\;
s_axi_dbiterr <= \<const0>\;
s_axi_rdaddrecc(10) <= \<const0>\;
s_axi_rdaddrecc(9) <= \<const0>\;
s_axi_rdaddrecc(8) <= \<const0>\;
s_axi_rdaddrecc(7) <= \<const0>\;
s_axi_rdaddrecc(6) <= \<const0>\;
s_axi_rdaddrecc(5) <= \<const0>\;
s_axi_rdaddrecc(4) <= \<const0>\;
s_axi_rdaddrecc(3) <= \<const0>\;
s_axi_rdaddrecc(2) <= \<const0>\;
s_axi_rdaddrecc(1) <= \<const0>\;
s_axi_rdaddrecc(0) <= \<const0>\;
s_axi_rdata(11) <= \<const0>\;
s_axi_rdata(10) <= \<const0>\;
s_axi_rdata(9) <= \<const0>\;
s_axi_rdata(8) <= \<const0>\;
s_axi_rdata(7) <= \<const0>\;
s_axi_rdata(6) <= \<const0>\;
s_axi_rdata(5) <= \<const0>\;
s_axi_rdata(4) <= \<const0>\;
s_axi_rdata(3) <= \<const0>\;
s_axi_rdata(2) <= \<const0>\;
s_axi_rdata(1) <= \<const0>\;
s_axi_rdata(0) <= \<const0>\;
s_axi_rid(3) <= \<const0>\;
s_axi_rid(2) <= \<const0>\;
s_axi_rid(1) <= \<const0>\;
s_axi_rid(0) <= \<const0>\;
s_axi_rlast <= \<const0>\;
s_axi_rresp(1) <= \<const0>\;
s_axi_rresp(0) <= \<const0>\;
s_axi_rvalid <= \<const0>\;
s_axi_sbiterr <= \<const0>\;
s_axi_wready <= \<const0>\;
sbiterr <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_blk_mem_gen: entity work.bg_low_blk_mem_gen_v8_3_5_synth
port map (
addra(10 downto 0) => addra(10 downto 0),
clka => clka,
dina(11 downto 0) => dina(11 downto 0),
douta(11 downto 0) => douta(11 downto 0),
wea(0) => wea(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bg_low is
port (
clka : in STD_LOGIC;
wea : in STD_LOGIC_VECTOR ( 0 to 0 );
addra : in STD_LOGIC_VECTOR ( 10 downto 0 );
dina : in STD_LOGIC_VECTOR ( 11 downto 0 );
douta : out STD_LOGIC_VECTOR ( 11 downto 0 )
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bg_low : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bg_low : entity is "bg_low,blk_mem_gen_v8_3_5,{}";
attribute downgradeipidentifiedwarnings : string;
attribute downgradeipidentifiedwarnings of bg_low : entity is "yes";
attribute x_core_info : string;
attribute x_core_info of bg_low : entity is "blk_mem_gen_v8_3_5,Vivado 2016.4";
end bg_low;
architecture STRUCTURE of bg_low is
signal NLW_U0_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rsta_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_rstb_busy_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_arready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_awready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_bvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_dbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rlast_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_rvalid_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_s_axi_wready_UNCONNECTED : STD_LOGIC;
signal NLW_U0_sbiterr_UNCONNECTED : STD_LOGIC;
signal NLW_U0_doutb_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_bid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_bresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_U0_s_axi_rdaddrecc_UNCONNECTED : STD_LOGIC_VECTOR ( 10 downto 0 );
signal NLW_U0_s_axi_rdata_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_U0_s_axi_rid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_U0_s_axi_rresp_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute C_ADDRA_WIDTH : integer;
attribute C_ADDRA_WIDTH of U0 : label is 11;
attribute C_ADDRB_WIDTH : integer;
attribute C_ADDRB_WIDTH of U0 : label is 11;
attribute C_ALGORITHM : integer;
attribute C_ALGORITHM of U0 : label is 1;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of U0 : label is 4;
attribute C_AXI_SLAVE_TYPE : integer;
attribute C_AXI_SLAVE_TYPE of U0 : label is 0;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of U0 : label is 1;
attribute C_BYTE_SIZE : integer;
attribute C_BYTE_SIZE of U0 : label is 9;
attribute C_COMMON_CLK : integer;
attribute C_COMMON_CLK of U0 : label is 0;
attribute C_COUNT_18K_BRAM : string;
attribute C_COUNT_18K_BRAM of U0 : label is "0";
attribute C_COUNT_36K_BRAM : string;
attribute C_COUNT_36K_BRAM of U0 : label is "1";
attribute C_CTRL_ECC_ALGO : string;
attribute C_CTRL_ECC_ALGO of U0 : label is "NONE";
attribute C_DEFAULT_DATA : string;
attribute C_DEFAULT_DATA of U0 : label is "0";
attribute C_DISABLE_WARN_BHV_COLL : integer;
attribute C_DISABLE_WARN_BHV_COLL of U0 : label is 0;
attribute C_DISABLE_WARN_BHV_RANGE : integer;
attribute C_DISABLE_WARN_BHV_RANGE of U0 : label is 0;
attribute C_ELABORATION_DIR : string;
attribute C_ELABORATION_DIR of U0 : label is "./";
attribute C_ENABLE_32BIT_ADDRESS : integer;
attribute C_ENABLE_32BIT_ADDRESS of U0 : label is 0;
attribute C_EN_DEEPSLEEP_PIN : integer;
attribute C_EN_DEEPSLEEP_PIN of U0 : label is 0;
attribute C_EN_ECC_PIPE : integer;
attribute C_EN_ECC_PIPE of U0 : label is 0;
attribute C_EN_RDADDRA_CHG : integer;
attribute C_EN_RDADDRA_CHG of U0 : label is 0;
attribute C_EN_RDADDRB_CHG : integer;
attribute C_EN_RDADDRB_CHG of U0 : label is 0;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of U0 : label is 0;
attribute C_EN_SHUTDOWN_PIN : integer;
attribute C_EN_SHUTDOWN_PIN of U0 : label is 0;
attribute C_EN_SLEEP_PIN : integer;
attribute C_EN_SLEEP_PIN of U0 : label is 0;
attribute C_EST_POWER_SUMMARY : string;
attribute C_EST_POWER_SUMMARY of U0 : label is "Estimated Power for IP : 2.5912999999999999 mW";
attribute C_FAMILY : string;
attribute C_FAMILY of U0 : label is "artix7";
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of U0 : label is 0;
attribute C_HAS_ENA : integer;
attribute C_HAS_ENA of U0 : label is 0;
attribute C_HAS_ENB : integer;
attribute C_HAS_ENB of U0 : label is 0;
attribute C_HAS_INJECTERR : integer;
attribute C_HAS_INJECTERR of U0 : label is 0;
attribute C_HAS_MEM_OUTPUT_REGS_A : integer;
attribute C_HAS_MEM_OUTPUT_REGS_A of U0 : label is 1;
attribute C_HAS_MEM_OUTPUT_REGS_B : integer;
attribute C_HAS_MEM_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_A : integer;
attribute C_HAS_MUX_OUTPUT_REGS_A of U0 : label is 0;
attribute C_HAS_MUX_OUTPUT_REGS_B : integer;
attribute C_HAS_MUX_OUTPUT_REGS_B of U0 : label is 0;
attribute C_HAS_REGCEA : integer;
attribute C_HAS_REGCEA of U0 : label is 0;
attribute C_HAS_REGCEB : integer;
attribute C_HAS_REGCEB of U0 : label is 0;
attribute C_HAS_RSTA : integer;
attribute C_HAS_RSTA of U0 : label is 0;
attribute C_HAS_RSTB : integer;
attribute C_HAS_RSTB of U0 : label is 0;
attribute C_HAS_SOFTECC_INPUT_REGS_A : integer;
attribute C_HAS_SOFTECC_INPUT_REGS_A of U0 : label is 0;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B : integer;
attribute C_HAS_SOFTECC_OUTPUT_REGS_B of U0 : label is 0;
attribute C_INITA_VAL : string;
attribute C_INITA_VAL of U0 : label is "0";
attribute C_INITB_VAL : string;
attribute C_INITB_VAL of U0 : label is "0";
attribute C_INIT_FILE : string;
attribute C_INIT_FILE of U0 : label is "bg_low.mem";
attribute C_INIT_FILE_NAME : string;
attribute C_INIT_FILE_NAME of U0 : label is "bg_low.mif";
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of U0 : label is 0;
attribute C_LOAD_INIT_FILE : integer;
attribute C_LOAD_INIT_FILE of U0 : label is 1;
attribute C_MEM_TYPE : integer;
attribute C_MEM_TYPE of U0 : label is 0;
attribute C_MUX_PIPELINE_STAGES : integer;
attribute C_MUX_PIPELINE_STAGES of U0 : label is 0;
attribute C_PRIM_TYPE : integer;
attribute C_PRIM_TYPE of U0 : label is 1;
attribute C_READ_DEPTH_A : integer;
attribute C_READ_DEPTH_A of U0 : label is 1092;
attribute C_READ_DEPTH_B : integer;
attribute C_READ_DEPTH_B of U0 : label is 1092;
attribute C_READ_WIDTH_A : integer;
attribute C_READ_WIDTH_A of U0 : label is 12;
attribute C_READ_WIDTH_B : integer;
attribute C_READ_WIDTH_B of U0 : label is 12;
attribute C_RSTRAM_A : integer;
attribute C_RSTRAM_A of U0 : label is 0;
attribute C_RSTRAM_B : integer;
attribute C_RSTRAM_B of U0 : label is 0;
attribute C_RST_PRIORITY_A : string;
attribute C_RST_PRIORITY_A of U0 : label is "CE";
attribute C_RST_PRIORITY_B : string;
attribute C_RST_PRIORITY_B of U0 : label is "CE";
attribute C_SIM_COLLISION_CHECK : string;
attribute C_SIM_COLLISION_CHECK of U0 : label is "ALL";
attribute C_USE_BRAM_BLOCK : integer;
attribute C_USE_BRAM_BLOCK of U0 : label is 0;
attribute C_USE_BYTE_WEA : integer;
attribute C_USE_BYTE_WEA of U0 : label is 0;
attribute C_USE_BYTE_WEB : integer;
attribute C_USE_BYTE_WEB of U0 : label is 0;
attribute C_USE_DEFAULT_DATA : integer;
attribute C_USE_DEFAULT_DATA of U0 : label is 0;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of U0 : label is 0;
attribute C_USE_SOFTECC : integer;
attribute C_USE_SOFTECC of U0 : label is 0;
attribute C_USE_URAM : integer;
attribute C_USE_URAM of U0 : label is 0;
attribute C_WEA_WIDTH : integer;
attribute C_WEA_WIDTH of U0 : label is 1;
attribute C_WEB_WIDTH : integer;
attribute C_WEB_WIDTH of U0 : label is 1;
attribute C_WRITE_DEPTH_A : integer;
attribute C_WRITE_DEPTH_A of U0 : label is 1092;
attribute C_WRITE_DEPTH_B : integer;
attribute C_WRITE_DEPTH_B of U0 : label is 1092;
attribute C_WRITE_MODE_A : string;
attribute C_WRITE_MODE_A of U0 : label is "WRITE_FIRST";
attribute C_WRITE_MODE_B : string;
attribute C_WRITE_MODE_B of U0 : label is "WRITE_FIRST";
attribute C_WRITE_WIDTH_A : integer;
attribute C_WRITE_WIDTH_A of U0 : label is 12;
attribute C_WRITE_WIDTH_B : integer;
attribute C_WRITE_WIDTH_B of U0 : label is 12;
attribute C_XDEVICEFAMILY : string;
attribute C_XDEVICEFAMILY of U0 : label is "artix7";
attribute downgradeipidentifiedwarnings of U0 : label is "yes";
begin
U0: entity work.bg_low_blk_mem_gen_v8_3_5
port map (
addra(10 downto 0) => addra(10 downto 0),
addrb(10 downto 0) => B"00000000000",
clka => clka,
clkb => '0',
dbiterr => NLW_U0_dbiterr_UNCONNECTED,
deepsleep => '0',
dina(11 downto 0) => dina(11 downto 0),
dinb(11 downto 0) => B"000000000000",
douta(11 downto 0) => douta(11 downto 0),
doutb(11 downto 0) => NLW_U0_doutb_UNCONNECTED(11 downto 0),
eccpipece => '0',
ena => '0',
enb => '0',
injectdbiterr => '0',
injectsbiterr => '0',
rdaddrecc(10 downto 0) => NLW_U0_rdaddrecc_UNCONNECTED(10 downto 0),
regcea => '0',
regceb => '0',
rsta => '0',
rsta_busy => NLW_U0_rsta_busy_UNCONNECTED,
rstb => '0',
rstb_busy => NLW_U0_rstb_busy_UNCONNECTED,
s_aclk => '0',
s_aresetn => '0',
s_axi_araddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_arburst(1 downto 0) => B"00",
s_axi_arid(3 downto 0) => B"0000",
s_axi_arlen(7 downto 0) => B"00000000",
s_axi_arready => NLW_U0_s_axi_arready_UNCONNECTED,
s_axi_arsize(2 downto 0) => B"000",
s_axi_arvalid => '0',
s_axi_awaddr(31 downto 0) => B"00000000000000000000000000000000",
s_axi_awburst(1 downto 0) => B"00",
s_axi_awid(3 downto 0) => B"0000",
s_axi_awlen(7 downto 0) => B"00000000",
s_axi_awready => NLW_U0_s_axi_awready_UNCONNECTED,
s_axi_awsize(2 downto 0) => B"000",
s_axi_awvalid => '0',
s_axi_bid(3 downto 0) => NLW_U0_s_axi_bid_UNCONNECTED(3 downto 0),
s_axi_bready => '0',
s_axi_bresp(1 downto 0) => NLW_U0_s_axi_bresp_UNCONNECTED(1 downto 0),
s_axi_bvalid => NLW_U0_s_axi_bvalid_UNCONNECTED,
s_axi_dbiterr => NLW_U0_s_axi_dbiterr_UNCONNECTED,
s_axi_injectdbiterr => '0',
s_axi_injectsbiterr => '0',
s_axi_rdaddrecc(10 downto 0) => NLW_U0_s_axi_rdaddrecc_UNCONNECTED(10 downto 0),
s_axi_rdata(11 downto 0) => NLW_U0_s_axi_rdata_UNCONNECTED(11 downto 0),
s_axi_rid(3 downto 0) => NLW_U0_s_axi_rid_UNCONNECTED(3 downto 0),
s_axi_rlast => NLW_U0_s_axi_rlast_UNCONNECTED,
s_axi_rready => '0',
s_axi_rresp(1 downto 0) => NLW_U0_s_axi_rresp_UNCONNECTED(1 downto 0),
s_axi_rvalid => NLW_U0_s_axi_rvalid_UNCONNECTED,
s_axi_sbiterr => NLW_U0_s_axi_sbiterr_UNCONNECTED,
s_axi_wdata(11 downto 0) => B"000000000000",
s_axi_wlast => '0',
s_axi_wready => NLW_U0_s_axi_wready_UNCONNECTED,
s_axi_wstrb(0) => '0',
s_axi_wvalid => '0',
sbiterr => NLW_U0_sbiterr_UNCONNECTED,
shutdown => '0',
sleep => '0',
wea(0) => wea(0),
web(0) => '0'
);
end STRUCTURE;
|
-- -----------------------------------------------------------------------
--
-- This is a table driven 65Cx2 core by A.Daly
-- This is a derivative of the excellent FPGA64 core see below
--
-- -----------------------------------------------------------------------
-- Copyright 2005-2008 by Peter Wendrich ([email protected])
-- http://www.syntiac.com/fpga64.html
-- -----------------------------------------------------------------------
library IEEE;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
entity R65C02 is
port (
reset : in std_logic;
clk : in std_logic;
enable : in std_logic;
nmi_n : in std_logic;
irq_n : in std_logic;
di : in unsigned(7 downto 0);
do : out unsigned(7 downto 0);
addr : out unsigned(15 downto 0);
nwe : out std_logic;
sync : out std_logic;
sync_irq : out std_logic;
-- 6502 registers (MSB) PC, SP, P, Y, X, A (LSB)
Regs : out std_logic_vector(63 downto 0)
);
end R65C02;
-- Store Zp (3) => fetch, cycle2, cycleEnd
-- Store Zp,x (4) => fetch, cycle2, preWrite, cycleEnd
-- Read Zp,x (4) => fetch, cycle2, cycleRead, cycleRead2
-- Rmw Zp,x (6) => fetch, cycle2, cycleRead, cycleRead2, cycleRmw, cycleEnd
-- Store Abs (4) => fetch, cycle2, cycle3, cycleEnd
-- Store Abs,x (5) => fetch, cycle2, cycle3, preWrite, cycleEnd
-- Rts (6) => fetch, cycle2, cycle3, cycleRead, cycleJump, cycleIncrEnd
-- Rti (6) => fetch, cycle2, stack1, stack2, stack3, cycleJump
-- Jsr (6) => fetch, cycle2, .. cycle5, cycle6, cycleJump
-- Jmp abs (3) => fetch, cycle2, cycleJump
-- Jmp (ind) (6) => fetch, cycle2, cycle3, cycleRead, cycleRead2, cycleJump
-- Jmp (ind,x) (6) => fetch, cycle2, cycle3, cycleRead, cycleRead2, cycleJump
-- Brk (7) => fetch, cycle2, stack2, stack3, stack4, cycleRead2, cycleJump
-- -----------------------------------------------------------------------
architecture Behavioral of R65C02 is
-- Statemachine
type cpuCycles is (
opcodeFetch, -- New opcode is read and registers updated
cycle2,
cycle3,
cyclePreIndirect,
cycleIndirect,
cycleBranchTaken,
cycleBranchPage,
cyclePreRead, -- Cycle before read while doing zeropage indexed addressing.
cycleRead, -- Read cycle
cycleRead2, -- Second read cycle after page-boundary crossing.
cycleRmw, -- Calculate ALU output for read-modify-write instr.
cyclePreWrite, -- Cycle before write when doing indexed addressing.
cycleWrite, -- Write cycle for zeropage or absolute addressing.
cycleStack1,
cycleStack2,
cycleStack3,
cycleStack4,
cycleJump, -- Last cycle of Jsr, Jmp. Next fetch address is target addr.
cycleEnd
);
signal theCpuCycle : cpuCycles;
signal nextCpuCycle : cpuCycles;
signal updateRegisters : boolean;
signal processIrq : std_logic;
signal nmiReg : std_logic;
signal nmiEdge : std_logic;
signal irqReg : std_logic; -- Delay IRQ input with one clock cycle.
signal soReg : std_logic; -- SO pin edge detection
-- Opcode decoding
constant opcUpdateA : integer := 0;
constant opcUpdateX : integer := 1;
constant opcUpdateY : integer := 2;
constant opcUpdateS : integer := 3;
constant opcUpdateN : integer := 4;
constant opcUpdateV : integer := 5;
constant opcUpdateD : integer := 6;
constant opcUpdateI : integer := 7;
constant opcUpdateZ : integer := 8;
constant opcUpdateC : integer := 9;
constant opcSecondByte : integer := 10;
constant opcAbsolute : integer := 11;
constant opcZeroPage : integer := 12;
constant opcIndirect : integer := 13;
constant opcStackAddr : integer := 14; -- Push/Pop address
constant opcStackData : integer := 15; -- Push/Pop status/data
constant opcJump : integer := 16;
constant opcBranch : integer := 17;
constant indexX : integer := 18;
constant indexY : integer := 19;
constant opcStackUp : integer := 20;
constant opcWrite : integer := 21;
constant opcRmw : integer := 22;
constant opcIncrAfter : integer := 23; -- Insert extra cycle to increment PC (RTS)
constant opcRti : integer := 24;
constant opcIRQ : integer := 25;
constant opcInA : integer := 26;
constant opcInBrk : integer := 27;
constant opcInX : integer := 28;
constant opcInY : integer := 29;
constant opcInS : integer := 30;
constant opcInT : integer := 31;
constant opcInH : integer := 32;
constant opcInClear : integer := 33;
constant aluMode1From : integer := 34;
--
constant aluMode1To : integer := 37;
constant aluMode2From : integer := 38;
--
constant aluMode2To : integer := 40;
constant opcInCmp : integer := 41;
constant opcInCpx : integer := 42;
constant opcInCpy : integer := 43;
subtype addrDef is unsigned(0 to 15);
--
-- is Interrupt -----------------+
-- instruction is RTI ----------------+|
-- PC++ on last cycle (RTS) ---------------+||
-- RMW --------------+|||
-- Write -------------+||||
-- Pop/Stack up -------------+|||||
-- Branch ---------+ ||||||
-- Jump ----------+| ||||||
-- Push or Pop data -------+|| ||||||
-- Push or Pop addr ------+||| ||||||
-- Indirect -----+|||| ||||||
-- ZeroPage ----+||||| ||||||
-- Absolute ---+|||||| ||||||
-- PC++ on cycle2 --+||||||| ||||||
-- |AZI||JBXY|WM|||
constant immediate : addrDef := "1000000000000000";
constant implied : addrDef := "0000000000000000";
-- Zero page
constant readZp : addrDef := "1010000000000000";
constant writeZp : addrDef := "1010000000010000";
constant rmwZp : addrDef := "1010000000001000";
-- Zero page indexed
constant readZpX : addrDef := "1010000010000000";
constant writeZpX : addrDef := "1010000010010000";
constant rmwZpX : addrDef := "1010000010001000";
constant readZpY : addrDef := "1010000001000000";
constant writeZpY : addrDef := "1010000001010000";
constant rmwZpY : addrDef := "1010000001001000";
-- Zero page indirect
constant readIndX : addrDef := "1001000010000000";
constant writeIndX : addrDef := "1001000010010000";
constant rmwIndX : addrDef := "1001000010001000";
constant readIndY : addrDef := "1001000001000000";
constant writeIndY : addrDef := "1001000001010000";
constant rmwIndY : addrDef := "1001000001001000";
constant rmwInd : addrDef := "1001000000001000";
constant readInd : addrDef := "1001000000000000";
constant writeInd : addrDef := "1001000000010000";
-- |AZI||JBXY|WM||
-- Absolute
constant readAbs : addrDef := "1100000000000000";
constant writeAbs : addrDef := "1100000000010000";
constant rmwAbs : addrDef := "1100000000001000";
constant readAbsX : addrDef := "1100000010000000";
constant writeAbsX : addrDef := "1100000010010000";
constant rmwAbsX : addrDef := "1100000010001000";
constant readAbsY : addrDef := "1100000001000000";
constant writeAbsY : addrDef := "1100000001010000";
constant rmwAbsY : addrDef := "1100000001001000";
-- PHA PHP
constant push : addrDef := "0000010000000000";
-- PLA PLP
constant pop : addrDef := "0000010000100000";
-- Jumps
constant jsr : addrDef := "1000101000000000";
constant jumpAbs : addrDef := "1000001000000000";
constant jumpInd : addrDef := "1100001000000000";
constant jumpIndX : addrDef := "1100001010000000";
constant relative : addrDef := "1000000100000000";
-- Specials
constant rts : addrDef := "0000101000100100";
constant rti : addrDef := "0000111000100010";
constant brk : addrDef := "1000111000000001";
constant xxxxxxxx : addrDef := "----------0---00";
-- A = accu
-- X = index X
-- Y = index Y
-- S = Stack pointer
-- H = indexH
--
-- AEXYSTHc
constant aluInA : unsigned(0 to 7) := "10000000";
constant aluInBrk : unsigned(0 to 7) := "01000000";
constant aluInX : unsigned(0 to 7) := "00100000";
constant aluInY : unsigned(0 to 7) := "00010000";
constant aluInS : unsigned(0 to 7) := "00001000";
constant aluInT : unsigned(0 to 7) := "00000100";
constant aluInClr : unsigned(0 to 7) := "00000001";
constant aluInSet : unsigned(0 to 7) := "00000000";
constant aluInXXX : unsigned(0 to 7) := "--------";
-- Most of the aluModes are just like the opcodes.
-- aluModeInp -> input is output. calculate N and Z
-- aluModeCmp -> Compare for CMP, CPX, CPY
-- aluModeFlg -> input to flags needed for PLP, RTI and CLC, SEC, CLV
-- aluModeInc -> for INC but also INX, INY
-- aluModeDec -> for DEC but also DEX, DEY
subtype aluMode1 is unsigned(0 to 3);
subtype aluMode2 is unsigned(0 to 2);
subtype aluMode is unsigned(0 to 9);
-- Logic/Shift ALU
constant aluModeInp : aluMode1 := "0000";
constant aluModeP : aluMode1 := "0001";
constant aluModeInc : aluMode1 := "0010";
constant aluModeDec : aluMode1 := "0011";
constant aluModeFlg : aluMode1 := "0100";
constant aluModeBit : aluMode1 := "0101";
-- 0110
-- 0111
constant aluModeLsr : aluMode1 := "1000";
constant aluModeRor : aluMode1 := "1001";
constant aluModeAsl : aluMode1 := "1010";
constant aluModeRol : aluMode1 := "1011";
constant aluModeTSB : aluMode1 := "1100";
constant aluModeTRB : aluMode1 := "1101";
-- 1110
-- 1111;
-- Arithmetic ALU
constant aluModePss : aluMode2 := "000";
constant aluModeCmp : aluMode2 := "001";
constant aluModeAdc : aluMode2 := "010";
constant aluModeSbc : aluMode2 := "011";
constant aluModeAnd : aluMode2 := "100";
constant aluModeOra : aluMode2 := "101";
constant aluModeEor : aluMode2 := "110";
constant aluModeNoF : aluMode2 := "111";
constant aluInp : aluMode := aluModeInp & aluModePss & "---";
constant aluP : aluMode := aluModeP & aluModePss & "---";
constant aluInc : aluMode := aluModeInc & aluModePss & "---";
constant aluDec : aluMode := aluModeDec & aluModePss & "---";
constant aluFlg : aluMode := aluModeFlg & aluModePss & "---";
constant aluBit : aluMode := aluModeBit & aluModeAnd & "---";
constant aluRor : aluMode := aluModeRor & aluModePss & "---";
constant aluLsr : aluMode := aluModeLsr & aluModePss & "---";
constant aluRol : aluMode := aluModeRol & aluModePss & "---";
constant aluAsl : aluMode := aluModeAsl & aluModePss & "---";
constant aluTSB : aluMode := aluModeTSB & aluModePss & "---";
constant aluTRB : aluMode := aluModeTRB & aluModePss & "---";
constant aluCmp : aluMode := aluModeInp & aluModeCmp & "100";
constant aluCpx : aluMode := aluModeInp & aluModeCmp & "010";
constant aluCpy : aluMode := aluModeInp & aluModeCmp & "001";
constant aluAdc : aluMode := aluModeInp & aluModeAdc & "---";
constant aluSbc : aluMode := aluModeInp & aluModeSbc & "---";
constant aluAnd : aluMode := aluModeInp & aluModeAnd & "---";
constant aluOra : aluMode := aluModeInp & aluModeOra & "---";
constant aluEor : aluMode := aluModeInp & aluModeEor & "---";
constant aluXXX : aluMode := (others => '-');
-- Stack operations. Push/Pop/None
constant stackInc : unsigned(0 to 0) := "0";
constant stackDec : unsigned(0 to 0) := "1";
constant stackXXX : unsigned(0 to 0) := "-";
subtype decodedBitsDef is unsigned(0 to 43);
type opcodeInfoTableDef is array(0 to 255) of decodedBitsDef;
constant opcodeInfoTable : opcodeInfoTableDef := (
-- +------- Update register A
-- |+------ Update register X
-- ||+----- Update register Y
-- |||+---- Update register S
-- |||| +-- Update Flags
-- |||| |
-- |||| _|__
-- |||| / \
-- AXYS NVDIZC addressing aluInput aluMode
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "001100" & brk & aluInBrk & aluP, -- 00 BRK
"1000" & "100010" & readIndX & aluInT & aluOra, -- 01 ORA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 02 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 03 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTSB, -- 04 TSB zp ----------- 65C02
"1000" & "100010" & readZp & aluInT & aluOra, -- 05 ORA zp
"0000" & "100011" & rmwZp & aluInT & aluAsl, -- 06 ASL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 07 NOP ------- 65C02
"0000" & "000000" & push & aluInXXX & aluP, -- 08 PHP
"1000" & "100010" & immediate & aluInT & aluOra, -- 09 ORA imm
"1000" & "100011" & implied & aluInA & aluAsl, -- 0A ASL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTSB, -- 0C TSB abs ---------- 65C02
"1000" & "100010" & readAbs & aluInT & aluOra, -- 0D ORA abs
"0000" & "100011" & rmwAbs & aluInT & aluAsl, -- 0E ASL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 0F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 10 BPL
"1000" & "100010" & readIndY & aluInT & aluOra, -- 11 ORA (zp),y
"1000" & "100010" & readInd & aluInT & aluOra, -- 12 ORA (zp) --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 13 NOP ------- 65C02
"0000" & "000010" & rmwZp & aluInT & aluTRB, -- 14 TRB zp ~---------- 65C02
"1000" & "100010" & readZpX & aluInT & aluOra, -- 15 ORA zp,x
"0000" & "100011" & rmwZpX & aluInT & aluAsl, -- 16 ASL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 17 NOP ------- 65C02
"0000" & "000001" & implied & aluInClr & aluFlg, -- 18 CLC
"1000" & "100010" & readAbsY & aluInT & aluOra, -- 19 ORA abs,y
"1000" & "100010" & implied & aluInA & aluInc, -- 1A INC accu --------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1B NOP ------- 65C02
"0000" & "000010" & rmwAbs & aluInT & aluTRB, -- 1C TRB abs ~----- --- 65C02
"1000" & "100010" & readAbsX & aluInT & aluOra, -- 1D ORA abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluAsl, -- 1E ASL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 1F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & jsr & aluInXXX & aluXXX, -- 20 JSR
"1000" & "100010" & readIndX & aluInT & aluAnd, -- 21 AND (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 22 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 23 NOP ------- 65C02
"0000" & "110010" & readZp & aluInT & aluBit, -- 24 BIT zp
"1000" & "100010" & readZp & aluInT & aluAnd, -- 25 AND zp
"0000" & "100011" & rmwZp & aluInT & aluRol, -- 26 ROL zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 27 NOP ------- 65C02
"0000" & "111111" & pop & aluInT & aluFlg, -- 28 PLP
"1000" & "100010" & immediate & aluInT & aluAnd, -- 29 AND imm
"1000" & "100011" & implied & aluInA & aluRol, -- 2A ROL accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2B NOP ------- 65C02
"0000" & "110010" & readAbs & aluInT & aluBit, -- 2C BIT abs
"1000" & "100010" & readAbs & aluInT & aluAnd, -- 2D AND abs
"0000" & "100011" & rmwAbs & aluInT & aluRol, -- 2E ROL abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 2F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 30 BMI
"1000" & "100010" & readIndY & aluInT & aluAnd, -- 31 AND (zp),y
"1000" & "100010" & readInd & aluInT & aluAnd, -- 32 AND (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 33 NOP ------- 65C02
"0000" & "110010" & readZpX & aluInT & aluBit, -- 34 BIT zp,x -------- 65C02
"1000" & "100010" & readZpX & aluInT & aluAnd, -- 35 AND zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRol, -- 36 ROL zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 37 NOP ------- 65C02
"0000" & "000001" & implied & aluInSet & aluFlg, -- 38 SEC
"1000" & "100010" & readAbsY & aluInT & aluAnd, -- 39 AND abs,y
"1000" & "100010" & implied & aluInA & aluDec, -- 3A DEC accu -------- 65C12
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3B NOP ------- 65C02
"0000" & "110010" & readAbsX & aluInT & aluBit, -- 3C BIT abs,x ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluAnd, -- 3D AND abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRol, -- 3E ROL abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 3F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "111111" & rti & aluInT & aluFlg, -- 40 RTI
"1000" & "100010" & readIndX & aluInT & aluEor, -- 41 EOR (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 42 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 43 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 44 NOP ------- 65C02
"1000" & "100010" & readZp & aluInT & aluEor, -- 45 EOR zp
"0000" & "100011" & rmwZp & aluInT & aluLsr, -- 46 LSR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 47 NOP ------- 65C02
"0000" & "000000" & push & aluInA & aluInp, -- 48 PHA
"1000" & "100010" & immediate & aluInT & aluEor, -- 49 EOR imm
"1000" & "100011" & implied & aluInA & aluLsr, -- 4A LSR accu -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4B NOP ------- 65C02
"0000" & "000000" & jumpAbs & aluInXXX & aluXXX, -- 4C JMP abs
"1000" & "100010" & readAbs & aluInT & aluEor, -- 4D EOR abs
"0000" & "100011" & rmwAbs & aluInT & aluLsr, -- 4E LSR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 4F NOP ------- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 50 BVC
"1000" & "100010" & readIndY & aluInT & aluEor, -- 51 EOR (zp),y
"1000" & "100010" & readInd & aluInT & aluEor, -- 52 EOR (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 53 NOP ------- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 54 NOP ------- 65C02
"1000" & "100010" & readZpX & aluInT & aluEor, -- 55 EOR zp,x
"0000" & "100011" & rmwZpX & aluInT & aluLsr, -- 56 LSR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 57 NOP ------- 65C02
"0000" & "000100" & implied & aluInClr & aluXXX, -- 58 CLI
"1000" & "100010" & readAbsY & aluInT & aluEor, -- 59 EOR abs,y
"0000" & "000000" & push & aluInY & aluInp, -- 5A PHY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5B NOP ------- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- 5C NOP ------- 65C02
"1000" & "100010" & readAbsX & aluInT & aluEor, -- 5D EOR abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluLsr, -- 5E LSR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 5F NOP ------- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & rts & aluInXXX & aluXXX, -- 60 RTS
"1000" & "110011" & readIndX & aluInT & aluAdc, -- 61 ADC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 62 NOP ------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 63 NOP ------- 65C02
"0000" & "000000" & writeZp & aluInClr & aluInp, -- 64 STZ zp ---------- 65C02
"1000" & "110011" & readZp & aluInT & aluAdc, -- 65 ADC zp
"0000" & "100011" & rmwZp & aluInT & aluRor, -- 66 ROR zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 67 NOP ------- 65C02
"1000" & "100010" & pop & aluInT & aluInp, -- 68 PLA
"1000" & "110011" & immediate & aluInT & aluAdc, -- 69 ADC imm
"1000" & "100011" & implied & aluInA & aluRor, -- 6A ROR accu
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6B NOP ------ 65C02
"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbs & aluInT & aluAdc, -- 6D ADC abs
"0000" & "100011" & rmwAbs & aluInT & aluRor, -- 6E ROR abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 6F NOP ------ 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 70 BVS
"1000" & "110011" & readIndY & aluInT & aluAdc, -- 71 ADC (zp),y
"1000" & "110011" & readInd & aluInT & aluAdc, -- 72 ADC (zp) -------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 73 NOP ------ 65C02
"0000" & "000000" & writeZpX & aluInClr & aluInp, -- 74 STZ zp,x -------- 65C02
"1000" & "110011" & readZpX & aluInT & aluAdc, -- 75 ADC zp,x
"0000" & "100011" & rmwZpX & aluInT & aluRor, -- 76 ROR zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 77 NOP ----- 65C02
"0000" & "000100" & implied & aluInSet & aluXXX, -- 78 SEI
"1000" & "110011" & readAbsY & aluInT & aluAdc, -- 79 ADC abs,y
"0010" & "100010" & pop & aluInT & aluInp, -- 7A PLY ------------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7B NOP ----- 65C02
"0000" & "000000" & jumpIndX & aluInXXX & aluXXX, -- 7C JMP indirect,x -- 65C02
--"0000" & "000000" & jumpInd & aluInXXX & aluXXX, -- 6C JMP indirect
"1000" & "110011" & readAbsX & aluInT & aluAdc, -- 7D ADC abs,x
"0000" & "100011" & rmwAbsX & aluInT & aluRor, -- 7E ROR abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 7F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 80 BRA ----------- 65C02
"0000" & "000000" & writeIndX & aluInA & aluInp, -- 81 STA (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- 82 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 83 NOP ----- 65C02
"0000" & "000000" & writeZp & aluInY & aluInp, -- 84 STY zp
"0000" & "000000" & writeZp & aluInA & aluInp, -- 85 STA zp
"0000" & "000000" & writeZp & aluInX & aluInp, -- 86 STX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 87 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluDec, -- 88 DEY
"0000" & "000010" & immediate & aluInT & aluBit, -- 89 BIT imm ------- 65C02
"1000" & "100010" & implied & aluInX & aluInp, -- 8A TXA
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInY & aluInp, -- 8C STY abs ------- 65C02
"0000" & "000000" & writeAbs & aluInA & aluInp, -- 8D STA abs
"0000" & "000000" & writeAbs & aluInX & aluInp, -- 8E STX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 8F NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- 90 BCC
"0000" & "000000" & writeIndY & aluInA & aluInp, -- 91 STA (zp),y
"0000" & "000000" & writeInd & aluInA & aluInp, -- 92 STA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 93 NOP ----- 65C02
"0000" & "000000" & writeZpX & aluInY & aluInp, -- 94 STY zp,x
"0000" & "000000" & writeZpX & aluInA & aluInp, -- 95 STA zp,x
"0000" & "000000" & writeZpY & aluInX & aluInp, -- 96 STX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 97 NOP ----- 65C02
"1000" & "100010" & implied & aluInY & aluInp, -- 98 TYA
"0000" & "000000" & writeAbsY & aluInA & aluInp, -- 99 STA abs,y
"0001" & "000000" & implied & aluInX & aluInp, -- 9A TXS
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9B NOP ----- 65C02
"0000" & "000000" & writeAbs & aluInClr & aluInp, -- 9C STZ Abs ------- 65C02
"0000" & "000000" & writeAbsX & aluInA & aluInp, -- 9D STA abs,x
"0000" & "000000" & writeAbsX & aluInClr & aluInp, -- 9C STZ Abs,x ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- 9F NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0010" & "100010" & immediate & aluInT & aluInp, -- A0 LDY imm
"1000" & "100010" & readIndX & aluInT & aluInp, -- A1 LDA (zp,x)
"0100" & "100010" & immediate & aluInT & aluInp, -- A2 LDX imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A3 NOP ----- 65C02
"0010" & "100010" & readZp & aluInT & aluInp, -- A4 LDY zp
"1000" & "100010" & readZp & aluInT & aluInp, -- A5 LDA zp
"0100" & "100010" & readZp & aluInT & aluInp, -- A6 LDX zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- A7 NOP ----- 65C02
"0010" & "100010" & implied & aluInA & aluInp, -- A8 TAY
"1000" & "100010" & immediate & aluInT & aluInp, -- A9 LDA imm
"0100" & "100010" & implied & aluInA & aluInp, -- AA TAX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AB NOP ----- 65C02
"0010" & "100010" & readAbs & aluInT & aluInp, -- AC LDY abs
"1000" & "100010" & readAbs & aluInT & aluInp, -- AD LDA abs
"0100" & "100010" & readAbs & aluInT & aluInp, -- AE LDX abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- AF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- B0 BCS
"1000" & "100010" & readIndY & aluInT & aluInp, -- B1 LDA (zp),y
"1000" & "100010" & readInd & aluInT & aluInp, -- B2 LDA (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B3 NOP ----- 65C02
"0010" & "100010" & readZpX & aluInT & aluInp, -- B4 LDY zp,x
"1000" & "100010" & readZpX & aluInT & aluInp, -- B5 LDA zp,x
"0100" & "100010" & readZpY & aluInT & aluInp, -- B6 LDX zp,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- B7 NOP ----- 65C02
"0000" & "010000" & implied & aluInClr & aluFlg, -- B8 CLV
"1000" & "100010" & readAbsY & aluInT & aluInp, -- B9 LDA abs,y
"0100" & "100010" & implied & aluInS & aluInp, -- BA TSX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BB NOP ----- 65C02
"0010" & "100010" & readAbsX & aluInT & aluInp, -- BC LDY abs,x
"1000" & "100010" & readAbsX & aluInT & aluInp, -- BD LDA abs,x
"0100" & "100010" & readAbsY & aluInT & aluInp, -- BE LDX abs,y
"0000" & "000000" & implied & aluInXXX & aluXXX, -- BF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpy, -- C0 CPY imm
"0000" & "100011" & readIndX & aluInT & aluCmp, -- C1 CMP (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- C2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpy, -- C4 CPY zp
"0000" & "100011" & readZp & aluInT & aluCmp, -- C5 CMP zp
"0000" & "100010" & rmwZp & aluInT & aluDec, -- C6 DEC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- C7 NOP ----- 65C02
"0010" & "100010" & implied & aluInY & aluInc, -- C8 INY
"0000" & "100011" & immediate & aluInT & aluCmp, -- C9 CMP imm
"0100" & "100010" & implied & aluInX & aluDec, -- CA DEX
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpy, -- CC CPY abs
"0000" & "100011" & readAbs & aluInT & aluCmp, -- CD CMP abs
"0000" & "100010" & rmwAbs & aluInT & aluDec, -- CE DEC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- CF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- D0 BNE
"0000" & "100011" & readIndY & aluInT & aluCmp, -- D1 CMP (zp),y
"0000" & "100011" & readInd & aluInT & aluCmp, -- D2 CMP (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- D4 NOP ----- 65C02
"0000" & "100011" & readZpX & aluInT & aluCmp, -- D5 CMP zp,x
"0000" & "100010" & rmwZpX & aluInT & aluDec, -- D6 DEC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- D7 NOP ----- 65C02
"0000" & "001000" & implied & aluInClr & aluXXX, -- D8 CLD
"0000" & "100011" & readAbsY & aluInT & aluCmp, -- D9 CMP abs,y
"0000" & "000000" & push & aluInX & aluInp, -- DA PHX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- DC NOP ----- 65C02
"0000" & "100011" & readAbsX & aluInT & aluCmp, -- DD CMP abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluDec, -- DE DEC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- DF NOP ----- 65C02
-- AXYS NVDIZC addressing aluInput aluMode
"0000" & "100011" & immediate & aluInT & aluCpx, -- E0 CPX imm
"1000" & "110011" & readIndX & aluInT & aluSbc, -- E1 SBC (zp,x)
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- E2 NOP ----- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E3 NOP ----- 65C02
"0000" & "100011" & readZp & aluInT & aluCpx, -- E4 CPX zp
"1000" & "110011" & readZp & aluInT & aluSbc, -- E5 SBC zp
"0000" & "100010" & rmwZp & aluInT & aluInc, -- E6 INC zp
"0000" & "000000" & implied & aluInXXX & aluXXX, -- E7 NOP ----- 65C02
"0100" & "100010" & implied & aluInX & aluInc, -- E8 INX
"1000" & "110011" & immediate & aluInT & aluSbc, -- E9 SBC imm
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EA NOP
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EB NOP ----- 65C02
"0000" & "100011" & readAbs & aluInT & aluCpx, -- EC CPX abs
"1000" & "110011" & readAbs & aluInT & aluSbc, -- ED SBC abs
"0000" & "100010" & rmwAbs & aluInT & aluInc, -- EE INC abs
"0000" & "000000" & implied & aluInXXX & aluXXX, -- EF NOP ----- 65C02
"0000" & "000000" & relative & aluInXXX & aluXXX, -- F0 BEQ
"1000" & "110011" & readIndY & aluInT & aluSbc, -- F1 SBC (zp),y
"1000" & "110011" & readInd & aluInT & aluSbc, -- F2 SBC (zp) ------ 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F3 NOP ----- 65C02
"0000" & "000000" & immediate & aluInXXX & aluXXX, -- F4 NOP ----- 65C02
"1000" & "110011" & readZpX & aluInT & aluSbc, -- F5 SBC zp,x
"0000" & "100010" & rmwZpX & aluInT & aluInc, -- F6 INC zp,x
"0000" & "000000" & implied & aluInXXX & aluXXX, -- F7 NOP ---- 65C02
"0000" & "001000" & implied & aluInSet & aluXXX, -- F8 SED
"1000" & "110011" & readAbsY & aluInT & aluSbc, -- F9 SBC abs,y
"0100" & "100010" & pop & aluInT & aluInp, -- FA PLX ----------- 65C02
"0000" & "000000" & implied & aluInXXX & aluXXX, -- FB NOP ----- 65C02
"0000" & "000000" & readAbs & aluInXXX & aluXXX, -- FC NOP ----- 65C02
"1000" & "110011" & readAbsX & aluInT & aluSbc, -- FD SBC abs,x
"0000" & "100010" & rmwAbsX & aluInT & aluInc, -- FE INC abs,x
"0000" & "000000" & implied & aluInXXX & aluXXX -- FF NOP ----- 65C02
);
signal opcInfo : decodedBitsDef;
signal nextOpcInfo : decodedBitsDef; -- Next opcode (decoded)
signal theOpcode : unsigned(7 downto 0);
signal nextOpcode : unsigned(7 downto 0);
-- Program counter
signal PC : unsigned(15 downto 0); -- Program counter
-- Address generation
type nextAddrDef is (
nextAddrHold,
nextAddrIncr,
nextAddrIncrL, -- Increment low bits only (zeropage accesses)
nextAddrIncrH, -- Increment high bits only (page-boundary)
nextAddrDecrH, -- Decrement high bits (branch backwards)
nextAddrPc,
nextAddrIrq,
nextAddrReset,
nextAddrAbs,
nextAddrAbsIndexed,
nextAddrZeroPage,
nextAddrZPIndexed,
nextAddrStack,
nextAddrRelative
);
signal nextAddr : nextAddrDef;
signal myAddr : unsigned(15 downto 0);
signal myAddrIncr : unsigned(15 downto 0);
signal myAddrIncrH : unsigned(7 downto 0);
signal myAddrDecrH : unsigned(7 downto 0);
signal theWe : std_logic;
signal irqActive : std_logic;
-- Output register
signal doReg : unsigned(7 downto 0);
-- Buffer register
signal T : unsigned(7 downto 0);
-- General registers
signal A : unsigned(7 downto 0); -- Accumulator
signal X : unsigned(7 downto 0); -- Index X
signal Y : unsigned(7 downto 0); -- Index Y
signal S : unsigned(7 downto 0); -- stack pointer
-- Status register
signal C : std_logic; -- Carry
signal Z : std_logic; -- Zero flag
signal I : std_logic; -- Interrupt flag
signal D : std_logic; -- Decimal mode
signal B : std_logic; -- Break software interrupt
signal R : std_logic; -- always 1
signal V : std_logic; -- Overflow
signal N : std_logic; -- Negative
-- ALU
-- ALU input
signal aluInput : unsigned(7 downto 0);
signal aluCmpInput : unsigned(7 downto 0);
-- ALU output
signal aluRegisterOut : unsigned(7 downto 0);
signal aluRmwOut : unsigned(7 downto 0);
signal aluC : std_logic;
signal aluZ : std_logic;
signal aluV : std_logic;
signal aluN : std_logic;
-- Indexing
signal indexOut : unsigned(8 downto 0);
begin
processAluInput: process(clk, opcInfo, A, X, Y, T, S)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInA) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInX) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInY) = '1' then
temp := temp and Y;
end if;
if opcInfo(opcInS) = '1' then
temp := temp and S;
end if;
if opcInfo(opcInT) = '1' then
temp := temp and T;
end if;
if opcInfo(opcInBrk) = '1' then
temp := temp and "11100111"; -- also DMB clear D (bit 3)
end if;
if opcInfo(opcInClear) = '1' then
temp := (others => '0');
end if;
aluInput <= temp;
end process;
processCmpInput: process(clk, opcInfo, A, X, Y)
variable temp : unsigned(7 downto 0);
begin
temp := (others => '1');
if opcInfo(opcInCmp) = '1' then
temp := temp and A;
end if;
if opcInfo(opcInCpx) = '1' then
temp := temp and X;
end if;
if opcInfo(opcInCpy) = '1' then
temp := temp and Y;
end if;
aluCmpInput <= temp;
end process;
-- ALU consists of two parts
-- Read-Modify-Write or index instructions: INC/DEC/ASL/LSR/ROR/ROL
-- Accumulator instructions: ADC, SBC, EOR, AND, EOR, ORA
-- Some instructions are both RMW and accumulator so for most
-- instructions the rmw results are routed through accu alu too.
-- The B flag
------------
--No actual "B" flag exists inside the 6502's processor status register. The B
--flag only exists in the status flag byte pushed to the stack. Naturally,
--when the flags are restored (via PLP or RTI), the B bit is discarded.
--
--Depending on the means, the B status flag will be pushed to the stack as
--either 0 or 1.
--
--software instructions BRK & PHP will push the B flag as being 1.
--hardware interrupts IRQ & NMI will push the B flag as being 0.
processAlu: process(clk, opcInfo, aluInput, aluCmpInput, A, T, irqActive, N, V, D, I, Z, C, R)
variable lowBits : unsigned(5 downto 0);
variable nineBits : unsigned(8 downto 0);
variable rmwBits : unsigned(8 downto 0);
variable tsxBits : unsigned(8 downto 0);
variable varC : std_logic;
variable varZ : std_logic;
variable varV : std_logic;
variable varN : std_logic;
begin
lowBits := (others => '-');
nineBits := (others => '-');
rmwBits := (others => '-');
tsxBits := (others => '-');
R <= '1';
B <= '0';
-- Shift unit
case opcInfo(aluMode1From to aluMode1To) is
when aluModeInp => rmwBits := C & aluInput;
when aluModeP => rmwBits := C & N & V & R & (not irqActive) & D & I & Z & C; -- irqActive
when aluModeInc => rmwBits := C & (aluInput + 1);
when aluModeDec => rmwBits := C & (aluInput - 1);
when aluModeAsl => rmwBits := aluInput & "0";
when aluModeTSB => rmwBits := "0" & (aluInput(7 downto 0) or A); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeTRB => rmwBits := "0" & (aluInput(7 downto 0) and (not A)); -- added by alan for 65c02
tsxBits := "0" & (aluInput(7 downto 0) and A);
when aluModeFlg => rmwBits := aluInput(0) & aluInput;
when aluModeLsr => rmwBits := aluInput(0) & "0" & aluInput(7 downto 1);
when aluModeRol => rmwBits := aluInput & C;
when aluModeRoR => rmwBits := aluInput(0) & C & aluInput(7 downto 1);
when others => rmwBits := C & aluInput;
end case;
-- ALU
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & rmwBits(3 downto 0) & "1");
ninebits := ("0" & A) + ("0" & rmwBits(7 downto 0)) + (B"00000000" & rmwBits(8));
when aluModeSbc => lowBits := ("0" & A(3 downto 0) & rmwBits(8)) + ("0" & (not rmwBits(3 downto 0)) & "1");
ninebits := ("0" & A) + ("0" & (not rmwBits(7 downto 0))) + (B"00000000" & rmwBits(8));
when aluModeCmp => ninebits := ("0" & aluCmpInput) + ("0" & (not rmwBits(7 downto 0))) + "000000001";
when aluModeAnd => ninebits := rmwBits(8) & (A and rmwBits(7 downto 0));
when aluModeEor => ninebits := rmwBits(8) & (A xor rmwBits(7 downto 0));
when aluModeOra => ninebits := rmwBits(8) & (A or rmwBits(7 downto 0));
when aluModeNoF => ninebits := "000110000";
when others => ninebits := rmwBits;
end case;
varV := aluInput(6); -- Default for BIT / PLP / RTI
if (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varZ := rmwBits(1);
elsif (opcInfo(aluMode1From to aluMode1To) = aluModeTSB) or (opcInfo(aluMode1From to aluMode1To) = aluModeTRB) then
if tsxBits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
elsif ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
if (opcInfo(aluMode1From to aluMode1To) = aluModeBit) or (opcInfo(aluMode1From to aluMode1To) = aluModeFlg) then
varN := rmwBits(7);
else
varN := nineBits(7);
end if;
varC := ninebits(8);
case opcInfo(aluMode2From to aluMode2To) is
-- Flags Affected: n v — — — — z c
-- n Set if most significant bit of result is set; else cleared.
-- v Set if signed overflow; cleared if valid signed result.
-- z Set if result is zero; else cleared.
-- c Set if unsigned overflow; cleared if valid unsigned result
when aluModeAdc =>
-- decimal mode low bits correction, is done after setting Z flag.
if D = '1' then
if lowBits(5 downto 1) > 9 then
ninebits(3 downto 0) := ninebits(3 downto 0) + 6;
if lowBits(5) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) + 1;
end if;
end if;
end if;
when others =>
null;
end case;
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
-- decimal mode high bits correction, is done after setting Z and N flags
varV := (A(7) xor ninebits(7)) and (rmwBits(7) xor ninebits(7));
if D = '1' then
if ninebits(8 downto 4) > 9 then
ninebits(8 downto 4) := ninebits(8 downto 4) + 6;
varC := '1';
end if;
end if;
when aluModeSbc =>
varV := (A(7) xor ninebits(7)) and ((not rmwBits(7)) xor ninebits(7));
if D = '1' then
-- Check for borrow (lower 4 bits)
if lowBits(5) = '0' then
ninebits(7 downto 0) := ninebits(7 downto 0) - 6;
end if;
-- Check for borrow (upper 4 bits)
if ninebits(8) = '0' then
ninebits(8 downto 4) := ninebits(8 downto 4) - 6;
end if;
end if;
when others =>
null;
end case;
-- fix n and z flag for 65c02 adc sbc instructions in decimal mode
case opcInfo(aluMode2From to aluMode2To) is
when aluModeAdc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when aluModeSbc =>
if D = '1' then
if ninebits(7 downto 0) = X"00" then
varZ := '1';
else
varZ := '0';
end if;
varN := ninebits(7);
end if;
when others =>
null;
end case;
-- DMB Remove Pipelining
-- if rising_edge(clk) then
aluRmwOut <= rmwBits(7 downto 0);
aluRegisterOut <= ninebits(7 downto 0);
aluC <= varC;
aluZ <= varZ;
aluV <= varV;
aluN <= varN;
-- end if;
end process;
calcInterrupt: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = cycleStack4 or reset = '0' then
nmiReg <= '1';
end if;
if nextCpuCycle /= cycleBranchTaken and nextCpuCycle /= opcodeFetch then
irqReg <= irq_n;
nmiEdge <= nmi_n;
if (nmiEdge = '1') and (nmi_n = '0') then
nmiReg <= '0';
end if;
end if;
-- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
end if;
end if;
end process;
--pipeirq: process(clk)
-- begin
-- if rising_edge(clk) then
-- if enable = '1' then
-- if (reset = '0') or (theCpuCycle = opcodeFetch) then
-- -- The 'or opcInfo(opcSetI)' prevents NMI immediately after BRK or IRQ.
-- -- Presumably this is done in the real 6502/6510 to prevent a double IRQ.
-- processIrq <= not ((nmiReg and (irqReg or I)) or opcInfo(opcIRQ));
-- end if;
-- end if;
-- end if;
-- end process;
calcNextOpcode: process(clk, di, reset, processIrq)
variable myNextOpcode : unsigned(7 downto 0);
begin
-- Next opcode is read from input unless a reset or IRQ is pending.
myNextOpcode := di;
if reset = '0' then
myNextOpcode := X"4C";
elsif processIrq = '1' then
myNextOpcode := X"00";
end if;
nextOpcode <= myNextOpcode;
end process;
nextOpcInfo <= opcodeInfoTable(to_integer(nextOpcode));
-- Read bits and flags from opcodeInfoTable and store in opcInfo.
-- This info is used to control the execution of the opcode.
calcOpcInfo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if (reset = '0') or (theCpuCycle = opcodeFetch) then
opcInfo <= nextOpcInfo;
end if;
end if;
end if;
end process;
calcTheOpcode: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
if theCpuCycle = opcodeFetch then
irqActive <= '0';
if processIrq = '1' then
irqActive <= '1';
end if;
-- Fetch opcode
theOpcode <= nextOpcode;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- State machine
-- -----------------------------------------------------------------------
process(enable, theCpuCycle, opcInfo)
begin
updateRegisters <= false;
if enable = '1' then
if opcInfo(opcRti) = '1' then
if theCpuCycle = cycleRead then
updateRegisters <= true;
end if;
elsif theCpuCycle = opcodeFetch then
updateRegisters <= true;
end if;
end if;
end process;
process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theCpuCycle <= nextCpuCycle;
end if;
if reset = '0' then
theCpuCycle <= cycle2;
end if;
end if;
end process;
-- Determine the next cpu cycle. After the last cycle we always
-- go to opcodeFetch to get the next opcode.
calcNextCpuCycle: process(theCpuCycle, opcInfo, theOpcode, nextOpcode, indexOut, T, N, V, C, Z)
begin
nextCpuCycle <= opcodeFetch;
case theCpuCycle is
when opcodeFetch =>
-- DMB: Implement single cycle NOPs (columns 3,7,B,F) by
-- looking ahead at opcode (bypassing the normal decoding)
if nextOpcode(1 downto 0) = "11" then
nextCpuCycle <= opcodeFetch;
else
nextCpuCycle <= cycle2;
end if;
when cycle2 =>
if opcInfo(opcBranch) = '1' then
if (N = theOpcode(5) and theOpcode(7 downto 6) = "00")
or (V = theOpcode(5) and theOpcode(7 downto 6) = "01")
or (C = theOpcode(5) and theOpcode(7 downto 6) = "10")
or (Z = theOpcode(5) and theOpcode(7 downto 6) = "11")
or (theOpcode(7 downto 0) = x"80") then -- Branch condition is true
nextCpuCycle <= cycleBranchTaken;
end if;
elsif (opcInfo(opcStackUp) = '1') then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackAddr) = '1' and opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleStack2;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack1;
elsif opcInfo(opcStackData) = '1' then
nextCpuCycle <= cycleWrite;
elsif opcInfo(opcAbsolute) = '1' then
nextCpuCycle <= cycle3;
elsif opcInfo(opcIndirect) = '1' then
if opcInfo(indexX) = '1' then
nextCpuCycle <= cyclePreIndirect;
else
nextCpuCycle <= cycleIndirect;
end if;
elsif opcInfo(opcZeroPage) = '1' then
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
else
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreRead;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
elsif opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycle3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcWrite) = '1' then
if (opcInfo(indexX) = '1') or (opcInfo(indexY) = '1') then
nextCpuCycle <= cyclePreWrite;
else
nextCpuCycle <= cycleWrite;
end if;
end if;
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
if opcInfo(opcWrite) = '1' then
nextCpuCycle <= cycleWrite;
else
nextCpuCycle <= cycleRead2;
end if;
end if;
when cyclePreIndirect =>
nextCpuCycle <= cycleIndirect;
when cycleIndirect =>
nextCpuCycle <= cycle3;
when cycleBranchTaken =>
if indexOut(8) /= T(7) then
nextCpuCycle <= cycleBranchPage;
end if;
when cyclePreRead =>
if opcInfo(opcZeroPage) = '1' then
nextCpuCycle <= cycleRead2;
end if;
when cycleRead =>
if opcInfo(opcJump) = '1' or indexOut(8) = '1' then
nextCpuCycle <= cycleRead2;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
if opcInfo(indexX) = '1' or opcInfo(indexY) = '1' then
nextCpuCycle <= cycleRead2;
end if;
end if;
when cycleRead2 =>
if opcInfo(opcJump) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcRmw) = '1' then
nextCpuCycle <= cycleRmw;
end if;
when cycleRmw =>
nextCpuCycle <= cycleWrite;
when cyclePreWrite =>
nextCpuCycle <= cycleWrite;
when cycleStack1 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack2;
end if;
when cycleStack2 =>
nextCpuCycle <= cycleStack3;
if opcInfo(opcRti) = '1' then
nextCpuCycle <= cycleRead;
end if;
if opcInfo(opcStackData) = '0' and opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
end if;
when cycleStack3 =>
nextCpuCycle <= cycleRead;
if opcInfo(opcStackData) = '0' or opcInfo(opcStackUp) = '1' then
nextCpuCycle <= cycleJump;
elsif opcInfo(opcStackAddr) = '1' then
nextCpuCycle <= cycleStack4;
end if;
when cycleStack4 =>
nextCpuCycle <= cycleRead2;
when cycleJump =>
if opcInfo(opcIncrAfter) = '1' then
nextCpuCycle <= cycleEnd;
end if;
when others =>
null;
end case;
end process;
-- -----------------------------------------------------------------------
-- T register
-- -----------------------------------------------------------------------
calcT: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when cycle2 =>
T <= di;
when cycleStack1 | cycleStack2 =>
if opcInfo(opcStackUp) = '1' then
if theOpcode = x"28" or theOpcode = x"40" then -- plp or rti pulling the flags off the stack
T <= (di or "00110000"); -- Read from stack
else
T <= di;
end if;
end if;
when cycleIndirect | cycleRead | cycleRead2 =>
T <= di;
when others =>
null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- A register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateA) = '1' then
A <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- X register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateX) = '1' then
X <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Y register
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateY) = '1' then
Y <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- C flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateC) = '1' then
C <= aluC;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Z flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateZ) = '1' then
Z <= aluZ;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- I flag interupt flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
I <= '1';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateI) = '1' then
I <= aluInput(2);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- D flag
-- -----------------------------------------------------------------------
process(clk, reset)
begin
if reset = '0' then
D <= '0';
elsif rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateD) = '1' then
D <= aluInput(3);
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- V flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateV) = '1' then
V <= aluV;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- N flag
-- -----------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if updateRegisters then
if opcInfo(opcUpdateN) = '1' then
N <= aluN;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Stack pointer
-- -----------------------------------------------------------------------
process(clk)
variable sIncDec : unsigned(7 downto 0);
variable updateFlag : boolean;
begin
if rising_edge(clk) then
if opcInfo(opcStackUp) = '1' then
sIncDec := S + 1;
else
sIncDec := S - 1;
end if;
if enable = '1' then
updateFlag := false;
case nextCpuCycle is
when cycleStack1 =>
if (opcInfo(opcStackUp) = '1') or (opcInfo(opcStackData) = '1') then
updateFlag := true;
end if;
when cycleStack2 =>
updateFlag := true;
when cycleStack3 =>
updateFlag := true;
when cycleStack4 =>
updateFlag := true;
when cycleRead =>
if opcInfo(opcRti) = '1' then
updateFlag := true;
end if;
when cycleWrite =>
if opcInfo(opcStackData) = '1' then
updateFlag := true;
end if;
when others =>
null;
end case;
if updateFlag then
S <= sIncDec;
end if;
end if;
if updateRegisters then
if opcInfo(opcUpdateS) = '1' then
S <= aluRegisterOut;
end if;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Data out
-- -----------------------------------------------------------------------
calcDo: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
doReg <= aluRmwOut;
case nextCpuCycle is
when cycleStack2 =>
if opcInfo(opcIRQ) = '1' and irqActive = '0' then
doReg <= myAddrIncr(15 downto 8);
else
doReg <= PC(15 downto 8);
end if;
when cycleStack3 =>
doReg <= PC(7 downto 0);
when cycleRmw =>
doReg <= di; -- Read-modify-write write old value first.
when others =>
null;
end case;
end if;
end if;
end process;
do <= doReg;
-- -----------------------------------------------------------------------
-- Write enable
-- -----------------------------------------------------------------------
calcWe: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
theWe <= '1';
case nextCpuCycle is
when cycleStack1 =>
if opcInfo(opcStackUp) = '0' and ((opcInfo(opcStackAddr) = '0') or (opcInfo(opcStackData) = '1')) then
theWe <= '0';
end if;
when cycleStack2 | cycleStack3 | cycleStack4 =>
if opcInfo(opcStackUp) = '0' then
theWe <= '0';
end if;
when cycleRmw =>
theWe <= '0';
when cycleWrite =>
theWe <= '0';
when others =>
null;
end case;
end if;
end if;
--nwe <= theWe;
end process;
nwe <= theWe;
-- -----------------------------------------------------------------------
-- Program counter
-- -----------------------------------------------------------------------
calcPC: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case theCpuCycle is
when opcodeFetch =>
PC <= myAddr;
when cycle2 =>
if irqActive = '0' then
if opcInfo(opcSecondByte) = '1' then
PC <= myAddrIncr;
else
PC <= myAddr;
end if;
end if;
when cycle3 =>
if opcInfo(opcAbsolute) = '1' then
PC <= myAddrIncr;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
-- -----------------------------------------------------------------------
-- Address generation
-- -----------------------------------------------------------------------
calcNextAddr: process(theCpuCycle, opcInfo, indexOut, T, reset)
begin
nextAddr <= nextAddrIncr;
case theCpuCycle is
when cycle2 =>
if opcInfo(opcStackAddr) = '1' or opcInfo(opcStackData) = '1' then
nextAddr <= nextAddrStack;
elsif opcInfo(opcAbsolute) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcIndirect) = '1' then
nextAddr <= nextAddrZeroPage;
elsif opcInfo(opcSecondByte) = '1' then
nextAddr <= nextAddrIncr;
else
nextAddr <= nextAddrHold;
end if;
when cycle3 =>
if (opcInfo(opcIndirect) = '1') and (opcInfo(indexX) = '1') then
nextAddr <= nextAddrAbs;
else
nextAddr <= nextAddrAbsIndexed;
end if;
when cyclePreIndirect =>
nextAddr <= nextAddrZPIndexed;
when cycleIndirect =>
nextAddr <= nextAddrIncrL;
when cycleBranchTaken =>
nextAddr <= nextAddrRelative;
when cycleBranchPage =>
if T(7) = '0' then
nextAddr <= nextAddrIncrH;
else
nextAddr <= nextAddrDecrH;
end if;
when cyclePreRead =>
nextAddr <= nextAddrZPIndexed;
when cycleRead =>
nextAddr <= nextAddrPc;
if indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
elsif opcInfo(opcRmw) = '1' or opcInfo(opcJump) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRead2 =>
nextAddr <= nextAddrPc;
if opcInfo(opcJump) = '1' then
nextAddr <= nextAddrIncr;
elsif opcInfo(opcRmw) = '1' then
nextAddr <= nextAddrHold;
end if;
when cycleRmw =>
nextAddr <= nextAddrHold;
when cyclePreWrite =>
nextAddr <= nextAddrHold;
if opcInfo(opcZeroPage) = '1' then
nextAddr <= nextAddrZPIndexed;
elsif indexOut(8) = '1' then
nextAddr <= nextAddrIncrH;
end if;
when cycleWrite =>
nextAddr <= nextAddrPc;
when cycleStack1 =>
nextAddr <= nextAddrStack;
when cycleStack2 =>
nextAddr <= nextAddrStack;
when cycleStack3 =>
nextAddr <= nextAddrStack;
if opcInfo(opcStackData) = '0' then
nextAddr <= nextAddrPc;
end if;
when cycleStack4 =>
nextAddr <= nextAddrIrq;
when cycleJump =>
nextAddr <= nextAddrAbs;
when others =>
null;
end case;
if reset = '0' then
nextAddr <= nextAddrReset;
end if;
end process;
indexAlu: process(opcInfo, myAddr, T, X, Y)
begin
if opcInfo(indexX) = '1' then
indexOut <= (B"0" & T) + (B"0" & X);
elsif opcInfo(indexY) = '1' then
indexOut <= (B"0" & T) + (B"0" & Y);
elsif opcInfo(opcBranch) = '1' then
indexOut <= (B"0" & T) + (B"0" & myAddr(7 downto 0));
else
indexOut <= B"0" & T;
end if;
end process;
calcAddr: process(clk)
begin
if rising_edge(clk) then
if enable = '1' then
case nextAddr is
when nextAddrIncr =>
myAddr <= myAddrIncr;
when nextAddrIncrL =>
myAddr(7 downto 0) <= myAddrIncr(7 downto 0);
when nextAddrIncrH =>
myAddr(15 downto 8) <= myAddrIncrH;
when nextAddrDecrH =>
myAddr(15 downto 8) <= myAddrDecrH;
when nextAddrPc =>
myAddr <= PC;
when nextAddrIrq =>
myAddr <= X"FFFE";
if nmiReg = '0' then
myAddr <= X"FFFA";
end if;
when nextAddrReset =>
myAddr <= X"FFFC";
when nextAddrAbs =>
myAddr <= di & T;
when nextAddrAbsIndexed =>
myAddr <= di & indexOut(7 downto 0);
when nextAddrZeroPage =>
myAddr <= "00000000" & di;
when nextAddrZPIndexed =>
myAddr <= "00000000" & indexOut(7 downto 0);
when nextAddrStack =>
myAddr <= "00000001" & S;
when nextAddrRelative =>
myAddr(7 downto 0) <= indexOut(7 downto 0);
when others =>
null;
end case;
end if;
end if;
end process;
myAddrIncr <= myAddr + 1;
myAddrIncrH <= myAddr(15 downto 8) + 1;
myAddrDecrH <= myAddr(15 downto 8) - 1;
addr <= myAddr;
-- DMB This looked plain broken and inferred a latch
--
-- calcsync: process(clk)
-- begin
-- if enable = '1' then
-- case theCpuCycle is
-- when opcodeFetch =>
-- sync <= '1';
-- when others =>
-- sync <= '0';
-- end case;
-- end if;
-- end process;
sync <= '1' when theCpuCycle = opcodeFetch else '0';
sync_irq <= irqActive;
Regs <= std_logic_vector(myAddr) &
"00000001" & std_logic_vector(S)&
N & V & R & B & D & I & Z & C &
std_logic_vector(Y) &
std_logic_vector(X) &
std_logic_vector(A);
end architecture;
|
--------------------------------------------------------------------------------
-- Title : external SRAM Interface
-- Project : A15
--------------------------------------------------------------------------------
-- File : sram.vhd
-- Author : [email protected]
-- Organization : MEN Mikro Elektronik GmbH
-- Created : 24/01/03
--------------------------------------------------------------------------------
-- Simulator : Modelsim PE 6.6
-- Synthesis : Quartus 15.1
--------------------------------------------------------------------------------
-- Description :
--
-- Interface controller to asynchronous RAM with 1 MB.
-- Longword accesses will be performed by two SRAM accesses.
--------------------------------------------------------------------------------
-- Hierarchy:
--
--
--------------------------------------------------------------------------------
-- Copyright (c) 2016, MEN Mikro Elektronik GmbH
--
-- This program is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- History:
--------------------------------------------------------------------------------
-- $Revision: 1.1 $
--
-- $Log: sram.vhd,v $
-- Revision 1.1 2012/03/29 10:21:15 MMiehling
-- Initial Revision
--
-- Revision 1.4 2004/07/27 17:15:30 mmiehling
-- changed pci-core to 16z014
-- changed wishbone bus to wb_bus.vhd
-- added clk_trans_wb2wb.vhd
-- improved dma
--
-- Revision 1.3 2003/12/01 10:03:31 MMiehling
-- now whishbone bus
--
-- Revision 1.2 2003/06/24 13:46:54 MMiehling
-- removed burst
--
-- Revision 1.1 2003/04/01 13:04:31 MMiehling
-- Initial Revision
--
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.ALL;
ENTITY sram IS
PORT (
clk66 : IN std_logic; -- 66 MHz
rst : IN std_logic; -- global reset signal (asynch)
-- local bus
stb_i : IN std_logic;
ack_o : OUT std_logic;
we_i : IN std_logic; -- high active write enable
sel_i : IN std_logic_vector(3 DOWNTO 0); -- high active byte enables
cyc_i : IN std_logic;
dat_o : OUT std_logic_vector(31 DOWNTO 0);
dat_i : IN std_logic_vector(31 DOWNTO 0);
adr_i : IN std_logic_vector(19 DOWNTO 0);
-- pins to sram
bwn : OUT std_logic; -- global byte write enable:
bwan : OUT std_logic; -- byte a write enable:
bwbn : OUT std_logic; -- byte b write enable:
adscn : OUT std_logic; -- Synchronous Address Status Controller: .
roen : OUT std_logic; -- data output enable of sram data signals
ra : OUT std_logic_vector(18 DOWNTO 0); -- address lines:
rd_in : IN std_logic_vector(15 DOWNTO 0); -- fpga data input vector
rd_out : OUT std_logic_vector(15 DOWNTO 0); -- fpga data output vector
rd_oe : OUT std_logic -- fpga data output enable (if '1', rd_out should be driven to sram)
);
END sram;
ARCHITECTURE sram_arch OF sram IS
TYPE sram_states IS (sram_idle, sram_wait, sram_low, sram_high, sram_read_end);
SIGNAL sram_state : sram_states;
SIGNAL ra_1 : std_logic;
SIGNAL ra_int : std_logic_vector(19 DOWNTO 2);
SIGNAL roen_int : std_logic;
SIGNAL we_i_q : std_logic;
BEGIN
ra <= ra_int & ra_1;
roen <= roen_int;
--oe : PROCESS (rd_oe, rd_out, rd)
-- BEGIN
-- IF rd_oe = '1' THEN
-- rd <= rd_out AFTER 3 ns;
-- rd_in <= rd;
-- ELSE
-- rd <= (OTHERS => 'Z');
-- rd_in <= rd AFTER 3 ns;
-- END IF;
-- END PROCESS oe;
reg : PROCESS (clk66, rst)
BEGIN
IF rst = '1' THEN
ra_int <= (OTHERS => '0');
dat_o <= (OTHERS => '0');
rd_out <= (OTHERS => '0');
we_i_q <= '0';
ELSIF clk66'EVENT AND clk66 = '1' THEN
we_i_q <= we_i;
IF ra_1 = '1' THEN -- low byte
rd_out <= dat_i(15 DOWNTO 0);
ELSE -- high byte
rd_out <= dat_i(31 DOWNTO 16);
END IF;
IF ra_1 = '1' AND roen_int = '0' THEN -- low byte
dat_o(15 DOWNTO 0) <= rd_in;
ELSIF ra_1 = '0' AND roen_int = '0' THEN -- high_byte
dat_o(31 DOWNTO 16) <= rd_in;
END IF;
ra_int <= adr_i(19 DOWNTO 2);
END IF;
END PROCESS reg;
sram_fsm : PROCESS (clk66, rst)
BEGIN
IF rst = '1' THEN
ack_o <= '0';
sram_state <= sram_idle;
bwn <= '1';
bwan <= '1';
bwbn <= '1';
roen_int <= '1';
adscn <= '1';
ra_1 <= '0';
rd_oe <= '0';
ELSIF clk66'EVENT AND clk66 = '1' THEN
CASE sram_state IS
WHEN sram_idle =>
ack_o <= '0';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
roen_int <= '1';
IF stb_i = '1' AND cyc_i = '1' THEN
sram_state <= sram_wait;
IF we_i = '1' THEN -- write
adscn <= '1';
rd_oe <= '1';
ELSE -- read
adscn <= '0';
rd_oe <= '0';
END IF;
ra_1 <= '1';
ELSE
sram_state <= sram_idle;
adscn <= '1';
ra_1 <= '0';
rd_oe <= '0';
END IF;
WHEN sram_wait =>
ra_1 <= '0';
IF stb_i = '1' AND cyc_i = '1' THEN
sram_state <= sram_low;
adscn <= '0';
IF we_i = '1' THEN -- write
ack_o <= '1';
bwn <= '0';
bwan <= NOT sel_i(0);
bwbn <= NOT sel_i(1);
rd_oe <= '1';
roen_int <= '1';
ELSE -- read
ack_o <= '0';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
rd_oe <= '0';
roen_int <= '0';
END IF;
ELSE
sram_state <= sram_idle;
ack_o <= '0';
adscn <= '1';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
rd_oe <= '0';
roen_int <= '1';
END IF;
WHEN sram_low =>
sram_state <= sram_high;
ra_1 <= '1';
IF we_i = '1' THEN -- write
ack_o <= '0';
bwn <= '0';
bwan <= NOT sel_i(2);
bwbn <= NOT sel_i(3);
rd_oe <= '1';
roen_int <= '1';
adscn <= '0';
ELSE -- read
ack_o <= '0';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
rd_oe <= '0';
roen_int <= '0';
adscn <= '1';
END IF;
WHEN sram_high =>
sram_state <= sram_read_end;
adscn <= '1';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
ra_1 <= '0';
IF we_i_q = '1' THEN -- write
ack_o <= '0';
rd_oe <= '1';
roen_int <= '1';
ELSE -- read
ack_o <= '1';
rd_oe <= '0';
roen_int <= '1';
END IF;
WHEN sram_read_end =>
ack_o <= '0';
bwn <= '1';
bwan <= '1';
bwbn <= '1';
roen_int <= '1';
sram_state <= sram_idle;
ra_1 <= '0';
adscn <= '1';
rd_oe <= '0';
WHEN OTHERS =>
ack_o <= '0';
sram_state <= sram_idle;
bwn <= '1';
bwan <= '1';
bwbn <= '1';
roen_int <= '1';
adscn <= '1';
ra_1 <= '0';
rd_oe <= '0';
END CASE;
END IF;
END PROCESS sram_fsm;
END sram_arch;
|
-- libraries --------------------------------------------------------------------------------- {{{
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_textio.all;
use std.textio.all;
------------------------------------------------------------------------------------------------- }}}
package FGPU_definitions is
constant N_CU_W : natural := 3; --0 to 3
-- Bitwidth of # of CUs
constant LMEM_ADDR_W : natural := 10;
-- bitwidth of local memory address for a single PE
constant N_AXI_W : natural := 2;
-- Bitwidth of # of AXI data ports
constant SUB_INTEGER_IMPLEMENT : natural := 0;
-- implement sub-integer store operations
constant N_STATIONS_ALU : natural := 4;
-- # stations to store memory requests sourced by a single ALU
constant ATOMIC_IMPLEMENT : natural := 0;
-- implement global atomic operations
constant LMEM_IMPLEMENT : natural := 1;
-- implement local scratchpad
constant N_TAG_MANAGERS_W : natural := N_CU_W+0; -- 0 to 1
-- Bitwidth of # tag controllers per CU
constant RD_CACHE_N_WORDS_W : natural := 0;
constant RD_CACHE_FIFO_PORTB_ADDR_W : natural := 6;
constant FLOAT_IMPLEMENT : natural := 0;
constant FADD_IMPLEMENT : integer := 1;
constant FMUL_IMPLEMENT : integer := 1;
constant FDIV_IMPLEMENT : integer := 1;
constant FSQRT_IMPLEMENT : integer := 1;
constant UITOFP_IMPLEMENT : integer := 0;
constant FSLT_IMPLEMENT : integer := 0;
constant FRSQRT_IMPLEMENT : integer := 0;
constant FADD_DELAY : integer := 11;
constant UITOFP_DELAY : integer := 5;
constant FMUL_DELAY : integer := 8;
constant FDIV_DELAY : integer := 28;
constant FSQRT_DELAY : integer := 28;
constant FRSQRT_DELAY : integer := 28;
constant FSLT_DELAY : integer := 2;
constant MAX_FPU_DELAY : integer := FDIV_DELAY;
constant CACHE_N_BANKS_W : natural := 3;
-- Bitwidth of # words within a cache line. Minimum is 2
constant N_RECEIVERS_CU_W : natural := 6-N_CU_W;
-- Bitwidth of # of receivers inside the global memory controller per CU. (6-N_CU_W) will lead to 64 receivers whatever the # of CU is.
constant BURST_WORDS_W : natural := 5;
-- Bitwidth # of words within a single AXI burst
constant ENABLE_READ_PRIORIRY_PIPE : boolean := false;
constant FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo size to store outgoing memory requests from a CU
constant N_RD_FIFOS_TAG_MANAGER_W : natural := 0;
constant FINISH_FIFO_ADDR_W : natural := 3;
-- Bitwidth of the fifo depth to mark dirty cache lines to be cleared at the end
-- constant CRAM_BLOCKS : natural := 1;
-- # of CRAM replicates. Each replicate will serve some CUs (1 or 2 supported only)
constant CV_W : natural := 3;
-- bitwidth of # of PEs within a CV
constant CV_TO_CACHE_SLICE : natural := 3;
constant INSTR_READ_SLICE : boolean := true;
constant RTM_WRITE_SLICE : boolean := true;
constant WRITE_PHASE_W : natural := 1;
-- # of MSBs of the receiver index in the global memory controller which will be selected to write. These bits increments always.
-- This incrmenetation should help to balance serving the receivers
constant RCV_PRIORITY_W : natural := 3;
constant N_WF_CU_W : natural := 3;
-- bitwidth of # of WFs that can be simultaneously managed within a CU
constant AADD_ATOMIC : natural := 1;
constant AMAX_ATOMIC : natural := 1;
constant GMEM_N_BANK_W : natural := 1;
constant ID_WIDTH : natural := 6;
constant PHASE_W : natural := 3;
constant CV_SIZE : natural := 2**CV_W;
constant RD_CACHE_N_WORDS : natural := 2**RD_CACHE_N_WORDS_W;
constant WF_SIZE_W : natural := PHASE_W + CV_W;
-- A WF will be executed on the PEs of a single CV withen PAHSE_LEN cycels
constant WG_SIZE_W : natural := WF_SIZE_W + N_WF_CU_W;
-- A WG must be executed on a single CV. It contains a number of WFs which is at maximum the amount that can be managed within a CV
constant RTM_ADDR_W : natural := 1+2+N_WF_CU_W+PHASE_W; -- 1+2+3+3 = 9bit
-- The MSB if select between local indcs or other information
-- The lower 2 MSBs for d0, d1 or d2. The middle N_WF_CU_W are for the WF index with the CV. The lower LSBs are for the phase index
constant RTM_DATA_W : natural := CV_SIZE*WG_SIZE_W; -- Bitwidth of RTM data ports
constant BURST_W : natural := BURST_WORDS_W - GMEM_N_BANK_W; -- burst width in number of transfers on the axi bus
constant RD_FIFO_N_BURSTS_W : natural := 1;
constant RD_FIFO_W : natural := BURST_W + RD_FIFO_N_BURSTS_W;
constant N_TAG_MANAGERS : natural := 2**N_TAG_MANAGERS_W;
constant N_AXI : natural := 2**N_AXI_W;
constant N_WR_FIFOS_AXI_W : natural := N_TAG_MANAGERS_W-N_AXI_W;
constant INTERFCE_W_ADDR_W : natural := 14;
constant CRAM_ADDR_W : natural := 12; -- TODO
constant DATA_W : natural := 32;
constant BRAM18kb32b_ADDR_W : natural := 9;
constant BRAM36kb64b_ADDR_W : natural := 9;
constant BRAM36kb_ADDR_W : natural := 10;
constant INST_FIFO_PRE_LEN : natural := 8;
constant CV_INST_FIFO_W : natural := 3;
constant LOC_MEM_W : natural := BRAM18kb32b_ADDR_W;
constant N_PARAMS_W : natural := 4;
constant GMEM_ADDR_W : natural := 32;
constant WI_REG_ADDR_W : natural := 5;
constant N_REG_BLOCKS_W : natural := 2;
constant REG_FILE_BLOCK_W : natural := PHASE_W+WI_REG_ADDR_W+N_WF_CU_W-N_REG_BLOCKS_W; -- default=3+5+3-2=9
constant N_WR_FIFOS_W : natural := N_WR_FIFOS_AXI_W + N_AXI_W;
constant N_WR_FIFOS_AXI : natural := 2**N_WR_FIFOS_AXI_W;
constant N_WR_FIFOS : natural := 2**N_WR_FIFOS_W;
constant STAT : natural := 1;
constant STAT_LOAD : natural := 0;
-- cache & gmem controller constants
constant BRMEM_ADDR_W : natural := BRAM36kb_ADDR_W; -- default=10
constant N_RD_PORTS : natural := 4;
constant N : natural := CACHE_N_BANKS_W; -- max. 3
constant L : natural := BURST_WORDS_W-N; -- min. 2
constant M : natural := BRMEM_ADDR_W - L; -- max. 8
-- L+M = BMEM_ADDR_W = 10 = #address bits of a BRAM
-- cache size = 2^(N+L+M) words; max.=8*4KB=32KB
constant N_RECEIVERS_CU : natural := 2**N_RECEIVERS_CU_W;
constant N_RECEIVERS_W : natural := N_CU_W + N_RECEIVERS_CU_W;
constant N_RECEIVERS : natural := 2**N_RECEIVERS_W;
constant N_CU_STATIONS_W : natural := 6;
constant GMEM_WORD_ADDR_W : natural := GMEM_ADDR_W - 2;
constant TAG_W : natural := GMEM_WORD_ADDR_W -M -L -N;
constant GMEM_N_BANK : natural := 2**GMEM_N_BANK_W;
constant CACHE_N_BANKS : natural := 2**CACHE_N_BANKS_W;
constant REG_FILE_W : natural := N_REG_BLOCKS_W+REG_FILE_BLOCK_W;
constant N_REG_BLOCKS : natural := 2**N_REG_BLOCKS_W;
constant REG_ADDR_W : natural := BRAM18kb32b_ADDR_W+BRAM18kb32b_ADDR_W;
constant REG_FILE_SIZE : natural := 2**REG_ADDR_W;
constant REG_FILE_BLOCK_SIZE : natural := 2**REG_FILE_BLOCK_W;
constant GMEM_DATA_W : natural := GMEM_N_BANK * DATA_W;
constant N_PARAMS : natural := 2**N_PARAMS_W;
constant LOC_MEM_SIZE : natural := 2**LOC_MEM_W;
constant PHASE_LEN : natural := 2**PHASE_W;
constant CV_INST_FIFO_SIZE : natural := 2**CV_INST_FIFO_W;
constant N_CU : natural := 2**N_CU_W;
constant N_WF_CU : natural := 2**N_WF_CU_W;
constant WF_SIZE : natural := 2**WF_SIZE_W;
constant CRAM_SIZE : natural := 2**CRAM_ADDR_W;
constant RTM_SIZE : natural := 2**RTM_ADDR_W;
constant BRAM18kb_SIZE : natural := 2**BRAM18kb32b_ADDR_W;
constant regFile_addr : natural := 2**(INTERFCE_W_ADDR_W-1); -- "10" of the address msbs to choose the register file
constant Rstat_addr : natural := regFile_addr + 0; --address of status register in the register file
constant Rstart_addr : natural := regFile_addr + 1; --address of stat register in the register file
constant RcleanCache_addr : natural := regFile_addr + 2; --address of cleanCache register in the register file
constant RInitiate_addr : natural := regFile_addr + 3; --address of cleanCache register in the register file
constant Rstat_regFile_addr : natural := 0; --address of status register in the register file
constant Rstart_regFile_addr : natural := 1; --address of stat register in the register file
constant RcleanCache_regFile_addr : natural := 2; --address of cleanCache register in the register file
constant RInitiate_regFile_addr : natural := 3; --address of initiate register in the register file
constant N_REG_W : natural := 2;
constant PARAMS_ADDR_LOC_MEM_OFFSET : natural := LOC_MEM_SIZE - N_PARAMS;
-- constant GMEM_RQST_BUS_W : natural := GMEM_DATA_W;
-- new kernel descriptor ----------------------------------------------------------------
constant NEW_KRNL_DESC_W : natural := 5; -- length of the kernel's descripto
constant NEW_KRNL_INDX_W : natural := 4; -- bitwidth of number of kernels that can be started
constant NEW_KRNL_DESC_LEN : natural := 12;
constant WG_MAX_SIZE : natural := 2**WG_SIZE_W;
constant NEW_KRNL_DESC_MAX_LEN : natural := 2**NEW_KRNL_DESC_W;
constant NEW_KRNL_MAX_INDX : natural := 2**NEW_KRNL_INDX_W;
constant KRNL_SCH_ADDR_W : natural := NEW_KRNL_DESC_W + NEW_KRNL_INDX_W;
constant NEW_KRNL_DESC_N_WF : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 0;
constant NEW_KRNL_DESC_ID0_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 1;
constant NEW_KRNL_DESC_ID1_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 2;
constant NEW_KRNL_DESC_ID2_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 3;
constant NEW_KRNL_DESC_ID0_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 4;
constant NEW_KRNL_DESC_ID1_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 5;
constant NEW_KRNL_DESC_ID2_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 6;
constant NEW_KRNL_DESC_WG_SIZE : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 7;
constant NEW_KRNL_DESC_N_WG_0 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 8;
constant NEW_KRNL_DESC_N_WG_1 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 9;
constant NEW_KRNL_DESC_N_WG_2 : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 10;
constant NEW_KRNL_DESC_N_PARAMS : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 11;
constant PARAMS_OFFSET : natural range 0 to NEW_KRNL_DESC_MAX_LEN-1 := 16;
constant WG_SIZE_0_OFFSET : natural := 0;
constant WG_SIZE_1_OFFSET : natural := 10;
constant WG_SIZE_2_OFFSET : natural := 20;
constant N_DIM_OFFSET : natural := 30;
constant ADDR_FIRST_INST_OFFSET : natural := 0;
constant ADDR_LAST_INST_OFFSET : natural := 14;
constant N_WF_OFFSET : natural := 28;
constant N_WG_0_OFFSET : natural := 16;
constant N_WG_1_OFFSET : natural := 0;
constant N_WG_2_OFFSET : natural := 16;
constant WG_SIZE_OFFSET : natural := 0;
constant N_PARAMS_OFFSET : natural := 28;
type cram_type is array (2**CRAM_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type slv32_array is array (natural range<>) of std_logic_vector(DATA_W-1 downto 0);
type krnl_scheduler_ram_TYPE is array (2**KRNL_SCH_ADDR_W-1 downto 0) of std_logic_vector (DATA_W-1 downto 0);
type cram_addr_array is array (natural range <>) of unsigned(CRAM_ADDR_W-1 downto 0); -- range 0 to CRAM_SIZE-1;
type rtm_ram_type is array (natural range <>) of unsigned(RTM_DATA_W-1 downto 0);
type gmem_addr_array is array (natural range<>) of unsigned(GMEM_ADDR_W-1 downto 0);
type op_arith_shift_type is (op_add, op_lw, op_mult, op_bra, op_shift, op_slt, op_mov, op_ato, op_lmem);
type op_logical_type is (op_andi, op_and, op_ori, op_or, op_xor, op_xori, op_nor);
type be_array is array(natural range <>) of std_logic_vector(DATA_W/8-1 downto 0);
type gmem_be_array is array(natural range <>) of std_logic_vector(GMEM_N_BANK*DATA_W/8-1 downto 0);
type sl_array is array(natural range <>) of std_logic;
type nat_array is array(natural range <>) of natural;
type nat_2d_array is array(natural range <>, natural range <>) of natural;
type reg_addr_array is array (natural range <>) of unsigned(REG_FILE_W-1 downto 0);
type gmem_word_addr_array is array(natural range <>) of unsigned(GMEM_WORD_ADDR_W-1 downto 0);
type gmem_addr_array_no_bank is array (natural range <>) of unsigned(GMEM_WORD_ADDR_W-CACHE_N_BANKS_W-1 downto 0);
type alu_en_vec_type is array(natural range <>) of std_logic_vector(CV_SIZE-1 downto 0);
type alu_en_rdAddr_type is array(natural range <>) of unsigned(PHASE_W+N_WF_CU_W-1 downto 0);
type tag_array is array (natural range <>) of unsigned(TAG_W-1 downto 0);
type gmem_word_array is array (natural range <>) of std_logic_vector(DATA_W*GMEM_N_BANK-1 downto 0);
type wf_active_array is array (natural range <>) of std_logic_vector(N_WF_CU-1 downto 0);
type cache_addr_array is array(natural range <>) of unsigned(M+L-1 downto 0);
type cache_word_array is array(natural range <>) of std_logic_vector(CACHE_N_BANKS*DATA_W-1 downto 0);
type tag_addr_array is array(natural range <>) of unsigned(M-1 downto 0);
type reg_file_block_array is array(natural range<>) of unsigned(REG_FILE_BLOCK_W-1 downto 0);
type id_array is array(natural range<>) of std_logic_vector(ID_WIDTH-1 downto 0);
type real_array is array (natural range <>) of real;
type atomic_sgntr_array is array (natural range <>) of std_logic_vector(N_CU_STATIONS_W-1 downto 0);
attribute max_fanout: integer;
attribute keep: string;
attribute mark_debug : string;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len: in natural; file_len: in natural) return SLV32_ARRAY;
impure function init_CRAM(file_name : in string; file_len: in natural) return cram_type;
function pri_enc(datain: in std_logic_vector) return integer;
function max (LEFT, RIGHT: integer) return integer;
function min_int (LEFT, RIGHT: integer) return integer;
function clogb2 (bit_depth : integer) return integer;
--- ISA --------------------------------------------------------------------------------------
constant FAMILY_W : natural := 4;
constant CODE_W : natural := 4;
constant IMM_ARITH_W : natural := 14;
constant IMM_W : natural := 16;
constant BRANCH_ADDR_W : natural := 14;
constant FAMILY_POS : natural := 28;
constant CODE_POS : natural := 24;
constant RD_POS : natural := 0;
constant RS_POS : natural := 5;
constant RT_POS : natural := 10;
constant IMM_POS : natural := 10;
constant DIM_POS : natural := 5;
constant PARAM_POS : natural := 5;
constant BRANCH_ADDR_POS : natural := 10;
--------------- families
constant ADD_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"1";
constant SHF_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"2";
constant LGK_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"3";
constant MOV_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"4";
constant MUL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"5";
constant BRA_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"6";
constant GLS_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"7";
constant ATO_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"8";
constant CTL_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"9";
constant RTM_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"A";
constant CND_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"B";
constant FLT_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"C";
constant LSI_FAMILY : std_logic_vector(FAMILY_W-1 downto 0) := X"D";
--------------- codes
--RTM
constant LID : std_logic_vector(CODE_W-1 downto 0) := X"0"; --upper two MSBs indicate if the operation is localdx or offsetdx
constant WGOFF : std_logic_vector(CODE_W-1 downto 0) := X"1";
constant SIZE : std_logic_vector(CODE_W-1 downto 0) := X"2";
constant WGID : std_logic_vector(CODE_W-1 downto 0) := X"3";
constant WGSIZE : std_logic_vector(CODE_W-1 downto 0) := X"4";
constant LP : std_logic_vector(CODE_W-1 downto 0) := X"8";
--ADD
constant ADD : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant SUB : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant ADDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant LI : std_logic_vector(CODE_W-1 downto 0) := "1001";
constant LUI : std_logic_vector(CODE_W-1 downto 0) := "1101";
--MUL
constant MACC : std_logic_vector(CODE_W-1 downto 0) := "1000";
--BRA
constant BEQ : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant BNE : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant JSUB : std_logic_vector(CODE_W-1 downto 0) := "0100";
--GLS
constant LW : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant SW : std_logic_vector(CODE_W-1 downto 0) := "1100";
--CTL
constant RET : std_logic_vector(CODE_W-1 downto 0) := "0010";
--SHF
constant SLLI : std_logic_vector(CODE_W-1 downto 0) := "0001";
--LGK
constant CODE_AND : std_logic_vector(CODE_W-1 downto 0) := "0000";
constant CODE_ANDI : std_logic_vector(CODE_W-1 downto 0) := "0001";
constant CODE_OR : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_ORI : std_logic_vector(CODE_W-1 downto 0) := "0011";
constant CODE_XOR : std_logic_vector(CODE_W-1 downto 0) := "0100";
constant CODE_XORI : std_logic_vector(CODE_W-1 downto 0) := "0101";
constant CODE_NOR : std_logic_vector(CODE_W-1 downto 0) := "1000";
--ATO
constant CODE_AMAX : std_logic_vector(CODE_W-1 downto 0) := "0010";
constant CODE_AADD : std_logic_vector(CODE_W-1 downto 0) := "0001";
type branch_distance_vec is array(natural range <>) of unsigned(BRANCH_ADDR_W-1 downto 0);
type code_vec_type is array(natural range <>) of std_logic_vector(CODE_W-1 downto 0);
type atomic_type_vec_type is array(natural range <>) of std_logic_vector(2 downto 0);
end FGPU_definitions;
package body FGPU_definitions is
-- function called clogb2 that returns an integer which has the
--value of the ceiling of the log base 2
function clogb2 (bit_depth : integer) return integer is
variable depth : integer := bit_depth;
variable count : integer := 1;
begin
for clogb2 in 1 to bit_depth loop -- Works for up to 32 bit integers
if (bit_depth <= 2) then
count := 1;
else
if(depth <= 1) then
count := count;
else
depth := depth / 2;
count := count + 1;
end if;
end if;
end loop;
return(count);
end;
impure function init_krnl_ram(file_name : in string) return KRNL_SCHEDULER_RAM_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_bv : bit_vector(DATA_W-1 downto 0);
variable temp_mem : KRNL_SCHEDULER_RAM_type;
begin
for i in 0 to 16*32-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
-- read(init_line, temp_bv);
-- temp_mem(i) := to_stdlogicvector(temp_bv);
end loop;
return temp_mem;
end function;
function max (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end max;
function min_int (LEFT, RIGHT: integer) return integer is
begin
if LEFT > RIGHT then return RIGHT;
else return LEFT;
end if;
end min_int;
impure function init_CRAM(file_name : in string; file_len : in natural) return cram_type is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable cram : cram_type;
-- variable tmp: std_logic_vector(DATA_W-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, cram(i)); -- vivado breaks when synthesizing hread(init_line, cram(0)(i)) without giving any indication about the error
-- cram(i) := tmp;
-- if CRAM_BLOCKS > 1 then
-- for j in 1 to max(1,CRAM_BLOCKS-1) loop
-- cram(j)(i) := cram(0)(i);
-- end loop;
-- end if;
end loop;
return cram;
end function;
impure function init_SLV32_ARRAY_from_file(file_name : in string; len : in natural; file_len : in natural) return SLV32_ARRAY is
file init_file : text open read_mode is file_name;
variable init_line : line;
variable temp_mem : SLV32_ARRAY(len-1 downto 0);
begin
for i in 0 to file_len-1 loop
readline(init_file, init_line);
hread(init_line, temp_mem(i));
end loop;
return temp_mem;
end function;
function pri_enc(datain: in std_logic_vector) return integer is
variable res : integer range 0 to datain'high;
begin
res := 0;
for i in datain'high downto 1 loop
if datain(i) = '1' then
res := i;
end if;
end loop;
return res;
end function;
end FGPU_definitions;
|
----------------------------------------------------------------------------------
-- Create Date: 16:31:16 04/25/2017
-- Module Name: BANCADA_TESTE - Behavioral
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity BANCADA_TESTE is
Port ( Controle : in STD_LOGIC_VECTOR (2 downto 0);
clockFPGA : in STD_LOGIC;
LedSaida : out STD_LOGIC_VECTOR (7 downto 0));
end BANCADA_TESTE;
architecture Behavioral of BANCADA_TESTE is
signal EntradaA, EntradaB: STD_LOGIC_VECTOR(3 downto 0); --sinal auxiliar
signal VetorAB, Saida: STD_LOGIC_VECTOR(7 downto 0); --sinal auxiliar
signal contadorClock: integer; --sinal auxiliar
signal clockAux: STD_LOGIC ; --sinal auxiliar
-- 0 component Divisor de Clocks é chamado para ditar o tempo em que as entradas
-- são geradas e tamhém o tempo que cada um dos operandos e que o resultado são impressos nos LEDs adequados.
component DivisorDeClock is
port(clockIn: in std_LOGIC ;
counter : buffer integer range 0 to 100000001;
clockOut : out std_LOGIC );
end component;
-- O componente Gerador de entrada é chamado para gerar as entradas conforme o sinal de clock que é recebido
-- são gerados vetores de 8 bits de 0000 0000 até 1111 1111, onde será assumido que os 4 bits mais significativos
-- representam o vetor A e os 4 bits menos significativos representam o vetor B. Dessa forma, podemos mapear todas as
-- possíveis entradas de 4 bits.
component GeradorDeEntradas is
Port ( Saida : out STD_LOGIC_VECTOR (7 downto 0);
clock : in STD_LOGIC );
end component;
component ULA_MODULO is
port ( A: in STD_LOGIC_VECTOR (3 downto 0); -- EntradaA
B: in STD_LOGIC_VECTOR (3 downto 0); -- EntradaB
Controle : in STD_LOGIC_VECTOR (2 downto 0); -- Vetor de Controle(S2S1S0)
Z: out STD_LOGIC_VECTOR(7 downto 0) -- Saída
);
end component;
begin
divisorClock: DivisorDeClock port map(clockIn => clockFPGA, --Chamada dos componentes
counter => contadorClock,
clockOut => clockAux);
escolherEntradas: GeradorDeEntradas port map(VetorAB, clockAux); --Chamada dos componentes
EntradaA <= VetorAB(3 downto 0);
EntradaB <= VetorAB(7 downto 4);
saidas: ULA_MODULO port map(A => EntradaA, --Chamada dos componentes
B => EntradaB,
Controle => Controle,
Z => Saida);
imprimir: process(EntradaA, EntradaB, Saida, clockAux) -- lnício do processo de impressão nos LEDs
variable processCounter: integer := 2; --variável auxiliar
variable contadorA: integer; --variável auxiliar
--Primeiro é impresso nos LEDs o operando A, depois o opcrand B e, por ultimo, o resultado.
begin
if (clockAux'event and clockAux = '1') then
if processCounter = 1 then
LedSaida(0) <= EntradaA(0);
LedSaida(1) <= EntradaA(1);
LedSaida(2) <= EntradaA(2);
LedSaida(3) <= EntradaA(3);
LedSaida(4) <= '0';
LedSaida(5) <= '0';
LedSaida(6) <= '0';
LedSaida(7) <= '1';
processCounter := 2;
elsif (processCounter = 2) then
LedSaida(0) <= EntradaB(0);
LedSaida(1) <= EntradaB(1);
LedSaida(2) <= EntradaB(2);
LedSaida(3) <= EntradaB(3);
LedSaida(4) <= '0';
LedSaida(5) <= '0';
LedSaida(6) <= '1';
LedSaida(7) <= '0';
processCounter := 3;
elsif processCounter= 3 then
LedSaida(0) <= Saida(0);
LedSaida(1) <= Saida(1);
LedSaida(2) <= Saida(2);
LedSaida(3) <= Saida(3);
LedSaida(4) <= '0';
LedSaida(5) <= '1';
LedSaida(6) <= '1';
LedSaida(7 )<= '1';
end if;
end if;
end process imprimir;
end Behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc612.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:43 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00612ent IS
END c03s04b01x00p01n01i00612ent;
ARCHITECTURE c03s04b01x00p01n01i00612arch OF c03s04b01x00p01n01i00612ent IS
constant C1 : boolean := true;
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_array_file is file of record_cons_array;
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
BEGIN
TESTING: PROCESS
file filein : record_cons_array_file open write_mode is "iofile.34";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00612 - The output file will be verified by test s010254.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00612arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc612.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:43 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00612ent IS
END c03s04b01x00p01n01i00612ent;
ARCHITECTURE c03s04b01x00p01n01i00612arch OF c03s04b01x00p01n01i00612ent IS
constant C1 : boolean := true;
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_array_file is file of record_cons_array;
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
BEGIN
TESTING: PROCESS
file filein : record_cons_array_file open write_mode is "iofile.34";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00612 - The output file will be verified by test s010254.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00612arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc612.vhd,v 1.3 2001-10-29 02:12:45 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
-- **************************** --
-- Ported to VHDL 93 by port93.pl - Tue Nov 5 16:37:43 1996 --
-- **************************** --
ENTITY c03s04b01x00p01n01i00612ent IS
END c03s04b01x00p01n01i00612ent;
ARCHITECTURE c03s04b01x00p01n01i00612arch OF c03s04b01x00p01n01i00612ent IS
constant C1 : boolean := true;
constant C4 : severity_level := note;
constant C5 : integer := 3;
constant C6 : real := 3.0;
constant C7 : time := 3 ns;
constant C8 : natural := 3;
constant C9 : positive := 3;
type boolean_cons_vector is array (15 downto 0) of boolean;
type severity_level_cons_vector is array (15 downto 0) of severity_level;
type integer_cons_vector is array (15 downto 0) of integer;
type real_cons_vector is array (15 downto 0) of real;
type time_cons_vector is array (15 downto 0) of time;
type natural_cons_vector is array (15 downto 0) of natural;
type positive_cons_vector is array (15 downto 0) of positive;
constant C19 : boolean_cons_vector := (others => C1);
constant C20 : severity_level_cons_vector := (others => C4);
constant C21 : integer_cons_vector := (others => C5);
constant C22 : real_cons_vector := (others => C6);
constant C23 : time_cons_vector := (others => C7);
constant C24 : natural_cons_vector := (others => C8);
constant C25 : positive_cons_vector := (others => C9);
type record_cons_array is record
a:boolean_cons_vector;
b:severity_level_cons_vector;
c:integer_cons_vector;
d:real_cons_vector;
e:time_cons_vector;
f:natural_cons_vector;
g:positive_cons_vector;
end record;
type record_cons_array_file is file of record_cons_array;
constant C27 : record_cons_array := (C19,C20,C21,C22,C23,C24,C25);
BEGIN
TESTING: PROCESS
file filein : record_cons_array_file open write_mode is "iofile.34";
BEGIN
for i in 1 to 100 loop
write(filein, C27);
end loop;
assert FALSE
report "***PASSED TEST: c03s04b01x00p01n01i00612 - The output file will be verified by test s010254.vhd."
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b01x00p01n01i00612arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity rom is
generic(width: integer:= 32; addwidth: integer:= 4);
port(address: in unsigned(addwidth-1 downto 0);
result: out signed(width-1 downto 0));
end entity rom;
-------------------------------------------------------------------------------
architecture arch of rom is
begin -- architecture arch
process(address)
begin
case to_integer(address) is
--when 0 => result <= to_signed(6433, width); --000.1100100100001
--when 1 => result <= to_signed(3798, width); --000.0111011010110
--when 2 => result <= to_signed(2006, width); --000.0011111010110
--when 3 => result <= to_signed(1018, width); --000.0001111111010
--when 4 => result <= to_signed(511, width); --000.0000111111111
--when 5 => result <= to_signed(255, width); --000.0000011111111
--when 6 => result <= to_signed(127, width); --000.0000001111111
--when 7 => result <= to_signed(63, width); --000.0000000111111
--when 8 => result <= to_signed(31, width); --000.0000000011111
--when 9 => result <= to_signed(15, width); --000.0000000001111
--when 10 => result <= to_signed(8, width); --000.0000000001000
--when 11 => result <= to_signed(3, width); --000.0000000000011
--when 12 => result <= to_signed(1, width); --000.0000000000001
--when 13 => result <= to_signed(0, width); --000.0000000000000
--when others => result <= to_signed(0, width);
when 0 => result <= to_signed(421657428, width); --000.11001001000011111101101010100
when 1 => result <= to_signed(248918914, width); --000.01110110101100011001110000010
when 2 => result <= to_signed(131521918, width); --000.00111110101101101110101111110
when 3 => result <= to_signed(66762579, width); --000.00011111110101011011101010011
when 4 => result <= to_signed(33510843, width); --000.00001111111110101010110111011
when 5 => result <= to_signed(16771757, width); --000.00000111111111110101010101101
when 6 => result <= to_signed(8387925, width); --000.00000011111111111110101010101
when 7 => result <= to_signed(4194218, width); --000.00000001111111111111110101010
when 8 => result <= to_signed(2097141, width); --000.00000000111111111111111110101
when 9 => result <= to_signed(1048574, width); --000.00000000011111111111111111110
when 10 => result <= to_signed(524287, width); --000.00000000001111111111111111111
when 11 => result <= to_signed(262143, width); --000.00000000000111111111111111111
when 12 => result <= to_signed(131071, width); --000.00000000000011111111111111111
when 13 => result <= to_signed(65535, width); --000.00000000000001111111111111111
when others => result <= to_signed(0, width);
end case;
end process;
end architecture arch;
-------------------------------------------------------------------------------
|
-- NEED RESULT: ARCH00030.P1: Target of a variable assignment may be a simple name passed
-- NEED RESULT: ARCH00030.P2: Target of a variable assignment may be a simple name passed
-- NEED RESULT: ARCH00030.P3: Target of a variable assignment may be a simple name passed
-- NEED RESULT: ARCH00030.P4: Target of a variable assignment may be a simple name passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00030
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 8.4 (1)
-- 8.4 (3)
--
-- DESIGN UNIT ORDERING:
--
-- E00000(ARCH00030)
-- ENT00030_Test_Bench(ARCH00030_Test_Bench)
--
-- REVISION HISTORY:
--
-- 29-JUN-1987 - initial revision
--
-- NOTES:
--
-- self-checking
-- automatically generated
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00030 of E00000 is
signal Dummy : Boolean := false ;
--
begin
P1 :
process ( Dummy )
variable v_boolean : boolean :=
c_boolean_1 ;
variable v_bit : bit :=
c_bit_1 ;
variable v_severity_level : severity_level :=
c_severity_level_1 ;
variable v_character : character :=
c_character_1 ;
variable v_st_enum1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer : integer :=
c_integer_1 ;
variable v_st_int1 : st_int1 :=
c_st_int1_1 ;
variable v_time : time :=
c_time_1 ;
variable v_st_phys1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real : real :=
c_real_1 ;
variable v_st_real1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
begin
v_boolean := c_boolean_2 ;
v_bit := c_bit_2 ;
v_severity_level := c_severity_level_2 ;
v_character := c_character_2 ;
v_st_enum1 := c_st_enum1_2 ;
v_integer := c_integer_2 ;
v_st_int1 := c_st_int1_2 ;
v_time := c_time_2 ;
v_st_phys1 := c_st_phys1_2 ;
v_real := c_real_2 ;
v_st_real1 := c_st_real1_2 ;
v_st_rec1 := c_st_rec1_2 ;
v_st_rec2 := c_st_rec2_2 ;
v_st_rec3 := c_st_rec3_2 ;
v_st_arr1 := c_st_arr1_2 ;
v_st_arr2 := c_st_arr2_2 ;
v_st_arr3 := c_st_arr3_2 ;
--
correct := correct and
v_boolean = c_boolean_2 ;
correct := correct and
v_bit = c_bit_2 ;
correct := correct and
v_severity_level = c_severity_level_2 ;
correct := correct and
v_character = c_character_2 ;
correct := correct and
v_st_enum1 = c_st_enum1_2 ;
correct := correct and
v_integer = c_integer_2 ;
correct := correct and
v_st_int1 = c_st_int1_2 ;
correct := correct and
v_time = c_time_2 ;
correct := correct and
v_st_phys1 = c_st_phys1_2 ;
correct := correct and
v_real = c_real_2 ;
correct := correct and
v_st_real1 = c_st_real1_2 ;
correct := correct and
v_st_rec1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3 = c_st_arr3_2 ;
--
test_report ( "ARCH00030.P1" ,
"Target of a variable assignment may be a " &
"simple name" ,
correct) ;
end process P1 ;
--
P2 :
process ( Dummy )
variable correct : boolean := true ;
--
procedure Proc1 is
variable v_boolean : boolean :=
c_boolean_1 ;
variable v_bit : bit :=
c_bit_1 ;
variable v_severity_level : severity_level :=
c_severity_level_1 ;
variable v_character : character :=
c_character_1 ;
variable v_st_enum1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer : integer :=
c_integer_1 ;
variable v_st_int1 : st_int1 :=
c_st_int1_1 ;
variable v_time : time :=
c_time_1 ;
variable v_st_phys1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real : real :=
c_real_1 ;
variable v_st_real1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
begin
v_boolean := c_boolean_2 ;
v_bit := c_bit_2 ;
v_severity_level := c_severity_level_2 ;
v_character := c_character_2 ;
v_st_enum1 := c_st_enum1_2 ;
v_integer := c_integer_2 ;
v_st_int1 := c_st_int1_2 ;
v_time := c_time_2 ;
v_st_phys1 := c_st_phys1_2 ;
v_real := c_real_2 ;
v_st_real1 := c_st_real1_2 ;
v_st_rec1 := c_st_rec1_2 ;
v_st_rec2 := c_st_rec2_2 ;
v_st_rec3 := c_st_rec3_2 ;
v_st_arr1 := c_st_arr1_2 ;
v_st_arr2 := c_st_arr2_2 ;
v_st_arr3 := c_st_arr3_2 ;
--
correct := correct and
v_boolean = c_boolean_2 ;
correct := correct and
v_bit = c_bit_2 ;
correct := correct and
v_severity_level = c_severity_level_2 ;
correct := correct and
v_character = c_character_2 ;
correct := correct and
v_st_enum1 = c_st_enum1_2 ;
correct := correct and
v_integer = c_integer_2 ;
correct := correct and
v_st_int1 = c_st_int1_2 ;
correct := correct and
v_time = c_time_2 ;
correct := correct and
v_st_phys1 = c_st_phys1_2 ;
correct := correct and
v_real = c_real_2 ;
correct := correct and
v_st_real1 = c_st_real1_2 ;
correct := correct and
v_st_rec1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3 = c_st_arr3_2 ;
--
end Proc1 ;
begin
Proc1 ;
test_report ( "ARCH00030.P2" ,
"Target of a variable assignment may be a " &
"simple name" ,
correct) ;
end process P2 ;
--
P3 :
process ( Dummy )
variable v_boolean : boolean :=
c_boolean_1 ;
variable v_bit : bit :=
c_bit_1 ;
variable v_severity_level : severity_level :=
c_severity_level_1 ;
variable v_character : character :=
c_character_1 ;
variable v_st_enum1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer : integer :=
c_integer_1 ;
variable v_st_int1 : st_int1 :=
c_st_int1_1 ;
variable v_time : time :=
c_time_1 ;
variable v_st_phys1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real : real :=
c_real_1 ;
variable v_st_real1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 is
begin
v_boolean := c_boolean_2 ;
v_bit := c_bit_2 ;
v_severity_level := c_severity_level_2 ;
v_character := c_character_2 ;
v_st_enum1 := c_st_enum1_2 ;
v_integer := c_integer_2 ;
v_st_int1 := c_st_int1_2 ;
v_time := c_time_2 ;
v_st_phys1 := c_st_phys1_2 ;
v_real := c_real_2 ;
v_st_real1 := c_st_real1_2 ;
v_st_rec1 := c_st_rec1_2 ;
v_st_rec2 := c_st_rec2_2 ;
v_st_rec3 := c_st_rec3_2 ;
v_st_arr1 := c_st_arr1_2 ;
v_st_arr2 := c_st_arr2_2 ;
v_st_arr3 := c_st_arr3_2 ;
--
end Proc1 ;
begin
Proc1 ;
correct := correct and
v_boolean = c_boolean_2 ;
correct := correct and
v_bit = c_bit_2 ;
correct := correct and
v_severity_level = c_severity_level_2 ;
correct := correct and
v_character = c_character_2 ;
correct := correct and
v_st_enum1 = c_st_enum1_2 ;
correct := correct and
v_integer = c_integer_2 ;
correct := correct and
v_st_int1 = c_st_int1_2 ;
correct := correct and
v_time = c_time_2 ;
correct := correct and
v_st_phys1 = c_st_phys1_2 ;
correct := correct and
v_real = c_real_2 ;
correct := correct and
v_st_real1 = c_st_real1_2 ;
correct := correct and
v_st_rec1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3 = c_st_arr3_2 ;
--
test_report ( "ARCH00030.P3" ,
"Target of a variable assignment may be a " &
"simple name" ,
correct) ;
end process P3 ;
--
P4 :
process ( Dummy )
variable v_boolean : boolean :=
c_boolean_1 ;
variable v_bit : bit :=
c_bit_1 ;
variable v_severity_level : severity_level :=
c_severity_level_1 ;
variable v_character : character :=
c_character_1 ;
variable v_st_enum1 : st_enum1 :=
c_st_enum1_1 ;
variable v_integer : integer :=
c_integer_1 ;
variable v_st_int1 : st_int1 :=
c_st_int1_1 ;
variable v_time : time :=
c_time_1 ;
variable v_st_phys1 : st_phys1 :=
c_st_phys1_1 ;
variable v_real : real :=
c_real_1 ;
variable v_st_real1 : st_real1 :=
c_st_real1_1 ;
variable v_st_rec1 : st_rec1 :=
c_st_rec1_1 ;
variable v_st_rec2 : st_rec2 :=
c_st_rec2_1 ;
variable v_st_rec3 : st_rec3 :=
c_st_rec3_1 ;
variable v_st_arr1 : st_arr1 :=
c_st_arr1_1 ;
variable v_st_arr2 : st_arr2 :=
c_st_arr2_1 ;
variable v_st_arr3 : st_arr3 :=
c_st_arr3_1 ;
--
variable correct : boolean := true ;
--
procedure Proc1 (
p_boolean : inout boolean
; p_bit : inout bit
; p_severity_level : inout severity_level
; p_character : inout character
; p_st_enum1 : inout st_enum1
; p_integer : inout integer
; p_st_int1 : inout st_int1
; p_time : inout time
; p_st_phys1 : inout st_phys1
; p_real : inout real
; p_st_real1 : inout st_real1
; p_st_rec1 : inout st_rec1
; p_st_rec2 : inout st_rec2
; p_st_rec3 : inout st_rec3
; p_st_arr1 : inout st_arr1
; p_st_arr2 : inout st_arr2
; p_st_arr3 : inout st_arr3
)
is
begin
p_boolean := c_boolean_2 ;
p_bit := c_bit_2 ;
p_severity_level := c_severity_level_2 ;
p_character := c_character_2 ;
p_st_enum1 := c_st_enum1_2 ;
p_integer := c_integer_2 ;
p_st_int1 := c_st_int1_2 ;
p_time := c_time_2 ;
p_st_phys1 := c_st_phys1_2 ;
p_real := c_real_2 ;
p_st_real1 := c_st_real1_2 ;
p_st_rec1 := c_st_rec1_2 ;
p_st_rec2 := c_st_rec2_2 ;
p_st_rec3 := c_st_rec3_2 ;
p_st_arr1 := c_st_arr1_2 ;
p_st_arr2 := c_st_arr2_2 ;
p_st_arr3 := c_st_arr3_2 ;
--
end Proc1 ;
begin
Proc1 (
v_boolean
, v_bit
, v_severity_level
, v_character
, v_st_enum1
, v_integer
, v_st_int1
, v_time
, v_st_phys1
, v_real
, v_st_real1
, v_st_rec1
, v_st_rec2
, v_st_rec3
, v_st_arr1
, v_st_arr2
, v_st_arr3
) ;
correct := correct and
v_boolean = c_boolean_2 ;
correct := correct and
v_bit = c_bit_2 ;
correct := correct and
v_severity_level = c_severity_level_2 ;
correct := correct and
v_character = c_character_2 ;
correct := correct and
v_st_enum1 = c_st_enum1_2 ;
correct := correct and
v_integer = c_integer_2 ;
correct := correct and
v_st_int1 = c_st_int1_2 ;
correct := correct and
v_time = c_time_2 ;
correct := correct and
v_st_phys1 = c_st_phys1_2 ;
correct := correct and
v_real = c_real_2 ;
correct := correct and
v_st_real1 = c_st_real1_2 ;
correct := correct and
v_st_rec1 = c_st_rec1_2 ;
correct := correct and
v_st_rec2 = c_st_rec2_2 ;
correct := correct and
v_st_rec3 = c_st_rec3_2 ;
correct := correct and
v_st_arr1 = c_st_arr1_2 ;
correct := correct and
v_st_arr2 = c_st_arr2_2 ;
correct := correct and
v_st_arr3 = c_st_arr3_2 ;
--
test_report ( "ARCH00030.P4" ,
"Target of a variable assignment may be a " &
"simple name" ,
correct) ;
end process P4 ;
--
end ARCH00030 ;
--
entity ENT00030_Test_Bench is
end ENT00030_Test_Bench ;
--
architecture ARCH00030_Test_Bench of ENT00030_Test_Bench is
begin
L1:
block
component UUT
end component ;
for CIS1 : UUT use entity WORK.E00000 ( ARCH00030 ) ;
begin
CIS1 : UUT ;
end block L1 ;
end ARCH00030_Test_Bench ;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2529.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02529ent IS
END c07s03b05x00p06n04i02529ent;
ARCHITECTURE c07s03b05x00p06n04i02529arch OF c07s03b05x00p06n04i02529ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.5);
assert NOT((V1 = 10) or ( V1 = 11 ))
report "***PASSED TEST: c07s03b05x00p06n04i02529"
severity NOTE;
assert ((V1 = 10) or ( V1 = 11 ))
report "***FAILED TEST: c07s03b05x00p06n04i02529 - The conversion of a floating point to an integer point, if the value is halfway between two integers, rounding may be up or down."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02529arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2529.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02529ent IS
END c07s03b05x00p06n04i02529ent;
ARCHITECTURE c07s03b05x00p06n04i02529arch OF c07s03b05x00p06n04i02529ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.5);
assert NOT((V1 = 10) or ( V1 = 11 ))
report "***PASSED TEST: c07s03b05x00p06n04i02529"
severity NOTE;
assert ((V1 = 10) or ( V1 = 11 ))
report "***FAILED TEST: c07s03b05x00p06n04i02529 - The conversion of a floating point to an integer point, if the value is halfway between two integers, rounding may be up or down."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02529arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2529.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s03b05x00p06n04i02529ent IS
END c07s03b05x00p06n04i02529ent;
ARCHITECTURE c07s03b05x00p06n04i02529arch OF c07s03b05x00p06n04i02529ent IS
BEGIN
TESTING: PROCESS
variable V1 : Integer;
BEGIN
V1 := Integer (10.5);
assert NOT((V1 = 10) or ( V1 = 11 ))
report "***PASSED TEST: c07s03b05x00p06n04i02529"
severity NOTE;
assert ((V1 = 10) or ( V1 = 11 ))
report "***FAILED TEST: c07s03b05x00p06n04i02529 - The conversion of a floating point to an integer point, if the value is halfway between two integers, rounding may be up or down."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s03b05x00p06n04i02529arch;
|
--------------------------------------------------------------------------------
-- Copyright (c) 2009 Alan Daly. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ /
-- \ \ \/
-- \ \
-- / / Filename : AtomFpga_PapilioOne.vhd
-- /___/ /\ Timestamp : 02/03/2013 06:17:50
-- \ \ / \
-- \___\/\___\
--
--Design Name: AtomFpga_PapilioOne
--Device: spartan3E
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity AtomFpga_PapilioOne is
port (clk_32M00 : in std_logic;
ps2_clk : in std_logic;
ps2_data : in std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
ERST : in std_logic;
red : out std_logic_vector (2 downto 0);
green : out std_logic_vector (2 downto 0);
blue : out std_logic_vector (2 downto 0);
vsync : out std_logic;
hsync : out std_logic;
audiol : out std_logic;
audioR : out std_logic;
SDMISO : in std_logic;
SDSS : out std_logic;
SDCLK : out std_logic;
SDMOSI : out std_logic;
RxD : in std_logic;
TxD : out std_logic;
LED1 : out std_logic;
LED2 : out std_logic;
LED3 : out std_logic;
LED4 : out std_logic
);
end AtomFpga_PapilioOne;
architecture behavioral of AtomFpga_PapilioOne is
signal clock_16 : std_logic;
signal clock_25 : std_logic;
signal clock_32 : std_logic;
signal ERSTn : std_logic;
signal RomCE1 : std_logic;
signal RomCE2 : std_logic;
signal RamCE1 : std_logic;
signal RamCE2 : std_logic;
signal ExternCE : std_logic;
signal ExternWE : std_logic;
signal ExternA : std_logic_vector (18 downto 0);
signal ExternDin : std_logic_vector (7 downto 0);
signal ExternDout : std_logic_vector (7 downto 0);
signal RamDout1 : std_logic_vector (7 downto 0);
signal RamDout2 : std_logic_vector (7 downto 0);
signal RomDout1 : std_logic_vector (7 downto 0);
signal RomDout2 : std_logic_vector (7 downto 0);
begin
inst_dcm4 : entity work.dcm4 port map(
CLKIN_IN => clk_32M00,
CLK0_OUT => clock_32,
CLKFX_OUT => clock_25
);
inst_dcm5 : entity work.dcm5 port map(
CLKIN_IN => clk_32M00,
CLKFX_OUT => clock_16
);
ram_0000_07ff : entity work.RAM_2K port map(
clk => clock_16,
we_uP => ExternWE,
ce => RamCE1,
addr_uP => ExternA(10 downto 0),
D_uP => ExternDin,
Q_uP => RamDout1
);
ram_2000_3fff : entity work.RAM_8K port map(
clk => clock_16,
we_uP => ExternWE,
ce => RamCE2,
addr_uP => ExternA(12 downto 0),
D_uP => ExternDin,
Q_uP => RamDout2
);
rom_c000_ffff : entity work.InternalROM port map(
CLK => clock_16,
ADDR => ExternA(16 downto 0),
DATA => RomDout1
);
rom_a000 : entity work.fpgautils port map(
CLK => clock_16,
ADDR => ExternA(11 downto 0),
DATA => RomDout2
);
RamCE1 <= '1' when ExternCE = '1' and ExternA(15 downto 11) = "00000" else '0';
RamCE2 <= '1' when ExternCE = '1' and ExternA(15 downto 13) = "001" else '0';
RomCE1 <= '1' when ExternCE = '1' and ExternA(15 downto 14) = "11" else '0';
RomCE2 <= '1' when ExternCE = '1' and ExternA(15 downto 12) = "1010" else '0';
ExternDout(7 downto 0) <= RamDout1 when RamCE1 = '1' else
RamDout2 when RamCE2 = '1' else
RomDout1 when RomCE1 = '1' else
RomDout2 when RomCE2 = '1' else
"11110001";
ERSTn <= not ERST;
inst_AtomFpga_Core : entity work.AtomFpga_Core
generic map (
CImplSDDOS => true,
CImplAtoMMC2 => false,
CImplGraphicsExt => true,
CImplSoftChar => false,
CImplSID => true,
CImplVGA80x40 => true,
CImplHWScrolling => true,
CImplMouse => true,
CImplUart => true,
CImplDoubleVideo => false,
CImplRamRomNone => true,
CImplRamRomPhill => false,
CImplRamRomAtom2015 => false,
CImplRamRomSchakelKaart => false,
MainClockSpeed => 16000000,
DefaultBaud => 115200
)
port map(
clk_vga => clock_25,
clk_main => clock_16,
clk_avr => clock_16,
clk_dac => clock_32,
clk_32M00 => clock_32,
ps2_clk => ps2_clk,
ps2_data => ps2_data,
ps2_mouse_clk => ps2_mouse_clk,
ps2_mouse_data => ps2_mouse_data,
powerup_reset_n => ERSTn,
ext_reset_n => '1',
int_reset_n => open,
red => red,
green => green,
blue => blue,
vsync => vsync,
hsync => hsync,
phi2 => open,
ExternCE => ExternCE,
ExternWE => ExternWE,
ExternA => ExternA,
ExternDin => ExternDin,
ExternDout => ExternDout,
sid_audio => audiol,
sid_audio_d => open,
atom_audio => audioR,
SDMISO => SDMISO,
SDSS => SDSS,
SDCLK => SDCLK,
SDMOSI => SDMOSI,
uart_RxD => RxD,
uart_TxD => TxD,
avr_RxD => '1',
avr_TxD => open,
LED1 => LED1,
LED2 => LED2,
charSet => '0'
);
LED3 <= '0';
LED4 <= '0';
end behavioral;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity execute_stage is
port(
clk : in std_logic;
reset_n : in std_logic;
stall : in std_logic;
noop_in : in std_logic;
--inputs
ubranch_in : in std_logic;
cbranch_in : in std_logic;
ex_w_addr : in std_logic_vector(31 downto 0);
ex_w_data : in std_logic_vector(31 downto 0);
ex_we : in std_logic;
start_address : in std_logic_vector(31 downto 0);
a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
c_in : in std_logic_vector(31 downto 0);
addr_a : in std_logic_vector(31 downto 0);
addr_b : in std_logic_vector(31 downto 0);
addr_c : in std_logic_vector(31 downto 0);
next_pc : in std_logic_vector(31 downto 0);
--outputs
cbranch_out : out std_logic;
cbranch_addr : out std_logic_vector(31 downto 0);
-- memory
da_in : in std_logic_vector(31 downto 0);
db_in : in std_logic_vector(31 downto 0);
w_data : out std_logic_vector(31 downto 0);
w_addr : out std_logic_vector(31 downto 0);
we_out : out std_logic
);
end entity;
architecture a1 of execute_stage is
--signals
signal da_fwd : std_logic_vector(31 downto 0);
signal db_fwd : std_logic_vector(31 downto 0);
-- --for self-modifying instruction forwarding
-- signal a_fwd : std_logic_vector(31 downto 0);
-- signal b_fwd : std_logic_vector(31 downto 0);
-- signal c_fwd : std_logic_vector(31 downto 0);
signal sub : signed(31 downto 0);
signal cbranch : std_logic;
signal we : std_logic;
begin
--determine forwarding
da_fwd <= ex_w_data when (a_in = ex_w_addr and ex_we = '1') else da_in;
db_fwd <= ex_w_data when (b_in = ex_w_addr and ex_we = '1') else db_in;
-- --self-modifying instruction forwarding (NOT USED. To enable this, replace instances of a with a_fwd, b with b_fwd ...)
-- a_fwd <= ex_db when (addr_a = ex_b) else a_in;
-- b_fwd <= ex_db when (addr_b = ex_b) else b_in;
-- c_fwd <= ex_db when (addr_c = ex_b) else c_in;
--'execute'
sub <= signed(db_fwd) - signed(da_fwd);
--determine cbranch
cbranch <= '1' when (sub <= 0 and not(noop_in = '1') and not(ubranch_in = '1') and not(next_pc = c_in)) else '0';
--determine whether to write
we <= '1' when (not(noop_in = '1') and not(cbranch_in = '1')) else '0';
process(clk, reset_n, start_address) begin
if(reset_n = '0') then
--initial values
w_data <= "00000000000000000000000000000000";
w_addr <= std_logic_vector(unsigned(start_address) + to_unsigned(7,32)); --as if the third instruction is executing
we_out <= '0';
cbranch_out <= '0';
elsif (rising_edge(clk)) then
if(stall = '0') then
cbranch_out <= cbranch;
cbranch_addr <= c_in;
if(not(noop_in = '1')) then w_addr <= b_in; end if; --to prevent undefined address output after reset
w_data <= std_logic_vector(sub);
we_out <= we;
else
--hold previous outputs on stall (automatic)
end if;
end if;
end process;
end architecture;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "KC705"; -- KC705 - Xilinx Kintex 7 reference design board: XC7K325T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Thomas B. Preusser
-- Martin Zabel
-- Patrick Lehmann
--
-- Package: Project specific configuration.
--
-- Description:
-- ------------------------------------
-- This file was created from template <PoCRoot>/src/common/my_config.template.vhdl.
--
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany,
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library PoC;
package my_config is
-- Change these lines to setup configuration.
constant MY_BOARD : string := "KC705"; -- KC705 - Xilinx Kintex 7 reference design board: XC7K325T
constant MY_DEVICE : string := "None"; -- infer from MY_BOARD
-- For internal use only
constant MY_VERBOSE : boolean := FALSE;
end package;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity SM_mem_init_test is
Port (clock : in STD_LOGIC;
reset : in STD_LOGIC;
RAM_wait : in STD_LOGIC;
memory_data_bus : inout STD_LOGIC_VECTOR(15 downto 0);
memory_address_bus : out STD_LOGIC_VECTOR(22 downto 0);
SM_reset : out STD_LOGIC;
RAM_ce : out STD_LOGIC;
RAM_we : out STD_LOGIC;
RAM_oe : out STD_LOGIC;
RAM_lb : out STD_LOGIC;
RAM_ub : out STD_LOGIC;
RAM_cre : out STD_LOGIC;
RAM_adv : out STD_LOGIC;
RAM_clk : out STD_LOGIC);
end entity;
architecture Behavioral of SM_mem_init_test is
component four_dig_7seg is
Port ( clock : in STD_LOGIC;
display_data : in STD_LOGIC_VECTOR (15 downto 0);
anodes : out STD_LOGIC_VECTOR (3 downto 0);
to_display : out STD_LOGIC_VECTOR (6 downto 0));
end component;
signal state : STD_LOGIC_VECTOR(4 downto 0);
signal SM_wait_counter : STD_LOGIC_VECTOR(2 downto 0);
signal clk_100MHz : STD_LOGIC;
signal RAM_clk_en : STD_LOGIC;
signal output_enable : STD_LOGIC;
signal memory_data_bus_in : STD_LOGIC_VECTOR(15 downto 0);
signal memory_data_bus_out : STD_LOGIC_VECTOR(15 downto 0);
signal collected_data : STD_LOGIC_VECTOR(15 downto 0);
begin
--The state machine
process (clk_100MHz, reset)
begin
if reset = '1' then
state <= "00000";
SM_reset <= '1';
SM_wait_counter <= "000";
output_enable <= '0';
RAM_ce <= '1';
RAM_we <= '1';
RAM_oe <= '0';
RAM_adv <= '1';
RAM_lb <= '0';
RAM_ub <= '0';
RAM_cre <= '0';
RAM_clk_en <= '0';
elsif falling_edge(clk_100MHz) then
case state is
--These first states put the memory into synchronous mode
--Read cycle one
when "00000" =>
SM_reset <= '1';
RAM_ce <= '0';
RAM_we <= '1';
RAM_oe <= '0';
RAM_lb <= '0';
RAM_ub <= '0';
RAM_clk_en <= '0';
RAM_cre <= '0';
memory_address_bus <= (others => '1');
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00001";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00000";
end if;
when "00001" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00010";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00001";
end if;
--Read cycle two
when "00010" =>
RAM_ce <= '0';
memory_address_bus <= (others => '1');
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00011";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00010";
end if;
when "00011" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00100";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00011";
end if;
--Write cycle one
when "00100" =>
--Setup state for the first write cycle
RAM_oe <= '1';
RAM_ce <= '0';
memory_address_bus <= (others => '1');
output_enable <= '1';
memory_data_bus_out <= x"0001";
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00101";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00100";
end if;
when "00101" =>
--Second half of the first write cycle
RAM_we <= '0';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00110";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00101";
end if;
when "00110" =>
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "00111";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00110";
end if;
--Second write cycle
when "00111" =>
RAM_ce <= '0';
memory_data_bus_out <= b"0001110101001111"; --BCR data
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "01000";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "00111";
end if;
when "01000" =>
output_enable <= '0';
RAM_ce <= '1';
if SM_wait_counter = "111" then
SM_wait_counter <= "000";
state <= "01001";
else
SM_wait_counter <= SM_wait_counter + 1;
state <= "01000";
end if;
--End of initialization, begin normal operation
--Wait state, also enable RAM_clk
when "01001" =>
RAM_clk_en <= '1';
output_enable <= '1';
state <= "01010";
--Set up the signals for a write
when "01010" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_we <= '0';
RAM_oe <= '1';
memory_address_bus <= b"00000000000000000000001";
state <= "01011";
--Wait for RAM_wait
when "01100" =>
RAM_adv <= '0';
if RAM_wait = '1' then
state <= "01101";
else
state <= "01100";
end if;
--Begin the writes
when "01101" =>
memory_data_bus_out <= x"000F";
state <= "01110";
when "01110" =>
memory_data_bus_out <= x"000E";
state <= "01111";
when "01111" =>
memory_data_bus_out <= x"000D";
state <= "10000";
when "10000" =>
memory_data_bus_out <= x"000C";
state <= "10001";
--End the write
when "10001" =>
RAM_ce <= '1';
state <= "10010";
--A wait cycle
when "10010" =>
state <= "10011";
--Set up the signals for a read
when "10011" =>
RAM_ce <= '0';
RAM_adv <= '0';
RAM_oe <= '0';
RAM_we <= '1';
output_enable <= '0';
memory_address_bus <= b"00000000000000000000001";
state <= "10100";
--Read into a register
when "10100" =>
collected_data(3 downto 0) <= memory_data_bus_in(3 downto 0);
state <= "10101";
when "10101" =>
collected_data(7 downto 4) <= memory_data_bus_in(3 downto 0);
state <= "10110";
when "10110" =>
collected_data(11 downto 8) <= memory_data_bus_in(3 downto 0);
state <= "10111";
when "10111" =>
collected_data(15 downto 12) <= memory_data_bus_in(3 downto 0);
state <= "11000";
--End the read and wait here
when "11000" =>
RAM_ce <= '1';
RAM_oe <= '1';
RAM_we <= '1';
state <= "11000";
when others =>
state <= "00000";
end case;
end if;
end process;
--A tristate buffer for the memory data bus
tristate : process (output_enable, memory_data_bus_in)
begin
if output_enable = '1' then
memory_data_bus <= memory_data_bus_out;
else
memory_data_bus <= (others => 'Z');
end if;
memory_data_bus_in <= memory_data_bus;
end process;
--Handles the enabling of the RAM clock
RAM_clock : process (RAM_clk, RAM_clk_en)
begin
if RAM_clk_en = '1' then
RAM_clk <= clk_100MHz;
else
RAM_clk <= 'Z';
end if;
end process;
display: four_dig_7seg port map (clock => clock,
display_data => collected_data,
anodes => anodes,
to_display => decoder_out);
clk_100MHz <= clock;
end Behavioral; |
--4选1信号选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY MUX41 IS
PORT(X:IN STD_LOGIC_VECTOR(3 DOWNTO 0);
A,B:IN STD_LOGIC;
Y:OUT STD_LOGIC);
END ENTITY MUX41;
ARCHITECTURE ART OF MUX41 IS
SIGNAL SEL:STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
SEL<=B&A;
PROCESS(X,SEL) IS
BEGIN
IF(SEL="00") THEN Y<=X(0);
ELSIF(SEL="01") THEN Y<=X(1);
ELSIF(SEL="11") THEN Y<=X(2);
ELSE Y<=X(3);
END IF;
END PROCESS;
END ARCHITECTURE ART; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3023.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library WORK, STD;
ENTITY c11s02b00x00p05n01i03023ent IS
END c11s02b00x00p05n01i03023ent;
ARCHITECTURE c11s02b00x00p05n01i03023arch OF c11s02b00x00p05n01i03023ent IS
signal S1 : STD.STANDARD.bit; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 20 ns;
wait for 30 ns;
assert NOT( S1 = '1' )
report "***PASSED TEST: c11s02b00x00p05n01i03023"
severity NOTE;
assert ( S1 = '1' )
report "***FAILED TEST: c11s02b00x00p05n01i03023 - Library logical name may be referenced in the design unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s02b00x00p05n01i03023arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3023.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library WORK, STD;
ENTITY c11s02b00x00p05n01i03023ent IS
END c11s02b00x00p05n01i03023ent;
ARCHITECTURE c11s02b00x00p05n01i03023arch OF c11s02b00x00p05n01i03023ent IS
signal S1 : STD.STANDARD.bit; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 20 ns;
wait for 30 ns;
assert NOT( S1 = '1' )
report "***PASSED TEST: c11s02b00x00p05n01i03023"
severity NOTE;
assert ( S1 = '1' )
report "***FAILED TEST: c11s02b00x00p05n01i03023 - Library logical name may be referenced in the design unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s02b00x00p05n01i03023arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3023.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
library WORK, STD;
ENTITY c11s02b00x00p05n01i03023ent IS
END c11s02b00x00p05n01i03023ent;
ARCHITECTURE c11s02b00x00p05n01i03023arch OF c11s02b00x00p05n01i03023ent IS
signal S1 : STD.STANDARD.bit; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
S1 <= '1' after 20 ns;
wait for 30 ns;
assert NOT( S1 = '1' )
report "***PASSED TEST: c11s02b00x00p05n01i03023"
severity NOTE;
assert ( S1 = '1' )
report "***FAILED TEST: c11s02b00x00p05n01i03023 - Library logical name may be referenced in the design unit."
severity ERROR;
wait;
END PROCESS TESTING;
END c11s02b00x00p05n01i03023arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HAZARD_RESOLVE_global is
PORT(
select_signal : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture resolve of HAZARD_RESOLVE_global is
signal data_present : std_logic;
signal buffer_output : std_logic_vector(31 downto 0);
signal data_buffer : std_logic_vector(31 downto 0);
signal hazard_rising_edge : std_logic;
begin
--edge capture
hazard_rising_edge <= hazard_advanced and (hazard_advanced xor hazard);
data_present <= select_signal(15) or select_signal(14) or select_signal(13) or select_signal(12) or
select_signal(11) or select_signal(10) or select_signal(9) or select_signal(8) or
select_signal(7) or select_signal(6) or select_signal(5) or select_signal(4) or
select_signal(3) or select_signal(2) or select_signal(1) or select_signal(0);
buffering : process (CLK, RESET_n, hazard, data_present, data) begin
if (RESET_n = '0') then
buffer_output <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (data_present = '1' and hazard = '1') then
buffer_output <= data;
end if;
end if;
end process;
hazard_detect : process (hazard, data, data_buffer, RESET_n, buffer_output, data_present, CLK) begin
if (RESET_n = '0') then
data_buffer <= "00000000000000000000000000000000";
elsif (rising_edge(CLK))then --was on rising edge hazard
if (hazard_rising_edge = '1') then --this if never existed
if (data_present = '1') then
data_buffer <= data;
else
data_buffer <= buffer_output;
end if;
end if;
end if;
if (hazard = '0')then
if (data_present = '1') then
data_out <= data;
else
data_out <= buffer_output;
end if;
else
data_out <= data_buffer;
end if;
end process;
end; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity HAZARD_RESOLVE_global is
PORT(
select_signal : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
hazard : IN STD_LOGIC;
data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
CLK : IN STD_LOGIC;
RESET_n : IN STD_LOGIC;
hazard_advanced : IN STD_LOGIC;
data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
);
end;
architecture resolve of HAZARD_RESOLVE_global is
signal data_present : std_logic;
signal buffer_output : std_logic_vector(31 downto 0);
signal data_buffer : std_logic_vector(31 downto 0);
signal hazard_rising_edge : std_logic;
begin
--edge capture
hazard_rising_edge <= hazard_advanced and (hazard_advanced xor hazard);
data_present <= select_signal(15) or select_signal(14) or select_signal(13) or select_signal(12) or
select_signal(11) or select_signal(10) or select_signal(9) or select_signal(8) or
select_signal(7) or select_signal(6) or select_signal(5) or select_signal(4) or
select_signal(3) or select_signal(2) or select_signal(1) or select_signal(0);
buffering : process (CLK, RESET_n, hazard, data_present, data) begin
if (RESET_n = '0') then
buffer_output <= "00000000000000000000000000000000";
elsif (rising_edge(CLK)) then
if (data_present = '1' and hazard = '1') then
buffer_output <= data;
end if;
end if;
end process;
hazard_detect : process (hazard, data, data_buffer, RESET_n, buffer_output, data_present, CLK) begin
if (RESET_n = '0') then
data_buffer <= "00000000000000000000000000000000";
elsif (rising_edge(CLK))then --was on rising edge hazard
if (hazard_rising_edge = '1') then --this if never existed
if (data_present = '1') then
data_buffer <= data;
else
data_buffer <= buffer_output;
end if;
end if;
end if;
if (hazard = '0')then
if (data_present = '1') then
data_out <= data;
else
data_out <= buffer_output;
end if;
else
data_out <= data_buffer;
end if;
end process;
end; |
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 8208)
`protect data_block
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`protect end_protected
|
library IEEE;
use IEEE.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library work;
use work.constants.all;
entity ram_tb is
end ram_tb;
architecture Behavior of ram_tb is
component ram
Port(
I_clk: in std_logic;
I_en: in std_logic;
I_write: in std_logic;
I_addr: in std_logic_vector(XLEN-1 downto 0);
I_data: in std_logic_vector(XLEN-1 downto 0);
O_data: out std_logic_vector(XLEN-1 downto 0);
O_busy: out std_logic
);
end component;
constant I_clk_period : time := 10 ns;
signal I_clk : std_logic := '0';
signal I_en: std_logic := '1';
signal I_write: std_logic := '0';
signal I_addr: std_logic_vector(XLEN-1 downto 0);
signal I_data: std_logic_vector(XLEN-1 downto 0);
signal O_data: std_logic_vector(XLEN-1 downto 0);
signal O_busy: std_logic := '0';
begin
-- instantiate unit under test
uut: ram port map(
I_clk => I_clk,
I_en => I_en,
I_write => I_write,
I_addr => I_addr,
I_data => I_data,
O_data => O_data,
O_busy => O_busy
);
proc_clock: process
begin
I_clk <= '0';
wait for I_clk_period/2;
I_clk <= '1';
wait for I_clk_period/2;
end process;
proc_stimuli: process
begin
-- ram works on falling edge, so stimulus should hapen on rising edge
wait until rising_edge(I_clk);
I_en <= '1';
I_addr <= X"00000000";
I_data <= X"01234567";
I_write <= '1';
wait until rising_edge(I_clk);
I_write <= '0';
wait until rising_edge(I_clk);
assert O_data = X"01234567" report "wrong output value" severity failure;
I_addr <= X"00000001";
I_data <= X"BEEFBEEF";
I_write <= '1';
wait until falling_edge(O_busy);
wait until rising_edge(I_clk);
I_addr <= X"00000000";
I_write <= '0';
wait until rising_edge(I_clk);
assert O_data = X"01BEEFBE";
I_addr <= X"00000001";
I_write <= '0';
wait until falling_edge(O_busy);
wait until rising_edge(I_clk);
assert O_data = X"BEEFBEEF";
I_addr <= X"00000002";
I_data <= X"AABBCCDD";
I_write <= '1';
wait until falling_edge(O_busy);
wait until rising_edge(I_clk);
I_addr <= X"00000000";
I_write <= '0';
wait until rising_edge(I_clk);
assert O_data = X"01BEAABB";
I_addr <= X"00000002";
I_write <= '0';
wait until falling_edge(O_busy);
wait until rising_edge(I_clk);
assert O_data = X"AABBCCDD";
I_addr <= X"00000003";
I_data <= X"1337EBAB";
I_write <= '1';
wait until falling_edge(O_busy);
wait until rising_edge(I_clk);
I_addr <= X"00000000";
I_write <= '0';
wait until rising_edge(I_clk);
assert O_data = X"01BEAA13";
I_addr <= X"00000003";
I_write <= '0';
wait until falling_edge(O_busy);
wait until rising_edge(I_clk);
assert O_data = X"1337EBAB";
wait for I_clk_period;
assert false report "end of simulation" severity failure;
end process;
end architecture; |
-- ----------------------------------------------------------------------------
-- Title : NUMERIC_STD arithmetic package for synthesis
-- : Rev. 1.7 (Nov. 23 1994)
-- :
-- Library : This package shall be compiled into a library symbolically
-- : named IEEE.
-- :
-- Developers : IEEE DASC Synthesis Working Group, PAR 1076.3
-- :
-- Purpose : This package defines numeric types and arithmetic functions
-- : for use with synthesis tools. Two numeric types are defined:
-- : --> UNSIGNED : represents UNSIGNED number in vector form
-- : --> SIGNED : represents a SIGNED number in vector form
-- : The base element type is type STD_LOGIC.
-- : The leftmost bit is treated as the most significant bit.
-- : Signed vectors are represented in two's complement form.
-- : This package contains overloaded arithmetic operators on
-- : the SIGNED and UNSIGNED types. The package also contains
-- : useful type conversions functions.
-- :
-- : If any argument to a function is a null array, a null array is
-- : returned (exceptions, if any, are noted individually).
-- :
-- Note : No declarations or definitions shall be included in, or
-- : excluded from, this package. The package declaration declares
-- : the functions that can be used by a user. The package body
-- : shall be considered the formal definition of the semantics of
-- : this package. Tool developers may choose to implement the
-- : package body in the most efficient manner available to them.
-- :
-- ----------------------------------------------------------------------------
library ieee;
use ieee.STD_LOGIC_1164.all;
Package numeric_std is
--===========================================================================
-- Numeric array type definitions
--===========================================================================
type UNSIGNED is array ( NATURAL range <> ) of STD_LOGIC;
type SIGNED is array ( NATURAL range <> ) of STD_LOGIC;
--===========================================================================
-- Arithmetic Operators:
--===========================================================================
-- Id: A.1
function "abs" ( X : SIGNED) return SIGNED;
-- Result subtype: SIGNED(X'LENGTH-1 downto 0).
-- Result: Returns the absolute value of a SIGNED vector X.
-- Id: A.2
function "-" ( ARG: SIGNED) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0).
-- Result: Returns the value of the unary minus operation on a
-- SIGNED vector ARG.
--============================================================================
-- Id: A.3
function "+" (L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two UNSIGNED vectors that may be of different lengths.
-- Id: A.4
function "+" ( L,R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Adds two SIGNED vectors that may be of different lengths.
-- Id: A.5
function "+" ( L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0).
-- Result: Adds an UNSIGNED vector, L, with a non-negative INTEGER, R.
-- Id: A.6
function "+" ( L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Adds a non-negative INTEGER, L, with an UNSIGNED vector, R.
-- Id: A.7
function "+" ( L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED (R'LENGTH-1 downto 0).
-- Result: Adds an INTEGER, L (may be positive or negative), to a SIGNED
-- vector, R.
-- Id: A.8
function "+" ( L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED (L'LENGTH-1 downto 0).
-- Result: Adds a SIGNED vector, L, to an INTEGER, R.
--============================================================================
-- Id: A.9
function "-" (L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts two UNSIGNED vectors that may be of different lengths.
-- Id: A.10
function "-" ( L,R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(MAX(L'LENGTH, R'LENGTH)-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from another SIGNED vector, L,
-- that may possibly be of different lengths.
-- Id: A.11
function "-" ( L: UNSIGNED;R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED (L'LENGTH-1 downto 0).
-- Result: Subtracts a non-negative INTEGER, R, from an UNSIGNED vector, L.
-- Id: A.12
function "-" ( L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts an UNSIGNED vector, R, from a non-negative INTEGER, L.
-- Id: A.13
function "-" ( L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED (L'LENGTH-1 downto 0).
-- Result: Subtracts an INTEGER, R, from a SIGNED vector, L.
-- Id: A.14
function "-" ( L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0).
-- Result: Subtracts a SIGNED vector, R, from an INTEGER, L.
--============================================================================
-- Id: A.15
function "*" (L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED((L'length+R'length-1) downto 0).
-- Result: Performs the multiplication operation on two UNSIGNED vectors
-- that may possibly be of different lengths.
-- Id: A.16
function "*" ( L,R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((L'length+R'length-1) downto 0)
-- Result: Multiplies two SIGNED vectors that may possibly be of
-- different lengths.
-- Id: A.17
function "*" ( L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED((L'length+L'length-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, L, with a non-negative
-- INTEGER, R. R is converted to an UNSIGNED vector of
-- SIZE L'length before multiplication.
-- Id: A.18
function "*" ( L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED((R'length+R'length-1) downto 0).
-- Result: Multiplies an UNSIGNED vector, R, with a non-negative
-- INTEGER, L. L is converted to an UNSIGNED vector of
-- SIZE R'length before multiplication.
-- Id: A.19
function "*" ( L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED((L'length+L'length-1) downto 0)
-- Result: Multiplies a SIGNED vector, L, with an INTEGER, R. R is
-- converted to a SIGNED vector of SIZE L'length before
-- multiplication.
-- Id: A.20
function "*" ( L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED((R'length+R'length-1) downto 0)
-- Result: Multiplies a SIGNED vector, R, with an INTEGER, L. L is
-- converted to a SIGNED vector of SIZE R'length before
-- multiplication.
--============================================================================
--
-- NOTE: If second argument is zero for "/" operator, a severity level
-- of ERROR is issued.
-- Id: A.21
function "/" (L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED (L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by another UNSIGNED vector, R.
-- Id: A.22
function "/" ( L,R: SIGNED) return SIGNED;
-- Result subtype: SIGNED (L'LENGTH-1 downto 0)
-- Result: Divides an SIGNED vector, L, by another SIGNED vector, R.
-- Id: A.23
function "/" ( L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED (L'LENGTH-1 downto 0)
-- Result: Divides an UNSIGNED vector, L, by a non-negative INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH.
-- Id: A.24
function "/" ( L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED (R'LENGTH-1 downto 0)
-- Result: Divides a non-negative INTEGER, L, by an UNSIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH.
-- Id: A.25
function "/" ( L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED (L'LENGTH-1 downto 0)
-- Result: Divides a SIGNED vector, L, by an INTEGER, R.
-- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH.
-- Id: A.26
function "/" ( L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED (R'LENGTH-1 downto 0)
-- Result: Divides an INTEGER, L, by a SIGNED vector, R.
-- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "rem" operator, a severity level
-- of ERROR is issued.
-- Id: A.27
function "rem" (L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are UNSIGNED vectors.
-- Id: A.28
function "rem" ( L,R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L and R are SIGNED vectors.
-- Id: A.29
function "rem" ( L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is an UNSIGNED vector and R is a
-- non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH.
-- Id: A.30
function "rem" ( L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is an UNSIGNED vector and L is a
-- non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH.
-- Id: A.31
function "rem" ( L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where L is SIGNED vector and R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH.
-- Id: A.32
function "rem" ( L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L rem R" where R is SIGNED vector and L is an INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH.
--============================================================================
--
-- NOTE: If second argument is zero for "mod" operator, a severity level
-- of ERROR is issued.
-- Id: A.33
function "mod" (L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are UNSIGNED vectors.
-- Id: A.34
function "mod" ( L,R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L and R are SIGNED vectors.
-- Id: A.35
function "mod" ( L: UNSIGNED; R: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an UNSIGNED vector and R
-- is a non-negative INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH.
-- Id: A.36
function "mod" ( L: NATURAL; R: UNSIGNED) return UNSIGNED;
-- Result subtype: UNSIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where R is an UNSIGNED vector and L
-- is a non-negative INTEGER.
-- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH.
-- Id: A.37
function "mod" ( L: SIGNED; R: INTEGER) return SIGNED;
-- Result subtype: SIGNED(L'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is a SIGNED vector and
-- R is an INTEGER.
-- If NO_OF_BITS(R) > L'LENGTH, then R is truncated to L'LENGTH.
-- Id: A.38
function "mod" ( L: INTEGER; R: SIGNED) return SIGNED;
-- Result subtype: SIGNED(R'LENGTH-1 downto 0)
-- Result: Computes "L mod R" where L is an INTEGER and
-- R is a SIGNED vector.
-- If NO_OF_BITS(L) > R'LENGTH, then L is truncated to R'LENGTH.
--============================================================================
-- Comparison Operators
--============================================================================
-- Id: C.1
function ">" (L,R: UNSIGNED ) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.2
function ">" ( L,R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.3
function ">" ( L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.4
function ">" ( L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a INTEGER and
-- R is a SIGNED vector.
-- Id: C.5
function ">" ( L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.6
function ">" ( L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L > R" where L is a SIGNED vector and
-- R is a INTEGER.
--============================================================================
-- Id: C.7
function "<" (L,R: UNSIGNED ) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.8
function "<" ( L,R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.9
function "<" ( L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.10
function "<" ( L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.11
function "<" ( L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.12
function "<" ( L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L < R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.13
function "<=" (L,R: UNSIGNED ) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.14
function "<=" ( L,R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.15
function "<=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.16
function "<=" ( L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.17
function "<=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.18
function "<=" ( L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L <= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.19
function ">=" (L,R: UNSIGNED ) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.20
function ">=" ( L,R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.21
function ">=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.22
function ">=" ( L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.23
function ">=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.24
function ">=" ( L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L >= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.25
function "=" (L,R: UNSIGNED ) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.26
function "=" ( L,R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.27
function "=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.28
function "=" ( L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.29
function "=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.30
function "=" ( L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L = R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Id: C.31
function "/=" (L,R: UNSIGNED ) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are UNSIGNED vectors possibly
-- of different lengths.
-- Id: C.32
function "/=" ( L,R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L and R are SIGNED vectors possibly
-- of different lengths.
-- Id: C.33
function "/=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a non-negative INTEGER and
-- R is an UNSIGNED vector.
-- Id: C.34
function "/=" ( L: INTEGER; R: SIGNED) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an INTEGER and
-- R is a SIGNED vector.
-- Id: C.35
function "/=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is an UNSIGNED vector and
-- R is a non-negative INTEGER.
-- Id: C.36
function "/=" ( L: SIGNED; R: INTEGER) return BOOLEAN;
-- Result subtype: BOOLEAN
-- Result: Computes "L /= R" where L is a SIGNED vector and
-- R is an INTEGER.
--============================================================================
-- Shift and Rotate Functions
--============================================================================
-- Id: S.1
function shift_left ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits are lost.
-- Id: S.2
function shift_right ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on an UNSIGNED vector COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT rightmost bits are lost.
-- Id: S.3
function shift_left ( ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED (ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-left on a SIGNED vector COUNT times.
-- All bits of ARG, except ARG'LEFT, are shifted left COUNT times.
-- The vacated positions are filled with Bit '0'.
-- The COUNT leftmost bits, except ARG'LEFT, are lost.
-- Id: S.4
function shift_right ( ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED (ARG'LENGTH-1 downto 0)
-- Result: Performs a shift-right on a SIGNED vector COUNT times.
-- The vacated positions are filled with the leftmost bit,ARG'LEFT.
-- The COUNT rightmost bits are lost.
--============================================================================
--============================================================================
-- Id: S.5
function rotate_left ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate_left of an UNSIGNED vector COUNT times.
-- Id: S.6
function rotate_right ( ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED (ARG'LENGTH-1 downto 0)
-- Result: Performs a rotate_right of an UNSIGNED vector COUNT times.
-- Id: S.7
function rotate_left ( ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED (ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-left of a SIGNED
-- vector COUNT times.
-- Id: S.8
function rotate_right ( ARG: SIGNED; COUNT: NATURAL) return SIGNED;
-- Result subtype: SIGNED (ARG'LENGTH-1 downto 0)
-- Result: Performs a logical rotate-right of a SIGNED
-- vector COUNT times.
--============================================================================
-- RESIZE Functions
--============================================================================
-- Id: R.1
function RESIZE ( ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED(ARG'LENGTH-1 downto 0)
-- Result: ReSIZEs the SIGNED vector ARG to the specified SIZE.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with the sign bit (ARG'LEFT). When truncating,
-- the sign bit is retained along with the rightmost part.
-- Id: R.2
function RESIZE ( ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED(ARG'LENGTH-1 downto 0)
-- Result: ReSIZEs the SIGNED vector ARG to the specified SIZE.
-- To create a larger vector, the new [leftmost] bit positions
-- are filled with '0'. When truncating, the leftmost bits
-- are dropped.
--============================================================================
-- Conversion Functions
--============================================================================
-- Id: D.1
function TO_INTEGER ( ARG: UNSIGNED) return NATURAL;
-- Result subtype: NATURAL. Value cannot be negative since parameter is an
-- UNSIGNED vector.
-- Result: Converts the UNSIGNED vector to an INTEGER.
-- Id: D.2
function TO_INTEGER ( ARG: SIGNED) return INTEGER;
-- Result subtype: INTEGER
-- Result: Converts a SIGNED vector to an INTEGER.
-- Id: D.3
function TO_UNSIGNED ( ARG,SIZE: NATURAL) return UNSIGNED;
-- Result subtype: UNSIGNED (SIZE-1 downto 0)
-- Result: Converts a non-negative INTEGER to an UNSIGNED vector with
-- the specified SIZE.
-- Id: D.4
function TO_SIGNED ( ARG: INTEGER; SIZE: NATURAL) return SIGNED;
-- Result subtype: SIGNED (SIZE-1 downto 0)
-- Result: Converts an INTEGER to a SIGNED vector of the specified SIZE.
-- Id: D.5
function TO_UNSIGNED ( ARG: STD_LOGIC_VECTOR) return UNSIGNED;
-- Result subtype: UNSIGNED, same range as input ARG
-- Result: Converts STD_LOGIC_VECTOR to UNSIGNED.
-- Id: D.6
function TO_SIGNED ( ARG: STD_LOGIC_VECTOR) return SIGNED;
-- Result subtype: SIGNED, same range as input ARG
-- Result: Converts STD_LOGIC_VECTOR to SIGNED.
-- Id: D.7
function TO_STDLOGICVECTOR ( ARG: UNSIGNED) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR, same range as input ARG
-- Result: Converts UNSIGNED to STD_LOGIC_VECTOR.
-- Id: D.8
function TO_STDLOGICVECTOR ( ARG: SIGNED) return STD_LOGIC_VECTOR;
-- Result subtype: STD_LOGIC_VECTOR, same range as input ARG
-- Result: Converts SIGNED to STD_LOGIC_VECTOR.
--============================================================================
-- Logical Operators
--============================================================================
-- Id: L.1
function "not" ( L: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED, same range as input L
-- Result: Termwise inversion
-- Id: L.2
function "and" ( L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED, same range as input L
-- Result: Vector AND operation
-- Id: L.3
function "or" ( L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED, same range as input L
-- Result: Vector OR operation
-- Id: L.4
function "nand" ( L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED, same range as input L
-- Result: Vector NAND operation
-- Id: L.5
function "nor" ( L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED, same range as input L
-- Result: Vector NOR operation
-- Id: L.6
function "xor" ( L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED, same range as input L
-- Result: Vector XOR operation
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this 1076.3 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
-- Id: L.7
-- function "xnor" ( L,R: UNSIGNED ) return UNSIGNED;
-- Result subtype: UNSIGNED, same range as input L
-- Result: Vector XNOR operation
-- Id: L.8
function "not" ( L: SIGNED) return SIGNED;
-- Result subtype: SIGNED, same range as input L
-- Result: Termwise inversion
-- Id: L.9
function "and" ( L,R: SIGNED ) return SIGNED;
-- Result subtype: SIGNED, same range as input L
-- Result: Vector AND operation
-- Id: L.10
function "or" ( L,R: SIGNED ) return SIGNED;
-- Result subtype: SIGNED, same range as input L
-- Result: Vector OR operation
-- Id: L.11
function "nand" ( L,R: SIGNED ) return SIGNED;
-- Result subtype: SIGNED, same range as input L
-- Result: Vector NAND operation
-- Id: L.12
function "nor" ( L,R: SIGNED ) return SIGNED;
-- Result subtype: SIGNED, same range as input L
-- Result: Vector NOR operation
-- Id: L.13
function "xor" ( L,R: SIGNED ) return SIGNED;
-- Result subtype: SIGNED, same range as input L
-- Result: Vector XOR operation
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this 1076.3 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
-- Id: L.14
-- function "xnor" ( L,R: SIGNED ) return SIGNED;
-- Result subtype: SIGNED, same range as input L
-- Result: Vector XNOR operation
--============================================================================
-- Match Functions
--============================================================================
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN;
-- Result: terms compared per STD_LOGIC_1164 intent
-- Id: M.2
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN;
-- Result: termwise comparison per STD_LOGIC_1164 intent
end numeric_std;
--=============================================================================
--======================= Package Body ===============================
--=============================================================================
Package body numeric_std is
-- null range array constants
constant NAU : UNSIGNED (0 downto 1) := (others => '0');
constant NAS : SIGNED (0 downto 1) := (others => '0');
-- implementation controls
constant NO_WARNING : boolean := FALSE; -- default to emit warnings
--=========================Local Subprograms=================================
function MAX(LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT > RIGHT then return LEFT;
else return RIGHT;
end if;
end;
function MIN(LEFT, RIGHT: INTEGER) return INTEGER is
begin
if LEFT < RIGHT then return LEFT;
else return RIGHT;
end if;
end;
function Signed_NUM_BITS ( ARG: INTEGER) return natural is
variable nBits: natural;
variable N: natural;
begin
if ARG>=0 then
N:=ARG;
else
N:=-(ARG+1);
end if;
nBits:=1;
while N>0 loop
nBits:=nBits+1;
N:= N / 2;
end loop;
return nBits;
end;
function UNSIGNED_NUM_BITS (ARG: natural) return natural is
variable nBits: natural;
variable N: natural;
begin
N:=ARG;
nBits:=1;
while N>1 loop
nBits:=nBits+1;
N:= N / 2;
end loop;
return nBits;
end;
------------------------------------------------------------------------
-- this internal function computes the addition of two UNSIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_UNSIGNED ( L,R: UNSIGNED; C: STD_LOGIC ) return UNSIGNED is
constant L_left:INTEGER:= L'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
alias XR: UNSIGNED(L_left downto 0) is R;
variable RESULT: UNSIGNED(L_left downto 0);
variable CBIT : STD_LOGIC:= C;
begin
for i in 0 to L_left loop
RESULT(i) := CBIT xor XL(i) xor XR(i);
CBIT := (CBIT and XL(i)) or (CBIT and XR(i)) or (XL(i) and XR(i));
end loop;
return RESULT;
end ADD_UNSIGNED;
-- this internal function computes the addition of two SIGNED
-- with input CARRY
-- * the two arguments are of the same length
function ADD_SIGNED ( L,R: SIGNED; C: STD_LOGIC ) return SIGNED is
constant L_left:INTEGER:= L'length-1;
alias XL: SIGNED(L_left downto 0) is L;
alias XR: SIGNED(L_left downto 0) is R;
variable RESULT: SIGNED(L_left downto 0);
variable CBIT: STD_LOGIC:= C;
begin
for i in 0 to L_left loop
RESULT(i) := CBIT xor XL(i) xor XR(i);
CBIT := (CBIT and XL(i)) or (CBIT and XR(i)) or (XL(i) and XR(i));
end loop;
return RESULT;
end ADD_SIGNED;
------------------------------------------------------------------------
-- this internal procedure computes UNSIGNED division
-- giving the quotient and remainder.
procedure divMod (num, XDENOM: UNSIGNED;
xquot, xremain: out UNSIGNED) is
variable TEMP: UNSIGNED(num'length-1 downto 0);
variable quot: UNSIGNED(MAX(num'length,XDENOM'length)-1 downto 0);
variable diff: UNSIGNED(XDENOM'length downto 0);
alias DENOM : UNSIGNED (XDENOM'length-1 downto 0) is XDENOM;
variable CARRY: STD_LOGIC;
variable TOPBIT: natural;
variable isZero: boolean;
begin
isZero:=TRUE;
for j in XDENOM'range loop
CARRY:=DENOM(j);
if CARRY/='0' then
isZero:=FALSE;
end if;
end loop;
assert not isZero
report "DIV,MOD,or REM by zero"
severity error;
TEMP:=num;
quot:= (others =>'0');
TOPBIT:=0;
for j in DENOM'range loop
if DENOM(j)='1' then
TOPBIT:=j;
exit;
end if;
end loop;
CARRY:='0';
for j in num'length-(TOPBIT+1) downto 0 loop
-- lexical ordering works okay for this comparison, no overloaded
-- function is needed.
if CARRY&TEMP(TOPBIT+j downto j) >= "0"&DENOM(TOPBIT downto 0) then
diff(TOPBIT+1 downto 0) := (CARRY&TEMP(TOPBIT+j downto j))
-("0"&DENOM(TOPBIT downto 0));
assert diff(TOPBIT+1)='0'
report "internal error in the division algorithm"
severity error;
CARRY:=diff(TOPBIT);
if TOPBIT+j+1<=TEMP'left then
TEMP(TOPBIT+j+1):='0';
end if;
TEMP(TOPBIT+j downto j):=diff(TOPBIT downto 0);
quot(j):='1';
else
assert CARRY='0'
report "internal error in the division algorithm"
severity error;
CARRY:=TEMP(TOPBIT+j);
end if;
end loop;
xquot:=quot(num'length-1 downto 0);
xremain:=TEMP(num'length-1 downto 0);
end divMod;
-----------------Local Subprograms - shift/rotate ops-------------------------
function XSLL(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is
constant ARG_L:INTEGER:= ARG'length-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others=>'0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L downto COUNT):=XARG(ARG_L-COUNT downto 0);
end if;
return RESULT;
end;
function XSRL(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is
constant ARG_L:INTEGER:= ARG'length-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := (others=>'0');
begin
if COUNT <= ARG_L then
RESULT(ARG_L-COUNT downto 0):=XARG(ARG_L downto COUNT);
end if;
return RESULT;
end;
function XSRA(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is
constant ARG_L:INTEGER:= ARG'length-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0);
variable XCOUNT: natural := COUNT;
begin
if ((ARG'length <= 1) or (xCOUNT = 0)) then return ARG;
else
if (XCOUNT > ARG_L) then xCOUNT:= ARG_L; end if;
RESULT(ARG_L-XCOUNT downto 0):=XARG(ARG_L downto XCOUNT);
RESULT(ARG_L downto (ARG_L - XCOUNT + 1)) := (others=>XARG(ARG_L));
end if;
return RESULT;
end;
function XROL(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is
constant ARG_L:INTEGER:= ARG'length-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM:= COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L downto COUNTM):=XARG(ARG_L-COUNTM downto 0);
RESULT(COUNTM-1 downto 0):=XARG(ARG_L downto ARG_L-COUNTM+1);
end if;
return RESULT;
end;
function XROR(ARG: STD_LOGIC_VECTOR; COUNT: NATURAL) return STD_LOGIC_VECTOR is
constant ARG_L:INTEGER:= ARG'length-1;
alias XARG: STD_LOGIC_VECTOR(ARG_L downto 0) is ARG;
variable RESULT: STD_LOGIC_VECTOR(ARG_L downto 0) := XARG;
variable COUNTM: INTEGER;
begin
COUNTM:= COUNT mod (ARG_L + 1);
if COUNTM /= 0 then
RESULT(ARG_L-COUNTM downto 0):=XARG(ARG_L downto COUNTM);
RESULT(ARG_L downto ARG_L-COUNTM+1):=XARG(COUNTM-1 downto 0);
end if;
return RESULT;
end;
-----------------Local Subprograms - Relational ops--------------------------
--
-- General "=" for UNSIGNED vectors, same length
--
function UNSIGNED_equal ( L,R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR (L) = STD_LOGIC_VECTOR (R) ;
end;
--
-- General "=" for SIGNED vectors, same length
--
function SIGNED_equal ( L,R: SIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR (L) = STD_LOGIC_VECTOR (R) ;
end;
--
-- General "<" for UNSIGNED vectors, same length
--
function UNSIGNED_LESS ( L,R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR (L) < STD_LOGIC_VECTOR (R) ;
end UNSIGNED_LESS ;
--
-- General "<" function for SIGNED vectors, same length
--
function SIGNED_LESS ( L,R: SIGNED) return BOOLEAN is
variable intern_l : SIGNED (0 to L'LENGTH-1);
variable intern_r : SIGNED (0 to R'LENGTH-1);
begin
intern_l:=l;
intern_r:=r;
intern_l(0):=not intern_l(0);
intern_r(0):=not intern_r(0);
return STD_LOGIC_VECTOR (intern_L) < STD_LOGIC_VECTOR (intern_R) ;
end;
--
-- General "<=" function for UNSIGNED vectors, same length
--
function UNSIGNED_LESS_OR_EQUAL ( L,R: UNSIGNED) return BOOLEAN is
begin
return STD_LOGIC_VECTOR (L) <= STD_LOGIC_VECTOR (R) ;
end;
--
-- General "<=" function for SIGNED vectors, same length
--
function SIGNED_LESS_OR_EQUAL ( L,R: SIGNED) return BOOLEAN is
-- Need aliasses to assure index direction
variable intern_l : SIGNED (0 to L'LENGTH-1);
variable intern_r : SIGNED (0 to R'LENGTH-1);
begin
intern_l:=l;
intern_r:=r;
intern_l(0):=not intern_l(0);
intern_r(0):=not intern_r(0);
return STD_LOGIC_VECTOR (intern_L) <= STD_LOGIC_VECTOR (intern_R) ;
end;
-- function TO_01 is used to convert vectors to the
-- correct form for exported functions,
-- and to report if there is an element which
-- is not in (0,1,h,l).
-- Assume the vector is normalized and non-null.
-- The function is duplicated for SIGNED and UNSIGNED types.
function TO_01(S : SIGNED ; xmap : STD_LOGIC:= '0') return SIGNED is
variable RESULT: SIGNED(S'length-1 downto 0);
variable bad_element : boolean := FALSE;
alias xs : SIGNED(s'length-1 downto 0) is S;
begin
for i in RESULT'range loop
case xs(i) is
when '0' | 'L' => RESULT(i):='0';
when '1' | 'H' => RESULT(i):='1';
when others => bad_element := TRUE;
end case;
end loop;
if bad_element then
assert NO_WARNING
report "numeric_std.TO_01: Array Element not in {0,1,H,L}"
severity warning;
for i in RESULT'range loop
RESULT(i) := xmap; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
function TO_01(S : UNSIGNED ; xmap : STD_LOGIC:= '0') return UNSIGNED is
variable RESULT: UNSIGNED(S'length-1 downto 0);
variable bad_element : boolean := FALSE;
alias xs : UNSIGNED(S'length-1 downto 0) is S;
begin
for i in RESULT'range loop
case xs(i) is
when '0' | 'L' => RESULT(i):='0';
when '1' | 'H' => RESULT(i):='1';
when others => bad_element := TRUE;
end case;
end loop;
if bad_element then
assert NO_WARNING
report "numeric_std.TO_01: Array Element not in {0,1,H,L}"
severity warning;
for i in RESULT'range loop
RESULT(i) := xmap; -- standard fixup
end loop;
end if;
return RESULT;
end TO_01;
--=========================Exported Functions=================================
-- Id: A.1
function "abs" ( X : SIGNED) return SIGNED is
constant ARG_LEFT:INTEGER:= X'length-1;
alias XX : SIGNED(ARG_LEFT downto 0) is X;
variable RESULT: SIGNED (ARG_LEFT downto 0);
begin
if X'length<1 then return NAS; end if;
RESULT:=TO_01(xx,std_logic' ('X'));
if (RESULT(RESULT'left)='X') then return RESULT; end if;
if RESULT(RESULT'left) = '1' then
RESULT:= -RESULT;
end if;
return RESULT;
end; -- "abs"
-- Id: A.2
function "-" ( ARG: SIGNED) return SIGNED is
constant ARG_LEFT:INTEGER:= ARG'length-1;
alias XARG: SIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT,XARG01 : SIGNED(ARG_LEFT downto 0);
variable CBIT : STD_LOGIC:= '1';
begin
if ARG'length<1 then return NAS; end if;
XARG01 := TO_01(ARG,std_logic' ('X'));
if (XARG01(XARG01'left)='X') then return XARG01; end if;
for i in 0 to RESULT'left loop
RESULT(i) := not(XARG01(i)) xor CBIT;
CBIT := CBIT and not(XARG01(i));
end loop;
return RESULT;
end; -- "-"
--=============================================================================
-- Id: A.3
function "+" ( L,R: UNSIGNED ) return UNSIGNED is
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length<1) or (R'length<1)) then return NAU; end if;
L01 := TO_01(RESIZE(L,SIZE), 'X');
if (L01(L01'left)='X') then return L01; end if;
R01 := TO_01(RESIZE(R,SIZE),std_logic' ('X'));
if (R01(R01'left)='X') then return R01; end if;
return ADD_UNSIGNED (L01, R01, std_logic' ('0')) ;
end;
-- Id: A.4
function "+" ( L,R: SIGNED ) return SIGNED is
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length<1) or (R'length<1)) then return NAS; end if;
L01 := TO_01(RESIZE(L,SIZE),std_logic' ('X'));
if (L01(L01'left)='X') then return L01; end if;
R01 := TO_01(RESIZE(R,SIZE),std_logic' ('X'));
if (R01(R01'left)='X') then return R01; end if;
return ADD_SIGNED (L01, R01, std_logic' ('0')) ;
end;
-- Id: A.5
function "+" ( L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L + TO_UNSIGNED( R , L'length);
end;
-- Id: A.6
function "+" ( L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED( L , R'length) + R;
end;
-- Id: A.7
function "+" ( L: SIGNED; R: INTEGER) return SIGNED is
begin
return L + TO_SIGNED( R , L'length);
end;
-- Id: A.8
function "+" ( L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED( L , R'length) + R;
end;
--=============================================================================
-- Id: A.9
function "-" ( L,R: UNSIGNED) return UNSIGNED is
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : UNSIGNED(SIZE-1 downto 0);
variable R01 : UNSIGNED(SIZE-1 downto 0);
begin
if ((L'length<1) or (R'length<1)) then return NAU; end if;
L01 := TO_01(RESIZE(L,SIZE),std_logic' ('X'));
if (L01(L01'left)='X') then return L01; end if;
R01 := TO_01(RESIZE(R,SIZE),std_logic' ('X'));
if (R01(R01'left)='X') then return R01; end if;
return ADD_UNSIGNED (L01,not(R01),std_logic' ('1'));
end;
-- Id: A.10
function "-" ( L,R: SIGNED) return SIGNED is
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : SIGNED(SIZE-1 downto 0);
variable R01 : SIGNED(SIZE-1 downto 0);
begin
if ((L'length<1) or (R'length<1)) then return NAS; end if;
L01 := TO_01(RESIZE(L,SIZE),std_logic' ('X'));
if (L01(L01'left)='X') then return L01; end if;
R01 := TO_01(RESIZE(R,SIZE),std_logic' ('X'));
if (R01(R01'left)='X') then return R01; end if;
return ADD_SIGNED (L01,not(R01),std_logic' ('1'));
end;
-- Id: A.11
function "-" ( L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L - TO_UNSIGNED( R , L'length);
end;
-- Id: A.12
function "-" ( L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED( L , R'length) - R;
end;
-- Id: A.13
function "-" ( L: SIGNED; R: INTEGER) return SIGNED is
begin
return L - TO_SIGNED( R , L'length);
end;
-- Id: A.14
function "-" ( L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED( L , R'length) - R ;
end;
--=============================================================================
-- Id: A.15
function "*" ( L,R: UNSIGNED) return UNSIGNED is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias xxl : UNSIGNED(L_left downto 0) is L;
alias xxr : UNSIGNED(R_left downto 0) is R;
variable xl : UNSIGNED(L_left downto 0);
variable xr : UNSIGNED(R_left downto 0);
variable RESULT: UNSIGNED((L'length+R'length-1) downto 0) :=(others=>'0');
variable adval : UNSIGNED((L'length+R'length-1) downto 0);
begin
if ((L'length<1) or (R'length<1)) then return NAU; end if;
xl := TO_01(xxl,std_logic' ('X'));
xr := TO_01(xxr,std_logic' ('X'));
if ((xl(xl'left)='X') or (xr(xr'left)='X')) then
RESULT:= (others=>'X');
return RESULT;
end if;
adval := RESIZE(xr,RESULT'length);
for i in 0 to L_left loop
if xl(i)='1' then RESULT:= RESULT + adval;
end if;
adval := shift_left(adval,1);
end loop;
return RESULT;
end;
-- Id: A.16
function "*" ( L,R: SIGNED) return SIGNED is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias xxl : SIGNED(L_left downto 0) is L;
alias xxr : SIGNED(R_left downto 0) is R;
variable xl : SIGNED(L_left downto 0);
variable xr : SIGNED(R_left downto 0);
variable RESULT: SIGNED((L'length+R'length-1) downto 0) :=(others=>'0');
variable adval : SIGNED((L'length+R'length-1) downto 0);
variable invt : STD_LOGIC:= '0';
begin
if ((L'length<1) or (R'length<1)) then return NAS; end if;
xl := TO_01(xxl,std_logic' ('X'));
xr := TO_01(xxr,std_logic' ('X'));
if ((xl(xl'left)='X') or (xr(xr'left)='X')) then
RESULT:= (others=>'X');
return RESULT;
end if;
adval := RESIZE(xr,RESULT'length);
if xl(xl'left)='1' then
adval := -(adval);
invt := '1';
end if;
for i in 0 to L_left loop
if (invt xor xl(i))='1' then RESULT:= RESULT + adval;
end if;
adval := shift_left(adval,1);
end loop;
return RESULT;
end;
-- Id: A.17
function "*" ( L: UNSIGNED; R: NATURAL) return UNSIGNED is
begin
return L * TO_UNSIGNED( R , L'length);
end;
-- Id: A.18
function "*" ( L: NATURAL; R: UNSIGNED) return UNSIGNED is
begin
return TO_UNSIGNED( L , R'length) * R;
end;
-- Id: A.19
function "*" ( L: SIGNED; R: INTEGER) return SIGNED is
begin
return L * TO_SIGNED( R , L'length);
end;
-- Id: A.20
function "*" ( L: INTEGER; R: SIGNED) return SIGNED is
begin
return TO_SIGNED( L , R'length) * R ;
end;
--=============================================================================
-- Id: A.21
function "/" ( L,R: UNSIGNED) return UNSIGNED is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias xxl : UNSIGNED(L_left downto 0) is L;
alias xxr : UNSIGNED(R_left downto 0) is R;
variable xl : UNSIGNED(L_left downto 0);
variable xr : UNSIGNED(R_left downto 0);
variable fquot,fremain : UNSIGNED(L'length-1 downto 0);
begin
if ((L'length<1) or (R'length<1)) then return NAU; end if;
xl := TO_01(xxl,std_logic' ('X'));
xr := TO_01(xxr,std_logic' ('X'));
if ((xl(xl'left)='X') or (xr(xr'left)='X')) then
fquot := (others=>'X');
return fquot;
end if;
divMod(xl,xr,fquot,fremain);
return fquot;
end;
-- Id: A.22
function "/" ( L,R: SIGNED) return SIGNED is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias xxl : SIGNED(L_left downto 0) is L;
alias xxr : SIGNED(R_left downto 0) is R;
variable xl : SIGNED(L_left downto 0);
variable xr : SIGNED(R_left downto 0);
variable fquot,fremain : UNSIGNED(L'length-1 downto 0);
variable xnum: UNSIGNED(L'length-1 downto 0);
variable XDENOM: UNSIGNED(R'length-1 downto 0);
variable qneg: boolean := FALSE;
begin
if ((L'length<1) or (R'length<1)) then return NAS; end if;
xl := TO_01(xxl,std_logic' ('X'));
xr := TO_01(xxr,std_logic' ('X'));
if ((xl(xl'left)='X') or (xr(xr'left)='X')) then
fquot := (others=>'X');
return SIGNED(fquot);
end if;
if xl(xl'left)='1' then
xnum:=UNSIGNED(-xl);
qNeg:=TRUE;
else
xnum:=UNSIGNED(xl);
end if;
if xr(xr'left)='1' then
xdenom:=UNSIGNED(-xr);
qNeg:=not qNeg;
else
xdenom:=UNSIGNED(xr);
end if;
divMod(xnum,XDENOM,fquot,fremain);
if qNeg then fquot:="0"-fquot; end if;
return SIGNED(fquot);
end;
-- Id: A.23
function "/" ( L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_Length : Natural := max(L'Length, unsigned_num_bits(R));
variable XR,Quot : unsigned (R_Length-1 downto 0);
begin
XR := TO_UNSIGNED(R, R_Length);
Quot := L / XR;
if R_Length>L'Length and Quot(0)/='X'
and Quot(R_Length-1 downto L'Length)/=(R_Length-1 downto L'Length => '0')
then
ASSERT no_warning report "Numeric_std.""/"": Quotient Truncated"
severity warning;
end if;
return Quot(L'Length-1 downto 0);
end;
-- Id: A.24
function "/" ( L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_Length : Natural := max(unsigned_num_bits(L), R'length);
variable XL,Quot : UNSIGNED (L_Length-1 downto 0);
begin
XL := TO_UNSIGNED(L,L_LENGTH);
QUOT := XL / R;
if L_LENGTH>R'LENGTH and Quot(0)/='X'
and QUOT(L_LENGTH-1 downto R'Length)/=(L_LENGTH-1 downto R'Length => '0')
then
ASSERT no_warning report "Numeric_std.""/"": Quotient Truncated"
severity warning;
end if;
return Quot(R'Length-1 downto 0);
end;
-- Id: A.25
function "/" ( L : SIGNED; R : INTEGER ) return SIGNED is
constant R_Length : Natural := max(L'Length, signed_num_bits(R));
variable XR,Quot : signed (R_Length-1 downto 0);
begin
XR := TO_SIGNED(R, R_Length);
Quot := L / XR;
if R_Length>L'Length and Quot(0)/='X'
and Quot(R_Length-1 downto L'Length)
/= (R_Length-1 downto L'Length => Quot(L'Length-1))
then
ASSERT no_warning report "Numeric_std.""/"": Quotient Truncated"
severity warning;
end if;
return Quot(L'Length-1 downto 0);
end;
-- Id: A.26
function "/" ( L : INTEGER; R : SIGNED) return SIGNED is
constant L_Length : Natural := max(signed_num_bits(L), R'length);
variable XL,Quot : SIGNED (L_Length-1 downto 0);
begin
XL := TO_SIGNED(L,L_LENGTH);
QUOT := XL / R;
if L_LENGTH>R'LENGTH and Quot(0)/='X'
and QUOT(L_LENGTH-1 downto R'Length)
/= (L_LENGTH-1 downto R'Length => Quot(R'Length-1))
then
ASSERT no_warning report "Numeric_std.""/"": Quotient Truncated"
severity warning;
end if;
return Quot(R'Length-1 downto 0);
end;
--=============================================================================
-- Id: A.27
function "rem" ( L,R: UNSIGNED) return UNSIGNED is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias xxl : UNSIGNED(L_left downto 0) is L;
alias xxr : UNSIGNED(R_left downto 0) is R;
variable xl : UNSIGNED(L_left downto 0);
variable xr : UNSIGNED(R_left downto 0);
variable fquot,fremain : UNSIGNED(l'length-1 downto 0);
begin
if ((L'length<1) or (R'length<1)) then return NAU; end if;
xl := TO_01(xxl,std_logic' ('X'));
xr := TO_01(xxr,std_logic' ('X'));
if ((xl(xl'left)='X') or (xr(xr'left)='X')) then
fremain := (others=>'X');
return fremain;
end if;
divMod(xl,xr,fquot,fremain);
return fremain;
end;
-- Id: A.28
function "rem" ( L,R: SIGNED) return SIGNED is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias xxl : SIGNED(L_left downto 0) is L;
alias xxr : SIGNED(R_left downto 0) is R;
variable fquot,fremain : UNSIGNED(l'length-1 downto 0);
variable xnum: UNSIGNED(l'length-1 downto 0);
variable XDENOM: UNSIGNED(r'length-1 downto 0);
variable rneg: boolean := FALSE;
begin
if ((L'length<1) or (R'length<1)) then return NAS; end if;
xnum := UNSIGNED(TO_01(xxl,std_logic' ('X')));
XDENOM := UNSIGNED(TO_01(xxr,std_logic' ('X')));
if ((xnum(xnum'left)='X') or (xdenom(xnum'left)='X')) then
fremain := (others=>'X');
return SIGNED(fremain);
end if;
if xnum(xnum'left)='1' then
xnum:=UNSIGNED(-SIGNED(xnum));
rNeg:=TRUE;
else
xNum:=UNSIGNED(xnum);
end if;
if XDENOM(XDENOM'left)='1' then
XDENOM:=UNSIGNED(-SIGNED(XDENOM));
else
XDENOM:=UNSIGNED(XDENOM);
end if;
divMod(xnum,XDENOM,fquot,fremain);
if rNeg then
fremain:="0"-fremain;
end if;
return SIGNED(fremain);
end;
-- Id: A.29
function "rem" ( L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_Length : Natural := max(L'Length, unsigned_num_bits(R));
variable XR,XRem : unsigned (R_Length-1 downto 0);
begin
XR := TO_UNSIGNED(R, R_Length);
XRem := L rem XR;
if R_Length>L'Length and XRem(0)/='X'
and XRem(R_Length-1 downto L'Length)
/= (R_Length-1 downto L'Length => '0')
then
ASSERT no_warning report "Numeric_std.""rem"": Remainder Truncated"
severity warning;
end if;
return XRem(L'Length-1 downto 0);
end;
-- Id: A.30
function "rem" ( L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_Length : Natural := max(unsigned_num_bits(L), R'Length);
variable XL,XRem : unsigned (L_Length-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_Length);
XRem := XL rem R;
if L_Length>R'Length and XRem(0)/='X'
and XRem(L_Length-1 downto R'Length)
/= (L_Length-1 downto R'Length => '0')
then
ASSERT no_warning report "Numeric_std.""rem"": Remainder Truncated"
severity warning;
end if;
return XRem(R'Length-1 downto 0);
end;
-- Id: A.31
function "rem" ( L : SIGNED; R : INTEGER ) return SIGNED is
constant R_Length : Natural := max(L'Length, signed_num_bits(R));
variable XR,XRem : signed (R_Length-1 downto 0);
begin
XR := TO_SIGNED(R, R_Length);
XRem := L rem XR;
if R_Length>L'Length and XRem(0)/='X'
and XRem(R_Length-1 downto L'Length)
/= (R_Length-1 downto L'Length => XRem(L'Length-1))
then
ASSERT no_warning report "Numeric_std.""rem"": Remainder Truncated"
severity warning;
end if;
return XRem(L'Length-1 downto 0);
end;
-- Id: A.32
function "rem" ( L : INTEGER; R : SIGNED) return SIGNED is
constant L_Length : Natural := max(signed_num_bits(L), R'Length);
variable XL,XRem : signed (L_Length-1 downto 0);
begin
XL := TO_SIGNED(L, L_Length);
XRem := XL rem R;
if L_Length>R'Length and XRem(0)/='X'
and XRem(L_Length-1 downto R'Length)
/= (L_Length-1 downto R'Length => XRem(R'Length-1))
then
ASSERT no_warning report "Numeric_std.""rem"": Remainder Truncated"
severity warning;
end if;
return XRem(R'Length-1 downto 0);
end;
--=============================================================================
-- Id: A.33
function "mod" ( L,R: UNSIGNED) return UNSIGNED is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias xxl : UNSIGNED(L_left downto 0) is L;
alias xxr : UNSIGNED(R_left downto 0) is R;
variable xl : UNSIGNED(L_left downto 0);
variable xr : UNSIGNED(R_left downto 0);
variable fquot,fremain : UNSIGNED(l'length-1 downto 0);
begin
if ((L'length<1) or (R'length<1)) then return NAU; end if;
xl := TO_01(xxl,std_logic' ('X'));
xr := TO_01(xxr,std_logic' ('X'));
if ((xl(xl'left)='X') or (xr(xr'left)='X')) then
fremain := (others=>'X');
return fremain;
end if;
divMod(xl,xr,fquot,fremain);
return fremain;
end;
-- Id: A.34
function "mod" ( L,R: SIGNED) return SIGNED is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias xxl : SIGNED(L_left downto 0) is L;
alias xxr : SIGNED(R_left downto 0) is R;
variable xl : SIGNED(L_left downto 0);
variable xr : SIGNED(R_left downto 0);
variable fquot,fremain : UNSIGNED(l'length-1 downto 0);
variable xnum: UNSIGNED(l'length-1 downto 0);
variable XDENOM: UNSIGNED(r'length-1 downto 0);
variable rneg: boolean := FALSE;
begin
if ((L'length<1) or (R'length<1)) then return NAS; end if;
xl := TO_01(xxl,std_logic' ('X'));
xr := TO_01(xxr,std_logic' ('X'));
if ((xl(xl'left)='X') or (xr(xr'left)='X')) then
fremain := (others=>'X');
return SIGNED(fremain);
end if;
if xl(xl'left)='1' then
xnum:=UNSIGNED(-xl);
else
xNum:=UNSIGNED(xl);
end if;
if xr(xr'left)='1' then
XDENOM:=UNSIGNED(-xr);
rNeg:=TRUE;
else
XDENOM:=UNSIGNED(xr);
end if;
divMod(xnum,XDENOM,fquot,fremain);
if rNeg and l(l'left)='1' then
fremain:="0"-fremain;
elsif rNeg then
fremain:=fremain-XDENOM;
elsif l(l'left)='1' then
fremain:=XDENOM-fremain;
end if;
return SIGNED(fremain);
end;
-- Id: A.35
function "mod" ( L : UNSIGNED; R : NATURAL) return UNSIGNED is
constant R_Length : Natural := max(L'Length, unsigned_num_bits(R));
variable XR,XRem : unsigned (R_Length-1 downto 0);
begin
XR := TO_UNSIGNED(R, R_Length);
XRem := L mod XR;
if R_Length>L'Length and XRem(0)/='X'
and XRem(R_Length-1 downto L'Length)
/= (R_Length-1 downto L'Length => '0')
then
ASSERT no_warning report "Numeric_std.""mod"": Modulus Truncated"
severity warning;
end if;
return XRem(L'Length-1 downto 0);
end;
-- Id: A.36
function "mod" ( L : NATURAL; R : UNSIGNED) return UNSIGNED is
constant L_Length : Natural := max(unsigned_num_bits(L), R'Length);
variable XL,XRem : unsigned (L_Length-1 downto 0);
begin
XL := TO_UNSIGNED(L, L_Length);
XRem := XL mod R;
if L_Length>R'Length and XRem(0)/='X'
and XRem(L_Length-1 downto R'Length)
/= (L_Length-1 downto R'Length => '0')
then
ASSERT no_warning report "Numeric_std.""mod"": Modulus Truncated"
severity warning;
end if;
return XRem(R'Length-1 downto 0);
end;
-- Id: A.37
function "mod" ( L : SIGNED; R : INTEGER ) return SIGNED is
constant R_Length : Natural := max(L'Length, signed_num_bits(R));
variable XR,XRem : signed (R_Length-1 downto 0);
begin
XR := TO_SIGNED(R, R_Length);
XRem := L mod XR;
if R_Length>L'Length and XRem(0)/='X'
and XRem(R_Length-1 downto L'Length)
/= (R_Length-1 downto L'Length => XRem(L'Length-1))
then
ASSERT no_warning report "Numeric_std.""mod"": Modulus Truncated"
severity warning;
end if;
return XRem(L'Length-1 downto 0);
end;
-- Id: A.38
function "mod" ( L : INTEGER; R : SIGNED) return SIGNED is
constant L_Length : Natural := max(signed_num_bits(L), R'Length);
variable XL,XRem : signed (L_Length-1 downto 0);
begin
XL := TO_SIGNED(L, L_Length);
XRem := XL mod R;
if L_Length>R'Length and XRem(0)/='X'
and XRem(L_Length-1 downto R'Length)
/= (L_Length-1 downto R'Length => XRem(R'Length-1))
then
ASSERT no_warning report "Numeric_std.""mod"": Modulus Truncated"
severity warning;
end if;
return XRem(R'Length-1 downto 0);
end;
--=============================================================================
-- Id: C.1
function ">" ( L,R: UNSIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
alias XR: UNSIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : UNSIGNED(L_left downto 0);
variable R01 : UNSIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return not UNSIGNED_LESS_OR_EQUAL (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end ">" ;
-- Id: C.2
function ">" ( L,R: SIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: SIGNED(L_left downto 0) is L;
alias XR: SIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : SIGNED(L_left downto 0);
variable R01 : SIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return not SIGNED_LESS_OR_EQUAL (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end ">" ;
-- Id: C.3
function ">" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: UNSIGNED(R_left downto 0) is R;
variable R01 : UNSIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(l)>R'length then return TRUE; end if;
return not UNSIGNED_LESS_OR_EQUAL (TO_UNSIGNED (L,R01'LENGTH), R01) ;
end ">" ;
-- Id: C.4
function ">" ( L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: SIGNED(R_left downto 0) is R;
variable R01 : SIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if Signed_NUM_BITS(l)>R'length then return L>0; end if;
return not SIGNED_LESS_OR_EQUAL (TO_SIGNED(L,R01'LENGTH), R01) ;
end ">" ;
-- Id: C.5
function ">" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
variable L01 : UNSIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(R)>L'length then return FALSE; end if;
return not UNSIGNED_LESS_OR_EQUAL (L01, TO_UNSIGNED (R,L01'LENGTH)) ;
end ">" ;
-- Id: C.6
function ">" ( L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: SIGNED(L_left downto 0) is L;
variable L01 : SIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if Signed_NUM_BITS(R)>L'length then return 0>R; end if;
return not SIGNED_LESS_OR_EQUAL (L01, TO_SIGNED(R,L01'LENGTH)) ;
end ">" ;
--=============================================================================
-- Id: C.7
function "<" ( L,R: UNSIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
alias XR: UNSIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : UNSIGNED(L_left downto 0);
variable R01 : UNSIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return UNSIGNED_LESS (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end "<" ;
-- Id: C.8
function "<" ( L,R: SIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: SIGNED(L_left downto 0) is L;
alias XR: SIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : SIGNED(L_left downto 0);
variable R01 : SIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return SIGNED_LESS (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end "<" ;
-- Id: C.9
function "<" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: UNSIGNED(R_left downto 0) is R;
variable R01 : UNSIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(L)>R'length then return L<0; end if;
return UNSIGNED_LESS (TO_UNSIGNED(L,R01'LENGTH), R01) ;
end "<" ;
-- Id: C.10
function "<" ( L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: SIGNED(R_left downto 0) is R;
variable R01 : SIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if Signed_NUM_BITS(L)>R'length then return L<0; end if;
return SIGNED_LESS (TO_SIGNED(L,R01'LENGTH), R01) ;
end "<" ;
-- Id: C.11
function "<" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
variable L01 : UNSIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(R)>L'length then return 0<R; end if;
return UNSIGNED_LESS (L01, TO_UNSIGNED (R,L01'LENGTH)) ;
end "<" ;
-- Id: C.12
function "<" ( L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: SIGNED(L_left downto 0) is L;
variable L01 : SIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if Signed_NUM_BITS(R)>L'length then return 0<R; end if;
return SIGNED_LESS (L01, TO_SIGNED (R,L01'LENGTH)) ;
end "<" ;
--=============================================================================
-- Id: C.13
function "<=" ( L,R: UNSIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
alias XR: UNSIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : UNSIGNED(L_left downto 0);
variable R01 : UNSIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return UNSIGNED_LESS_OR_EQUAL (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end "<=" ;
-- Id: C.14
function "<=" ( L,R: SIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: SIGNED(L_left downto 0) is L;
alias XR: SIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : SIGNED(L_left downto 0);
variable R01 : SIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return SIGNED_LESS_OR_EQUAL (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end "<=" ;
-- Id: C.15
function "<=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: UNSIGNED(R_left downto 0) is R;
variable R01 : UNSIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(L)>R'length then return L<0; end if;
return UNSIGNED_LESS_OR_EQUAL (TO_UNSIGNED(L,R01'LENGTH), R01) ;
end "<=" ;
-- Id: C.16
function "<=" ( L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: SIGNED(R_left downto 0) is R;
variable R01 : SIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if Signed_NUM_BITS(L)>R'length then return L<0; end if;
return SIGNED_LESS_OR_EQUAL (TO_SIGNED(L,R01'LENGTH), R01) ;
end "<=" ;
-- Id: C.17
function "<=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
variable L01 : UNSIGNED(L_left downto 0);
begin
if (L_left<0) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(R)>L'length then return 0<R; end if;
return UNSIGNED_LESS_OR_EQUAL (L01, TO_UNSIGNED(R,L01'LENGTH)) ;
end "<=" ;
-- Id: C.18
function "<=" ( L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: SIGNED(L_left downto 0) is L;
variable L01 : SIGNED(L_left downto 0);
begin
if (L_left<0) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if Signed_NUM_BITS(R)>L'length then return 0<R; end if;
return SIGNED_LESS_OR_EQUAL (L01, TO_SIGNED(R,L01'LENGTH)) ;
end "<=" ;
--=============================================================================
-- Id: C.19
function ">=" ( L,R: UNSIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
alias XR: UNSIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : UNSIGNED(L_left downto 0);
variable R01 : UNSIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return not UNSIGNED_LESS (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end ">=" ;
-- Id: C.20
function ">=" ( L,R: SIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: SIGNED(L_left downto 0) is L;
alias XR: SIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : SIGNED(L_left downto 0);
variable R01 : SIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return not SIGNED_LESS (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end ">=" ;
-- Id: C.21
function ">=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: UNSIGNED(R_left downto 0) is R;
variable R01 : UNSIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(L)>R'length then return L>0; end if;
return not UNSIGNED_LESS (TO_UNSIGNED(L,R01'LENGTH), R01) ;
end ">=" ;
-- Id: C.22
function ">=" ( L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: SIGNED(R_left downto 0) is R;
variable R01 : SIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if Signed_NUM_BITS(L)>R'length then return L>0; end if;
return not SIGNED_LESS (TO_SIGNED (L,R01'LENGTH), R01) ;
end ">=" ;
-- Id: C.23
function ">=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
variable L01 : UNSIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(R)>L'length then return 0>R; end if;
return not UNSIGNED_LESS(L01, TO_UNSIGNED(R,L01'LENGTH)) ;
end ">=" ;
-- Id: C.24
function ">=" ( L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: SIGNED(L_left downto 0) is L;
variable L01 : SIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if Signed_NUM_BITS(R)>L'length then return 0>R; end if;
return not SIGNED_LESS (L01, TO_SIGNED(R,L01'LENGTH)) ;
end ">=" ;
--=============================================================================
-- Id: C.25
function "=" ( L,R: UNSIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
alias XR: UNSIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : UNSIGNED(L_left downto 0);
variable R01 : UNSIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return UNSIGNED_equal (RESIZE(L01,SIZE),RESIZE(R01,SIZE)) ;
end "=" ;
-- Id: C.26
function "=" ( L,R: SIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: SIGNED(L_left downto 0) is L;
alias XR: SIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : SIGNED(L_left downto 0);
variable R01 : SIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
R01 := TO_01(XR,std_logic' ('X'));
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return FALSE; end if;
return SIGNED_equal (RESIZE(L01,SIZE), RESIZE(R01,SIZE)) ;
end "=" ;
-- Id: C.27
function "=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: UNSIGNED(R_left downto 0) is R;
variable R01 : UNSIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(L)>R'Length then return FALSE; end if;
return UNSIGNED_equal ( TO_UNSIGNED(L,R01'LENGTH), R01);
end "=" ;
-- Id: C.28
function "=" ( L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: SIGNED(R_left downto 0) is R;
variable R01 : SIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR,std_logic' ('X'));
if (R01(R01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(L)>R'Length then return FALSE; end if;
return SIGNED_equal ( TO_SIGNED(L,R01'LENGTH), R01) ;
end "=" ;
-- Id: C.29
function "=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
variable L01 : UNSIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(R)>L'length then return FALSE; end if;
return UNSIGNED_equal (L01, TO_UNSIGNED (R,L01'LENGTH)) ;
end "=" ;
-- Id: C.30
function "=" ( L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: SIGNED(L_left downto 0) is L;
variable L01 : SIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL,std_logic' ('X'));
if (L01(L01'left)='X') then return FALSE; end if;
if UNSIGNED_NUM_BITS(R)>L'length then return FALSE; end if;
return SIGNED_equal (L01, TO_SIGNED (R,L01'LENGTH)) ;
end "=" ;
--=============================================================================
-- Id: C.31
function "/=" ( L,R: UNSIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
alias XR: UNSIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : UNSIGNED(L_left downto 0);
variable R01 : UNSIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL);
R01 := TO_01(XR);
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return TRUE; end if;
return not(UNSIGNED_equal (RESIZE(L01,SIZE),RESIZE(R01,SIZE))) ;
end "/=" ;
-- Id: C.32
function "/=" ( L,R: SIGNED) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
constant R_left:INTEGER:= R'length-1;
alias XL: SIGNED(L_left downto 0) is L;
alias XR: SIGNED(R_left downto 0) is R;
constant SIZE: NATURAL:= MAX (L'LENGTH, R'LENGTH) ;
variable L01 : SIGNED(L_left downto 0);
variable R01 : SIGNED(R_left downto 0);
begin
if ((L'length<1) or (R'length<1)) then return FALSE; end if;
L01 := TO_01(XL);
R01 := TO_01(XR);
if ((L01(L01'left)='X') or (R01(R01'left)='X')) then return TRUE; end if;
return not(SIGNED_equal (RESIZE(L01,SIZE), RESIZE(R01,SIZE))) ;
end "/=" ;
-- Id: C.33
function "/=" ( L: NATURAL; R: UNSIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: UNSIGNED(R_left downto 0) is R;
variable R01 : UNSIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR);
if (R01(R01'left)='X') then return TRUE; end if;
if UNSIGNED_NUM_BITS(L)>R'Length then return TRUE; end if;
return not(UNSIGNED_equal ( TO_UNSIGNED(L,R01'LENGTH), R01));
end "/=" ;
-- Id: C.34
function "/=" ( L: INTEGER; R: SIGNED) return BOOLEAN is
constant R_left:INTEGER:= R'length-1;
alias XR: SIGNED(R_left downto 0) is R;
variable R01 : SIGNED(R_left downto 0);
begin
if (R'length<1) then return FALSE; end if;
R01 := TO_01(XR);
if (R01(R01'left)='X') then return TRUE; end if;
if Signed_NUM_BITS(L)>R'Length then return TRUE; end if;
return not(SIGNED_equal ( TO_SIGNED(L,R01'LENGTH), R01)) ;
end "/=" ;
-- Id: C.35
function "/=" ( L: UNSIGNED; R: NATURAL) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: UNSIGNED(L_left downto 0) is L;
variable L01 : UNSIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL);
if (L01(L01'left)='X') then return TRUE; end if;
if UNSIGNED_NUM_BITS(R)>L'Length then return TRUE; end if;
return not(UNSIGNED_equal (L01, TO_UNSIGNED (R,L01'LENGTH))) ;
end "/=" ;
-- Id: C.36
function "/=" ( L: SIGNED; R: INTEGER) return BOOLEAN is
constant L_left:INTEGER:= L'length-1;
alias XL: SIGNED(L_left downto 0) is L;
variable L01 : SIGNED(L_left downto 0);
begin
if (L'length<1) then return FALSE; end if;
L01 := TO_01(XL);
if (L01(L01'left)='X') then return TRUE; end if;
if Signed_NUM_BITS(R)>L'Length then return TRUE; end if;
return not(SIGNED_equal (L01, TO_SIGNED (R,L01'LENGTH))) ;
end "/=" ;
--=============================================================================
-- Id: S.1
function shift_left(ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'length<1) then return NAU; end if;
return UNSIGNED(XSLL(STD_LOGIC_VECTOR(ARG),COUNT));
end;
-- Id: S.2
function shift_right(ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'length<1) then return NAU; end if;
return UNSIGNED(XSRL(STD_LOGIC_VECTOR(ARG),COUNT));
end;
-- Id: S.3
function shift_left(ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'length<1) then return NAS; end if;
return SIGNED(XSLL(STD_LOGIC_VECTOR(ARG),COUNT));
end;
-- Id: S.4
function shift_right(ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'length<1) then return NAS; end if;
return SIGNED(XSRA(STD_LOGIC_VECTOR(ARG),COUNT));
end;
--=============================================================================
-- Id: S.5
function rotate_left(ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'length<1) then return NAU; end if;
return UNSIGNED(XROL(STD_LOGIC_VECTOR(ARG),COUNT));
end;
-- Id: S.6
function rotate_right(ARG: UNSIGNED; COUNT: NATURAL) return UNSIGNED is
begin
if (ARG'length<1) then return NAU; end if;
return UNSIGNED(XROR(STD_LOGIC_VECTOR(ARG),COUNT));
end;
-- Id: S.7
function rotate_left(ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'length<1) then return NAS; end if;
return SIGNED(XROL(STD_LOGIC_VECTOR(ARG),COUNT));
end;
-- Id: S.8
function rotate_right(ARG: SIGNED; COUNT: NATURAL) return SIGNED is
begin
if (ARG'length<1) then return NAS; end if;
return SIGNED(XROR(STD_LOGIC_VECTOR(ARG),COUNT));
end;
--=============================================================================
-- Id: D.1
function TO_INTEGER(ARG: UNSIGNED) return NATURAL is
constant ARG_LEFT:INTEGER:= ARG'length-1;
alias XXARG:UNSIGNED(ARG_LEFT downto 0) is ARG;
variable XARG:UNSIGNED(ARG_LEFT downto 0);
variable RESULT: NATURAL:= 0;
variable w : INTEGER:= 1; -- weight factor
begin
if (ARG'length<1) then
assert NO_WARNING
report "numeric_std.TO_INTEGER: null arg"
severity warning;
return 0;
end if;
XARG:= TO_01(XXARG);
if (XARG(XARG'left)='X') then
assert NO_WARNING
report "numeric_std.TO_INTEGER: metavalue arg set to 0"
severity warning;
return 0;
end if;
for i in XARG'reverse_range loop
if XARG (i) = '1' then
RESULT:= RESULT + w;
end if;
if (i /= XARG'left) then w := w + w;
end if;
end loop;
return RESULT;
end TO_INTEGER;
-- Id: D.2
function TO_INTEGER(ARG: SIGNED) return INTEGER is
begin
if ARG(ARG'left) = '0' then
return TO_INTEGER( UNSIGNED (ARG)) ;
else
return (- (TO_INTEGER( UNSIGNED ( - (ARG + 1)))) -1);
end if;
end TO_INTEGER;
-- Id: D.3
function TO_UNSIGNED(ARG,SIZE: NATURAL) return UNSIGNED is
variable RESULT: UNSIGNED (SIZE-1 downto 0) ;
variable i_val:natural := ARG;
begin
if (SIZE < 1) then return NAU; end if;
for i in 0 to RESULT'left loop
if (i_val MOD 2) = 0 then
RESULT(i) := '0';
else RESULT(i) := '1' ;
end if;
i_val := i_val/2 ;
end loop;
if not(i_val=0) then
assert NO_WARNING
report "numeric_std.TO_UNSIGNED : vector truncated"
severity WARNING ;
end if;
return RESULT ;
end TO_UNSIGNED;
-- Id: D.4
function TO_SIGNED(ARG: INTEGER; SIZE: NATURAL) return SIGNED is
variable RESULT: SIGNED (SIZE-1 downto 0) ;
variable b_val : STD_LOGIC:= '0' ;
variable i_val : INTEGER:= ARG ;
begin
if (SIZE < 1) then return NAS; end if;
if (ARG<0) then
b_val := '1' ;
i_val := -(ARG+1) ;
end if ;
for i in 0 to RESULT'left loop
if (i_val MOD 2) = 0 then
RESULT(i) := b_val;
else
RESULT(i) := not b_val ;
end if;
i_val := i_val/2 ;
end loop;
if ((i_val/=0) or (b_val/=RESULT(RESULT'left))) then
assert NO_WARNING
report "numeric_std.TO_SIGNED : vector truncated"
severity WARNING ;
end if;
return RESULT;
end TO_SIGNED;
-- Id: D.5
function TO_UNSIGNED(ARG: STD_LOGIC_VECTOR) return UNSIGNED is
begin
return UNSIGNED(ARG);
end TO_UNSIGNED;
-- Id: D.6
function TO_SIGNED(ARG: STD_LOGIC_VECTOR) return SIGNED is
begin
return SIGNED(ARG);
end TO_SIGNED;
-- Id: D.7
function TO_STDLOGICVECTOR(ARG: UNSIGNED) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(ARG);
end TO_STDLOGICVECTOR;
-- Id: D.8
function TO_STDLOGICVECTOR(ARG: SIGNED) return STD_LOGIC_VECTOR is
begin
return STD_LOGIC_VECTOR(ARG);
end TO_STDLOGICVECTOR;
--=============================================================================
-- Id: R.1
function RESIZE (ARG: SIGNED; NEW_SIZE: NATURAL) return SIGNED is
alias invec : SIGNED (ARG'length-1 downto 0) is ARG ;
variable RESULT: SIGNED (NEW_SIZE-1 downto 0) ;
constant bound : NATURAL:= MIN(ARG'length,RESULT'length)-2 ;
begin
if (NEW_SIZE<1) then return NAS; end if;
RESULT:= (others=>ARG(ARG'left)) ;
if bound >= 0 then
RESULT(bound downto 0) := invec(bound downto 0) ;
end if;
return RESULT;
end RESIZE ;
-- Id: R.2
function RESIZE ( ARG: UNSIGNED; NEW_SIZE: NATURAL) return UNSIGNED is
constant ARG_LEFT:INTEGER:= ARG'length-1;
alias XARG: UNSIGNED(ARG_LEFT downto 0) is ARG;
variable RESULT: UNSIGNED(NEW_SIZE-1 downto 0) := (others=>'0');
begin
if (NEW_SIZE<1) then return NAU; end if;
if XARG'length=0 then return RESULT;
end if;
if (RESULT'length < ARG'length) then
RESULT(RESULT'left downto 0) := XARG(RESULT'left downto 0);
else
RESULT(RESULT'left downto XARG'left+1) := (others => '0');
RESULT(XARG'left downto 0) := XARG;
end if;
return RESULT;
end RESIZE;
--============================================================================
-- Id: L.1
function "not" ( L: UNSIGNED) return UNSIGNED is
variable RESULT: UNSIGNED (L'range);
begin
RESULT:= UNSIGNED(not(STD_LOGIC_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.2
function "and" ( L,R: UNSIGNED ) return UNSIGNED is
variable RESULT: UNSIGNED (L'range);
begin
RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R));
return RESULT;
end "and";
-- Id: L.3
function "or" ( L,R: UNSIGNED ) return UNSIGNED is
variable RESULT: UNSIGNED (L'range);
begin
RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R));
return RESULT;
end "or";
-- Id: L.4
function "nand" ( L,R: UNSIGNED ) return UNSIGNED is
variable RESULT: UNSIGNED (L'range);
begin
RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.5
function "nor" ( L,R: UNSIGNED ) return UNSIGNED is
variable RESULT: UNSIGNED (L'range);
begin
RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.6
function "xor" ( L,R: UNSIGNED ) return UNSIGNED is
variable RESULT: UNSIGNED (L'range);
begin
RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R));
return RESULT;
end "xor";
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this 1076.3 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
-- Id: L.7
--function "xnor" ( L,R: UNSIGNED ) return UNSIGNED is
--variable RESULT: UNSIGNED (L'range);
--begin
-- RESULT:= UNSIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R));
-- return RESULT;
-- end "xnor";
-- Id: L.8
function "not" ( L: SIGNED) return SIGNED is
variable RESULT: SIGNED (L'range);
begin
RESULT:= SIGNED(not(STD_LOGIC_VECTOR(L)));
return RESULT;
end "not";
-- Id: L.9
function "and" ( L,R: SIGNED ) return SIGNED is
variable RESULT: SIGNED (L'range);
begin
RESULT:= SIGNED(STD_LOGIC_VECTOR(L) and STD_LOGIC_VECTOR(R));
return RESULT;
end "and";
-- Id: L.10
function "or" ( L,R: SIGNED ) return SIGNED is
variable RESULT: SIGNED (L'range);
begin
RESULT:= SIGNED(STD_LOGIC_VECTOR(L) or STD_LOGIC_VECTOR(R));
return RESULT;
end "or";
-- Id: L.11
function "nand" ( L,R: SIGNED ) return SIGNED is
variable RESULT: SIGNED (L'range);
begin
RESULT:= SIGNED(STD_LOGIC_VECTOR(L) nand STD_LOGIC_VECTOR(R));
return RESULT;
end "nand";
-- Id: L.12
function "nor" ( L,R: SIGNED ) return SIGNED is
variable RESULT: SIGNED (L'range);
begin
RESULT:= SIGNED(STD_LOGIC_VECTOR(L) nor STD_LOGIC_VECTOR(R));
return RESULT;
end "nor";
-- Id: L.13
function "xor" ( L,R: SIGNED ) return SIGNED is
variable RESULT: SIGNED (L'range);
begin
RESULT:= SIGNED(STD_LOGIC_VECTOR(L) xor STD_LOGIC_VECTOR(R));
return RESULT;
end "xor";
-- -----------------------------------------------------------------------
-- Note : The declaration and implementation of the "xnor" function is
-- specifically commented until at which time the VHDL language has been
-- officially adopted as containing such a function. At such a point,
-- the following comments may be removed along with this notice without
-- further "official" ballotting of this 1076.3 package. It is
-- the intent of this effort to provide such a function once it becomes
-- available in the VHDL standard.
-- -----------------------------------------------------------------------
-- Id: L.14
--function "xnor" ( L,R: SIGNED ) return SIGNED is
--variable RESULT: SIGNED (L'range);
--begin
-- RESULT:= SIGNED(STD_LOGIC_VECTOR(L) xnor STD_LOGIC_VECTOR(R));
-- return RESULT;
-- end "xnor";
--=============================================================================
-- support constants for STD_MATCH:
type STDULOGIC_TABLE is array(STD_ULOGIC, STD_ULOGIC) of STD_ULOGIC;
-- truth table for "and" function
constant AND_TABLE : STDULOGIC_TABLE := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', '0', 'U', 'U', 'U', '0', 'U', 'U' ), -- | U |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | X |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | 1 |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | Z |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ), -- | W |
( '0', '0', '0', '0', '0', '0', '0', '0', '0' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', 'X' ), -- | H |
( 'U', 'X', '0', 'X', 'X', 'X', '0', 'X', 'X' ) -- | - |
);
-- truth table for STD_MATCH function
constant MATCH_TABLE : STDULOGIC_TABLE := (
-- ----------------------------------------------------
-- | U X 0 1 Z W L H - | |
-- ----------------------------------------------------
( 'U', 'U', 'U', 'U', 'U', 'U', 'U', 'U', '1' ), -- | U |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | X |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | 0 |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | 1 |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | Z |
( 'U', 'X', 'X', 'X', 'X', 'X', 'X', 'X', '1' ), -- | W |
( 'U', 'X', '1', '0', 'X', 'X', '1', '0', '1' ), -- | L |
( 'U', 'X', '0', '1', 'X', 'X', '0', '1', '1' ), -- | H |
( '1', '1', '1', '1', '1', '1', '1', '1', '1' ) -- | - |
);
-- Id: M.1
function STD_MATCH (L, R: STD_ULOGIC) return BOOLEAN is
variable VALUE : STD_ULOGIC;
begin
VALUE := MATCH_TABLE(L, R);
return VALUE = '1';
end STD_MATCH;
-- Id: M.2
function STD_MATCH (L, R: STD_LOGIC_VECTOR) return BOOLEAN is
alias LV: STD_LOGIC_VECTOR ( 1 to L'LENGTH ) is L;
alias RV: STD_LOGIC_VECTOR ( 1 to R'LENGTH ) is R;
variable VALUE: STD_ULOGIC:= '1';
begin
-- Check that both input vectors are the same length.
if LV'LENGTH /= RV'LENGTH then
assert NO_WARNING
report "STD_MATCH input arguments are not of equal length"
severity warning;
return FALSE;
else
for i in LV'LOW to LV'HIGH loop
VALUE := AND_TABLE(MATCH_TABLE(LV(i), RV(i)), VALUE);
end loop;
return VALUE = '1';
end if;
end STD_MATCH;
--=============================================================================
end numeric_std;
|
entity t is
end;
architecture behav of t is
begin
assert (1 + 1) * 1 = 2;
end behav;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Design Name:
-- Module Name: DMA_Calculate - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision 1.20 - Taken out from the original version. 26.07.2007
--
-- Revision 1.10 - Msg inserted. 26.02.2007
--
-- Revision 1.00 - Created. 09.02.2007
--
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
library work;
use work.abb64Package.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity DMA_Calculate is
port (
-- Downstream Registers from MWr Channel
DMA_PA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- EP (local)
DMA_HA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- Host (remote)
DMA_BDA : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Length : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_Control : in std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, for better timing
HA_is_64b : in std_logic;
BDA_is_64b : in std_logic;
-- Calculation in advance, for better timing
Leng_Hi19b_True : in std_logic;
Leng_Lo7b_True : in std_logic;
-- Parameters fed to DMA_FSM
DMA_PA_Loaded : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_PA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_HA_Var : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BDA_fsm : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
BDA_is_64b_fsm : out std_logic;
DMA_Snout_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Body_Length : out std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_Tail_Length : out std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- Only for downstream channel
DMA_PA_Snout : out std_logic_vector(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number : out std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
-- Engine control signals
DMA_Start : in std_logic;
DMA_Start2 : in std_logic; -- out of consecutive dex
-- Control signals to FSM
No_More_Bodies : out std_logic; -- No more block(s) of Max_Size
ThereIs_Snout : out std_logic; -- 1st packet before Body blocks
ThereIs_Body : out std_logic; -- Block(s) of Max_Size
ThereIs_Tail : out std_logic; -- Last packet with size less than Max_Size
ThereIs_Dex : out std_logic; -- Not the last descriptor
HA64bit : out std_logic; -- Host Address is 64-bit
Addr_Inc : out std_logic; -- Peripheral Address increase token
-- FSM indicators
State_Is_LoadParam : in std_logic;
State_Is_Snout : in std_logic;
State_Is_Body : in std_logic;
-- State_Is_Tail : IN std_logic;
-- Additional
Param_Max_Cfg : in std_logic_vector(2 downto 0);
-- Common ports
dma_clk : in std_logic;
dma_reset : in std_logic
);
end entity DMA_Calculate;
architecture Behavioral of DMA_Calculate is
-- Significant bits from the MaXSiZe parameter
signal Max_TLP_Size : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal mxsz_left : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_mid : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal mxsz_right : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Signals masked by MaxSize
signal DMA_Leng_Left_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Mid_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
signal DMA_Leng_Right_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT);
-- Alias
signal Lo_Leng_Left_Msk_is_True : std_logic;
signal Lo_Leng_Mid_Msk_is_True : std_logic;
signal Lo_Leng_Right_Msk_is_True : std_logic;
-- Masked values of HA and Length
signal DMA_HA_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Length_Msk : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Indicates whether the DMA_PA is already accepted
signal PA_is_taken : std_logic;
-- Calculation for the PA of the next DMA, if UPA bit = 0
signal DMA_PA_next : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_PA_current : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- eventual PA parameter for the current DMA transaction
signal DMA_PA_Loaded_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- Calculation in advance, only for better timing
signal Carry_PA_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Carry_PAx_plus_Leng : std_logic_vector(CBIT_CARRY downto 0);
signal Leng_Hi_plus_PA_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
signal Leng_Hi_plus_PAx_Hi : std_logic_vector(C_DBUS_WIDTH-1 downto CBIT_CARRY);
-- DMA parameters from the register module
signal DMA_PA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BDA_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Length_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_Control_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- delay
signal State_Is_Snout_r1 : std_logic;
signal State_Is_Body_r1 : std_logic;
-- from control word
signal Dex_is_Last : std_logic;
signal Engine_Ends : std_logic;
-- Major FSM control signals
signal ThereIs_Snout_i : std_logic;
signal ThereIs_Body_i : std_logic;
signal ThereIs_Tail_i : std_logic;
signal Snout_Only : std_logic;
signal ThereIs_Dex_i : std_logic;
signal No_More_Bodies_i : std_logic;
-- Address/Length combination
signal ALc : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
-- Compressed ALc
-- ALc_B bit means the ALc has carry in, making an extra Body block.
signal ALc_B : std_logic;
signal ALc_B_wire : std_logic;
-- ALc_T bit means the ALc has trailer, making a final Tail block.
signal ALc_T : std_logic;
signal ALc_T_wire : std_logic;
-- Compressed Length
-- Leng_Two bit means Length >= 2 Max_Size.
signal Leng_Two : std_logic;
-- Leng_One bit means Length >= 1 Max_Size.
signal Leng_One : std_logic;
-- Leng_nint bit means Length is not integral of Max_Sizes.
signal Leng_nint : std_logic;
signal Length_analysis : std_logic_vector(2 downto 0);
signal Snout_Body_Tail : std_logic_vector(2 downto 0);
-- Byte counter
signal DMA_Byte_Counter : std_logic_vector(C_DBUS_WIDTH-1 downto 0); -- !!! Elastic
signal Length_minus : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_BC_Carry : std_logic_vector(CBIT_CARRY downto 0);
-- Remote & Local Address variable
signal DMA_HA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal DMA_HA_Carry32 : std_logic_vector(C_DBUS_WIDTH/2 downto 0);
signal DMA_PA_Var_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
-- BDA parameter is buffered for FSM module
signal DMA_BDA_fsm_i : std_logic_vector(C_DBUS_WIDTH-1 downto 0);
signal BDA_is_64b_fsm_i : std_logic;
-- Token bits out of Control word
signal HA64bit_i : std_logic;
signal Addr_Inc_i : std_logic;
signal use_PA : std_logic;
-- for better timing
signal HA_gap : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
--
signal DMA_Snout_Length_i : std_logic_vector(C_MAXSIZE_FLD_BIT_TOP downto 0);
signal DMA_Tail_Length_i : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
-- for better timing
signal raw_Tail_Length : std_logic_vector(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
signal DMA_PA_Snout_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_PA_Body_Carry : std_logic_vector(CBIT_CARRY downto 0);
signal DMA_BAR_Number_i : std_logic_vector(C_ENCODE_BAR_NUMBER-1 downto 0);
begin
-- Partition indicators
No_More_Bodies <= No_More_Bodies_i;
ThereIs_Snout <= ThereIs_Snout_i;
ThereIs_Body <= ThereIs_Body_i;
ThereIs_Tail <= ThereIs_Tail_i;
ThereIs_Dex <= ThereIs_Dex_i;
HA64bit <= HA64bit_i;
Addr_Inc <= Addr_Inc_i;
--
DMA_PA_Loaded <= DMA_PA_Loaded_i;
DMA_PA_Var <= DMA_PA_Var_i;
DMA_HA_Var <= DMA_HA_Var_i;
DMA_BDA_fsm <= DMA_BDA_fsm_i;
BDA_is_64b_fsm <= BDA_is_64b_fsm_i;
-- Only for downstream channel
DMA_PA_Snout <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
DMA_BAR_Number <= DMA_BAR_Number_i;
-- different lengths
DMA_Snout_Length <= DMA_Snout_Length_i;
DMA_Body_Length <= Max_TLP_Size;
DMA_Tail_Length <= DMA_Tail_Length_i;
-- Register stubs
DMA_PA_i <= DMA_PA;
DMA_HA_i <= DMA_HA;
DMA_BDA_i <= DMA_BDA;
DMA_Length_i <= DMA_Length;
DMA_Control_i <= DMA_Control;
-- ---------------------------------------------------------------
-- Parameters should be captured by the start/start2 and be kept
-- in case Pause command comes.
--
Syn_Param_Capture :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Addr_Inc_i <= '0';
use_PA <= '0';
Dex_is_Last <= '0';
Engine_Ends <= '1';
DMA_BAR_Number_i <= (others => '0');
DMA_BDA_fsm_i <= (others => '0');
BDA_is_64b_fsm_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' or DMA_Start2 = '1' then
Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
DMA_BAR_Number_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_BAR_TOP downto CINT_BIT_DMA_CTRL_BAR_BOT);
DMA_BDA_fsm_i <= DMA_BDA_i;
BDA_is_64b_fsm_i <= BDA_is_64b;
else
Addr_Inc_i <= Addr_Inc_i;
use_PA <= use_PA;
Dex_is_Last <= Dex_is_Last;
Engine_Ends <= Engine_Ends;
DMA_BAR_Number_i <= DMA_BAR_Number_i;
DMA_BDA_fsm_i <= DMA_BDA_fsm_i;
BDA_is_64b_fsm_i <= BDA_is_64b_fsm_i;
end if;
end if;
end process;
-- Addr_Inc_i <= DMA_Control_i(CINT_BIT_DMA_CTRL_AINC);
-- use_PA <= DMA_Control_i(CINT_BIT_DMA_CTRL_UPA);
-- Dex_is_Last <= DMA_Control_i(CINT_BIT_DMA_CTRL_LAST);
-- Engine_Ends <= DMA_Control_i(CINT_BIT_DMA_CTRL_END);
-- use_Irpt_Done <= not DMA_Control_i(CINT_BIT_DMA_CTRL_EDI);
-- Means there is consecutive descriptor(s)
ThereIs_Dex_i <= not Dex_is_Last and not Engine_Ends;
-- ---------------------------------------------------------------
-- PA_i selection
--
Syn_Calc_DMA_PA :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_current <= (others => '0');
-- DMA_BAR_Number_i <= (Others=>'0');
PA_is_taken <= '0';
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken = '0' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken = '0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '1' then
DMA_PA_current <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
PA_is_taken <= '1';
elsif DMA_Start2 = '1' and PA_is_taken = '0' and DMA_Control_i(CINT_BIT_DMA_CTRL_UPA) = '0' then
DMA_PA_current(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_next;
PA_is_taken <= '1';
else
DMA_PA_current <= DMA_PA_current;
if DMA_Start = '0' and DMA_Start2 = '0' then
PA_is_taken <= '0';
else
PA_is_taken <= PA_is_taken;
end if;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- PA_next Calculation
--
Syn_Calc_DMA_PA_next :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_next <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if DMA_Start = '1' and PA_is_taken = '0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PA_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PA_Hi
+ Carry_PA_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_i(C_DBUS_WIDTH-1 downto 2) &"00";
end if;
elsif DMA_Start2 = '1' and PA_is_taken = '0' then
if DMA_Control_i(CINT_BIT_DMA_CTRL_AINC) = '1' then
DMA_PA_next(CBIT_CARRY-1 downto 0) <= Carry_PAx_plus_Leng(CBIT_CARRY-1 downto 0);
DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= Leng_Hi_plus_PAx_Hi
+ Carry_PAx_plus_Leng(CBIT_CARRY);
else
DMA_PA_next <= DMA_PA_next;
end if;
else
DMA_PA_next <= DMA_PA_next;
end if;
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PA_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PA_plus_Leng :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PA_plus_Leng <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PA_plus_Leng <= ('0'& DMA_PA_i(CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Carry_PAx_plus_Leng(16 downto 0)
--
Syn_Calc_Carry_PAx_plus_Leng :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Carry_PAx_plus_Leng <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Carry_PAx_plus_Leng <= ('0'& DMA_PA_next (CBIT_CARRY-1 downto 2) &"00")
+ ('0'& DMA_Length_i(CBIT_CARRY-1 downto 2) &"00");
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PA_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PA_Hi :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PA_Hi <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PA_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_i(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- ---------------------------------------------------------------
-- Leng_Hi_plus_PAx_Hi(31 downto 16)
--
Syn_Calc_Leng_Hi_plus_PAx_Hi :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Hi_plus_PAx_Hi <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Leng_Hi_plus_PAx_Hi <= DMA_Length_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_next(C_DBUS_WIDTH-1 downto CBIT_CARRY);
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_Leng_Left_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left;
DMA_Leng_Mid_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid;
DMA_Leng_Right_Msk <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right;
-- -----------------------------------------------------------------------------------------------------------------------------------
DMA_HA_Msk <= (DMA_HA_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_HA_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
DMA_Length_Msk <= (DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right)
& DMA_Length_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 2)
& "00";
-- -----------------------------------------------------------------------------------------------------------------------------------
Lo_Leng_Left_Msk_is_True <= '0' when DMA_Leng_Left_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Mid_Msk_is_True <= '0' when DMA_Leng_Mid_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
Lo_Leng_Right_Msk_is_True <= '0' when DMA_Leng_Right_Msk = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) else '1';
-- ----------------------------------------------------------
-- Synchronous Register: Leng_Info(Compressed Length Information)
---
Syn_Calc_Parameter_Leng_Info :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Leng_Two <= '0';
Leng_One <= '0';
Leng_nint <= '0';
elsif dma_clk'event and dma_clk = '1' then
Leng_Two <= Leng_Hi19b_True or Lo_Leng_Left_Msk_is_True;
Leng_One <= Lo_Leng_Mid_Msk_is_True;
Leng_nint <= Leng_Lo7b_True or Lo_Leng_Right_Msk_is_True;
end if;
end process;
-- -----------------------------------------------------------------------------------------------------------------------------------
ALc_B_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
else '1';
ALc_T_wire <= '0' when (ALc(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_right) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and ALc(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_BOT-1 downto 0)
else '1';
-- -----------------------------------------------------------------------------------------------------------------------------------
-- -------------------------------------------------------
-- Synchronous Register: ALc (Address-Length combination)
---
Syn_Calc_Parameter_ALc :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
ALc <= (others => '0');
ALc_B <= '0';
ALc_T <= '0';
elsif dma_clk'event and dma_clk = '1' then
ALc <= DMA_Length_Msk + DMA_HA_Msk;
ALc_B <= ALc_B_wire;
ALc_T <= ALc_T_wire;
end if;
end process;
-- concatenation of the Length information
Length_analysis <= Leng_Two & Leng_One & Leng_nint;
-- -------------------------------------------
-- Analysis on the DMA division
-- truth-table expressions
--
Comb_S_B_T :
process (
Length_analysis
, ALc_B
, ALc_T
)
begin
case Length_analysis is
-- Zero-length DMA, nothing to send
when "000" =>
Snout_Body_Tail <= "000";
-- Length < Max_Size. Always Snout and never Body, Tail depends on ALc.
when "001" =>
Snout_Body_Tail <= '1' & '0' & (ALc_B and ALc_T);
-- Length = Max_Size. Division depends only on ALc-Tail.
when "010" =>
Snout_Body_Tail <= ALc_T & not ALc_T & ALc_T;
-- Length = (k+1) Max_Size, k>=1. Always Body. Snout and Tail depend on ALc-Tail.
-- Body = Leng_Two or not ALc_T
when "100" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
when "110" =>
Snout_Body_Tail <= ALc_T & '1' & ALc_T;
-- Length = (1+d) Max_Size, 0<d<1. Always Snout. Body and Tail copy ALc.
when "011" =>
Snout_Body_Tail <= '1' & ALc_B & ALc_T;
-- Length = (k+1+d) Max_Size, k>=1, 0<d<1. Always Snout and Body. Tail copies ALc-Tail.
-- Body = Leng_Two or ALc_B
when "101" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
when "111" =>
Snout_Body_Tail <= '1' & '1' & ALc_T;
-- dealt as zero-length DMA
when others =>
Snout_Body_Tail <= "000";
end case;
end process;
-- -----------------------------------------------
-- Synchronous Register:
-- ThereIs_Snout
-- ThereIs_Body
-- ThereIs_Tail
--
Syn_Calc_Parameters_SBT :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
ThereIs_Snout_i <= '0';
ThereIs_Body_i <= '0';
ThereIs_Tail_i <= '0';
Snout_Only <= '0';
elsif dma_clk'event and dma_clk = '1' then
ThereIs_Snout_i <= Snout_Body_Tail(2);
ThereIs_Body_i <= Snout_Body_Tail(1);
ThereIs_Tail_i <= Snout_Body_Tail(0);
Snout_Only <= ALc_T and not Snout_Body_Tail(0);
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA_gap
--
Syn_Calc_HA_gap :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA_gap <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
HA_gap <= Max_TLP_Size - DMA_HA_Msk;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Snout_Carry
--
FSM_Calc_DMA_PA_Snout_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Snout_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Snout_Carry <= ('0'& DMA_PA_current(CBIT_CARRY-1 downto 0)) + HA_gap;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Body_Carry
--
FSM_Calc_DMA_PA_Body_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Body_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_PA_Body_Carry <= ('0'& DMA_PA_Var_i(CBIT_CARRY-1 downto 0)) + Max_TLP_Size;
end if;
end process;
-- ------------------------------------------------------------------
-- Synchronous Register: Length_minus
--
Sync_Calc_Length_minus :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
Length_minus <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
Length_minus <= DMA_Length_i - Max_TLP_Size;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_BC_Carry
--
FSM_Calc_DMA_BC_Carry :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_BC_Carry <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_BC_Carry <= ('0'& DMA_Byte_Counter(CBIT_CARRY-1 downto 0)) - Max_TLP_Size;
end if;
end process;
-- --------------------------------------------
-- Synchronous reg: DMA_Snout_Length
-- DMA_Tail_Length
--
FSM_Calc_DMA_Snout_Tail_Lengths :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Snout_Length_i <= (others => '0');
DMA_Tail_Length_i <= (others => '0');
raw_Tail_Length <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
DMA_Tail_Length_i(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= (raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
and mxsz_right(C_TLP_FLD_WIDTH_OF_LENG+1 downto C_MAXSIZE_FLD_BIT_BOT)
) & raw_Tail_Length( C_MAXSIZE_FLD_BIT_BOT-1 downto 0);
if State_Is_LoadParam = '1' then
raw_Tail_Length(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0) <= DMA_Length_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0)
+ DMA_HA_Msk(C_TLP_FLD_WIDTH_OF_LENG+1 downto 0);
if Snout_Only = '1' then
DMA_Snout_Length_i <= DMA_Length_i(C_MAXSIZE_FLD_BIT_TOP downto 2) &"00";
else
DMA_Snout_Length_i <= Max_TLP_Size - DMA_HA_Msk;
end if;
else
DMA_Snout_Length_i <= DMA_Snout_Length_i;
raw_Tail_Length <= raw_Tail_Length;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous Delays:
-- State_Is_Snout_r1
-- State_Is_Body_r1
--
Syn_Delay_State_is_x :
process (dma_clk)
begin
if dma_clk'event and dma_clk = '1' then
State_Is_Snout_r1 <= State_Is_Snout;
State_Is_Body_r1 <= State_Is_Body;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Carry32
--
FSM_Calc_DMA_HA_Carry32 :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Carry32 <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Carry32 <= '0' & DMA_HA_i(C_DBUS_WIDTH/2-1 downto 2) & "00"; -- temp
elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Carry32(C_DBUS_WIDTH/2 downto C_MAXSIZE_FLD_BIT_BOT) <= ('0'& DMA_HA_Var_i(C_DBUS_WIDTH/2-1 downto C_MAXSIZE_FLD_BIT_TOP+1) &
(DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right)
) + mxsz_mid;
else
DMA_HA_Carry32 <= DMA_HA_Carry32;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_HA_Var
--
FSM_Calc_DMA_HA_Var :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_HA_Var_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_HA_Var_i <= DMA_HA_i(C_DBUS_WIDTH-1 downto 2) & "00"; -- temp
elsif State_Is_Snout_r1 = '1' or State_Is_Body_r1 = '1' then
-- elsif State_Is_Snout = '1' or State_Is_Body = '1' then
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2) <= DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_DBUS_WIDTH/2)
+ DMA_HA_Carry32(C_DBUS_WIDTH/2);
DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_BOT) <= (DMA_HA_Var_i(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
& (DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and not mxsz_right))
+ mxsz_mid;
DMA_HA_Var_i(C_MAXSIZE_FLD_BIT_BOT-1 downto 0) <= (others => '0'); -- MaxSize aligned
else
DMA_HA_Var_i <= DMA_HA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- HA64bit
--
FSM_Calc_HA64bit :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
HA64bit_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
HA64bit_i <= HA_is_64b;
elsif DMA_HA_Carry32(C_DBUS_WIDTH/2) = '1' then
HA64bit_i <= '1';
else
HA64bit_i <= HA64bit_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Var
--
FSM_Calc_DMA_PA_Var :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Var_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if Addr_Inc_i = '1' and ThereIs_Snout_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_current(CBIT_CARRY-1 downto 0)
+ HA_gap(C_MAXSIZE_FLD_BIT_TOP downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_current(C_DBUS_WIDTH-1 downto CBIT_CARRY);
else
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto 0) <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
end if;
elsif State_Is_Snout_r1 = '1' then
---- elsif State_Is_Snout = '1' then
if Addr_Inc_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Var_i(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Snout_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
elsif State_Is_Body_r1 = '1' then
---- elsif State_Is_Body = '1' then
if Addr_Inc_i = '1' then
DMA_PA_Var_i(CBIT_CARRY-1 downto 0) <= DMA_PA_Body_Carry(CBIT_CARRY-1 downto 0);
DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_PA_Var_i(C_DBUS_WIDTH-1 downto CBIT_CARRY)
+ DMA_PA_Body_Carry(CBIT_CARRY);
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
else
DMA_PA_Var_i <= DMA_PA_Var_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg:
-- DMA_PA_Loaded_i
--
FSM_Calc_DMA_PA_Loaded_i :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_PA_Loaded_i <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
DMA_PA_Loaded_i <= DMA_PA_current(C_DBUS_WIDTH-1 downto 0);
else
DMA_PA_Loaded_i <= DMA_PA_Loaded_i;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: DMA_Byte_Counter
---
FSM_Calc_DMA_Byte_Counter :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
DMA_Byte_Counter <= (others => '0');
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
if ALc_B = '0' and ALc_T = '1' then
DMA_Byte_Counter <= Length_minus;
else
DMA_Byte_Counter <= DMA_Length_i(C_DBUS_WIDTH-1 downto 2) & "00";
end if;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY) <= DMA_Byte_Counter(C_DBUS_WIDTH-1 downto CBIT_CARRY)
- DMA_BC_Carry(CBIT_CARRY);
DMA_Byte_Counter(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT) <= DMA_BC_Carry(CBIT_CARRY-1 downto C_MAXSIZE_FLD_BIT_BOT);
else
DMA_Byte_Counter <= DMA_Byte_Counter;
end if;
end if;
end process;
-- -------------------------------------------------------------
-- Synchronous reg: No_More_Bodies
---
FSM_Calc_No_More_Bodies :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then
No_More_Bodies_i <= '0';
elsif dma_clk'event and dma_clk = '1' then
if State_Is_LoadParam = '1' then
No_More_Bodies_i <= not ThereIs_Body_i;
-- elsif State_Is_Body_r1 = '1' then
elsif State_Is_Body = '1' then
if DMA_Byte_Counter(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1) = C_ALL_ZEROS(C_DBUS_WIDTH-1 downto C_MAXSIZE_FLD_BIT_TOP+1)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_left) = C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
and (DMA_Byte_Counter(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT) and mxsz_mid) /= C_ALL_ZEROS(C_MAXSIZE_FLD_BIT_TOP downto C_MAXSIZE_FLD_BIT_BOT)
then
No_More_Bodies_i <= '1';
else
No_More_Bodies_i <= '0';
end if;
else
No_More_Bodies_i <= No_More_Bodies_i;
end if;
end if;
end process;
-- ------------------------------------------
-- Configuration pamameters: Param_Max_Cfg
--
Syn_Config_Param_Max_Cfg :
process (dma_clk, dma_reset)
begin
if dma_reset = '1' then -- 0x0080 Bytes
mxsz_left <= "111110"; -- 6 bits
mxsz_mid <= "000001"; -- 6 bits
mxsz_right <= "000000"; -- 6 bits
elsif dma_clk'event and dma_clk = '1' then
case Param_Max_Cfg is
when "000" => -- 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
when "001" => -- 0x0100 Bytes
mxsz_left <= "111100";
mxsz_mid <= "000010";
mxsz_right <= "000001";
when "010" => -- 0x0200 Bytes
mxsz_left <= "111000";
mxsz_mid <= "000100";
mxsz_right <= "000011";
when "011" => -- 0x0400 Bytes
mxsz_left <= "110000";
mxsz_mid <= "001000";
mxsz_right <= "000111";
when "100" => -- 0x0800 Bytes
mxsz_left <= "100000";
mxsz_mid <= "010000";
mxsz_right <= "001111";
when "101" => -- 0x1000 Bytes
mxsz_left <= "000000";
mxsz_mid <= "100000";
mxsz_right <= "011111";
when others => -- as 0x0080 Bytes
mxsz_left <= "111110";
mxsz_mid <= "000001";
mxsz_right <= "000000";
end case;
end if;
end process;
Max_TLP_Size <= mxsz_mid & CONV_STD_LOGIC_VECTOR(0, C_MAXSIZE_FLD_BIT_BOT);
end architecture Behavioral;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Steffen Koehler
--
-- Module: Synchronizes a strobe signal across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes multiple high-active bits from clock-domain
-- 'Clock1' to clock-domain 'Clock2'. The clock-domain boundary crossing is
-- done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy
-- flag is additionally calculated and can be used to block new inputs. All
-- bits are independent from each other. Multiple consecutive strobes are
-- suppressed by a rising edge detection.
--
-- ATTENTION:
-- Use this synchronizer only for one-cycle high-active signals (strobes).
--
-- CONSTRAINTS:
-- General:
-- This module uses sub modules which need to be constrained. Please
-- attend to the notes of the instantiated sub modules.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
entity sync_Strobe IS
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
GATED_INPUT_BY_BUSY : BOOLEAN := TRUE -- use gated input (by busy signal)
);
port (
Clock1 : in STD_LOGIC; -- <Clock> input clock domain
Clock2 : in STD_LOGIC; -- <Clock> output clock domain
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock1: input bits
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock2: output bits
Busy : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock1: busy bits
);
end;
architecture rtl of sync_Strobe is
attribute SHREG_EXTRACT : STRING;
signal syncClk1_In : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk1_Out : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk2_In : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk2_Out : STD_LOGIC_VECTOR(BITS - 1 downto 0);
BEGIN
gen : for i in 0 to BITS - 1 generate
signal D0 : STD_LOGIC := '0';
signal T1 : STD_LOGIC := '0';
signal D2 : STD_LOGIC := '0';
signal Changed_Clk1 : STD_LOGIC;
signal Changed_Clk2 : STD_LOGIC;
signal Busy_i : STD_LOGIC;
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT OF D0 : signal is "NO";
attribute SHREG_EXTRACT OF T1 : signal is "NO";
attribute SHREG_EXTRACT OF D2 : signal is "NO";
begin
process(Clock1)
begin
if rising_edge(Clock1) then
-- input delay for rising edge detection
D0 <= Input(I);
-- T-FF to converts a strobe to a flag signal
if (GATED_INPUT_BY_BUSY = TRUE) then
T1 <= (Changed_Clk1 and not Busy_i) xor T1;
else
T1 <= Changed_Clk1 xor T1;
end if;
end if;
end process;
-- D-FF for level change detection (both edges)
D2 <= syncClk2_Out(I) when rising_edge(Clock2);
-- assign syncClk*_In signals
syncClk2_In(I) <= T1;
syncClk1_In(I) <= syncClk2_Out(I); -- D2
Changed_Clk1 <= not D0 and Input(I); -- rising edge detection
Changed_Clk2 <= syncClk2_Out(I) xor D2; -- level change detection; restore strobe signal from flag
Busy_i <= T1 xor syncClk1_Out(I); -- calculate busy signal
-- output signals
Output(I) <= Changed_Clk2;
Busy(I) <= Busy_i;
end generate;
syncClk2 : entity PoC.sync_Bits
generic map (
BITS => BITS -- number of bit to be synchronized
)
port map (
Clock => Clock2, -- <Clock> output clock domain
Input => syncClk2_In, -- @async: input bits
Output => syncClk2_Out -- @Clock: output bits
);
syncClk1 : entity PoC.sync_Bits
generic map (
BITS => BITS -- number of bit to be synchronized
)
port map (
Clock => Clock1, -- <Clock> output clock domain
Input => syncClk1_In, -- @async: input bits
Output => syncClk1_Out -- @Clock: output bits
);
end; |
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
--
-- =============================================================================
-- Authors: Patrick Lehmann
-- Steffen Koehler
--
-- Module: Synchronizes a strobe signal across clock-domain boundaries
--
-- Description:
-- ------------------------------------
-- This module synchronizes multiple high-active bits from clock-domain
-- 'Clock1' to clock-domain 'Clock2'. The clock-domain boundary crossing is
-- done by a T-FF, two synchronizer D-FFs and a reconstructive XOR. A busy
-- flag is additionally calculated and can be used to block new inputs. All
-- bits are independent from each other. Multiple consecutive strobes are
-- suppressed by a rising edge detection.
--
-- ATTENTION:
-- Use this synchronizer only for one-cycle high-active signals (strobes).
--
-- CONSTRAINTS:
-- General:
-- This module uses sub modules which need to be constrained. Please
-- attend to the notes of the instantiated sub modules.
--
-- License:
-- =============================================================================
-- Copyright 2007-2015 Technische Universitaet Dresden - Germany
-- Chair for VLSI-Design, Diagnostics and Architecture
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
-- =============================================================================
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library PoC;
entity sync_Strobe IS
generic (
BITS : POSITIVE := 1; -- number of bit to be synchronized
GATED_INPUT_BY_BUSY : BOOLEAN := TRUE -- use gated input (by busy signal)
);
port (
Clock1 : in STD_LOGIC; -- <Clock> input clock domain
Clock2 : in STD_LOGIC; -- <Clock> output clock domain
Input : in STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock1: input bits
Output : out STD_LOGIC_VECTOR(BITS - 1 downto 0); -- @Clock2: output bits
Busy : out STD_LOGIC_VECTOR(BITS - 1 downto 0) -- @Clock1: busy bits
);
end;
architecture rtl of sync_Strobe is
attribute SHREG_EXTRACT : STRING;
signal syncClk1_In : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk1_Out : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk2_In : STD_LOGIC_VECTOR(BITS - 1 downto 0);
signal syncClk2_Out : STD_LOGIC_VECTOR(BITS - 1 downto 0);
BEGIN
gen : for i in 0 to BITS - 1 generate
signal D0 : STD_LOGIC := '0';
signal T1 : STD_LOGIC := '0';
signal D2 : STD_LOGIC := '0';
signal Changed_Clk1 : STD_LOGIC;
signal Changed_Clk2 : STD_LOGIC;
signal Busy_i : STD_LOGIC;
-- Prevent XST from translating two FFs into SRL plus FF
attribute SHREG_EXTRACT OF D0 : signal is "NO";
attribute SHREG_EXTRACT OF T1 : signal is "NO";
attribute SHREG_EXTRACT OF D2 : signal is "NO";
begin
process(Clock1)
begin
if rising_edge(Clock1) then
-- input delay for rising edge detection
D0 <= Input(I);
-- T-FF to converts a strobe to a flag signal
if (GATED_INPUT_BY_BUSY = TRUE) then
T1 <= (Changed_Clk1 and not Busy_i) xor T1;
else
T1 <= Changed_Clk1 xor T1;
end if;
end if;
end process;
-- D-FF for level change detection (both edges)
D2 <= syncClk2_Out(I) when rising_edge(Clock2);
-- assign syncClk*_In signals
syncClk2_In(I) <= T1;
syncClk1_In(I) <= syncClk2_Out(I); -- D2
Changed_Clk1 <= not D0 and Input(I); -- rising edge detection
Changed_Clk2 <= syncClk2_Out(I) xor D2; -- level change detection; restore strobe signal from flag
Busy_i <= T1 xor syncClk1_Out(I); -- calculate busy signal
-- output signals
Output(I) <= Changed_Clk2;
Busy(I) <= Busy_i;
end generate;
syncClk2 : entity PoC.sync_Bits
generic map (
BITS => BITS -- number of bit to be synchronized
)
port map (
Clock => Clock2, -- <Clock> output clock domain
Input => syncClk2_In, -- @async: input bits
Output => syncClk2_Out -- @Clock: output bits
);
syncClk1 : entity PoC.sync_Bits
generic map (
BITS => BITS -- number of bit to be synchronized
)
port map (
Clock => Clock1, -- <Clock> output clock domain
Input => syncClk1_In, -- @async: input bits
Output => syncClk1_Out -- @Clock: output bits
);
end; |
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-13.07:37:13)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_alap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 30);
output1, output2, output3: OUT unsigned(0 TO 31));
END mpegmv_alap_entity;
ARCHITECTURE mpegmv_alap_description OF mpegmv_alap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register2: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register3: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register4: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register5: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register6: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register7: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register8: unsigned(0 TO 31) := "00000000000000000000000000000000";
SHARED VARIABLE register9: unsigned(0 TO 31) := "00000000000000000000000000000000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
register2 := input2 * 2;
register3 := input3 * 3;
WHEN "00000010" =>
register1 := register1 + 5;
register4 := input4 * 6;
register5 := input5 * 7;
register2 := register2 + 9;
register6 := input6 * 10;
register3 := register3 + 12;
register7 := input7 * 13;
WHEN "00000011" =>
register1 := register4 + register1;
register4 := input8 * 14;
register5 := register5 + 16;
register8 := input9 * 17;
register2 := register6 + register2;
register6 := input10 * 18;
register9 := input11 * 19;
register3 := register7 + register3;
WHEN "00000100" =>
register7 := input12 * 20;
register1 := register4 + register1;
register4 := register8 + register5;
register5 := input13 * 21;
register2 := register6 + register2;
register6 := register9 + 23;
register8 := input14 * 24;
WHEN "00000101" =>
register3 := register7 + register3;
register1 := ((NOT register1) + 1) XOR register1;
register4 := register5 + register4;
register2 := ((NOT register2) + 1) XOR register2;
output1 <= register8 + register6;
WHEN "00000110" =>
output2 <= register1(0 TO 15) & register3(0 TO 15);
output3 <= register2(0 TO 15) & register4(0 TO 15);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_alap_description; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1264.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p06n01i01264ent IS
END c08s02b00x00p06n01i01264ent;
ARCHITECTURE c08s02b00x00p06n01i01264arch OF c08s02b00x00p06n01i01264ent IS
BEGIN
TESTING: PROCESS
variable B : BIT;
BEGIN
assert B;
assert FALSE
report "***FAILED TEST: c08s02b00x00p06n01i01264 - Condition must be of Boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p06n01i01264arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1264.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p06n01i01264ent IS
END c08s02b00x00p06n01i01264ent;
ARCHITECTURE c08s02b00x00p06n01i01264arch OF c08s02b00x00p06n01i01264ent IS
BEGIN
TESTING: PROCESS
variable B : BIT;
BEGIN
assert B;
assert FALSE
report "***FAILED TEST: c08s02b00x00p06n01i01264 - Condition must be of Boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p06n01i01264arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1264.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p06n01i01264ent IS
END c08s02b00x00p06n01i01264ent;
ARCHITECTURE c08s02b00x00p06n01i01264arch OF c08s02b00x00p06n01i01264ent IS
BEGIN
TESTING: PROCESS
variable B : BIT;
BEGIN
assert B;
assert FALSE
report "***FAILED TEST: c08s02b00x00p06n01i01264 - Condition must be of Boolean type"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p06n01i01264arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2864.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p03n01i02864ent IS
END c02s01b00x00p03n01i02864ent;
ARCHITECTURE c02s01b00x00p03n01i02864arch OF c02s01b00x00p03n01i02864ent IS
BEGIN
TESTING: PROCESS
function greater (i,l:time) return boolean;
function greater (i,l:time) return boolean is
begin
if i > l then
return TRUE;
else
return FALSE;
end if;
end greater;
variable result : boolean;
BEGIN
result := greater (10 ns, 5 ns);
assert NOT( result = true )
report "***PASSED TEST: c02s01b00x00p03n01i02864"
severity NOTE;
assert ( result = true )
report "***FAILED TEST: c02s01b00x00p03n01i02864 - Funcation call syntax test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p03n01i02864arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2864.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p03n01i02864ent IS
END c02s01b00x00p03n01i02864ent;
ARCHITECTURE c02s01b00x00p03n01i02864arch OF c02s01b00x00p03n01i02864ent IS
BEGIN
TESTING: PROCESS
function greater (i,l:time) return boolean;
function greater (i,l:time) return boolean is
begin
if i > l then
return TRUE;
else
return FALSE;
end if;
end greater;
variable result : boolean;
BEGIN
result := greater (10 ns, 5 ns);
assert NOT( result = true )
report "***PASSED TEST: c02s01b00x00p03n01i02864"
severity NOTE;
assert ( result = true )
report "***FAILED TEST: c02s01b00x00p03n01i02864 - Funcation call syntax test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p03n01i02864arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2864.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c02s01b00x00p03n01i02864ent IS
END c02s01b00x00p03n01i02864ent;
ARCHITECTURE c02s01b00x00p03n01i02864arch OF c02s01b00x00p03n01i02864ent IS
BEGIN
TESTING: PROCESS
function greater (i,l:time) return boolean;
function greater (i,l:time) return boolean is
begin
if i > l then
return TRUE;
else
return FALSE;
end if;
end greater;
variable result : boolean;
BEGIN
result := greater (10 ns, 5 ns);
assert NOT( result = true )
report "***PASSED TEST: c02s01b00x00p03n01i02864"
severity NOTE;
assert ( result = true )
report "***FAILED TEST: c02s01b00x00p03n01i02864 - Funcation call syntax test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s01b00x00p03n01i02864arch;
|
-- $Id: bpgenrbuslib.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2013- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Package Name: bpgenrbuslib
-- Description: Generic Board/Part components using rbus
--
-- Dependencies: -
-- Tool versions: 12.1, 13.3; ghdl 0.26-0.29
-- Revision History:
-- Date Rev Version Comment
-- 2013-01-26 476 1.0 Initial version (extracted from bpgenlib)
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.rblib.all;
package bpgenrbuslib is
component bp_swibtnled_rbus is -- swi,btn,led handling /w rbus icept
generic (
SWIDTH : positive := 4; -- SWI port width
BWIDTH : positive := 4; -- BTN port width
LWIDTH : positive := 4; -- LED port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv(SWIDTH-1 downto 0); -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv(LWIDTH-1 downto 0); -- led data
I_SWI : in slv(SWIDTH-1 downto 0); -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv(LWIDTH-1 downto 0) -- pad-o: leds
);
end component;
component sn_humanio_rbus is -- human i/o handling /w rbus intercept
generic (
BWIDTH : positive := 4; -- BTN port width
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv(BWIDTH-1 downto 0); -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv(BWIDTH-1 downto 0); -- pad-i: buttons
O_LED : out slv8; -- pad-o: leds
O_ANO_N : out slv4; -- pad-o: 7 seg disp: anodes (act.low)
O_SEG_N : out slv8 -- pad-o: 7 seg disp: segments (act.low)
);
end component;
component sn_humanio_demu_rbus is -- human i/o swi,btn,led only /w rbus
generic (
DEBOUNCE : boolean := true; -- instantiate debouncer for SWI,BTN
RB_ADDR : slv8 := slv(to_unsigned(2#10000000#,8)));
port (
CLK : in slbit; -- clock
RESET : in slbit := '0'; -- reset
CE_MSEC : in slbit; -- 1 ms clock enable
RB_MREQ : in rb_mreq_type; -- rbus: request
RB_SRES : out rb_sres_type; -- rbus: response
SWI : out slv8; -- switch settings, debounced
BTN : out slv4; -- button settings, debounced
LED : in slv8; -- led data
DSP_DAT : in slv16; -- display data
DSP_DP : in slv4; -- display decimal points
I_SWI : in slv8; -- pad-i: switches
I_BTN : in slv6; -- pad-i: buttons
O_LED : out slv8 -- pad-o: leds
);
end component;
end package bpgenrbuslib;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity fir_filter_4 is
port (
i_clk : in std_logic;
i_rstb : in std_logic;
-- coefficient
i_coeff_0 : in std_logic_vector( 7 downto 0);
i_coeff_1 : in std_logic_vector( 7 downto 0);
i_coeff_2 : in std_logic_vector( 7 downto 0);
i_coeff_3 : in std_logic_vector( 7 downto 0);
-- data input
i_data : in std_logic_vector( 7 downto 0);
-- filtered data
o_data : out std_logic_vector( 9 downto 0));
end fir_filter_4;
architecture rtl of fir_filter_4 is
type t_data_pipe is array (0 to 3) of signed(7 downto 0);
type t_coeff is array (0 to 3) of signed(7 downto 0);
type t_mult is array (0 to 3) of signed(15 downto 0);
type t_add_st0 is array (0 to 1) of signed(15+1 downto 0);
signal r_coeff : t_coeff ;
signal p_data : t_data_pipe;
signal r_mult : t_mult;
signal r_add_st0 : t_add_st0;
signal r_add_st1 : signed(15+2 downto 0);
begin
p_input : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
p_data <= (others=>(others=>'0'));
r_coeff <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
p_data <= signed(i_data)&p_data(0 to p_data'length-2);
r_coeff(0) <= signed(i_coeff_0);
r_coeff(1) <= signed(i_coeff_1);
r_coeff(2) <= signed(i_coeff_2);
r_coeff(3) <= signed(i_coeff_3);
end if;
end process p_input;
p_mult : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
r_mult <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
for k in 0 to 3 loop
r_mult(k) <= p_data(k) * r_coeff(k);
end loop;
end if;
end process p_mult;
p_add_st0 : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
r_add_st0 <= (others=>(others=>'0'));
elsif(rising_edge(i_clk)) then
for k in 0 to 1 loop
r_add_st0(k) <= resize(r_mult(2*k),17) + resize(r_mult(2*k+1),17);
end loop;
end if;
end process p_add_st0;
p_add_st1 : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
r_add_st1 <= (others=>'0');
elsif(rising_edge(i_clk)) then
r_add_st1 <= resize(r_add_st0(0),18) + resize(r_add_st0(1),18);
end if;
end process p_add_st1;
p_output : process (i_rstb,i_clk)
begin
if(i_rstb='0') then
o_data <= (others=>'0');
elsif(rising_edge(i_clk)) then
o_data <= std_logic_vector(r_add_st1(17 downto 8));
end if;
end process p_output;
end rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:04:17 07/16/2014
-- Design Name:
-- Module Name: state_reg - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.types.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity state_reg is
port (
clk : in std_logic;
reset : in std_logic;
D : in state;
Q : out state
);
end state_reg;
architecture Behavioral of state_reg is
begin
reg : process (reset, clk, D)
begin
if reset = '1' then
Q <= (others => '0');
elsif rising_edge(clk) then
Q <= D;
end if;
end process reg;
end Behavioral;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY part5 IS
PORT ( dE1 : IN STD_LOGIC_VECTOR(5 DOWNTO 0); -- chars to display
dE1SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- select one of 'dEl', 'Eld' or 'ldE'
CYCDISP : IN STD_LOGIC_VECTOR(1 DOWNTO 0); -- cycle through three displays
HEX0 : OUT STD_LOGIC_VECTOR(0 TO 6)); -- light segments during cycle n
END part5;
ARCHITECTURE Behavior OF part5 IS
COMPONENT mux_2bit_3to1
PORT ( S, U, V, W : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
END COMPONENT;
COMPONENT char_7seg
PORT ( C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
Display : OUT STD_LOGIC_VECTOR(0 TO 6));
END COMPONENT;
SIGNAL M : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL N : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL O : STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL P : STD_LOGIC_VECTOR(1 DOWNTO 0);
BEGIN
M0: mux_2bit_3to1 PORT MAP (dE1SEL, dE1(5 DOWNTO 4), dE1(3 DOWNTO 2), dE1(1 DOWNTO 0), M);
M1: mux_2bit_3to1 PORT MAP (dE1SEL, dE1(3 DOWNTO 2), dE1(1 DOWNTO 0), dE1(5 DOWNTO 4), N);
M2: mux_2bit_3to1 PORT MAP (dE1SEL, dE1(1 DOWNTO 0), dE1(5 DOWNTO 4), dE1(3 DOWNTO 2), O);
M3: mux_2bit_3to1 PORT MAP (CYCDISP, M, N, O, P);
H2: char_7seg PORT MAP (P, HEX0);
END Behavior; |
---------------------------------------------------------------------------
-- (c) 2013 mark watson
-- I am happy for anyone to use this for non-commercial use.
-- If my vhdl files are used commercially or otherwise sold,
-- please contact me for explicit permission at scrameta (gmail).
-- This applies for source and binary form and derived works.
---------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.all;
use ieee.numeric_std.all;
ENTITY gtia_palette IS
PORT
(
ATARI_COLOUR : IN STD_LOGIC_VECTOR(7 downto 0);
R_next : OUT STD_LOGIC_VECTOR(7 downto 0);
G_next : OUT STD_LOGIC_VECTOR(7 downto 0);
B_next : OUT STD_LOGIC_VECTOR(7 downto 0)
);
END gtia_palette;
ARCHITECTURE altirra OF gtia_palette IS
begin
process(atari_colour)
begin
case atari_colour is
when X"00" =>
R_next <= X"00";
G_next <= X"00";
B_next <= X"00";
when X"01" =>
R_next <= X"11";
G_next <= X"11";
B_next <= X"11";
when X"02" =>
R_next <= X"22";
G_next <= X"22";
B_next <= X"22";
when X"03" =>
R_next <= X"33";
G_next <= X"33";
B_next <= X"33";
when X"04" =>
R_next <= X"44";
G_next <= X"44";
B_next <= X"44";
when X"05" =>
R_next <= X"55";
G_next <= X"55";
B_next <= X"55";
when X"06" =>
R_next <= X"66";
G_next <= X"66";
B_next <= X"66";
when X"07" =>
R_next <= X"77";
G_next <= X"77";
B_next <= X"77";
when X"08" =>
R_next <= X"88";
G_next <= X"88";
B_next <= X"88";
when X"09" =>
R_next <= X"99";
G_next <= X"99";
B_next <= X"99";
when X"0a" =>
R_next <= X"aa";
G_next <= X"aa";
B_next <= X"aa";
when X"0b" =>
R_next <= X"bb";
G_next <= X"bb";
B_next <= X"bb";
when X"0c" =>
R_next <= X"cc";
G_next <= X"cc";
B_next <= X"cc";
when X"0d" =>
R_next <= X"dd";
G_next <= X"dd";
B_next <= X"dd";
when X"0e" =>
R_next <= X"ee";
G_next <= X"ee";
B_next <= X"ee";
when X"0f" =>
R_next <= X"ff";
G_next <= X"ff";
B_next <= X"ff";
when X"10" =>
R_next <= X"3f";
G_next <= X"00";
B_next <= X"00";
when X"11" =>
R_next <= X"50";
G_next <= X"05";
B_next <= X"00";
when X"12" =>
R_next <= X"61";
G_next <= X"16";
B_next <= X"00";
when X"13" =>
R_next <= X"72";
G_next <= X"27";
B_next <= X"00";
when X"14" =>
R_next <= X"83";
G_next <= X"38";
B_next <= X"00";
when X"15" =>
R_next <= X"94";
G_next <= X"49";
B_next <= X"00";
when X"16" =>
R_next <= X"a5";
G_next <= X"5a";
B_next <= X"01";
when X"17" =>
R_next <= X"b6";
G_next <= X"6b";
B_next <= X"12";
when X"18" =>
R_next <= X"c7";
G_next <= X"7c";
B_next <= X"23";
when X"19" =>
R_next <= X"d8";
G_next <= X"8d";
B_next <= X"34";
when X"1a" =>
R_next <= X"e9";
G_next <= X"9e";
B_next <= X"45";
when X"1b" =>
R_next <= X"fa";
G_next <= X"af";
B_next <= X"56";
when X"1c" =>
R_next <= X"ff";
G_next <= X"c0";
B_next <= X"67";
when X"1d" =>
R_next <= X"ff";
G_next <= X"d1";
B_next <= X"78";
when X"1e" =>
R_next <= X"ff";
G_next <= X"e2";
B_next <= X"89";
when X"1f" =>
R_next <= X"ff";
G_next <= X"f3";
B_next <= X"9a";
when X"20" =>
R_next <= X"50";
G_next <= X"00";
B_next <= X"00";
when X"21" =>
R_next <= X"61";
G_next <= X"00";
B_next <= X"00";
when X"22" =>
R_next <= X"72";
G_next <= X"03";
B_next <= X"00";
when X"23" =>
R_next <= X"83";
G_next <= X"14";
B_next <= X"03";
when X"24" =>
R_next <= X"94";
G_next <= X"25";
B_next <= X"14";
when X"25" =>
R_next <= X"a5";
G_next <= X"36";
B_next <= X"25";
when X"26" =>
R_next <= X"b6";
G_next <= X"47";
B_next <= X"36";
when X"27" =>
R_next <= X"c7";
G_next <= X"58";
B_next <= X"47";
when X"28" =>
R_next <= X"d8";
G_next <= X"69";
B_next <= X"58";
when X"29" =>
R_next <= X"e9";
G_next <= X"7a";
B_next <= X"69";
when X"2a" =>
R_next <= X"fa";
G_next <= X"8b";
B_next <= X"7a";
when X"2b" =>
R_next <= X"ff";
G_next <= X"9c";
B_next <= X"8b";
when X"2c" =>
R_next <= X"ff";
G_next <= X"ad";
B_next <= X"9c";
when X"2d" =>
R_next <= X"ff";
G_next <= X"be";
B_next <= X"ad";
when X"2e" =>
R_next <= X"ff";
G_next <= X"cf";
B_next <= X"be";
when X"2f" =>
R_next <= X"ff";
G_next <= X"e0";
B_next <= X"cf";
when X"30" =>
R_next <= X"54";
G_next <= X"00";
B_next <= X"03";
when X"31" =>
R_next <= X"65";
G_next <= X"00";
B_next <= X"14";
when X"32" =>
R_next <= X"76";
G_next <= X"00";
B_next <= X"25";
when X"33" =>
R_next <= X"87";
G_next <= X"08";
B_next <= X"36";
when X"34" =>
R_next <= X"98";
G_next <= X"19";
B_next <= X"47";
when X"35" =>
R_next <= X"a9";
G_next <= X"2a";
B_next <= X"58";
when X"36" =>
R_next <= X"ba";
G_next <= X"3b";
B_next <= X"69";
when X"37" =>
R_next <= X"cb";
G_next <= X"4c";
B_next <= X"7a";
when X"38" =>
R_next <= X"dc";
G_next <= X"5d";
B_next <= X"8b";
when X"39" =>
R_next <= X"ed";
G_next <= X"6e";
B_next <= X"9c";
when X"3a" =>
R_next <= X"fe";
G_next <= X"7f";
B_next <= X"ad";
when X"3b" =>
R_next <= X"ff";
G_next <= X"90";
B_next <= X"be";
when X"3c" =>
R_next <= X"ff";
G_next <= X"a1";
B_next <= X"cf";
when X"3d" =>
R_next <= X"ff";
G_next <= X"b2";
B_next <= X"e0";
when X"3e" =>
R_next <= X"ff";
G_next <= X"c3";
B_next <= X"f1";
when X"3f" =>
R_next <= X"ff";
G_next <= X"d4";
B_next <= X"ff";
when X"40" =>
R_next <= X"4f";
G_next <= X"00";
B_next <= X"35";
when X"41" =>
R_next <= X"60";
G_next <= X"00";
B_next <= X"46";
when X"42" =>
R_next <= X"71";
G_next <= X"00";
B_next <= X"57";
when X"43" =>
R_next <= X"82";
G_next <= X"01";
B_next <= X"68";
when X"44" =>
R_next <= X"93";
G_next <= X"12";
B_next <= X"79";
when X"45" =>
R_next <= X"a4";
G_next <= X"23";
B_next <= X"8a";
when X"46" =>
R_next <= X"b5";
G_next <= X"34";
B_next <= X"9b";
when X"47" =>
R_next <= X"c6";
G_next <= X"45";
B_next <= X"ac";
when X"48" =>
R_next <= X"d7";
G_next <= X"56";
B_next <= X"bd";
when X"49" =>
R_next <= X"e8";
G_next <= X"67";
B_next <= X"ce";
when X"4a" =>
R_next <= X"f9";
G_next <= X"78";
B_next <= X"df";
when X"4b" =>
R_next <= X"ff";
G_next <= X"89";
B_next <= X"f0";
when X"4c" =>
R_next <= X"ff";
G_next <= X"9a";
B_next <= X"ff";
when X"4d" =>
R_next <= X"ff";
G_next <= X"ab";
B_next <= X"ff";
when X"4e" =>
R_next <= X"ff";
G_next <= X"bc";
B_next <= X"ff";
when X"4f" =>
R_next <= X"ff";
G_next <= X"cd";
B_next <= X"ff";
when X"50" =>
R_next <= X"3d";
G_next <= X"00";
B_next <= X"68";
when X"51" =>
R_next <= X"4e";
G_next <= X"00";
B_next <= X"79";
when X"52" =>
R_next <= X"5f";
G_next <= X"00";
B_next <= X"8a";
when X"53" =>
R_next <= X"70";
G_next <= X"00";
B_next <= X"9b";
when X"54" =>
R_next <= X"81";
G_next <= X"11";
B_next <= X"ac";
when X"55" =>
R_next <= X"92";
G_next <= X"22";
B_next <= X"bd";
when X"56" =>
R_next <= X"a3";
G_next <= X"33";
B_next <= X"ce";
when X"57" =>
R_next <= X"b4";
G_next <= X"44";
B_next <= X"df";
when X"58" =>
R_next <= X"c5";
G_next <= X"55";
B_next <= X"f0";
when X"59" =>
R_next <= X"d6";
G_next <= X"66";
B_next <= X"ff";
when X"5a" =>
R_next <= X"e7";
G_next <= X"77";
B_next <= X"ff";
when X"5b" =>
R_next <= X"f8";
G_next <= X"88";
B_next <= X"ff";
when X"5c" =>
R_next <= X"ff";
G_next <= X"99";
B_next <= X"ff";
when X"5d" =>
R_next <= X"ff";
G_next <= X"aa";
B_next <= X"ff";
when X"5e" =>
R_next <= X"ff";
G_next <= X"bb";
B_next <= X"ff";
when X"5f" =>
R_next <= X"ff";
G_next <= X"cc";
B_next <= X"ff";
when X"60" =>
R_next <= X"20";
G_next <= X"00";
B_next <= X"8b";
when X"61" =>
R_next <= X"31";
G_next <= X"00";
B_next <= X"9c";
when X"62" =>
R_next <= X"42";
G_next <= X"00";
B_next <= X"ad";
when X"63" =>
R_next <= X"53";
G_next <= X"08";
B_next <= X"be";
when X"64" =>
R_next <= X"64";
G_next <= X"19";
B_next <= X"cf";
when X"65" =>
R_next <= X"75";
G_next <= X"2a";
B_next <= X"e0";
when X"66" =>
R_next <= X"86";
G_next <= X"3b";
B_next <= X"f1";
when X"67" =>
R_next <= X"97";
G_next <= X"4c";
B_next <= X"ff";
when X"68" =>
R_next <= X"a8";
G_next <= X"5d";
B_next <= X"ff";
when X"69" =>
R_next <= X"b9";
G_next <= X"6e";
B_next <= X"ff";
when X"6a" =>
R_next <= X"ca";
G_next <= X"7f";
B_next <= X"ff";
when X"6b" =>
R_next <= X"db";
G_next <= X"90";
B_next <= X"ff";
when X"6c" =>
R_next <= X"ec";
G_next <= X"a1";
B_next <= X"ff";
when X"6d" =>
R_next <= X"fd";
G_next <= X"b2";
B_next <= X"ff";
when X"6e" =>
R_next <= X"ff";
G_next <= X"c3";
B_next <= X"ff";
when X"6f" =>
R_next <= X"ff";
G_next <= X"d4";
B_next <= X"ff";
when X"70" =>
R_next <= X"00";
G_next <= X"00";
B_next <= X"89";
when X"71" =>
R_next <= X"00";
G_next <= X"08";
B_next <= X"9a";
when X"72" =>
R_next <= X"00";
G_next <= X"19";
B_next <= X"ab";
when X"73" =>
R_next <= X"10";
G_next <= X"2a";
B_next <= X"bc";
when X"74" =>
R_next <= X"21";
G_next <= X"3b";
B_next <= X"cd";
when X"75" =>
R_next <= X"32";
G_next <= X"4c";
B_next <= X"de";
when X"76" =>
R_next <= X"43";
G_next <= X"5d";
B_next <= X"ef";
when X"77" =>
R_next <= X"54";
G_next <= X"6e";
B_next <= X"ff";
when X"78" =>
R_next <= X"65";
G_next <= X"7f";
B_next <= X"ff";
when X"79" =>
R_next <= X"76";
G_next <= X"90";
B_next <= X"ff";
when X"7a" =>
R_next <= X"87";
G_next <= X"a1";
B_next <= X"ff";
when X"7b" =>
R_next <= X"98";
G_next <= X"b2";
B_next <= X"ff";
when X"7c" =>
R_next <= X"a9";
G_next <= X"c3";
B_next <= X"ff";
when X"7d" =>
R_next <= X"ba";
G_next <= X"d4";
B_next <= X"ff";
when X"7e" =>
R_next <= X"cb";
G_next <= X"e5";
B_next <= X"ff";
when X"7f" =>
R_next <= X"dc";
G_next <= X"f6";
B_next <= X"ff";
when X"80" =>
R_next <= X"00";
G_next <= X"0c";
B_next <= X"65";
when X"81" =>
R_next <= X"00";
G_next <= X"1d";
B_next <= X"76";
when X"82" =>
R_next <= X"00";
G_next <= X"2e";
B_next <= X"87";
when X"83" =>
R_next <= X"00";
G_next <= X"3f";
B_next <= X"98";
when X"84" =>
R_next <= X"05";
G_next <= X"50";
B_next <= X"a9";
when X"85" =>
R_next <= X"16";
G_next <= X"61";
B_next <= X"ba";
when X"86" =>
R_next <= X"27";
G_next <= X"72";
B_next <= X"cb";
when X"87" =>
R_next <= X"38";
G_next <= X"83";
B_next <= X"dc";
when X"88" =>
R_next <= X"49";
G_next <= X"94";
B_next <= X"ed";
when X"89" =>
R_next <= X"5a";
G_next <= X"a5";
B_next <= X"fe";
when X"8a" =>
R_next <= X"6b";
G_next <= X"b6";
B_next <= X"ff";
when X"8b" =>
R_next <= X"7c";
G_next <= X"c7";
B_next <= X"ff";
when X"8c" =>
R_next <= X"8d";
G_next <= X"d8";
B_next <= X"ff";
when X"8d" =>
R_next <= X"9e";
G_next <= X"e9";
B_next <= X"ff";
when X"8e" =>
R_next <= X"af";
G_next <= X"fa";
B_next <= X"ff";
when X"8f" =>
R_next <= X"c0";
G_next <= X"ff";
B_next <= X"ff";
when X"90" =>
R_next <= X"00";
G_next <= X"1f";
B_next <= X"30";
when X"91" =>
R_next <= X"00";
G_next <= X"30";
B_next <= X"41";
when X"92" =>
R_next <= X"00";
G_next <= X"41";
B_next <= X"52";
when X"93" =>
R_next <= X"00";
G_next <= X"52";
B_next <= X"63";
when X"94" =>
R_next <= X"00";
G_next <= X"63";
B_next <= X"74";
when X"95" =>
R_next <= X"05";
G_next <= X"74";
B_next <= X"85";
when X"96" =>
R_next <= X"16";
G_next <= X"85";
B_next <= X"96";
when X"97" =>
R_next <= X"27";
G_next <= X"96";
B_next <= X"a7";
when X"98" =>
R_next <= X"38";
G_next <= X"a7";
B_next <= X"b8";
when X"99" =>
R_next <= X"49";
G_next <= X"b8";
B_next <= X"c9";
when X"9a" =>
R_next <= X"5a";
G_next <= X"c9";
B_next <= X"da";
when X"9b" =>
R_next <= X"6b";
G_next <= X"da";
B_next <= X"eb";
when X"9c" =>
R_next <= X"7c";
G_next <= X"eb";
B_next <= X"fc";
when X"9d" =>
R_next <= X"8d";
G_next <= X"fc";
B_next <= X"ff";
when X"9e" =>
R_next <= X"9e";
G_next <= X"ff";
B_next <= X"ff";
when X"9f" =>
R_next <= X"af";
G_next <= X"ff";
B_next <= X"ff";
when X"a0" =>
R_next <= X"00";
G_next <= X"2b";
B_next <= X"00";
when X"a1" =>
R_next <= X"00";
G_next <= X"3c";
B_next <= X"0e";
when X"a2" =>
R_next <= X"00";
G_next <= X"4d";
B_next <= X"1f";
when X"a3" =>
R_next <= X"00";
G_next <= X"5e";
B_next <= X"30";
when X"a4" =>
R_next <= X"00";
G_next <= X"6f";
B_next <= X"41";
when X"a5" =>
R_next <= X"01";
G_next <= X"80";
B_next <= X"52";
when X"a6" =>
R_next <= X"12";
G_next <= X"91";
B_next <= X"63";
when X"a7" =>
R_next <= X"23";
G_next <= X"a2";
B_next <= X"74";
when X"a8" =>
R_next <= X"34";
G_next <= X"b3";
B_next <= X"85";
when X"a9" =>
R_next <= X"45";
G_next <= X"c4";
B_next <= X"96";
when X"aa" =>
R_next <= X"56";
G_next <= X"d5";
B_next <= X"a7";
when X"ab" =>
R_next <= X"67";
G_next <= X"e6";
B_next <= X"b8";
when X"ac" =>
R_next <= X"78";
G_next <= X"f7";
B_next <= X"c9";
when X"ad" =>
R_next <= X"89";
G_next <= X"ff";
B_next <= X"da";
when X"ae" =>
R_next <= X"9a";
G_next <= X"ff";
B_next <= X"eb";
when X"af" =>
R_next <= X"ab";
G_next <= X"ff";
B_next <= X"fc";
when X"b0" =>
R_next <= X"00";
G_next <= X"33";
B_next <= X"00";
when X"b1" =>
R_next <= X"00";
G_next <= X"44";
B_next <= X"00";
when X"b2" =>
R_next <= X"00";
G_next <= X"55";
B_next <= X"00";
when X"b3" =>
R_next <= X"00";
G_next <= X"66";
B_next <= X"00";
when X"b4" =>
R_next <= X"07";
G_next <= X"77";
B_next <= X"00";
when X"b5" =>
R_next <= X"18";
G_next <= X"88";
B_next <= X"00";
when X"b6" =>
R_next <= X"29";
G_next <= X"99";
B_next <= X"00";
when X"b7" =>
R_next <= X"3a";
G_next <= X"aa";
B_next <= X"0f";
when X"b8" =>
R_next <= X"4b";
G_next <= X"bb";
B_next <= X"20";
when X"b9" =>
R_next <= X"5c";
G_next <= X"cc";
B_next <= X"31";
when X"ba" =>
R_next <= X"6d";
G_next <= X"dd";
B_next <= X"42";
when X"bb" =>
R_next <= X"7e";
G_next <= X"ee";
B_next <= X"53";
when X"bc" =>
R_next <= X"8f";
G_next <= X"ff";
B_next <= X"64";
when X"bd" =>
R_next <= X"a0";
G_next <= X"ff";
B_next <= X"75";
when X"be" =>
R_next <= X"b1";
G_next <= X"ff";
B_next <= X"86";
when X"bf" =>
R_next <= X"c2";
G_next <= X"ff";
B_next <= X"97";
when X"c0" =>
R_next <= X"00";
G_next <= X"2b";
B_next <= X"00";
when X"c1" =>
R_next <= X"00";
G_next <= X"3c";
B_next <= X"00";
when X"c2" =>
R_next <= X"02";
G_next <= X"4d";
B_next <= X"00";
when X"c3" =>
R_next <= X"13";
G_next <= X"5e";
B_next <= X"00";
when X"c4" =>
R_next <= X"24";
G_next <= X"6f";
B_next <= X"00";
when X"c5" =>
R_next <= X"35";
G_next <= X"80";
B_next <= X"00";
when X"c6" =>
R_next <= X"46";
G_next <= X"91";
B_next <= X"00";
when X"c7" =>
R_next <= X"57";
G_next <= X"a2";
B_next <= X"00";
when X"c8" =>
R_next <= X"68";
G_next <= X"b3";
B_next <= X"00";
when X"c9" =>
R_next <= X"79";
G_next <= X"c4";
B_next <= X"0e";
when X"ca" =>
R_next <= X"8a";
G_next <= X"d5";
B_next <= X"1f";
when X"cb" =>
R_next <= X"9b";
G_next <= X"e6";
B_next <= X"30";
when X"cc" =>
R_next <= X"ac";
G_next <= X"f7";
B_next <= X"41";
when X"cd" =>
R_next <= X"bd";
G_next <= X"ff";
B_next <= X"52";
when X"ce" =>
R_next <= X"ce";
G_next <= X"ff";
B_next <= X"63";
when X"cf" =>
R_next <= X"df";
G_next <= X"ff";
B_next <= X"74";
when X"d0" =>
R_next <= X"01";
G_next <= X"1c";
B_next <= X"00";
when X"d1" =>
R_next <= X"12";
G_next <= X"2d";
B_next <= X"00";
when X"d2" =>
R_next <= X"23";
G_next <= X"3e";
B_next <= X"00";
when X"d3" =>
R_next <= X"34";
G_next <= X"4f";
B_next <= X"00";
when X"d4" =>
R_next <= X"45";
G_next <= X"60";
B_next <= X"00";
when X"d5" =>
R_next <= X"56";
G_next <= X"71";
B_next <= X"00";
when X"d6" =>
R_next <= X"67";
G_next <= X"82";
B_next <= X"00";
when X"d7" =>
R_next <= X"78";
G_next <= X"93";
B_next <= X"00";
when X"d8" =>
R_next <= X"89";
G_next <= X"a4";
B_next <= X"00";
when X"d9" =>
R_next <= X"9a";
G_next <= X"b5";
B_next <= X"03";
when X"da" =>
R_next <= X"ab";
G_next <= X"c6";
B_next <= X"14";
when X"db" =>
R_next <= X"bc";
G_next <= X"d7";
B_next <= X"25";
when X"dc" =>
R_next <= X"cd";
G_next <= X"e8";
B_next <= X"36";
when X"dd" =>
R_next <= X"de";
G_next <= X"f9";
B_next <= X"47";
when X"de" =>
R_next <= X"ef";
G_next <= X"ff";
B_next <= X"58";
when X"df" =>
R_next <= X"ff";
G_next <= X"ff";
B_next <= X"69";
when X"e0" =>
R_next <= X"23";
G_next <= X"09";
B_next <= X"00";
when X"e1" =>
R_next <= X"34";
G_next <= X"1a";
B_next <= X"00";
when X"e2" =>
R_next <= X"45";
G_next <= X"2b";
B_next <= X"00";
when X"e3" =>
R_next <= X"56";
G_next <= X"3c";
B_next <= X"00";
when X"e4" =>
R_next <= X"67";
G_next <= X"4d";
B_next <= X"00";
when X"e5" =>
R_next <= X"78";
G_next <= X"5e";
B_next <= X"00";
when X"e6" =>
R_next <= X"89";
G_next <= X"6f";
B_next <= X"00";
when X"e7" =>
R_next <= X"9a";
G_next <= X"80";
B_next <= X"00";
when X"e8" =>
R_next <= X"ab";
G_next <= X"91";
B_next <= X"00";
when X"e9" =>
R_next <= X"bc";
G_next <= X"a2";
B_next <= X"10";
when X"ea" =>
R_next <= X"cd";
G_next <= X"b3";
B_next <= X"21";
when X"eb" =>
R_next <= X"de";
G_next <= X"c4";
B_next <= X"32";
when X"ec" =>
R_next <= X"ef";
G_next <= X"d5";
B_next <= X"43";
when X"ed" =>
R_next <= X"ff";
G_next <= X"e6";
B_next <= X"54";
when X"ee" =>
R_next <= X"ff";
G_next <= X"f7";
B_next <= X"65";
when X"ef" =>
R_next <= X"ff";
G_next <= X"ff";
B_next <= X"76";
when X"f0" =>
R_next <= X"3f";
G_next <= X"00";
B_next <= X"00";
when X"f1" =>
R_next <= X"50";
G_next <= X"05";
B_next <= X"00";
when X"f2" =>
R_next <= X"61";
G_next <= X"16";
B_next <= X"00";
when X"f3" =>
R_next <= X"72";
G_next <= X"27";
B_next <= X"00";
when X"f4" =>
R_next <= X"83";
G_next <= X"38";
B_next <= X"00";
when X"f5" =>
R_next <= X"94";
G_next <= X"49";
B_next <= X"00";
when X"f6" =>
R_next <= X"a5";
G_next <= X"5a";
B_next <= X"01";
when X"f7" =>
R_next <= X"b6";
G_next <= X"6b";
B_next <= X"12";
when X"f8" =>
R_next <= X"c7";
G_next <= X"7c";
B_next <= X"23";
when X"f9" =>
R_next <= X"d8";
G_next <= X"8d";
B_next <= X"34";
when X"fa" =>
R_next <= X"e9";
G_next <= X"9e";
B_next <= X"45";
when X"fb" =>
R_next <= X"fa";
G_next <= X"af";
B_next <= X"56";
when X"fc" =>
R_next <= X"ff";
G_next <= X"c0";
B_next <= X"67";
when X"fd" =>
R_next <= X"ff";
G_next <= X"d1";
B_next <= X"78";
when X"fe" =>
R_next <= X"ff";
G_next <= X"e2";
B_next <= X"89";
when X"ff" =>
R_next <= X"ff";
G_next <= X"f3";
B_next <= X"9a";
when others =>
-- nop
end case;
end process;
end altirra;
ARCHITECTURE laoo OF gtia_palette IS
begin
process(atari_colour)
begin
case atari_colour is
when X"00" =>
R_next <= X"00";
G_next <= X"00";
B_next <= X"00";
when X"01" =>
R_next <= X"0e";
G_next <= X"0d";
B_next <= X"0e";
when X"02" =>
R_next <= X"1d";
G_next <= X"1d";
B_next <= X"1d";
when X"03" =>
R_next <= X"2e";
G_next <= X"2d";
B_next <= X"2e";
when X"04" =>
R_next <= X"3e";
G_next <= X"3d";
B_next <= X"3e";
when X"05" =>
R_next <= X"4f";
G_next <= X"4e";
B_next <= X"4f";
when X"06" =>
R_next <= X"5f";
G_next <= X"5e";
B_next <= X"5f";
when X"07" =>
R_next <= X"70";
G_next <= X"6f";
B_next <= X"6f";
when X"08" =>
R_next <= X"7a";
G_next <= X"7a";
B_next <= X"79";
when X"09" =>
R_next <= X"8b";
G_next <= X"8a";
B_next <= X"8b";
when X"0a" =>
R_next <= X"9c";
G_next <= X"9b";
B_next <= X"9b";
when X"0b" =>
R_next <= X"ad";
G_next <= X"ac";
B_next <= X"ac";
when X"0c" =>
R_next <= X"bc";
G_next <= X"bb";
B_next <= X"bb";
when X"0d" =>
R_next <= X"cd";
G_next <= X"cc";
B_next <= X"cd";
when X"0e" =>
R_next <= X"dc";
G_next <= X"db";
B_next <= X"dc";
when X"0f" =>
R_next <= X"ec";
G_next <= X"ec";
B_next <= X"ec";
when X"10" =>
R_next <= X"35";
G_next <= X"00";
B_next <= X"00";
when X"11" =>
R_next <= X"40";
G_next <= X"05";
B_next <= X"00";
when X"12" =>
R_next <= X"4f";
G_next <= X"14";
B_next <= X"00";
when X"13" =>
R_next <= X"5f";
G_next <= X"25";
B_next <= X"00";
when X"14" =>
R_next <= X"6e";
G_next <= X"34";
B_next <= X"00";
when X"15" =>
R_next <= X"7f";
G_next <= X"45";
B_next <= X"03";
when X"16" =>
R_next <= X"8e";
G_next <= X"55";
B_next <= X"13";
when X"17" =>
R_next <= X"9f";
G_next <= X"66";
B_next <= X"23";
when X"18" =>
R_next <= X"a9";
G_next <= X"71";
B_next <= X"2d";
when X"19" =>
R_next <= X"ba";
G_next <= X"82";
B_next <= X"40";
when X"1a" =>
R_next <= X"ca";
G_next <= X"92";
B_next <= X"50";
when X"1b" =>
R_next <= X"db";
G_next <= X"a3";
B_next <= X"61";
when X"1c" =>
R_next <= X"ea";
G_next <= X"b2";
B_next <= X"70";
when X"1d" =>
R_next <= X"fa";
G_next <= X"c3";
B_next <= X"82";
when X"1e" =>
R_next <= X"fe";
G_next <= X"d2";
B_next <= X"91";
when X"1f" =>
R_next <= X"ff";
G_next <= X"e3";
B_next <= X"a1";
when X"20" =>
R_next <= X"3f";
G_next <= X"00";
B_next <= X"00";
when X"21" =>
R_next <= X"4b";
G_next <= X"00";
B_next <= X"00";
when X"22" =>
R_next <= X"59";
G_next <= X"09";
B_next <= X"00";
when X"23" =>
R_next <= X"69";
G_next <= X"19";
B_next <= X"03";
when X"24" =>
R_next <= X"78";
G_next <= X"29";
B_next <= X"12";
when X"25" =>
R_next <= X"88";
G_next <= X"3a";
B_next <= X"23";
when X"26" =>
R_next <= X"98";
G_next <= X"4a";
B_next <= X"34";
when X"27" =>
R_next <= X"a9";
G_next <= X"5b";
B_next <= X"45";
when X"28" =>
R_next <= X"b3";
G_next <= X"65";
B_next <= X"4f";
when X"29" =>
R_next <= X"c4";
G_next <= X"76";
B_next <= X"61";
when X"2a" =>
R_next <= X"d4";
G_next <= X"87";
B_next <= X"72";
when X"2b" =>
R_next <= X"e5";
G_next <= X"98";
B_next <= X"83";
when X"2c" =>
R_next <= X"f4";
G_next <= X"a7";
B_next <= X"92";
when X"2d" =>
R_next <= X"fd";
G_next <= X"b8";
B_next <= X"a3";
when X"2e" =>
R_next <= X"ff";
G_next <= X"c7";
B_next <= X"b3";
when X"2f" =>
R_next <= X"ff";
G_next <= X"d7";
B_next <= X"c2";
when X"30" =>
R_next <= X"3d";
G_next <= X"00";
B_next <= X"00";
when X"31" =>
R_next <= X"49";
G_next <= X"00";
B_next <= X"00";
when X"32" =>
R_next <= X"57";
G_next <= X"05";
B_next <= X"0b";
when X"33" =>
R_next <= X"68";
G_next <= X"15";
B_next <= X"1b";
when X"34" =>
R_next <= X"77";
G_next <= X"25";
B_next <= X"2a";
when X"35" =>
R_next <= X"88";
G_next <= X"36";
B_next <= X"3c";
when X"36" =>
R_next <= X"98";
G_next <= X"46";
B_next <= X"4c";
when X"37" =>
R_next <= X"a8";
G_next <= X"57";
B_next <= X"5d";
when X"38" =>
R_next <= X"b2";
G_next <= X"61";
B_next <= X"67";
when X"39" =>
R_next <= X"c3";
G_next <= X"72";
B_next <= X"79";
when X"3a" =>
R_next <= X"d3";
G_next <= X"83";
B_next <= X"89";
when X"3b" =>
R_next <= X"e4";
G_next <= X"94";
B_next <= X"9a";
when X"3c" =>
R_next <= X"f3";
G_next <= X"a3";
B_next <= X"a9";
when X"3d" =>
R_next <= X"fd";
G_next <= X"b4";
B_next <= X"ba";
when X"3e" =>
R_next <= X"ff";
G_next <= X"c4";
B_next <= X"ca";
when X"3f" =>
R_next <= X"ff";
G_next <= X"d4";
B_next <= X"d9";
when X"40" =>
R_next <= X"38";
G_next <= X"00";
B_next <= X"27";
when X"41" =>
R_next <= X"42";
G_next <= X"00";
B_next <= X"32";
when X"42" =>
R_next <= X"51";
G_next <= X"01";
B_next <= X"40";
when X"43" =>
R_next <= X"61";
G_next <= X"0e";
B_next <= X"50";
when X"44" =>
R_next <= X"70";
G_next <= X"1e";
B_next <= X"5f";
when X"45" =>
R_next <= X"81";
G_next <= X"2f";
B_next <= X"70";
when X"46" =>
R_next <= X"90";
G_next <= X"3f";
B_next <= X"81";
when X"47" =>
R_next <= X"a0";
G_next <= X"51";
B_next <= X"90";
when X"48" =>
R_next <= X"ab";
G_next <= X"5b";
B_next <= X"9a";
when X"49" =>
R_next <= X"bc";
G_next <= X"6c";
B_next <= X"ac";
when X"4a" =>
R_next <= X"cc";
G_next <= X"7c";
B_next <= X"bc";
when X"4b" =>
R_next <= X"dc";
G_next <= X"8d";
B_next <= X"cd";
when X"4c" =>
R_next <= X"ec";
G_next <= X"9d";
B_next <= X"dc";
when X"4d" =>
R_next <= X"fa";
G_next <= X"ae";
B_next <= X"ed";
when X"4e" =>
R_next <= X"fe";
G_next <= X"bd";
B_next <= X"fa";
when X"4f" =>
R_next <= X"ff";
G_next <= X"cd";
B_next <= X"fe";
when X"50" =>
R_next <= X"2c";
G_next <= X"00";
B_next <= X"46";
when X"51" =>
R_next <= X"37";
G_next <= X"00";
B_next <= X"50";
when X"52" =>
R_next <= X"46";
G_next <= X"01";
B_next <= X"5f";
when X"53" =>
R_next <= X"55";
G_next <= X"0e";
B_next <= X"6e";
when X"54" =>
R_next <= X"65";
G_next <= X"1e";
B_next <= X"7d";
when X"55" =>
R_next <= X"75";
G_next <= X"2f";
B_next <= X"8e";
when X"56" =>
R_next <= X"85";
G_next <= X"3f";
B_next <= X"9f";
when X"57" =>
R_next <= X"95";
G_next <= X"50";
B_next <= X"ae";
when X"58" =>
R_next <= X"a0";
G_next <= X"5b";
B_next <= X"b8";
when X"59" =>
R_next <= X"b1";
G_next <= X"6c";
B_next <= X"ca";
when X"5a" =>
R_next <= X"c1";
G_next <= X"7c";
B_next <= X"da";
when X"5b" =>
R_next <= X"d2";
G_next <= X"8d";
B_next <= X"eb";
when X"5c" =>
R_next <= X"e1";
G_next <= X"9d";
B_next <= X"f8";
when X"5d" =>
R_next <= X"f2";
G_next <= X"ae";
B_next <= X"fe";
when X"5e" =>
R_next <= X"fc";
G_next <= X"bd";
B_next <= X"ff";
when X"5f" =>
R_next <= X"fe";
G_next <= X"cd";
B_next <= X"ff";
when X"60" =>
R_next <= X"19";
G_next <= X"00";
B_next <= X"5e";
when X"61" =>
R_next <= X"24";
G_next <= X"00";
B_next <= X"67";
when X"62" =>
R_next <= X"34";
G_next <= X"03";
B_next <= X"76";
when X"63" =>
R_next <= X"44";
G_next <= X"13";
B_next <= X"85";
when X"64" =>
R_next <= X"53";
G_next <= X"22";
B_next <= X"94";
when X"65" =>
R_next <= X"64";
G_next <= X"33";
B_next <= X"a5";
when X"66" =>
R_next <= X"74";
G_next <= X"43";
B_next <= X"b5";
when X"67" =>
R_next <= X"85";
G_next <= X"55";
B_next <= X"c4";
when X"68" =>
R_next <= X"8f";
G_next <= X"5f";
B_next <= X"ce";
when X"69" =>
R_next <= X"a0";
G_next <= X"70";
B_next <= X"e0";
when X"6a" =>
R_next <= X"b0";
G_next <= X"81";
B_next <= X"f0";
when X"6b" =>
R_next <= X"c1";
G_next <= X"92";
B_next <= X"fc";
when X"6c" =>
R_next <= X"d0";
G_next <= X"a1";
B_next <= X"fe";
when X"6d" =>
R_next <= X"e1";
G_next <= X"b2";
B_next <= X"ff";
when X"6e" =>
R_next <= X"f0";
G_next <= X"c2";
B_next <= X"ff";
when X"6f" =>
R_next <= X"fc";
G_next <= X"d2";
B_next <= X"ff";
when X"70" =>
R_next <= X"00";
G_next <= X"00";
B_next <= X"5c";
when X"71" =>
R_next <= X"00";
G_next <= X"09";
B_next <= X"66";
when X"72" =>
R_next <= X"09";
G_next <= X"18";
B_next <= X"75";
when X"73" =>
R_next <= X"1a";
G_next <= X"29";
B_next <= X"84";
when X"74" =>
R_next <= X"29";
G_next <= X"38";
B_next <= X"93";
when X"75" =>
R_next <= X"3a";
G_next <= X"49";
B_next <= X"a4";
when X"76" =>
R_next <= X"4a";
G_next <= X"59";
B_next <= X"b4";
when X"77" =>
R_next <= X"5c";
G_next <= X"6a";
B_next <= X"c3";
when X"78" =>
R_next <= X"66";
G_next <= X"74";
B_next <= X"cd";
when X"79" =>
R_next <= X"77";
G_next <= X"85";
B_next <= X"df";
when X"7a" =>
R_next <= X"87";
G_next <= X"96";
B_next <= X"ef";
when X"7b" =>
R_next <= X"98";
G_next <= X"a7";
B_next <= X"fc";
when X"7c" =>
R_next <= X"a8";
G_next <= X"b6";
B_next <= X"fe";
when X"7d" =>
R_next <= X"b9";
G_next <= X"c7";
B_next <= X"ff";
when X"7e" =>
R_next <= X"c8";
G_next <= X"d6";
B_next <= X"ff";
when X"7f" =>
R_next <= X"d8";
G_next <= X"e7";
B_next <= X"ff";
when X"80" =>
R_next <= X"00";
G_next <= X"0b";
B_next <= X"45";
when X"81" =>
R_next <= X"00";
G_next <= X"16";
B_next <= X"4f";
when X"82" =>
R_next <= X"00";
G_next <= X"25";
B_next <= X"5d";
when X"83" =>
R_next <= X"09";
G_next <= X"36";
B_next <= X"6d";
when X"84" =>
R_next <= X"18";
G_next <= X"45";
B_next <= X"7c";
when X"85" =>
R_next <= X"29";
G_next <= X"56";
B_next <= X"8d";
when X"86" =>
R_next <= X"39";
G_next <= X"66";
B_next <= X"9d";
when X"87" =>
R_next <= X"4b";
G_next <= X"77";
B_next <= X"ac";
when X"88" =>
R_next <= X"56";
G_next <= X"81";
B_next <= X"b6";
when X"89" =>
R_next <= X"67";
G_next <= X"92";
B_next <= X"c8";
when X"8a" =>
R_next <= X"77";
G_next <= X"a2";
B_next <= X"d9";
when X"8b" =>
R_next <= X"88";
G_next <= X"b3";
B_next <= X"e9";
when X"8c" =>
R_next <= X"98";
G_next <= X"c3";
B_next <= X"f7";
when X"8d" =>
R_next <= X"a9";
G_next <= X"d3";
B_next <= X"fe";
when X"8e" =>
R_next <= X"b8";
G_next <= X"e3";
B_next <= X"ff";
when X"8f" =>
R_next <= X"c8";
G_next <= X"f3";
B_next <= X"ff";
when X"90" =>
R_next <= X"00";
G_next <= X"16";
B_next <= X"25";
when X"91" =>
R_next <= X"00";
G_next <= X"22";
B_next <= X"30";
when X"92" =>
R_next <= X"00";
G_next <= X"31";
B_next <= X"3f";
when X"93" =>
R_next <= X"01";
G_next <= X"42";
B_next <= X"4f";
when X"94" =>
R_next <= X"0c";
G_next <= X"51";
B_next <= X"5e";
when X"95" =>
R_next <= X"1e";
G_next <= X"62";
B_next <= X"6f";
when X"96" =>
R_next <= X"2e";
G_next <= X"72";
B_next <= X"80";
when X"97" =>
R_next <= X"40";
G_next <= X"82";
B_next <= X"8f";
when X"98" =>
R_next <= X"4a";
G_next <= X"8d";
B_next <= X"99";
when X"99" =>
R_next <= X"5c";
G_next <= X"9d";
B_next <= X"ab";
when X"9a" =>
R_next <= X"6c";
G_next <= X"ae";
B_next <= X"bc";
when X"9b" =>
R_next <= X"7e";
G_next <= X"be";
B_next <= X"cc";
when X"9c" =>
R_next <= X"8d";
G_next <= X"ce";
B_next <= X"db";
when X"9d" =>
R_next <= X"9e";
G_next <= X"de";
B_next <= X"ed";
when X"9e" =>
R_next <= X"ad";
G_next <= X"ee";
B_next <= X"fa";
when X"9f" =>
R_next <= X"bd";
G_next <= X"fc";
B_next <= X"fe";
when X"a0" =>
R_next <= X"00";
G_next <= X"24";
B_next <= X"00";
when X"a1" =>
R_next <= X"00";
G_next <= X"2f";
B_next <= X"00";
when X"a2" =>
R_next <= X"00";
G_next <= X"3e";
B_next <= X"0a";
when X"a3" =>
R_next <= X"00";
G_next <= X"4f";
B_next <= X"1a";
when X"a4" =>
R_next <= X"08";
G_next <= X"5e";
B_next <= X"29";
when X"a5" =>
R_next <= X"18";
G_next <= X"6f";
B_next <= X"3b";
when X"a6" =>
R_next <= X"28";
G_next <= X"7f";
B_next <= X"4b";
when X"a7" =>
R_next <= X"3a";
G_next <= X"8f";
B_next <= X"5c";
when X"a8" =>
R_next <= X"44";
G_next <= X"9a";
B_next <= X"65";
when X"a9" =>
R_next <= X"55";
G_next <= X"ab";
B_next <= X"78";
when X"aa" =>
R_next <= X"65";
G_next <= X"bb";
B_next <= X"88";
when X"ab" =>
R_next <= X"77";
G_next <= X"cc";
B_next <= X"99";
when X"ac" =>
R_next <= X"86";
G_next <= X"db";
B_next <= X"a8";
when X"ad" =>
R_next <= X"97";
G_next <= X"ec";
B_next <= X"ba";
when X"ae" =>
R_next <= X"a6";
G_next <= X"fa";
B_next <= X"c9";
when X"af" =>
R_next <= X"b7";
G_next <= X"fe";
B_next <= X"d9";
when X"b0" =>
R_next <= X"00";
G_next <= X"2a";
B_next <= X"00";
when X"b1" =>
R_next <= X"00";
G_next <= X"37";
B_next <= X"00";
when X"b2" =>
R_next <= X"00";
G_next <= X"46";
B_next <= X"00";
when X"b3" =>
R_next <= X"01";
G_next <= X"56";
B_next <= X"00";
when X"b4" =>
R_next <= X"0f";
G_next <= X"65";
B_next <= X"00";
when X"b5" =>
R_next <= X"20";
G_next <= X"76";
B_next <= X"03";
when X"b6" =>
R_next <= X"31";
G_next <= X"85";
B_next <= X"13";
when X"b7" =>
R_next <= X"42";
G_next <= X"96";
B_next <= X"24";
when X"b8" =>
R_next <= X"4c";
G_next <= X"a1";
B_next <= X"2d";
when X"b9" =>
R_next <= X"5d";
G_next <= X"b1";
B_next <= X"40";
when X"ba" =>
R_next <= X"6d";
G_next <= X"c1";
B_next <= X"51";
when X"bb" =>
R_next <= X"7f";
G_next <= X"d2";
B_next <= X"62";
when X"bc" =>
R_next <= X"8e";
G_next <= X"e2";
B_next <= X"71";
when X"bd" =>
R_next <= X"9f";
G_next <= X"f2";
B_next <= X"82";
when X"be" =>
R_next <= X"af";
G_next <= X"fd";
B_next <= X"92";
when X"bf" =>
R_next <= X"bf";
G_next <= X"ff";
B_next <= X"a1";
when X"c0" =>
R_next <= X"00";
G_next <= X"24";
B_next <= X"00";
when X"c1" =>
R_next <= X"00";
G_next <= X"31";
B_next <= X"00";
when X"c2" =>
R_next <= X"05";
G_next <= X"40";
B_next <= X"00";
when X"c3" =>
R_next <= X"16";
G_next <= X"50";
B_next <= X"00";
when X"c4" =>
R_next <= X"26";
G_next <= X"5f";
B_next <= X"00";
when X"c5" =>
R_next <= X"36";
G_next <= X"70";
B_next <= X"00";
when X"c6" =>
R_next <= X"47";
G_next <= X"80";
B_next <= X"00";
when X"c7" =>
R_next <= X"58";
G_next <= X"90";
B_next <= X"08";
when X"c8" =>
R_next <= X"62";
G_next <= X"9b";
B_next <= X"12";
when X"c9" =>
R_next <= X"73";
G_next <= X"ac";
B_next <= X"24";
when X"ca" =>
R_next <= X"84";
G_next <= X"bc";
B_next <= X"35";
when X"cb" =>
R_next <= X"95";
G_next <= X"cd";
B_next <= X"46";
when X"cc" =>
R_next <= X"a4";
G_next <= X"dc";
B_next <= X"55";
when X"cd" =>
R_next <= X"b5";
G_next <= X"ed";
B_next <= X"67";
when X"ce" =>
R_next <= X"c5";
G_next <= X"fb";
B_next <= X"77";
when X"cf" =>
R_next <= X"d5";
G_next <= X"ff";
B_next <= X"86";
when X"d0" =>
R_next <= X"02";
G_next <= X"18";
B_next <= X"00";
when X"d1" =>
R_next <= X"0f";
G_next <= X"25";
B_next <= X"00";
when X"d2" =>
R_next <= X"1f";
G_next <= X"34";
B_next <= X"00";
when X"d3" =>
R_next <= X"2f";
G_next <= X"45";
B_next <= X"00";
when X"d4" =>
R_next <= X"3f";
G_next <= X"54";
B_next <= X"00";
when X"d5" =>
R_next <= X"4f";
G_next <= X"65";
B_next <= X"00";
when X"d6" =>
R_next <= X"60";
G_next <= X"75";
B_next <= X"00";
when X"d7" =>
R_next <= X"70";
G_next <= X"86";
B_next <= X"01";
when X"d8" =>
R_next <= X"7b";
G_next <= X"90";
B_next <= X"0a";
when X"d9" =>
R_next <= X"8c";
G_next <= X"a1";
B_next <= X"1c";
when X"da" =>
R_next <= X"9c";
G_next <= X"b1";
B_next <= X"2c";
when X"db" =>
R_next <= X"ad";
G_next <= X"c2";
B_next <= X"3e";
when X"dc" =>
R_next <= X"bd";
G_next <= X"d1";
B_next <= X"4d";
when X"dd" =>
R_next <= X"cd";
G_next <= X"e2";
B_next <= X"5e";
when X"de" =>
R_next <= X"dd";
G_next <= X"f1";
B_next <= X"6e";
when X"df" =>
R_next <= X"ed";
G_next <= X"fd";
B_next <= X"7e";
when X"e0" =>
R_next <= X"1e";
G_next <= X"09";
B_next <= X"00";
when X"e1" =>
R_next <= X"2a";
G_next <= X"16";
B_next <= X"00";
when X"e2" =>
R_next <= X"39";
G_next <= X"25";
B_next <= X"00";
when X"e3" =>
R_next <= X"49";
G_next <= X"36";
B_next <= X"00";
when X"e4" =>
R_next <= X"58";
G_next <= X"45";
B_next <= X"00";
when X"e5" =>
R_next <= X"69";
G_next <= X"56";
B_next <= X"00";
when X"e6" =>
R_next <= X"79";
G_next <= X"66";
B_next <= X"00";
when X"e7" =>
R_next <= X"8a";
G_next <= X"77";
B_next <= X"08";
when X"e8" =>
R_next <= X"94";
G_next <= X"81";
B_next <= X"12";
when X"e9" =>
R_next <= X"a5";
G_next <= X"92";
B_next <= X"24";
when X"ea" =>
R_next <= X"b5";
G_next <= X"a3";
B_next <= X"35";
when X"eb" =>
R_next <= X"c6";
G_next <= X"b3";
B_next <= X"46";
when X"ec" =>
R_next <= X"d6";
G_next <= X"c3";
B_next <= X"55";
when X"ed" =>
R_next <= X"e6";
G_next <= X"d4";
B_next <= X"66";
when X"ee" =>
R_next <= X"f6";
G_next <= X"e3";
B_next <= X"76";
when X"ef" =>
R_next <= X"fe";
G_next <= X"f3";
B_next <= X"86";
when X"f0" =>
R_next <= X"34";
G_next <= X"00";
B_next <= X"00";
when X"f1" =>
R_next <= X"40";
G_next <= X"05";
B_next <= X"00";
when X"f2" =>
R_next <= X"4f";
G_next <= X"15";
B_next <= X"00";
when X"f3" =>
R_next <= X"5f";
G_next <= X"25";
B_next <= X"00";
when X"f4" =>
R_next <= X"6e";
G_next <= X"35";
B_next <= X"00";
when X"f5" =>
R_next <= X"7f";
G_next <= X"46";
B_next <= X"03";
when X"f6" =>
R_next <= X"8f";
G_next <= X"56";
B_next <= X"13";
when X"f7" =>
R_next <= X"9f";
G_next <= X"67";
B_next <= X"23";
when X"f8" =>
R_next <= X"aa";
G_next <= X"71";
B_next <= X"2e";
when X"f9" =>
R_next <= X"ba";
G_next <= X"82";
B_next <= X"40";
when X"fa" =>
R_next <= X"cb";
G_next <= X"92";
B_next <= X"51";
when X"fb" =>
R_next <= X"dc";
G_next <= X"a3";
B_next <= X"62";
when X"fc" =>
R_next <= X"eb";
G_next <= X"b3";
B_next <= X"71";
when X"fd" =>
R_next <= X"fa";
G_next <= X"c3";
B_next <= X"82";
when X"fe" =>
R_next <= X"fe";
G_next <= X"d3";
B_next <= X"92";
when X"ff" =>
R_next <= X"ff";
G_next <= X"e3";
B_next <= X"a1";
when others =>
-- nop
end case;
end process;
end laoo;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
hSmRZ/vf8BkmPtDxpmqOyny86zievG18EWWjJIEq9on8MDlXKJx1eTWoEoNhOnJ8+/QcvfJKEZoM
iGqcWtCz+g==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MJavrnR0ZzCXxDP9w2eMVjDsPDaxmuDc0X/w8r9NE7Bv+xeeh5zjIzDFyqBTDL3Q6toG1T7Nmmis
Eq6EYCzBX8V0QqGpFVtvDpbP2l9gCmpU/OrEadvPWQshRzBuDrPFyqe2pH7YJM0qXErXv8RpvKMc
UrwBEG7GdP3nl8H1tYU=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 23152)
`protect data_block
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|
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`protect end_protected
|
-- Library & Use Statements
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY infrastructure IS
PORT(
clk : IN std_logic;
reset_n : IN std_logic;
serdata_in : IN std_logic;
serdata_out : OUT std_logic
);
END infrastructure;
-- Architecture Declaration
ARCHITECTURE rtl OF infrastructure IS
-- Signals & Constants Declaration
SIGNAL q1, q2: std_logic:= '0';
-- Begin Architecture
BEGIN
-------------------------------------------
-- Process for registers (flip-flops)
-------------------------------------------
flip_flops : PROCESS(clk, reset_n, q1)
BEGIN
IF reset_n = '0' THEN
q1 <= '0';
q2 <= '0';
ELSIF rising_edge(clk) THEN
q1 <= serdata_in;
q2 <= q1;
END IF;
END PROCESS flip_flops;
serdata_out <= q2;
END rtl;
|
-----------------------------------------------------------------------------
--! @file
--! @copyright Copyright 2015 GNSS Sensor Ltd. All right reserved.
--! @author Sergey Khabarov - [email protected]
--! @brief Package for common testbenches implementation.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
package types_util is
function strlen(s: in string) return integer;
function StringToUVector(inStr: string) return std_ulogic_vector;
function StringToSVector(inStr: string) return std_logic_vector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector) return std_logic_vector;
function SignalFromString(inStr: string; ind : integer ) return std_logic;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector;
function tost(v:std_logic_vector) return string;
function tost(v:std_logic) return string;
function tost(i : integer) return string;
procedure print(s : string);
end;
package body types_util is
function strlen(s: in string) return integer is
variable n: integer:=0; variable sj: integer:=s'left;
begin
loop
if sj>s'right then exit;
elsif s(sj)=NUL then exit; --sequential if protects sj > length
else sj:=sj+1; n:=n+1;
end if;
end loop;
return n;
end strlen;
function SignalFromString(inStr: string; ind : integer ) return std_logic is
variable temp: std_logic := 'X';
begin
if(inStr(inStr'high-ind)='1') then temp := '1';
elsif(inStr(inStr'high-ind)='0') then temp := '0';
end if;
return temp;
end function SignalFromString;
function StringToUVector(inStr: string) return std_ulogic_vector is
variable temp: std_ulogic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToUVector;
-- conversion function
function StringToSVector(inStr: string) return std_logic_vector is
variable temp: std_logic_vector(inStr'range) := (others => 'X');
begin
for i in inStr'range loop --
if(inStr(inStr'high-i+1)='1') then temp(i) := '1';
elsif(inStr(inStr'high-i+1)='0') then temp(i) := '0';
end if;
end loop;
return temp(inStr'high downto 1);
end function StringToSVector;
function SymbolToSVector(inStr: string; idx: integer) return std_logic_vector is
constant ss: string(1 to inStr'length) := inStr;
variable c : integer;
variable temp: std_logic_vector(7 downto 0) := (others => 'X');
begin
c := character'pos(ss(idx+1));
for i in 0 to 7 loop --
temp(i) := to_unsigned(c,8)(i);
end loop;
return temp;
end function SymbolToSVector;
function UnsignedToSigned(inUnsigned: std_ulogic_vector)
return std_logic_vector is
variable temp: std_logic_vector(inUnsigned'length-1 downto 0) := (others => 'X');
variable i: integer:=0;
begin
while i < inUnsigned'length loop
if(inUnsigned(i)='1') then temp(i) := '1';
elsif(inUnsigned(i)='0') then temp(i) := '0';
end if;
i := i+1;
end loop;
return temp;
end function UnsignedToSigned;
subtype nibble is std_logic_vector(3 downto 0);
function todec(i:integer) return character is
begin
case i is
when 0 => return('0');
when 1 => return('1');
when 2 => return('2');
when 3 => return('3');
when 4 => return('4');
when 5 => return('5');
when 6 => return('6');
when 7 => return('7');
when 8 => return('8');
when 9 => return('9');
when others => return('0');
end case;
end;
function tohex(n:nibble) return character is
begin
case n is
when "0000" => return('0');
when "0001" => return('1');
when "0010" => return('2');
when "0011" => return('3');
when "0100" => return('4');
when "0101" => return('5');
when "0110" => return('6');
when "0111" => return('7');
when "1000" => return('8');
when "1001" => return('9');
when "1010" => return('a');
when "1011" => return('b');
when "1100" => return('c');
when "1101" => return('d');
when "1110" => return('e');
when "1111" => return('f');
when others => return('X');
end case;
end;
function tost(v:std_logic_vector) return string is
constant vlen : natural := v'length; --'
constant slen : natural := (vlen+3)/4;
variable vv : std_logic_vector(0 to slen*4-1) := (others => '0');
variable s : string(1 to slen);
variable nz : boolean := false;
variable index : integer := -1;
begin
vv(slen*4-vlen to slen*4-1) := v;
for i in 0 to slen-1 loop
if (vv(i*4 to i*4+3) = "0000") and nz and (i /= (slen-1)) then
index := i;
else
nz := false;
s(i+1) := tohex(vv(i*4 to i*4+3));
end if;
end loop;
if ((index +2) = slen) then return(s(slen to slen));
else return(string'("0x") & s(index+2 to slen)); end if; --'
end;
function tost(v:std_logic) return string is
begin
if to_x01(v) = '1' then return("1"); else return("0"); end if;
end;
function tost(i : integer) return string is
variable L : line;
variable s, x : string(1 to 128);
variable n, tmp : integer := 0;
begin
tmp := i;
if i < 0 then tmp := -i; end if;
loop
s(128-n) := todec(tmp mod 10);
tmp := tmp / 10;
n := n+1;
if tmp = 0 then exit; end if;
end loop;
x(1 to n) := s(129-n to 128);
if i < 0 then return "-" & x(1 to n); end if;
return(x(1 to n));
end;
procedure print(s : string) is
variable L : line;
begin
L := new string'(s); writeline(output, L);
end;
end;
|
-------------------------------------------------------------------------------
-- Author: David Wolf, Leonhardt Schwarz
-- Project: FPGA Project
--
-- Copyright (C) 2014 David Wolf, Leonhardt Schwarz
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bcd is
port(
clk : in std_logic; -- Takteingang
reset_n : in std_logic; -- Externer Reset
reset_i : in std_logic; -- Interner Reset
enable_i : in std_logic; -- '0'=FALSE und '1'=TRUE
operation_i : in std_logic; -- '0'=UP und '1'=DOWN
result_o : out std_logic_vector(3 downto 0)); -- Ergebnis der Berechnung
end bcd;
|
library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
library work;
use work.rv_components.all;
use work.utils.all;
use work.constants_pkg.all;
entity cache_controller is
generic (
CACHE_SIZE : natural;
LINE_SIZE : positive range 16 to 256;
ADDRESS_WIDTH : positive;
INTERNAL_WIDTH : positive;
EXTERNAL_WIDTH : positive;
LOG2_BURSTLENGTH : positive;
POLICY : cache_policy;
REGION_OPTIMIZATIONS : boolean;
WRITE_FIRST_SUPPORTED : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
--Cache control (Invalidate/flush/writeback)
from_cache_control_ready : out std_logic;
to_cache_control_valid : in std_logic;
to_cache_control_command : in cache_control_command;
to_cache_control_base : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
to_cache_control_last : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
precache_idle : in std_logic;
cache_idle : out std_logic;
--Cache interface ORCA-internal memory-mapped slave
cacheint_oimm_address : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
cacheint_oimm_byteenable : in std_logic_vector((INTERNAL_WIDTH/8)-1 downto 0);
cacheint_oimm_requestvalid : in std_logic;
cacheint_oimm_readnotwrite : in std_logic;
cacheint_oimm_writedata : in std_logic_vector(INTERNAL_WIDTH-1 downto 0);
cacheint_oimm_readdata : out std_logic_vector(INTERNAL_WIDTH-1 downto 0);
cacheint_oimm_readdatavalid : out std_logic;
cacheint_oimm_waitrequest : buffer std_logic;
--Cached ORCA-internal memory-mapped master
c_oimm_address : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
c_oimm_burstlength : out std_logic_vector(LOG2_BURSTLENGTH downto 0);
c_oimm_burstlength_minus1 : out std_logic_vector(LOG2_BURSTLENGTH-1 downto 0);
c_oimm_byteenable : out std_logic_vector((EXTERNAL_WIDTH/8)-1 downto 0);
c_oimm_requestvalid : out std_logic;
c_oimm_readnotwrite : out std_logic;
c_oimm_writedata : out std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
c_oimm_writelast : out std_logic;
c_oimm_readdata : in std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
c_oimm_readdatavalid : in std_logic;
c_oimm_waitrequest : in std_logic
);
end entity cache_controller;
architecture rtl of cache_controller is
constant DIRTY_BITS : natural := conditional(POLICY = WRITE_BACK, 1, 0);
constant NUM_LINES : positive := CACHE_SIZE/LINE_SIZE;
constant TAG_BITS : positive := ADDRESS_WIDTH-log2(CACHE_SIZE);
constant TAG_LEFT : natural := ADDRESS_WIDTH-1;
constant TAG_RIGHT : natural := log2(NUM_LINES)+log2(LINE_SIZE);
constant CACHELINE_BITS : positive := log2(NUM_LINES);
constant CACHELINE_RIGHT : natural := log2(LINE_SIZE);
constant INTERNAL_WORDS_PER_EXTERNAL_WORD : positive := EXTERNAL_WIDTH/INTERNAL_WIDTH;
alias to_cache_control_base_tag_line : std_logic_vector(TAG_BITS+CACHELINE_BITS-1 downto 0) is
to_cache_control_base(TAG_LEFT downto CACHELINE_RIGHT);
alias to_cache_control_last_tag_line : std_logic_vector(TAG_BITS+CACHELINE_BITS-1 downto 0) is
to_cache_control_last(TAG_LEFT downto CACHELINE_RIGHT);
signal to_cache_control_base_partial : std_logic;
signal to_cache_control_last_partial : std_logic;
signal cache_walker_read_tag_line : std_logic_vector(TAG_BITS+CACHELINE_BITS-1 downto 0);
signal read_region_base_hit : std_logic;
signal read_region_inner_hit : std_logic;
signal read_region_last_hit : std_logic;
signal read_region_hit : std_logic;
signal read_region_hit_partial : std_logic;
function compute_burst_length
return positive is
begin -- function compute_burst_length
if LINE_SIZE/(EXTERNAL_WIDTH/8) > (2**LOG2_BURSTLENGTH) then
return 2**LOG2_BURSTLENGTH;
end if;
return LINE_SIZE/(EXTERNAL_WIDTH/8);
end function compute_burst_length;
constant BYTES_PER_BEAT : positive := EXTERNAL_WIDTH/8;
constant BEATS_PER_BURST : positive range 1 to (2**LOG2_BURSTLENGTH) := compute_burst_length;
constant BYTES_PER_BURST : positive := BYTES_PER_BEAT*BEATS_PER_BURST;
constant BEATS_PER_LINE : positive := LINE_SIZE/BYTES_PER_BEAT;
constant BURSTS_PER_LINE : positive := LINE_SIZE/BYTES_PER_BURST;
signal read_miss : std_logic;
signal read_requestinflight : std_logic;
signal read_lastaddress : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal read_lastline : unsigned(log2(NUM_LINES)-1 downto 0);
type control_state_type is (WALK_CACHE, IDLE, CACHE_MISSED, WAIT_FOR_HIT);
signal control_state : control_state_type;
signal next_control_state : control_state_type;
signal write_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal write_byteenable : std_logic_vector((EXTERNAL_WIDTH/8)-1 downto 0);
signal write_writedata : std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
signal write_requestvalid : std_logic;
signal write_tag_update : std_logic;
signal write_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
alias write_tag_valid : std_logic is write_dirty_valid(0);
signal cache_mgt_tag_update : std_logic;
signal cache_mgt_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
alias cache_mgt_tag_valid : std_logic is cache_mgt_dirty_valid(0);
signal cache_walker_tag_update : std_logic;
signal cache_walker_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
alias cache_walker_tag_valid : std_logic is cache_walker_dirty_valid(0);
signal start_to_cache_walker : std_logic;
signal ready_from_cache_walker : std_logic;
signal done_from_cache_walker : std_logic;
signal cache_walking : std_logic;
signal cache_walker_command : cache_control_command;
signal cache_walker_line : unsigned(log2(NUM_LINES)-1 downto 0);
signal cache_walker_line_increment : std_logic;
signal cache_walker_line_last : std_logic;
signal write_hit : std_logic;
signal write_hit_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
signal filling : std_logic;
signal fill_reading : std_logic;
signal start_to_filler : std_logic;
signal ready_from_filler : std_logic;
signal done_from_filler : std_logic;
signal fill_external_offset : unsigned(log2(LINE_SIZE)-1 downto 0);
signal fill_external_offset_increment : std_logic;
signal fill_external_offset_last : std_logic;
signal fill_internal_offset : unsigned(log2(LINE_SIZE)-1 downto 0);
signal fill_internal_offset_increment : std_logic;
signal fill_internal_offset_last : std_logic;
signal write_idle : std_logic;
signal write_ready : std_logic;
signal write_on_hit : std_logic;
signal read_address : std_logic_vector(ADDRESS_WIDTH-1 downto 0);
signal read_requestvalid : std_logic;
signal read_speculative : std_logic;
signal read_readdata : std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
signal read_readdatavalid : std_logic;
signal read_readabort : std_logic;
signal read_tag : std_logic_vector(TAG_BITS-1 downto 0);
signal read_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
begin
--Idle when no reads in flight (either hit or miss), not waiting on a
--writeback/writethrough, and not walking the cache.
--Idle is state-only; do not check for incoming requests
cache_idle <= (not read_requestinflight) and write_idle and (not cache_walking);
cacheint_oimm_waitrequest <= read_miss or
(not write_ready) or
cache_walking;
c_oimm_address(log2(BYTES_PER_BEAT)-1 downto 0) <= (others => '0');
read_requestvalid <= cacheint_oimm_requestvalid and (not cacheint_oimm_waitrequest);
cacheint_oimm_readdatavalid <= read_readdatavalid and (not write_on_hit);
single_internal_word_gen : if INTERNAL_WORDS_PER_EXTERNAL_WORD = 1 generate
cacheint_oimm_readdata <= read_readdata;
end generate single_internal_word_gen;
multiple_internal_words_gen : if INTERNAL_WORDS_PER_EXTERNAL_WORD > 1 generate
type internal_word_vector is array (natural range <>) of std_logic_vector(INTERNAL_WIDTH-1 downto 0);
signal read_readdata_word : internal_word_vector(INTERNAL_WORDS_PER_EXTERNAL_WORD-1 downto 0);
begin
internal_word_gen : for gword in INTERNAL_WORDS_PER_EXTERNAL_WORD-1 downto 0 generate
read_readdata_word(gword) <= read_readdata(((gword+1)*INTERNAL_WIDTH)-1 downto gword*INTERNAL_WIDTH);
end generate internal_word_gen;
cacheint_oimm_readdata <=
read_readdata_word(to_integer(unsigned(read_lastaddress(log2(EXTERNAL_WIDTH/8)-1 downto
log2(INTERNAL_WIDTH/8)))));
end generate multiple_internal_words_gen;
------------------------------------------------------------------------------
-- Cache Contol FSM
------------------------------------------------------------------------------
process(control_state, cache_walker_tag_update, cache_walker_dirty_valid, done_from_cache_walker, read_miss, ready_from_filler, precache_idle, cacheint_oimm_requestvalid, write_idle, to_cache_control_valid, ready_from_cache_walker, to_cache_control_command, done_from_filler)
begin
next_control_state <= control_state;
cache_mgt_tag_update <= '0';
cache_mgt_dirty_valid <= (others => '0');
start_to_filler <= '0';
from_cache_control_ready <= '0';
start_to_cache_walker <= '0';
case control_state is
when WALK_CACHE =>
cache_mgt_tag_update <= cache_walker_tag_update;
cache_mgt_dirty_valid <= cache_walker_dirty_valid;
if done_from_cache_walker = '1' then
next_control_state <= IDLE;
end if;
when IDLE =>
--Could make this combinational to reduce miss latency by one cycle at
--the expense of a longer path to external memory.
if read_miss = '1' then
start_to_filler <= '1';
if ready_from_filler = '1' then
next_control_state <= CACHE_MISSED;
cache_mgt_tag_update <= '1';
cache_mgt_tag_valid <= '0';
end if;
else
if precache_idle = '1' and cacheint_oimm_requestvalid = '0' and write_idle = '1' then
if ready_from_cache_walker = '1' then
from_cache_control_ready <= '1';
if to_cache_control_valid = '1' then
case to_cache_control_command is
when WRITEBACK =>
--Skip writeback commands for read_only and writethrough caches
if POLICY = WRITE_BACK then
start_to_cache_walker <= '1';
next_control_state <= WALK_CACHE;
end if;
when others =>
--Initialize/Invalidate/Flush
start_to_cache_walker <= '1';
next_control_state <= WALK_CACHE;
end case;
end if;
end if;
end if;
end if;
when CACHE_MISSED =>
if done_from_filler = '1' then
cache_mgt_tag_update <= '1';
cache_mgt_tag_valid <= '1';
next_control_state <= WAIT_FOR_HIT;
end if;
when WAIT_FOR_HIT =>
if read_miss = '0' then
next_control_state <= IDLE;
end if;
when others =>
null;
end case;
end process;
ready_from_cache_walker <= '1';
cache_walker_line_last <= '1' when cache_walker_line = to_unsigned(NUM_LINES-1, log2(NUM_LINES)) else '0';
process(clk)
begin
if rising_edge(clk) then
control_state <= next_control_state;
if done_from_cache_walker = '1' then
cache_walking <= '0';
end if;
if start_to_cache_walker = '1' and ready_from_cache_walker = '1' then
cache_walking <= '1';
cache_walker_command <= to_cache_control_command;
end if;
if cache_walker_line_increment = '1' then
cache_walker_line <= cache_walker_line + to_unsigned(1, cache_walker_line'length);
end if;
if reset = '1' then
control_state <= WALK_CACHE;
cache_walker_command <= INITIALIZE;
cache_walking <= '1';
cache_walker_line <= to_unsigned(0, cache_walker_line'length);
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Cache Filler FSM
------------------------------------------------------------------------------
done_from_filler <= filling and (fill_internal_offset_increment and fill_internal_offset_last);
process(clk)
begin
if rising_edge(clk) then
if fill_external_offset_increment = '1' and fill_external_offset_last = '1' then
fill_reading <= '0';
end if;
if done_from_filler = '1' then
filling <= '0';
end if;
if start_to_filler = '1' and ready_from_filler = '1' then
fill_reading <= '1';
filling <= '1';
end if;
if reset = '1' then
fill_reading <= '0';
filling <= '0';
end if;
end if;
end process;
fill_internal_offset_increment <= c_oimm_readdatavalid;
fill_external_offset_increment <= (not c_oimm_waitrequest) and fill_reading;
one_beat_per_line_gen : if BEATS_PER_LINE = 1 generate
fill_internal_offset_last <= '1';
fill_internal_offset <= to_unsigned(0, fill_internal_offset'length);
end generate one_beat_per_line_gen;
multiple_beats_per_line_gen : if BEATS_PER_LINE > 1 generate
fill_internal_offset_last <= '1' when (fill_internal_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) =
to_unsigned(BEATS_PER_LINE-1, log2(BEATS_PER_LINE))) else
'0';
process(clk)
begin
if rising_edge(clk) then
if fill_internal_offset_increment = '1' then
fill_internal_offset <= fill_internal_offset + to_unsigned(BYTES_PER_BEAT, fill_internal_offset'length);
end if;
if reset = '1' then
fill_internal_offset <= to_unsigned(0, fill_internal_offset'length);
end if;
end if;
end process;
end generate multiple_beats_per_line_gen;
one_burst_per_line_gen : if BURSTS_PER_LINE = 1 generate
fill_external_offset_last <= '1';
fill_external_offset <= to_unsigned(0, fill_external_offset'length);
end generate one_burst_per_line_gen;
multiple_bursts_per_line_gen : if BURSTS_PER_LINE > 1 generate
fill_external_offset_last <= '1' when (fill_external_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BURST)) =
to_unsigned(BURSTS_PER_LINE-1, log2(BURSTS_PER_LINE))) else
'0';
process(clk)
begin
if rising_edge(clk) then
if fill_external_offset_increment = '1' then
fill_external_offset <= fill_external_offset + to_unsigned(BYTES_PER_BURST, fill_external_offset'length);
end if;
if reset = '1' then
fill_external_offset <= to_unsigned(0, fill_external_offset'length);
end if;
end if;
end process;
end generate multiple_bursts_per_line_gen;
--Write if filling a cacheline (c_oimm_readdatavalid) or a write has caused a
--tag check (write_on_hit) and that write has hit an existing cacheline
--(read_readdatavalid)
write_hit <= write_on_hit and read_readdatavalid;
write_hit_dirty_valid(0) <= '1';
write_requestvalid <= c_oimm_readdatavalid or write_hit;
write_tag_update <= cache_mgt_tag_update or write_hit;
write_dirty_valid <= write_hit_dirty_valid when write_hit = '1' else cache_mgt_dirty_valid;
------------------------------------------------------------------------------
-- Cache Internals
------------------------------------------------------------------------------
the_cache : cache
generic map (
NUM_LINES => NUM_LINES,
LINE_SIZE => LINE_SIZE,
ADDRESS_WIDTH => ADDRESS_WIDTH,
WIDTH => EXTERNAL_WIDTH,
DIRTY_BITS => DIRTY_BITS,
WRITE_FIRST_SUPPORTED => WRITE_FIRST_SUPPORTED
)
port map (
clk => clk,
reset => reset,
read_address => read_address,
read_requestvalid => read_requestvalid,
read_speculative => read_speculative,
read_readdata => read_readdata,
read_readdatavalid => read_readdatavalid,
read_readabort => read_readabort,
read_miss => read_miss,
read_requestinflight => read_requestinflight,
read_lastaddress => read_lastaddress,
read_tag => read_tag,
read_dirty_valid => read_dirty_valid,
write_address => write_address,
write_byteenable => write_byteenable,
write_requestvalid => write_requestvalid,
write_writedata => write_writedata,
write_tag_update => write_tag_update,
write_dirty_valid => write_dirty_valid
);
read_lastline <= unsigned(read_lastaddress(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)));
cache_walker_read_tag_line <= read_tag & std_logic_vector(cache_walker_line);
to_cache_control_base_partial <=
'1' when to_cache_control_base(log2(LINE_SIZE)-1 downto 0) /= replicate_slv("0", log2(LINE_SIZE)) else '0';
read_region_base_hit <= '1' when cache_walker_read_tag_line = to_cache_control_base_tag_line else '0';
read_region_inner_hit <= '1' when (unsigned(cache_walker_read_tag_line) > unsigned(to_cache_control_base_tag_line) and
unsigned(cache_walker_read_tag_line) < unsigned(to_cache_control_last_tag_line)) else '0';
to_cache_control_last_partial <=
'1' when to_cache_control_last(log2(LINE_SIZE)-1 downto 0) /= replicate_slv("1", log2(LINE_SIZE)) else '0';
read_region_last_hit <= '1' when cache_walker_read_tag_line = to_cache_control_last_tag_line else '0';
--If REGION_OPTIMIZATIONS are off then everything hits and we treat all hits
--as partial hits (i.e. requiring a writeback before invalidating).
read_region_hit <=
read_region_base_hit or read_region_inner_hit or read_region_last_hit when REGION_OPTIMIZATIONS else '1';
read_region_hit_partial <= ((read_region_base_hit and to_cache_control_base_partial) or
(read_region_last_hit and to_cache_control_last_partial)) when REGION_OPTIMIZATIONS else
'1';
------------------------------------------------------------------------------
-- Read-only
------------------------------------------------------------------------------
read_only_gen : if POLICY = READ_ONLY generate
--Cache walking 'FSM'; just invalidate every line (not entered on Writeback/Flush)
cache_walker_tag_update <= cache_walking;
cache_walker_tag_valid <= '0';
cache_walker_line_increment <= cache_walking;
done_from_cache_walker <= cache_walker_line_last and cache_walking;
write_idle <= '1';
write_ready <= '1';
write_on_hit <= '0';
write_writedata <= c_oimm_readdata;
write_byteenable <= (others => '1');
c_oimm_byteenable <= (others => '1');
c_oimm_writedata <= (others => '-');
c_oimm_burstlength <= std_logic_vector(to_unsigned(BEATS_PER_BURST, c_oimm_burstlength'length));
c_oimm_burstlength_minus1 <=
std_logic_vector(to_unsigned(BEATS_PER_BURST-1, c_oimm_burstlength_minus1'length));
c_oimm_writelast <= '1';
ready_from_filler <= (not filling) or done_from_filler;
c_oimm_requestvalid <= fill_reading;
c_oimm_readnotwrite <= '1';
c_oimm_address(ADDRESS_WIDTH-1 downto log2(LINE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(LINE_SIZE));
multiple_beats_per_line_gen : if BEATS_PER_LINE > 1 generate
c_oimm_address(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) <=
std_logic_vector(fill_external_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)));
end generate multiple_beats_per_line_gen;
read_address <= cacheint_oimm_address when read_miss = '0' else
read_lastaddress;
read_speculative <= '0';
--On a cacheline fill use the last address (which caused the miss).
write_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE));
write_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(cache_walker_line) when cache_walking = '1' else
std_logic_vector(read_lastline);
write_address(log2(LINE_SIZE)-1 downto 0) <=
std_logic_vector(fill_internal_offset) when read_miss = '1' else
read_lastaddress(log2(LINE_SIZE)-1 downto 0);
end generate read_only_gen;
------------------------------------------------------------------------------
-- Not Read-only
------------------------------------------------------------------------------
not_read_only_gen : if POLICY /= READ_ONLY generate
signal write_hit_byteenable : std_logic_vector((EXTERNAL_WIDTH/8)-1 downto 0);
signal last_writedata : std_logic_vector(INTERNAL_WIDTH-1 downto 0);
signal done_to_write_on_hit : std_logic;
begin
process (clk) is
begin
if rising_edge(clk) then
if cacheint_oimm_waitrequest = '0' then
last_writedata <= cacheint_oimm_writedata;
end if;
if done_to_write_on_hit = '1' then
write_on_hit <= '0';
end if;
if (cacheint_oimm_requestvalid = '1' and
cacheint_oimm_readnotwrite = '0' and
cacheint_oimm_waitrequest = '0') then
write_on_hit <= '1';
end if;
if reset = '1' then
write_on_hit <= '0';
end if;
end if;
end process;
single_internal_word_gen : if INTERNAL_WORDS_PER_EXTERNAL_WORD = 1 generate
process (clk) is
begin
if rising_edge(clk) then
if cacheint_oimm_waitrequest = '0' then
write_hit_byteenable <= cacheint_oimm_byteenable;
end if;
end if;
end process;
end generate single_internal_word_gen;
multiple_internal_words_gen : if INTERNAL_WORDS_PER_EXTERNAL_WORD > 1 generate
process (clk) is
begin
if rising_edge(clk) then
if cacheint_oimm_waitrequest = '0' then
write_hit_byteenable <= (others => '0');
for iword in INTERNAL_WORDS_PER_EXTERNAL_WORD-1 downto 0 loop
if (unsigned(cacheint_oimm_address(log2(BYTES_PER_BEAT)-1 downto log2(INTERNAL_WIDTH/8))) =
to_unsigned(iword, log2(INTERNAL_WORDS_PER_EXTERNAL_WORD))) then
write_hit_byteenable(((iword+1)*(INTERNAL_WIDTH/8))-1 downto iword*(INTERNAL_WIDTH/8)) <=
cacheint_oimm_byteenable;
end if;
end loop; -- iword
end if;
end if;
end process;
end generate multiple_internal_words_gen;
write_writedata <= c_oimm_readdata when read_miss = '1' else
replicate_slv(last_writedata, INTERNAL_WORDS_PER_EXTERNAL_WORD);
write_byteenable <= (others => '1') when read_miss = '1' else write_hit_byteenable;
----------------------------------------------------------------------------
-- Write-through
----------------------------------------------------------------------------
writethrough_gen : if POLICY = WRITE_THROUGH generate
signal writing_through : std_logic;
signal start_to_write_through : std_logic;
signal ready_from_write_through : std_logic;
signal done_from_write_through : std_logic;
begin
--Cache walking 'FSM'; just invalidate every line (not entered on Writeback/Flush)
cache_walker_tag_update <= cache_walking;
cache_walker_tag_valid <= '0';
cache_walker_line_increment <= cache_walking;
done_from_cache_walker <= cache_walker_line_last and cache_walking;
write_idle <= not writing_through;
write_ready <= ready_from_write_through;
--In write-through mode all writes are single cycle, all reads are BEATS_PER_BURST
c_oimm_burstlength <=
std_logic_vector(to_unsigned(1, c_oimm_burstlength'length)) when writing_through = '1' else
std_logic_vector(to_unsigned(BEATS_PER_BURST, c_oimm_burstlength'length));
c_oimm_burstlength_minus1 <=
std_logic_vector(to_unsigned(0, c_oimm_burstlength_minus1'length)) when writing_through = '1' else
std_logic_vector(to_unsigned(BEATS_PER_BURST-1, c_oimm_burstlength_minus1'length));
c_oimm_writedata <= replicate_slv(last_writedata, INTERNAL_WORDS_PER_EXTERNAL_WORD);
c_oimm_byteenable <= write_hit_byteenable when writing_through = '1' else (others => '1');
c_oimm_writelast <= '1';
ready_from_filler <= ((not filling) or done_from_filler) and ready_from_write_through;
c_oimm_requestvalid <= fill_reading or writing_through;
c_oimm_readnotwrite <= not writing_through;
c_oimm_address(ADDRESS_WIDTH-1 downto log2(LINE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(LINE_SIZE));
multiple_beats_per_line_gen : if BEATS_PER_LINE > 1 generate
c_oimm_address(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) <=
read_lastaddress(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) when writing_through = '1' else
std_logic_vector(fill_external_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)));
end generate multiple_beats_per_line_gen;
read_address <= cacheint_oimm_address when read_miss = '0' else
read_lastaddress;
read_speculative <= not cacheint_oimm_readnotwrite;
done_to_write_on_hit <= read_readdatavalid or read_readabort;
--On a cacheline fill use the last address (which caused the miss). On a
--write hit, use the last address (which caused the hit).
write_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE));
write_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(cache_walker_line) when cache_walking = '1' else
std_logic_vector(read_lastline);
write_address(log2(LINE_SIZE)-1 downto 0) <=
std_logic_vector(fill_internal_offset) when read_miss = '1' else
read_lastaddress(log2(LINE_SIZE)-1 downto 0);
done_from_write_through <= (not c_oimm_waitrequest);
ready_from_write_through <= (not writing_through) or done_from_write_through;
start_to_write_through <=
cacheint_oimm_requestvalid and (not cacheint_oimm_readnotwrite) and (not cacheint_oimm_waitrequest);
process (clk) is
begin
if rising_edge(clk) then
if done_from_write_through = '1' then
writing_through <= '0';
end if;
if start_to_write_through = '1' and ready_from_write_through = '1' then
writing_through <= '1';
end if;
if reset = '1' then
writing_through <= '0';
end if;
end if;
end process;
end generate writethrough_gen;
----------------------------------------------------------------------------
-- Write-back
----------------------------------------------------------------------------
writeback_gen : if POLICY = WRITE_BACK generate
signal start_to_spiller : std_logic;
signal spilling : std_logic;
signal spill_reading_into_buffer : std_logic;
signal spill_reading_from_buffer : std_logic;
signal spill_writing_to_memory : std_logic;
signal spill_skipping : std_logic;
signal ready_from_spiller : std_logic;
signal done_from_spiller : std_logic;
signal spill_offset : unsigned(log2(LINE_SIZE)-1 downto 0);
signal next_spill_offset : unsigned(log2(LINE_SIZE)-1 downto 0);
signal spill_offset_increment : std_logic;
signal spill_offset_last : std_logic;
signal next_spill_offset_last : std_logic;
signal spill_burst_last : std_logic;
signal spill_buffer_read_data : std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
signal spill_buffer_write_enable : std_logic;
signal spill_buffer_write_data : std_logic_vector(EXTERNAL_WIDTH-1 downto 0);
signal spill_tag : std_logic_vector(TAG_BITS-1 downto 0);
signal spill_dirty_valid : std_logic_vector(DIRTY_BITS downto 0);
signal spill_region_hit : std_logic;
signal spill_line : unsigned(log2(NUM_LINES)-1 downto 0);
type cache_walker_state_type is (IDLE, START_SPILLER, WAIT_ON_SPILLER);
signal cache_walker_state : cache_walker_state_type;
signal next_cache_walker_state : cache_walker_state_type;
signal cache_walker_start_to_spiller : std_logic;
begin
--Cache walking FSM. Note that this may add an extra cycle per line for
--spilling vs. integrating with the spiller FSM; done this way for
--simplicity and can be optimized later.
process (cache_walker_state, cache_walking, cache_walker_command, cache_walker_line_last, ready_from_spiller, done_from_spiller, spill_dirty_valid) is
begin
next_cache_walker_state <= cache_walker_state;
cache_walker_tag_update <= '0';
cache_walker_dirty_valid <= (others => '0');
done_from_cache_walker <= '0';
cache_walker_line_increment <= '0';
cache_walker_start_to_spiller <= '0';
case cache_walker_state is
when IDLE =>
if cache_walking = '1' then
case cache_walker_command is
when INITIALIZE =>
--Write every line until done
cache_walker_tag_update <= '1';
cache_walker_tag_valid <= '0';
cache_walker_line_increment <= '1';
if cache_walker_line_last = '1' then
done_from_cache_walker <= '1';
end if;
when others => --INVALIDATE/WRITEBACK/FLUSH
--Loading in line address to spill
next_cache_walker_state <= START_SPILLER;
end case;
end if;
when START_SPILLER =>
--Address loaded; wait for spiller to ack
cache_walker_start_to_spiller <= '1';
if ready_from_spiller = '1' then
next_cache_walker_state <= WAIT_ON_SPILLER;
end if;
when WAIT_ON_SPILLER =>
--Spiller FSM in progress
if done_from_spiller = '1' then
cache_walker_tag_update <= spill_region_hit;
if cache_walker_command = WRITEBACK then
--Set to clean, valid if previously valid
cache_walker_tag_valid <= spill_dirty_valid(0);
else
--FLUSH, set to invalid
cache_walker_tag_valid <= '0';
end if;
cache_walker_line_increment <= '1';
next_cache_walker_state <= IDLE;
if cache_walker_line_last = '1' then
done_from_cache_walker <= '1';
end if;
end if;
when others =>
null;
end case;
end process;
process (clk) is
begin
if rising_edge(clk) then
cache_walker_state <= next_cache_walker_state;
if reset = '1' then
cache_walker_state <= IDLE;
end if;
end if;
end process;
write_idle <= not spilling;
write_ready <= ready_from_spiller;
--In write-back mode writes and reads are all BEATS_PER_BURST
c_oimm_burstlength <= std_logic_vector(to_unsigned(BEATS_PER_BURST, c_oimm_burstlength'length));
c_oimm_burstlength_minus1 <=
std_logic_vector(to_unsigned(BEATS_PER_BURST-1, c_oimm_burstlength_minus1'length));
c_oimm_writedata <= spill_buffer_read_data;
c_oimm_byteenable <= (others => '1');
c_oimm_writelast <= spill_burst_last;
ready_from_filler <= ((not filling) or done_from_filler) and ready_from_spiller;
c_oimm_requestvalid <= fill_reading or spill_writing_to_memory;
c_oimm_readnotwrite <= fill_reading;
c_oimm_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) when fill_reading = '1' else
spill_tag;
c_oimm_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(read_lastline) when fill_reading = '1' else
std_logic_vector(spill_line);
multiple_bursts_per_line_address_gen : if BURSTS_PER_LINE > 1 generate
c_oimm_address(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BURST)) <=
std_logic_vector(fill_external_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BURST))) when
fill_reading = '1' else
std_logic_vector(spill_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BURST)));
end generate multiple_bursts_per_line_address_gen;
multiple_beats_per_burst_line_address_gen : if BEATS_PER_BURST > 1 generate
c_oimm_address(log2(BYTES_PER_BURST)-1 downto log2(BYTES_PER_BEAT)) <= (others => '0');
end generate multiple_beats_per_burst_line_address_gen;
read_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
spill_tag when spill_reading_into_buffer = '1' else
cacheint_oimm_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) when read_miss = '0' else
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE));
read_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(spill_line) when spill_reading_into_buffer = '1' else
std_logic_vector(cache_walker_line) when cache_walking = '1' else
cacheint_oimm_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) when read_miss = '0' else
std_logic_vector(read_lastline);
read_address(log2(LINE_SIZE)-1 downto 0) <=
std_logic_vector(spill_offset) when spill_reading_into_buffer = '1' else
cacheint_oimm_address(log2(LINE_SIZE)-1 downto 0) when read_miss = '0' else
read_lastaddress(log2(LINE_SIZE)-1 downto 0);
read_speculative <= '0';
done_to_write_on_hit <= read_readdatavalid;
write_hit_dirty_valid(write_hit_dirty_valid'left) <= '1';
--On a cacheline fill use the last address (which caused the miss). On a
--write hit, use the last address (which caused the hit). When spilling
--a line use the same tag so that the WRITEBACK command correctly sets
--the line to clean after writing it out to memory.
write_address(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE)) <=
spill_tag when cache_walking = '1' else
read_lastaddress(ADDRESS_WIDTH-1 downto log2(CACHE_SIZE));
write_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)) <=
std_logic_vector(cache_walker_line) when cache_walking = '1' else
std_logic_vector(read_lastline);
write_address(log2(LINE_SIZE)-1 downto 0) <=
std_logic_vector(fill_internal_offset) when read_miss = '1' else
read_lastaddress(log2(LINE_SIZE)-1 downto 0);
--------------------------------------------------------------------------
-- Cache Spiller FSM
--------------------------------------------------------------------------
start_to_spiller <= (start_to_filler and ready_from_filler) or cache_walker_start_to_spiller;
ready_from_spiller <= ((not spilling) or done_from_spiller);
done_from_spiller <= (spill_writing_to_memory and
(not c_oimm_waitrequest) and
(not fill_reading) and
spill_offset_last) or
spill_skipping;
process(clk)
begin
if rising_edge(clk) then
if done_from_spiller = '1' then
spilling <= '0';
spill_writing_to_memory <= '0';
spill_skipping <= '0';
end if;
if spill_offset_increment = '1' then
if spill_offset_last = '1' then
spill_reading_from_buffer <= spill_reading_into_buffer;
spill_reading_into_buffer <= '0';
end if;
if next_spill_offset_last = '1' then
if spill_reading_into_buffer = '0' then
spill_reading_from_buffer <= '0';
end if;
end if;
end if;
if spill_reading_from_buffer = '1' then
spill_writing_to_memory <= '1';
end if;
--Set spilling to indicate the line needs to be spilled
if start_to_spiller = '1' and ready_from_spiller = '1' then
spilling <= '1';
spill_tag <= read_tag;
spill_line <= unsigned(read_address(log2(CACHE_SIZE)-1 downto log2(LINE_SIZE)));
spill_dirty_valid <= read_dirty_valid;
spill_region_hit <= read_region_hit;
--Spill for real only if valid, within the region, dirty, and not
--invalidating (except partial cachelines, which must be flushed on
--invalidate).
--
--Note that INITIALIZE command does not call the spiller so we
--don't have to check for it here.
if (read_dirty_valid(0) = '1' and
read_dirty_valid(read_dirty_valid'left) = '1' and
(cache_walking = '0' or (read_region_hit = '1' and
(cache_walker_command /= INVALIDATE or read_region_hit_partial = '1')))) then
spill_reading_into_buffer <= '1';
else
spill_skipping <= '1';
end if;
end if;
if reset = '1' then
spilling <= '0';
spill_reading_into_buffer <= '0';
spill_reading_from_buffer <= '0';
spill_writing_to_memory <= '0';
spill_skipping <= '0';
end if;
end if;
end process;
spill_offset_increment <= spill_reading_into_buffer or
(spill_writing_to_memory and ((not c_oimm_waitrequest) and (not fill_reading)));
one_beat_per_line_offset_gen : if BEATS_PER_LINE = 1 generate
next_spill_offset <= to_unsigned(0, next_spill_offset'length);
spill_offset <= to_unsigned(0, spill_offset'length);
next_spill_offset_last <= '1';
spill_offset_last <= '1';
end generate one_beat_per_line_offset_gen;
multiple_beats_per_line_offset_gen : if BEATS_PER_LINE > 1 generate
next_spill_offset <=
spill_offset + to_unsigned(BYTES_PER_BEAT, spill_offset'length) when spill_offset_increment = '1' else
spill_offset;
next_spill_offset_last <= '1' when (next_spill_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT)) =
to_unsigned(BEATS_PER_LINE-1, log2(BEATS_PER_LINE))) else
'0';
process(clk)
begin
if rising_edge(clk) then
spill_offset <= next_spill_offset;
spill_offset_last <= next_spill_offset_last;
if reset = '1' then
spill_offset <= to_unsigned(0, spill_offset'length);
end if;
end if;
end process;
end generate multiple_beats_per_line_offset_gen;
one_beat_per_burst_gen : if BEATS_PER_BURST = 1 generate
spill_burst_last <= '1';
end generate one_beat_per_burst_gen;
multiple_beats_per_burst_gen : if BEATS_PER_BURST > 1 generate
spill_burst_last <= '1' when (spill_offset(log2(BYTES_PER_BURST)-1 downto log2(BYTES_PER_BEAT)) =
to_unsigned(BEATS_PER_BURST-1, log2(BEATS_PER_BURST))) else
'0';
end generate multiple_beats_per_burst_gen;
--------------------------------------------------------------------------
-- Spill Buffer
--------------------------------------------------------------------------
process (clk) is
begin
if rising_edge(clk) then
--Readdata comes back one cycle after fill address changes
spill_buffer_write_enable <= spill_offset_increment and spill_reading_into_buffer;
end if;
end process;
spill_buffer_write_data <= read_readdata;
one_beat_per_line_buffer_gen : if BEATS_PER_LINE = 1 generate
process (clk) is
begin
if rising_edge(clk) then
if spill_buffer_write_enable = '1' then
spill_buffer_read_data <= spill_buffer_write_data;
end if;
end if;
end process;
end generate one_beat_per_line_buffer_gen;
multiple_beats_per_line_buffer_gen : if BEATS_PER_LINE > 1 generate
signal spill_buffer_read_address : unsigned(log2(BEATS_PER_LINE)-1 downto 0);
signal spill_buffer_write_address : unsigned(log2(BEATS_PER_LINE)-1 downto 0);
begin
process (clk) is
begin
if rising_edge(clk) then
--Readdata comes back one cycle after fill address changes
spill_buffer_write_address <= spill_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT));
end if;
end process;
spill_buffer_read_address <= next_spill_offset(log2(LINE_SIZE)-1 downto log2(BYTES_PER_BEAT));
spill_buffer : bram_sdp_write_first
generic map (
DEPTH => BEATS_PER_LINE,
WIDTH => EXTERNAL_WIDTH,
WRITE_FIRST_SUPPORTED => WRITE_FIRST_SUPPORTED
)
port map (
clk => clk,
read_address => spill_buffer_read_address,
read_data => spill_buffer_read_data,
write_address => spill_buffer_write_address,
write_enable => spill_buffer_write_enable,
write_data => spill_buffer_write_data
);
end generate multiple_beats_per_line_buffer_gen;
end generate writeback_gen;
end generate not_read_only_gen;
------------------------------------------------------------------------------
-- Assertions
------------------------------------------------------------------------------
assert (CACHE_SIZE mod LINE_SIZE) = 0
report "Error in cache: CACHE_SIZE (" &
integer'image(CACHE_SIZE) &
") must be an even mulitple of LINE_SIZE (" &
integer'image(LINE_SIZE) &
")."
severity failure;
assert 2**log2(CACHE_SIZE) = CACHE_SIZE
report "Error in cache: CACHE_SIZE (" &
integer'image(CACHE_SIZE) &
") must be a power of 2."
severity failure;
assert EXTERNAL_WIDTH >= INTERNAL_WIDTH
report "Error in cache: EXTERNAL_WIDTH (" &
integer'image(EXTERNAL_WIDTH) &
") must be greater than or equal to INTERNAL_WIDTH (" &
integer'image(INTERNAL_WIDTH) &
")."
severity failure;
--pragma translate_off
-------------------------------------------------------------------------------
-- Simulation debug
-------------------------------------------------------------------------------
process(clk)
begin
if rising_edge(clk) then
if reset = '0' then
assert write_hit /= '1' or cache_mgt_tag_update /= '1' report "Multiple simultaneous tag updates" severity failure;
end if;
end if;
end process;
--pragma translate_on
end architecture;
|
entity record32 is
end entity;
architecture test of record32 is
type rec1 is record
f1 : integer_vector;
end record;
type rec2 is record
r : rec1;
f2 : integer_vector;
end record;
signal s : rec2(f2(1 to 3), r(f1(2 to 5)));
begin
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3041.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p01n02i03041ent IS
END c12s02b02x00p01n02i03041ent;
ARCHITECTURE c12s02b02x00p01n02i03041arch OF c12s02b02x00p01n02i03041ent IS
type c_a is array(integer range <>) of integer;
type c_r is
record
i : integer;
r : real;
b : bit;
end record;
BEGIN
-- test for first associations
bl2 : block
generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
generic map(i=>(5,5,5));
begin
assert ((i(1)=5) and (i(2)=5) and (i(3)=5))
report "Generic map value for array generic not correct"
severity failure;
assert ((r.i=10) and (r.r=3.4) and (r.b='1'))
report "Default value for record generic not correct"
severity failure;
assert NOT((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
report "***PASSED TEST: c12s02b02x00p01n02i03041"
severity NOTE;
assert ((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
report "***FAILED TEST: c12s02b02x00p01n02i03041 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03041arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3041.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p01n02i03041ent IS
END c12s02b02x00p01n02i03041ent;
ARCHITECTURE c12s02b02x00p01n02i03041arch OF c12s02b02x00p01n02i03041ent IS
type c_a is array(integer range <>) of integer;
type c_r is
record
i : integer;
r : real;
b : bit;
end record;
BEGIN
-- test for first associations
bl2 : block
generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
generic map(i=>(5,5,5));
begin
assert ((i(1)=5) and (i(2)=5) and (i(3)=5))
report "Generic map value for array generic not correct"
severity failure;
assert ((r.i=10) and (r.r=3.4) and (r.b='1'))
report "Default value for record generic not correct"
severity failure;
assert NOT((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
report "***PASSED TEST: c12s02b02x00p01n02i03041"
severity NOTE;
assert ((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
report "***FAILED TEST: c12s02b02x00p01n02i03041 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03041arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc3041.vhd,v 1.2 2001-10-26 16:29:51 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c12s02b02x00p01n02i03041ent IS
END c12s02b02x00p01n02i03041ent;
ARCHITECTURE c12s02b02x00p01n02i03041arch OF c12s02b02x00p01n02i03041ent IS
type c_a is array(integer range <>) of integer;
type c_r is
record
i : integer;
r : real;
b : bit;
end record;
BEGIN
-- test for first associations
bl2 : block
generic(i:c_a(1 to 3):=(10,10,10); r:c_r:=(10,3.4,'1'));
generic map(i=>(5,5,5));
begin
assert ((i(1)=5) and (i(2)=5) and (i(3)=5))
report "Generic map value for array generic not correct"
severity failure;
assert ((r.i=10) and (r.r=3.4) and (r.b='1'))
report "Default value for record generic not correct"
severity failure;
assert NOT((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
report "***PASSED TEST: c12s02b02x00p01n02i03041"
severity NOTE;
assert ((i(1)=5) and (i(2)=5) and (i(3)=5) and (r.i=10) and (r.r=3.4) and (r.b='1'))
report "***FAILED TEST: c12s02b02x00p01n02i03041 - The actual part of an implicit association element is the default expression test failed."
severity ERROR;
end block;
END c12s02b02x00p01n02i03041arch;
|
-------------------------------------------------------------------------------
-- Company : HSLU
-- Engineer : Gai, Waj
--
-- Create Date: 05-Apr-11, 21-Mar-14
-- Project : RT Video Lab 1: Exercise 1
-- Description: 5-tap FIR filter in direct form
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
entity fir_1d_dir is
generic
(IN_DW : integer := 8; -- Input word width
OUT_DW : integer := 19; -- Output word width
COEF_DW : integer := 7; -- coefficient word width
TAPS : integer := 5; -- # of taps + 1 input register
DELAY : integer := 8); -- output delay line
-- (to adapt latency to system architecture)
port
(ce_1 : in std_logic; -- clock enable
clk_1 : in std_logic; -- clock
load : in std_logic; -- load coeff pulse
coef : in std_logic_vector(COEF_DW-1 downto 0);
din : in std_logic_vector(IN_DW-1 downto 0);
out_data : out std_logic_vector(OUT_DW-1 downto 0)
);
end fir_1d_dir;
architecture Behavioral of fir_1d_dir is
-- type declarations
type STAGE_TYPE is array(TAPS-1 downto 0) of signed(IN_DW-1 downto 0);
type DELAY_TYPE is array(DELAY downto 0) of signed(IN_DW-1 downto 0);
type COEFF_TYPE is array(TAPS-1 downto 0) of signed(COEF_DW-1 downto 0);
-- signal declarations (init values for simulation only!!!)
signal stage : STAGE_TYPE := (others => (others => '0'));
signal del_line : DELAY_TYPE := (others => (others => '0'));
-- constant declarations
constant C_coef : COEFF_TYPE := (to_signed(2, COEF_DW), -- b4
to_signed(4, COEF_DW), -- b3
to_signed(8, COEF_DW), -- b2
to_signed(4, COEF_DW), -- b1
to_signed(2, COEF_DW)); -- b0
constant C_ext : signed(OUT_DW-IN_DW-COEF_DW-1 downto 0) := (others => '0');
begin
-- sequential process (without reset, because SysGen uses FIR-Compiler without
-- reset signal)
p0_FIR : process(clk_1)
variable v_filt : signed(OUT_DW-1 downto 0);
begin
if rising_edge(clk_1) then
if ce_1 = '1' then
-- input delay line
del_line(DELAY) <= signed(din);
del_line(DELAY-1 downto 0) <= del_line(DELAY downto 1);
-- shift tap delay line
stage(0) <= del_line(0);
stage(TAPS-1 downto 1) <= stage(TAPS-2 downto 0);
-- compute filter taps
v_filt := (C_ext & stage(0)) * C_coef(0);
for k in 1 to TAPS-1 loop
v_filt := ((C_ext & stage(k)) * C_coef(k)) + v_filt;
end loop;
-- output register
out_data <= std_logic_vector(v_filt);
end if;
end if;
end process;
end Behavioral;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity JK_FF is
port( T: in std_logic;
Reset: in std_logic;
Clock_enable: in std_logic;
Clock: in std_logic;
Output: out std_logic);
end JK_FF;
architecture Behavioral of JK_FF is
signal temp: std_logic;
begin
process (Clock)
begin
if (Clock'event and Clock='0') then
if Reset='1' then
temp <= '0' after 6ns;
elsif Clock_enable ='1' then
if T='0' then
temp <= temp after 10ns;
elsif T='1' then
temp <= not (temp) after 10ns;
end if;
end if;
end if;
end process;
Output <= temp;
end Behavioral; |
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_06.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_06 is
end entity ch_07_06;
library bv_utilities;
use bv_utilities.bv_arithmetic;
architecture test of ch_07_06 is
begin
process_07_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv_arithmetic."+"(left, right);
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bv_arithmetic."-"(right);
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_07_5_b;
end architecture test;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_06.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_06 is
end entity ch_07_06;
library bv_utilities;
use bv_utilities.bv_arithmetic;
architecture test of ch_07_06 is
begin
process_07_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv_arithmetic."+"(left, right);
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bv_arithmetic."-"(right);
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_07_5_b;
end architecture test;
|
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