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-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_07_ch_07_06.vhd,v 1.3 2001-10-26 16:29:34 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
entity ch_07_06 is
end entity ch_07_06;
library bv_utilities;
use bv_utilities.bv_arithmetic;
architecture test of ch_07_06 is
begin
process_07_5_b : process is
-- code from book:
function "+" ( left, right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
return bv_arithmetic."+"(left, right);
-- end not in book
end function "+";
variable addr_reg : bit_vector(31 downto 0);
-- . . .
-- end of code from book
-- code from book:
function "abs" ( right : in bit_vector ) return bit_vector is
begin
-- . . .
-- not in book
if right(right'left) = '0' then
return right;
else
return bv_arithmetic."-"(right);
end if;
-- end not in book
end function "abs";
variable accumulator : bit_vector(31 downto 0);
-- . . .
-- end of code from book
begin
-- code from book:
addr_reg := addr_reg + X"0000_0004";
-- end of code from book
accumulator := X"000000FF";
-- code from book:
accumulator := abs accumulator;
-- end of code from book
accumulator := X"FFFFFFFE";
accumulator := abs accumulator;
wait;
end process process_07_5_b;
end architecture test;
|
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
-- --
-- This file is part of the DE0 Nano Linux project --
-- http://www.de0nanolinux.com --
-- --
-- Author(s): --
-- - Helmut, [email protected] --
-- --
-----------------------------------------------------------------------------
-- --
-- Copyright (C) 2015 Authors and www.de0nanolinux.com --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
-- --
-----------------------------------------------------------------------------
-----------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package global is
---------------------------------------------------------------------
-- Functions
---------------------------------------------------------------------
function log_dualis(number : natural) return natural;
end global;
package body global is
---------------------------------------------------------------------
-- returns the logarithm of base 2
function log_dualis(number : natural) return natural is
variable needed_bits : natural := 0;
variable running_bit : natural := 1;
begin
while running_bit < number loop
needed_bits := needed_bits + 1;
running_bit := running_bit * 2;
end loop;
return needed_bits;
end log_dualis;
---------------------------------------------------------------------
end global;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-12.08:57:10)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY hal_asap_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END hal_asap_entity;
ARCHITECTURE hal_asap_description OF hal_asap_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 + 1;
register2 := input2 * 2;
register3 := input3 * 3;
register4 := input4 * 4;
register5 := input5 * 5;
WHEN "00000010" =>
IF (register1 < 6) THEN
output1 <= register1;
ELSE
output1 <= "00110";
END IF;
register1 := register2 * register3;
register2 := register4 * 8;
output2 <= register5 + 9;
WHEN "00000011" =>
register1 := register1 - 11;
WHEN "00000100" =>
output3 <= register1 - register2;
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END hal_asap_description; |
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.centralRouter_package.all;
--! a wrap for 8b10b decoder
entity dec_8b10_wrap is
port (
RESET : in std_logic;
RBYTECLK : in std_logic;
ABCDEIFGHJ_IN : in std_logic_vector (9 downto 0);
HGFEDCBA : out std_logic_vector (7 downto 0);
ISK : out std_logic_vector (1 downto 0);
BUSY : out std_logic
);
end dec_8b10_wrap;
architecture Behavioral of dec_8b10_wrap is
----------------------------------
----------------------------------
COMPONENT dec_8b10b
PORT(
RESET : IN std_logic;
RBYTECLK : IN std_logic;
AI : IN std_logic;
BI : IN std_logic;
CI : IN std_logic;
DI : IN std_logic;
EI : IN std_logic;
II : IN std_logic;
FI : IN std_logic;
GI : IN std_logic;
HI : IN std_logic;
JI : IN std_logic;
KO : OUT std_logic;
HO : OUT std_logic;
GO : OUT std_logic;
FO : OUT std_logic;
EO : OUT std_logic;
DO : OUT std_logic;
CO : OUT std_logic;
BO : OUT std_logic;
AO : OUT std_logic
);
END COMPONENT;
----------------------------------
----------------------------------
signal ISK_falling_edge : std_logic;
signal BUSY_s : std_logic := '0';
signal HGFEDCBA_falling_edge : std_logic_vector(7 downto 0);
signal HGFEDCBA_sig : std_logic_vector(7 downto 0) := (others => '0');
signal ISKcode : std_logic_vector(1 downto 0);
signal ISK_sig : std_logic_vector(1 downto 0) := (others => '0');
signal ISK_comma, ISK_soc, ISK_eoc, ISK_sob, ISK_eob : std_logic;
begin
-- 8b10b decoder
dec_8b10b_INST: dec_8b10b
PORT MAP(
RESET => RESET,
RBYTECLK => RBYTECLK,
AI => ABCDEIFGHJ_IN(9),
BI => ABCDEIFGHJ_IN(8),
CI => ABCDEIFGHJ_IN(7),
DI => ABCDEIFGHJ_IN(6),
EI => ABCDEIFGHJ_IN(5),
II => ABCDEIFGHJ_IN(4),
FI => ABCDEIFGHJ_IN(3),
GI => ABCDEIFGHJ_IN(2),
HI => ABCDEIFGHJ_IN(1),
JI => ABCDEIFGHJ_IN(0),
KO => ISK_falling_edge,
HO => HGFEDCBA_falling_edge(7),
GO => HGFEDCBA_falling_edge(6),
FO => HGFEDCBA_falling_edge(5),
EO => HGFEDCBA_falling_edge(4),
DO => HGFEDCBA_falling_edge(3),
CO => HGFEDCBA_falling_edge(2),
BO => HGFEDCBA_falling_edge(1),
AO => HGFEDCBA_falling_edge(0)
);
------------------------------------------------------------------------------------------------------
ISK_comma <= '1' when (ABCDEIFGHJ_IN = COMMAp or ABCDEIFGHJ_IN = COMMAn) else '0';
ISK_soc <= '1' when (ABCDEIFGHJ_IN = SOCp or ABCDEIFGHJ_IN = SOCn) else '0';
ISK_eoc <= '1' when (ABCDEIFGHJ_IN = EOCp or ABCDEIFGHJ_IN = EOCn) else '0';
ISK_sob <= '1' when (ABCDEIFGHJ_IN = SOBp or ABCDEIFGHJ_IN = SOBn) else '0';
ISK_eob <= '1' when (ABCDEIFGHJ_IN = EOBp or ABCDEIFGHJ_IN = EOBn) else '0';
---
ISKcode(0) <= ((not ISK_soc) and (ISK_eoc xor ISK_comma)) or ISK_sob or ISK_eob;
ISKcode(1) <= ((not ISK_eoc) and (ISK_soc xor ISK_comma)) or ISK_sob or ISK_eob;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_falling_edge = '1' then
ISK_sig <= ISKcode;
else
ISK_sig <= "00";
end if;
end if;
end process;
--
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
HGFEDCBA_sig <= HGFEDCBA_falling_edge;
end if;
end process;
------------------------------------------------------------------------------------------------------
ISK <= ISK_sig;
HGFEDCBA <= HGFEDCBA_sig;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_sob = '1' then
BUSY_s <= '1';
elsif ISK_eob = '1' then
BUSY_s <= '0';
end if;
end if;
end process;
--
BUSY <= BUSY_s;
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.centralRouter_package.all;
--! a wrap for 8b10b decoder
entity dec_8b10_wrap is
port (
RESET : in std_logic;
RBYTECLK : in std_logic;
ABCDEIFGHJ_IN : in std_logic_vector (9 downto 0);
HGFEDCBA : out std_logic_vector (7 downto 0);
ISK : out std_logic_vector (1 downto 0);
BUSY : out std_logic
);
end dec_8b10_wrap;
architecture Behavioral of dec_8b10_wrap is
----------------------------------
----------------------------------
COMPONENT dec_8b10b
PORT(
RESET : IN std_logic;
RBYTECLK : IN std_logic;
AI : IN std_logic;
BI : IN std_logic;
CI : IN std_logic;
DI : IN std_logic;
EI : IN std_logic;
II : IN std_logic;
FI : IN std_logic;
GI : IN std_logic;
HI : IN std_logic;
JI : IN std_logic;
KO : OUT std_logic;
HO : OUT std_logic;
GO : OUT std_logic;
FO : OUT std_logic;
EO : OUT std_logic;
DO : OUT std_logic;
CO : OUT std_logic;
BO : OUT std_logic;
AO : OUT std_logic
);
END COMPONENT;
----------------------------------
----------------------------------
signal ISK_falling_edge : std_logic;
signal BUSY_s : std_logic := '0';
signal HGFEDCBA_falling_edge : std_logic_vector(7 downto 0);
signal HGFEDCBA_sig : std_logic_vector(7 downto 0) := (others => '0');
signal ISKcode : std_logic_vector(1 downto 0);
signal ISK_sig : std_logic_vector(1 downto 0) := (others => '0');
signal ISK_comma, ISK_soc, ISK_eoc, ISK_sob, ISK_eob : std_logic;
begin
-- 8b10b decoder
dec_8b10b_INST: dec_8b10b
PORT MAP(
RESET => RESET,
RBYTECLK => RBYTECLK,
AI => ABCDEIFGHJ_IN(9),
BI => ABCDEIFGHJ_IN(8),
CI => ABCDEIFGHJ_IN(7),
DI => ABCDEIFGHJ_IN(6),
EI => ABCDEIFGHJ_IN(5),
II => ABCDEIFGHJ_IN(4),
FI => ABCDEIFGHJ_IN(3),
GI => ABCDEIFGHJ_IN(2),
HI => ABCDEIFGHJ_IN(1),
JI => ABCDEIFGHJ_IN(0),
KO => ISK_falling_edge,
HO => HGFEDCBA_falling_edge(7),
GO => HGFEDCBA_falling_edge(6),
FO => HGFEDCBA_falling_edge(5),
EO => HGFEDCBA_falling_edge(4),
DO => HGFEDCBA_falling_edge(3),
CO => HGFEDCBA_falling_edge(2),
BO => HGFEDCBA_falling_edge(1),
AO => HGFEDCBA_falling_edge(0)
);
------------------------------------------------------------------------------------------------------
ISK_comma <= '1' when (ABCDEIFGHJ_IN = COMMAp or ABCDEIFGHJ_IN = COMMAn) else '0';
ISK_soc <= '1' when (ABCDEIFGHJ_IN = SOCp or ABCDEIFGHJ_IN = SOCn) else '0';
ISK_eoc <= '1' when (ABCDEIFGHJ_IN = EOCp or ABCDEIFGHJ_IN = EOCn) else '0';
ISK_sob <= '1' when (ABCDEIFGHJ_IN = SOBp or ABCDEIFGHJ_IN = SOBn) else '0';
ISK_eob <= '1' when (ABCDEIFGHJ_IN = EOBp or ABCDEIFGHJ_IN = EOBn) else '0';
---
ISKcode(0) <= ((not ISK_soc) and (ISK_eoc xor ISK_comma)) or ISK_sob or ISK_eob;
ISKcode(1) <= ((not ISK_eoc) and (ISK_soc xor ISK_comma)) or ISK_sob or ISK_eob;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_falling_edge = '1' then
ISK_sig <= ISKcode;
else
ISK_sig <= "00";
end if;
end if;
end process;
--
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
HGFEDCBA_sig <= HGFEDCBA_falling_edge;
end if;
end process;
------------------------------------------------------------------------------------------------------
ISK <= ISK_sig;
HGFEDCBA <= HGFEDCBA_sig;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_sob = '1' then
BUSY_s <= '1';
elsif ISK_eob = '1' then
BUSY_s <= '0';
end if;
end if;
end process;
--
BUSY <= BUSY_s;
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.centralRouter_package.all;
--! a wrap for 8b10b decoder
entity dec_8b10_wrap is
port (
RESET : in std_logic;
RBYTECLK : in std_logic;
ABCDEIFGHJ_IN : in std_logic_vector (9 downto 0);
HGFEDCBA : out std_logic_vector (7 downto 0);
ISK : out std_logic_vector (1 downto 0);
BUSY : out std_logic
);
end dec_8b10_wrap;
architecture Behavioral of dec_8b10_wrap is
----------------------------------
----------------------------------
COMPONENT dec_8b10b
PORT(
RESET : IN std_logic;
RBYTECLK : IN std_logic;
AI : IN std_logic;
BI : IN std_logic;
CI : IN std_logic;
DI : IN std_logic;
EI : IN std_logic;
II : IN std_logic;
FI : IN std_logic;
GI : IN std_logic;
HI : IN std_logic;
JI : IN std_logic;
KO : OUT std_logic;
HO : OUT std_logic;
GO : OUT std_logic;
FO : OUT std_logic;
EO : OUT std_logic;
DO : OUT std_logic;
CO : OUT std_logic;
BO : OUT std_logic;
AO : OUT std_logic
);
END COMPONENT;
----------------------------------
----------------------------------
signal ISK_falling_edge : std_logic;
signal BUSY_s : std_logic := '0';
signal HGFEDCBA_falling_edge : std_logic_vector(7 downto 0);
signal HGFEDCBA_sig : std_logic_vector(7 downto 0) := (others => '0');
signal ISKcode : std_logic_vector(1 downto 0);
signal ISK_sig : std_logic_vector(1 downto 0) := (others => '0');
signal ISK_comma, ISK_soc, ISK_eoc, ISK_sob, ISK_eob : std_logic;
begin
-- 8b10b decoder
dec_8b10b_INST: dec_8b10b
PORT MAP(
RESET => RESET,
RBYTECLK => RBYTECLK,
AI => ABCDEIFGHJ_IN(9),
BI => ABCDEIFGHJ_IN(8),
CI => ABCDEIFGHJ_IN(7),
DI => ABCDEIFGHJ_IN(6),
EI => ABCDEIFGHJ_IN(5),
II => ABCDEIFGHJ_IN(4),
FI => ABCDEIFGHJ_IN(3),
GI => ABCDEIFGHJ_IN(2),
HI => ABCDEIFGHJ_IN(1),
JI => ABCDEIFGHJ_IN(0),
KO => ISK_falling_edge,
HO => HGFEDCBA_falling_edge(7),
GO => HGFEDCBA_falling_edge(6),
FO => HGFEDCBA_falling_edge(5),
EO => HGFEDCBA_falling_edge(4),
DO => HGFEDCBA_falling_edge(3),
CO => HGFEDCBA_falling_edge(2),
BO => HGFEDCBA_falling_edge(1),
AO => HGFEDCBA_falling_edge(0)
);
------------------------------------------------------------------------------------------------------
ISK_comma <= '1' when (ABCDEIFGHJ_IN = COMMAp or ABCDEIFGHJ_IN = COMMAn) else '0';
ISK_soc <= '1' when (ABCDEIFGHJ_IN = SOCp or ABCDEIFGHJ_IN = SOCn) else '0';
ISK_eoc <= '1' when (ABCDEIFGHJ_IN = EOCp or ABCDEIFGHJ_IN = EOCn) else '0';
ISK_sob <= '1' when (ABCDEIFGHJ_IN = SOBp or ABCDEIFGHJ_IN = SOBn) else '0';
ISK_eob <= '1' when (ABCDEIFGHJ_IN = EOBp or ABCDEIFGHJ_IN = EOBn) else '0';
---
ISKcode(0) <= ((not ISK_soc) and (ISK_eoc xor ISK_comma)) or ISK_sob or ISK_eob;
ISKcode(1) <= ((not ISK_eoc) and (ISK_soc xor ISK_comma)) or ISK_sob or ISK_eob;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_falling_edge = '1' then
ISK_sig <= ISKcode;
else
ISK_sig <= "00";
end if;
end if;
end process;
--
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
HGFEDCBA_sig <= HGFEDCBA_falling_edge;
end if;
end process;
------------------------------------------------------------------------------------------------------
ISK <= ISK_sig;
HGFEDCBA <= HGFEDCBA_sig;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_sob = '1' then
BUSY_s <= '1';
elsif ISK_eob = '1' then
BUSY_s <= '0';
end if;
end if;
end process;
--
BUSY <= BUSY_s;
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 06/19/2014
--! Module Name: dec_8b10_wrap
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.centralRouter_package.all;
--! a wrap for 8b10b decoder
entity dec_8b10_wrap is
port (
RESET : in std_logic;
RBYTECLK : in std_logic;
ABCDEIFGHJ_IN : in std_logic_vector (9 downto 0);
HGFEDCBA : out std_logic_vector (7 downto 0);
ISK : out std_logic_vector (1 downto 0);
BUSY : out std_logic
);
end dec_8b10_wrap;
architecture Behavioral of dec_8b10_wrap is
----------------------------------
----------------------------------
COMPONENT dec_8b10b
PORT(
RESET : IN std_logic;
RBYTECLK : IN std_logic;
AI : IN std_logic;
BI : IN std_logic;
CI : IN std_logic;
DI : IN std_logic;
EI : IN std_logic;
II : IN std_logic;
FI : IN std_logic;
GI : IN std_logic;
HI : IN std_logic;
JI : IN std_logic;
KO : OUT std_logic;
HO : OUT std_logic;
GO : OUT std_logic;
FO : OUT std_logic;
EO : OUT std_logic;
DO : OUT std_logic;
CO : OUT std_logic;
BO : OUT std_logic;
AO : OUT std_logic
);
END COMPONENT;
----------------------------------
----------------------------------
signal ISK_falling_edge : std_logic;
signal BUSY_s : std_logic := '0';
signal HGFEDCBA_falling_edge : std_logic_vector(7 downto 0);
signal HGFEDCBA_sig : std_logic_vector(7 downto 0) := (others => '0');
signal ISKcode : std_logic_vector(1 downto 0);
signal ISK_sig : std_logic_vector(1 downto 0) := (others => '0');
signal ISK_comma, ISK_soc, ISK_eoc, ISK_sob, ISK_eob : std_logic;
begin
-- 8b10b decoder
dec_8b10b_INST: dec_8b10b
PORT MAP(
RESET => RESET,
RBYTECLK => RBYTECLK,
AI => ABCDEIFGHJ_IN(9),
BI => ABCDEIFGHJ_IN(8),
CI => ABCDEIFGHJ_IN(7),
DI => ABCDEIFGHJ_IN(6),
EI => ABCDEIFGHJ_IN(5),
II => ABCDEIFGHJ_IN(4),
FI => ABCDEIFGHJ_IN(3),
GI => ABCDEIFGHJ_IN(2),
HI => ABCDEIFGHJ_IN(1),
JI => ABCDEIFGHJ_IN(0),
KO => ISK_falling_edge,
HO => HGFEDCBA_falling_edge(7),
GO => HGFEDCBA_falling_edge(6),
FO => HGFEDCBA_falling_edge(5),
EO => HGFEDCBA_falling_edge(4),
DO => HGFEDCBA_falling_edge(3),
CO => HGFEDCBA_falling_edge(2),
BO => HGFEDCBA_falling_edge(1),
AO => HGFEDCBA_falling_edge(0)
);
------------------------------------------------------------------------------------------------------
ISK_comma <= '1' when (ABCDEIFGHJ_IN = COMMAp or ABCDEIFGHJ_IN = COMMAn) else '0';
ISK_soc <= '1' when (ABCDEIFGHJ_IN = SOCp or ABCDEIFGHJ_IN = SOCn) else '0';
ISK_eoc <= '1' when (ABCDEIFGHJ_IN = EOCp or ABCDEIFGHJ_IN = EOCn) else '0';
ISK_sob <= '1' when (ABCDEIFGHJ_IN = SOBp or ABCDEIFGHJ_IN = SOBn) else '0';
ISK_eob <= '1' when (ABCDEIFGHJ_IN = EOBp or ABCDEIFGHJ_IN = EOBn) else '0';
---
ISKcode(0) <= ((not ISK_soc) and (ISK_eoc xor ISK_comma)) or ISK_sob or ISK_eob;
ISKcode(1) <= ((not ISK_eoc) and (ISK_soc xor ISK_comma)) or ISK_sob or ISK_eob;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_falling_edge = '1' then
ISK_sig <= ISKcode;
else
ISK_sig <= "00";
end if;
end if;
end process;
--
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
HGFEDCBA_sig <= HGFEDCBA_falling_edge;
end if;
end process;
------------------------------------------------------------------------------------------------------
ISK <= ISK_sig;
HGFEDCBA <= HGFEDCBA_sig;
------------------------------------------------------------------------------------------------------
process(RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '1' then
if ISK_sob = '1' then
BUSY_s <= '1';
elsif ISK_eob = '1' then
BUSY_s <= '0';
end if;
end if;
end process;
--
BUSY <= BUSY_s;
--
end Behavioral;
|
-----------------------------------------------------------
--------- AUTOGENERATED FILE, DO NOT EDIT -----------------
-----------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
entity tute3 is port(
clk_clk, clk_reset_n: in std_ulogic;
iwrite0: in std_ulogic; -- reg
iwdata0: in u8; -- reg
iaddr0: in u8; -- reg
iaddr1: in u8; -- reg
r0: out u8; -- WIRE
r1: out u8; -- WIRE
r2: out u8; -- WIRE
r3: out u8 -- WIRE
);
end entity;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.desilog.all;
--#------- tute3 ------------------------------------
architecture rtl of tute3 is
----- internal regs/wires/etc --------
signal dg_c_iwrite0: std_ulogic;
signal dg_c_iwdata0: u8;
signal dg_c_iaddr0: u8;
signal dg_c_iaddr1: u8;
signal dg_w_r0: u8;
signal dg_w_r1: u8;
signal dg_w_r2: u8;
signal dg_w_r3: u8;
---- internal signals for RAM mem -------------
signal mem_data0: u8;
signal mem_data1: u8;
signal mem_addr0: u8;
signal mem_addr1: u8;
signal mem_wdata0: u8;
signal mem_wdata1: u8 := X"00"; -- WARNING: unwritten RAM input
signal mem_write0: std_ulogic;
signal mem_write1: std_ulogic := '0'; -- WARNING: unwritten RAM input
---- internal signals for RAM solo_ram -------------
signal solo_ram_data0: u8;
signal solo_ram_addr0: u8;
signal solo_ram_wdata0: u8;
signal solo_ram_write0: std_ulogic;
---- internal signals for ROM mrom -------------
signal mrom_data0: u8;
signal mrom_addr0: u8;
type mrom_romtype is array(0 to 255) of u8;
signal mrom_romdata : mrom_romtype := (
X"01",X"02",X"03",X"04",X"05",X"06",X"07",X"08",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00",
X"00",X"00",X"00",X"00",X"00",X"00",X"00",X"00"
);
begin
main: process (all)
begin
dg_w_r0 <= X"00"; -- wire pre-zero-init
dg_w_r1 <= X"00"; -- wire pre-zero-init
dg_w_r2 <= X"00"; -- wire pre-zero-init
dg_w_r3 <= X"00"; -- wire pre-zero-init
mem_addr0 <= X"00"; -- wire pre-zero-init
mem_addr1 <= X"00"; -- wire pre-zero-init
mem_wdata0 <= X"00"; -- wire pre-zero-init
mem_write0 <= '0'; -- wire pre-zero-init
solo_ram_addr0 <= X"00"; -- wire pre-zero-init
solo_ram_wdata0 <= X"00"; -- wire pre-zero-init
solo_ram_write0 <= '0'; -- wire pre-zero-init
mrom_addr0 <= X"00"; -- wire pre-zero-init
mem_addr0 <= iaddr0;
mem_wdata0 <= iwdata0;
mem_write0 <= iwrite0;
mem_addr1 <= X"04";
solo_ram_addr0 <= (iaddr0 + 5);
solo_ram_wdata0 <= (iwdata0 + 1);
solo_ram_write0 <= iwrite0;
mrom_addr0 <= iaddr0;
dg_w_r0 <= mem_data0;
dg_w_r1 <= mem_data1;
dg_w_r2 <= (solo_ram_data0 + 1);
dg_w_r3 <= mrom_data0;
end process;
----[ sync clock pump for clk ]------
process begin
wait until rising_edge(clk_clk);
end process;
mem: entity work.dg_sys_ram_dual_sync generic map(DATA_BITS=> 8, ADDR_BITS=>8)
port map(clk_clk, mem_write0, mem_addr0, mem_wdata0, mem_data0, clk_clk, mem_write1, mem_addr1, mem_wdata1, mem_data1);
solo_ram: entity work.dg_sys_ram_mono_sync generic map(DATA_BITS=> 8, ADDR_BITS=>8)
port map(clk_clk, solo_ram_write0, solo_ram_addr0, solo_ram_wdata0, solo_ram_data0);
process -- ROM pump for mrom
variable rv_addr0 : u8;
begin
wait until rising_edge(clk_clk);
mrom_data0 <= mrom_romdata(to_integer(rv_addr0));
rv_addr0 := mrom_addr0;
end process;
------[ output registers/wires/latches ] --------------
r0 <= dg_w_r0;
r1 <= dg_w_r1;
r2 <= dg_w_r2;
r3 <= dg_w_r3;
end;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
-- ***************************************************************************
-- ***************************************************************************
-- Copyright 2013(c) Analog Devices, Inc.
-- Author: Lars-Peter Clausen <[email protected]>
--
-- All rights reserved.
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
-- - Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- - Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- - Neither the name of Analog Devices, Inc. nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
-- - The use of this software may or may not infringe the patent rights
-- of one or more patent holders. This license does not release you
-- from the requirement that you obtain separate licenses from these
-- patent holders to use this software.
-- - Use of the software either in source or binary form, must be run
-- on or directly connected to an Analog Devices Inc. component.
--
-- THIS SOFTWARE IS PROVIDED BY ANALOG DEVICES "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
-- INCLUDING, BUT NOT LIMITED TO, NON-INFRINGEMENT, MERCHANTABILITY AND FITNESS FOR A
-- PARTICULAR PURPOSE ARE DISCLAIMED.
--
-- IN NO EVENT SHALL ANALOG DEVICES BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
-- EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, INTELLECTUAL PROPERTY
-- RIGHTS, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
-- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-- STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF
-- THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-- ***************************************************************************
-- ***************************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity i2s_clkgen is
port(
clk : in std_logic; -- System clock
resetn : in std_logic; -- System reset
enable : in Boolean ; -- Enable clockgen
tick : in std_logic;
bclk_div_rate : in natural range 0 to 255;
lrclk_div_rate : in natural range 0 to 255;
bclk : out std_logic; -- Bit Clock
lrclk : out std_logic; -- Frame Clock
channel_sync : out std_logic;
frame_sync : out std_logic
);
end i2s_clkgen;
architecture Behavioral of i2s_clkgen is
signal reset_int : Boolean;
signal prev_bclk_div_rate : natural range 0 to 255;
signal prev_lrclk_div_rate : natural range 0 to 255;
signal bclk_count : natural range 0 to 255;
signal lrclk_count : natural range 0 to 255;
signal bclk_int : std_logic;
signal lrclk_int : std_logic;
signal lrclk_tick : Boolean;
begin
reset_int <= resetn = '0' or not enable;
bclk <= bclk_int;
lrclk <= lrclk_int;
-----------------------------------------------------------------------------------
-- Serial clock generation BCLK_O
-----------------------------------------------------------------------------------
bclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_bclk_div_rate <= bclk_div_rate;
if reset_int then -- or (bclk_div_rate /= prev_bclk_div_rate) then
bclk_int <= '1';
bclk_count <= bclk_div_rate;
else
if tick = '1' then
if bclk_count = bclk_div_rate then
bclk_count <= 0;
bclk_int <= not bclk_int;
else
bclk_count <= bclk_count + 1;
end if;
end if;
end if;
end if;
end process bclk_gen;
lrclk_tick <= tick = '1' and bclk_count = bclk_div_rate and bclk_int = '1';
channel_sync <= '1' when lrclk_count = 1 else '0';
frame_sync <= '1' when lrclk_count = 1 and lrclk_int = '0' else '0';
-----------------------------------------------------------------------------------
-- Frame clock generator LRCLK_O
-----------------------------------------------------------------------------------
lrclk_gen: process(clk)
begin
if rising_edge(clk) then
prev_lrclk_div_rate <= lrclk_div_rate;
-- Reset
if reset_int then -- or lrclk_div_rate /= prev_lrclk_div_rate then
lrclk_int <= '1';
lrclk_count <= lrclk_div_rate;
else
if lrclk_tick then
if lrclk_count = lrclk_div_rate then
lrclk_count <= 0;
lrclk_int <= not lrclk_int;
else
lrclk_count <= lrclk_count + 1;
end if;
end if;
end if;
end if;
end process lrclk_gen;
end Behavioral;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_splice_e_s
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:03:31 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl -sheet HIER=HIER_SPLICE -sheet CONN=CONN_SPLICE ../../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_splice_e_s-rtl-a.vhd,v 1.2 2006/07/04 09:54:11 wig Exp $
-- $Date: 2006/07/04 09:54:11 $
-- $Log: inst_splice_e_s-rtl-a.vhd,v $
-- Revision 1.2 2006/07/04 09:54:11 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_splice_e_s
--
architecture rtl of inst_splice_e_s is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
component inst_splice_3_0_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_0_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 0 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_0 : out std_ulogic -- Splice signal connector up 3, 0
-- End of Generated Port for Entity inst_splice_3_0_e_s
);
end component;
-- ---------
component inst_splice_3_1_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_1_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 1 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_1 : out std_ulogic -- Splice signal connector up 3, 1
-- End of Generated Port for Entity inst_splice_3_1_e_s
);
end component;
-- ---------
component inst_splice_3_10_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_10_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 10 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_10 : out std_ulogic -- Splice signal connector up 3, 10
-- End of Generated Port for Entity inst_splice_3_10_e_s
);
end component;
-- ---------
component inst_splice_3_11_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_11_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 11 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_11 : out std_ulogic -- Splice signal connector up 3, 11
-- End of Generated Port for Entity inst_splice_3_11_e_s
);
end component;
-- ---------
component inst_splice_3_12_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_12_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 12 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_12 : out std_ulogic -- Splice signal connector up 3, 12
-- End of Generated Port for Entity inst_splice_3_12_e_s
);
end component;
-- ---------
component inst_splice_3_13_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_13_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 13 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_13 : out std_ulogic -- Splice signal connector up 3, 13
-- End of Generated Port for Entity inst_splice_3_13_e_s
);
end component;
-- ---------
component inst_splice_3_14_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_14_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 14 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_14 : out std_ulogic -- Splice signal connector up 3, 14
-- End of Generated Port for Entity inst_splice_3_14_e_s
);
end component;
-- ---------
component inst_splice_3_15_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_15_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 15 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_15 : out std_ulogic -- Splice signal connector up 3, 15
-- End of Generated Port for Entity inst_splice_3_15_e_s
);
end component;
-- ---------
component inst_splice_3_2_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_2_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 2 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_2 : out std_ulogic -- Splice signal connector up 3, 2
-- End of Generated Port for Entity inst_splice_3_2_e_s
);
end component;
-- ---------
component inst_splice_3_3_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_3_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 3 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_3 : out std_ulogic -- Splice signal connector up 3, 3
-- End of Generated Port for Entity inst_splice_3_3_e_s
);
end component;
-- ---------
component inst_splice_3_4_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_4_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 4 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_4 : out std_ulogic -- Splice signal connector up 3, 4
-- End of Generated Port for Entity inst_splice_3_4_e_s
);
end component;
-- ---------
component inst_splice_3_5_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_5_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 5 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_5 : out std_ulogic -- Splice signal connector up 3, 5
-- End of Generated Port for Entity inst_splice_3_5_e_s
);
end component;
-- ---------
component inst_splice_3_6_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_6_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 6 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_6 : out std_ulogic -- Splice signal connector up 3, 6
-- End of Generated Port for Entity inst_splice_3_6_e_s
);
end component;
-- ---------
component inst_splice_3_7_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_7_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 7 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_7 : out std_ulogic -- Splice signal connector up 3, 7
-- End of Generated Port for Entity inst_splice_3_7_e_s
);
end component;
-- ---------
component inst_splice_3_8_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_8_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 8 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_8 : out std_ulogic -- Splice signal connector up 3, 8
-- End of Generated Port for Entity inst_splice_3_8_e_s
);
end component;
-- ---------
component inst_splice_3_9_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_3_9_e_s
s_splice_3 : in std_ulogic; -- Splice signal connector in: 3, 9 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_3_9 : out std_ulogic -- Splice signal connector up 3, 9
-- End of Generated Port for Entity inst_splice_3_9_e_s
);
end component;
-- ---------
component inst_splice_4_0_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_0_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 0 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 0 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_0_e_s
);
end component;
-- ---------
component inst_splice_4_1_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_1_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 1 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 1 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_1_e_s
);
end component;
-- ---------
component inst_splice_4_10_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_10_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 10 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 10 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_10_e_s
);
end component;
-- ---------
component inst_splice_4_11_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_11_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 11 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 11 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_11_e_s
);
end component;
-- ---------
component inst_splice_4_12_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_12_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 12 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 12 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_12_e_s
);
end component;
-- ---------
component inst_splice_4_13_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_13_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 13 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 13 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_13_e_s
);
end component;
-- ---------
component inst_splice_4_14_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_14_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 14 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 14 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_14_e_s
);
end component;
-- ---------
component inst_splice_4_15_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_15_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 15 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 15 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_15_e_s
);
end component;
-- ---------
component inst_splice_4_2_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_2_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 2 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 2 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_2_e_s
);
end component;
-- ---------
component inst_splice_4_3_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_3_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 3 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 3 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_3_e_s
);
end component;
-- ---------
component inst_splice_4_4_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_4_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 4 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 4 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_4_e_s
);
end component;
-- ---------
component inst_splice_4_5_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_5_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 5 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 5 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_5_e_s
);
end component;
-- ---------
component inst_splice_4_6_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_6_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 6 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 6 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_6_e_s
);
end component;
-- ---------
component inst_splice_4_7_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_7_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 7 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 7 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_7_e_s
);
end component;
-- ---------
component inst_splice_4_8_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_8_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 8 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 8 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_8_e_s
);
end component;
-- ---------
component inst_splice_4_9_e_s -- seperate entities
-- No Generated Generics
port (
-- Generated Port for Entity inst_splice_4_9_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 4, 9 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_4 : in std_ulogic -- Splice signal connector in 4, 9 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_splice_4_9_e_s
);
end component;
-- ---------
component inst_spbit_e_s -- common entitiy
-- No Generated Generics
port (
-- Generated Port for Entity inst_spbit_e_s
p_splice_o : out std_ulogic; -- Splice signal connector up, joined 5, 3 __I_AUTO_REDUCED_BUS2SIGNAL
s_splice_5 : in std_ulogic -- Splice signal connector in 5, 3 __I_AUTO_REDUCED_BUS2SIGNAL
-- End of Generated Port for Entity inst_spbit_e_s
);
end component;
-- ---------
--
-- Generated Signal List
--
signal s_splice_3 : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_0 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_1 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_10 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_11 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_12 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_13 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_14 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_15 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_2 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_3 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_4 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_5 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_6 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_7 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_8 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_3_9 : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_4 : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_5 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_join_4 : std_ulogic_vector(15 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_splice_join_5 : std_ulogic_vector(7 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
s_splice_3 <= p_mix_s_splice_3_gi; -- __I_I_BUS_PORT
p_mix_s_splice_3_0_go <= s_splice_3_0; -- __I_O_BIT_PORT
p_mix_s_splice_3_1_go <= s_splice_3_1; -- __I_O_BIT_PORT
p_mix_s_splice_3_10_go <= s_splice_3_10; -- __I_O_BIT_PORT
p_mix_s_splice_3_11_go <= s_splice_3_11; -- __I_O_BIT_PORT
p_mix_s_splice_3_12_go <= s_splice_3_12; -- __I_O_BIT_PORT
p_mix_s_splice_3_13_go <= s_splice_3_13; -- __I_O_BIT_PORT
p_mix_s_splice_3_14_go <= s_splice_3_14; -- __I_O_BIT_PORT
p_mix_s_splice_3_15_go <= s_splice_3_15; -- __I_O_BIT_PORT
p_mix_s_splice_3_2_go <= s_splice_3_2; -- __I_O_BIT_PORT
p_mix_s_splice_3_3_go <= s_splice_3_3; -- __I_O_BIT_PORT
p_mix_s_splice_3_4_go <= s_splice_3_4; -- __I_O_BIT_PORT
p_mix_s_splice_3_5_go <= s_splice_3_5; -- __I_O_BIT_PORT
p_mix_s_splice_3_6_go <= s_splice_3_6; -- __I_O_BIT_PORT
p_mix_s_splice_3_7_go <= s_splice_3_7; -- __I_O_BIT_PORT
p_mix_s_splice_3_8_go <= s_splice_3_8; -- __I_O_BIT_PORT
p_mix_s_splice_3_9_go <= s_splice_3_9; -- __I_O_BIT_PORT
s_splice_4 <= p_mix_s_splice_4_gi; -- __I_I_BUS_PORT
s_splice_5 <= p_mix_s_splice_5_gi; -- __I_I_BUS_PORT
p_mix_s_splice_join_4_go <= s_splice_join_4; -- __I_O_BUS_PORT
p_mix_s_splice_join_5_go <= s_splice_join_5; -- __I_O_BUS_PORT
--
-- Generated Instances and Port Mappings
--
-- Generated Instance Port Map for inst_splice_3_0
inst_splice_3_0: inst_splice_3_0_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(0), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_0 => s_splice_3_0 -- Splice signal connector up 3, 0
);
-- End of Generated Instance Port Map for inst_splice_3_0
-- Generated Instance Port Map for inst_splice_3_1
inst_splice_3_1: inst_splice_3_1_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(1), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_1 => s_splice_3_1 -- Splice signal connector up 3, 1
);
-- End of Generated Instance Port Map for inst_splice_3_1
-- Generated Instance Port Map for inst_splice_3_10
inst_splice_3_10: inst_splice_3_10_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(10), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_10 => s_splice_3_10 -- Splice signal connector up 3, 10
);
-- End of Generated Instance Port Map for inst_splice_3_10
-- Generated Instance Port Map for inst_splice_3_11
inst_splice_3_11: inst_splice_3_11_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(11), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_11 => s_splice_3_11 -- Splice signal connector up 3, 11
);
-- End of Generated Instance Port Map for inst_splice_3_11
-- Generated Instance Port Map for inst_splice_3_12
inst_splice_3_12: inst_splice_3_12_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(12), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_12 => s_splice_3_12 -- Splice signal connector up 3, 12
);
-- End of Generated Instance Port Map for inst_splice_3_12
-- Generated Instance Port Map for inst_splice_3_13
inst_splice_3_13: inst_splice_3_13_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(13), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_13 => s_splice_3_13 -- Splice signal connector up 3, 13
);
-- End of Generated Instance Port Map for inst_splice_3_13
-- Generated Instance Port Map for inst_splice_3_14
inst_splice_3_14: inst_splice_3_14_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(14), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_14 => s_splice_3_14 -- Splice signal connector up 3, 14
);
-- End of Generated Instance Port Map for inst_splice_3_14
-- Generated Instance Port Map for inst_splice_3_15
inst_splice_3_15: inst_splice_3_15_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(15), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_15 => s_splice_3_15 -- Splice signal connector up 3, 15
);
-- End of Generated Instance Port Map for inst_splice_3_15
-- Generated Instance Port Map for inst_splice_3_2
inst_splice_3_2: inst_splice_3_2_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(2), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_2 => s_splice_3_2 -- Splice signal connector up 3, 2
);
-- End of Generated Instance Port Map for inst_splice_3_2
-- Generated Instance Port Map for inst_splice_3_3
inst_splice_3_3: inst_splice_3_3_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(3), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_3 => s_splice_3_3 -- Splice signal connector up 3, 3
);
-- End of Generated Instance Port Map for inst_splice_3_3
-- Generated Instance Port Map for inst_splice_3_4
inst_splice_3_4: inst_splice_3_4_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(4), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_4 => s_splice_3_4 -- Splice signal connector up 3, 4
);
-- End of Generated Instance Port Map for inst_splice_3_4
-- Generated Instance Port Map for inst_splice_3_5
inst_splice_3_5: inst_splice_3_5_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(5), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_5 => s_splice_3_5 -- Splice signal connector up 3, 5
);
-- End of Generated Instance Port Map for inst_splice_3_5
-- Generated Instance Port Map for inst_splice_3_6
inst_splice_3_6: inst_splice_3_6_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(6), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_6 => s_splice_3_6 -- Splice signal connector up 3, 6
);
-- End of Generated Instance Port Map for inst_splice_3_6
-- Generated Instance Port Map for inst_splice_3_7
inst_splice_3_7: inst_splice_3_7_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(7), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_7 => s_splice_3_7 -- Splice signal connector up 3, 7
);
-- End of Generated Instance Port Map for inst_splice_3_7
-- Generated Instance Port Map for inst_splice_3_8
inst_splice_3_8: inst_splice_3_8_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(8), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_8 => s_splice_3_8 -- Splice signal connector up 3, 8
);
-- End of Generated Instance Port Map for inst_splice_3_8
-- Generated Instance Port Map for inst_splice_3_9
inst_splice_3_9: inst_splice_3_9_e_s -- seperate entities
port map (
s_splice_3 => s_splice_3(9), -- Splice signal connector in: 3, 0Splice signal connector in: 3, 1Splice signal connector in: 3,...
s_splice_3_9 => s_splice_3_9 -- Splice signal connector up 3, 9
);
-- End of Generated Instance Port Map for inst_splice_3_9
-- Generated Instance Port Map for inst_splice_4_0
inst_splice_4_0: inst_splice_4_0_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(0), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(0) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_0
-- Generated Instance Port Map for inst_splice_4_1
inst_splice_4_1: inst_splice_4_1_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(1), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(1) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_1
-- Generated Instance Port Map for inst_splice_4_10
inst_splice_4_10: inst_splice_4_10_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(10), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(10) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_10
-- Generated Instance Port Map for inst_splice_4_11
inst_splice_4_11: inst_splice_4_11_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(11), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(11) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_11
-- Generated Instance Port Map for inst_splice_4_12
inst_splice_4_12: inst_splice_4_12_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(12), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(12) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_12
-- Generated Instance Port Map for inst_splice_4_13
inst_splice_4_13: inst_splice_4_13_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(13), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(13) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_13
-- Generated Instance Port Map for inst_splice_4_14
inst_splice_4_14: inst_splice_4_14_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(14), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(14) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_14
-- Generated Instance Port Map for inst_splice_4_15
inst_splice_4_15: inst_splice_4_15_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(15), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(15) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_15
-- Generated Instance Port Map for inst_splice_4_2
inst_splice_4_2: inst_splice_4_2_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(2), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(2) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_2
-- Generated Instance Port Map for inst_splice_4_3
inst_splice_4_3: inst_splice_4_3_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(3), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(3) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_3
-- Generated Instance Port Map for inst_splice_4_4
inst_splice_4_4: inst_splice_4_4_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(4), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(4) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_4
-- Generated Instance Port Map for inst_splice_4_5
inst_splice_4_5: inst_splice_4_5_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(5), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(5) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_5
-- Generated Instance Port Map for inst_splice_4_6
inst_splice_4_6: inst_splice_4_6_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(6), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(6) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_6
-- Generated Instance Port Map for inst_splice_4_7
inst_splice_4_7: inst_splice_4_7_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(7), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(7) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_7
-- Generated Instance Port Map for inst_splice_4_8
inst_splice_4_8: inst_splice_4_8_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(8), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(8) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_8
-- Generated Instance Port Map for inst_splice_4_9
inst_splice_4_9: inst_splice_4_9_e_s -- seperate entities
port map (
p_splice_o => s_splice_join_4(9), -- Splice signal connector up, joined 4, 0Splice signal connector up, joined 4, 1Splice signal co...
s_splice_4 => s_splice_4(9) -- Splice signal connector in 4, 0Splice signal connector in 4, 1Splice signal connector in 4, 2S...
);
-- End of Generated Instance Port Map for inst_splice_4_9
-- Generated Instance Port Map for inst_splice_5_0
inst_splice_5_0: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(0), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(0) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_0
-- Generated Instance Port Map for inst_splice_5_1
inst_splice_5_1: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(1), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(1) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_1
-- Generated Instance Port Map for inst_splice_5_2
inst_splice_5_2: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(2), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(2) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_2
-- Generated Instance Port Map for inst_splice_5_3
inst_splice_5_3: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(3), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(3) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_3
-- Generated Instance Port Map for inst_splice_5_4
inst_splice_5_4: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(4), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(4) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_4
-- Generated Instance Port Map for inst_splice_5_5
inst_splice_5_5: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(5), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(5) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_5
-- Generated Instance Port Map for inst_splice_5_6
inst_splice_5_6: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(6), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(6) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_6
-- Generated Instance Port Map for inst_splice_5_7
inst_splice_5_7: inst_spbit_e_s -- common entitiy
port map (
p_splice_o => s_splice_join_5(7), -- Splice signal connector up, joined 5, 0Splice signal connector up, joined 5, 1Splice signal co...
s_splice_5 => s_splice_5(7) -- Splice signal connector in 5, 0Splice signal connector in 5, 1Splice signal connector in 5, 2S...
);
-- End of Generated Instance Port Map for inst_splice_5_7
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/TWDLROM_3_16.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: TWDLROM_3_16
-- Source Path: ifft_16_bit/IFFT HDL Optimized/TWDLROM_3_16
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
USE work.ifft_16_bit_pkg.ALL;
ENTITY TWDLROM_3_16 IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
dout_2_vld : IN std_logic;
softReset : IN std_logic;
twdl_3_16_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17_En15
twdl_3_16_vld : OUT std_logic
);
END TWDLROM_3_16;
ARCHITECTURE rtl OF TWDLROM_3_16 IS
-- Constants
CONSTANT Twiddle_re_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#08000#, 17), to_signed(16#07642#, 17)); -- sfix17 [2]
CONSTANT Twiddle_im_table_data : vector_of_signed17(0 TO 1) :=
(to_signed(16#00000#, 17), to_signed(-16#030FC#, 17)); -- sfix17 [2]
-- Signals
SIGNAL Radix22TwdlMapping_cnt : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1 : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1 : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2 : std_logic;
SIGNAL Radix22TwdlMapping_cnt_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_phase_next : unsigned(1 DOWNTO 0); -- ufix2
SIGNAL Radix22TwdlMapping_octantReg1_next : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL Radix22TwdlMapping_twdlAddr_raw_next : unsigned(3 DOWNTO 0); -- ufix4
SIGNAL Radix22TwdlMapping_twdlAddrMap_next : std_logic; -- ufix1
SIGNAL Radix22TwdlMapping_twdl45Reg_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg1_next : std_logic;
SIGNAL Radix22TwdlMapping_dvldReg2_next : std_logic;
SIGNAL twdlAddr : std_logic; -- ufix1
SIGNAL twdlAddrVld : std_logic;
SIGNAL twdlOctant : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45 : std_logic;
SIGNAL Twiddle_re_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_re : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL Twiddle_im_cast : signed(31 DOWNTO 0); -- int32
SIGNAL twiddleS_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twiddleReg_im : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdlOctantReg : unsigned(2 DOWNTO 0); -- ufix3
SIGNAL twdl45Reg : std_logic;
SIGNAL twdl_3_16_re_tmp : signed(16 DOWNTO 0); -- sfix17_En15
SIGNAL twdl_3_16_im_tmp : signed(16 DOWNTO 0); -- sfix17_En15
BEGIN
-- Radix22TwdlMapping
Radix22TwdlMapping_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22TwdlMapping_octantReg1 <= to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdlAddr_raw <= to_unsigned(16#0#, 4);
Radix22TwdlMapping_twdlAddrMap <= '0';
Radix22TwdlMapping_twdl45Reg <= '0';
Radix22TwdlMapping_dvldReg1 <= '0';
Radix22TwdlMapping_dvldReg2 <= '0';
Radix22TwdlMapping_cnt <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_phase <= to_unsigned(16#3#, 2);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22TwdlMapping_cnt <= Radix22TwdlMapping_cnt_next;
Radix22TwdlMapping_phase <= Radix22TwdlMapping_phase_next;
Radix22TwdlMapping_octantReg1 <= Radix22TwdlMapping_octantReg1_next;
Radix22TwdlMapping_twdlAddr_raw <= Radix22TwdlMapping_twdlAddr_raw_next;
Radix22TwdlMapping_twdlAddrMap <= Radix22TwdlMapping_twdlAddrMap_next;
Radix22TwdlMapping_twdl45Reg <= Radix22TwdlMapping_twdl45Reg_next;
Radix22TwdlMapping_dvldReg1 <= Radix22TwdlMapping_dvldReg1_next;
Radix22TwdlMapping_dvldReg2 <= Radix22TwdlMapping_dvldReg2_next;
END IF;
END IF;
END PROCESS Radix22TwdlMapping_process;
Radix22TwdlMapping_output : PROCESS (Radix22TwdlMapping_cnt, Radix22TwdlMapping_phase,
Radix22TwdlMapping_octantReg1, Radix22TwdlMapping_twdlAddr_raw,
Radix22TwdlMapping_twdlAddrMap, Radix22TwdlMapping_twdl45Reg,
Radix22TwdlMapping_dvldReg1, Radix22TwdlMapping_dvldReg2, dout_2_vld)
VARIABLE octant : unsigned(2 DOWNTO 0);
VARIABLE cnt_cast : unsigned(3 DOWNTO 0);
VARIABLE sub_cast : signed(9 DOWNTO 0);
VARIABLE sub_temp : signed(9 DOWNTO 0);
VARIABLE sub_cast_0 : signed(5 DOWNTO 0);
VARIABLE sub_temp_0 : signed(5 DOWNTO 0);
VARIABLE sub_cast_1 : signed(5 DOWNTO 0);
VARIABLE sub_temp_1 : signed(5 DOWNTO 0);
VARIABLE sub_cast_2 : signed(9 DOWNTO 0);
VARIABLE sub_temp_2 : signed(9 DOWNTO 0);
VARIABLE sub_cast_3 : signed(9 DOWNTO 0);
VARIABLE sub_temp_3 : signed(9 DOWNTO 0);
BEGIN
Radix22TwdlMapping_twdlAddr_raw_next <= Radix22TwdlMapping_twdlAddr_raw;
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddrMap;
Radix22TwdlMapping_twdl45Reg_next <= Radix22TwdlMapping_twdl45Reg;
Radix22TwdlMapping_dvldReg2_next <= Radix22TwdlMapping_dvldReg1;
Radix22TwdlMapping_dvldReg1_next <= dout_2_vld;
CASE Radix22TwdlMapping_twdlAddr_raw IS
WHEN "0010" =>
octant := to_unsigned(16#0#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "0100" =>
octant := to_unsigned(16#1#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "0110" =>
octant := to_unsigned(16#2#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN "1000" =>
octant := to_unsigned(16#3#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '0';
WHEN "1010" =>
octant := to_unsigned(16#4#, 3);
Radix22TwdlMapping_twdl45Reg_next <= '1';
WHEN OTHERS =>
octant := Radix22TwdlMapping_twdlAddr_raw(3 DOWNTO 1);
Radix22TwdlMapping_twdl45Reg_next <= '0';
END CASE;
Radix22TwdlMapping_octantReg1_next <= octant;
CASE octant IS
WHEN "000" =>
Radix22TwdlMapping_twdlAddrMap_next <= Radix22TwdlMapping_twdlAddr_raw(0);
WHEN "001" =>
sub_cast_0 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_0 := to_signed(16#04#, 6) - sub_cast_0;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_0(0);
WHEN "010" =>
sub_cast_1 := signed(resize(Radix22TwdlMapping_twdlAddr_raw, 6));
sub_temp_1 := sub_cast_1 - to_signed(16#04#, 6);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_1(0);
WHEN "011" =>
sub_cast_2 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_2 := to_signed(16#010#, 10) - sub_cast_2;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_2(1);
WHEN "100" =>
sub_cast_3 := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp_3 := sub_cast_3 - to_signed(16#010#, 10);
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp_3(1);
WHEN OTHERS =>
sub_cast := signed(resize(Radix22TwdlMapping_twdlAddr_raw & '0', 10));
sub_temp := to_signed(16#018#, 10) - sub_cast;
Radix22TwdlMapping_twdlAddrMap_next <= sub_temp(1);
END CASE;
IF Radix22TwdlMapping_phase = to_unsigned(16#0#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= to_unsigned(16#0#, 4);
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#1#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4) sll 1;
ELSIF Radix22TwdlMapping_phase = to_unsigned(16#2#, 2) THEN
Radix22TwdlMapping_twdlAddr_raw_next <= resize(Radix22TwdlMapping_cnt, 4);
ELSE
cnt_cast := resize(Radix22TwdlMapping_cnt, 4);
Radix22TwdlMapping_twdlAddr_raw_next <= (cnt_cast sll 1) + cnt_cast;
END IF;
Radix22TwdlMapping_phase_next <= to_unsigned(16#3#, 2);
Radix22TwdlMapping_cnt_next <= Radix22TwdlMapping_cnt + to_unsigned(16#000000010#, 2);
twdlAddr <= Radix22TwdlMapping_twdlAddrMap;
twdlAddrVld <= Radix22TwdlMapping_dvldReg2;
twdlOctant <= Radix22TwdlMapping_octantReg1;
twdl45 <= Radix22TwdlMapping_twdl45Reg;
END PROCESS Radix22TwdlMapping_output;
-- Twiddle ROM1
Twiddle_re_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_re <= Twiddle_re_table_data(to_integer(Twiddle_re_cast));
TWIDDLEROM_RE_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_re <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_re <= twiddleS_re;
END IF;
END IF;
END PROCESS TWIDDLEROM_RE_process;
-- Twiddle ROM2
Twiddle_im_cast <= '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & '0' & twdlAddr;
twiddleS_im <= Twiddle_im_table_data(to_integer(Twiddle_im_cast));
TWIDDLEROM_IM_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twiddleReg_im <= to_signed(16#00000#, 17);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twiddleReg_im <= twiddleS_im;
END IF;
END IF;
END PROCESS TWIDDLEROM_IM_process;
intdelay_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdlOctantReg <= to_unsigned(16#0#, 3);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdlOctantReg <= twdlOctant;
END IF;
END IF;
END PROCESS intdelay_process;
intdelay_1_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl45Reg <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl45Reg <= twdl45;
END IF;
END IF;
END PROCESS intdelay_1_process;
-- Radix22TwdlOctCorr
Radix22TwdlOctCorr_output : PROCESS (twiddleReg_re, twiddleReg_im, twdlOctantReg, twdl45Reg)
VARIABLE twdlIn_re : signed(16 DOWNTO 0);
VARIABLE twdlIn_im : signed(16 DOWNTO 0);
VARIABLE cast : signed(17 DOWNTO 0);
VARIABLE cast_0 : signed(17 DOWNTO 0);
VARIABLE cast_1 : signed(17 DOWNTO 0);
VARIABLE cast_2 : signed(17 DOWNTO 0);
VARIABLE cast_3 : signed(17 DOWNTO 0);
VARIABLE cast_4 : signed(17 DOWNTO 0);
VARIABLE cast_5 : signed(17 DOWNTO 0);
VARIABLE cast_6 : signed(17 DOWNTO 0);
VARIABLE cast_7 : signed(17 DOWNTO 0);
VARIABLE cast_8 : signed(17 DOWNTO 0);
VARIABLE cast_9 : signed(17 DOWNTO 0);
VARIABLE cast_10 : signed(17 DOWNTO 0);
BEGIN
twdlIn_re := twiddleReg_re;
twdlIn_im := twiddleReg_im;
IF twdl45Reg = '1' THEN
CASE twdlOctantReg IS
WHEN "000" =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "010" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
WHEN "100" =>
twdlIn_re := to_signed(-16#05A82#, 17);
twdlIn_im := to_signed(16#05A82#, 17);
WHEN OTHERS =>
twdlIn_re := to_signed(16#05A82#, 17);
twdlIn_im := to_signed(-16#05A82#, 17);
END CASE;
ELSE
CASE twdlOctantReg IS
WHEN "000" =>
NULL;
WHEN "001" =>
cast := resize(twiddleReg_im, 18);
cast_0 := - (cast);
twdlIn_re := cast_0(16 DOWNTO 0);
cast_5 := resize(twiddleReg_re, 18);
cast_6 := - (cast_5);
twdlIn_im := cast_6(16 DOWNTO 0);
WHEN "010" =>
twdlIn_re := twiddleReg_im;
cast_7 := resize(twiddleReg_re, 18);
cast_8 := - (cast_7);
twdlIn_im := cast_8(16 DOWNTO 0);
WHEN "011" =>
cast_1 := resize(twiddleReg_re, 18);
cast_2 := - (cast_1);
twdlIn_re := cast_2(16 DOWNTO 0);
twdlIn_im := twiddleReg_im;
WHEN "100" =>
cast_3 := resize(twiddleReg_re, 18);
cast_4 := - (cast_3);
twdlIn_re := cast_4(16 DOWNTO 0);
cast_9 := resize(twiddleReg_im, 18);
cast_10 := - (cast_9);
twdlIn_im := cast_10(16 DOWNTO 0);
WHEN OTHERS =>
twdlIn_re := twiddleReg_im;
twdlIn_im := twiddleReg_re;
END CASE;
END IF;
twdl_3_16_re_tmp <= twdlIn_re;
twdl_3_16_im_tmp <= twdlIn_im;
END PROCESS Radix22TwdlOctCorr_output;
twdl_3_16_re <= std_logic_vector(twdl_3_16_re_tmp);
twdl_3_16_im <= std_logic_vector(twdl_3_16_im_tmp);
intdelay_2_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
twdl_3_16_vld <= '0';
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
twdl_3_16_vld <= twdlAddrVld;
END IF;
END IF;
END PROCESS intdelay_2_process;
END rtl;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
---------------------------------------------------------------------------------
--
-- U S E R F U N C T I O N : P R E D I C T I O N
--
--
-- The particles are loaded into the local RAM by the Framework.
-- The 8kb local RAM is filled with as many particles as possible.
-- There will not be any space between the particles.
--
-- The user of the framework knows how a particle is defined and
-- he defines here, how the next state is going to be predicted.
-- In the end the user has to overwrite every particle with the
-- sampled particle.
--
-- If this has be done for every particle, the finshed signal
-- has to be set to '1'. A new run of the prediction will be
-- started if new particles are loaded to the local RAM and
-- the signal particles_loaded is equal to '1'.
--
-- Because this function depends on parameter, additional
-- parameter can be given to the framework, which copies
-- them into the first 128 byte of the local RAM.
--
------------------------------------------------------------------------------------
entity uf_prediction is
generic (
C_BURST_AWIDTH : integer := 12;
C_BURST_DWIDTH : integer := 32
);
port (
clk : in std_logic;
reset : in std_logic;
-- burst ram interface
o_RAMAddr : out std_logic_vector(0 to C_BURST_AWIDTH-1);
o_RAMData : out std_logic_vector(0 to C_BURST_DWIDTH-1);
i_RAMData : in std_logic_vector(0 to C_BURST_DWIDTH-1);
o_RAMWE : out std_logic;
o_RAMClk : out std_logic;
-- init signal
init : in std_logic;
-- enable signal
enable : in std_logic;
-- start signal for the prediction user process
particles_loaded : in std_logic;
-- number of particles in local RAM
number_of_particles : in integer;
-- size of one particle
particle_size : in integer;
-- if every particle is sampled, this signal has to be set to '1'
finished : out std_logic
);
end uf_prediction;
architecture Behavioral of uf_prediction is
component pseudo_random is
Port ( reset : in STD_LOGIC;
clk : in STD_LOGIC;
enable : in STD_LOGIC;
load : in STD_LOGIC;
seed : in STD_LOGIC_VECTOR(31 downto 0);
pseudoR : out STD_LOGIC_VECTOR(31 downto 0));
end component;
-- GRANULARITY
constant GRANULARITY :integer := 16384;
-- factors for prediction fucntion
constant A1: integer := 2;
constant A2: integer := -1;
constant B0: integer := 1;
-- local RAM read/write address
signal local_ram_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
signal particle_start_address : std_logic_vector(0 to C_BURST_AWIDTH-1) := (others => '0');
-- particle counter
signal counter : integer := 0;
-- signals for new values
signal x_new : integer := 0;
signal y_new : integer := 0;
signal s_new : integer := 0;
-- particle data
signal x : integer := 0;
signal y : integer := 0;
signal s : integer := 0;
signal x_old : integer := 0;
signal y_old : integer := 0;
signal s_old : integer := 0;
signal x0 : integer := -1;
signal y0 : integer := -1;
-- parameters
signal SIZE_X : integer := 480;
signal SIZE_Y : integer := 360;
signal TRANS_X_STD : integer := 16384;
signal TRANS_Y_STD : integer := 8192;
signal TRANS_S_STD : integer := 16;
-- temporary signals
signal tmp1 : integer := 0;
signal tmp2 : integer := 0;
signal tmp3 : integer := 0;
signal tmp4 : integer := 0;
signal tmp5 : integer := 0;
signal tmp6 : integer := 0;
-- states
type t_state is (STATE_INIT,
STATE_LOAD_PARAMETER_1, STATE_LOAD_PARAMETER_2, STATE_LOAD_SIZE_X,
STATE_LOAD_SIZE_Y, STATE_LOAD_TRANS_X_STD, STATE_LOAD_TRANS_Y_STD,
STATE_LOAD_TRANS_S_STD, STATE_SAMPLING, STATE_LOAD_PARTICLE_DECISION,
STATE_LOAD_PARTICLE_1, STATE_LOAD_PARTICLE_2,
STATE_LOAD_X, STATE_LOAD_Y, STATE_LOAD_S,
STATE_LOAD_XP, STATE_LOAD_YP, STATE_LOAD_YP_2, STATE_LOAD_SP,
STATE_LOAD_SP_2, STATE_LOAD_X0, STATE_LOAD_Y0,
STATE_CALCULATE_NEW_DATA_1, STATE_CALCULATE_NEW_DATA_2, STATE_CALCULATE_NEW_DATA_3,
STATE_CALCULATE_NEW_DATA_4, STATE_CALCULATE_NEW_DATA_5, STATE_CALCULATE_NEW_DATA_6,
STATE_CALCULATE_NEW_DATA_7, STATE_WRITE_X, STATE_WRITE_Y, STATE_WRITE_S,
STATE_WRITE_XP, STATE_WRITE_YP, STATE_WRITE_SP,
STATE_FINISH);
-- current state
signal state : t_state := STATE_INIT;
-- needed for pseudo random entity
signal enable_pseudo : std_logic := '0';
signal load : std_logic := '0';
signal seed : std_logic_vector(31 downto 0) := (others => '0');
signal pseudoR : std_logic_vector(31 downto 0) := (others => '0');
-- pseudo number as integer;
signal pseudo : integer := 0;
begin
pseudo_r : pseudo_random
port map (reset=>reset, clk=>clk, enable=>enable_pseudo, load=>load, seed=>seed, pseudoR=>pseudoR);
-- burst ram interface
o_RAMClk <= clk;
state_proc : process(clk, reset)
begin
if (reset = '1') then
seed <= X"7A3E0426";
load <= '1';
enable_pseudo <= '1';
state <= STATE_INIT;
finished <= '0';
x0 <= -1;
elsif rising_edge(clk) then
enable_pseudo <= enable;
load <= '0';
if init = '1' then
state <= STATE_INIT;
finished <= '0';
o_RAMData <= (others=>'0');
o_RAMWE <= '0';
o_RAMAddr <= (others => '0');
elsif enable = '1' then
case state is
--! init data
when STATE_INIT =>
local_ram_address <= (others => '0');
counter <= 0;
finished <= '0';
o_RAMWE <= '0';
if (particles_loaded = '1') then
-- TODO: C H A N G E !!! (3 of 3)
-- CHANGE BACK !!! (2 of 2)
state <= STATE_LOAD_PARAMETER_1;
--state <= STATE_SAMPLING;
end if;
--! load parameter 1/2
when STATE_LOAD_PARAMETER_1 =>
o_RAMWE <= '0';
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_PARAMETER_2;
--! load parameter 2/2
when STATE_LOAD_PARAMETER_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_SIZE_X;
--! load parameter SIZE_X
when STATE_LOAD_SIZE_X =>
SIZE_X <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_SIZE_Y;
--! load parameter SIZE_Y
when STATE_LOAD_SIZE_Y =>
SIZE_Y <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_TRANS_X_STD;
--! load parameter TRANS_X_STD
when STATE_LOAD_TRANS_X_STD =>
TRANS_X_STD <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_TRANS_Y_STD;
--! load parameter TRANS_Y_STD
when STATE_LOAD_TRANS_Y_STD =>
TRANS_Y_STD <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_LOAD_TRANS_S_STD;
--! load parameter TRANS_S_STD
when STATE_LOAD_TRANS_S_STD =>
TRANS_S_STD <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_SAMPLING;
when STATE_SAMPLING =>
-- first 32 are saved for parameter, the 33th is the first weight
-- => 33 - the first x value
local_ram_address <= "000000100001";
particle_start_address <= "000000100001";
o_RAMWE <= '0';
finished <= '0';
counter <= 0;
--x0 <= -1;
state <= STATE_LOAD_PARTICLE_DECISION;
--! decision if another particle has to be sampled
when STATE_LOAD_PARTICLE_DECISION =>
o_RAMWE <= '0';
if (counter < number_of_particles) then
state <= STATE_LOAD_PARTICLE_1;
local_ram_address <= particle_start_address;
else
state <= STATE_FINISH;
end if;
--! load particle data 1/2
when STATE_LOAD_PARTICLE_1 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_PARTICLE_2;
--! load particle data 2/2
when STATE_LOAD_PARTICLE_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_X;
--! load particle data: x
when STATE_LOAD_X =>
x <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_Y;
--! load particle data: y
when STATE_LOAD_Y =>
y <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
state <= STATE_LOAD_S;
--! load particle data: s
when STATE_LOAD_S =>
s <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
pseudo <= TO_INTEGER(SIGNED(pseudoR));
state <= STATE_LOAD_XP;
--! load particle data: xp
when STATE_LOAD_XP =>
x_old <= TO_INTEGER(SIGNED(i_RAMData));
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
pseudo <= pseudo / 16;
state <= STATE_LOAD_YP;
--! load particle data: yp
when STATE_LOAD_YP =>
y_old <= TO_INTEGER(SIGNED(i_RAMData));
pseudo <= TO_INTEGER(SIGNED(pseudoR));
--tmp2 <= pseudo mod 16384;
----tmp2 <= pseudo mod 65536;
tmp2 <= pseudo mod 32768;
state <= STATE_LOAD_YP_2;
--! load particle data: yp
when STATE_LOAD_YP_2 =>
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
--tmp2 <= tmp2 - 8192;
----tmp2 <= tmp2 - 32768;
tmp2 <= tmp2 - 16384;
state <= STATE_LOAD_SP;
--! load particle data: sp
when STATE_LOAD_SP =>
s_old <= TO_INTEGER(SIGNED(i_RAMData));
pseudo <= TO_INTEGER(SIGNED(pseudoR));
----tmp4 <= pseudo mod 8192;
tmp4 <= pseudo mod 32768;
--tmp4 <= pseudo mod 16384;
state <= STATE_LOAD_SP_2;
--! load particle data: sp
when STATE_LOAD_SP_2 =>
----tmp4 <= tmp4 - 4096;
tmp4 <= tmp4 - 16384;
--tmp4 <= tmp4 - 8192;
o_RAMAddr <= local_ram_address;
local_ram_address <= local_ram_address + 1;
if (x0 > -1 ) then
-- x0, y0 loaded before
state <= STATE_CALCULATE_NEW_DATA_1;
else
-- x0, y0 not loaded yet
state <= STATE_LOAD_X0;
end if;
--! load particle data: x0
when STATE_LOAD_X0 =>
x0 <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_LOAD_Y0;
--! load particle data: y0
when STATE_LOAD_Y0 =>
y0 <= TO_INTEGER(SIGNED(i_RAMData));
state <= STATE_CALCULATE_NEW_DATA_1;
--! calculate new data (1/7)
--
-- x_new = A1 * (x - x0) + A2 * (x_old - x0)
-- + B0 * pseudo_gaussian (TRANS_X_STD) + p->x0;
--
-- y_new and s_new are calculated in a similar way
-- this equation is splitted up into four states
--
-- A 6th and 7th state is used for correction
--
when STATE_CALCULATE_NEW_DATA_1 =>
-- calculate new x
x_new <= x - x0;
tmp1 <= x_old - x0;
--tmp2 <= (pseudo mod 16384) - 8192; -- calculated with different pseudonumber
-- calcualte new y
y_new <= y - y0;
tmp3 <= y_old - y0;
--tmp4 <= (pseudo mod 8192) - 4096; -- calculated with different pseudonumber
-- calculate new s
s_new <= s - GRANULARITY;
tmp5 <= s_old - GRANULARITY;
tmp6 <= pseudo mod 16;
--tmp6 <= pseudo mod 64;
state <= STATE_CALCULATE_NEW_DATA_2;
--! calculate new data (2/7)
when STATE_CALCULATE_NEW_DATA_2 =>
tmp6 <= tmp6 - 8;
--tmp6 <= tmp6 - 32;
state <= STATE_CALCULATE_NEW_DATA_3;
--! calculate new data (3/7)
when STATE_CALCULATE_NEW_DATA_3 =>
-- calculate new x
x_new <= A1 * x_new;
tmp1 <= A2 * tmp1;
tmp2 <= - B0 * tmp2;
-- calculate new y
y_new <= A1 * y_new;
tmp3 <= A2 * tmp3;
tmp4 <= B0 * tmp4;
-- calculate new s
s_new <= A1 * s_new;
tmp5 <= A2 * tmp5;
tmp6 <= B0 * tmp6;
state <= STATE_CALCULATE_NEW_DATA_4;
--! calculate new data (4/7)
when STATE_CALCULATE_NEW_DATA_4 =>
-- calcualte new x
x_new <= x_new + tmp1;
tmp2 <= tmp2 + x0;
-- calcualte new y
y_new <= y_new + tmp3;
tmp4 <= tmp4 + y0;
-- calcualte new s
s_new <= s_new + tmp5;
tmp6 <= tmp6 + GRANULARITY;
state <= STATE_CALCULATE_NEW_DATA_5;
--! calculate new data (5/7)
when STATE_CALCULATE_NEW_DATA_5 =>
-- calculate new x
x_new <= x_new + tmp2;
-- calculate new y
y_new <= y_new + tmp4;
-- calculate new s
s_new <= s_new + tmp6;
state <= STATE_CALCULATE_NEW_DATA_6;
--! calculate new data (6/7): correction
when STATE_CALCULATE_NEW_DATA_6 =>
-- correct new x
if (x_new < 0) then
x_new <= 0;
elsif ((SIZE_X * GRANULARITY) <= x_new) then
x_new <= SIZE_X * GRANULARITY;
end if;
-- correct new y
if (y_new < 0) then
y_new <= 0;
elsif ((SIZE_Y * GRANULARITY) <= y_new) then
y_new <= SIZE_Y * GRANULARITY;
end if;
-- correct new s
if (s_new < 0) then
s_new <= 0;
elsif (s_new <= (GRANULARITY / 8)) then
s_new <= GRANULARITY / 8;
elsif ((8*GRANULARITY) <= s_new) then
s_new <= 8 * GRANULARITY;
end if;
state <= STATE_CALCULATE_NEW_DATA_7;
--! calculate new data (7/7): correction
when STATE_CALCULATE_NEW_DATA_7 =>
-- correct new x
if (x_new = (SIZE_X * GRANULARITY)) then
x_new <= x_new - 1;
end if;
-- correct new y
if (y_new = (SIZE_Y * GRANULARITY)) then
y_new <= y_new - 1;
end if;
state <= STATE_WRITE_X;
--! write sampled particle: x
when STATE_WRITE_X =>
o_RAMWE <= '1';
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(x_new, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address;
state <= STATE_WRITE_Y;
--! write sampled particle: y
when STATE_WRITE_Y =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(y_new, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 1;
state <= STATE_WRITE_S;
--! write sampled particle: s
when STATE_WRITE_S =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(s_new, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 2;
state <= STATE_WRITE_XP;
--! write sampled particle: xp
when STATE_WRITE_XP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(x, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 3;
state <= STATE_WRITE_YP;
--! write sampled particle: yp
when STATE_WRITE_YP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(y, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 4;
state <= STATE_WRITE_SP;
--! write sampled particle: sp
when STATE_WRITE_SP =>
o_RAMData <= STD_LOGIC_VECTOR(TO_SIGNED(s, C_BURST_DWIDTH));
o_RAMAddr <= particle_start_address + 5;
particle_start_address <= particle_start_address + particle_size;
counter <= counter + 1;
state <= STATE_LOAD_PARTICLE_DECISION;
-- write finished signal
when STATE_FINISH =>
o_RAMWE <= '0';
finished <= '1';
if (particles_loaded = '1') then
state <= STATE_SAMPLING;
end if;
when others =>
state <= STATE_INIT;
end case;
end if;
end if;
end process;
end Behavioral;
|
package p is
type r1 is record -- OK
x : integer;
y : integer;
end record;
type r2 is record -- Error
x, x : integer;
end record;
type r3;
type r3 is record -- Error
x : r3;
end record;
type r4 is record
x, y, z : integer;
end record;
type r5 is record
x : r1;
y : integer;
end record;
type r1_vec is array (integer range <>) of r1;
type r6 is record
x : r1_vec; -- Error
end record;
end package;
package body p is
procedure p1 is
variable v1 : r1 := (1, 2); -- OK
variable v2 : r4 := (1, 2); -- Error
variable v3 : r1 := (1, v1); -- Error
variable v4 : r1 := (x => 1, y => 2); -- OK
variable v5 : r1 := (x => 1); -- Error
variable v6 : r1 := (x => 1, y => 2, q => 1); -- Error
variable v7 : r1 := (x => 1, y => v1); -- Error
variable v8 : r1 := (others => 9); -- OK
variable v9 : r1 := (x => 1, others => 2);
variable v10 : r1 := (x => 1, x => 2, y => 3); -- Error
variable v11 : r1 := (1, x => 4, y => 2); -- Error
variable v12 : r1 := (1, y => 4); -- OK
variable v13 : r1;
begin
end procedure;
procedure p2 is
variable v1 : r1;
variable v2 : r5;
begin
v1.x := 2;
v1.y := v1.x + 5;
v2.x.x := 3;
end procedure;
procedure p3 is
variable a1 : r1_vec; -- Error
begin
end procedure;
procedure p4 is
variable a2 : r1_vec(0 to 3); -- OK
begin
a2(2).x := 5; -- OK
a2(1).f := 2; -- Error
a2(0).x := a2(1).y; -- OK
end procedure;
procedure p5 is
subtype r1_sub is r1; -- OK
variable a : r1_sub; -- OK
begin
a.x := 5; -- OK
a.y := a.x + 2; -- OK
a.z := 2; -- Error
end procedure;
procedure p6 is
subtype r1_bad is r1(1 to 3); -- Error
begin
end procedure;
procedure p7 is
type rec is record
vec : bit_vector(1 to 3);
end record;
variable a : rec;
begin
assert a.vec'length = 3; -- OK
end procedure;
procedure p8 is
function make_r1 return r1 is
begin
return (x => 1, y => 2); -- OK
end function;
begin
assert make_r1.x = 1; -- OK
assert make_r1.z = 2; -- Error
end procedure;
type int_file is file of integer;
type r7 is record
a : int_file;
end record;
type r8 is record
a : integer range 1 to 10;
end record;
procedure p9 is
variable x : r8; -- OK
begin
end procedure;
procedure p10 is
variable x : r8 := (ack => '1'); -- Error
begin
end procedure;
type line is access string;
-- Copied from incorrect code in std.textio
procedure read (l : inout line;
value : out time;
good : out boolean ) is
type unit_spec_t is record
name : string(1 to 3);
length : positive;
unit : time;
end record;
type unit_map_t is array (natural range <>) of unit_spec_t;
constant unit_map : unit_spec_t := (
( "fs ", 2, fs ) );
variable scale, len : integer;
variable scale_good : boolean;
begin
good := false;
if not scale_good then
return;
end if;
for i in 0 to 0 loop
len := unit_map(i).length; -- Error
if l'length > len
and l.all(1 to len) = unit_map(i).name(1 to len)
then
value := scale * unit_map(i).unit;
good := true;
end if;
end loop;
end procedure;
procedure aggregates is
variable r : r1;
begin
r := (1 => 1); -- Error
r := (1, 2, 3); -- Error
r := (1, 2, others => 3); -- Error
r := (x to y => 4); -- Error
r := (x to z => 2); -- Error
end procedure;
procedure test1 is
variable r : foo; -- Error
begin
r.baz := 1; -- Error
end procedure;
procedure test2 is
procedure sub (x : integer) is
begin
end procedure;
begin
sub(x.z => 2); -- Error
end procedure;
end package body;
|
-- Copyright (C) Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
LIBRARY IEEE;
use IEEE.STD_LOGIC_1164.all;
USE IEEE.vital_timing.ALL;
USE IEEE.vital_primitives.ALL;
package STRATIXIV_PCIE_HIP_COMPONENTS is
-- VITAL constants BEGIN
-- default generic values
CONSTANT DefWireDelay : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01 : VitalDelayType01 := (0 ns, 0 ns);
CONSTANT DefPropDelay01Z : VitalDelayType01Z := (OTHERS => 0 ns);
CONSTANT DefSetupHoldCnst : TIME := 0 ns;
CONSTANT DefPulseWdthCnst : TIME := 0 ns;
-- default control options
-- CONSTANT DefGlitchMode : VitalGlitchKindType := OnEvent;
-- change default delay type to Transport : for spr 68748
CONSTANT DefGlitchMode : VitalGlitchKindType := VitalTransport;
CONSTANT DefGlitchMsgOn : BOOLEAN := FALSE;
CONSTANT DefGlitchXOn : BOOLEAN := FALSE;
CONSTANT DefMsgOnChecks : BOOLEAN := TRUE;
CONSTANT DefXOnChecks : BOOLEAN := TRUE;
-- output strength mapping
-- UX01ZWHL-
CONSTANT PullUp : VitalOutputMapType := "UX01HX01X";
CONSTANT NoPullUpZ : VitalOutputMapType := "UX01ZX01X";
CONSTANT PullDown : VitalOutputMapType := "UX01LX01X";
-- primitive result strength mapping
CONSTANT wiredOR : VitalResultMapType := ( 'U', 'X', 'L', '1' );
CONSTANT wiredAND : VitalResultMapType := ( 'U', 'X', '0', 'H' );
CONSTANT L : VitalTableSymbolType := '0';
CONSTANT H : VitalTableSymbolType := '1';
CONSTANT x : VitalTableSymbolType := '-';
CONSTANT S : VitalTableSymbolType := 'S';
CONSTANT R : VitalTableSymbolType := '/';
CONSTANT U : VitalTableSymbolType := 'X';
CONSTANT V : VitalTableSymbolType := 'B'; -- valid clock signal (non-rising)
-- VITAL constants END
-- GENERIC utility functions BEGIN
function str2bin (s : string) return std_logic_vector;
function str2int (s : string) return integer;
function int2bin (arg : integer; size : integer) return std_logic_vector;
function tx_top_ctrl_in_width(
double_data_mode : string;
ser_double_data_mode : string
) return integer;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer;
function rx_top_ctrl_out_width(
double_data_mode : string;
des_double_data_mode : string
) return integer;
-- GENERIC utility functions BEGIN
function bin2int (s : std_logic_vector) return integer;
function bin2int (s : std_logic) return integer;
function int2bit (arg : boolean) return std_logic;
function int2bin (arg : boolean; size : integer) return std_logic_vector;
function int2bit (arg : integer) return std_logic;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic;
function reduction_or (val : std_logic_vector) return std_logic;
function reduction_nor (val : std_logic_vector) return std_logic;
function reduction_xor (val : std_logic_vector) return std_logic;
function reduction_and (val : std_logic_vector) return std_logic;
function reduction_nand (val : std_logic_vector) return std_logic;
function hssiSelectDelay (CONSTANT Paths: IN VitalPathArray01Type) return TIME;
function alpha_tolower (given_string : string) return string;
-- GENERIC utility functions END
--
-- stratixiv_pciehip_pciexp_dcfiforam
--
COMPONENT stratixiv_pciehip_pciexp_dcfiforam
GENERIC (
addr_width : INTEGER := 4;
data_width : INTEGER := 32
);
PORT (
data : IN STD_LOGIC_VECTOR((data_width - 1) DOWNTO 0);
wren : IN STD_LOGIC;
wraddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR((addr_width - 1) DOWNTO 0);
wrclock : IN STD_LOGIC;
rdclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(data_width - 1 DOWNTO 0)
);
END COMPONENT;
--
-- stratixiv_hssi_pcie_hip
--
COMPONENT stratixiv_hssi_pcie_hip
GENERIC (
MsgOn : Boolean := DefGlitchMsgOn;
XOn : Boolean := DefGlitchXOn;
MsgOnChecks : Boolean := DefMsgOnChecks;
XOnChecks : Boolean := DefXOnChecks;
InstancePath : String := "*";
TimingChecksOn : Boolean := True;
tipd_bistenrcv0 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrcv1 : VitalDelayType01 := DefpropDelay01;
tipd_bistenrpl : VitalDelayType01 := DefpropDelay01;
tipd_bistscanen : VitalDelayType01 := DefpropDelay01;
tipd_bistscanin : VitalDelayType01 := DefpropDelay01;
tipd_bisttesten : VitalDelayType01 := DefpropDelay01;
tipd_coreclkin : VitalDelayType01 := DefpropDelay01;
tipd_corecrst : VitalDelayType01 := DefpropDelay01;
tipd_corepor : VitalDelayType01 := DefpropDelay01;
tipd_corerst : VitalDelayType01 := DefpropDelay01;
tipd_coresrst : VitalDelayType01 := DefpropDelay01;
tipd_cplerr : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_cplpending : VitalDelayType01 := DefpropDelay01;
tipd_dbgpipex1rx : VitalDelayArrayType01(15 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlaspmcr0 : VitalDelayType01 := DefpropDelay01;
tipd_dlcomclkreg : VitalDelayType01 := DefpropDelay01;
tipd_dlctrllink2 : VitalDelayArrayType01(13 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dldataupfc : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlhdrupfc : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlinhdllp : VitalDelayType01 := DefpropDelay01;
tipd_dlmaxploaddcr : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphycfg : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlreqphypm : VitalDelayArrayType01(4 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlrequpfc : VitalDelayType01 := DefpropDelay01;
tipd_dlreqwake : VitalDelayType01 := DefpropDelay01;
tipd_dlrxecrcchk : VitalDelayType01 := DefpropDelay01;
tipd_dlsndupfc : VitalDelayType01 := DefpropDelay01;
tipd_dltxcfgextsy : VitalDelayType01 := DefpropDelay01;
tipd_dltxreqpm : VitalDelayType01 := DefpropDelay01;
tipd_dltxtyppm : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dltypupfc : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcctrl : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidmap : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dlvcidupfc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_dpclk : VitalDelayType01 := DefpropDelay01;
tipd_dpriodisable : VitalDelayType01 := DefpropDelay01;
tipd_dprioin : VitalDelayType01 := DefpropDelay01;
tipd_dprioload : VitalDelayType01 := DefpropDelay01;
tipd_extrain : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmiaddr : VitalDelayArrayType01(12 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmidin : VitalDelayArrayType01(32 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_lmirden : VitalDelayType01 := DefpropDelay01;
tipd_lmiwren : VitalDelayType01 := DefpropDelay01;
tipd_mode : VitalDelayArrayType01(2 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_mramhiptestenable : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanen : VitalDelayType01 := DefpropDelay01;
tipd_mramregscanin : VitalDelayType01 := DefpropDelay01;
tipd_pclkcentral : VitalDelayType01 := DefpropDelay01;
tipd_pclkch0 : VitalDelayType01 := DefpropDelay01;
tipd_phyrst : VitalDelayType01 := DefpropDelay01;
tipd_physrst : VitalDelayType01 := DefpropDelay01;
tipd_phystatus : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_pldclk : VitalDelayType01 := DefpropDelay01;
tipd_pldrst : VitalDelayType01 := DefpropDelay01;
tipd_pldsrst : VitalDelayType01 := DefpropDelay01;
tipd_pllfixedclk : VitalDelayType01 := DefpropDelay01;
tipd_rxdata : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxdatak : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxelecidle : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxmaskvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxmaskvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc0 : VitalDelayType01 := DefpropDelay01;
tipd_rxreadyvc1 : VitalDelayType01 := DefpropDelay01;
tipd_rxstatus : VitalDelayArrayType01(24 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_rxvalid : VitalDelayArrayType01(8 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_scanen : VitalDelayType01 := DefpropDelay01;
tipd_scanmoden : VitalDelayType01 := DefpropDelay01;
tipd_swdnin : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_swupin : VitalDelayArrayType01(7 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_testin : VitalDelayArrayType01(40 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlaermsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappintasts : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlappmsireq : VitalDelayType01 := DefpropDelay01;
tipd_tlappmsitc : VitalDelayArrayType01(3 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlhpgctrler : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpexmsinum : VitalDelayArrayType01(5 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmauxpwr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmdata : VitalDelayArrayType01(10 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_tlpmetocr : VitalDelayType01 := DefpropDelay01;
tipd_tlpmevent : VitalDelayType01 := DefpropDelay01;
tipd_tlslotclkcfg : VitalDelayType01 := DefpropDelay01;
tipd_txdatavc00 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc01 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc10 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txdatavc11 : VitalDelayArrayType01(64 - 1 DOWNTO 0) := (OTHERS => DefPropDelay01);
tipd_txeopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txeopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txerrvc1 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc00 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc01 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc10 : VitalDelayType01 := DefpropDelay01;
tipd_txsopvc11 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc0 : VitalDelayType01 := DefpropDelay01;
tipd_txvalidvc1 : VitalDelayType01 := DefpropDelay01;
tpd_pldclk_clrrxpath_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackphypm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlackrequpfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlacksndupfc_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentdeemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlcurrentspeed_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dldllreq_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrdll_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlerrphy_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkautobdwstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dllinkbdwmngstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlltssm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrpbufemp_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrstentercompbit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrsttxmarginfield_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxtyppm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlrxvalpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dltxackpm_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlupexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_dlvcstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev128ns_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_ev1us_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_extraclkout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_hotrstexit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_intstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_l2exit_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_laneact_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_linkup_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_lmidout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_resetstatus_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbardecvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxbevc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxdatavc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxeopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxerrvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc00_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc01_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc10_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxsopvc11_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_rxvalidvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_r2cerr0ext_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_serrout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_successspeednegoint_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swdnwake_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_swuphotrst_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappintaack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlappmsiack_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_tlpmetosr_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txcredvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifoemptyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifofullvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifordpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txfifowrpvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc0_posedge : VitalDelayType01 := DefPropDelay01;
tpd_pldclk_txreadyvc1_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dataenablen_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dprioout_posedge : VitalDelayType01 := DefPropDelay01;
tpd_dpclk_dpriostate_posedge : VitalDelayType01 := DefPropDelay01;
tsetup_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_corecrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_coresrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplerr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_cplpending_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlctrllink2_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dldataupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlhdrupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlinhdllp_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlmaxploaddcr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphycfg_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqphypm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrequpfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlreqwake_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlrxecrcchk_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlsndupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxcfgextsy_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxreqpm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltxtyppm_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dltypupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcctrl_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidmap_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dlvcidupfc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiaddr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmidin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmirden_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_lmiwren_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_physrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_pldsrst_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxmaskvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_rxreadyvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swdnin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_swupin_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlaermsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappintasts_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsireq_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlappmsitc_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlhpgctrler_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpexmsinum_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmauxpwr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmdata_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmetocr_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_tlpmevent_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txdatavc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txeopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txerrvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc00_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc01_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc10_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txsopvc11_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc0_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_txvalidvc1_pldclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
tsetup_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dpriodisable_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
thold_dprioin_dpclk_noedge_posedge : VitalDelayType := DefSetupHoldCnst;
lpm_type : STRING := "stratixiv_hssi_pcie_hip";
advanced_errors : STRING := "false";
allow_rx_valid_empty : STRING := "false"; -- july3,2008
bar0_64bit_mem_space : STRING := "true";
bar0_io_space : STRING := "false";
bar0_prefetchable : STRING := "true";
bar0_size_mask : INTEGER := 32;
bar1_64bit_mem_space : STRING := "false";
bar1_io_space : STRING := "false";
bar1_prefetchable : STRING := "false";
bar1_size_mask : INTEGER := 4;
bar2_64bit_mem_space : STRING := "false";
bar2_io_space : STRING := "false";
bar2_prefetchable : STRING := "false";
bar2_size_mask : INTEGER := 4;
bar3_64bit_mem_space : STRING := "false";
bar3_io_space : STRING := "false";
bar3_prefetchable : STRING := "false";
bar3_size_mask : INTEGER := 4;
bar4_64bit_mem_space : STRING := "false";
bar4_io_space : STRING := "false";
bar4_prefetchable : STRING := "false";
bar4_size_mask : INTEGER := 4;
bar5_64bit_mem_space : STRING := "false";
bar5_io_space : STRING := "false";
bar5_prefetchable : STRING := "false";
bar5_size_mask : INTEGER := 4;
bar_io_window_size : STRING := "NONE";
bar_prefetchable : INTEGER := 0;
base_address : INTEGER := 0;
bridge_port_ssid_support : STRING := "false";
bridge_port_vga_enable : STRING := "false";
bypass_cdc : STRING := "false";
bypass_tl : STRING := "false";
class_code : INTEGER := 16711680;
completion_timeout : STRING := "ABCD";
core_clk_divider : INTEGER := 1;
core_clk_source : STRING := "PLL_FIXED_CLK";
credit_buffer_allocation_aux : STRING := "BALANCED";
deemphasis_enable : STRING := "false";
device_address : INTEGER := 0;
device_id : INTEGER := 1;
device_number : INTEGER := 0;
diffclock_nfts_count : INTEGER := 128;
disable_async_l2_logic : STRING := "false"; -- july2,2008
disable_cdc_clk_ppm : STRING := "true";
disable_device_number_mismatch : STRING := "false";
disable_link_x2_support : STRING := "false";
disable_snoop_packet : STD_LOGIC_VECTOR(7 DOWNTO 0) := "00000000";
dll_active_report_support : STRING := "false";
ei_delay_powerdown_count : INTEGER := 10;
eie_before_nfts_count : INTEGER := 4;
enable_adapter_half_rate_mode : STRING := "false";
enable_ch0_pclk_out : STRING := "false";
enable_completion_timeout_disable : STRING := "true";
enable_coreclk_out_half_rate : STRING := "false";
enable_d1pm_support : STRING := "false";
enable_d2pm_support : STRING := "false";
enable_ecrc_check : STRING := "false";
enable_ecrc_gen : STRING := "false";
enable_function_msi_support : STRING := "true";
enable_function_msix_support : STRING := "false";
enable_gen2_core : STRING := "true";
enable_hip_x1_loopback : STRING := "false";
enable_l1_aspm : STRING := "false";
enable_msi_64bit_addressing : STRING := "true";
enable_msi_masking : STRING := "false";
enable_rcv0buf_a_we : STRING := "true";
enable_rcv0buf_b_re : STRING := "true";
enable_rcv0buf_output_regs : STRING := "false";
enable_rcv1buf_a_we : STRING := "true";
enable_rcv1buf_b_re : STRING := "true";
enable_rcv1buf_output_regs : STRING := "false";
enable_retrybuf_a_we : STRING := "true";
enable_retrybuf_b_re : STRING := "true";
enable_retrybuf_ecc : STRING := "false"; -- ww12
enable_retrybuf_output_regs : STRING := "false";
enable_retrybuf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx0buf_ecc : STRING := "false"; -- ww12
enable_rx0buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx1buf_ecc : STRING := "false"; -- ww12
enable_rx1buf_x8_clk_stealing : INTEGER := 0; -- ww12
enable_rx_buffer_checking : STRING := "false";
enable_rx_ei_l0s_exit_refined : STRING := "false";
enable_rx_reordering : STRING := "true";
enable_slot_register : STRING := "false";
endpoint_l0_latency : INTEGER := 0;
endpoint_l1_latency : INTEGER := 0;
expansion_base_address_register : INTEGER := 0;
extend_tag_field : STRING := "false";
fc_init_timer : INTEGER := 1024;
flow_control_timeout_count : INTEGER := 200;
flow_control_update_count : INTEGER := 30;
gen2_diffclock_nfts_count : INTEGER := 255;
gen2_lane_rate_mode : STRING := "false";
gen2_sameclock_nfts_count : INTEGER := 255;
hot_plug_support : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
iei_logic : STRING := "IEI_IIIS";
indicator : INTEGER := 7;
l01_entry_latency : INTEGER := 31;
l0_exit_latency_diffclock : INTEGER := 6;
l0_exit_latency_sameclock : INTEGER := 6;
l1_exit_latency_diffclock : INTEGER := 0;
l1_exit_latency_sameclock : INTEGER := 0;
lane_mask : STD_LOGIC_VECTOR(7 DOWNTO 0) := "11110000";
low_priority_vc : INTEGER := 0;
max_link_width : INTEGER := 4;
max_payload_size : INTEGER := 2;
maximum_current : INTEGER := 0;
migrated_from_prev_family : STRING := "false";
millisecond_cycle_count : INTEGER := 0;
mram_bist_settings : STRING := "";
msi_function_count : INTEGER := 2;
msix_pba_bir : INTEGER := 0;
msix_pba_offset : INTEGER := 0;
msix_table_bir : INTEGER := 0;
msix_table_offset : INTEGER := 0;
msix_table_size : INTEGER := 0;
no_command_completed : STRING := "true";
no_soft_reset : STRING := "false";
pcie_mode : STRING := "SHARED_MODE";
pme_state_enable : STD_LOGIC_VECTOR(4 DOWNTO 0) := "00000";
port_link_number : INTEGER := 1;
port_address : INTEGER := 0;
register_pipe_signals : STRING := "false";
retry_buffer_last_active_address : INTEGER := 2047;
retry_buffer_memory_settings : INTEGER := 0;
revision_id : INTEGER := 1;
rx0_adap_fifo_full_value : INTEGER := 9;
rx1_adap_fifo_full_value : INTEGER := 9;
rx_cdc_full_value : INTEGER := 12;
rx_idl_os_count : INTEGER := 0;
rx_ptr0_nonposted_dpram_max : INTEGER := 0;
rx_ptr0_nonposted_dpram_min : INTEGER := 0;
rx_ptr0_posted_dpram_max : INTEGER := 0;
rx_ptr0_posted_dpram_min : INTEGER := 0;
rx_ptr1_nonposted_dpram_max : INTEGER := 0;
rx_ptr1_nonposted_dpram_min : INTEGER := 0;
rx_ptr1_posted_dpram_max : INTEGER := 0;
rx_ptr1_posted_dpram_min : INTEGER := 0;
sameclock_nfts_count : INTEGER := 128;
single_rx_detect : INTEGER := 0;
skp_os_schedule_count : INTEGER := 0;
slot_number : INTEGER := 0;
slot_power_limit : INTEGER := 0;
slot_power_scale : INTEGER := 0;
ssid : INTEGER := 0;
ssvid : INTEGER := 0;
subsystem_device_id : INTEGER := 1;
subsystem_vendor_id : INTEGER := 4466;
surprise_down_error_support : STRING := "false";
tx0_adap_fifo_full_value : INTEGER := 11;
tx1_adap_fifo_full_value : INTEGER := 11;
tx_cdc_full_value : INTEGER := 12;
tx_cdc_stop_dummy_full_value : INTEGER := 11;
use_crc_forwarding : STRING := "false";
vc0_clk_enable : STRING := "true";
vc0_rx_buffer_memory_settings : INTEGER := 0;
vc0_rx_flow_ctrl_compl_data : INTEGER := 448;
vc0_rx_flow_ctrl_compl_header : INTEGER := 112;
vc0_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc0_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc0_rx_flow_ctrl_posted_data : INTEGER := 360;
vc0_rx_flow_ctrl_posted_header : INTEGER := 50;
vc1_clk_enable : STRING := "false";
vc1_rx_buffer_memory_settings : INTEGER := 0;
vc1_rx_flow_ctrl_compl_data : INTEGER := 448;
vc1_rx_flow_ctrl_compl_header : INTEGER := 112;
vc1_rx_flow_ctrl_nonposted_data : INTEGER := 0;
vc1_rx_flow_ctrl_nonposted_header : INTEGER := 54;
vc1_rx_flow_ctrl_posted_data : INTEGER := 360;
vc1_rx_flow_ctrl_posted_header : INTEGER := 50;
vc_arbitration : INTEGER := 1;
vc_enable : STD_LOGIC_VECTOR(6 DOWNTO 0) := "0000000";
vendor_id : INTEGER := 4466
);
PORT (
bistenrcv0 : IN STD_LOGIC := '0';
bistenrcv1 : IN STD_LOGIC := '0';
bistenrpl : IN STD_LOGIC := '0';
bistscanen : IN STD_LOGIC := '0';
bistscanin : IN STD_LOGIC := '0';
bisttesten : IN STD_LOGIC := '0';
coreclkin : IN STD_LOGIC := '0';
corecrst : IN STD_LOGIC := '0';
corepor : IN STD_LOGIC := '0';
corerst : IN STD_LOGIC := '0';
coresrst : IN STD_LOGIC := '0';
cplerr : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
cplpending : IN STD_LOGIC := '0';
dbgpipex1rx : IN STD_LOGIC_VECTOR(15 - 1 DOWNTO 0) := (others => '0');
dlaspmcr0 : IN STD_LOGIC := '0';
dlcomclkreg : IN STD_LOGIC := '0';
dlctrllink2 : IN STD_LOGIC_VECTOR(13 - 1 DOWNTO 0) := (others => '0');
dldataupfc : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
dlhdrupfc : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlinhdllp : IN STD_LOGIC := '1';
dlmaxploaddcr : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dlreqphycfg : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlreqphypm : IN STD_LOGIC_VECTOR(4 - 1 DOWNTO 0) := (others => '0');
dlrequpfc : IN STD_LOGIC := '0';
dlreqwake : IN STD_LOGIC := '0';
dlrxecrcchk : IN STD_LOGIC := '0';
dlsndupfc : IN STD_LOGIC := '0';
dltxcfgextsy : IN STD_LOGIC := '0';
dltxreqpm : IN STD_LOGIC := '0';
dltxtyppm : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dltypupfc : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
dlvcctrl : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
dlvcidmap : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
dlvcidupfc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
dpclk : IN STD_LOGIC := '0';
dpriodisable : IN STD_LOGIC := '1';
dprioin : IN STD_LOGIC := '0';
dprioload : IN STD_LOGIC := '0';
extrain : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmiaddr : IN STD_LOGIC_VECTOR(12 - 1 DOWNTO 0) := (others => '0');
lmidin : IN STD_LOGIC_VECTOR(32 - 1 DOWNTO 0) := (others => '0');
lmirden : IN STD_LOGIC := '0';
lmiwren : IN STD_LOGIC := '0';
mode : IN STD_LOGIC_VECTOR(2 - 1 DOWNTO 0) := (others => '0');
mramhiptestenable : IN STD_LOGIC := '0';
mramregscanen : IN STD_LOGIC := '0';
mramregscanin : IN STD_LOGIC := '0';
pclkcentral : IN STD_LOGIC := '0';
pclkch0 : IN STD_LOGIC := '0';
phyrst : IN STD_LOGIC := '0';
physrst : IN STD_LOGIC := '0';
phystatus : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
pldclk : IN STD_LOGIC := '0';
pldrst : IN STD_LOGIC := '0';
pldsrst : IN STD_LOGIC := '0';
pllfixedclk : IN STD_LOGIC := '0';
rxdata : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
rxdatak : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxelecidle : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
rxmaskvc0 : IN STD_LOGIC := '0';
rxmaskvc1 : IN STD_LOGIC := '0';
rxreadyvc0 : IN STD_LOGIC := '0';
rxreadyvc1 : IN STD_LOGIC := '0';
rxstatus : IN STD_LOGIC_VECTOR(24 - 1 DOWNTO 0) := (others => '0');
rxvalid : IN STD_LOGIC_VECTOR(8 - 1 DOWNTO 0) := (others => '0');
scanen : IN STD_LOGIC := '0';
scanmoden : IN STD_LOGIC := '0';
swdnin : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
swupin : IN STD_LOGIC_VECTOR(7 - 1 DOWNTO 0) := (others => '0');
testin : IN STD_LOGIC_VECTOR(40 - 1 DOWNTO 0) := (others => '0');
tlaermsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappintasts : IN STD_LOGIC := '0';
tlappmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlappmsireq : IN STD_LOGIC := '0';
tlappmsitc : IN STD_LOGIC_VECTOR(3 - 1 DOWNTO 0) := (others => '0');
tlhpgctrler : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpexmsinum : IN STD_LOGIC_VECTOR(5 - 1 DOWNTO 0) := (others => '0');
tlpmauxpwr : IN STD_LOGIC := '0';
tlpmdata : IN STD_LOGIC_VECTOR(10 - 1 DOWNTO 0) := (others => '0');
tlpmetocr : IN STD_LOGIC := '0';
tlpmevent : IN STD_LOGIC := '0';
tlslotclkcfg : IN STD_LOGIC := '0';
txdatavc00 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc01 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc10 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txdatavc11 : IN STD_LOGIC_VECTOR(64 - 1 DOWNTO 0) := (others => '0');
txeopvc00 : IN STD_LOGIC := '0';
txeopvc01 : IN STD_LOGIC := '0';
txeopvc10 : IN STD_LOGIC := '0';
txeopvc11 : IN STD_LOGIC := '0';
txerrvc0 : IN STD_LOGIC := '0';
txerrvc1 : IN STD_LOGIC := '0';
txsopvc00 : IN STD_LOGIC := '0';
txsopvc01 : IN STD_LOGIC := '0';
txsopvc10 : IN STD_LOGIC := '0';
txsopvc11 : IN STD_LOGIC := '0';
txvalidvc0 : IN STD_LOGIC := '0';
txvalidvc1 : IN STD_LOGIC := '0';
bistdonearcv0 : OUT STD_LOGIC;
bistdonearcv1 : OUT STD_LOGIC;
bistdonearpl : OUT STD_LOGIC;
bistdonebrcv0 : OUT STD_LOGIC;
bistdonebrcv1 : OUT STD_LOGIC;
bistdonebrpl : OUT STD_LOGIC;
bistpassrcv0 : OUT STD_LOGIC;
bistpassrcv1 : OUT STD_LOGIC;
bistpassrpl : OUT STD_LOGIC;
bistscanoutrcv0 : OUT STD_LOGIC;
bistscanoutrcv1 : OUT STD_LOGIC;
bistscanoutrpl : OUT STD_LOGIC;
clrrxpath : OUT STD_LOGIC;
coreclkout : OUT STD_LOGIC;
dataenablen : OUT STD_LOGIC;
derrcorextrcv0 : OUT STD_LOGIC;
derrcorextrcv1 : OUT STD_LOGIC;
derrcorextrpl : OUT STD_LOGIC;
derrrpl : OUT STD_LOGIC;
dlackphypm : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dlackrequpfc : OUT STD_LOGIC;
dlacksndupfc : OUT STD_LOGIC;
dlcurrentdeemp : OUT STD_LOGIC;
dlcurrentspeed : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
dldllreq : OUT STD_LOGIC;
dlerrdll : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlerrphy : OUT STD_LOGIC;
dllinkautobdwstatus : OUT STD_LOGIC;
dllinkbdwmngstatus : OUT STD_LOGIC;
dlltssm : OUT STD_LOGIC_VECTOR(5 - 1 DOWNTO 0);
dlrpbufemp : OUT STD_LOGIC;
dlrstentercompbit : OUT STD_LOGIC;
dlrsttxmarginfield : OUT STD_LOGIC;
dlrxtyppm : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
dlrxvalpm : OUT STD_LOGIC;
dltxackpm : OUT STD_LOGIC;
dlup : OUT STD_LOGIC;
dlupexit : OUT STD_LOGIC;
dlvcstatus : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
dprioout : OUT STD_LOGIC;
dpriostate : OUT STD_LOGIC_VECTOR(3 - 1 DOWNTO 0);
eidleinfersel : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
ev128ns : OUT STD_LOGIC;
ev1us : OUT STD_LOGIC;
extraclkout : OUT STD_LOGIC_VECTOR(2 - 1 DOWNTO 0);
extraout : OUT STD_LOGIC_VECTOR(15 - 1 DOWNTO 0);
gen2rate : OUT STD_LOGIC;
gen2rategnd : OUT STD_LOGIC;
hotrstexit : OUT STD_LOGIC;
intstatus : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
l2exit : OUT STD_LOGIC;
laneact : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
linkup : OUT STD_LOGIC;
lmiack : OUT STD_LOGIC;
lmidout : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
ltssml0state : OUT STD_LOGIC;
mramregscanout : OUT STD_LOGIC;
powerdown : OUT STD_LOGIC_VECTOR(16 - 1 DOWNTO 0);
resetstatus : OUT STD_LOGIC;
rxbardecvc0 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbardecvc1 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc00 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc01 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc10 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxbevc11 : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxdatavc00 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc01 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc10 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxdatavc11 : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
rxeopvc00 : OUT STD_LOGIC;
rxeopvc01 : OUT STD_LOGIC;
rxeopvc10 : OUT STD_LOGIC;
rxeopvc11 : OUT STD_LOGIC;
rxerrvc0 : OUT STD_LOGIC;
rxerrvc1 : OUT STD_LOGIC;
rxfifoemptyvc0 : OUT STD_LOGIC;
rxfifoemptyvc1 : OUT STD_LOGIC;
rxfifofullvc0 : OUT STD_LOGIC;
rxfifofullvc1 : OUT STD_LOGIC;
rxfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
rxpolarity : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
rxsopvc00 : OUT STD_LOGIC;
rxsopvc01 : OUT STD_LOGIC;
rxsopvc10 : OUT STD_LOGIC;
rxsopvc11 : OUT STD_LOGIC;
rxvalidvc0 : OUT STD_LOGIC;
rxvalidvc1 : OUT STD_LOGIC;
r2cerr0ext : OUT STD_LOGIC;
serrout : OUT STD_LOGIC;
successspeednegoint : OUT STD_LOGIC;
swdnwake : OUT STD_LOGIC;
swuphotrst : OUT STD_LOGIC;
testout : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
tlappintaack : OUT STD_LOGIC;
tlappmsiack : OUT STD_LOGIC;
tlcfgadd : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
tlcfgctl : OUT STD_LOGIC_VECTOR(32 - 1 DOWNTO 0);
tlcfgctlwr : OUT STD_LOGIC;
tlcfgsts : OUT STD_LOGIC_VECTOR(53 - 1 DOWNTO 0);
tlcfgstswr : OUT STD_LOGIC;
tlpmetosr : OUT STD_LOGIC;
txcompl : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txcredvc0 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txcredvc1 : OUT STD_LOGIC_VECTOR(36 - 1 DOWNTO 0);
txdata : OUT STD_LOGIC_VECTOR(64 - 1 DOWNTO 0);
txdatak : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdeemph : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txdetectrx : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txelecidle : OUT STD_LOGIC_VECTOR(8 - 1 DOWNTO 0);
txfifoemptyvc0 : OUT STD_LOGIC;
txfifoemptyvc1 : OUT STD_LOGIC;
txfifofullvc0 : OUT STD_LOGIC;
txfifofullvc1 : OUT STD_LOGIC;
txfifordpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifordpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc0 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txfifowrpvc1 : OUT STD_LOGIC_VECTOR(4 - 1 DOWNTO 0);
txmargin : OUT STD_LOGIC_VECTOR(24 - 1 DOWNTO 0);
txreadyvc0 : OUT STD_LOGIC;
txreadyvc1 : OUT STD_LOGIC;
wakeoen : OUT STD_LOGIC
);
END COMPONENT;
end stratixiv_pcie_hip_components;
package body STRATIXIV_PCIE_HIP_COMPONENTS is
function str2bin (s : string) return std_logic_vector is
variable len : integer := s'length;
variable result : std_logic_vector(len -1 DOWNTO 0) := (OTHERS => '0');
variable i : integer;
begin
for i in 1 to len loop
case s(i) is
when '0' => result(len - i) := '0';
when '1' => result(len - i) := '1';
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
end loop;
return result;
end;
function str2int (s : string) return integer is
variable len : integer := s'length;
variable newdigit : integer := 0;
variable sign : integer := 1;
variable digit : integer := 0;
begin
for i in 1 to len loop
case s(i) is
when '-' =>
if i = 1 then
sign := -1;
else
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "i n string parameter! " SEVERITY ERROR;
end if;
when '0' =>
digit := 0;
when '1' =>
digit := 1;
when '2' =>
digit := 2;
when '3' =>
digit := 3;
when '4' =>
digit := 4;
when '5' =>
digit := 5;
when '6' =>
digit := 6;
when '7' =>
digit := 7;
when '8' =>
digit := 8;
when '9' =>
digit := 9;
when others =>
ASSERT FALSE
REPORT "Illegal Character "& s(i) & "in string parameter! "
SEVERITY ERROR;
end case;
newdigit := newdigit * 10 + digit;
end loop;
return (sign*newdigit);
end;
function int2bin (arg : integer; size : integer) return std_logic_vector is
variable int_val : integer := arg;
variable result : std_logic_vector(size-1 downto 0);
begin
for i in 0 to result'left loop
if ((int_val mod 2) = 0) then
result(i) := '0';
else
result(i) := '1';
end if;
int_val := int_val/2;
end loop;
return result;
end int2bin;
function int2bin (arg : boolean; size : integer) return std_logic_vector is
variable result : std_logic_vector(size-1 downto 0);
begin
if(arg)then
result := (OTHERS => '1');
else
result := (OTHERS => '0');
end if;
return result;
end int2bin;
function tx_top_ctrl_in_width(double_data_mode : string;
ser_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (ser_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (ser_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end tx_top_ctrl_in_width;
function rx_top_a1k1_out_width(des_double_data_mode : string) return integer is
variable real_widthb : integer;
begin
if (des_double_data_mode = "true") then
real_widthb := 2;
else
real_widthb := 1;
end if;
return real_widthb;
end rx_top_a1k1_out_width;
function rx_top_ctrl_out_width(double_data_mode : string;
des_double_data_mode : string
) return integer is
variable real_widthb : integer;
begin
real_widthb := 1;
if (des_double_data_mode = "true" AND double_data_mode = "true") then
real_widthb := 4;
elsif (des_double_data_mode = "false" AND double_data_mode = "false") then
real_widthb := 1;
else
real_widthb := 2;
end if;
return real_widthb;
end rx_top_ctrl_out_width;
function hssiSelectDelay (CONSTANT Paths : IN VitalPathArray01Type) return TIME IS
variable Temp : TIME;
variable TransitionTime : TIME := TIME'HIGH;
variable PathDelay : TIME := TIME'HIGH;
begin
for i IN Paths'RANGE loop
next when not Paths(i).PathCondition;
next when Paths(i).InputChangeTime > TransitionTime;
Temp := Paths(i).PathDelay(tr01);
if Paths(i).InputChangeTime < TransitionTime then
PathDelay := Temp;
else
if Temp < PathDelay then
PathDelay := Temp;
end if;
end if;
TransitionTime := Paths(i).InputChangeTime;
end loop;
return PathDelay;
end;
function bin2int (s : std_logic_vector) return integer is
constant temp : std_logic_vector(s'high-s'low DOWNTO 0) := s;
variable result : integer := 0;
begin
for i in temp'range loop
if (temp(i) = '1') then
result := result + (2**i);
end if;
end loop;
return(result);
end bin2int;
function bin2int (s : std_logic) return integer is
constant temp : std_logic := s;
variable result : integer := 0;
begin
if (temp = '1') then
result := 1;
else
result := 0;
end if;
return(result);
end bin2int;
function int2bit (arg : integer) return std_logic is
variable int_val : integer := arg;
variable result : std_logic;
begin
if (int_val = 0) then
result := '0';
else
result := '1';
end if;
return result;
end int2bit;
function int2bit (arg : boolean) return std_logic is
variable int_val : boolean := arg;
variable result : std_logic;
begin
if (int_val ) then
result := '1';
else
result := '0';
end if;
return result;
end int2bit;
function mux_select (sel : boolean; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : boolean; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel) then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic_vector; data2 : std_logic_vector) return std_logic_vector is
variable dataout : std_logic_vector(data1'range);
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function mux_select (sel : bit; data1 : std_logic; data2 : std_logic) return std_logic is
variable dataout : std_logic;
begin
if(sel = '1') then
dataout := data1;
else
dataout := data2;
end if;
return (dataout);
end mux_select;
function reduction_or (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(result);
end reduction_or;
function reduction_nor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result or val(i);
end loop;
return(not result);
end reduction_nor;
function reduction_xor (
val : std_logic_vector) return std_logic is
variable result : std_logic := '0';
begin
for i in val'range loop
result := result xor val(i);
end loop;
return(result);
end reduction_xor;
function reduction_and (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(result);
end reduction_and;
function reduction_nand (
val : std_logic_vector) return std_logic is
variable result : std_logic := '1';
begin
for i in val'range loop
result := result and val(i);
end loop;
return(not result);
end reduction_nand;
function alpha_tolower (given_string : string) return string is
-- VARIABLE DECLARATION
variable string_length : integer := given_string'length;
variable result_string : string(1 to 25) := " ";
begin
for i in 1 to string_length loop
case given_string(i) is
when 'A' => result_string(i) := 'a';
when 'B' => result_string(i) := 'b';
when 'C' => result_string(i) := 'c';
when 'D' => result_string(i) := 'd';
when 'E' => result_string(i) := 'e';
when 'F' => result_string(i) := 'f';
when 'G' => result_string(i) := 'g';
when 'H' => result_string(i) := 'h';
when 'I' => result_string(i) := 'i';
when 'J' => result_string(i) := 'j';
when 'K' => result_string(i) := 'k';
when 'L' => result_string(i) := 'l';
when 'M' => result_string(i) := 'm';
when 'N' => result_string(i) := 'n';
when 'O' => result_string(i) := 'o';
when 'P' => result_string(i) := 'p';
when 'Q' => result_string(i) := 'q';
when 'R' => result_string(i) := 'r';
when 'S' => result_string(i) := 's';
when 'T' => result_string(i) := 't';
when 'U' => result_string(i) := 'u';
when 'V' => result_string(i) := 'v';
when 'W' => result_string(i) := 'w';
when 'X' => result_string(i) := 'x';
when 'Y' => result_string(i) := 'y';
when 'Z' => result_string(i) := 'z';
when others => result_string(i) := given_string(i);
end case;
end loop;
return (result_string(1 to string_length));
end alpha_tolower;
end STRATIXIV_PCIE_HIP_COMPONENTS;
|
-- -*- vhdl -*-
-------------------------------------------------------------------------------
-- Copyright (c) 2012, The CARPE Project, All rights reserved. --
-- See the AUTHORS file for individual contributors. --
-- --
-- Copyright and related rights are licensed under the Solderpad --
-- Hardware License, Version 0.51 (the "License"); you may not use this --
-- file except in compliance with the License. You may obtain a copy of --
-- the License at http://solderpad.org/licenses/SHL-0.51. --
-- --
-- Unless required by applicable law or agreed to in writing, software, --
-- hardware and materials distributed under this License is distributed --
-- on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, --
-- either express or implied. See the License for the specific language --
-- governing permissions and limitations under the License. --
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
architecture rtl of syncram_1r1w_inferred is
constant memory_size : natural := 2**addr_bits;
type memory_type is array(0 to memory_size-1) of std_ulogic_vector((data_bits-1) downto 0);
signal memory : memory_type
-- pragma translate_off
:= (others => (others => '0'));
-- pragma translate_on
;
type reg_type is record
raddr : std_ulogic_vector(addr_bits-1 downto 0);
end record;
signal r : reg_type;
pure function conv_addr (addr : std_ulogic_vector(addr_bits-1 downto 0)) return natural is
begin
if addr_bits > 0 then
return to_integer(unsigned(addr));
else
return 0;
end if;
end function;
begin
write_first_true_gen: if write_first generate
rdata <= memory(conv_addr(r.raddr));
main : process(clk)
begin
if rising_edge(clk) then
if re = '1' then
r.raddr <= raddr;
end if;
if we = '1' then
if addr_bits > 0 then
memory(conv_addr(waddr)) <= wdata;
else
memory(0) <= wdata;
end if;
end if;
end process;
end generate;
write_first_false_gen: if not write_first generate
main : process(clk)
begin
if rising_edge(clk) then
if re = '1' then
if addr_bits > 0 then
r.rdata <= memory(conv_addr(raddr));
else
r.rdata <= memory(0);
end if;
end if;
if we = '1' then
if addr_bits > 0 then
memory(conv_addr(waddr)) <= wdata;
else
memory(0) <= wdata;
end if
end if;
end if;
end generate;
end;
|
-------------------------------------------------------------------------------
-- Title : Exercise
-- Project : Counter
-------------------------------------------------------------------------------
-- File : bin2bcd.vhd
-- Author : Martin Angermair
-- Company : Technikum Wien, Embedded Systems
-- Last update: 24.10.2017
-- Platform : ModelSim
-------------------------------------------------------------------------------
-- Description: Converts a binary vector into a bcd coded number
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 27.10.2017 0.1 Martin Angermair init
-- 19.11.2017 1.0 Martin Angermair final version
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
architecture rtl of bin2bcd is
begin
process(digits_i)
variable z: std_logic_vector(32 downto 0);
begin
for i in 0 to 32 loop
z(i) := '0';
end loop;
z(16 downto 3) := digits_i;
for i in 0 to 10 loop
if z(17 downto 14) > 4 then
z(17 downto 14) := z(17 downto 14) + 3;
end if;
if z(21 downto 18) > 4 then
z(21 downto 18) := z(21 downto 18) + 3;
end if;
if z(25 downto 22) > 4 then
z(25 downto 22) := z(25 downto 22) + 3;
end if;
if z(29 downto 26) > 4 then
z(29 downto 26) := z(29 downto 26) + 3;
end if;
z(32 downto 1) := z(31 downto 0);
end loop;
bcd_o <= z(30 downto 14);
end process;
end rtl; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity rstkey is
port
(
rstkey_port_rst: in std_logic;
rstkey_rst: out std_logic
);
end rstkey;
architecture Behavioral of rstkey is
begin
rstkey_rst <= rstkey_port_rst;
end Behavioral;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural := nested_function;
begin
result := bar;
end;
end package body;
-------------------------------------------------------------------------------
entity issue122 is
end entity;
use work.nested_function_bug.all;
architecture test of issue122 is
begin
process is
variable r : integer;
begin
proc(5, r);
assert r = 10;
wait;
end process;
end architecture;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural := nested_function;
begin
result := bar;
end;
end package body;
-------------------------------------------------------------------------------
entity issue122 is
end entity;
use work.nested_function_bug.all;
architecture test of issue122 is
begin
process is
variable r : integer;
begin
proc(5, r);
assert r = 10;
wait;
end process;
end architecture;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural := nested_function;
begin
result := bar;
end;
end package body;
-------------------------------------------------------------------------------
entity issue122 is
end entity;
use work.nested_function_bug.all;
architecture test of issue122 is
begin
process is
variable r : integer;
begin
proc(5, r);
assert r = 10;
wait;
end process;
end architecture;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural := nested_function;
begin
result := bar;
end;
end package body;
-------------------------------------------------------------------------------
entity issue122 is
end entity;
use work.nested_function_bug.all;
architecture test of issue122 is
begin
process is
variable r : integer;
begin
proc(5, r);
assert r = 10;
wait;
end process;
end architecture;
|
package nested_function_bug is
procedure proc(param : integer; result : out integer);
end package;
package body nested_function_bug is
procedure proc(param : integer; result : out integer) is
impure function nested_function return integer is
begin
return param * 2;
end;
variable bar : natural := nested_function;
begin
result := bar;
end;
end package body;
-------------------------------------------------------------------------------
entity issue122 is
end entity;
use work.nested_function_bug.all;
architecture test of issue122 is
begin
process is
variable r : integer;
begin
proc(5, r);
assert r = 10;
wait;
end process;
end architecture;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1243.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01243ent IS
END c08s02b00x00p04n01i01243ent;
ARCHITECTURE c08s02b00x00p04n01i01243arch OF c08s02b00x00p04n01i01243ent IS
BEGIN
TESTING: PROCESS
variable N2 : Character := 'R';
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01243 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01243arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1243.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01243ent IS
END c08s02b00x00p04n01i01243ent;
ARCHITECTURE c08s02b00x00p04n01i01243arch OF c08s02b00x00p04n01i01243ent IS
BEGIN
TESTING: PROCESS
variable N2 : Character := 'R';
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01243 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01243arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1243.vhd,v 1.2 2001-10-26 16:30:07 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c08s02b00x00p04n01i01243ent IS
END c08s02b00x00p04n01i01243ent;
ARCHITECTURE c08s02b00x00p04n01i01243arch OF c08s02b00x00p04n01i01243ent IS
BEGIN
TESTING: PROCESS
variable N2 : Character := 'R';
BEGIN
assert FALSE
report N2
severity NOTE;
assert FALSE
report "***FAILED TEST: c08s02b00x00p04n01i01243 - Expression type used in a report clause should be STRING"
severity ERROR;
wait;
END PROCESS TESTING;
END c08s02b00x00p04n01i01243arch;
|
-------------------------------------------------------------------------------
-- FILE NAME : GPR.vhd
-- MODULE NAME : GPR
-- AUTHOR : Bogdan Ardelean
-- AUTHOR'S EMAIL : [email protected]
-------------------------------------------------------------------------------
-- REVISION HISTORY
-- VERSION DATE AUTHOR DESCRIPTION
-- 1.0 2016-05-2 Bogdan Ardelean Created
-------------------------------------------------------------------------------
-- DESCRIPTION : General Purpose Registers
--
-------------------------------------------------------------------------------
library ieee;
library xil_defaultlib;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.FpwamPkg.all;
entity GPR is
generic
(
kAddressWidth : natural := 4;
kWordWidth : natural := 16
);
port
(
--Common
clk : in std_logic;
address1 : in std_logic_vector(kAddressWidth - 1 downto 0);
wr1 : in std_logic;
input_word1 : in std_logic_vector(kWordWidth - 1 downto 0);
output_word1 : out std_logic_vector(kWordWidth - 1 downto 0);
address2 : in std_logic_vector(kAddressWidth - 1 downto 0);
wr2 : in std_logic;
input_word2 : in std_logic_vector(kWordWidth - 1 downto 0);
output_word2 : out std_logic_vector(kWordWidth - 1 downto 0)
);
end GPR;
architecture Behavioral of GPR is
type sram is array (0 to 2**kAddressWidth) of std_logic_vector(kWordWidth - 1 downto 0);
signal RAM : sram := (others => (others => '0'));
begin
WRITE_PROCESS: process(clk)
begin
if rising_edge(clk) then
if wr1 = '1' then
RAM(to_integer(unsigned(address1))) <= input_word1;
end if;
if wr2 = '1' then
RAM(to_integer(unsigned(address2))) <= input_word2;
end if;
end if;
end process;
output_word1 <= RAM(to_integer(unsigned(address1)));
output_word2 <= RAM(to_integer(unsigned(address2)));
end Behavioral;
|
-- -----------------------------------------------------------------------
--
-- Company: INVEA-TECH a.s.
--
-- Project: IPFIX design
--
-- -----------------------------------------------------------------------
--
-- (c) Copyright 2011 INVEA-TECH a.s.
-- All rights reserved.
--
-- Please review the terms of the license agreement before using this
-- file. If you are not an authorized user, please destroy this
-- source code file and notify INVEA-TECH a.s. immediately that you
-- inadvertently received an unauthorized copy.
--
-- -----------------------------------------------------------------------
--
-- fsm_master.vhd: FSM controlling asynchronous transfer at master side
-- Copyright (C) 2006 CESNET
-- Author(s): Viktor Pus <[email protected]>
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in
-- the documentation and/or other materials provided with the
-- distribution.
-- 3. Neither the name of the Company nor the names of its contributors
-- may be used to endorse or promote products derived from this
-- software without specific prior written permission.
--
-- This software is provided ``as is'', and any express or implied
-- warranties, including, but not limited to, the implied warranties of
-- merchantability and fitness for a particular purpose are disclaimed.
-- In no event shall the company or contributors be liable for any
-- direct, indirect, incidental, special, exemplary, or consequential
-- damages (including, but not limited to, procurement of substitute
-- goods or services; loss of use, data, or profits; or business
-- interruption) however caused and on any theory of liability, whether
-- in contract, strict liability, or tort (including negligence or
-- otherwise) arising in any way out of the use of this software, even
-- if advised of the possibility of such damage.
--
-- $Id: fsm_master.vhd 14 2007-07-31 06:44:05Z kosek $
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
-- ----------------------------------------------------------------------------
-- Entity declaration
-- ----------------------------------------------------------------------------
entity MI32_ASYNC_FSMM is
port(
RESET : in std_logic;
CLK : in std_logic;
RD : in std_logic;
WR : in std_logic;
ACK : in std_logic;
REQ : out std_logic;
ARDY : out std_logic;
DONE : out std_logic
);
end entity MI32_ASYNC_FSMM;
-- ----------------------------------------------------------------------------
-- Architecture
-- ----------------------------------------------------------------------------
architecture full of MI32_ASYNC_FSMM is
type t_fsmm is (wait_for_op, wait_for_ack, wait_for_nack);
signal fsm : t_fsmm;
signal fsm_next : t_fsmm;
signal sig_req : std_logic;
signal sig_ardy : std_logic;
begin
fsm_p : process(CLK, RESET)
begin
if RESET = '1' then
fsm <= wait_for_op;
elsif CLK'event and CLK = '1' then
fsm <= fsm_next;
end if;
end process;
fsm_next_p : process(fsm, RD, WR, ACK)
begin
fsm_next <= fsm;
case fsm is
when wait_for_op =>
if RD = '1' or WR = '1' then
fsm_next <= wait_for_ack;
end if;
when wait_for_ack =>
if ACK = '1' then
fsm_next <= wait_for_nack;
end if;
when wait_for_nack =>
if ACK = '0' then
fsm_next <= wait_for_op;
end if;
end case;
end process;
REQ <= '1' when fsm = wait_for_ack else
'0';
ARDY <= '1' when fsm = wait_for_op else
'0';
DONE <= '1' when fsm = wait_for_ack and ACK = '1' else
'0';
end architecture full;
|
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myreset <= reset or t;
f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
end bigcount_rtl;
|
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myreset <= reset or t;
f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
end bigcount_rtl;
|
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myreset <= reset or t;
f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
end bigcount_rtl;
|
library ieee;
library uselib;
use ieee.std_logic_1164.all;
use uselib.work7.all;
entity bigcount is
port (clk, reset: in std_logic;
count: out std_logic_vector (24 downto 0)
);
end entity bigcount;
architecture bigcount_rtl of bigcount is
signal d, t, q, myreset: std_logic;
begin
d <= t xor q;
myreset <= reset or t;
f1: fdc port map (clk => clk, reset => reset, d => d, q => q);
tb: timebase port map (CLOCK => clk, RESET => myreset, ENABLE => '1', TICK => t, COUNT_VALUE => open );
counting: timebase port map (CLOCK => clk, RESET => reset, ENABLE => q, TICK => open, COUNT_VALUE => count );
end bigcount_rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d1_A_shiftReg;
architecture rtl of fifo_w8_d1_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d1_A is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d1_A is
component fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d1_A_shiftReg : fifo_w8_d1_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d1_A_shiftReg;
architecture rtl of fifo_w8_d1_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d1_A is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d1_A is
component fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d1_A_shiftReg : fifo_w8_d1_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w8_d1_A_shiftReg;
architecture rtl of fifo_w8_d1_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w8_d1_A is
generic (
MEM_STYLE : string := "auto";
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w8_d1_A is
component fifo_w8_d1_A_shiftReg is
generic (
DATA_WIDTH : integer := 8;
ADDR_WIDTH : integer := 1;
DEPTH : integer := 2);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w8_d1_A_shiftReg : fifo_w8_d1_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: sdram_phy
-- File: sdram_phy.vhd
-- Author: Jan Andersson - Aeroflex Gaisler
-- Description: SDRAM PHY with tech mapping, includes pads and can be
-- implemented with registers on all signals.
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib;
use grlib.stdlib.all;
library techmap;
use techmap.gencomp.all;
use techmap.allpads.all;
entity sdram_phy is
generic (
tech : integer := spartan3;
oepol : integer := 0;
level : integer := 0;
voltage : integer := x33v;
strength : integer := 12;
aw : integer := 15; -- # address bits
dw : integer := 32; -- # data bits
ncs : integer := 2;
reg : integer := 0); -- 1: include registers on all signals
port (
-- SDRAM interface
addr : out std_logic_vector(aw-1 downto 0);
dq : inout std_logic_vector(dw-1 downto 0);
cke : out std_logic_vector(ncs-1 downto 0);
sn : out std_logic_vector(ncs-1 downto 0);
wen : out std_ulogic;
rasn : out std_ulogic;
casn : out std_ulogic;
dqm : out std_logic_vector(dw/8-1 downto 0);
-- Interface toward memory controller
laddr : in std_logic_vector(aw-1 downto 0);
ldq_din : out std_logic_vector(dw-1 downto 0);
ldq_dout : in std_logic_vector(dw-1 downto 0);
ldq_oen : in std_logic_vector(dw-1 downto 0);
lcke : in std_logic_vector(ncs-1 downto 0);
lsn : in std_logic_vector(ncs-1 downto 0);
lwen : in std_ulogic;
lrasn : in std_ulogic;
lcasn : in std_ulogic;
ldqm : in std_logic_vector(dw/8-1 downto 0);
-- Only used when reg generic is non-zero
rstn : in std_ulogic; -- Registered pads reset
clk : in std_ulogic; -- SDRAM clock for registered pads
-- Optional pad configuration inputs
cfgi_cmd : in std_logic_vector(19 downto 0) := "00000000000000000000"; -- CMD pads
cfgi_dq : in std_logic_vector(19 downto 0) := "00000000000000000000" -- DQ pads
);
end;
architecture rtl of sdram_phy is
signal laddrx : std_logic_vector(aw-1 downto 0);
signal ldq_dinx : std_logic_vector(dw-1 downto 0);
signal ldq_doutx : std_logic_vector(dw-1 downto 0);
signal ldq_oenx : std_logic_vector(dw-1 downto 0);
signal lckex : std_logic_vector(ncs-1 downto 0);
signal lsnx : std_logic_vector(ncs-1 downto 0);
signal lwenx : std_ulogic;
signal lrasnx : std_ulogic;
signal lcasnx : std_ulogic;
signal ldqmx : std_logic_vector(dw/8-1 downto 0);
signal oen : std_ulogic;
signal voen : std_logic_vector(dw-1 downto 0);
-- Determines if there is a customized phy available for target tech,
-- otherwise a generic PHY will be built
constant has_sdram_phy : tech_ability_type :=
(easic45 => 1, others => 0);
-- Determines if target tech has pads with built in registers (or rather if
-- target technology requires special pad instantiations in order to get
-- registers into pad ring).
constant tech_has_padregs : tech_ability_type :=
(easic45 => 1, others => 0);
begin
oen <= not ldq_oen(0) when padoen_polarity(tech) /= oepol else ldq_oen(0);
voen <= not ldq_oen when padoen_polarity(tech) /= oepol else ldq_oen;
nopadregs : if (reg = 0) or (tech_has_padregs(tech) /= 0) generate
laddrx <= laddr;
ldq_din <= ldq_dinx;
ldq_doutx <= ldq_dout;
ldq_oenx <= voen;
lckex <= lcke;
lsnx <= lsn;
lwenx <= lwen;
lrasnx <= lrasn;
lcasnx <= lcasn;
ldqmx <= ldqm;
end generate;
padregs : if (reg /= 0) and (tech_has_padregs(tech) = 0) generate
regproc : process(clk, rstn)
begin
if rising_edge(clk) then
laddrx <= laddr;
ldq_din <= ldq_dinx;
ldq_doutx <= ldq_dout;
ldq_oenx <= (others => oen);
lckex <= lcke;
lsnx <= lsn;
lwenx <= lwen;
lrasnx <= lrasn;
lcasnx <= lcasn;
ldqmx <= ldqm;
end if;
if rstn = '0' then
lsnx <= (others => '1');
for i in ldq_oenx'range loop
ldq_oenx(i) <= conv_std_logic(padoen_polarity(tech) = 0);
end loop;
end if;
end process;
end generate;
gen : if has_sdram_phy(tech) = 0 generate
-- SDRAM address
sa_pad : outpadv
generic map (
width => aw,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (addr, laddrx, cfgi_cmd);
-- SDRAM data
sd_pad : iopadvv
generic map (
width => dw,
tech => tech,
level => level,
voltage => voltage,
strength => strength,
oepol => padoen_polarity(tech))
port map (dq, ldq_doutx, ldq_oenx, ldq_dinx, cfgi_dq);
-- SDRAM clock enable
sdcke_pad : outpadv
generic map (
width => ncs,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (cke, lckex, cfgi_cmd);
-- SDRAM write enable
sdwen_pad : outpad generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (wen, lwenx, cfgi_cmd);
-- SDRAM chip select
sdcsn_pad : outpadv
generic map (
width => ncs,
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (sn, lsnx, cfgi_cmd);
-- SDRAM ras
sdras_pad : outpad
generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (rasn, lrasnx, cfgi_cmd);
-- SDRAM cas
sdcas_pad : outpad
generic map (
tech => tech,
level => level,
voltage => voltage,
strength => strength)
port map (casn, lcasnx, cfgi_cmd);
-- SDRAM dqm
sddqm_pad : outpadv
generic map (
width => dw/8,
level => level,
voltage => voltage,
tech => tech,
strength => strength)
port map (dqm, ldqmx, cfgi_cmd);
end generate;
n2x : if (tech = easic45) generate
phy0 : n2x_sdram_phy
generic map (
level => level, voltage => voltage, strength => strength,
aw => aw, dw => dw, ncs => ncs, reg => reg)
port map (
addr, dq, cke, sn, wen, rasn, casn, dqm,
laddrx, ldq_dinx, ldq_doutx, ldq_oenx, lckex,
lsnx, lwenx, lrasnx, lcasnx, ldqmx,
rstn, clk,
cfgi_cmd, cfgi_dq);
end generate;
end;
|
----------------------------------------------------------------------------------------------------
-- Linear Feedback Shift Register
----------------------------------------------------------------------------------------------------
-- Matthew Dallmeyer - [email protected]
----------------------------------------------------------------------------------------------------
-- PACKAGE
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package lfsr_pkg is
component lfsr is
port( clk : in std_logic;
rst : in std_logic;
poly_mask : in std_logic_vector;
seed : in std_logic_vector;
feedin : in std_logic_vector;
feedout : out std_logic_vector;
history : out std_logic_vector);
end component;
function xor_Reduce(bits: std_logic_vector) return std_logic;
end package;
----------------------------------------------------------------------------------------------------
-- PACKAGE BODY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package body lfsr_pkg is
-- XOR's all the bits in a vector. Useful for checking the parity of a vector.
-- bits: Logic vector
-- returns: result of all the bits XOR'd together
function xor_Reduce(bits: std_logic_vector) return std_logic is
begin
if(bits'low = bits'high) then
return bits(bits'low);
else
if(bits'ascending) then
return bits(bits'low) xor xor_Reduce(bits(bits'low+1 to bits'high));
else
return bits(bits'low) xor xor_Reduce(bits(bits'high downto bits'low+1));
end if;
end if;
end function;
end package body;
----------------------------------------------------------------------------------------------------
-- ENTITY
----------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.lfsr_pkg.all;
use work.reduce_pkg.reduce_xor;
--Linear feedback shift register
--Using this module requires that the feedout be fed-back into feedin at some point. The feedback
--would normally be done internally, except some designs require modifying the feedback before
--returning it to the shift register. To support such robust designs the feedback is always
--expected to be performed at a higher level, even when simple feedback is all that is required
--(e.g. feedin<=feedout;)
entity lfsr is
port( --Process clock, on every rising edge the LFSR updates the feedback with a new value and
--shifts previous values into the history.
clk : in std_logic;
--Asynchronous reset. While high: resets the LFSR to the seed value and sets the poly_mask
--used for the feedback polynomial
rst : in std_logic;
--Place '1's in the bits where the polynomial calls for taps. Read up on LFSR's before
--selecting a polynomial, not all choices will yield "good" random numbers.
--(e.g. X^5 + X^3 + 1 would be poly_mask(4 downto 0) <= "10100";)
poly_mask : in std_logic_vector;
--Must be identical in length to poly_mask. Initial value of the shift register. Is only
--set during rst = '1'. DO NOT SET TO ALL '0's
seed : in std_logic_vector;
--Return path for the feedback. Feeds directly into the shift register.
feedin : in std_logic_vector;
--Outbound path of the feedback. This value is the result of the polynomial. Feedback
--this value to this module using feedin port. Some designs call for xor'ing this value
--with another value before returning to feedin. Wider feedback signal generate multiple
--feedback bits per clock cycle, but can be difficult for timing.
feedout : out std_logic_vector;
--This output contains the history of the feedback which is also used to calculate the
--subsequent feedback. The history has to be seeded, hence the seed input. It can also
--be used to source pseudorandom values.
history : out std_logic_vector);
end lfsr;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE (structural)
----------------------------------------------------------------------------------------------------
architecture structural of lfsr is
signal poly_mask_reg : std_logic_vector(poly_mask'range) := (others => '0');
--All of these internal signals need to be defined in the same 0-to-'length range-order to make
--optimal use of the 'range attribute
signal shift_reg : std_logic_vector(0 to (feedin'length + poly_mask'length-1)) := (others => '0');
alias data_in : std_logic_vector(0 to (feedin'length-1)) is shift_reg(0 to (feedin'length-1));
alias polynomial : std_logic_vector(0 to (poly_mask'length-1)) is shift_reg(feedin'length to (feedin'length + poly_mask'length-1));
signal result : std_logic_vector(0 to (feedout'length-1)) := (others => '0');
begin
--load the left-most bits of shift_reg with the feedin
data_in <= feedin;
--Process to shift the feedback through a shift-register
shifter: process(clk, rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
--Typical vector assignments preserve the left-to-right bit order. We need to preserve the
--0 to n order for this assignment. The seed may not always be defined 0-to-n, but at
--least we know polynomial is 0-to-n.
for n in seed'low to seed'high loop
polynomial(n-seed'low) <= seed(n);
end loop;
--Set the polynomial mask when only while reset is asserted.
poly_mask_reg <= poly_mask;
else
--shift_reg is a concatenation of data_in and polynomial. By assigning the left-most
--bits of shift_reg to polynomial(the right-most bits), we achieve a right shift.
polynomial <= shift_reg(polynomial'range);
end if;
end if;
end process;
--The shift register updates every clock cycle, when it does, this generate loop calculates the
--feedback result. The result is the modulus-2 summation of specified polynomial taps.
--Modulus-2 addition is simply an xor operation.
calc_feedback: for outbit in result'reverse_range generate
signal polynomial_window : std_logic_vector(polynomial'range);
signal final_polynomial : std_logic_vector(polynomial'range);
signal iResult : std_logic := '0';
begin
--Lines up the polynomial with the current outbit
polynomial_window <= shift_reg(outbit + polynomial'low + 1 to outbit + polynomial'high + 1);
--This loop will handle situations when the poly_mask is not a 0-based ascending ranged vector
loop_taps: for tap in poly_mask_reg'range generate
final_polynomial(tap-poly_mask'low) <= poly_mask_reg(tap-poly_mask'low) and polynomial_window(tap-poly_mask'low);
end generate;
--Finally we need to find the modulus-2 summation of the final polynomial for this outbit
reducer: reduce_xor
port map(data => final_polynomial,
result => iResult);
result(outbit) <= iResult;
end generate;
--Before feeding the result back to the shift register, pass it to the higher level first.
feedout <= result;
--Output the polynomial portion of the shift register.
history <= polynomial;
end structural;
----------------------------------------------------------------------------------------------------
-- ARCHITECTURE (behavioral)
----------------------------------------------------------------------------------------------------
architecture behave of lfsr is
signal poly_mask_reg : std_logic_vector(poly_mask'range) := (others => '0');
--All of these internal signals need to be defined in the same 0-to-'length range order to make optimal use of the 'range attribute
signal shift_reg : std_logic_vector(0 to (feedin'length + poly_mask'length-1)) := (others => '0');
alias data_in : std_logic_vector(0 to (feedin'length-1)) is shift_reg(0 to (feedin'length-1));
alias polynomial : std_logic_vector(0 to (poly_mask'length-1)) is shift_reg(feedin'length to (feedin'length + poly_mask'length-1));
signal result : std_logic_vector(0 to (feedout'length-1));
begin
--load the left-most bits of shift_reg with the feedin
data_in <= feedin;
--Process to shift the feedback through a shift-register
shifter: process(clk, rst)
begin
if(rising_edge(clk)) then
if(rst = '1') then
--Typical vector assignments preserve the left-to-right bit order. We need to preserve the
--0 to n order for this assignment. The seed may not always be defined 0-to-n, but at
--least we know polynomial is 0-to-n.
for n in seed'low to seed'high loop
polynomial(n-seed'low) <= seed(n);
end loop;
--Set the polynomial mask when only while reset is asserted.
poly_mask_reg <= poly_mask;
else
--shift_reg is a concatenation of data_in and polynomial. By assigning the left-most
--bits of shift_reg to polynomial(the right-most bits), we achieve a right shift.
polynomial <= shift_reg(polynomial'range);
end if;
end if;
end process;
--The shift register updates every clock cycle, when it does, this process calculates the feedback result
--The result is the modulus-2 summation of specified polynomial taps.
--Modulus-2 addition is simply an xor operation.
process(polynomial)
variable tmp : std_logic_vector(0 to (result'length + polynomial'length-1));
begin
tmp := (others => '0');
tmp(result'length to (result'length + polynomial'length-1)) := polynomial;--way to say polynomial'(range + scalar)?
for outbit in result'reverse_range loop --It is critical that the result is calculated from right to left. This ensures the feedback history is preserved
for tap in poly_mask_reg'range loop
if(poly_mask_reg(tap) = '1') then
tmp(outbit) := tmp(outbit) xor tmp(tap-poly_mask_reg'low+outbit+1); --subtracting poly_mask_reg'low is to handle situations where the poly_mask_reg'range is not 0-based (e.g. 1 to 15)
end if;
end loop;
end loop;
--left-most bits of the temporary variable contains the result.
result <= tmp(result'range);
end process;
--Before feeding the result back to the shift register, pass it to the higher level first.
feedout(feedout'range) <= result(result'range);
--Output the polynomial portion of the shift register.
history <= polynomial;
end behave;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity clkgen is
port(
res: in std_logic;
clk_ext: in std_logic;
res_out: out std_logic;
clk_sdram: out std_logic;
clk_sdram_shift: out std_logic
);
end entity clkgen;
architecture clkgen_arch of clkgen is
component pll is
port (
areset : in std_logic := '0';
inclk0 : in std_logic := '0';
c0 : out std_logic ;
c1 : out std_logic ;
locked : out std_logic
);
end component pll;
signal locked: std_logic;
begin
res_out <= res or not(locked);
pll1: pll
port map(res, clk_ext, clk_sdram, clk_sdram_shift, locked);
end architecture clkgen_arch;
|
--======================================================================
-- reset.vhd :: Debounce and Synchonize Reset
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity XRESET is
port (
RST_OUT1 : out std_logic; -- (active low)
RST_OUT2 : out std_logic; -- (active low)
RST_IN : in std_logic; -- (active low)
CLK : in std_logic
);
end XRESET;
architecture BEHAVIORAL of XRESET is
--=================================================================
-- Signal definitions
--=================================================================
signal DLY_CNTR : std_logic_vector(3 downto 0);
signal RST_DLY1 : std_logic;
signal RST_DLY2 : std_logic;
signal RST_INT1 : std_logic;
signal RST_INT2 : std_logic;
begin
--================================================================
-- Debounce and Synchonize the (active-low) Reset Input
--================================================================
-- Depending on the reset and power-supply circuits of the host
-- system, we may need to wait for the power supply to stabilize
-- before starting to fetch opcodes. A simple LFSR counter is
-- provided for this purpose. Here are the states
--
-- 0 0000 4 1010 8 0110 12 1110
-- 1 0001 5 0100 9 1101 13 1100
-- 2 0010 6 1001 10 1011 14 1000
-- 3 0101 7 0011 11 0111
--
--================================================================
DEBOUNCE_AND_SYNCHRONIZE_RESET:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
RST_DLY1 <= RST_IN;
RST_DLY2 <= RST_DLY1;
-- count
if (RST_INT2 = '1') then
-- linear-feedback counter
DLY_CNTR(0) <= DLY_CNTR(3) xnor DLY_CNTR(0);
DLY_CNTR(1) <= DLY_CNTR(0);
DLY_CNTR(2) <= DLY_CNTR(1);
DLY_CNTR(3) <= DLY_CNTR(2);
end if;
-- release early reset
if (DLY_CNTR = "0110") then
RST_INT1 <= '0';
end if;
-- release late reset
if (DLY_CNTR = "1000") then
RST_INT2 <= '0';
DLY_CNTR <= "0000";
end if;
-- initiatialize the reset counter
if (RST_DLY1 = '0' and RST_DLY2 = '0') then
RST_INT1 <= '1';
RST_INT2 <= '1';
DLY_CNTR <= "0000";
end if;
end if;
end process;
RST_OUT1 <= not RST_INT1;
RST_OUT2 <= not RST_INT2;
end architecture BEHAVIORAL;
|
--======================================================================
-- reset.vhd :: Debounce and Synchonize Reset
--
-- (c) Scott L. Baker, Sierra Circuit Design
--======================================================================
library IEEE;
use IEEE.std_logic_1164.all;
entity XRESET is
port (
RST_OUT1 : out std_logic; -- (active low)
RST_OUT2 : out std_logic; -- (active low)
RST_IN : in std_logic; -- (active low)
CLK : in std_logic
);
end XRESET;
architecture BEHAVIORAL of XRESET is
--=================================================================
-- Signal definitions
--=================================================================
signal DLY_CNTR : std_logic_vector(3 downto 0);
signal RST_DLY1 : std_logic;
signal RST_DLY2 : std_logic;
signal RST_INT1 : std_logic;
signal RST_INT2 : std_logic;
begin
--================================================================
-- Debounce and Synchonize the (active-low) Reset Input
--================================================================
-- Depending on the reset and power-supply circuits of the host
-- system, we may need to wait for the power supply to stabilize
-- before starting to fetch opcodes. A simple LFSR counter is
-- provided for this purpose. Here are the states
--
-- 0 0000 4 1010 8 0110 12 1110
-- 1 0001 5 0100 9 1101 13 1100
-- 2 0010 6 1001 10 1011 14 1000
-- 3 0101 7 0011 11 0111
--
--================================================================
DEBOUNCE_AND_SYNCHRONIZE_RESET:
process(CLK)
begin
if (CLK = '0' and CLK'event) then
RST_DLY1 <= RST_IN;
RST_DLY2 <= RST_DLY1;
-- count
if (RST_INT2 = '1') then
-- linear-feedback counter
DLY_CNTR(0) <= DLY_CNTR(3) xnor DLY_CNTR(0);
DLY_CNTR(1) <= DLY_CNTR(0);
DLY_CNTR(2) <= DLY_CNTR(1);
DLY_CNTR(3) <= DLY_CNTR(2);
end if;
-- release early reset
if (DLY_CNTR = "0110") then
RST_INT1 <= '0';
end if;
-- release late reset
if (DLY_CNTR = "1000") then
RST_INT2 <= '0';
DLY_CNTR <= "0000";
end if;
-- initiatialize the reset counter
if (RST_DLY1 = '0' and RST_DLY2 = '0') then
RST_INT1 <= '1';
RST_INT2 <= '1';
DLY_CNTR <= "0000";
end if;
end if;
end process;
RST_OUT1 <= not RST_INT1;
RST_OUT2 <= not RST_INT2;
end architecture BEHAVIORAL;
|
LIBRARY ieee;
USE ieee.numeric_std.ALL;
PACKAGE range_util IS
FUNCTION range_start(base, size : POSITIVE) return POSITIVE;
END PACKAGE;
PACKAGE BODY range_util IS
FUNCTION range_start(base, size : POSITIVE) return POSITIVE IS
BEGIN
RETURN base + size - 1;
END FUNCTION;
END PACKAGE BODY; |
-------------------------------------------------------------------------------------
-- FILE NAME : sip_clkrst_vp780.vhd
--
-- AUTHOR : StellarIP (c) 4DSP
--
-- COMPANY : 4DSP
--
-- ITEM : 1
--
-- UNITS : Entity - sip_clkrst_vp780
-- architecture - arch_sip_clkrst_vp780
--
-- LANGUAGE : VHDL
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
-- DESCRIPTION
-- ===========
--
-- sip_clkrst_vp780
-- Notes: sip_clkrst_vp780
-------------------------------------------------------------------------------------
-- Disclaimer: LIMITED WARRANTY AND DISCLAIMER. These designs are
-- provided to you as is. 4DSP specifically disclaims any
-- implied warranties of merchantability, non-infringement, or
-- fitness for a particular purpose. 4DSP does not warrant that
-- the functions contained in these designs will meet your
-- requirements, or that the operation of these designs will be
-- uninterrupted or error free, or that defects in the Designs
-- will be corrected. Furthermore, 4DSP does not warrant or
-- make any representations regarding use or the results of the
-- use of the designs in terms of correctness, accuracy,
-- reliability, or otherwise.
--
-- LIMITATION OF LIABILITY. In no event will 4DSP or its
-- licensors be liable for any loss of data, lost profits, cost
-- or procurement of substitute goods or services, or for any
-- special, incidental, consequential, or indirect damages
-- arising from the use or operation of the designs or
-- accompanying documentation, however caused and on any theory
-- of liability. This limitation will apply even if 4DSP
-- has been advised of the possibility of such damage. This
-- limitation shall apply not-withstanding the failure of the
-- essential purpose of any limited remedies herein.
--
----------------------------------------------
--
-------------------------------------------------------------------------------------
--
-------------------------------------------------------------------------------------
--library declaration
-------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all ;
use ieee.std_logic_arith.all ;
use ieee.std_logic_unsigned.all ;
use ieee.std_logic_misc.all ;
-------------------------------------------------------------------------------------
--Entity Declaration
-------------------------------------------------------------------------------------
entity sip_clkrst_vp780 is
port (
--Wormhole 'cmdclk_in':
cmdclk_in_cmdclk : in std_logic;
--Wormhole 'cmd_in':
cmd_in_cmdin : in std_logic_vector(63 downto 0);
cmd_in_cmdin_val : in std_logic;
--Wormhole 'cmd_out':
cmd_out_cmdout : out std_logic_vector(63 downto 0);
cmd_out_cmdout_val : out std_logic;
--Wormhole 'clkout':
clkout_clkout : out std_logic_vector(31 downto 0);
--Wormhole 'ext_vp780_clkin' of type 'ext_vp780_clkin':
clk200_n : in std_logic;
clk200_p : in std_logic;
clk300_n : in std_logic;
clk300_p : in std_logic;
aux_clk : in std_logic;
clk_synth_0 : in std_logic;
clk_synth_1 : in std_logic;
--Wormhole 'rst_out':
rst_out_rstout : out std_logic_vector(31 downto 0);
--Wormhole 'ifpga_rst_in':
ifpga_rst_in_ifpga_rst : in std_logic
);
end entity sip_clkrst_vp780;
-------------------------------------------------------------------------------------
--Architecture declaration
-------------------------------------------------------------------------------------
architecture arch_sip_clkrst_vp780 of sip_clkrst_vp780 is
-------------------------------------------------------------------------------------
--Constants declaration
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--Signal declaration
-------------------------------------------------------------------------------------
signal clk200M_o :std_logic;
signal clk300M_o :std_logic;
-------------------------------------------------------------------------------------
--components declarations
-------------------------------------------------------------------------------------
component clkrst_vp780 is
generic ( reset_base :integer:=1024);
port
(
clk200_n : in std_logic;
clk200_p : in std_logic;
clk300_n : in std_logic;
clk300_p : in std_logic;
aux_clk : in std_logic;
clk_synth_0 : in std_logic;
clk_synth_1 : in std_logic;
reset_i :in std_logic; --reset complete FPGA
--command if
out_cmd :out std_logic_vector(63 downto 0);
out_cmd_val :out std_logic;
in_cmd :in std_logic_vector(63 downto 0);
in_cmd_val :in std_logic;
cmdclk_in :in std_logic;
--clk outputs
clk200M_o :out std_logic;
clk300M_o :out std_logic;
dly_ready_o :out std_logic;
clk_synth_0o :out std_logic;
clk_synth_90o :out std_logic;
clk_synth_180o :out std_logic;
clk_synth_270o :out std_logic;
clk_synth_D4o :out std_logic;
clk_ddr_0_div2o :out std_logic;
clk_ddr_0o :out std_logic;
clk_ddr_90o :out std_logic;
clk_ddr_180o :out std_logic;
clk_ddr_270o :out std_logic;
clk_ddr_capt_div2 :out std_logic; --the MIG design requires the div2 clock for the resynchronisation path to be gated to allow releasing the iserdes reset while the slow and fast clocks are off
clk_ddr_capt :out std_logic; --the MIG design requires the div2 clock for the resynchronisation path to be gated to allow releasing the iserdes reset while the slow and fast clocks are off
clk_ddr_reset_capt :out std_logic; --the MIG design requires the div2 clock for the resynchronisation path to be gated to allow releasing the iserdes reset while the slow and fast clocks are off
clk_synth_1o :out std_logic;
--reset outputs
reset1_o :out std_logic;
reset2_o :out std_logic;
reset3_o :out std_logic
);
end component;
begin
-------------------------------------------------------------------------------------
--components instantiations
-------------------------------------------------------------------------------------
i_clkrst_vp780:clkrst_vp780
generic map (
reset_base => 2
)
port map
(
clk200_n =>clk200_n,
clk200_p =>clk200_p,
clk300_n =>clk300_n,
clk300_p =>clk300_p,
aux_clk =>aux_clk,
clk_synth_0 =>clk_synth_0,
clk_synth_1 =>clk_synth_1,
reset_i =>ifpga_rst_in_ifpga_rst,
--command if
out_cmd =>cmd_out_cmdout,
out_cmd_val =>cmd_out_cmdout_val,
in_cmd =>cmd_in_cmdin,
in_cmd_val =>cmd_in_cmdin_val,
cmdclk_in =>cmdclk_in_cmdclk,
--clk outputs
clk200M_o =>clk200M_o,
clk300M_o =>clk300M_o,
dly_ready_o =>open,
clk_synth_0o =>clkout_clkout(0),
clk_synth_90o =>clkout_clkout(1),
clk_synth_180o =>clkout_clkout(2),
clk_synth_270o =>clkout_clkout(3),
clk_synth_D4o =>clkout_clkout(4),
clk_ddr_0_div2o =>clkout_clkout(9),
clk_ddr_0o =>clkout_clkout(5),
clk_ddr_90o =>clkout_clkout(6),
clk_ddr_180o =>clkout_clkout(7),
clk_ddr_270o =>clkout_clkout(8),
clk_ddr_capt_div2 =>clkout_clkout(16),
clk_ddr_capt =>clkout_clkout(17),
clk_ddr_reset_capt =>rst_out_rstout(16),
clk_synth_1o =>clkout_clkout(12),
--reset outputs
reset1_o =>rst_out_rstout(0),
reset2_o =>rst_out_rstout(1),
reset3_o =>rst_out_rstout(2)
);
clkout_clkout(10) <=clk200M_o;
clkout_clkout(11) <=clk200M_o; --clock is used for the command clock
clkout_clkout(18) <=clk300M_o;
-------------------------------------------------------------------------------------
--synchronous processes
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--asynchronous processes
-------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------
--asynchronous mapping
-------------------------------------------------------------------------------------
rst_out_rstout(31 downto 3) <= (others=>'0');
end architecture arch_sip_clkrst_vp780 ; -- of sip_clkrst_vp780
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity kr_fuzman_Vtminus is
port
( clock : in std_logic;
Vtminusone : in std_logic_vector (31 downto 0);
Vref : in std_logic_vector (31 downto 0);
koft : in std_logic_vector (31 downto 0);
Vtminus : out std_logic_vector (31 downto 0)
);
end kr_fuzman_Vtminus;
architecture struct of kr_fuzman_Vtminus is
component kn_kalman_add IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_mult IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
component kn_kalman_sub IS
PORT
( clock : IN STD_LOGIC ;
dataa : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
datab : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (31 DOWNTO 0)
);
end component;
signal Z1,Z2 : std_logic_vector (31 downto 0);
begin
M1 : kn_kalman_sub port map (clock => clock, dataa => Vref, datab => Vtminusone, result => Z1);
M2 : kn_kalman_mult port map (clock => clock, dataa => koft, datab => Z1, result => Z2);
M3 : kn_kalman_add port map (clock => clock, dataa => Z2, datab => Vtminusone, result => Vtminus);
end struct; |
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_8_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 08:31:57 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../../generic.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_8_e-rtl-a.vhd,v 1.5 2006/06/26 08:39:42 wig Exp $
-- $Date: 2006/06/26 08:39:42 $
-- $Log: inst_8_e-rtl-a.vhd,v $
-- Revision 1.5 2006/06/26 08:39:42 wig
-- Update more testcases (up to generic)
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_8_e
--
architecture rtl of inst_8_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter_tb is
end entity;
architecture behavv of counter_tb is
component counter is
port(
clk, res_as, up : in std_logic;
count : out std_logic_vector (3 downto 0)
);
end component;
for counter_0 : counter use entity work.counter;
signal clk,up : std_logic :='1';
signal res_as : std_logic:='0';
signal count : std_logic_vector(3 downto 0);
constant period : time := 10 ns;
begin
counter_0 : counter port map (clk=>clk, res_as=>res_as, up=>up, count=>count);
clk_process: process
begin
clk<=not clk;
wait for period/2;
end process;
stim_proc : process
begin
res_as<='0';
up<='1';
wait for 80 ns;
up<='0';
wait for 30 ns;
res_as<='1';
wait for 10 ns;
wait;
end process;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_184 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_184;
architecture augh of add_184 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_184 is
port (
result : out std_logic_vector(31 downto 0);
in_a : in std_logic_vector(31 downto 0);
in_b : in std_logic_vector(31 downto 0)
);
end add_184;
architecture augh of add_184 is
signal carry_inA : std_logic_vector(33 downto 0);
signal carry_inB : std_logic_vector(33 downto 0);
signal carry_res : std_logic_vector(33 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(32 downto 1);
end architecture;
|
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;
ENTITY VGA IS
-----SYNC PARAMETERS FOR 640x480 VGA DISPLAY (25MHz clock)-----
GENERIC(
Ha: INTEGER:=96; -- Hpulse
Hb: INTEGER:=143; -- Hpulse+Hbp
Hc: INTEGER:=783; -- Hpulse+Hbp+Hactive
Hd: INTEGER:=800; -- Hpulse+Hbp+Hactive+Hfp
Va: INTEGER:=2; -- Vpulse
Vb: INTEGER:=35; -- Vpulse+Vbp
Vc: INTEGER:=515; -- Vpulse+Vbp+Vactive
Vd: INTEGER:=525); -- Vpulse+Vbp+Vactive+Vfp
PORT(
CLK_VGA : IN STD_LOGIC;
Hsync,Vsync : BUFFER STD_LOGIC;
BLANK,SYNC : BUFFER STD_LOGIC;
Xcnt, Ycnt : OUT INTEGER
);
END VGA;
ARCHITECTURE MAIN OF VGA IS
SIGNAL Hactive, Vactive: STD_LOGIC;
BEGIN
---------------------------------
-- CONTROL GENERATOR --
---------------------------------
-- Static signals for DACs:
BLANK <= Hactive AND Vactive;
SYNC <= '0';
-- Horizontal signal generation
PROCESS(CLK_VGA)
VARIABLE Hcnt: INTEGER RANGE 0 TO Hd;
BEGIN
IF RISING_EDGE(CLK_VGA) THEN
Hcnt:=Hcnt+1;
IF (Hcnt=Ha)THEN
Hsync<='1';
ELSIF(Hcnt=Hb) THEN
Hactive<='1';
ELSIF(Hcnt=Hc) THEN
Hactive<='0';
ELSIF(Hcnt=Hd) THEN
Hsync<='0';
Hcnt:=0;
END IF;
IF (Hcnt>=Hb AND Hcnt<Hc) THEN
Xcnt<=Hcnt-Hb; -- Xcnt 0 --> 639
ELSE
Xcnt<=0;
END IF;
END IF;
END PROCESS;
-- Vertical signal generation
PROCESS(Hsync)
VARIABLE Vcnt: INTEGER RANGE 0 TO Vd;
BEGIN
IF FALLING_EDGE(Hsync) THEN
Vcnt:=Vcnt+1;
IF (Vcnt=Va)THEN
Vsync<='1';
ELSIF(Vcnt=Vb) THEN
Vactive<='1';
ELSIF(Vcnt=Vc) THEN
Vactive<='0';
ELSIF(Vcnt=Vd) THEN
Vsync<='0';
Vcnt:=0;
END IF;
IF (Vcnt>=Vb AND Vcnt<Vc) THEN
Ycnt<=Vcnt-Vb; -- Ycnt 0 --> 479
ELSE
Ycnt<=0;
END IF;
END IF;
END PROCESS;
END MAIN; |
-------------------------------------------------------------------------------
-- Title : TIE-50206, Exercise 06
-- Project :
-------------------------------------------------------------------------------
-- File : wave_gen.vhd
-- Author : Tuomas Huuki
-- Company : TUT
-- Created : 23.11.2015
-- Platform :
-- Standard : VHDL'87
-------------------------------------------------------------------------------
-- Description: Sixth excercise.
-------------------------------------------------------------------------------
-- Copyright (c) 2015
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 23.11.2015 1.0 tuhu Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity wave_gen is -- Wave generator entity.
generic (
width_g : integer; -- Width of the generated wave in bits.
step_g : integer -- Width of one step.
);
port(
clk : in std_logic; -- Clock signal.
rst_n : in std_logic; -- Reset, actove low.
sync_clear_in : in std_logic; -- Sync bit input to clear the counter.
value_out : out std_logic_vector(width_g - 1 downto 0) -- Counter value out.
);
end wave_gen;
architecture rtl of wave_gen is
type dir_type is (up, down); -- Definition for counter direction type.
constant maxval_c : integer := (2**(width_g - 1) - 1)/step_g * step_g; -- Maximum value for counter.
constant minval_c : integer := -maxval_c; -- Minimun value for counter.
signal dir_r : dir_type; -- Counter direction.
signal count_r : signed(width_g - 1 downto 0); -- Counter count register.
begin -- rtl
value_out <= std_logic_vector(count_r); -- Assign register to output.
count : process (clk, rst_n) -- Process to increment or decrement counter value.
begin
if(rst_n = '0') then
count_r <= (others => '0'); -- Clear the output on reset ...
elsif(clk'event and clk = '1') then
if(sync_clear_in = '1') then
count_r <= (others => '0'); -- ... or if the sync bit is active.
else
case (dir_r) is -- Check the direction and step the counter up or down.
when up =>
count_r <= count_r + step_g; -- Step counter up.
when down =>
count_r <= count_r - step_g; -- Step counter down.
end case; -- dir_r
end if; -- sync_clear_in
end if; -- clk'event ...
end process count;
compare : process (clk, rst_n) -- Process to do compare and change direction.
begin
if(rst_n = '0') then
dir_r <= up; -- Set the default direction of the counter on reset ...
elsif(clk'event and clk = '1') then
if(sync_clear_in = '1') then
dir_r <= up; -- ... and also set the counter direction on sync bit active.
else
if((count_r + step_g) = maxval_c) then -- If we are on the limit on the next round ...
dir_r <= down; -- ... change the direction of the counter.
elsif((count_r - step_g) = minval_c) then -- Note, as assignments take place after the block
dir_r <= up; -- has been executed, we need to change the direction
end if; -- count_r -- before hitting the actual limit.
end if; -- sync_clear_in
end if; -- clk'event ...
end process compare;
end rtl; |
library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHB2APB is
generic(
TPD : real := 0.100000;
T0 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
T2 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1);
T345 : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi0);
TR0 : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi1);
WAIT1 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
WAIT2 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
WAIT3 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1);
WAIT4 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0);
idle : vl_logic_vector(1 downto 0) := (Hi0, Hi0);
waitone : vl_logic_vector(1 downto 0) := (Hi0, Hi1);
waittwo : vl_logic_vector(1 downto 0) := (Hi1, Hi0);
waitthree : vl_logic_vector(1 downto 0) := (Hi1, Hi1)
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
PSEL : out vl_logic_vector(15 downto 0);
PADDR : out vl_logic_vector(31 downto 0);
PWRITE : out vl_logic;
PENABLE : out vl_logic;
PWDATA : out vl_logic_vector(31 downto 0);
PRDATA : in vl_logic_vector(31 downto 0);
PREADY : in vl_logic;
PSLVERR : in vl_logic;
PCLK_DIV : in vl_logic_vector(1 downto 0)
);
attribute T0_mti_vect_attrib : integer;
attribute T0_mti_vect_attrib of T0 : constant is 0;
attribute T2_mti_vect_attrib : integer;
attribute T2_mti_vect_attrib of T2 : constant is 5;
attribute T345_mti_vect_attrib : integer;
attribute T345_mti_vect_attrib of T345 : constant is 6;
attribute TR0_mti_vect_attrib : integer;
attribute TR0_mti_vect_attrib of TR0 : constant is 7;
attribute WAIT1_mti_vect_attrib : integer;
attribute WAIT1_mti_vect_attrib of WAIT1 : constant is 1;
attribute WAIT2_mti_vect_attrib : integer;
attribute WAIT2_mti_vect_attrib of WAIT2 : constant is 2;
attribute WAIT3_mti_vect_attrib : integer;
attribute WAIT3_mti_vect_attrib of WAIT3 : constant is 3;
attribute WAIT4_mti_vect_attrib : integer;
attribute WAIT4_mti_vect_attrib of WAIT4 : constant is 4;
attribute idle_mti_vect_attrib : integer;
attribute idle_mti_vect_attrib of idle : constant is 0;
attribute waitone_mti_vect_attrib : integer;
attribute waitone_mti_vect_attrib of waitone : constant is 1;
attribute waittwo_mti_vect_attrib : integer;
attribute waittwo_mti_vect_attrib of waittwo : constant is 2;
attribute waitthree_mti_vect_attrib : integer;
attribute waitthree_mti_vect_attrib of waitthree : constant is 3;
end MSS_BFM_AHB2APB;
|
library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHB2APB is
generic(
TPD : real := 0.100000;
T0 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
T2 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1);
T345 : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi0);
TR0 : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi1);
WAIT1 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
WAIT2 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
WAIT3 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1);
WAIT4 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0);
idle : vl_logic_vector(1 downto 0) := (Hi0, Hi0);
waitone : vl_logic_vector(1 downto 0) := (Hi0, Hi1);
waittwo : vl_logic_vector(1 downto 0) := (Hi1, Hi0);
waitthree : vl_logic_vector(1 downto 0) := (Hi1, Hi1)
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
PSEL : out vl_logic_vector(15 downto 0);
PADDR : out vl_logic_vector(31 downto 0);
PWRITE : out vl_logic;
PENABLE : out vl_logic;
PWDATA : out vl_logic_vector(31 downto 0);
PRDATA : in vl_logic_vector(31 downto 0);
PREADY : in vl_logic;
PSLVERR : in vl_logic;
PCLK_DIV : in vl_logic_vector(1 downto 0)
);
attribute T0_mti_vect_attrib : integer;
attribute T0_mti_vect_attrib of T0 : constant is 0;
attribute T2_mti_vect_attrib : integer;
attribute T2_mti_vect_attrib of T2 : constant is 5;
attribute T345_mti_vect_attrib : integer;
attribute T345_mti_vect_attrib of T345 : constant is 6;
attribute TR0_mti_vect_attrib : integer;
attribute TR0_mti_vect_attrib of TR0 : constant is 7;
attribute WAIT1_mti_vect_attrib : integer;
attribute WAIT1_mti_vect_attrib of WAIT1 : constant is 1;
attribute WAIT2_mti_vect_attrib : integer;
attribute WAIT2_mti_vect_attrib of WAIT2 : constant is 2;
attribute WAIT3_mti_vect_attrib : integer;
attribute WAIT3_mti_vect_attrib of WAIT3 : constant is 3;
attribute WAIT4_mti_vect_attrib : integer;
attribute WAIT4_mti_vect_attrib of WAIT4 : constant is 4;
attribute idle_mti_vect_attrib : integer;
attribute idle_mti_vect_attrib of idle : constant is 0;
attribute waitone_mti_vect_attrib : integer;
attribute waitone_mti_vect_attrib of waitone : constant is 1;
attribute waittwo_mti_vect_attrib : integer;
attribute waittwo_mti_vect_attrib of waittwo : constant is 2;
attribute waitthree_mti_vect_attrib : integer;
attribute waitthree_mti_vect_attrib of waitthree : constant is 3;
end MSS_BFM_AHB2APB;
|
library verilog;
use verilog.vl_types.all;
entity MSS_BFM_AHB2APB is
generic(
TPD : real := 0.100000;
T0 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi0);
T2 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi1);
T345 : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi0);
TR0 : vl_logic_vector(2 downto 0) := (Hi1, Hi1, Hi1);
WAIT1 : vl_logic_vector(2 downto 0) := (Hi0, Hi0, Hi1);
WAIT2 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi0);
WAIT3 : vl_logic_vector(2 downto 0) := (Hi0, Hi1, Hi1);
WAIT4 : vl_logic_vector(2 downto 0) := (Hi1, Hi0, Hi0);
idle : vl_logic_vector(1 downto 0) := (Hi0, Hi0);
waitone : vl_logic_vector(1 downto 0) := (Hi0, Hi1);
waittwo : vl_logic_vector(1 downto 0) := (Hi1, Hi0);
waitthree : vl_logic_vector(1 downto 0) := (Hi1, Hi1)
);
port(
HCLK : in vl_logic;
HRESETN : in vl_logic;
HSEL : in vl_logic;
HWRITE : in vl_logic;
HADDR : in vl_logic_vector(31 downto 0);
HWDATA : in vl_logic_vector(31 downto 0);
HRDATA : out vl_logic_vector(31 downto 0);
HREADYIN : in vl_logic;
HREADYOUT : out vl_logic;
HTRANS : in vl_logic_vector(1 downto 0);
HSIZE : in vl_logic_vector(2 downto 0);
HBURST : in vl_logic_vector(2 downto 0);
HMASTLOCK : in vl_logic;
HPROT : in vl_logic_vector(3 downto 0);
HRESP : out vl_logic;
PSEL : out vl_logic_vector(15 downto 0);
PADDR : out vl_logic_vector(31 downto 0);
PWRITE : out vl_logic;
PENABLE : out vl_logic;
PWDATA : out vl_logic_vector(31 downto 0);
PRDATA : in vl_logic_vector(31 downto 0);
PREADY : in vl_logic;
PSLVERR : in vl_logic;
PCLK_DIV : in vl_logic_vector(1 downto 0)
);
attribute T0_mti_vect_attrib : integer;
attribute T0_mti_vect_attrib of T0 : constant is 0;
attribute T2_mti_vect_attrib : integer;
attribute T2_mti_vect_attrib of T2 : constant is 5;
attribute T345_mti_vect_attrib : integer;
attribute T345_mti_vect_attrib of T345 : constant is 6;
attribute TR0_mti_vect_attrib : integer;
attribute TR0_mti_vect_attrib of TR0 : constant is 7;
attribute WAIT1_mti_vect_attrib : integer;
attribute WAIT1_mti_vect_attrib of WAIT1 : constant is 1;
attribute WAIT2_mti_vect_attrib : integer;
attribute WAIT2_mti_vect_attrib of WAIT2 : constant is 2;
attribute WAIT3_mti_vect_attrib : integer;
attribute WAIT3_mti_vect_attrib of WAIT3 : constant is 3;
attribute WAIT4_mti_vect_attrib : integer;
attribute WAIT4_mti_vect_attrib of WAIT4 : constant is 4;
attribute idle_mti_vect_attrib : integer;
attribute idle_mti_vect_attrib of idle : constant is 0;
attribute waitone_mti_vect_attrib : integer;
attribute waitone_mti_vect_attrib of waitone : constant is 1;
attribute waittwo_mti_vect_attrib : integer;
attribute waittwo_mti_vect_attrib of waittwo : constant is 2;
attribute waitthree_mti_vect_attrib : integer;
attribute waitthree_mti_vect_attrib of waitthree : constant is 3;
end MSS_BFM_AHB2APB;
|
-- NEED RESULT: ARCH00268: 'All' in an attribute spec applies to all entities of the specified class declared in the same declarative region as the attribute spec passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00268
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.1 (6)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00268_Test_Bench(ARCH00268_Test_Bench)
--
-- REVISION HISTORY:
--
-- 7-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
--
use WORK.STANDARD_TYPES.all ;
entity ENT00268_Test_Bench is
attribute Attr : boolean ;
end ENT00268_Test_Bench ;
architecture ARCH00268_Test_Bench of ENT00268_Test_Bench is
signal S : Integer := -1 ;
begin
L1 :
block ( S /= -1 )
port ( P : in Integer ) ;
port map ( S ) ;
signal Local_S : Real := -0.1 ;
attribute Attr of all : signal is true ;
begin
process
begin
test_report ( "ARCH00268" ,
"'All' in an attribute spec applies to " &
"all entities of the specified class declared in " &
"the same declarative region as the attribute spec" ,
Local_S'Attr and
GUARD'Attr and
P'Attr ) ;
wait ;
end process ;
end block L1 ;
end ARCH00268_Test_Bench ;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:56:26 05/26/2014
-- Design Name:
-- Module Name: wishbone_ping - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.control_pack.all ;
entity wishbone_ping is
generic( nb_ping : positive := 2;
clock_period_ns : integer := 10
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( 15 downto 0);
wbs_readdata : out std_logic_vector( 15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
ping_io : inout std_logic_vector(nb_ping-1 downto 0 )
);
end wishbone_ping;
architecture Behavioral of wishbone_ping is
type reg16_array is array (0 to (nb_ping-1)) of std_logic_vector(15 downto 0) ;
signal ping_regs : reg16_array ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal enable_reg : std_logic_vector(15 downto 0);
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
enable_reg <= wbs_writedata ;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= ping_regs(conv_integer(wbs_address)) ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
gen_trigs_echo : for i in 0 to nb_ping-1 generate
pinger : ping_sensor
generic map(CLK_FREQ_NS => clock_period_ns)
port map(
clk => gls_clk,
reset => gls_reset,
ping_io => ping_io(i),
ping_enable => enable_reg(i),
state_debug => open,
echo_length => ping_regs(i),
echo_done_out => open,
timeout => open,
busy => open
);
end generate ;
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 14:56:26 05/26/2014
-- Design Name:
-- Module Name: wishbone_ping - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use IEEE.std_logic_unsigned.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
library work ;
use work.control_pack.all ;
entity wishbone_ping is
generic( nb_ping : positive := 2;
clock_period_ns : integer := 10
);
port(
-- Syscon signals
gls_reset : in std_logic ;
gls_clk : in std_logic ;
-- Wishbone signals
wbs_address : in std_logic_vector(15 downto 0) ;
wbs_writedata : in std_logic_vector( 15 downto 0);
wbs_readdata : out std_logic_vector( 15 downto 0);
wbs_strobe : in std_logic ;
wbs_cycle : in std_logic ;
wbs_write : in std_logic ;
wbs_ack : out std_logic;
ping_io : inout std_logic_vector(nb_ping-1 downto 0 )
);
end wishbone_ping;
architecture Behavioral of wishbone_ping is
type reg16_array is array (0 to (nb_ping-1)) of std_logic_vector(15 downto 0) ;
signal ping_regs : reg16_array ;
signal read_ack : std_logic ;
signal write_ack : std_logic ;
signal enable_reg : std_logic_vector(15 downto 0);
begin
wbs_ack <= read_ack or write_ack;
write_bloc : process(gls_clk,gls_reset)
begin
if gls_reset = '1' then
write_ack <= '0';
elsif rising_edge(gls_clk) then
if ((wbs_strobe and wbs_write and wbs_cycle) = '1' ) then
enable_reg <= wbs_writedata ;
write_ack <= '1';
else
write_ack <= '0';
end if;
end if;
end process write_bloc;
read_bloc : process(gls_clk, gls_reset)
begin
if gls_reset = '1' then
elsif rising_edge(gls_clk) then
wbs_readdata <= ping_regs(conv_integer(wbs_address)) ;
if (wbs_strobe = '1' and wbs_write = '0' and wbs_cycle = '1' ) then
read_ack <= '1';
else
read_ack <= '0';
end if;
end if;
end process read_bloc;
gen_trigs_echo : for i in 0 to nb_ping-1 generate
pinger : ping_sensor
generic map(CLK_FREQ_NS => clock_period_ns)
port map(
clk => gls_clk,
reset => gls_reset,
ping_io => ping_io(i),
ping_enable => enable_reg(i),
state_debug => open,
echo_length => ping_regs(i),
echo_done_out => open,
timeout => open,
busy => open
);
end generate ;
end Behavioral;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "spi_slave"
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.spislave_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity spi_slave_tb is
end spi_slave_tb;
-------------------------------------------------------------------------------
architecture tb of spi_slave_tb is
-- component ports
signal mosi : std_logic;
signal miso : std_logic;
signal sck : std_logic;
signal csn : std_logic;
signal clk : std_logic := '1';
signal bus_o : busmaster_out_type;
signal bus_i : busmaster_in_type;
signal bus_data : unsigned(15 downto 0) := (others => '0');
signal debug_addr : std_logic_vector(14 downto 0);
signal debug_data : std_logic_vector(15 downto 0);
begin -- tb
DUT : spi_slave port map (
--ireg => open,
--bit_cnt => open,
miso_p => miso,
mosi_p => mosi,
sck_p => sck,
csn_p => csn,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
Clk <= not Clk after 5.0 ns;
-- Change the bus data to find out when exactly the bus is sampled
process (clk) is
begin -- process
if rising_edge(clk) then -- rising clock edge
bus_i.data <= std_logic_vector(bus_data);
bus_data <= bus_data + 1;
end if;
end process;
process
variable d : std_logic_vector(31 downto 0);
begin
debug_addr <= std_logic_vector(to_unsigned(16#0ff#, 15));
debug_data <= x"fe35";
-- read access to addr 0x7000 with 0x0000 as dummy data.
spiReadWord(addr => 16#7000#, sck => sck, mosi => mosi, cs_n => csn, clk => clk);
-- write access to addr 0x00ff with data 0xfe35
spiWriteWord(addr => debug_addr, data => debug_data, sck => sck, mosi => mosi, cs_n => csn, clk => clk);
--
wait for 1 us;
d := X"8209" & X"cd43";
-- start
csn <= '1';
sck <= '0';
mosi <= '0';
wait for 250 ns;
csn <= '0';
for i in 31 downto 0 loop
sck <= '0';
mosi <= d(i);
wait for 250 ns;
sck <= '1';
wait for 250 ns;
end loop; -- i
-- no pause between two transfers:
if false then
sck <= '0';
wait for 250 ns;
csn <= '1';
mosi <= 'Z';
wait for 250 ns;
csn <= '0';
wait for 250 ns;
end if;
-- write access to addr 0xf0f with data 0x1234
d := X"8f0f" & X"1234";
for i in 31 downto 0 loop
sck <= '0';
mosi <= d(i);
wait for 250 ns;
sck <= '1';
wait for 250 ns;
end loop; -- i
sck <= '0';
wait for 250 ns;
csn <= '1';
mosi <= 'Z';
end process;
end tb;
|
-------------------------------------------------------------------------------
-- Title : Testbench for design "spi_slave"
-------------------------------------------------------------------------------
-- Author : [email protected]
-------------------------------------------------------------------------------
-- Description:
-------------------------------------------------------------------------------
-- Copyright (c) 2011
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.spislave_pkg.all;
use work.bus_pkg.all;
-------------------------------------------------------------------------------
entity spi_slave_tb is
end spi_slave_tb;
-------------------------------------------------------------------------------
architecture tb of spi_slave_tb is
-- component ports
signal mosi : std_logic;
signal miso : std_logic;
signal sck : std_logic;
signal csn : std_logic;
signal clk : std_logic := '1';
signal bus_o : busmaster_out_type;
signal bus_i : busmaster_in_type;
signal bus_data : unsigned(15 downto 0) := (others => '0');
signal debug_addr : std_logic_vector(14 downto 0);
signal debug_data : std_logic_vector(15 downto 0);
begin -- tb
DUT : spi_slave port map (
--ireg => open,
--bit_cnt => open,
miso_p => miso,
mosi_p => mosi,
sck_p => sck,
csn_p => csn,
bus_o => bus_o,
bus_i => bus_i,
clk => clk);
-- clock generation
Clk <= not Clk after 5.0 ns;
-- Change the bus data to find out when exactly the bus is sampled
process (clk) is
begin -- process
if rising_edge(clk) then -- rising clock edge
bus_i.data <= std_logic_vector(bus_data);
bus_data <= bus_data + 1;
end if;
end process;
process
variable d : std_logic_vector(31 downto 0);
begin
debug_addr <= std_logic_vector(to_unsigned(16#0ff#, 15));
debug_data <= x"fe35";
-- read access to addr 0x7000 with 0x0000 as dummy data.
spiReadWord(addr => 16#7000#, sck => sck, mosi => mosi, cs_n => csn, clk => clk);
-- write access to addr 0x00ff with data 0xfe35
spiWriteWord(addr => debug_addr, data => debug_data, sck => sck, mosi => mosi, cs_n => csn, clk => clk);
--
wait for 1 us;
d := X"8209" & X"cd43";
-- start
csn <= '1';
sck <= '0';
mosi <= '0';
wait for 250 ns;
csn <= '0';
for i in 31 downto 0 loop
sck <= '0';
mosi <= d(i);
wait for 250 ns;
sck <= '1';
wait for 250 ns;
end loop; -- i
-- no pause between two transfers:
if false then
sck <= '0';
wait for 250 ns;
csn <= '1';
mosi <= 'Z';
wait for 250 ns;
csn <= '0';
wait for 250 ns;
end if;
-- write access to addr 0xf0f with data 0x1234
d := X"8f0f" & X"1234";
for i in 31 downto 0 loop
sck <= '0';
mosi <= d(i);
wait for 250 ns;
sck <= '1';
wait for 250 ns;
end loop; -- i
sck <= '0';
wait for 250 ns;
csn <= '1';
mosi <= 'Z';
end process;
end tb;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
library work;
use work.rv_components.all;
use work.utils.all;
--Sets waitrequest on the slave if too many outstanding requests are in flight.
--This is needed for certain interconnect tools that want a bounded number of
--requests in progress.
entity oimm_throttler is
generic (
MAX_OUTSTANDING_REQUESTS : natural;
READ_WRITE_FENCE : boolean
);
port (
clk : in std_logic;
reset : in std_logic;
throttler_idle : out std_logic;
--ORCA-internal memory-mapped slave
slave_oimm_requestvalid : in std_logic;
slave_oimm_readnotwrite : in std_logic;
slave_oimm_writelast : in std_logic;
slave_oimm_waitrequest : out std_logic;
--ORCA-internal memory-mapped master
master_oimm_requestvalid : out std_logic;
master_oimm_readcomplete : in std_logic;
master_oimm_writecomplete : in std_logic;
master_oimm_waitrequest : in std_logic
);
end entity oimm_throttler;
architecture rtl of oimm_throttler is
signal slave_oimm_waitrequest_signal : std_logic;
signal outstanding_are_reads : std_logic;
signal request_accepted : std_logic;
signal throttle : std_logic;
begin
slave_oimm_waitrequest <= slave_oimm_waitrequest_signal;
master_oimm_requestvalid <= slave_oimm_requestvalid and (not throttle);
slave_oimm_waitrequest_signal <= master_oimm_waitrequest or throttle;
process (clk) is
begin
if rising_edge(clk) then
if slave_oimm_requestvalid = '1' and slave_oimm_waitrequest_signal = '0' then
outstanding_are_reads <= slave_oimm_readnotwrite;
end if;
end if;
end process;
request_accepted <=
slave_oimm_requestvalid and (slave_oimm_readnotwrite or slave_oimm_writelast) and (not slave_oimm_waitrequest_signal);
dont_throttle_gen : if MAX_OUTSTANDING_REQUESTS = 0 generate
throttle <= '0';
throttler_idle <= '1';
end generate dont_throttle_gen;
throttle_gen : if MAX_OUTSTANDING_REQUESTS > 0 generate
one_outstanding_request_gen : if MAX_OUTSTANDING_REQUESTS = 1 generate
signal outstanding_request : std_logic;
begin
process (clk) is
begin
if rising_edge(clk) then
if master_oimm_readcomplete = '1' or master_oimm_writecomplete = '1' then
outstanding_request <= '0';
throttler_idle <= '1';
end if;
if request_accepted = '1' then
outstanding_request <= '1';
throttler_idle <= '0';
end if;
if reset = '1' then
outstanding_request <= '0';
throttler_idle <= '1';
end if;
end if;
end process;
--No need to worry about READ_WRITE_FENCE; since only one access can be in
--flight a read must return before a write is accepted and vice-versa
throttle <= outstanding_request and (not (master_oimm_readcomplete or master_oimm_writecomplete));
end generate one_outstanding_request_gen;
multiple_outstanding_requests_gen : if MAX_OUTSTANDING_REQUESTS > 1 generate
signal outstanding_requests : unsigned(log2(MAX_OUTSTANDING_REQUESTS+1)-1 downto 0);
signal change_in_requests : signed(log2(MAX_OUTSTANDING_REQUESTS+1)-1 downto 0);
signal next_outstanding_requests : unsigned(log2(MAX_OUTSTANDING_REQUESTS+1)-1 downto 0);
signal outstanding_requests_eq_zero : std_logic;
signal outstanding_requests_eq_max : std_logic;
signal change_select_vector : std_logic_vector(2 downto 0);
begin
change_select_vector <= request_accepted & master_oimm_readcomplete & master_oimm_writecomplete;
with change_select_vector select
change_in_requests <=
to_signed(-2, change_in_requests'length) when "011",
to_signed(-1, change_in_requests'length) when "111"|"010"|"001",
to_signed(1, change_in_requests'length) when "100",
to_signed(0, change_in_requests'length) when others;
next_outstanding_requests <= outstanding_requests + unsigned(change_in_requests);
--Note that 'throttle' is based on outstanding requests only (not using
--readcomplete or writecomplete combinationally) to avoid a combinational
--path from the master back to the slave. This means, however, that for
--a fully pipelined slave with fixed latency you will need
--MAX_OUTSTANDING_REQUESTS to be request latency + 1 to get full
--throughput.
process (clk) is
begin
if rising_edge(clk) then
outstanding_requests <= next_outstanding_requests;
if next_outstanding_requests = to_unsigned(MAX_OUTSTANDING_REQUESTS, next_outstanding_requests'length) then
outstanding_requests_eq_max <= '1';
else
outstanding_requests_eq_max <= '0';
end if;
if next_outstanding_requests = to_unsigned(0, next_outstanding_requests'length) then
outstanding_requests_eq_zero <= '1';
else
outstanding_requests_eq_zero <= '0';
end if;
if reset = '1' then
outstanding_requests <= to_unsigned(0, outstanding_requests'length);
outstanding_requests_eq_max <= '0';
outstanding_requests_eq_zero <= '1';
end if;
end if;
end process;
throttler_idle <= outstanding_requests_eq_zero;
no_rw_fence_gen : if not READ_WRITE_FENCE generate
throttle <= outstanding_requests_eq_max;
end generate no_rw_fence_gen;
rw_fence_gen : if READ_WRITE_FENCE generate
throttle <= outstanding_requests_eq_max or ((not outstanding_requests_eq_zero) and (outstanding_are_reads xor slave_oimm_readnotwrite));
end generate rw_fence_gen;
end generate multiple_outstanding_requests_gen;
end generate throttle_gen;
end architecture rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity test2 is
port (val : out std_logic_vector (63 downto 0));
end entity test2;
architecture beh of test2 is
type t_register is array(0 to 7) of std_logic_vector(7 downto 0);
signal s_register : t_register;
begin
-- the problem is the next line
s_register <= (0 => x"f0", 1 => x"e1", 2 => x"d2", 3 => x"c3",
4 => x"b4", 5 => x"a5", 6 => x"96", 7 => x"87");
val <= s_register(7) & s_register(6) & s_register(5) & s_register(4)
& s_register(3) & s_register(2) & s_register(1) & s_register(0);
end architecture beh;
|
library ieee;
use ieee.std_logic_1164.all;
entity reg_5bits is
port (EN, CLK, RST: in std_logic;
D: in std_logic_vector(4 downto 0);
Q: out std_logic_vector(4 downto 0)
);
end reg_5bits;
architecture bhv of reg_5bits is
begin
process(CLK, D)
begin
if RST = '0' then--reset assíncrono do registrador.
Q <= "00000";
elsif
(CLK' event and CLK ='1') then--clock na borda de subida.
if EN = '1' then
Q <= D;
end if;
end if;
end process;
end bhv;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc545.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n01i00545ent IS
END c03s04b00x00p03n01i00545ent;
ARCHITECTURE c03s04b00x00p03n01i00545arch OF c03s04b00x00p03n01i00545ent IS
type TM is -- unconstrained array decl
array (Integer range <>) of Integer; -- No_failure_here
type FT is -- file decl
file of TM; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c03s04b00x00p03n01i00545"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n01i00545arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc545.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n01i00545ent IS
END c03s04b00x00p03n01i00545ent;
ARCHITECTURE c03s04b00x00p03n01i00545arch OF c03s04b00x00p03n01i00545ent IS
type TM is -- unconstrained array decl
array (Integer range <>) of Integer; -- No_failure_here
type FT is -- file decl
file of TM; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c03s04b00x00p03n01i00545"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n01i00545arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc545.vhd,v 1.2 2001-10-26 16:29:56 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c03s04b00x00p03n01i00545ent IS
END c03s04b00x00p03n01i00545ent;
ARCHITECTURE c03s04b00x00p03n01i00545arch OF c03s04b00x00p03n01i00545ent IS
type TM is -- unconstrained array decl
array (Integer range <>) of Integer; -- No_failure_here
type FT is -- file decl
file of TM; -- No_failure_here
BEGIN
TESTING: PROCESS
BEGIN
assert FALSE
report "***PASSED TEST: c03s04b00x00p03n01i00545"
severity NOTE;
wait;
END PROCESS TESTING;
END c03s04b00x00p03n01i00545arch;
|
-------------------------------------------------------------------------------
--! @file dpRamSplxNbe-e.vhd
--
--! @brief Simplex Dual Port Ram without byteenables entity
--
--! @details This is the Simplex DPRAM without byteenables entity.
--! The DPRAM has one write and one read port only.
--
-------------------------------------------------------------------------------
--
-- (c) B&R, 2013
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
--! use global library
use work.global.all;
entity dpRamSplxNbe is
generic (
--! Word width [bit]
gWordWidth : natural := 16;
--! Number of words
gNumberOfWords : natural := 1024;
--! Word width [bit]
--! Initialization file
gInitFile : string := "UNUSED"
);
port (
-- PORT A
--! Clock of port A
iClk_A : in std_logic;
--! Enable of port A
iEnable_A : in std_logic;
--! Write enable of port A
iWriteEnable_A : in std_logic;
--! Address of port A
iAddress_A : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Writedata of port A
iWritedata_A : in std_logic_vector(gWordWidth-1 downto 0);
-- PORT B
--! Clock of port B
iClk_B : in std_logic;
--! Enable of port B
iEnable_B : in std_logic;
--! Address of port B
iAddress_B : in std_logic_vector(logDualis(gNumberOfWords)-1 downto 0);
--! Readdata of port B
oReaddata_B : out std_logic_vector(gWordWidth-1 downto 0)
);
end dpRamSplxNbe;
|
-------------------------------------------------------------------------------------
-- Company: NTUA - BNL
-- Engineer: Paris Moschovakos, Panagiotis Gkountoumis & Christos Bakalis
--
-- Copyright Notice/Copying Permission:
-- Copyright 2017 Paris Moschovakos, Panagiotis Gkountoumis & Christos Bakalis
--
-- This file is part of NTUA-BNL_VMM_firmware.
--
-- NTUA-BNL_VMM_firmware is free software: you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- NTUA-BNL_VMM_firmware is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with NTUA-BNL_VMM_firmware. If not, see <http://www.gnu.org/licenses/>.
--
-- Create Date: 16.03.2016
-- Design Name: VMM boards firmware
-- Module Name: vmmFrontEnd.vhd
-- Project Name: Depends on the board
-- Target Devices: Artix7 xc7a200t-2fbg484 & xc7a200t-3fbg484
-- Tool Versions: Vivado 2017.2
--
-- Changelog:
-- 04.08.2016 Added the XADC Component and multiplexer to share fifo UDP Signals (Reid Pinkham)
-- 11.08.2016 Corrected the fifo resets to go through select_data (Reid Pinkham)
-- 16.09.2016 Added Dynamic IP configuration. (Lev Kurilenko)
-- 16.02.2017 Added new configuration component (udp_data_in_handler) (Christos Bakalis)
-- 27.02.2017 Changed main logic clock to 125MHz (Paris)
-- 10.03.2017 Added configurable CKTP/CKBC module. (Christos Bakalis)
-- 12.03.2017 Changed flow_fsm's primary cktp assertion to comply with cktp_gen
-- module. (Christos Bakalis)
-- 14.03.2017 Added register address/value configuration scheme. (Christos Bakalis)
-- 28.03.2017 Changes to accomodate to MMFE8 VMM3. (Christos Bakalis)
-- 31.03.2017 Added 2 CKBC readout mode (Paris)
-- 30.04.2017 Added vmm_readout_wrapper that contains level-0 readout mode besides
-- the pre-existing continuous mode. (Christos Bakalis)
-- 06.06.2017 Added ART readout handling (Paris)
-- 12.06.2017 Added support for MMFE1 board (Paris)
-- 21.06.2017 Added support for GPVMM board (Paris)
-- 22.06.2017 Added ODDRs for VMM clock forwarding optimization. (Christos Bakalis)
--
----------------------------------------------------------------------------------
library unisim;
use unisim.vcomponents.all;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity vmmFrontEnd is
port(
-- VMM signals
--------------------------------------
DATA0_1_P, DATA0_1_N : IN std_logic;
DATA0_2_P, DATA0_2_N : IN std_logic;
DATA0_3_P, DATA0_3_N : IN std_logic;
DATA0_4_P, DATA0_4_N : IN std_logic;
DATA0_5_P, DATA0_5_N : IN std_logic;
DATA0_6_P, DATA0_6_N : IN std_logic;
DATA0_7_P, DATA0_7_N : IN std_logic;
DATA0_8_P, DATA0_8_N : IN std_logic;
DATA1_1_P, DATA1_1_N : IN std_logic;
DATA1_2_P, DATA1_2_N : IN std_logic;
DATA1_3_P, DATA1_3_N : IN std_logic;
DATA1_4_P, DATA1_4_N : IN std_logic;
DATA1_5_P, DATA1_5_N : IN std_logic;
DATA1_6_P, DATA1_6_N : IN std_logic;
DATA1_7_P, DATA1_7_N : IN std_logic;
DATA1_8_P, DATA1_8_N : IN std_logic;
ART_1_P, ART_1_N : IN std_logic;
-- ART_2_P, ART_2_N : IN std_logic;
-- ART_3_P, ART_3_N : IN std_logic;
-- ART_4_P, ART_4_N : IN std_logic;
-- ART_5_P, ART_5_N : IN std_logic;
-- ART_6_P, ART_6_N : IN std_logic;
-- ART_7_P, ART_7_N : IN std_logic;
-- ART_8_P, ART_8_N : IN std_logic;
SDO_1 : IN std_logic;
SDO_2 : IN std_logic;
SDO_3 : IN std_logic;
SDO_4 : IN std_logic;
SDO_5 : IN std_logic;
SDO_6 : IN std_logic;
SDO_7 : IN std_logic;
SDO_8 : IN std_logic;
SDI_1 : OUT std_logic;
SDI_2 : OUT std_logic;
SDI_3 : OUT std_logic;
SDI_4 : OUT std_logic;
SDI_5 : OUT std_logic;
SDI_6 : OUT std_logic;
SDI_7 : OUT std_logic;
SDI_8 : OUT std_logic;
SCK_1 : OUT std_logic;
SCK_2 : OUT std_logic;
SCK_3 : OUT std_logic;
SCK_4 : OUT std_logic;
SCK_5 : OUT std_logic;
SCK_6 : OUT std_logic;
SCK_7 : OUT std_logic;
SCK_8 : OUT std_logic;
CS_1 : OUT std_logic;
CS_2 : OUT std_logic;
CS_3 : OUT std_logic;
CS_4 : OUT std_logic;
CS_5 : OUT std_logic;
CS_6 : OUT std_logic;
CS_7 : OUT std_logic;
CS_8 : OUT std_logic;
ENA_1_P, ENA_1_N : OUT std_logic;
ENA_2_P, ENA_2_N : OUT std_logic;
ENA_3_P, ENA_3_N : OUT std_logic;
ENA_4_P, ENA_4_N : OUT std_logic;
ENA_5_P, ENA_5_N : OUT std_logic;
ENA_6_P, ENA_6_N : OUT std_logic;
ENA_7_P, ENA_7_N : OUT std_logic;
ENA_8_P, ENA_8_N : OUT std_logic;
CKTK_1_P, CKTK_1_N : OUT std_logic;
CKTK_2_P, CKTK_2_N : OUT std_logic;
CKTK_3_P, CKTK_3_N : OUT std_logic;
CKTK_4_P, CKTK_4_N : OUT std_logic;
CKTK_5_P, CKTK_5_N : OUT std_logic;
CKTK_6_P, CKTK_6_N : OUT std_logic;
CKTK_7_P, CKTK_7_N : OUT std_logic;
CKTK_8_P, CKTK_8_N : OUT std_logic;
CKTP_1_P, CKTP_1_N : OUT std_logic;
CKTP_2_P, CKTP_2_N : OUT std_logic;
CKTP_3_P, CKTP_3_N : OUT std_logic;
CKTP_4_P, CKTP_4_N : OUT std_logic;
CKTP_5_P, CKTP_5_N : OUT std_logic;
CKTP_6_P, CKTP_6_N : OUT std_logic;
CKTP_7_P, CKTP_7_N : OUT std_logic;
CKTP_8_P, CKTP_8_N : OUT std_logic;
CKBC_1_P, CKBC_1_N : OUT std_logic;
CKBC_2_P, CKBC_2_N : OUT std_logic;
CKBC_3_P, CKBC_3_N : OUT std_logic;
CKBC_4_P, CKBC_4_N : OUT std_logic;
CKBC_5_P, CKBC_5_N : OUT std_logic;
CKBC_6_P, CKBC_6_N : OUT std_logic;
CKBC_7_P, CKBC_7_N : OUT std_logic;
CKBC_8_P, CKBC_8_N : OUT std_logic;
CKDT_1_P, CKDT_1_N : OUT std_logic;
CKDT_2_P, CKDT_2_N : OUT std_logic;
CKDT_3_P, CKDT_3_N : OUT std_logic;
CKDT_4_P, CKDT_4_N : OUT std_logic;
CKDT_5_P, CKDT_5_N : OUT std_logic;
CKDT_6_P, CKDT_6_N : OUT std_logic;
CKDT_7_P, CKDT_7_N : OUT std_logic;
CKDT_8_P, CKDT_8_N : OUT std_logic;
TKI_P, TKI_N : OUT std_logic;
TKO_P, TKO_N : IN std_logic;
CKART_1_P, CKART_1_N : OUT std_logic;
CKART_2_P, CKART_2_N : OUT std_logic;
CKART_3_P, CKART_3_N : OUT std_logic;
CKART_4_P, CKART_4_N : OUT std_logic;
CKART_5_P, CKART_5_N : OUT std_logic;
CKART_6_P, CKART_6_N : OUT std_logic;
CKART_7_P, CKART_7_N : OUT std_logic;
CKART_8_P, CKART_8_N : OUT std_logic;
SETT_P, SETT_N : OUT std_logic;
SETB_P, SETB_N : OUT std_logic;
CK6B_1_P, CK6B_1_N : OUT std_logic;
CK6B_2_P, CK6B_2_N : OUT std_logic;
CK6B_3_P, CK6B_3_N : OUT std_logic;
CK6B_4_P, CK6B_4_N : OUT std_logic;
CK6B_5_P, CK6B_5_N : OUT std_logic;
CK6B_6_P, CK6B_6_N : OUT std_logic;
CK6B_7_P, CK6B_7_N : OUT std_logic;
CK6B_8_P, CK6B_8_N : OUT std_logic;
-- ADDC ART CLK
--------------------------------------
CKART_ADDC_P : OUT std_logic;
CKART_ADDC_N : OUT std_logic;
-- MDT_446/MDT_MU2E Specific Pins
--------------------------------------
TRIGGER_OUT_P : OUT std_logic;
TRIGGER_OUT_N : OUT std_logic;
CH_TRIGGER : IN std_logic;
MO : OUT std_logic;
ART_OUT_P, ART_OUT_N : OUT std_logic;
-- xADC Interface
--------------------------------------
VP_0 : IN std_logic;
VN_0 : IN std_logic;
Vaux0_v_n : IN std_logic;
Vaux0_v_p : IN std_logic;
Vaux1_v_n : IN std_logic;
Vaux1_v_p : IN std_logic;
Vaux2_v_n : IN std_logic;
Vaux2_v_p : IN std_logic;
Vaux3_v_n : IN std_logic;
Vaux3_v_p : IN std_logic;
Vaux8_v_n : IN std_logic;
Vaux8_v_p : IN std_logic;
Vaux9_v_n : IN std_logic;
Vaux9_v_p : IN std_logic;
Vaux10_v_n : IN std_logic;
Vaux10_v_p : IN std_logic;
Vaux11_v_n : IN std_logic;
Vaux11_v_p : IN std_logic;
MuxAddr0 : OUT std_logic;
MuxAddr1 : OUT std_logic;
MuxAddr2 : OUT std_logic;
MuxAddr3_p : OUT std_logic;
MuxAddr3_n : OUT std_logic;
-- 200.0359MHz from bank 14
--------------------------------------
X_2V5_DIFF_CLK_P : IN std_logic;
X_2V5_DIFF_CLK_N : IN std_logic;
-- Tranceiver interface
--------------------------------------
gtrefclk_p : IN std_logic; -- Differential +ve of reference clock for tranceiver: 125MHz, very high quality
gtrefclk_n : IN std_logic; -- Differential -ve of reference clock for tranceiver: 125MHz, very high quality
txp : OUT std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : OUT std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : IN std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : IN std_logic; -- Differential -ve for serial reception from PMD to PMA.
phy_int : OUT std_logic;
phy_rstn_out : OUT std_logic;
-- AXI4SPI Flash Configuration
---------------------------------------
IO0_IO : INOUT std_logic;
IO1_IO : INOUT std_logic;
SS_IO : INOUT std_logic
);
end vmmFrontEnd;
architecture Behavioral of vmmFrontEnd is
-------------------------------------------------------------------
-- Global Settings
-------------------------------------------------------------------
-- Default IP and MAC address of the board
signal default_IP : std_logic_vector(31 downto 0) := x"c0a80002";
signal default_MAC : std_logic_vector(47 downto 0) := x"002320189223";
signal default_destIP : std_logic_vector(31 downto 0) := x"c0a80010";
-- Set to '1' for MMFE8 or '0' for 1-VMM boards
constant is_mmfe8 : std_logic := '0';
-- Set to '0' for continuous readout mode or '1' for L0 readout mode
constant vmmReadoutMode : std_logic := '1';
-- Set to '1' to enable the ART header
constant artEnabled : std_logic := '1';
-------------------------------------------------------------------
-- Transceiver, TEMAC, UDP_ICMP block
-------------------------------------------------------------------
-- clock generation signals for transceiver
signal gtrefclkp, gtrefclkn : std_logic; -- Route gtrefclk through an IBUFG.
signal txoutclk : std_logic; -- txoutclk from GT transceiver
signal resetdone : std_logic; -- To indicate that the GT transceiver has completed its reset cycle
signal mmcm_locked : std_logic; -- MMCM locked signal.
signal mmcm_reset : std_logic; -- MMCM reset signal.
signal clkfbout : std_logic; -- MMCM feedback clock
signal userclk : std_logic; -- 62.5MHz clock for GT transceiver Tx/Rx user clocks
signal userclk2 : std_logic; -- 125MHz clock for core reference clock.
-- PMA reset generation signals for tranceiver
signal pma_reset_pipe : std_logic_vector(3 downto 0); -- flip-flop pipeline for reset duration stretch
signal pma_reset : std_logic; -- Synchronous transcevier PMA reset
-- An independent clock source used as the reference clock for an
-- IDELAYCTRL (if present) and for the main GT transceiver reset logic.
signal independent_clock_bufg: std_logic;
-- clock generation signals for SGMII clock
signal sgmii_clk_r : std_logic; -- Clock to client MAC (125MHz, 12.5MHz or 1.25MHz) (to rising edge DDR).
signal sgmii_clk_f : std_logic; -- Clock to client MAC (125MHz, 12.5MHz or 1.25MHz) (to falling edge DDR).
-- GMII signals
signal gmii_isolate : std_logic; -- Internal gmii_isolate signal.
signal gmii_txd_int : std_logic_vector(7 downto 0); -- Internal gmii_txd signal (between core and SGMII adaptation module).
signal gmii_tx_en_int : std_logic; -- Internal gmii_tx_en signal (between core and SGMII adaptation module).
signal gmii_tx_er_int : std_logic; -- Internal gmii_tx_er signal (between core and SGMII adaptation module).
signal gmii_rxd_int : std_logic_vector(7 downto 0); -- Internal gmii_rxd signal (between core and SGMII adaptation module).
signal gmii_rx_dv_int : std_logic; -- Internal gmii_rx_dv signal (between core and SGMII adaptation module).
signal gmii_rx_er_int : std_logic; -- Internal gmii_rx_er signal (between core and SGMII adaptation module).
signal phy_rstn : std_logic := '0';
-- Extra registers to ease IOB placement
signal status_vector_int : std_logic_vector(15 downto 0);
signal gmii_txd_emac : std_logic_vector(7 downto 0);
signal gmii_tx_en_emac : std_logic;
signal gmii_tx_er_emac : std_logic;
signal gmii_rxd_emac : std_logic_vector(7 downto 0);
signal gmii_rx_dv_emac : std_logic;
signal gmii_rx_er_emac : std_logic;
signal speed_is_10_100 : std_logic;
signal speed_is_100 : std_logic;
signal tx_axis_mac_tready_int : std_logic;
signal rx_axis_mac_tuser_int : std_logic;
signal rx_axis_mac_tlast_int : std_logic;
signal rx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal rx_axis_mac_tvalid_int : std_logic;
signal local_gtx_reset : std_logic;
signal rx_reset : std_logic;
signal tx_reset : std_logic;
signal gtx_pre_resetn : std_logic := '0';
signal tx_axis_mac_tdata_int : std_logic_vector(7 downto 0);
signal tx_axis_mac_tvalid_int : std_logic;
signal tx_axis_mac_tlast_int : std_logic;
signal gtx_resetn : std_logic;
signal glbl_rstn : std_logic := '1';
signal glbl_rst_i : std_logic := '0';
signal gtx_clk_reset_int : std_logic;
signal an_restart_config_int : std_logic;
signal rx_axis_mac_tready_int : std_logic;
signal rx_configuration_vector_int : std_logic_vector(79 downto 0);
signal tx_configuration_vector_int : std_logic_vector(79 downto 0);
signal vector_resetn : std_logic := '0';
signal vector_pre_resetn : std_logic := '0';
signal vector_reset_int : std_logic;
signal clk_enable_int : std_logic;
signal sgmii_clk_int_oddr : std_logic;
signal udp_txi_int : udp_tx_type;
signal control : udp_control_type;
signal udp_rx_int : udp_rx_type;
signal ip_rx_hdr_int : ipv4_rx_header_type;
signal udp_tx_data_out_ready_int : std_logic;
signal udp_tx_start_int : std_logic;
signal icmp_rx_start : std_logic;
signal icmp_rxo : icmp_rx_type;
signal user_data_out_i : std_logic_vector(15 downto 0);
signal end_packet_i : std_logic := '0';
signal we_conf_int : std_logic := '0';
signal packet_length_int : std_logic_vector(11 downto 0);
signal daq_data_out_i : std_logic_vector(15 downto 0);
signal daq_wr_en_i : std_logic := '0';
signal start_conf_proc_int : std_logic := '0';
-------------------------------------------------
-- VMM/FPGA Configuration Signals
-------------------------------------------------
signal vmm_sdo_vec_i : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_cs_all : std_logic := '0';
signal vmm_sck_all : std_logic := '0';
signal vmm_sdi_all : std_logic := '0';
signal vmm_bitmask : std_logic_vector(7 downto 0) := "11111111";
signal vmm_bitmask_1VMM : std_logic_vector(7 downto 0) := "11111111";
signal vmm_bitmask_8VMM : std_logic_vector(7 downto 0) := "11111111";
signal sel_cs : std_logic_vector(1 downto 0) := (others => '0');
signal VMM_CS_i : std_logic := '0';
signal vmm_cs_vec_obuf : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_sck_vec_obuf : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_ena_vec_obuf : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_sdi_vec_obuf : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_ckbc_vec : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_cktp_vec : std_logic_vector(8 downto 1) := (others => '0');
signal ckart_vec : std_logic_vector(9 downto 1) := (others => '0');
signal conf_di_i : std_logic := '0';
signal conf_ena_i : std_logic := '0';
signal conf_wen_i : std_logic := '0';
signal cnt_vmm : integer range 0 to 7 := 0;
signal tko_i : std_logic;
signal MO_i : std_logic := 'Z';
signal end_packet_conf_int: std_logic := '0';
signal end_packet_daq_int : std_logic := '0';
signal is_state : std_logic_vector(3 downto 0) := "1010";
signal latency_conf : std_logic_vector(15 downto 0) := x"0000";
signal art_cnt2 : integer range 0 to 127 := 0;
signal art2 : std_logic := '0';
signal reset_FF : std_logic := '0';
signal wait_cnt : unsigned(7 downto 0) := (others => '0');
signal vmm_id_rdy : std_logic := '0';
signal vmm_conf : std_logic := '0';
signal newIP_rdy : std_logic := '0';
signal xadc_conf_rdy : std_logic := '0';
signal daq_on : std_logic := '0';
signal vmmConf_done : std_logic := '0';
signal flash_busy : std_logic := '0';
signal inhibit_conf : std_logic := '0';
signal conf_state : std_logic_vector(2 downto 0) := b"000";
signal serial_number : std_logic_vector(31 downto 0) := x"00000000";
signal packet_len_conf : std_logic_vector(11 downto 0) := x"000";
signal fpga_rst_i : std_logic := '0';
signal reply_done : std_logic := '0';
signal reply_enable : std_logic := '0';
signal glbl_fifo_init : std_logic := '1'; --synced@200Mhz
signal glbl_fifo_init_s0 : std_logic := '1';
signal glbl_fifo_init_s1 : std_logic := '1'; --synced@125Mhz
-------------------------------------------------
-- VMM Signals
-------------------------------------------------
signal cktk_out_vec : std_logic_vector(8 downto 1);
signal ckdt_out_vec : std_logic_vector(8 downto 1);
signal data0_in_vec : std_logic_vector(8 downto 1);
signal data1_in_vec : std_logic_vector(8 downto 1);
signal art_in_vec : std_logic_vector(8 downto 1) := (others => '0');
signal vmm_tki : std_logic := '0';
signal vmm_cktp_primary : std_logic := '0';
signal CKTP_glbl : std_logic := '0';
signal vmm_ena_all : std_logic := '0';
-------------------------------------------------
-- Readout Signals
-------------------------------------------------
signal daq_enable_i : std_logic := '0';
signal daqFIFO_wr_en_i : std_logic := '0';
signal daqFIFO_din_i : std_logic_vector(15 downto 0);
signal vmmWordReady_i : std_logic := '0';
signal vmmWord_i : std_logic_vector(15 downto 0);
signal vmmEventDone_i : std_logic := '0';
signal daqFIFO_reset : std_logic := '0';
signal daq_vmm_ena_wen_enable : std_logic_vector(8 downto 1) := (others => '0');
signal daq_cktk_out_enable : std_logic_vector(8 downto 1) := (others => '0');
signal linkHealth_bmsk : std_logic_vector(8 downto 1) := (others => '0');
signal UDPDone : std_logic;
signal ckbc_enable : std_logic := '0';
signal cktp_enable : std_logic := '0';
signal dt_state : std_logic_vector(3 downto 0) := b"0000";
signal dt_cntr_st : std_logic_vector(3 downto 0) := b"0000";
signal rst_l0_buff : std_logic := '0';
signal rst_l0_buff_flow : std_logic := '1';
signal rst_l0_pf : std_logic := '0';
signal level_0 : std_logic := '0';
signal daq_on_inhib : std_logic := '1';
signal CKDT_glbl : std_logic := '0';
signal vmm_ckdt_enable : std_logic_vector(8 downto 1) := (others => '0');
-------------------------------------------------
-- Trigger Signals
-------------------------------------------------
signal tren : std_logic := '0';
signal tr_hold : std_logic := '0';
signal trmode : std_logic := '0';
signal ext_trigger_in : std_logic := '0';
signal tr_reset : std_logic := '0';
signal tr_out_i : std_logic;
signal trig_mode_int : std_logic := '0';
signal CH_TRIGGER_i : std_logic := '0';
signal request2ckbc : std_logic := '0';
signal trraw_synced125_i : std_logic := '0';
signal accept_wr : std_logic := '0';
signal vmmArtData : std_logic_vector(5 downto 0) := (others => '0');
signal vmmArtReady : std_logic := '0';
-------------------------------------------------
-- Event Timing & Soft Reset
-------------------------------------------------
signal etr_vmm_wen_vec : std_logic_vector(8 downto 1) := ( others => '0' );
signal etr_vmm_ena_vec : std_logic_vector(8 downto 1) := ( others => '0' );
signal etr_reset_latched: std_logic;
signal glBCID_i : std_logic_vector(11 downto 0) := ( others => '0' );
signal state_rst_etr_i : std_logic_vector(2 downto 0) := ( others => '0' );
signal rst_etr_i : std_logic;
signal rst_done_etr_i : std_logic;
-------------------------------------------------
-- Packet Formation Signals
-------------------------------------------------
signal pf_newCycle : std_logic;
signal pf_packLen : std_logic_vector(11 downto 0);
signal pf_trigVmmRo : std_logic := '0';
signal pf_vmmIdRo : std_logic_vector(2 downto 0) := b"000";
signal pf_rst_flow : std_logic := '0';
signal rst_vmm : std_logic := '0';
signal pf_rst_FIFO : std_logic := '0';
signal pfBusy_i : std_logic := '0';
signal pf_dbg_st : std_logic_vector(4 downto 0) := b"00000";
signal rd_ena_buff : std_logic := '0';
signal pf_rst_final : std_logic := '0';
-------------------------------------------------
-- FIFO2UDP Signals
-------------------------------------------------
signal FIFO2UDP_state : std_logic_vector(3 downto 0) := b"0000";
signal faifouki : std_logic := '0';
------------------------------------------------------------------
-- xADC signals
------------------------------------------------------------------
signal xadc_start : std_logic;
signal vmm_id_xadc : std_logic_vector (15 downto 0) := (others => '0');
signal xadc_sample_size : std_logic_vector (10 downto 0) := "01111111111"; -- 1023 packets
signal xadc_delay : std_logic_vector (17 downto 0) := "011111111111111111"; -- 1023 samples over ~0.7 seconds
signal xadc_end_of_data : std_logic;
signal xadc_fifo_bus : std_logic_vector (15 downto 0);
signal xadc_fifo_enable : std_logic;
signal xadc_packet_len : std_logic_vector (11 downto 0);
signal xadc_busy : std_logic;
signal MuxAddr0_i : std_logic := '0';
signal MuxAddr1_i : std_logic := '0';
signal MuxAddr2_i : std_logic := '0';
signal MuxAddr3_p_i : std_logic := '0';
signal MuxAddr3_n_i : std_logic := '0';
------------------------------------------------------------------
-- Dynamic IP signals
------------------------------------------------------------------
signal myIP_set : std_logic_vector (31 downto 0);
signal myMAC_set : std_logic_vector (47 downto 0);
signal destIP_set : std_logic_vector (31 downto 0);
signal myIP : std_logic_vector (31 downto 0);
signal myMAC : std_logic_vector (47 downto 0);
signal destIP : std_logic_vector (31 downto 0);
signal newIP_start : std_logic;
signal io0_i : std_logic:= '0';
signal io0_o : std_logic:= '0';
signal io0_t : std_logic:= '0';
signal io1_i : std_logic:= '0';
signal io1_o : std_logic:= '0';
signal io1_t : std_logic:= '0';
signal ss_i : std_logic_vector(0 DOWNTO 0):=(others => '0');
signal ss_o : std_logic_vector(0 DOWNTO 0):=(others => '0');
signal ss_t : std_logic:= '0';
------------------------------------------------------------------
-- MMCM + CKBC/CKTP Generator signals
------------------------------------------------------------------
signal clk_160 : std_logic := '0';
signal clk_500 : std_logic := '0';
signal clk_200 : std_logic := '0';
signal clk_40 : std_logic := '0';
signal clk_50 : std_logic := '0';
signal master_locked : std_logic := '0';
signal CKBC_glbl : std_logic := '0';
signal cktp_pulse_width : std_logic_vector(7 downto 0) := x"04"; -- 2 us
signal cktp_period : std_logic_vector(15 downto 0) := x"1388"; -- 1 ms
signal cktp_skew : std_logic_vector(7 downto 0) := (others => '0');
signal ckbc_freq : std_logic_vector(7 downto 0) := x"28"; --40 Mhz
signal cktp_max_num : std_logic_vector(15 downto 0) := x"ffff";
signal cktk_max_num : std_logic_vector(7 downto 0) := x"07";
signal ckbcMode : std_logic := '0';
signal CKTP_raw : std_logic := '0';
signal ckbc_max_num : std_logic_vector(7 downto 0) := x"20";
-------------------------------------------------
-- Flow FSM signals
-------------------------------------------------
type state_t is (IDLE, WAIT_FOR_CONF, CONFIGURE, CONF_DONE, CONFIGURE_DELAY, SEND_CONF_REPLY, DAQ_INIT, FIRST_RESET, TRIG, DAQ, XADC_init, XADC_wait, FLASH_init, FLASH_wait);
signal state : state_t := IDLE;
signal rstFIFO_flow : std_logic := '0';
signal rstFIFO_top : std_logic := '0';
-------------------------------------------------
-- Debugging Signals
-------------------------------------------------
signal overviewProbe : std_logic_vector(63 downto 0);
signal vmmSignalsProbe : std_logic_vector(63 downto 0);
signal triggerETRProbe : std_logic_vector(63 downto 0);
signal configurationProbe : std_logic_vector(63 downto 0);
signal readoutProbe : std_logic_vector(63 downto 0);
signal dataOutProbe : std_logic_vector(63 downto 0);
signal flowProbe : std_logic_vector(63 downto 0);
signal trigger_i : std_logic;
-------------------------------------------------------------------
-- These attribute will stop timing errors being reported in back
-- annotated SDF simulation.
-------------------------------------------------------------------
attribute ASYNC_REG : string;
attribute ASYNC_REG of pma_reset_pipe : signal is "TRUE";
attribute ASYNC_REG of glbl_fifo_init_s0 : signal is "TRUE";
attribute ASYNC_REG of glbl_fifo_init_s1 : signal is "TRUE";
-------------------------------------------------------------------
-- Keep signals for ILA
-------------------------------------------------------------------
attribute keep : string;
attribute dont_touch : string;
attribute mark_debug : string;
-------------------------------------------------------------------
-- IOB attribute for VMM pins
-------------------------------------------------------------------
attribute IOB : string;
-- data0
attribute IOB of DATA0_1_P : signal is "TRUE";
attribute IOB of DATA0_1_N : signal is "TRUE";
attribute IOB of DATA0_2_P : signal is "TRUE";
attribute IOB of DATA0_2_N : signal is "TRUE";
attribute IOB of DATA0_3_P : signal is "TRUE";
attribute IOB of DATA0_3_N : signal is "TRUE";
attribute IOB of DATA0_4_P : signal is "TRUE";
attribute IOB of DATA0_4_N : signal is "TRUE";
attribute IOB of DATA0_5_P : signal is "TRUE";
attribute IOB of DATA0_5_N : signal is "TRUE";
attribute IOB of DATA0_6_P : signal is "TRUE";
attribute IOB of DATA0_6_N : signal is "TRUE";
attribute IOB of DATA0_7_P : signal is "TRUE";
attribute IOB of DATA0_7_N : signal is "TRUE";
attribute IOB of DATA0_8_P : signal is "TRUE";
attribute IOB of DATA0_8_N : signal is "TRUE";
-- data1
attribute IOB of DATA1_1_P : signal is "TRUE";
attribute IOB of DATA1_1_N : signal is "TRUE";
attribute IOB of DATA1_2_P : signal is "TRUE";
attribute IOB of DATA1_2_N : signal is "TRUE";
attribute IOB of DATA1_3_P : signal is "TRUE";
attribute IOB of DATA1_3_N : signal is "TRUE";
attribute IOB of DATA1_4_P : signal is "TRUE";
attribute IOB of DATA1_4_N : signal is "TRUE";
attribute IOB of DATA1_5_P : signal is "TRUE";
attribute IOB of DATA1_5_N : signal is "TRUE";
attribute IOB of DATA1_6_P : signal is "TRUE";
attribute IOB of DATA1_6_N : signal is "TRUE";
attribute IOB of DATA1_7_P : signal is "TRUE";
attribute IOB of DATA1_7_N : signal is "TRUE";
attribute IOB of DATA1_8_P : signal is "TRUE";
attribute IOB of DATA1_8_N : signal is "TRUE";
-- cktk
attribute IOB of CKTK_1_P : signal is "TRUE";
attribute IOB of CKTK_1_N : signal is "TRUE";
attribute IOB of CKTK_2_P : signal is "TRUE";
attribute IOB of CKTK_2_N : signal is "TRUE";
attribute IOB of CKTK_3_P : signal is "TRUE";
attribute IOB of CKTK_3_N : signal is "TRUE";
attribute IOB of CKTK_4_P : signal is "TRUE";
attribute IOB of CKTK_4_N : signal is "TRUE";
attribute IOB of CKTK_5_P : signal is "TRUE";
attribute IOB of CKTK_5_N : signal is "TRUE";
attribute IOB of CKTK_6_P : signal is "TRUE";
attribute IOB of CKTK_6_N : signal is "TRUE";
attribute IOB of CKTK_7_P : signal is "TRUE";
attribute IOB of CKTK_7_N : signal is "TRUE";
attribute IOB of CKTK_8_P : signal is "TRUE";
attribute IOB of CKTK_8_N : signal is "TRUE";
-- sdi
attribute IOB of SDI_1 : signal is "TRUE";
attribute IOB of SDI_2 : signal is "TRUE";
attribute IOB of SDI_3 : signal is "TRUE";
attribute IOB of SDI_4 : signal is "TRUE";
attribute IOB of SDI_5 : signal is "TRUE";
attribute IOB of SDI_6 : signal is "TRUE";
attribute IOB of SDI_7 : signal is "TRUE";
attribute IOB of SDI_8 : signal is "TRUE";
-------------------------------------------------------------------
-- Readout Monitoring
-------------------------------------------------------------------
-- attribute keep of vmm_ena : signal is "true";
-- attribute dont_touch of vmm_ena : signal is "true";
-- attribute keep of vmm_wen_vec : signal is "true";
-- attribute dont_touch of vmm_wen_vec : signal is "true";
-- attribute keep of cktk_out_vec : signal is "true";
-- attribute dont_touch of cktk_out_vec : signal is "true";
-- attribute keep of cktk_out_i : signal is "true";
-- attribute keep of ckdt_out_vec : signal is "true";
-- attribute keep of vmm_do_vec_i : signal is "true";
-- attribute keep of daq_vmm_ena_wen_enable: signal is "true";
-- attribute keep of vmm_id_int : signal is "true";
-- attribute keep of data0_in_vec : signal is "true";
-- attribute dont_touch of data0_in_vec : signal is "true";
-- attribute keep of ro_cktk_out_vec : signal is "true";
-- attribute dont_touch of ro_cktk_out_vec : signal is "true";
-------------------------------------------------------------------
-- Trigger
-------------------------------------------------------------------
-- attribute keep of tren : signal is "true";
-- attribute keep of ext_trigger_in : signal is "true";
-- attribute keep of trig_mode_int : signal is "true";
-- attribute keep of tr_hold : signal is "true";
-- attribute dont_touch of tr_hold : signal is "true";
-- attribute mark_debug of tr_hold : signal is "true";
-------------------------------------------------------------------
-- Event Timing & Soft Reset
-------------------------------------------------------------------
-- attribute keep of etr_reset_latched : signal is "true";
-- attribute keep of rst_vmm : signal is "true";
-- attribute keep of etr_vmm_ena_vec : signal is "true";
-- attribute keep of daq_enable_i : signal is "true";
-- attribute keep of glBCID_i : signal is "true";
-- attribute dont_touch of glBCID_i : signal is "true";
-- attribute keep of state_rst_etr_i : signal is "true";
-- attribute dont_touch of state_rst_etr_i : signal is "true";
-- attribute keep of rst_etr_i : signal is "true";
-- attribute dont_touch of rst_etr_i : signal is "true";
-- attribute keep of rst_done_etr_i : signal is "true";
-- attribute dont_touch of rst_done_etr_i : signal is "true";
-------------------------------------------------------------------
-- Packet Formation
-------------------------------------------------------------------
-- attribute keep of pf_newCycle : signal is "true";
-- attribute keep of pfBusy_i : signal is "true";
-- attribute dont_touch of pfBusy_i : signal is "true";
-------------------------------------------------------------------
-- Dynamic IP
-------------------------------------------------------------------
-- attribute keep of io0_i : signal is "TRUE";
-- attribute keep of io0_o : signal is "TRUE";
-- attribute keep of io0_t : signal is "TRUE";
-- attribute keep of io1_i : signal is "TRUE";
-- attribute keep of io1_o : signal is "TRUE";
-- attribute keep of io1_t : signal is "TRUE";
-- attribute keep of ss_i : signal is "TRUE";
-- attribute keep of ss_o : signal is "TRUE";
-- attribute keep of ss_t : signal is "TRUE";
-------------------------------------------------------------------
-- Overview
-------------------------------------------------------------------
-- attribute mark_debug of is_state : signal is "TRUE";
-- attribute mark_debug of pf_dbg_st : signal is "TRUE";
-- attribute mark_debug of FIFO2UDP_state : signal is "TRUE";
-- attribute mark_debug of UDPDone : signal is "TRUE";
-- attribute mark_debug of CKBC_glbl : signal is "TRUE";
-- attribute mark_debug of tr_out_i : signal is "TRUE";
-- attribute mark_debug of conf_state : signal is "TRUE";
-- attribute mark_debug of rd_ena_buff : signal is "TRUE";
-- attribute mark_debug of vmmWord_i : signal is "TRUE";
-- attribute mark_debug of CKTP_glbl : signal is "TRUE";
-- attribute mark_debug of level_0 : signal is "TRUE";
-- attribute mark_debug of rst_l0_pf : signal is "TRUE";
-- attribute mark_debug of vmmWordReady_i : signal is "TRUE";
-- attribute mark_debug of vmmEventDone_i : signal is "TRUE";
-- attribute mark_debug of dt_state : signal is "TRUE";
-- attribute mark_debug of daq_data_out_i : signal is "TRUE";
-- attribute mark_debug of daq_enable_i : signal is "TRUE";
-- attribute mark_debug of pf_trigVmmRo : signal is "TRUE";
-- attribute mark_debug of dt_cntr_st : signal is "TRUE";
-- attribute mark_debug of linkHealth_bmsk : signal is "TRUE";
-------------------------------------------------------------------
-- Other
-------------------------------------------------------------------
-------------------------------------------------------------------
-- COMPONENTS --
-------------------------------------------------------------------
-- 1. clk_wiz_gen
-- 2. event_timing_reset
-- 3. vmm_readout_wrapper
-- 4. FIFO2UDP
-- 5. trigger
-- 6. packet_formation
-- 7. gig_ethernet_pcs_pma_0
-- 8. UDP_Complete_nomac
-- 9. temac_10_100_1000_fifo_block
-- 10. temac_10_100_1000_reset_sync
-- 11. temac_10_100_1000_config_vector_sm
-- 12. i2c_top
-- 13. udp_data_in_handler
-- 14. udp_reply_handler
-- 15. select_data
-- 16. ila_top_level
-- 17. xadc
-- 18. AXI4_SPI
-- 19. VIO_IP
-- 20. clk_gen_wrapper
-- 21. ila_overview
-- 22. art
-- 23. vmm_oddr_wrapper
-------------------------------------------------------------------
-- 1
component clk_wiz_gen
port
( -- Clock in ports
clk_in1_p : in std_logic;
clk_in1_n : in std_logic;
-- Clock out ports
clk_out_160 : out std_logic;
clk_out_500 : out std_logic;
clk_out_200 : out std_logic;
clk_out_50 : out std_logic;
clk_out_40 : out std_logic;
-- Status and control signals
reset : in std_logic;
gen_locked : out std_logic
);
end component;
-- 2
component event_timing_reset
port(
hp_clk : in std_logic;
clk : in std_logic;
clk_10_phase45 : in std_logic;
bc_clk : in std_logic;
daqEnable : in std_logic;
pfBusy : in std_logic;
reset : in std_logic;
glBCID : out std_logic_vector(11 downto 0);
prec_cnt : out std_logic_vector(4 downto 0);
state_rst_out : out std_logic_vector(2 downto 0);
rst_o : out std_logic;
rst_done_o : out std_logic;
vmm_ena_vec : out std_logic_vector(8 downto 1);
vmm_wen_vec : out std_logic_vector(8 downto 1);
reset_latched : out std_logic
);
end component;
-- 3
component vmm_readout_wrapper is
generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic);
port (
------------------------------------
--- Continuous Readout Interface ---
clkTkProc : in std_logic; -- Used to clock checking for data process
clkDtProc : in std_logic; -- Used to clock word readout process
clk : in std_logic; -- Main clock
--
daq_enable : in std_logic;
trigger_pulse : in std_logic; -- Trigger
cktk_max : in std_logic_vector(7 downto 0); -- Max number of CKTKs
--
dt_state_o : out std_logic_vector(3 downto 0); -- for debugging
dt_cntr_st_o : out std_logic_vector(3 downto 0); -- for debugging
------------------------------------
---- Level-0 Readout Interface -----
clk_ckdt : in std_logic; -- will be forwarded to the VMM
rst_buff : in std_logic; -- reset the level-0 buffer
rst_intf_proc : in std_logic; -- reset the pf interface
--
level_0 : in std_logic; -- level-0 signal
wr_accept : in std_logic; -- buffer acceptance window
--
vmm_conf : in std_logic; -- high during VMM configuration
daq_on_inhib : out std_logic; -- prevent daq_on state before checking link health
------------------------------------
---- Packet Formation Interface ----
vmmWordReady : out std_logic;
vmmWord : out std_logic_vector(15 downto 0);
vmmEventDone : out std_logic;
rd_ena_buff : in std_logic; -- read the readout buffer (level0 or continuous)
vmmId : in std_logic_vector(2 downto 0); -- VMM to be readout
linkHealth_bmsk : out std_logic_vector(8 downto 1); -- status of comma alignment links
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec : in std_logic_vector(8 downto 1); -- Single-ended data0 from VMM
vmm_data1_vec : in std_logic_vector(8 downto 1); -- Single-ended data1 from VMM
vmm_ckdt_glbl : out std_logic; -- Strobe to VMM CKDT
vmm_ckdt_enable : out std_logic_vector(8 downto 1); -- Enable signal for VMM CKDT
vmm_cktk_vec : out std_logic_vector(8 downto 1) -- Strobe to VMM CKTK
);
end component;
-- 4
component FIFO2UDP
port (
clk_125 : in std_logic;
destinationIP : in std_logic_vector(31 downto 0);
daq_data_in : in std_logic_vector(15 downto 0);
fifo_data_out : out std_logic_vector (7 downto 0);
udp_txi : out udp_tx_type;
udp_tx_start : out std_logic;
re_out : out std_logic;
control : out std_logic;
UDPDone : out std_logic;
udp_tx_data_out_ready : in std_logic;
wr_en : in std_logic;
end_packet : in std_logic;
global_reset : in std_logic;
packet_length_in : in std_logic_vector(11 downto 0);
reset_DAQ_FIFO : in std_logic;
vmmID : in std_logic_vector(2 downto 0);
confReply_packet : in std_logic;
trigger_out : out std_logic;
count_o : out std_logic_vector(3 downto 0);
faifouki : out std_logic
);
end component;
-- 5
component trigger is
generic (vmmReadoutMode : std_logic);
port (
clk : in std_logic;
ckbc : in std_logic;
clk_art : in std_logic;
rst_trig : in std_logic;
ckbcMode : in std_logic;
cktp_enable : in std_logic;
cktp_pulse_width: in std_logic_vector(4 downto 0);
CKTP_raw : in std_logic;
request2ckbc : out std_logic;
accept_wr : out std_logic;
pfBusy : in std_logic;
tren : in std_logic;
tr_hold : in std_logic;
trmode : in std_logic;
trext : in std_logic;
reset : in std_logic;
level_0 : out std_logic;
event_counter : out std_logic_vector(31 DOWNTO 0);
tr_out : out std_logic;
trraw_synced125 : out std_logic;
latency : in std_logic_vector(15 DOWNTO 0)
);
end component;
-- 6
component packet_formation is
generic(is_mmfe8 : std_logic;
vmmReadoutMode : std_logic;
artEnabled : std_logic);
port (
clk : in std_logic;
newCycle : in std_logic;
trigVmmRo : out std_logic;
vmmId : out std_logic_vector(2 downto 0);
vmmWord : in std_logic_vector(15 downto 0);
vmmWordReady : in std_logic;
vmmEventDone : in std_logic;
UDPDone : in std_logic;
pfBusy : out std_logic;
glBCID : in std_logic_vector(11 downto 0);
packLen : out std_logic_vector(11 downto 0);
dataout : out std_logic_vector(15 downto 0);
wrenable : out std_logic;
end_packet : out std_logic;
rd_ena_buff : out std_logic;
rst_l0 : out std_logic;
tr_hold : out std_logic;
reset : in std_logic;
rst_vmm : out std_logic;
linkHealth_bmsk : in std_logic_vector(8 downto 1);
rst_FIFO : out std_logic;
latency : in std_logic_vector(15 downto 0);
dbg_st_o : out std_logic_vector(4 downto 0);
trraw_synced125 : in std_logic;
vmmArtData125 : in std_logic_vector(5 downto 0);
vmmArtReady : in std_logic
);
end component;
-- 7
component gig_ethernet_pcs_pma_0
port(
-- Transceiver Interface
---------------------
gtrefclk_p : in std_logic;
gtrefclk_n : in std_logic;
gtrefclk_out : out std_logic; -- Very high quality clock for GT transceiver.
gtrefclk_bufg_out : out std_logic;
txp : out std_logic; -- Differential +ve of serial transmission from PMA to PMD.
txn : out std_logic; -- Differential -ve of serial transmission from PMA to PMD.
rxp : in std_logic; -- Differential +ve for serial reception from PMD to PMA.
rxn : in std_logic; -- Differential -ve for serial reception from PMD to PMA.
resetdone : out std_logic; -- The GT transceiver has completed its reset cycle
userclk_out : out std_logic;
userclk2_out : out std_logic;
rxuserclk_out : out std_logic;
rxuserclk2_out : out std_logic;
pma_reset_out : out std_logic; -- transceiver PMA reset signal
mmcm_locked_out : out std_logic; -- MMCM Locked
independent_clock_bufg : in std_logic;
-- GMII Interface
-----------------
sgmii_clk_r : out std_logic;
sgmii_clk_f : out std_logic;
sgmii_clk_en : out std_logic; -- Clock enable for client MAC
gmii_txd : in std_logic_vector(7 downto 0); -- Transmit data from client MAC.
gmii_tx_en : in std_logic; -- Transmit control signal from client MAC.
gmii_tx_er : in std_logic; -- Transmit control signal from client MAC.
gmii_rxd : out std_logic_vector(7 downto 0); -- Received Data to client MAC.
gmii_rx_dv : out std_logic; -- Received control signal to client MAC.
gmii_rx_er : out std_logic; -- Received control signal to client MAC.
gmii_isolate : out std_logic; -- Tristate control to electrically isolate GMII.
-- Management: Alternative to MDIO Interface
--------------------------------------------
configuration_vector : in std_logic_vector(4 downto 0); -- Alternative to MDIO interface.
an_interrupt : out std_logic; -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector : in std_logic_vector(15 downto 0); -- Alternate interface to program REG4 (AN ADV)
an_restart_config : in std_logic; -- Alternate signal to modify AN restart bit in REG0
-- Speed Control
----------------
speed_is_10_100 : in std_logic; -- Core should operate at either 10Mbps or 100Mbps speeds
speed_is_100 : in std_logic; -- Core should operate at 100Mbps speed
-- General IO's
---------------
status_vector : out std_logic_vector(15 downto 0); -- Core status.
reset : in std_logic; -- Asynchronous reset for entire core.
signal_detect : in std_logic; -- Input from PMD to indicate presence of optical input.
gt0_pll0outclk_out : out std_logic;
gt0_pll0outrefclk_out : out std_logic;
gt0_pll1outclk_out : out std_logic;
gt0_pll1outrefclk_out : out std_logic;
gt0_pll0refclklost_out : out std_logic;
gt0_pll0lock_out : out std_logic);
end component;
-- 8
component UDP_ICMP_Complete_nomac
Port (
-- UDP TX signals
udp_tx_start : in std_logic; -- indicates req to tx UDP
udp_txi : in udp_tx_type; -- UDP tx cxns
udp_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
udp_tx_data_out_ready : out std_logic; -- indicates udp_tx is ready to take data
-- UDP RX signals
udp_rx_start : out std_logic; -- indicates receipt of udp header
udp_rxo : out udp_rx_type;
-- ICMP RX signals
icmp_rx_start : out std_logic;
icmp_rxo : out icmp_rx_type;
-- IP RX signals
ip_rx_hdr : out ipv4_rx_header_type;
-- system signals
rx_clk : in std_logic;
tx_clk : in std_logic;
reset : in std_logic;
fifo_init : in std_logic;
our_ip_address : in std_logic_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
control : in udp_control_type;
-- status signals
arp_pkt_count : out std_logic_vector(7 downto 0); -- count of arp pkts received
ip_pkt_count : out std_logic_vector(7 downto 0); -- number of IP pkts received for us
-- MAC Transmitter
mac_tx_tdata : out std_logic_vector(7 downto 0); -- data byte to tx
mac_tx_tvalid : out std_logic; -- tdata is valid
mac_tx_tready : in std_logic; -- mac is ready to accept data
mac_tx_tfirst : out std_logic; -- indicates first byte of frame
mac_tx_tlast : out std_logic; -- indicates last byte of frame
-- MAC Receiver
mac_rx_tdata : in std_logic_vector(7 downto 0); -- data byte received
mac_rx_tvalid : in std_logic; -- indicates tdata is valid
mac_rx_tready : out std_logic; -- tells mac that we are ready to take data
mac_rx_tlast : in std_logic); -- indicates last byte of the trame
end component;
-- 9
component temac_10_100_1000_fifo_block
port(
gtx_clk : in std_logic;
-- asynchronous reset
glbl_rstn : in std_logic;
rx_axi_rstn : in std_logic;
tx_axi_rstn : in std_logic;
-- Receiver Statistics Interface
-----------------------------------------
rx_reset : out std_logic;
rx_statistics_vector : out std_logic_vector(27 downto 0);
rx_statistics_valid : out std_logic;
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock : in std_logic;
rx_fifo_resetn : in std_logic;
rx_axis_fifo_tdata : out std_logic_vector(7 downto 0);
rx_axis_fifo_tvalid : out std_logic;
rx_axis_fifo_tready : in std_logic;
rx_axis_fifo_tlast : out std_logic;
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset : out std_logic;
tx_ifg_delay : in std_logic_vector(7 downto 0);
tx_statistics_vector : out std_logic_vector(31 downto 0);
tx_statistics_valid : out std_logic;
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock : in std_logic;
tx_fifo_resetn : in std_logic;
tx_axis_fifo_tdata : in std_logic_vector(7 downto 0);
tx_axis_fifo_tvalid : in std_logic;
tx_axis_fifo_tready : out std_logic;
tx_axis_fifo_tlast : in std_logic;
-- MAC Control Interface
--------------------------
pause_req : in std_logic;
pause_val : in std_logic_vector(15 downto 0);
-- GMII Interface
-------------------
gmii_txd : out std_logic_vector(7 downto 0);
gmii_tx_en : out std_logic;
gmii_tx_er : out std_logic;
gmii_rxd : in std_logic_vector(7 downto 0);
gmii_rx_dv : in std_logic;
gmii_rx_er : in std_logic;
clk_enable : in std_logic;
speedis100 : out std_logic;
speedis10100 : out std_logic;
-- Configuration Vector
-------------------------
rx_configuration_vector : in std_logic_vector(79 downto 0);
tx_configuration_vector : in std_logic_vector(79 downto 0));
end component;
-- 10
component temac_10_100_1000_reset_sync
port (
reset_in : in std_logic; -- Active high asynchronous reset
enable : in std_logic;
clk : in std_logic; -- clock to be sync'ed to
reset_out : out std_logic); -- "Synchronised" reset signal
end component;
-- 11
component temac_10_100_1000_config_vector_sm is
port(
gtx_clk : in std_logic;
gtx_resetn : in std_logic;
mac_speed : in std_logic_vector(1 downto 0);
update_speed : in std_logic;
rx_configuration_vector : out std_logic_vector(79 downto 0);
tx_configuration_vector : out std_logic_vector(79 downto 0));
end component;
-- 12
component i2c_top is
port(
clk_in : in std_logic;
phy_rstn_out : out std_logic
);
end component;
-- 13
component udp_data_in_handler
port(
------------------------------------
------- General Interface ----------
clk_125 : in std_logic;
clk_40 : in std_logic;
inhibit_conf : in std_logic;
rst : in std_logic;
rst_fifo_init : in std_logic;
state_o : out std_logic_vector(2 downto 0);
valid_o : out std_logic;
------------------------------------
-------- FPGA Config Interface -----
latency : out std_logic_vector(15 downto 0);
serial_number : out std_logic_vector(31 downto 0);
daq_on : out std_logic;
ext_trigger : out std_logic;
ckbcMode : out std_logic;
fpga_rst : out std_logic;
------------------------------------
-------- UDP Interface -------------
udp_rx : in udp_rx_type;
------------------------------------
---------- AXI4SPI Interface -------
flash_busy : in std_logic;
newIP_rdy : out std_logic;
myIP_set : out std_logic_vector(31 downto 0);
myMAC_set : out std_logic_vector(47 downto 0);
destIP_set : out std_logic_vector(31 downto 0);
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq : out std_logic_vector(7 downto 0);
cktk_max_num : out std_logic_vector(7 downto 0);
cktp_max_num : out std_logic_vector(15 downto 0);
cktp_skew : out std_logic_vector(7 downto 0);
cktp_period : out std_logic_vector(15 downto 0);
cktp_width : out std_logic_vector(7 downto 0);
ckbc_max_num : out std_logic_vector(7 downto 0);
------------------------------------
------ VMM Config Interface --------
vmm_bitmask : out std_logic_vector(7 downto 0);
vmmConf_came : out std_logic;
vmmConf_rdy : out std_logic;
vmmConf_done : out std_logic;
vmm_sck : out std_logic;
vmm_cs : out std_logic;
vmm_cfg_bit : out std_logic;
top_rdy : in std_logic;
------------------------------------
---------- XADC Interface ----------
xadc_busy : in std_logic;
xadc_rdy : out std_logic;
vmm_id_xadc : out std_logic_vector(15 downto 0);
xadc_sample_size : out std_logic_vector(10 downto 0);
xadc_delay : out std_logic_vector(17 downto 0)
);
end component;
-- 14
component udp_reply_handler
port(
------------------------------------
------- General Interface ----------
clk : in std_logic;
enable : in std_logic;
serial_number : in std_logic_vector(31 downto 0);
reply_done : out std_logic;
------------------------------------
---- FIFO Data Select Interface ----
wr_en_conf : out std_logic;
dout_conf : out std_logic_vector(15 downto 0);
packet_len_conf : out std_logic_vector(11 downto 0);
end_conf : out std_logic
);
end component;
-- 15
component select_data
port(
configuring : in std_logic;
data_acq : in std_logic;
xadc : in std_logic;
we_data : in std_logic;
we_conf : in std_logic;
we_xadc : in std_logic;
daq_data_in : in std_logic_vector(15 downto 0);
conf_data_in : in std_logic_vector(15 downto 0);
xadc_data_in : in std_logic_vector(15 downto 0);
data_packet_length : in std_logic_vector(11 downto 0);
xadc_packet_length : in std_logic_vector(11 downto 0);
conf_packet_length : in std_logic_vector(11 downto 0);
end_packet_conf : in std_logic;
end_packet_daq : in std_logic;
end_packet_xadc : in std_logic;
fifo_rst_daq : in std_logic;
fifo_rst_xadc : in std_logic;
rstFIFO_top : in std_logic;
data_out : out std_logic_vector(15 downto 0);
packet_length : out std_logic_vector(11 downto 0);
we : out std_logic;
end_packet : out std_logic;
fifo_rst : out std_logic
);
end component;
-- 16
component ila_top_level
PORT ( clk : in std_logic;
probe0 : in std_logic_vector(63 DOWNTO 0);
probe1 : in std_logic_vector(63 DOWNTO 0);
probe2 : in std_logic_vector(63 DOWNTO 0);
probe3 : in std_logic_vector(63 DOWNTO 0);
probe4 : in std_logic_vector(63 DOWNTO 0);
probe5 : in std_logic_vector(63 DOWNTO 0)
);
end component;
-- 17
component xadcModule
port(
clk125 : in std_logic;
rst : in std_logic;
VP_0 : in std_logic;
VN_0 : in std_logic;
Vaux0_v_n : in std_logic;
Vaux0_v_p : in std_logic;
Vaux1_v_n : in std_logic;
Vaux1_v_p : in std_logic;
Vaux2_v_n : in std_logic;
Vaux2_v_p : in std_logic;
Vaux3_v_n : in std_logic;
Vaux3_v_p : in std_logic;
Vaux8_v_n : in std_logic;
Vaux8_v_p : in std_logic;
Vaux9_v_n : in std_logic;
Vaux9_v_p : in std_logic;
Vaux10_v_n : in std_logic;
Vaux10_v_p : in std_logic;
Vaux11_v_n : in std_logic;
Vaux11_v_p : in std_logic;
data_in_rdy : in std_logic;
vmm_id : in std_logic_vector(15 downto 0);
sample_size : in std_logic_vector(10 downto 0);
delay_in : in std_logic_vector(17 downto 0);
UDPDone : in std_logic;
MuxAddr0 : out std_logic;
MuxAddr1 : out std_logic;
MuxAddr2 : out std_logic;
MuxAddr3_p : out std_logic;
MuxAddr3_n : out std_logic;
end_of_data : out std_logic;
fifo_bus : out std_logic_vector(15 downto 0);
data_fifo_enable : out std_logic;
packet_len : out std_logic_vector(11 downto 0);
xadc_busy : out std_logic
);
end component;
-- 18
component AXI4_SPI
port(
clk_200 : in std_logic;
clk_125 : in std_logic;
clk_50 : in std_logic;
myIP : out std_logic_vector(31 downto 0);
myMAC : out std_logic_vector(47 downto 0);
destIP : out std_logic_vector(31 downto 0);
default_IP : in std_logic_vector(31 downto 0);
default_MAC : in std_logic_vector(47 downto 0);
default_destIP : in std_logic_vector(31 downto 0);
myIP_set : in std_logic_vector(31 downto 0);
myMAC_set : in std_logic_vector(47 downto 0);
destIP_set : in std_logic_vector(31 downto 0);
newip_start : in std_logic;
flash_busy : out std_logic;
io0_i : IN std_logic;
io0_o : OUT std_logic;
io0_t : OUT std_logic;
io1_i : IN std_logic;
io1_o : OUT std_logic;
io1_t : OUT std_logic;
ss_i : IN std_logic_vector(0 DOWNTO 0);
ss_o : OUT std_logic_vector(0 DOWNTO 0);
ss_t : OUT std_logic
);
end component;
-- 19
COMPONENT vio_ip
PORT (
clk : IN std_logic;
probe_out0 : OUT std_logic_VECTOR(31 DOWNTO 0);
probe_out1 : OUT std_logic_VECTOR(47 DOWNTO 0)
);
END COMPONENT;
-- 20
component clk_gen_wrapper
Port(
------------------------------------
------- General Interface ----------
clk_500 : in std_logic;
clk_160 : in std_logic;
clk_125 : in std_logic;
rst : in std_logic;
mmcm_locked : in std_logic;
CKTP_raw : out std_logic;
------------------------------------
----- Configuration Interface ------
cktp_enable : in std_logic;
cktp_primary : in std_logic;
readout_mode : in std_logic;
enable_ro_ckbc : in std_logic;
cktp_pulse_width : in std_logic_vector(4 downto 0);
cktp_max_num : in std_logic_vector(15 downto 0);
cktp_period : in std_logic_vector(15 downto 0);
cktp_skew : in std_logic_vector(4 downto 0);
ckbc_freq : in std_logic_vector(5 downto 0);
ckbc_max_num : in std_logic_vector(7 downto 0);
------------------------------------
---------- VMM Interface -----------
CKTP : out std_logic;
CKBC : out std_logic
);
end component;
-- 21
component ila_overview
Port(
clk : in std_logic;
probe0 : in std_logic_vector(63 downto 0)
);
end component;
-- 22
component artReadout --art_instance
generic( is_mmfe8 : std_logic;
artEnabled : std_logic);
Port(
clk : in std_logic;
clk_art : in std_logic;
trigger : in std_logic;
artData : in std_logic_vector(8 downto 1);
vmmArtData125 : out std_logic_vector(5 downto 0);
vmmArtReady : out std_logic
);
end component;
-- 23
component vmm_oddr_wrapper
Port(
-------------------------------------------------------
ckdt_bufg : in std_logic;
ckdt_enable_vec : in std_logic_vector(8 downto 1);
ckdt_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
ckbc_bufg : in std_logic;
ckbc_enable : in std_logic;
ckbc_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
cktp_bufg : in std_logic;
cktp_toBuf_vec : out std_logic_vector(8 downto 1);
-------------------------------------------------------
ckart_bufg : in std_logic;
ckart_toBuf_vec : out std_logic_vector(9 downto 1)
-------------------------------------------------------
);
end component;
begin
gen_vector_reset: process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
if vector_reset_int = '1' then
vector_pre_resetn <= '0';
vector_resetn <= '0';
else
vector_pre_resetn <= '1';
vector_resetn <= vector_pre_resetn;
end if;
end if;
end process gen_vector_reset;
-----------------------------------------------------------------------------
-- Transceiver PMA reset circuitry
-----------------------------------------------------------------------------
core_wrapper: gig_ethernet_pcs_pma_0
port map (
gtrefclk_p => gtrefclk_p,
gtrefclk_n => gtrefclk_n,
txp => txp,
txn => txn,
rxp => rxp,
rxn => rxn,
gtrefclk_out => open,
gtrefclk_bufg_out => txoutclk,
rxuserclk_out => open,
rxuserclk2_out => open,
resetdone => resetdone,
mmcm_locked_out => mmcm_locked,
userclk_out => userclk,
userclk2_out => userclk2,
independent_clock_bufg => clk_200,
pma_reset_out => pma_reset,
sgmii_clk_r => sgmii_clk_r,
sgmii_clk_f => sgmii_clk_f,
sgmii_clk_en => clk_enable_int,
gmii_txd => gmii_txd_int,
gmii_tx_en => gmii_tx_en_int,
gmii_tx_er => gmii_tx_er_int,
gmii_rxd => gmii_rxd_int,
gmii_rx_dv => gmii_rx_dv_int,
gmii_rx_er => gmii_rx_er_int,
gmii_isolate => gmii_isolate,
configuration_vector => "10000", -- configuration_vector,
status_vector => status_vector_int, -- status_vector_int,
reset => '0',
signal_detect => '1', -- signal_detect
speed_is_10_100 => speed_is_10_100,
speed_is_100 => speed_is_100,
an_interrupt => open, -- Interrupt to processor to signal that Auto-Negotiation has completed
an_adv_config_vector => "1111111000000001",-- Alternate interface to program REG4 (AN ADV)
an_restart_config => an_restart_config_int, -- Alternate signal to modify AN restart bit in REG0
gt0_pll0outclk_out => open,
gt0_pll0outrefclk_out => open,
gt0_pll1outclk_out => open,
gt0_pll1outrefclk_out => open,
gt0_pll0refclklost_out => open,
gt0_pll0lock_out => open);
process(userclk2)
begin
if (local_gtx_reset = '1') then
an_restart_config_int <= '1';
else
an_restart_config_int <= '0';
end if;
end process;
tri_fifo: temac_10_100_1000_fifo_block
port map(
gtx_clk => userclk2, --sgmii_clk_int, --userclk2,
-- asynchronous reset
glbl_rstn => glbl_rstn,
rx_axi_rstn => '1',
tx_axi_rstn => '1',
-- Receiver Statistics Interface
-----------------------------------------
rx_reset => rx_reset,
rx_statistics_vector => open,
rx_statistics_valid => open,
-- Receiver (AXI-S) Interface
------------------------------------------
rx_fifo_clock => userclk2,
rx_fifo_resetn => gtx_resetn,
rx_axis_fifo_tdata => rx_axis_mac_tdata_int,
rx_axis_fifo_tvalid => rx_axis_mac_tvalid_int,
rx_axis_fifo_tready => rx_axis_mac_tready_int,
rx_axis_fifo_tlast => rx_axis_mac_tlast_int,
-- Transmitter Statistics Interface
--------------------------------------------
tx_reset => tx_reset,
tx_ifg_delay => x"00",
tx_statistics_vector => open,
tx_statistics_valid => open,
-- Transmitter (AXI-S) Interface
---------------------------------------------
tx_fifo_clock => userclk2,
tx_fifo_resetn => gtx_resetn,
tx_axis_fifo_tdata => tx_axis_mac_tdata_int,
tx_axis_fifo_tvalid => tx_axis_mac_tvalid_int,
tx_axis_fifo_tready => tx_axis_mac_tready_int,
tx_axis_fifo_tlast => tx_axis_mac_tlast_int,
-- MAC Control Interface
--------------------------
pause_req => '0',
pause_val => x"0000",
-- GMII Interface
-------------------
gmii_txd => gmii_txd_emac,
gmii_tx_en => gmii_tx_en_emac,
gmii_tx_er => gmii_tx_er_emac,
gmii_rxd => gmii_rxd_emac,
gmii_rx_dv => gmii_rx_dv_emac,
gmii_rx_er => gmii_rx_er_emac,
clk_enable => clk_enable_int,
speedis100 => speed_is_100,
speedis10100 => speed_is_10_100,
-- Configuration Vector
-------------------------
rx_configuration_vector => rx_configuration_vector_int, -- x"0605_0403_02da_0000_2022",
tx_configuration_vector => tx_configuration_vector_int); -- x"0605_0403_02da_0000_2022"
-- Control vector reset
axi_lite_reset_gen: temac_10_100_1000_reset_sync
port map (
clk => userclk2,
enable => '1',
reset_in => glbl_rst_i,
reset_out => vector_reset_int);
config_vector: temac_10_100_1000_config_vector_sm
port map(
gtx_clk => userclk2, --sgmii_clk_int, --userclk2,
gtx_resetn => vector_resetn,
mac_speed => status_vector_int(11 downto 10), -- "10",
update_speed => '1',
rx_configuration_vector => rx_configuration_vector_int,
tx_configuration_vector => tx_configuration_vector_int);
-----------------------------------------------------------------------------
-- GMII transmitter data logic
-----------------------------------------------------------------------------
-- Drive input GMII signals through IOB input flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_txd_int <= gmii_txd_emac;
gmii_tx_en_int <= gmii_tx_en_emac;
gmii_tx_er_int <= gmii_tx_er_emac;
end if;
end process;
gtx_reset_gen: temac_10_100_1000_reset_sync
port map (
clk => userclk2,
enable => '1',
reset_in => local_gtx_reset,
reset_out => gtx_clk_reset_int);
gen_gtx_reset: process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
if gtx_clk_reset_int = '1' then
gtx_pre_resetn <= '0';
gtx_resetn <= '0';
else
gtx_pre_resetn <= '1';
gtx_resetn <= gtx_pre_resetn;
end if;
end if;
end process gen_gtx_reset;
-- Drive input GMII signals through IOB output flip-flops (inferred).
process (userclk2)
begin
if userclk2'event and userclk2 = '1' then
gmii_rxd_emac <= gmii_rxd_int;
gmii_rx_dv_emac <= gmii_rx_dv_int;
gmii_rx_er_emac <= gmii_rx_er_int;
end if;
end process;
UDP_ICMP_block: UDP_ICMP_Complete_nomac
Port map(
udp_tx_start => udp_tx_start_int,
udp_txi => udp_txi_int,
udp_tx_result => open,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
udp_rx_start => open,
udp_rxo => udp_rx_int,
icmp_rx_start => icmp_rx_start,
icmp_rxo => icmp_rxo,
ip_rx_hdr => ip_rx_hdr_int,
rx_clk => userclk2,
tx_clk => userclk2,
reset => glbl_rst_i,
fifo_init => glbl_fifo_init,
our_ip_address => myIP,
our_mac_address => myMAC,
control => control,
arp_pkt_count => open,
ip_pkt_count => open,
mac_tx_tdata => tx_axis_mac_tdata_int,
mac_tx_tvalid => tx_axis_mac_tvalid_int,
mac_tx_tready => tx_axis_mac_tready_int,
mac_tx_tfirst => open,
mac_tx_tlast => tx_axis_mac_tlast_int,
mac_rx_tdata => rx_axis_mac_tdata_int,
mac_rx_tvalid => rx_axis_mac_tvalid_int,
mac_rx_tready => rx_axis_mac_tready_int,
mac_rx_tlast => rx_axis_mac_tlast_int);
i2c_module: i2c_top
port map(
clk_in => clk_200,
phy_rstn_out => phy_rstn
);
udp_din_conf_block: udp_data_in_handler
port map(
------------------------------------
------- General Interface ----------
clk_125 => userclk2,
clk_40 => clk_40,
inhibit_conf => inhibit_conf,
rst => glbl_rst_i,
rst_fifo_init => glbl_fifo_init_s1,
state_o => conf_state,
valid_o => open,
------------------------------------
-------- FPGA Config Interface -----
latency => latency_conf,
serial_number => serial_number,
daq_on => daq_on,
ext_trigger => trig_mode_int,
ckbcMode => ckbcMode,
fpga_rst => glbl_rst_i,
------------------------------------
-------- UDP Interface -------------
udp_rx => udp_rx_int,
------------------------------------
---------- AXI4SPI Interface -------
flash_busy => flash_busy,
newIP_rdy => newIP_rdy,
myIP_set => myIP_set,
myMAC_set => myMAC_set,
destIP_set => destIP_set,
------------------------------------
-------- CKTP/CKBC Interface -------
ckbc_freq => ckbc_freq,
cktk_max_num => cktk_max_num,
cktp_max_num => cktp_max_num,
cktp_skew => cktp_skew,
cktp_period => cktp_period,
cktp_width => cktp_pulse_width,
ckbc_max_num => ckbc_max_num,
------------------------------------
------ VMM Config Interface --------
vmm_bitmask => vmm_bitmask_8VMM,
vmmConf_came => vmm_conf,
vmmConf_rdy => vmm_id_rdy,
vmmConf_done => vmmConf_done,
vmm_sck => vmm_sck_all,
vmm_cs => VMM_CS_i,
vmm_cfg_bit => vmm_sdi_all,
top_rdy => conf_wen_i,
------------------------------------
---------- XADC Interface ----------
xadc_busy => xadc_busy,
xadc_rdy => xadc_conf_rdy,
vmm_id_xadc => vmm_id_xadc,
xadc_sample_size => xadc_sample_size,
xadc_delay => xadc_delay
);
udp_reply_instance: udp_reply_handler
port map(
------------------------------------
------- General Interface ----------
clk => userclk2,
enable => reply_enable,
serial_number => serial_number,
reply_done => reply_done,
------------------------------------
---- FIFO Data Select Interface ----
wr_en_conf => we_conf_int,
dout_conf => user_data_out_i,
packet_len_conf => packet_len_conf,
end_conf => end_packet_conf_int
);
mmcm_master: clk_wiz_gen
port map (
-- Clock in ports
clk_in1_p => X_2V5_DIFF_CLK_P,
clk_in1_n => X_2V5_DIFF_CLK_N,
-- Clock out ports
clk_out_160 => clk_160,
clk_out_500 => clk_500,
clk_out_200 => clk_200,
clk_out_50 => clk_50,
clk_out_40 => clk_40,
-- Status and control signals
reset => '0',
gen_locked => master_locked
);
event_timing_reset_instance: event_timing_reset
port map(
hp_clk => '0', --clk_800
clk => userclk2,
clk_10_phase45 => '0', --clk_10_phase45
bc_clk => '0', --clk_10
daqEnable => daq_enable_i,
pfBusy => pfBusy_i,
reset => rst_vmm,
glBCID => glBCID_i,
prec_cnt => open,
state_rst_out => state_rst_etr_i,
rst_o => rst_etr_i,
rst_done_o => rst_done_etr_i,
vmm_ena_vec => open,
vmm_wen_vec => open,
reset_latched => etr_reset_latched
);
readout_vmm: vmm_readout_wrapper
generic map(is_mmfe8 => is_mmfe8, vmmReadoutMode => vmmReadoutMode)
port map(
------------------------------------
--- Continuous Readout Interface ---
clkTkProc => clk_40,
clkDtProc => clk_50,
clk => userclk2,
--
daq_enable => daq_enable_i,
trigger_pulse => pf_trigVmmRo,
cktk_max => cktk_max_num,
--
dt_state_o => dt_state,
dt_cntr_st_o => dt_cntr_st,
------------------------------------
---- Level-0 Readout Interface -----
clk_ckdt => clk_160,
rst_buff => rst_l0_buff,
rst_intf_proc => rst_l0_pf,
--
level_0 => level_0,
wr_accept => accept_wr,
--
vmm_conf => conf_wen_i,
daq_on_inhib => daq_on_inhib, -- synced to flow_fsm's clock
------------------------------------
---- Packet Formation Interface ----
vmmWordReady => vmmWordReady_i,
vmmWord => vmmWord_i,
rd_ena_buff => rd_ena_buff,
vmmEventDone => vmmEventDone_i,
vmmId => pf_vmmIdRo,
linkHealth_bmsk => linkHealth_bmsk,
------------------------------------
---------- VMM3 Interface ----------
vmm_data0_vec => data0_in_vec,
vmm_data1_vec => data1_in_vec,
vmm_ckdt_glbl => CKDT_glbl,
vmm_ckdt_enable => vmm_ckdt_enable,
vmm_cktk_vec => cktk_out_vec
);
trigger_instance: trigger
generic map(vmmReadoutMode => vmmReadoutMode)
port map(
clk => userclk2,
ckbc => CKBC_glbl,
clk_art => clk_160,
rst_trig => glbl_rst_i,
ckbcMode => ckbcMode,
request2ckbc => request2ckbc,
cktp_enable => cktp_enable,
CKTP_raw => CKTP_raw,
pfBusy => pfBusy_i,
cktp_pulse_width=> cktp_pulse_width(4 downto 0),
tren => tren, -- Trigger module enabled
tr_hold => tr_hold, -- Prevents trigger while high
trmode => trig_mode_int, -- Mode 0: internal / Mode 1: external
trext => CH_TRIGGER_i, -- External trigger is to be driven to this port
level_0 => level_0, -- Level-0 accept signal
accept_wr => accept_wr,
reset => tr_reset,
event_counter => open,
tr_out => tr_out_i,
trraw_synced125 => trraw_synced125_i,
latency => latency_conf
);
FIFO2UDP_instance: FIFO2UDP
Port map(
clk_125 => userclk2,
destinationIP => destIP,
daq_data_in => daqFIFO_din_i,
fifo_data_out => open,
udp_txi => udp_txi_int,
udp_tx_start => udp_tx_start_int,
control => control.ip_controls.arp_controls.clear_cache,
UDPDone => UDPDone,
re_out => open,
udp_tx_data_out_ready => udp_tx_data_out_ready_int,
wr_en => daqFIFO_wr_en_i,
end_packet => end_packet_i,
global_reset => glbl_rst_i,
packet_length_in => packet_length_int,
reset_DAQ_FIFO => daqFIFO_reset,
confReply_packet => start_conf_proc_int,
vmmID => pf_vmmIdRo,
trigger_out => trigger_i,
count_o => FIFO2UDP_state,
faifouki => faifouki
);
packet_formation_instance: packet_formation
generic map(is_mmfe8 => is_mmfe8,
vmmReadoutMode => vmmReadoutMode,
artEnabled => artEnabled)
port map(
clk => userclk2,
newCycle => pf_newCycle,
trigVmmRo => pf_trigVmmRo,
vmmId => pf_vmmIdRo,
vmmWord => vmmWord_i,
vmmWordReady => vmmWordReady_i,
vmmEventDone => vmmEventDone_i,
UDPDone => UDPDone,
pfBusy => pfBusy_i,
glBCID => glBCID_i,
packLen => pf_packLen,
dataout => daq_data_out_i,
wrenable => daq_wr_en_i,
end_packet => end_packet_daq_int,
rd_ena_buff => rd_ena_buff,
rst_l0 => rst_l0_pf,
tr_hold => tr_hold,
reset => pf_rst_final,
rst_vmm => rst_vmm,
linkHealth_bmsk => linkHealth_bmsk,
rst_FIFO => pf_rst_FIFO,
latency => latency_conf,
dbg_st_o => pf_dbg_st,
trraw_synced125 => trraw_synced125_i,
vmmArtData125 => vmmArtData,
vmmArtReady => vmmArtReady
);
data_selection: select_data
port map(
configuring => start_conf_proc_int,
xadc => xadc_busy,
data_acq => daq_enable_i,
we_data => daq_wr_en_i,
we_conf => we_conf_int,
we_xadc => xadc_fifo_enable,
daq_data_in => daq_data_out_i,
conf_data_in => user_data_out_i,
xadc_data_in => xadc_fifo_bus,
data_packet_length => pf_packLen,
xadc_packet_length => xadc_packet_len,
conf_packet_length => packet_len_conf,
end_packet_conf => end_packet_conf_int,
end_packet_daq => end_packet_daq_int,
end_packet_xadc => xadc_end_of_data,
fifo_rst_daq => pf_rst_FIFO,
fifo_rst_xadc => '0',
rstFIFO_top => rstFIFO_top,
data_out => daqFIFO_din_i,
packet_length => packet_length_int,
we => daqFIFO_wr_en_i,
end_packet => end_packet_i,
fifo_rst => daqFIFO_reset
);
xadc_instance: xadcModule
port map(
clk125 => userclk2,
rst => glbl_rst_i,
VP_0 => VP_0,
VN_0 => VN_0,
Vaux0_v_n => Vaux0_v_n,
Vaux0_v_p => Vaux0_v_p,
Vaux1_v_n => Vaux1_v_n,
Vaux1_v_p => Vaux1_v_p,
Vaux2_v_n => Vaux2_v_n,
Vaux2_v_p => Vaux2_v_p,
Vaux3_v_n => Vaux3_v_n,
Vaux3_v_p => Vaux3_v_p,
Vaux8_v_n => Vaux8_v_n,
Vaux8_v_p => Vaux8_v_p,
Vaux9_v_n => Vaux9_v_n,
Vaux9_v_p => Vaux9_v_p,
Vaux10_v_n => Vaux10_v_n,
Vaux10_v_p => Vaux10_v_p,
Vaux11_v_n => Vaux11_v_n,
Vaux11_v_p => Vaux11_v_p,
data_in_rdy => xadc_start,
vmm_id => vmm_id_xadc,
sample_size => xadc_sample_size,
delay_in => xadc_delay,
UDPDone => UDPDone,
MuxAddr0 => MuxAddr0_i,
MuxAddr1 => MuxAddr1_i,
MuxAddr2 => MuxAddr2_i,
MuxAddr3_p => MuxAddr3_p_i,
MuxAddr3_n => MuxAddr3_n_i,
end_of_data => xadc_end_of_data,
fifo_bus => xadc_fifo_bus,
data_fifo_enable => xadc_fifo_enable,
packet_len => xadc_packet_len,
xadc_busy => xadc_busy -- synced to 125 Mhz
);
axi4_spi_instance: AXI4_SPI
port map(
clk_200 => clk_200,
clk_125 => userclk2,
clk_50 => clk_50,
myIP => myIP, -- synced to 125 Mhz
myMAC => myMAC, -- synced to 125 Mhz
destIP => destIP, -- synced to 125 Mhz
default_IP => default_IP,
default_MAC => default_MAC,
default_destIP => default_destIP,
myIP_set => myIP_set, -- synced internally to 50 Mhz
myMAC_set => myMAC_set, -- synced internally to 50 Mhz
destIP_set => destIP_set, -- synced internally to 50 Mhz
newip_start => newIP_start, -- synced internally to 50 Mhz
flash_busy => flash_busy, -- synced to 125 Mhz
io0_i => io0_i,
io0_o => io0_o,
io0_t => io0_t,
io1_i => io1_i,
io1_o => io1_o,
io1_t => io1_t,
ss_i => ss_i,
ss_o => ss_o,
ss_t => ss_t
--SPI_CLK =>
);
ckbc_cktp_generator: clk_gen_wrapper
port map(
------------------------------------
------- General Interface ----------
clk_500 => clk_500,
clk_160 => clk_160,
clk_125 => userclk2,
rst => glbl_rst_i,
mmcm_locked => master_locked,
CKTP_raw => CKTP_raw,
------------------------------------
----- Configuration Interface ------
cktp_enable => cktp_enable,
cktp_primary => vmm_cktp_primary, -- from flow_fsm
readout_mode => ckbcMode,
enable_ro_ckbc => request2ckbc,
cktp_pulse_width => cktp_pulse_width(4 downto 0),
cktp_max_num => cktp_max_num,
cktp_period => cktp_period,
cktp_skew => cktp_skew(4 downto 0),
ckbc_freq => ckbc_freq(5 downto 0),
ckbc_max_num => ckbc_max_num,
------------------------------------
---------- VMM Interface -----------
CKTP => CKTP_glbl,
CKBC => CKBC_glbl
);
QSPI_IO0_0: IOBUF
port map (
O => io0_i,
IO => IO0_IO,
I => io0_o,
T => io0_t
);
QSPI_IO1_0: IOBUF
port map (
O => io1_i,
IO => IO1_IO,
I => io1_o,
T => io1_t
);
QSPI_SS_0: IOBUF
port map (
O => ss_i(0),
IO => SS_IO,
I => ss_o(0),
T => ss_t
);
art_instance: artReadout
generic map(is_mmfe8 => is_mmfe8,
artEnabled => artEnabled)
port map (
clk => userclk2,
clk_art => clk_160,
trigger => trraw_synced125_i,
artData => art_in_vec,
vmmArtData125 => vmmArtData,
vmmArtReady => vmmArtReady
);
vmm_oddr_inst: vmm_oddr_wrapper
port map(
-------------------------------------------------------
ckdt_bufg => CKDT_glbl,
ckdt_enable_vec => vmm_ckdt_enable,
ckdt_toBuf_vec => ckdt_out_vec,
-------------------------------------------------------
ckbc_bufg => CKBC_glbl,
ckbc_enable => ckbc_enable,
ckbc_toBuf_vec => vmm_ckbc_vec,
-------------------------------------------------------
cktp_bufg => CKTP_glbl,
cktp_toBuf_vec => vmm_cktp_vec,
-------------------------------------------------------
ckart_bufg => clk_160,
ckart_toBuf_vec => ckart_vec
-------------------------------------------------------
);
----------------------------------------------------CS------------------------------------------------------------
cs_obuf_1: OBUF port map (O => CS_1, I => vmm_cs_vec_obuf(1));
cs_obuf_2: OBUF port map (O => CS_2, I => vmm_cs_vec_obuf(2));
cs_obuf_3: OBUF port map (O => CS_3, I => vmm_cs_vec_obuf(3));
cs_obuf_4: OBUF port map (O => CS_4, I => vmm_cs_vec_obuf(4));
cs_obuf_5: OBUF port map (O => CS_5, I => vmm_cs_vec_obuf(5));
cs_obuf_6: OBUF port map (O => CS_6, I => vmm_cs_vec_obuf(6));
cs_obuf_7: OBUF port map (O => CS_7, I => vmm_cs_vec_obuf(7));
cs_obuf_8: OBUF port map (O => CS_8, I => vmm_cs_vec_obuf(8));
----------------------------------------------------SCK------------------------------------------------------------
sck_obuf_1: OBUF port map (O => SCK_1, I => vmm_sck_vec_obuf(1));
sck_obuf_2: OBUF port map (O => SCK_2, I => vmm_sck_vec_obuf(2));
sck_obuf_3: OBUF port map (O => SCK_3, I => vmm_sck_vec_obuf(3));
sck_obuf_4: OBUF port map (O => SCK_4, I => vmm_sck_vec_obuf(4));
sck_obuf_5: OBUF port map (O => SCK_5, I => vmm_sck_vec_obuf(5));
sck_obuf_6: OBUF port map (O => SCK_6, I => vmm_sck_vec_obuf(6));
sck_obuf_7: OBUF port map (O => SCK_7, I => vmm_sck_vec_obuf(7));
sck_obuf_8: OBUF port map (O => SCK_8, I => vmm_sck_vec_obuf(8));
----------------------------------------------------SDI------------------------------------------------------------
sdi_obuf_1: OBUF port map (O => SDI_1, I => vmm_sdi_vec_obuf(1));
sdi_obuf_2: OBUF port map (O => SDI_2, I => vmm_sdi_vec_obuf(2));
sdi_obuf_3: OBUF port map (O => SDI_3, I => vmm_sdi_vec_obuf(3));
sdi_obuf_4: OBUF port map (O => SDI_4, I => vmm_sdi_vec_obuf(4));
sdi_obuf_5: OBUF port map (O => SDI_5, I => vmm_sdi_vec_obuf(5));
sdi_obuf_6: OBUF port map (O => SDI_6, I => vmm_sdi_vec_obuf(6));
sdi_obuf_7: OBUF port map (O => SDI_7, I => vmm_sdi_vec_obuf(7));
sdi_obuf_8: OBUF port map (O => SDI_8, I => vmm_sdi_vec_obuf(8));
---------------------------------------------------SETT/SETB/CK6B--------------------------------------------------
sett_obuf: OBUFDS port map (O => SETT_P, OB => SETT_N, I => '0');
setb_obuf: OBUFDS port map (O => SETB_P, OB => SETB_N, I => '0');
ck6b_obuf_1: OBUFDS port map (O => CK6B_1_P, OB => CK6B_1_N, I => '0');
ck6b_obuf_2: OBUFDS port map (O => CK6B_2_P, OB => CK6B_2_N, I => '0');
ck6b_obuf_3: OBUFDS port map (O => CK6B_3_P, OB => CK6B_3_N, I => '0');
ck6b_obuf_4: OBUFDS port map (O => CK6B_4_P, OB => CK6B_4_N, I => '0');
ck6b_obuf_5: OBUFDS port map (O => CK6B_5_P, OB => CK6B_5_N, I => '0');
ck6b_obuf_6: OBUFDS port map (O => CK6B_6_P, OB => CK6B_6_N, I => '0');
ck6b_obuf_7: OBUFDS port map (O => CK6B_7_P, OB => CK6B_7_N, I => '0');
ck6b_obuf_8: OBUFDS port map (O => CK6B_8_P, OB => CK6B_8_N, I => '0');
----------------------------------------------------SDO------------------------------------------------------------
sdo_ibuf_1: IBUF port map ( O => vmm_sdo_vec_i(1), I => SDO_1);
sdo_ibuf_2: IBUF port map ( O => vmm_sdo_vec_i(2), I => SDO_2);
sdo_ibuf_3: IBUF port map ( O => vmm_sdo_vec_i(3), I => SDO_3);
sdo_ibuf_4: IBUF port map ( O => vmm_sdo_vec_i(4), I => SDO_4);
sdo_ibuf_5: IBUF port map ( O => vmm_sdo_vec_i(5), I => SDO_5);
sdo_ibuf_6: IBUF port map ( O => vmm_sdo_vec_i(6), I => SDO_6);
sdo_ibuf_7: IBUF port map ( O => vmm_sdo_vec_i(7), I => SDO_7);
sdo_ibuf_8: IBUF port map ( O => vmm_sdo_vec_i(8), I => SDO_8);
----------------------------------------------------ENA-----------------------------------------------------------
ena_diff_1: OBUFDS port map ( O => ENA_1_P, OB => ENA_1_N, I => vmm_ena_vec_obuf(1));
ena_diff_2: OBUFDS port map ( O => ENA_2_P, OB => ENA_2_N, I => vmm_ena_vec_obuf(2));
ena_diff_3: OBUFDS port map ( O => ENA_3_P, OB => ENA_3_N, I => vmm_ena_vec_obuf(3));
ena_diff_4: OBUFDS port map ( O => ENA_4_P, OB => ENA_4_N, I => vmm_ena_vec_obuf(4));
ena_diff_5: OBUFDS port map ( O => ENA_5_P, OB => ENA_5_N, I => vmm_ena_vec_obuf(5));
ena_diff_6: OBUFDS port map ( O => ENA_6_P, OB => ENA_6_N, I => vmm_ena_vec_obuf(6));
ena_diff_7: OBUFDS port map ( O => ENA_7_P, OB => ENA_7_N, I => vmm_ena_vec_obuf(7));
ena_diff_8: OBUFDS port map ( O => ENA_8_P, OB => ENA_8_N, I => vmm_ena_vec_obuf(8));
----------------------------------------------------CKBC------------------------------------------------------------
ckbc_diff_1: OBUFDS port map ( O => CKBC_1_P, OB => CKBC_1_N, I => vmm_ckbc_vec(1));
ckbc_diff_2: OBUFDS port map ( O => CKBC_2_P, OB => CKBC_2_N, I => vmm_ckbc_vec(2));
ckbc_diff_3: OBUFDS port map ( O => CKBC_3_P, OB => CKBC_3_N, I => vmm_ckbc_vec(3));
ckbc_diff_4: OBUFDS port map ( O => CKBC_4_P, OB => CKBC_4_N, I => vmm_ckbc_vec(4));
ckbc_diff_5: OBUFDS port map ( O => CKBC_5_P, OB => CKBC_5_N, I => vmm_ckbc_vec(5));
ckbc_diff_6: OBUFDS port map ( O => CKBC_6_P, OB => CKBC_6_N, I => vmm_ckbc_vec(6));
ckbc_diff_7: OBUFDS port map ( O => CKBC_7_P, OB => CKBC_7_N, I => vmm_ckbc_vec(7));
ckbc_diff_8: OBUFDS port map ( O => CKBC_8_P, OB => CKBC_8_N, I => vmm_ckbc_vec(8));
----------------------------------------------------CKTP------------------------------------------------------------
cktp_diff_1: OBUFDS port map ( O => CKTP_1_P, OB => CKTP_1_N, I => vmm_cktp_vec(1));
cktp_diff_2: OBUFDS port map ( O => CKTP_2_P, OB => CKTP_2_N, I => vmm_cktp_vec(2));
cktp_diff_3: OBUFDS port map ( O => CKTP_3_P, OB => CKTP_3_N, I => vmm_cktp_vec(3));
cktp_diff_4: OBUFDS port map ( O => CKTP_4_P, OB => CKTP_4_N, I => vmm_cktp_vec(4));
cktp_diff_5: OBUFDS port map ( O => CKTP_5_P, OB => CKTP_5_N, I => vmm_cktp_vec(5));
cktp_diff_6: OBUFDS port map ( O => CKTP_6_P, OB => CKTP_6_N, I => vmm_cktp_vec(6));
cktp_diff_7: OBUFDS port map ( O => CKTP_7_P, OB => CKTP_7_N, I => vmm_cktp_vec(7));
cktp_diff_8: OBUFDS port map ( O => CKTP_8_P, OB => CKTP_8_N, I => vmm_cktp_vec(8));
----------------------------------------------------CKTK------------------------------------------------------------
cktk_diff_1: OBUFDS port map ( O => CKTK_1_P, OB => CKTK_1_N, I => cktk_out_vec(1));
cktk_diff_2: OBUFDS port map ( O => CKTK_2_P, OB => CKTK_2_N, I => cktk_out_vec(2));
cktk_diff_3: OBUFDS port map ( O => CKTK_3_P, OB => CKTK_3_N, I => cktk_out_vec(3));
cktk_diff_4: OBUFDS port map ( O => CKTK_4_P, OB => CKTK_4_N, I => cktk_out_vec(4));
cktk_diff_5: OBUFDS port map ( O => CKTK_5_P, OB => CKTK_5_N, I => cktk_out_vec(5));
cktk_diff_6: OBUFDS port map ( O => CKTK_6_P, OB => CKTK_6_N, I => cktk_out_vec(6));
cktk_diff_7: OBUFDS port map ( O => CKTK_7_P, OB => CKTK_7_N, I => cktk_out_vec(7));
cktk_diff_8: OBUFDS port map ( O => CKTK_8_P, OB => CKTK_8_N, I => cktk_out_vec(8));
----------------------------------------------------CKDT-------------------------------------------------------------
ckdt_diff_1: OBUFDS port map ( O => ckdt_1_P, OB => ckdt_1_N, I => ckdt_out_vec(1));
ckdt_diff_2: OBUFDS port map ( O => ckdt_2_P, OB => ckdt_2_N, I => ckdt_out_vec(2));
ckdt_diff_3: OBUFDS port map ( O => ckdt_3_P, OB => ckdt_3_N, I => ckdt_out_vec(3));
ckdt_diff_4: OBUFDS port map ( O => ckdt_4_P, OB => ckdt_4_N, I => ckdt_out_vec(4));
ckdt_diff_5: OBUFDS port map ( O => ckdt_5_P, OB => ckdt_5_N, I => ckdt_out_vec(5));
ckdt_diff_6: OBUFDS port map ( O => ckdt_6_P, OB => ckdt_6_N, I => ckdt_out_vec(6));
ckdt_diff_7: OBUFDS port map ( O => ckdt_7_P, OB => ckdt_7_N, I => ckdt_out_vec(7));
ckdt_diff_8: OBUFDS port map ( O => ckdt_8_P, OB => ckdt_8_N, I => ckdt_out_vec(8));
----------------------------------------------------DATA 0-------------------------------------------------------------
data0_diff_1: IBUFDS port map ( O => data0_in_vec(1), I => DATA0_1_P, IB => DATA0_1_N);
data0_diff_2: IBUFDS port map ( O => data0_in_vec(2), I => DATA0_2_P, IB => DATA0_2_N);
data0_diff_3: IBUFDS port map ( O => data0_in_vec(3), I => DATA0_3_P, IB => DATA0_3_N);
data0_diff_4: IBUFDS port map ( O => data0_in_vec(4), I => DATA0_4_P, IB => DATA0_4_N);
data0_diff_5: IBUFDS port map ( O => data0_in_vec(5), I => DATA0_5_P, IB => DATA0_5_N);
data0_diff_6: IBUFDS port map ( O => data0_in_vec(6), I => DATA0_6_P, IB => DATA0_6_N);
data0_diff_7: IBUFDS port map ( O => data0_in_vec(7), I => DATA0_7_P, IB => DATA0_7_N);
data0_diff_8: IBUFDS port map ( O => data0_in_vec(8), I => DATA0_8_P, IB => DATA0_8_N);
----------------------------------------------------DATA 1-------------------------------------------------------------
data1_diff_1: IBUFDS port map ( O => data1_in_vec(1), I => DATA1_1_P, IB => DATA1_1_N);
data1_diff_2: IBUFDS port map ( O => data1_in_vec(2), I => DATA1_2_P, IB => DATA1_2_N);
data1_diff_3: IBUFDS port map ( O => data1_in_vec(3), I => DATA1_3_P, IB => DATA1_3_N);
data1_diff_4: IBUFDS port map ( O => data1_in_vec(4), I => DATA1_4_P, IB => DATA1_4_N);
data1_diff_5: IBUFDS port map ( O => data1_in_vec(5), I => DATA1_5_P, IB => DATA1_5_N);
data1_diff_6: IBUFDS port map ( O => data1_in_vec(6), I => DATA1_6_P, IB => DATA1_6_N);
data1_diff_7: IBUFDS port map ( O => data1_in_vec(7), I => DATA1_7_P, IB => DATA1_7_N);
data1_diff_8: IBUFDS port map ( O => data1_in_vec(8), I => DATA1_8_P, IB => DATA1_8_N);
----------------------------------------------------TKI/TKO-------------------------------------------------------------
TKI_diff_1: OBUFDS port map ( O => TKI_P, OB => TKI_N, I => vmm_tki);
TKO_diff_1: IBUFDS port map ( O => tko_i, I => TKO_P, IB => TKO_N);
---------------------------------------------------CKART----------------------------------------------------------------
ckart_diff_1: OBUFDS port map ( O => CKART_1_P, OB => CKART_1_N, I => ckart_vec(1));
ckart_diff_2: OBUFDS port map ( O => CKART_2_P, OB => CKART_2_N, I => ckart_vec(2));
ckart_diff_3: OBUFDS port map ( O => CKART_3_P, OB => CKART_3_N, I => ckart_vec(3));
ckart_diff_4: OBUFDS port map ( O => CKART_4_P, OB => CKART_4_N, I => ckart_vec(4));
ckart_diff_5: OBUFDS port map ( O => CKART_5_P, OB => CKART_5_N, I => ckart_vec(5));
ckart_diff_6: OBUFDS port map ( O => CKART_6_P, OB => CKART_6_N, I => ckart_vec(6));
ckart_diff_7: OBUFDS port map ( O => CKART_7_P, OB => CKART_7_N, I => ckart_vec(7));
ckart_diff_8: OBUFDS port map ( O => CKART_8_P, OB => CKART_8_N, I => ckart_vec(8));
----------------------------------------------------ART----------------------------------------------------------------
art_diff_1: IBUFDS port map ( O => art_in_vec(1), I => ART_1_P, IB => ART_1_N);
--art_diff_2: IBUFDS port map ( O => art_in_vec(2), I => ART_2_P, IB => ART_2_N);
--art_diff_3: IBUFDS port map ( O => art_in_vec(3), I => ART_3_P, IB => ART_3_N);
--art_diff_4: IBUFDS port map ( O => art_in_vec(4), I => ART_4_P, IB => ART_4_N);
--art_diff_5: IBUFDS port map ( O => art_in_vec(5), I => ART_5_P, IB => ART_5_N);
--art_diff_6: IBUFDS port map ( O => art_in_vec(6), I => ART_6_P, IB => ART_6_N);
--art_diff_7: IBUFDS port map ( O => art_in_vec(7), I => ART_7_P, IB => ART_7_N);
--art_diff_8: IBUFDS port map ( O => art_in_vec(8), I => ART_8_P, IB => ART_8_N);
ckart_addc_buf: OBUFDS port map ( O => CKART_ADDC_P, OB => CKART_ADDC_N, I => ckart_vec(9));
----------------------------------------------------XADC----------------------------------------------------------------
xadc_mux0_obuf: OBUF port map (O => MuxAddr0, I => MuxAddr0_i);
xadc_mux1_obuf: OBUF port map (O => MuxAddr1, I => MuxAddr1_i);
xadc_mux2_obuf: OBUF port map (O => MuxAddr2, I => MuxAddr2_i);
xadc_mux3_obufds: OBUFDS port map (O => MuxAddr3_p, OB => MuxAddr3_n, I => MuxAddr3_p_i);
art_out_diff_1: OBUFDS port map (O => ART_OUT_P, OB => ART_OUT_N, I => art2);
rstn_obuf: OBUF port map (O => phy_rstn_out, I => phy_rstn);
-------------------------------------------------------------------
-- Processes --
-------------------------------------------------------------------
-- 1. synced_to_flowFSM
-- 2. sel_cs
-- 3. flow_fsm
-------------------------------------------------------------------
sync_fifo_init: process(userclk2)
begin
if(rising_edge(userclk2))then
glbl_fifo_init_s0 <= glbl_fifo_init;
glbl_fifo_init_s1 <= glbl_fifo_init_s0;
end if;
end process;
art_process: process(userclk2, art2)
begin
if rising_edge(userclk2) then
if art_cnt2 < 125 and art2 = '1' then
art_cnt2 <= art_cnt2 + 1;
elsif art_cnt2 = 125 then
reset_FF <= '1';
art_cnt2 <= art_cnt2 + 1;
else
art_cnt2 <= 0;
reset_FF <= '0';
end if;
end if;
end process;
FDCE_inst: FDCE
generic map (INIT => '0') -- Initial value of register ('0' or '1')
port map (
Q => art2, -- Data output
C => art_in_vec(1), -- Clock input
CE => '1', -- Clock enable input
CLR => reset_FF, -- Asynchronous clear input
D => '1' -- Data input
);
sel_cs_proc: process(sel_cs, vmm_cs_i)
begin
case sel_cs is
when "00" => vmm_cs_all <= '0';
when "01" => vmm_cs_all <= vmm_cs_i;
when "10" => vmm_cs_all <= vmm_cs_i;
when "11" => vmm_cs_all <= '1';
when others => vmm_cs_all <= '0';
end case;
end process;
flow_fsm: process(userclk2)
begin
if rising_edge(userclk2) then
if glbl_rst_i = '1' then
state <= IDLE;
elsif is_state = "0000" then
state <= IDLE;
else
case state is
when IDLE =>
is_state <= "1111";
conf_wen_i <= '0';
conf_ena_i <= '0';
start_conf_proc_int <= '0';
reply_enable <= '0';
cnt_vmm <= 1;
daq_enable_i <= '0';
rst_l0_buff_flow <= '1';
pf_rst_flow <= '0';
rstFIFO_flow <= '0';
tren <= '0';
vmm_ena_all <= '0';
vmm_tki <= '0';
ckbc_enable <= '0';
vmm_cktp_primary <= '0';
daq_vmm_ena_wen_enable <= x"00";
daq_cktk_out_enable <= x"00";
sel_cs <= "11"; -- drive CS high
if(vmm_conf = '1')then
state <= WAIT_FOR_CONF;
elsif(newIP_rdy = '1')then -- start new IP setup
if(wait_cnt = "00000111")then -- wait for safe assertion of multi-bit signal
wait_cnt <= (others => '0');
newIP_start <= '1';
state <= FLASH_init;
else
wait_cnt <= wait_cnt + 1;
newIP_start <= '0';
state <= IDLE;
end if;
elsif(xadc_conf_rdy = '1')then -- start XADC
if(wait_cnt = "00000111")then -- wait for safe assertion of multi-bit signal
wait_cnt <= (others => '0');
xadc_start <= '1';
state <= XADC_init;
else
wait_cnt <= wait_cnt + 1;
xadc_start <= '0';
state <= IDLE;
end if;
elsif(daq_on = '1' and daq_on_inhib = '0')then
state <= DAQ_INIT;
else
state <= IDLE;
wait_cnt <= (others => '0');
end if;
when WAIT_FOR_CONF =>
vmm_ena_all <= '0';
if(vmm_id_rdy = '1')then
if(wait_cnt = "00000111")then -- wait for safe assertion of multi-bit signal
wait_cnt <= (others => '0');
state <= CONFIGURE;
else
wait_cnt <= wait_cnt + 1;
state <= WAIT_FOR_CONF;
end if;
else
wait_cnt <= (others => '0');
state <= WAIT_FOR_CONF;
end if;
when CONFIGURE =>
is_state <= "0001";
sel_cs <= "01"; -- select CS from config
if(vmmConf_done = '1')then
state <= CONF_DONE;
else
state <= CONFIGURE;
end if;
conf_wen_i <= '1';
start_conf_proc_int <= '1';
when CONF_DONE =>
-- sel_cs <= "10"; -- select CS from config
vmm_ena_all <= '1';
is_state <= "0010";
if wait_cnt = "00101000" then
cnt_vmm <= cnt_vmm - 1;
if cnt_vmm = 1 then --VMM conf done
state <= SEND_CONF_REPLY;
else
state <= CONFIGURE_DELAY;
end if;
wait_cnt <= (others => '0');
else
wait_cnt <= wait_cnt + 1;
end if;
conf_wen_i <= '0';
when CONFIGURE_DELAY => -- Waits 100 ns to move to next configuration
is_state <= "1011";
if (wait_cnt >= "00010011") then
wait_cnt <= (others => '0');
vmm_ena_all <= '0';
sel_cs <= "00"; -- drive CS to gnd
state <= CONFIGURE;
else
wait_cnt <= wait_cnt + 1;
end if;
when SEND_CONF_REPLY =>
reply_enable <= '1';
sel_cs <= "00"; -- drive CS to gnd
vmm_ena_all <= '0';
if(reply_done = '1' and UDPDone = '1')then
state <= IDLE;
else
state <= SEND_CONF_REPLY;
end if;
when DAQ_INIT =>
is_state <= "0011";
--for I in 1 to 100 loop
vmm_cktp_primary <= '1';
--end loop;
sel_cs <= "11"; -- drive CS high
vmm_ena_all <= '1';
rst_l0_buff_flow <= '0';
tren <= '0';
daq_vmm_ena_wen_enable <= x"ff";
daq_cktk_out_enable <= x"ff";
daq_enable_i <= '1';
rstFIFO_flow <= '1';
pf_rst_flow <= '1';
if(daq_on = '0')then -- Reset came
daq_vmm_ena_wen_enable <= x"00";
daq_cktk_out_enable <= x"00";
daq_enable_i <= '0';
pf_rst_flow <= '0';
state <= IDLE;
elsif(wait_cnt < "01100100")then
wait_cnt <= wait_cnt + 1;
state <= DAQ_INIT;
elsif(wait_cnt = "01100100")then
wait_cnt <= (others => '0');
state <= TRIG;
end if;
when TRIG =>
is_state <= "0100";
if(vmmReadoutMode = '0')then
vmm_tki <= '1';
else
vmm_tki <= '0';
end if;
vmm_cktp_primary <= '0';
rstFIFO_flow <= '0';
pf_rst_flow <= '0';
tren <= '1';
state <= DAQ;
when DAQ =>
is_state <= "0101";
ckbc_enable <= '1';
if(daq_on = '0')then -- Reset came
daq_enable_i <= '0';
state <= DAQ_INIT;
end if;
when XADC_init =>
is_state <= "0110";
if(xadc_busy = '1')then -- XADC got the message, wait for busy to go low
xadc_start <= '0';
state <= XADC_wait;
else -- XADC didn't get the message, wait and keep high
xadc_start <= '1';
state <= XADC_init;
end if;
when XADC_wait => -- wait for XADC to finish and go to IDLE
if(xadc_busy = '0')then
state <= IDLE;
else
state <= XADC_wait;
end if;
when FLASH_init =>
if(flash_busy = '1')then -- AXI4SPI got the message, wait for busy to go low
newIP_start <= '0';
state <= FLASH_wait;
else -- AXI4SPI didn't get the message, wait and keep high
newIP_start <= '1';
state <= FLASH_init;
end if;
when FLASH_wait => -- wait for AXI4SPI to finish and go to IDLE
if(flash_busy = '0')then
state <= IDLE;
else
state <= FLASH_wait;
end if;
when others =>
state <= IDLE;
is_state <= "0110";
end case;
end if;
end if;
end process;
mmcm_reset <= glbl_rst_i; -- reset;
glbl_rstn <= not glbl_rst_i;
phy_int <= '1';
local_gtx_reset <= glbl_rst_i or rx_reset or tx_reset;
cktp_enable <= '1' when ((state = DAQ and trig_mode_int = '0') or (state = XADC_wait and trig_mode_int = '0')) else '0';
inhibit_conf <= '0' when (state = IDLE) else '1';
vmm_bitmask_1VMM <= "11111111";
vmm_bitmask <= vmm_bitmask_8VMM when (is_mmfe8 = '1') else vmm_bitmask_1VMM;
pf_newCycle <= tr_out_i;
CH_TRIGGER_i <= not CH_TRIGGER;
TRIGGER_OUT_P <= art2;
TRIGGER_OUT_N <= not art2;
MO <= MO_i;
rst_l0_buff <= rst_l0_buff_flow or rst_l0_pf or glbl_rst_i;
pf_rst_final <= pf_rst_flow or glbl_rst_i;
glbl_fifo_init <= not phy_rstn;
rstFIFO_top <= rstFIFO_flow or glbl_fifo_init;
-- configuration assertion
vmm_cs_vec_obuf(1) <= vmm_cs_all;
vmm_cs_vec_obuf(2) <= vmm_cs_all;
vmm_cs_vec_obuf(3) <= vmm_cs_all;
vmm_cs_vec_obuf(4) <= vmm_cs_all;
vmm_cs_vec_obuf(5) <= vmm_cs_all;
vmm_cs_vec_obuf(6) <= vmm_cs_all;
vmm_cs_vec_obuf(7) <= vmm_cs_all;
vmm_cs_vec_obuf(8) <= vmm_cs_all;
vmm_sck_vec_obuf(1) <= vmm_sck_all and vmm_bitmask(0);
vmm_sck_vec_obuf(2) <= vmm_sck_all and vmm_bitmask(1);
vmm_sck_vec_obuf(3) <= vmm_sck_all and vmm_bitmask(2);
vmm_sck_vec_obuf(4) <= vmm_sck_all and vmm_bitmask(3);
vmm_sck_vec_obuf(5) <= vmm_sck_all and vmm_bitmask(4);
vmm_sck_vec_obuf(6) <= vmm_sck_all and vmm_bitmask(5);
vmm_sck_vec_obuf(7) <= vmm_sck_all and vmm_bitmask(6);
vmm_sck_vec_obuf(8) <= vmm_sck_all and vmm_bitmask(7);
vmm_sdi_vec_obuf(1) <= vmm_sdi_all and vmm_bitmask(0);
vmm_sdi_vec_obuf(2) <= vmm_sdi_all and vmm_bitmask(1);
vmm_sdi_vec_obuf(3) <= vmm_sdi_all and vmm_bitmask(2);
vmm_sdi_vec_obuf(4) <= vmm_sdi_all and vmm_bitmask(3);
vmm_sdi_vec_obuf(5) <= vmm_sdi_all and vmm_bitmask(4);
vmm_sdi_vec_obuf(6) <= vmm_sdi_all and vmm_bitmask(5);
vmm_sdi_vec_obuf(7) <= vmm_sdi_all and vmm_bitmask(6);
vmm_sdi_vec_obuf(8) <= vmm_sdi_all and vmm_bitmask(7);
vmm_ena_vec_obuf(1) <= vmm_ena_all;
vmm_ena_vec_obuf(2) <= vmm_ena_all;
vmm_ena_vec_obuf(3) <= vmm_ena_all;
vmm_ena_vec_obuf(4) <= vmm_ena_all;
vmm_ena_vec_obuf(5) <= vmm_ena_all;
vmm_ena_vec_obuf(6) <= vmm_ena_all;
vmm_ena_vec_obuf(7) <= vmm_ena_all;
vmm_ena_vec_obuf(8) <= vmm_ena_all;
--ila_top: ila_top_level
-- port map (
-- clk => userclk2,
-- probe0 => vmmSignalsProbe,
-- probe1 => triggerETRProbe,
-- probe2 => configurationProbe,
-- probe3 => readoutProbe,
-- probe4 => dataOutProbe,
-- probe5 => flowProbe
-- );
--ila_top: ila_overview
-- port map (
-- clk => userclk2,
-- probe0 => overviewProbe
-- );
--VIO_DEFAULT_IP: vio_ip
-- PORT MAP (
-- clk => clk_50,
-- probe_out0 => default_IP,
-- probe_out1 => default_MAC
-- );
-- overviewProbe(3 downto 0) <= is_state;
-- overviewProbe(8 downto 4) <= pf_dbg_st;
-- overviewProbe(9) <= vmmWordReady_i;
-- overviewProbe(10) <= vmmEventDone_i;
-- overviewProbe(11) <= daq_enable_i;
-- overviewProbe(12) <= pf_trigVmmRo;
-- overviewProbe(14 downto 13) <= (others => '0');
-- overviewProbe(15) <= rd_ena_buff;
-- overviewProbe(19 downto 16) <= dt_state;
-- overviewProbe(23 downto 20) <= FIFO2UDP_state;
-- overviewProbe(24) <= CKTP_glbl;
-- overviewProbe(25) <= UDPDone;
-- overviewProbe(26) <= CKBC_glbl;
-- overviewProbe(27) <= tr_out_i;
-- overviewProbe(29 downto 28) <= (others => '0');
-- overviewProbe(30) <= level_0;
-- overviewProbe(31) <= rst_l0_pf;
-- overviewProbe(47 downto 32) <= vmmWord_i;
-- overviewProbe(51 downto 48) <= dt_cntr_st;
-- overviewProbe(59 downto 52) <= linkHealth_bmsk;
-- overviewProbe(63 downto 60) <= (others => '0');
vmmSignalsProbe(7 downto 0) <= (others => '0');
vmmSignalsProbe(15 downto 8) <= cktk_out_vec;
vmmSignalsProbe(23 downto 16) <= ckdt_out_vec;
vmmSignalsProbe(31 downto 24) <= data0_in_vec;
vmmSignalsProbe(32) <= '0';
vmmSignalsProbe(33) <= ckdt_out_vec(1);
vmmSignalsProbe(34) <= data0_in_vec(1);
vmmSignalsProbe(35) <= data1_in_vec(1);
vmmSignalsProbe(36) <= vmm_cs_all;
vmmSignalsProbe(37) <= '0';
vmmSignalsProbe(38) <= vmm_ena_all;
vmmSignalsProbe(39) <= '0';
vmmSignalsProbe(40) <= tko_i;
vmmSignalsProbe(41) <= vmm_ena_all;
vmmSignalsProbe(42) <= art2;
vmmSignalsProbe(43) <= '0';
vmmSignalsProbe(44) <= art_in_vec(1);
vmmSignalsProbe(63 downto 45) <= (others => '0');
triggerETRProbe(0) <= '0';
triggerETRProbe(1) <= tren;
triggerETRProbe(2) <= tr_hold;
triggerETRProbe(3) <= ext_trigger_in;
triggerETRProbe(4) <= trig_mode_int;
triggerETRProbe(7 downto 5) <= state_rst_etr_i;
triggerETRProbe(15 downto 8) <= (others => '0');
triggerETRProbe(23 downto 16) <= (others => '0');
triggerETRProbe(24) <= rst_etr_i;
triggerETRProbe(25) <= etr_reset_latched;
triggerETRProbe(26) <= trigger_i;
triggerETRProbe(38 downto 27) <= glBCID_i;
triggerETRProbe(39) <= CH_TRIGGER_i;
triggerETRProbe(40) <= reset_FF;
triggerETRProbe(63 downto 41) <= (others => '0');
configurationProbe(0) <= start_conf_proc_int;
configurationProbe(1) <= conf_wen_i;
configurationProbe(2) <= conf_di_i;
configurationProbe(18 downto 3) <= (others => '0');
configurationProbe(50 downto 19) <= myIP;
configurationProbe(63 downto 51) <= (others => '0');
readoutProbe(0) <= pf_newCycle;
readoutProbe(1) <= pf_rst_FIFO;
readoutProbe(4 downto 2) <= pf_vmmIdRo;
readoutProbe(5) <= pfBusy_i;
readoutProbe(6) <= rst_vmm;
readoutProbe(7) <= daqFIFO_wr_en_i;
readoutProbe(8) <= daq_wr_en_i;
readoutProbe(24 downto 9) <= vmmWord_i;
readoutProbe(40 downto 25) <= daqFIFO_din_i;
readoutProbe(63 downto 41) <= (others => '0');
dataOutProbe(15 downto 0) <= daq_data_out_i;
dataOutProbe(63 downto 16) <= (others => '0');
flowProbe(3 downto 0) <= is_state;
flowProbe(7 downto 4) <= (others => '0');
flowProbe(11 downto 8) <= (others => '0');
flowProbe(12) <= daq_enable_i;
flowProbe(13) <= xadc_busy;
flowProbe(21 downto 14) <= daq_vmm_ena_wen_enable;
flowProbe(22) <= daqFIFO_reset;
flowProbe(23) <= rstFIFO_top;
flowProbe(24) <= ckbc_enable;
flowProbe(63 downto 25) <= (others => '0');
end Behavioral;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2004, Gideon's Logic Architectures
--
-------------------------------------------------------------------------------
-- Title : Small Synchronous Fifo Using SRL16
-------------------------------------------------------------------------------
-- File : srl_fifo.vhd
-- Author : Gideon Zweijtzer <[email protected]>
-------------------------------------------------------------------------------
-- Altera wrapper to make the "SRL" fifo available to Altera tools.. Obviously
-- it does not use any SRL, but just BRAM!
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
entity srl_fifo is
generic (Width : integer := 32;
Depth : integer := 15; -- 15 is the maximum
Threshold : integer := 13);
port (
clock : in std_logic;
reset : in std_logic;
GetElement : in std_logic;
PutElement : in std_logic;
FlushFifo : in std_logic;
DataIn : in std_logic_vector(Width-1 downto 0);
DataOut : out std_logic_vector(Width-1 downto 0);
SpaceInFifo : out std_logic;
AlmostFull : out std_logic;
DataInFifo : out std_logic);
end srl_fifo;
architecture Altera of srl_fifo is
COMPONENT scfifo
GENERIC (
add_ram_output_register : STRING;
almost_full_value : NATURAL;
intended_device_family : STRING;
lpm_numwords : NATURAL;
lpm_showahead : STRING;
lpm_type : STRING;
lpm_width : NATURAL;
lpm_widthu : NATURAL;
overflow_checking : STRING;
underflow_checking : STRING;
use_eab : STRING
);
PORT (
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (Width-1 DOWNTO 0);
rdreq : IN STD_LOGIC ;
sclr : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
almost_full : OUT STD_LOGIC ;
empty : OUT STD_LOGIC ;
full : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (Width-1 DOWNTO 0);
usedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);
END COMPONENT;
signal full : std_logic;
signal empty : std_logic;
signal sclr : std_logic;
BEGIN
scfifo_component : scfifo
GENERIC MAP (
add_ram_output_register => "ON",
almost_full_value => Threshold,
intended_device_family => "Cyclone IV E",
lpm_numwords => Depth,
lpm_showahead => "ON",
lpm_type => "scfifo",
lpm_width => Width,
lpm_widthu => 4,
overflow_checking => "ON",
underflow_checking => "ON",
use_eab => "ON"
)
PORT MAP (
clock => clock,
data => DataIn,
rdreq => GetElement,
sclr => sclr,
wrreq => PutElement,
almost_full => AlmostFull,
empty => empty,
full => full,
q => DataOut,
usedw => open );
SpaceInFifo <= not full;
DataInFifo <= not empty;
sclr <= reset or FlushFifo;
end Altera;
|
--
-- This is the top level VHDL file.
--
-- It iobufs for bidirational signals (towards an optional
-- external fast SRAM.
--
-- Pins fit the AVNET Virtex-E Evaluation board
--
-- For other boards, change pin assignments in this file.
--
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
use work.cpu_pack.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity board_cpu is
PORT ( CLK40 : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
CLK_OUT : out STD_LOGIC;
LED : out STD_LOGIC_VECTOR (7 downto 0);
ENABLE_N : out STD_LOGIC;
DEACTIVATE_N : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR (7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(14 downto 0);
XM_CE_N : out STD_LOGIC;
XM_OE_N : out STD_LOGIC;
XM_WE_N : inout STD_LOGIC;
XM_DIO : inout STD_LOGIC_VECTOR(7 downto 0)
);
end board_cpu;
architecture behavioral of board_cpu is
COMPONENT cpu
PORT( CLK_I : in STD_LOGIC;
SWITCH : in STD_LOGIC_VECTOR (9 downto 0);
SER_IN : in STD_LOGIC;
SER_OUT : out STD_LOGIC;
TEMP_SPO : in STD_LOGIC;
TEMP_SPI : out STD_LOGIC;
TEMP_CE : out STD_LOGIC;
TEMP_SCLK : out STD_LOGIC;
SEG1 : out STD_LOGIC_VECTOR (7 downto 0);
SEG2 : out STD_LOGIC_VECTOR( 7 downto 0);
LED : out STD_LOGIC_VECTOR( 7 downto 0);
XM_ADR : out STD_LOGIC_VECTOR(15 downto 0);
XM_RDAT : in STD_LOGIC_VECTOR( 7 downto 0);
XM_WDAT : out STD_LOGIC_VECTOR( 7 downto 0);
XM_WE : out STD_LOGIC;
XM_CE : out STD_LOGIC
);
END COMPONENT;
signal XM_WDAT : std_logic_vector( 7 downto 0);
signal XM_RDAT : std_logic_vector( 7 downto 0);
signal MEM_T : std_logic;
signal XM_WE : std_logic;
signal WE_N : std_logic;
signal DEL_WE_N : std_logic;
signal XM_CE : std_logic;
signal LCLK : std_logic;
begin
cp: cpu
PORT MAP( CLK_I => CLK40,
SWITCH => SWITCH,
SER_IN => SER_IN,
SER_OUT => SER_OUT,
TEMP_SPO => TEMP_SPO,
TEMP_SPI => TEMP_SPI,
XM_ADR(14 downto 0) => XM_ADR,
XM_ADR(15) => open,
XM_RDAT => XM_RDAT,
XM_WDAT => XM_WDAT,
XM_WE => XM_WE,
XM_CE => XM_CE,
TEMP_CE => TEMP_CE,
TEMP_SCLK => TEMP_SCLK,
SEG1 => SEG1,
SEG2 => SEG2,
LED => LED
);
ENABLE_N <= '0';
DEACTIVATE_N <= '1';
CLK_OUT <= LCLK;
MEM_T <= DEL_WE_N; -- active low
WE_N <= not XM_WE;
XM_OE_N <= XM_WE;
XM_CE_N <= not XM_CE;
p147: iobuf PORT MAP(I => XM_WDAT(7), O => XM_RDAT(7), T => MEM_T, IO => XM_DIO(7));
p144: iobuf PORT MAP(I => XM_WDAT(0), O => XM_RDAT(0), T => MEM_T, IO => XM_DIO(0));
p142: iobuf PORT MAP(I => XM_WDAT(6), O => XM_RDAT(6), T => MEM_T, IO => XM_DIO(6));
p141: iobuf PORT MAP(I => XM_WDAT(1), O => XM_RDAT(1), T => MEM_T, IO => XM_DIO(1));
p140: iobuf PORT MAP(I => XM_WDAT(5), O => XM_RDAT(5), T => MEM_T, IO => XM_DIO(5));
p139: iobuf PORT MAP(I => XM_WDAT(2), O => XM_RDAT(2), T => MEM_T, IO => XM_DIO(2));
p133: iobuf PORT MAP(I => XM_WDAT(4), O => XM_RDAT(4), T => MEM_T, IO => XM_DIO(4));
p131: iobuf PORT MAP(I => XM_WDAT(3), O => XM_RDAT(3), T => MEM_T, IO => XM_DIO(3));
p63: iobuf PORT MAP(I => WE_N, O => DEL_WE_N, T => '0', IO => XM_WE_N);
process(CLK40)
begin
if (rising_edge(CLK40)) then
LCLK <= not LCLK;
end if;
end process;
end behavioral;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 13:06:28 11/19/2013
-- Design Name:
-- Module Name: My_32bit4x1Mux_948282 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity My_32bit4x1Mux_948282 is
Port ( Select1 : in STD_LOGIC;
Select2 : in STD_LOGIC;
A : in STD_LOGIC_VECTOR (31 downto 0);
B : in STD_LOGIC_VECTOR (31 downto 0);
C : in STD_LOGIC_VECTOR (31 downto 0);
D : in STD_LOGIC_VECTOR (31 downto 0);
R : out STD_LOGIC_VECTOR (31 downto 0));
end My_32bit4x1Mux_948282;
architecture Behavioral of My_32bit4x1Mux_948282 is
component My_16bit4x1Mux_948282 is
Port ( S_1 : in STD_LOGIC;
S_2 : in STD_LOGIC;
A_mux : in STD_LOGIC_VECTOR (15 downto 0);
B_mux : in STD_LOGIC_VECTOR (15 downto 0);
C_mux : in STD_LOGIC_VECTOR (15 downto 0);
D_mux : in STD_LOGIC_VECTOR (15 downto 0);
Result : out STD_LOGIC_VECTOR (15 downto 0));
end component;
begin
u0: My_16bit4x1Mux_948282 port map (S_1=>Select1, S_2=>Select2, A_mux=>A(15 downto 0), B_mux=>B(15 downto 0), C_mux=>C(15 downto 0), D_mux=>D(15 downto 0), Result=>R(15 downto 0));
u1: My_16bit4x1Mux_948282 port map (S_1=>Select1, S_2=>Select2, A_mux=>A(31 downto 16), B_mux=>B(31 downto 16), C_mux=>C(31 downto 16), D_mux=>D(31 downto 16), Result=>R(31 downto 16));
end Behavioral;
|
--------------------------------------------------------------------------------
-- Company: Lehrstuhl Integrierte Systeme - TUM
-- Engineer: Johannes Zeppenfeld
--
-- Project Name: LIS-IPIF
-- Module Name: lipif_mst_arbiter
-- Architectures: lipif_mst_arbiter_rtl
-- Description:
--
-- Dependencies:
--
-- Revision:
-- 10.4.2006 - File Created
--
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library lisipif_master_v1_00_c;
use lisipif_master_v1_00_c.all;
library UNISIM;
use UNISIM.VComponents.all;
entity lipif_mst_arbiter is
generic(
C_NUM_WIDTH : integer := 5;
C_ARBITRATION : integer := 0;
C_EN_SRL16 : boolean := true
);
port(
clk : in std_logic;
reset : in std_logic;
-- Control Signals to/from Read and Write Controllers
rd_rdy_i : in std_logic;
rd_init_o : out std_logic;
rd_ack_o : out std_logic;
rd_rearb_o : out std_logic;
rd_retry_i : in std_logic;
rd_abort_i : in std_logic;
wr_rdy_i : in std_logic;
wr_init_o : out std_logic;
wr_ack_o : out std_logic;
wr_rearb_o : out std_logic;
wr_retry_i : in std_logic;
wr_abort_i : in std_logic;
-- LIS-IPIC Read Qualifiers
M_rdReq_i : in std_logic;
M_rdAccept_o : out std_logic;
M_rdAddr_i : in std_logic_vector(31 downto 0);
M_rdNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_rdBE_i : in std_logic_vector(7 downto 0);
M_rdPriority_i : in std_logic_vector(1 downto 0);
M_rdType_i : in std_logic_vector(2 downto 0);
M_rdCompress_i : in std_logic;
M_rdGuarded_i : in std_logic;
M_rdLockErr_i : in std_logic;
-- LIS-IPIC Write Qualifiers
M_wrReq_i : in std_logic;
M_wrAccept_o : out std_logic;
M_wrAddr_i : in std_logic_vector(31 downto 0);
M_wrNum_i : in std_logic_vector(C_NUM_WIDTH-1 downto 0);
M_wrBE_i : in std_logic_vector(7 downto 0);
M_wrPriority_i : in std_logic_vector(1 downto 0);
M_wrType_i : in std_logic_vector(2 downto 0);
M_wrCompress_i : in std_logic;
M_wrGuarded_i : in std_logic;
M_wrOrdered_i : in std_logic;
M_wrLockErr_i : in std_logic;
-- LIS-IPIC Shared Qualifiers
M_Error_o : out std_logic;
M_Lock_i : in std_logic;
-- PLB Signals
PLB_MAddrAck : in std_logic;
PLB_MRearbitrate : in std_logic;
PLB_MErr : in std_logic;
M_request : out std_logic;
M_priority : out std_logic_vector(0 to 1);
M_busLock : out std_logic;
M_RNW : out std_logic;
M_BE : out std_logic_vector(0 to 7);
M_size : out std_logic_vector(0 to 3);
M_type : out std_logic_vector(0 to 2);
M_compress : out std_logic;
M_guarded : out std_logic;
M_ordered : out std_logic;
M_lockErr : out std_logic;
M_abort : out std_logic;
M_ABus : out std_logic_vector(0 to 31)
);
end lipif_mst_arbiter;
architecture lipif_mst_arbiter_rtl of lipif_mst_arbiter is
constant C_QUAL_WIDTH : integer := 54;
signal arb_qual : std_logic_vector(C_QUAL_WIDTH-1 downto 0);
signal arb_qual_req : std_logic;
signal arb_qual_rdy : std_logic;
signal plb_qual : std_logic_vector(C_QUAL_WIDTH-1 downto 0);
signal plb_qual_req : std_logic;
signal plb_qual_rdy : std_logic;
signal arb_nxt_rnw : std_logic; -- Transfer direction priority for next request
signal xfer_rnw : std_logic; -- Last transfer direction
signal arb_ini_rd : std_logic; -- Latch read qualifiers and launch request
signal arb_ini_wr : std_logic; -- Latch write qualifiers and launch request
signal plb_rearb : std_logic; -- Current request needs rearbitration
signal plb_rnw : std_logic; -- Current request direction
begin
-- TODO: Error, Bus Locking
M_Error_o <= '0'; -- PLB_MErr
-- TIMING(18%): TODO
M_busLock <= M_Lock_i;
-- Generate control signals to control unit.
-- Ignore AddrAck when aborting
rd_ack_o <= PLB_MAddrAck and plb_rnw and not rd_abort_i;
rd_rearb_o <= plb_rearb and plb_rnw;
wr_ack_o <= PLB_MAddrAck and not plb_rnw and not wr_abort_i;
wr_rearb_o <= plb_rearb and not plb_rnw;
-- Mask PLB request signal with the transfer's rearbitration status.
-- TIMING(8%): Both plb_qual_req and plb_rearb are register outputs, which should
-- give enough time for one LUT to combine them.
M_request <= plb_qual_req and not plb_rearb;
-- Discard request when the control unit asserts an abort.
-- The unit is responsible for ensuring that it has the arbiter's focus.
plb_qual_rdy <= PLB_MAddrAck or rd_abort_i or wr_abort_i;
-- Assert abort signal to PLB when aborting a transfer prior to address ack
-- TIMING(43%): plb_rearb is direct register output, xx_abort generated by rd/wr
-- controller with 3-input AND gate ("mst_term and prim_valid and not prim_ack")
M_abort <= (rd_abort_i or wr_abort_i) and not plb_rearb;
-- Calculate next read/write priority based on arbitration scheme
arb_nxt_rnw <= '1' when (C_ARBITRATION=1 or (C_ARBITRATION=0 and xfer_rnw='0')) else '0';
-- Arbitrate between read and write units
arb_ini_rd <= M_rdReq_i and rd_rdy_i and arb_qual_rdy and (arb_nxt_rnw or not M_wrReq_i or not wr_rdy_i);
arb_ini_wr <= M_wrReq_i and wr_rdy_i and arb_qual_rdy and (not arb_nxt_rnw or not M_rdReq_i or not rd_rdy_i);
arb_qual_req <= arb_ini_rd or arb_ini_wr;
-- Pass accept signals to output
M_rdAccept_o <= arb_ini_rd;
rd_init_o <= arb_ini_rd;
M_wrAccept_o <= arb_ini_wr;
wr_init_o <= arb_ini_wr;
-- Keep track of current transfer direction
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
xfer_rnw <= '0';
else
if(arb_ini_rd='1') then
xfer_rnw <= '1';
elsif(arb_ini_wr='1') then
xfer_rnw <= '0';
end if;
end if;
end if;
end process;
-- Keep track of the rearbitration state of the current request
process(clk) begin
if(clk='1' and clk'event) then
if(reset='1') then
plb_rearb <= '0';
else
-- plb_rearb is set when slave requests rearbitration
if(PLB_MRearbitrate='1' and PLB_MAddrAck='0') then
plb_rearb <= '1';
-- plb_rearb is negated when the associated control unit
-- aborts the transfer or signals a retry
elsif((plb_rnw='1' and (rd_retry_i='1' or rd_abort_i='1')) or
(plb_rnw='0' and (wr_retry_i='1' or wr_abort_i='1'))) then
plb_rearb <= '0';
end if;
end if;
end if;
end process;
-- Generate request qualifiers and merge onto single bus for pipebuf
process(arb_ini_rd, M_rdAddr_i, M_rdNum_i, M_rdBE_i, M_rdPriority_i, M_rdType_i,
M_rdCompress_i, M_rdGuarded_i, M_rdLockErr_i,
arb_ini_wr, M_wrAddr_i, M_wrNum_i, M_wrBE_i, M_wrPriority_i, M_wrType_i,
M_wrCompress_i, M_wrGuarded_i, M_wrOrdered_i, M_wrLockErr_i)
variable be_cnt : std_logic_vector(3 downto 0);
begin
if(arb_ini_rd='1') then
-- TODO: C_EN_RECALC_ADDR
arb_qual(31 downto 0) <= M_rdAddr_i; -- M_ABus(0 to 31)
-- TODO: Can BE be optimized? Maybe by calculating after muxing?
-- size and BE dependant on requested transfer length
if(CONV_INTEGER(UNSIGNED(M_rdNum_i))<=1) then
arb_qual(39 downto 32) <= M_rdBE_i; -- M_BE(0 to 7)
arb_qual(43 downto 40) <= "0000"; -- M_size(0 to 3)
else
-- Check for transfer longer than 16 dwords
if(CONV_INTEGER(UNSIGNED(M_rdNum_i))>16) then
arb_qual(39 downto 32) <= (others=>'0'); -- M_BE(0 to 7)
else
be_cnt := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(UNSIGNED(M_rdNum_i))-1, 4);
arb_qual(39 downto 36) <= be_cnt; -- M_BE(0 to 3)
arb_qual(35 downto 32) <= "0000"; -- M_BE(4 to 7)
end if;
arb_qual(43 downto 40) <= "1011"; -- M_size(0 to 3)
end if;
arb_qual(45 downto 44) <= M_rdPriority_i; -- M_priority(0 to 1)
arb_qual(46) <= '1'; -- M_RNW
arb_qual(49 downto 47) <= M_rdType_i; -- M_type(0 to 2);
arb_qual(50) <= M_rdCompress_i; -- M_compress
arb_qual(51) <= M_rdGuarded_i; -- M_guarded
arb_qual(52) <= '0'; -- M_ordered
arb_qual(53) <= M_rdLockErr_i; -- M_lockErr
else
-- TODO: C_EN_RECALC_ADDR
arb_qual(31 downto 0) <= M_wrAddr_i; -- M_ABus(0 to 31)
-- TODO: Can BE be optimized? Maybe by calculating after muxing?
-- size and BE dependant on requested transfer length
if(CONV_INTEGER(UNSIGNED(M_wrNum_i))<=1) then
arb_qual(39 downto 32) <= M_wrBE_i; -- M_BE(0 to 7)
arb_qual(43 downto 40) <= "0000"; -- M_size(0 to 3)
else
-- Check for transfer longer than 16 dwords
if(CONV_INTEGER(UNSIGNED(M_wrNum_i))>16) then
arb_qual(39 downto 32) <= (others=>'0'); -- M_BE(0 to 7)
else
be_cnt := CONV_STD_LOGIC_VECTOR(CONV_INTEGER(UNSIGNED(M_wrNum_i))-1, 4);
arb_qual(39 downto 36) <= be_cnt; -- M_BE(0 to 3)
arb_qual(35 downto 32) <= "0000"; -- M_BE(4 to 7)
end if;
arb_qual(43 downto 40) <= "1011"; -- M_size(0 to 3)
end if;
arb_qual(45 downto 44) <= M_wrPriority_i; -- M_priority(0 to 1)
arb_qual(46) <= '0'; -- M_RNW
arb_qual(49 downto 47) <= M_wrType_i; -- M_type(0 to 2);
arb_qual(50) <= M_wrCompress_i; -- M_compress
arb_qual(51) <= M_wrGuarded_i; -- M_guarded
arb_qual(52) <= M_wrOrdered_i; -- M_ordered
arb_qual(53) <= M_wrLockErr_i; -- M_lockErr
end if;
end process;
-- Instantiate pipeline buffer
arb_pipebuf_0: entity lisipif_master_v1_00_c.lipif_mst_pipebuf
generic map (
C_DATA_WIDTH => C_QUAL_WIDTH,
-- Since SRL outputs are slow (>3ns after clk), must use registers
-- to meet PLB timings.
-- The good news: Even takes up fewer slices when using registers!
C_EN_SRL16 => false
)
port map (
clk => clk,
reset => reset,
-- Previous (input) stage I/O
prevReq_i => arb_qual_req,
prevRdy_o => arb_qual_rdy,
prevData_i => arb_qual,
-- Next (output) stage I/O
nextReq_o => plb_qual_req,
nextRdy_i => plb_qual_rdy,
nextData_o => plb_qual
);
-- Forward request qualifiers to PLB
-- TIMING(18%): Direct register outputs
M_ABus <= plb_qual(31 downto 0);
M_BE <= plb_qual(39 downto 32);
M_size <= plb_qual(43 downto 40);
M_type <= plb_qual(49 downto 47);
M_compress <= plb_qual(50);
M_guarded <= plb_qual(51);
M_ordered <= plb_qual(52);
M_lockErr <= plb_qual(53);
-- TIMING(8%): Direct register outputs
M_priority <= plb_qual(45 downto 44);
M_RNW <= plb_qual(46);
-- Transfer direction of current request for local use
plb_rnw <= plb_qual(46);
end lipif_mst_arbiter_rtl;
|
-- EMACS settings: -*- tab-width: 2; indent-tabs-mode: t -*-
-- vim: tabstop=2:shiftwidth=2:noexpandtab
-- kate: tab-width 2; replace-tabs off; indent-width 2;
-------------------------------------------------------------------------------
-- This file is part of the Queens@TUD solver suite
-- for enumerating and counting the solutions of an N-Queens Puzzle.
--
-- Copyright (C) 2008-2015
-- Thomas B. Preusser <[email protected]>
-------------------------------------------------------------------------------
-- This design is free software: you can redistribute it and/or modify
-- it under the terms of the GNU Affero General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU Affero General Public License for more details.
--
-- You should have received a copy of the GNU Affero General Public License
-- along with this design. If not, see <http://www.gnu.org/licenses/>.
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library PoC;
use PoC.physical.all;
entity kc705_queens_uart is
generic (
N : positive := 27;
L : positive := 2;
SOLVERS : positive := 144;
COUNT_CYCLES : boolean := false;
CLK_FREQ : FREQ := 200 MHz;
CLK_DIVA : positive := 7;
CLK_MULA : positive := 57;
CLK_DIVB : positive := 6;
BAUDRATE : positive := 115200;
SENTINEL : std_logic_vector(7 downto 0) := x"FA" -- Start Byte
);
port (
clk_p : in std_logic;
clk_n : in std_logic;
rx : in std_logic;
tx : out std_logic;
rts : in std_logic;
cts : out std_logic;
-- Fan Control
FanControl_PWM : out std_logic
);
end kc705_queens_uart;
library IEEE;
use IEEE.numeric_std.all;
library UNISIM;
use UNISIM.vcomponents.all;
library PoC;
architecture rtl of kc705_queens_uart is
-- Global Control
constant CLK_COMP_FREQ : FREQ := CLK_FREQ * CLK_MULA / CLK_DIVA / CLK_DIVB;
constant CLK_SLOW_FREQ : FREQ := CLK_FREQ * CLK_MULA / CLK_DIVA / 100;
signal clk200 : std_logic; -- 200 MHz Input Clock
signal clk_comp : std_logic; -- Computation Clock
signal clk_slow : std_logic; -- Slow Interface Clock
signal rst : std_logic;
begin
-----------------------------------------------------------------------------
-- Generate Global Controls
blkGlobal: block is
signal clkfb : std_logic; -- Feedback Clock
signal clk_compu : std_logic; -- Unbuffered Synthesized Clock
signal clk_slowu : std_logic; -- Unbuffered Synthesized Clock
begin
clk_in : IBUFGDS
port map(
O => clk200,
I => clk_p,
IB => clk_n
);
pll : PLLE2_BASE
generic map (
CLKIN1_PERIOD => to_real(to_time(CLK_FREQ), 1 ns),
DIVCLK_DIVIDE => CLK_DIVA,
CLKFBOUT_MULT => CLK_MULA,
CLKOUT0_DIVIDE => CLK_DIVB,
CLKOUT1_DIVIDE => 100,
STARTUP_WAIT => "true"
)
port map (
CLKIN1 => clk200,
CLKFBIN => clkfb,
RST => '0',
CLKOUT0 => clk_compu,
CLKOUT1 => clk_slowu,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
CLKFBOUT => clkfb,
LOCKED => open,
PWRDWN => '0'
);
comp_buf : BUFG
port map (
I => clk_compu,
O => clk_comp
);
slow_buf : BUFH
port map (
I => clk_slowu,
O => clk_slow
);
-- No Reset
rst <= '0';
end block blkGlobal;
-----------------------------------------------------------------------------
-- Fan Control
fan : entity PoC.io_FanControl
generic map (
CLOCK_FREQ => CLK_SLOW_FREQ
)
port map (
Clock => clk_slow,
Reset => '0',
Fan_PWM => FanControl_PWM,
TachoFrequency => open
);
----------------------------------------------------------------------------
-- Solver Chain
chain: entity work.queens_uart
generic map (
N => N,
L => L,
SOLVERS => SOLVERS,
COUNT_CYCLES => COUNT_CYCLES,
CLK_FREQ => integer(to_real(CLK_COMP_FREQ, 1 Hz)),
BAUDRATE => BAUDRATE,
SENTINEL => SENTINEL
)
port map (
clk => clk_comp,
rst => rst,
rx => rx,
tx => tx,
snap => open,
avail => open
);
cts <= rts;
end rtl;
|
entity names2 is
end entity;
architecture test of names2 is
type array1 is array (natural range <>) of integer;
type array2 is array (natural range <>) of array1(1 to 10);
type array3 is array (natural range <>) of array2(1 to 10);
type rec is record
x : array1(1 to 3);
y : integer;
end record;
function get_array3(n : integer) return array3;
function get_array2 return array2;
procedure do_rec(x : in rec);
type pt is protected
function get_array1(n : integer) return array1;
end protected;
begin
p1: process is
variable p : pt;
begin
assert get_array3(1)(2)(2)(3) = 1; -- OK
--assert get_array2(2)(3) = 1; -- OK (not yet)
assert p.get_array1(1)(2) = 1; -- OK
end process;
p2: process is
begin
do_rec(x.x => (1, 2, 3), x.y => 5); -- OK
end process;
end architecture;
|
entity tb_test3 is
end tb_test3;
library ieee;
use ieee.std_logic_1164.all;
architecture behav of tb_test3 is
signal clk : std_logic;
signal wr : std_logic;
signal arst : std_logic;
begin
dut: entity work.test3
port map (clk, wr, arst);
process
procedure pulse is
begin
clk <= '0';
wait for 1 ns;
clk <= '1';
wait for 1 ns;
end pulse;
begin
wr <= '0';
arst <= '1';
pulse;
report "cycle 2";
arst <= '0';
pulse;
report "cycle 3";
arst <= '1';
wr <= '1';
pulse;
wait;
end process;
end behav;
|
-- fifo_vw testbench
-- Greg Stitt
-- University of Florida
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use work.math_custom.all;
use work.tb_pkg.all;
entity fifo_vw_tb is
generic(
parallel_io : positive := 4;
data_width : positive := 8;
test_size : positive := 400;
input_delay_prob : real range 0.0 to 1.0 := 0.1;
min_input_delay : natural := 1;
max_input_delay : natural := 10;
output_delay_prob : real range 0.0 to 1.0 := 0.0;
min_output_delay : natural := 1;
max_output_delay : natural := 10
);
end fifo_vw_tb;
architecture TB of fifo_vw_tb is
-- ensure that that input size is a multiple of parallel_io. This will
-- round up test_size to the next multiple
constant adjusted_input_size : integer := integer(ceil(real(test_size) / real(parallel_io)))*parallel_io;
type data_array is array (0 to adjusted_input_size-1) of std_logic_vector(data_width-1 downto 0);
signal input_array : data_array;
signal output_array : data_array;
signal clk_en : std_logic := '1';
signal clk, rst, rd, wr : std_logic := '0';
signal empty, full : std_logic;
signal wr_amount : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0) := (others => '0');
signal valid_count : std_logic_vector(bitsNeeded(parallel_io)-1 downto 0) := (others => '0');
signal input : std_logic_vector(parallel_io*data_width-1 downto 0) := (others => '0');
signal output : std_logic_vector(parallel_io*data_width-1 downto 0);
signal input_ready : std_logic := '0';
signal output_ready : std_logic := '0';
signal input_done : std_logic := '0';
signal all_outputs : boolean := false;
type count_array is array (0 to adjusted_input_size-1) of integer;
signal counts : count_array;
signal stall : std_logic := '0';
begin
U_FIFO_VW : entity work.fifo_vw
generic map(
data_width => data_width,
parallel_io => parallel_io)
port map(
clk => clk,
rst => rst,
rd => rd,
wr => wr,
valid_count => valid_count,
empty => empty,
full => full,
input => input,
output => output
);
clk <= not clk after 10 ns when clk_en = '1' else '0';
-- determine when to write
process(full, input_ready, rst, input_done)
begin
-- input_ready includes random delays
wr <= input_ready and not full and not rst and not input_done;
end process;
-- set the inputs during a write
process(clk, wr, rst)
variable input_count : integer := 0;
begin
if (rst = '1') then
input_count := 0;
for j in 0 to parallel_io-1 loop
input((parallel_io-j)*data_width-1 downto (parallel_io-j-1)*data_width) <= input_array(j);
end loop;
-- set the inputs for each write
elsif (rising_edge(clk) and wr = '1' and rst = '0') then
input_count := input_count + to_integer(unsigned(valid_count));
-- write valid_count elements into the fifo
for j in 0 to parallel_io-1 loop
if (input_count + j < adjusted_input_size) then
input((parallel_io-j)*data_width-1 downto (parallel_io-j-1)*data_width) <= input_array(input_count + j);
end if;
end loop;
if (input_count = adjusted_input_size) then
input_done <= '1';
end if;
end if;
end process;
-- randomly vary write timings
process
variable s1, s2 : positive; -- seeds for rand function
begin
input_ready <= '0';
wait until rst = '0';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
while (input_done = '0') loop
input_ready <= '0';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, input_delay_prob, min_input_delay, max_input_delay);
input_ready <= '1';
wait until rising_edge(clk);
end loop;
input_ready <= '0';
wait;
end process;
-- initialize the simulation
process
variable rand : integer; -- random inputs to be written to fifo
variable s1, s2 : positive; -- seeds for rand function
variable input_count : integer;
begin
-- initialize inputs
for i in 0 to adjusted_input_size-1 loop
-- randomInt(s1, s2, 0, 2**data_width-1, rand);
-- input_array(i) <= std_logic_vector(to_unsigned(rand, data_width));
input_array(i) <= std_logic_vector(to_unsigned(i, data_width));
end loop;
--Reset the entity and initialize the wr and input to zero
rst <= '1';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
rst <= '0';
for i in 0 to 5 loop
wait until rising_edge(clk);
end loop;
wait;
end process;
-- randomly vary read timings
vary_read_timing : process
variable s1, s2 : positive; -- seeds for rand function
begin
while (not all_outputs) loop
output_ready <= '0';
--randomize a delay so that the fifo can drain and reads larger than whats in the buffer can be tested
randDelay(s1, s2, clk, output_delay_prob, min_output_delay, max_output_delay);
output_ready <= '1';
wait until rising_edge(clk);
end loop;
wait;
end process;
-- determine when reads occur
process(empty, output_ready)
begin
rd <= not empty and output_ready;
end process;
-- set write amounts
write_amounts : process(clk, rst)
variable s1, s2 : positive;
variable wr_amount_v : integer;
begin
if (rst = '1') then
randomInt(s1, s2, 0, parallel_io+1, wr_amount_v);
valid_count <= std_logic_vector(to_unsigned(wr_amount_v, valid_count'length));
elsif (rising_edge(clk) and wr = '1') then
randomInt(s1, s2, 0, parallel_io+1, wr_amount_v);
valid_count <= std_logic_vector(to_unsigned(wr_amount_v, valid_count'length));
end if;
end process;
check_outputs : process(clk)
variable out_ind_count : integer := 0;
variable output_temp : std_logic_vector(data_width-1 downto 0) := (others => '0');
begin
-- if there is a valid output, verify it
if (rising_edge(clk) and rd = '1') then
-- check the outputs
for i in 0 to parallel_io-1 loop
output_temp := output((parallel_io-i)*data_width-1 downto (parallel_io-i-1)*data_width);
assert(output_temp = input_array(out_ind_count)) report "Output incorrect.";
out_ind_count := out_ind_count + 1;
end loop;
end if;
if (out_ind_count = adjusted_input_size) then
report "SIMULATION COMPLETE!!!";
clk_en <= '0';
end if;
end process;
end TB;
|
--RAM for the result vector R
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.Numeric_Std.all;
use IEEE.Std_logic_unsigned.all;
-----------------------------------------
entity ramR is
port(
clock : in std_logic;
write_enable : in std_logic;
read_enable : in std_logic;
address : in std_logic_vector (2 downto 0);
datain : in std_logic_vector (18 downto 0);
dataout : out std_logic_vector (18 downto 0)
);
end entity ramR;
------------------------------------------
architecture ramR of ramR is
type memRam is array (0 to 8 - 1 ) of std_logic_vector (18 downto 0);
signal ram : memRam;
begin
process (clock) is
begin
if rising_edge(clock) then
if write_enable = '1' then
if conv_integer(address(2 downto 0)) < 8 then
ram(conv_integer(address(2 downto 0))) <= datain;
end if;
end if;
if read_enable = '1' then
dataout <= ram (conv_integer(address));
end if;
end if;
end process;
end architecture ramR;
|
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2003 Xilinx, Inc.
-- All Right Reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 7.1.04i
-- \ \ Application : sch2vhdl
-- / / Filename : a2dstatio.vhf
-- /___/ /\ Timestamp : 02/10/2006 14:47:29
-- \ \ / \
-- \___\/\___\
--
--Command: C:/Xilinx/bin/nt/sch2vhdl.exe -intstyle ise -family xc9500 -flat -suppress -w a2dstatio.sch a2dstatio.vhf
--Design Name: a2dstatio
--Device: xc9500
--Purpose:
-- This vhdl netlist is translated from an ECS schematic. It can be
-- synthesis and simulted, but it should not be modified.
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity FTCE_MXILINX_a2dstatio is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end FTCE_MXILINX_a2dstatio;
architecture BEHAVIORAL of FTCE_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
signal TQ : std_logic;
signal Q_DUMMY : std_logic;
component XOR2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of XOR2 : component is "BLACK_BOX";
component FDCE
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
D : in std_logic;
Q : out std_logic);
end component;
attribute BOX_TYPE of FDCE : component is "BLACK_BOX";
begin
Q <= Q_DUMMY;
I_36_32 : XOR2
port map (I0=>T,
I1=>Q_DUMMY,
O=>TQ);
I_36_35 : FDCE
port map (C=>C,
CE=>CE,
CLR=>CLR,
D=>TQ,
Q=>Q_DUMMY);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity CB4CE_MXILINX_a2dstatio is
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
CEO : out std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
TC : out std_logic);
end CB4CE_MXILINX_a2dstatio;
architecture BEHAVIORAL of CB4CE_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
attribute HU_SET : string ;
signal T2 : std_logic;
signal T3 : std_logic;
signal XLXN_1 : std_logic;
signal Q0_DUMMY : std_logic;
signal Q1_DUMMY : std_logic;
signal Q2_DUMMY : std_logic;
signal Q3_DUMMY : std_logic;
signal TC_DUMMY : std_logic;
component AND4
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
I3 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND4 : component is "BLACK_BOX";
component AND3
port ( I0 : in std_logic;
I1 : in std_logic;
I2 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND3 : component is "BLACK_BOX";
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component FTCE_MXILINX_a2dstatio
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
T : in std_logic;
Q : out std_logic);
end component;
attribute HU_SET of U0 : label is "U0_0";
attribute HU_SET of U1 : label is "U1_1";
attribute HU_SET of U2 : label is "U2_2";
attribute HU_SET of U3 : label is "U3_3";
begin
Q0 <= Q0_DUMMY;
Q1 <= Q1_DUMMY;
Q2 <= Q2_DUMMY;
Q3 <= Q3_DUMMY;
TC <= TC_DUMMY;
I_36_31 : AND4
port map (I0=>Q3_DUMMY,
I1=>Q2_DUMMY,
I2=>Q1_DUMMY,
I3=>Q0_DUMMY,
O=>TC_DUMMY);
I_36_32 : AND3
port map (I0=>Q2_DUMMY,
I1=>Q1_DUMMY,
I2=>Q0_DUMMY,
O=>T3);
I_36_33 : AND2
port map (I0=>Q1_DUMMY,
I1=>Q0_DUMMY,
O=>T2);
I_36_58 : VCC
port map (P=>XLXN_1);
I_36_67 : AND2
port map (I0=>CE,
I1=>TC_DUMMY,
O=>CEO);
U0 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>XLXN_1,
Q=>Q0_DUMMY);
U1 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>Q0_DUMMY,
Q=>Q1_DUMMY);
U2 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T2,
Q=>Q2_DUMMY);
U3 : FTCE_MXILINX_a2dstatio
port map (C=>C,
CE=>CE,
CLR=>CLR,
T=>T3,
Q=>Q3_DUMMY);
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity BUFE16_MXILINX_a2dstatio is
port ( E : in std_logic;
I : in std_logic_vector (15 downto 0);
O : out std_logic_vector (15 downto 0));
end BUFE16_MXILINX_a2dstatio;
architecture BEHAVIORAL of BUFE16_MXILINX_a2dstatio is
attribute BOX_TYPE : string ;
component BUFE
port ( E : in std_logic;
I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUFE : component is "BLACK_BOX";
begin
I_36_30 : BUFE
port map (E=>E,
I=>I(8),
O=>O(8));
I_36_31 : BUFE
port map (E=>E,
I=>I(9),
O=>O(9));
I_36_32 : BUFE
port map (E=>E,
I=>I(10),
O=>O(10));
I_36_33 : BUFE
port map (E=>E,
I=>I(11),
O=>O(11));
I_36_34 : BUFE
port map (E=>E,
I=>I(15),
O=>O(15));
I_36_35 : BUFE
port map (E=>E,
I=>I(14),
O=>O(14));
I_36_36 : BUFE
port map (E=>E,
I=>I(13),
O=>O(13));
I_36_37 : BUFE
port map (E=>E,
I=>I(12),
O=>O(12));
I_36_38 : BUFE
port map (E=>E,
I=>I(6),
O=>O(6));
I_36_39 : BUFE
port map (E=>E,
I=>I(7),
O=>O(7));
I_36_40 : BUFE
port map (E=>E,
I=>I(0),
O=>O(0));
I_36_41 : BUFE
port map (E=>E,
I=>I(1),
O=>O(1));
I_36_42 : BUFE
port map (E=>E,
I=>I(2),
O=>O(2));
I_36_43 : BUFE
port map (E=>E,
I=>I(3),
O=>O(3));
I_36_44 : BUFE
port map (E=>E,
I=>I(4),
O=>O(4));
I_36_45 : BUFE
port map (E=>E,
I=>I(5),
O=>O(5));
end BEHAVIORAL;
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
-- synopsys translate_off
library UNISIM;
use UNISIM.Vcomponents.ALL;
-- synopsys translate_on
entity a2dstatio is
port ( A2DIOEBL : in std_logic;
PLLOUT : in std_logic;
SIOR : in std_logic;
SIOW : in std_logic;
A2DRS : in std_logic;
FIFOCTL : in std_logic_vector (7 downto 0);
PLLDBN : out std_logic;
-- TEST45 : out std_logic;
A2DBUS : inout std_logic_vector (15 downto 0);
BSD : inout std_logic_vector (15 downto 0));
end a2dstatio;
architecture BEHAVIORAL of a2dstatio is
attribute HU_SET : string ;
attribute BOX_TYPE : string ;
-- signal Latch_A2DBUS: std_logic_vector(15 downto 0);
signal XLXN_199 : std_logic;
signal XLXN_200 : std_logic;
signal XLXN_201 : std_logic;
signal XLXN_202 : std_logic;
signal XLXN_203 : std_logic;
signal XLXN_238 : std_logic;
signal XLXN_239 : std_logic;
signal my_data : std_logic_vector(15 downto 0);
-- component FD16_MXILINX_a2dstatio
-- port ( C : in std_logic;
-- D : in std_logic_vector (15 downto 0);
-- Q : out std_logic_vector (15 downto 0));
-- end component;
component BUFE16_MXILINX_a2dstatio
port ( E : in std_logic;
I : in std_logic_vector (15 downto 0);
O : out std_logic_vector (15 downto 0));
end component;
component AND2
port ( I0 : in std_logic;
I1 : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of AND2 : component is "BLACK_BOX";
component CB4CE_MXILINX_a2dstatio
port ( C : in std_logic;
CE : in std_logic;
CLR : in std_logic;
CEO : out std_logic;
Q0 : out std_logic;
Q1 : out std_logic;
Q2 : out std_logic;
Q3 : out std_logic;
TC : out std_logic);
end component;
component VCC
port ( P : out std_logic);
end component;
attribute BOX_TYPE of VCC : component is "BLACK_BOX";
component GND
port ( G : out std_logic);
end component;
attribute BOX_TYPE of GND : component is "BLACK_BOX";
component BUF
port ( I : in std_logic;
O : out std_logic);
end component;
attribute BOX_TYPE of BUF : component is "BLACK_BOX";
attribute HU_SET of XLXI_17 : label is "XLXI_17_4";
attribute HU_SET of XLXI_84 : label is "XLXI_84_5";
attribute HU_SET of XLXI_160 : label is "XLXI_160_6";
attribute HU_SET of XLXI_166 : label is "XLXI_166_7";
begin
process(A2DRS)
begin
if A2DRS = '1' then
my_data <= X"AAAA";
else
my_data <= X"5555";
end if;
end process;
-- MY_XLXI : FD16_MXILINX_a2dstatio
-- port map (C=>PLLOUT,
-- D(15 downto 0)=>A2DBUS(15 downto 0),
-- Q(15 downto 0)=>Latch_A2DBUS(15 downto 0));
XLXI_17 : BUFE16_MXILINX_a2dstatio
port map (E=>XLXN_238,
-- I(15 downto 0)=>X"AAAA",
I(15 downto 0)=>A2DBUS(15 downto 0),
O(15 downto 0)=>BSD(15 downto 0));
XLXI_18 : AND2
port map (I0=>SIOR,
I1=>A2DIOEBL,
O=>XLXN_238);
XLXI_84 : BUFE16_MXILINX_a2dstatio
port map (E=>XLXN_239,
-- port map (E=>FIFOCTL(1),
-- I(15 downto 0)=>my_data(15 downto 0),
I(15 downto 0)=>BSD(15 downto 0),
O(15 downto 0)=>A2DBUS(15 downto 0));
XLXI_160 : CB4CE_MXILINX_a2dstatio
port map (C=>PLLOUT,
CE=>XLXN_200,
CLR=>XLXN_199,
CEO=>open,
Q0=>open,
Q1=>open,
Q2=>open,
Q3=>XLXN_203,
TC=>open);
XLXI_161 : VCC
port map (P=>XLXN_200);
XLXI_162 : GND
port map (G=>XLXN_199);
XLXI_164 : VCC
port map (P=>XLXN_201);
XLXI_165 : GND
port map (G=>XLXN_202);
XLXI_166 : CB4CE_MXILINX_a2dstatio
port map (C=>XLXN_203,
CE=>XLXN_201,
CLR=>XLXN_202,
CEO=>open,
Q0=>open,
Q1=>open,
Q2=>PLLDBN,
Q3=>open,
TC=>open);
-- XLXI_185 : BUF
-- port map (I=>XLXN_238,
-- O=>TEST45);
XLXI_186 : AND2
port map (I0=>A2DIOEBL,
I1=>SIOW,
O=>XLXN_239);
end BEHAVIORAL;
|
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 18:32:20 09/25/2015
-- Design Name:
-- Module Name: /home/kurtisn/mtc/Scrod_mTC_Firmware/src/firmware-general/General/sim/RstSim.vhd
-- Project Name: scrodMtc
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: InitRst
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY RstSim IS
END RstSim;
ARCHITECTURE behavior OF RstSim IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT InitRst
PORT(
clk : IN std_logic;
asyncRst : IN std_logic;
syncRst : OUT std_logic
);
END COMPONENT;
--Inputs
signal fabClk : std_logic;
signal fabClkRst : std_logic;
signal ethClk62 : std_logic;
signal ethClk62Rst : std_logic;
signal ethClk125 : std_logic;
signal ethClk125Rst : std_logic;
signal userRst : std_logic;
-- Clock period definitions
constant clk125_period : time := 8 ns;
constant clk62_period : time := 16 ns;
constant fabclk_period : time := 4 ns;
BEGIN
---------------------------------------------------------------------------
-- Resets
---------------------------------------------------------------------------
-- Generate stable reset signal
U_PwrUpRst : entity work.InitRst
generic map (
RST_CNT_G => 12500,
GATE_DELAY_G => 0 ns
)
port map (
clk => fabClk,
syncRst => fabClkRst
);
-- Synchronize the reset to the 125 MHz domain
U_RstSync125 : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => 0 ns
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => ethClk62Rst,
syncBit => ethClk125Rst
);
-- Synchronize the reset to the 62 MHz domain
U_RstSync62 : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => 0 ns
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => fabClkRst,
syncBit => ethClk62Rst
);
-- User reset
U_RstSyncUser : entity work.SyncBit
generic map (
INIT_STATE_G => '1',
GATE_DELAY_G => 0 ns
)
port map (
clk => ethClk125,
rst => '0',
asyncBit => ethClk62Rst,
syncBit => userRst
);
-- Clock process definitions
clk125_process :process
begin
ethClk125 <= '0';
wait for clk125_period/2;
ethClk125 <= '1';
wait for clk125_period/2;
end process;
-- Clock process definitions
clk62_process :process
begin
ethClk62 <= '0';
wait for clk62_period/2;
ethClk62 <= '1';
wait for clk62_period/2;
end process;
-- Clock process definitions
fabclk_process :process
begin
fabclk <= '0';
wait for fabclk_period/2;
fabclk <= '1';
wait for fabclk_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
-- insert stimulus here
wait;
end process;
END;
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3 Based Computer System designed for the
--Digilent Nexys 2 FPGA Development Board
--
--Module Title: Output_Port_MUX
--Module Description:
-- This module holds four 32-bit latches,
-- one for each extended output port, and the multiplexer that handles
-- sending data to the correct latch. This is tied to output pins 15
-- and 14, which select which one of the four latches get the output of the OZ-3.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Output_Port_MUX is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output0 : out STD_LOGIC_VECTOR (31 downto 0);
output1 : out STD_LOGIC_VECTOR (31 downto 0);
output2 : out STD_LOGIC_VECTOR (31 downto 0);
output3 : out STD_LOGIC_VECTOR (31 downto 0));
end Output_Port_MUX;
architecture Behavioral of Output_Port_MUX is
--//Signals\\--
signal reg0 : STD_LOGIC_VECTOR(31 downto 0);
signal reg1 : STD_LOGIC_VECTOR(31 downto 0);
signal reg2 : STD_LOGIC_VECTOR(31 downto 0);
signal reg3 : STD_LOGIC_VECTOR(31 downto 0);
signal enable0 : STD_LOGIC;
signal enable1 : STD_LOGIC;
signal enable2 : STD_LOGIC;
signal enable3 : STD_LOGIC;
--\\Signals//--
--//Components\\--
component GenRegFalling is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Components//--
begin
main : process (sel, data)
begin
reg0 <= (others => '0');
reg1 <= (others => '0');
reg2 <= (others => '0');
reg3 <= (others => '0');
case sel is
when "00" =>
reg0 <= data;
when "01" =>
reg1 <= data;
when "10" =>
reg2 <= data;
when "11" =>
reg3 <= data;
when others =>
reg0 <= (others => '0');
end case;
end process;
reg_0 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable0,
reset => reset,
data => reg0,
output => output0);
reg_1 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable1,
reset => reset,
data => reg1,
output => output1);
reg_2 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable2,
reset => reset,
data => reg2,
output => output2);
reg_3 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable3,
reset => reset,
data => reg3,
output => output3);
enable0 <= ((not sel(0)) and (not sel(1))) and enable;
enable1 <= (sel(0) and (not sel(1))) and enable;
enable2 <= ((not sel(0)) and sel(1)) and enable;
enable3 <= (sel(0) and sel(1)) and enable;
end Behavioral;
|
----------------------------------------------------------------------------------
--Ben Oztalay, 2009-2010
--
--This VHDL code is part of the OZ-3 Based Computer System designed for the
--Digilent Nexys 2 FPGA Development Board
--
--Module Title: Output_Port_MUX
--Module Description:
-- This module holds four 32-bit latches,
-- one for each extended output port, and the multiplexer that handles
-- sending data to the correct latch. This is tied to output pins 15
-- and 14, which select which one of the four latches get the output of the OZ-3.
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Output_Port_MUX is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
data : in STD_LOGIC_VECTOR (31 downto 0);
sel : in STD_LOGIC_VECTOR (1 downto 0);
output0 : out STD_LOGIC_VECTOR (31 downto 0);
output1 : out STD_LOGIC_VECTOR (31 downto 0);
output2 : out STD_LOGIC_VECTOR (31 downto 0);
output3 : out STD_LOGIC_VECTOR (31 downto 0));
end Output_Port_MUX;
architecture Behavioral of Output_Port_MUX is
--//Signals\\--
signal reg0 : STD_LOGIC_VECTOR(31 downto 0);
signal reg1 : STD_LOGIC_VECTOR(31 downto 0);
signal reg2 : STD_LOGIC_VECTOR(31 downto 0);
signal reg3 : STD_LOGIC_VECTOR(31 downto 0);
signal enable0 : STD_LOGIC;
signal enable1 : STD_LOGIC;
signal enable2 : STD_LOGIC;
signal enable3 : STD_LOGIC;
--\\Signals//--
--//Components\\--
component GenRegFalling is
generic (size : integer);
Port ( clock : in STD_LOGIC;
enable : in STD_LOGIC;
reset : in STD_LOGIC;
data : in STD_LOGIC_VECTOR ((size - 1) downto 0);
output : out STD_LOGIC_VECTOR ((size - 1) downto 0));
end component;
--\\Components//--
begin
main : process (sel, data)
begin
reg0 <= (others => '0');
reg1 <= (others => '0');
reg2 <= (others => '0');
reg3 <= (others => '0');
case sel is
when "00" =>
reg0 <= data;
when "01" =>
reg1 <= data;
when "10" =>
reg2 <= data;
when "11" =>
reg3 <= data;
when others =>
reg0 <= (others => '0');
end case;
end process;
reg_0 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable0,
reset => reset,
data => reg0,
output => output0);
reg_1 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable1,
reset => reset,
data => reg1,
output => output1);
reg_2 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable2,
reset => reset,
data => reg2,
output => output2);
reg_3 : GenRegFalling generic map (size => 32)
port map (clock => clock,
enable => enable3,
reset => reset,
data => reg3,
output => output3);
enable0 <= ((not sel(0)) and (not sel(1))) and enable;
enable1 <= (sel(0) and (not sel(1))) and enable;
enable2 <= ((not sel(0)) and sel(1)) and enable;
enable3 <= (sel(0) and sel(1)) and enable;
end Behavioral;
|
entity module is end entity;
architecture arch of module is
function func(a:natural) return natural is
begin
if a=32 then return 2;
elsif a=16 then return 1;
else return 0;
end if;
end function;
constant DATAPATH :natural := 32;
constant LSLICES :natural := func(DATAPATH);
-- constant LSLICES :natural := 2;
signal a :bit;
signal s :bit_vector(LSLICES-1 downto 0);
begin
DATA8: if DATAPATH=8 generate
a <= '0';
end generate;
-- DATA16: if DATAPATH=16 generate
-- with s select a <=
-- '1' when "0",
-- '0' when others;
-- end generate;
DATA32: if DATAPATH=32 generate
with s select a <=
'1' when "00",
'0' when "01",
'1' when "10",
'0' when others;
end generate;
end architecture;
|
entity module is end entity;
architecture arch of module is
function func(a:natural) return natural is
begin
if a=32 then return 2;
elsif a=16 then return 1;
else return 0;
end if;
end function;
constant DATAPATH :natural := 32;
constant LSLICES :natural := func(DATAPATH);
-- constant LSLICES :natural := 2;
signal a :bit;
signal s :bit_vector(LSLICES-1 downto 0);
begin
DATA8: if DATAPATH=8 generate
a <= '0';
end generate;
-- DATA16: if DATAPATH=16 generate
-- with s select a <=
-- '1' when "0",
-- '0' when others;
-- end generate;
DATA32: if DATAPATH=32 generate
with s select a <=
'1' when "00",
'0' when "01",
'1' when "10",
'0' when others;
end generate;
end architecture;
|
entity module is end entity;
architecture arch of module is
function func(a:natural) return natural is
begin
if a=32 then return 2;
elsif a=16 then return 1;
else return 0;
end if;
end function;
constant DATAPATH :natural := 32;
constant LSLICES :natural := func(DATAPATH);
-- constant LSLICES :natural := 2;
signal a :bit;
signal s :bit_vector(LSLICES-1 downto 0);
begin
DATA8: if DATAPATH=8 generate
a <= '0';
end generate;
-- DATA16: if DATAPATH=16 generate
-- with s select a <=
-- '1' when "0",
-- '0' when others;
-- end generate;
DATA32: if DATAPATH=32 generate
with s select a <=
'1' when "00",
'0' when "01",
'1' when "10",
'0' when others;
end generate;
end architecture;
|
entity test is
type t is (foo, bar, 'b', 'q');
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity FMul is
port (
clk : in std_logic;
flt_in1 : in std_logic_vector(31 downto 0);
flt_in2 : in std_logic_vector(31 downto 0);
flt_out : out std_logic_vector(31 downto 0));
end FMul;
architecture dataflow_pipeline of FMul is
signal s1_sgn : std_logic;
signal s1_exp_add : unsigned(8 downto 0);
signal s1_frc_all : unsigned(47 downto 0);
signal s1_zero : std_logic;
signal s2_sgn : std_logic := '0';
signal s2_exp_add : unsigned(8 downto 0) := (others => '0');
signal s2_frc_all : unsigned(47 downto 0) := (others => '0');
signal s2_exp : unsigned(9 downto 0) := (others => '0');
signal s2_exp_up : unsigned(9 downto 0) := (others => '0');
signal s2_ulp : unsigned(24 downto 0) := (others => '0');
signal s2_frc : unsigned(24 downto 0) := (others => '0');
signal s2_frc_up : unsigned(24 downto 0) := (others => '0');
signal s2_zero : std_logic := '0';
signal s2_tail_any : std_logic := '0';
signal s2_round : std_logic := '0';
signal s3_sgn : std_logic := '0';
signal s3_exp : unsigned(9 downto 0) := (others => '0');
signal s3_exp_up : unsigned(9 downto 0) := (others => '0');
signal s3_frc : unsigned(24 downto 0) := (others => '0');
signal s3_frc_up : unsigned(24 downto 0) := (others => '0');
signal s3_round : std_logic := '0';
signal s3_frc_out_tmp : std_logic_vector(24 downto 0);
signal s3_exp_out_tmp : std_logic_vector(9 downto 0);
signal s3_frc_out : std_logic_vector(22 downto 0);
signal s3_exp_out : std_logic_vector(7 downto 0);
constant zero_22 : unsigned(21 downto 0) := (others => '0');
begin
s1_sgn <= flt_in1(31) xor flt_in2(31);
s1_exp_add <= unsigned("0" & flt_in1(30 downto 23)) + unsigned("0" & flt_in2(30 downto 23));
s1_frc_all <= unsigned('1' & flt_in1(22 downto 0)) * unsigned('1' & flt_in2(22 downto 0));
s1_zero <= '1' when flt_in1(30 downto 23) = "00000000" or flt_in2(30 downto 23) = "00000000" else '0';
pipe1 : process(clk)
begin
if rising_edge(clk) then
s2_sgn <= s1_sgn;
s2_exp_add <= s1_exp_add;
s2_frc_all <= s1_frc_all;
s2_zero <= s1_zero;
end if;
end process;
s2_exp <= (('0' & s2_exp_add) - "0001111111") or (s2_zero & "000000000");
s2_exp_up <= (('0' & s2_exp_add) - "0001111110") or (s2_zero & "000000000");
s2_frc <= s2_frc_all(47 downto 23);
s2_ulp <= x"00000" & "00001" when s2_frc_all(47) = '0' else x"00000" & "00010";
s2_frc_up <= s2_frc + s2_ulp;
s2_tail_any <= '0' when s2_frc_all(21 downto 0) = zero_22 else '1';
s2_round <= (s2_frc_all(22) and s2_tail_any) or (s2_frc_all(23) and s2_frc_all(22)) when s2_frc_all(47) = '0' else
(s2_frc_all(23) and (s2_frc_all(22) or s2_tail_any)) or (s2_frc_all(24) and s2_frc_all(23));
pipe2 : process(clk)
begin
if rising_edge(clk) then
s3_sgn <= s2_sgn;
s3_exp <= s2_exp;
s3_exp_up <= s2_exp_up;
s3_frc <= s2_frc;
s3_frc_up <= s2_frc_up;
s3_round <= s2_round;
end if;
end process;
s3_frc_out_tmp <= std_logic_vector(s3_frc) when s3_round = '0' else std_logic_vector(s3_frc_up);
s3_exp_out_tmp <= std_logic_vector(s3_exp) when s3_frc_out_tmp(24) = '0' else std_logic_vector(s3_exp_up);
s3_exp_out <= "00000000" when s3_exp_out_tmp(9) = '1' else
"11111111" when s3_exp_out_tmp(8) = '1' else
s3_exp_out_tmp(7 downto 0);
s3_frc_out <= (others => '0') when s3_exp_out = "00000000" or s3_exp_out = "11111111" else
s3_frc_out_tmp(22 downto 0) when s3_frc_out_tmp(24) = '0' else
s3_frc_out_tmp(23 downto 1);
flt_out <= s3_sgn & s3_exp_out & s3_frc_out;
end dataflow_pipeline;
|
-- IT Tijuana, NetList-FPGA-Optimizer 0.01 (printed on 2016-05-16.09:03:50)
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.all;
USE IEEE.NUMERIC_STD.all;
ENTITY mpegmv_hype_entity IS
PORT (
reset, clk: IN std_logic;
input1, input2, input3, input4, input5, input6, input7, input8, input9, input10, input11, input12, input13, input14: IN unsigned(0 TO 3);
output1, output2, output3: OUT unsigned(0 TO 4));
END mpegmv_hype_entity;
ARCHITECTURE mpegmv_hype_description OF mpegmv_hype_entity IS
SIGNAL current_state : unsigned(0 TO 7) := "00000000";
SHARED VARIABLE register1: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register2: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register3: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register4: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register5: unsigned(0 TO 4) := "00000";
SHARED VARIABLE register6: unsigned(0 TO 4) := "00000";
BEGIN
moore_machine: PROCESS(clk, reset)
BEGIN
IF reset = '0' THEN
current_state <= "00000000";
ELSIF clk = '1' AND clk'event THEN
IF current_state < 4 THEN
current_state <= current_state + 1;
END IF;
END IF;
END PROCESS moore_machine;
operations: PROCESS(current_state)
BEGIN
CASE current_state IS
WHEN "00000001" =>
register1 := input1 * 1;
WHEN "00000010" =>
register1 := register1 + 3;
register2 := input2 * 4;
register3 := input3 * 5;
WHEN "00000011" =>
register4 := input4 * 6;
register5 := input5 * 7;
register1 := register3 + register1;
register2 := register2 + 9;
WHEN "00000100" =>
register3 := input6 * 10;
register6 := input7 * 11;
register5 := register5 + 13;
output1 <= register4 + register2;
WHEN "00000101" =>
register2 := input8 * 15;
register4 := input9 * 16;
register3 := register3 + register5;
register1 := register6 + register1;
WHEN "00000110" =>
register4 := register4 + 18;
register5 := input10 * 19;
WHEN "00000111" =>
register2 := register2 + register4;
register4 := input11 * 20;
register1 := ((NOT register1) + 1) XOR register1;
register6 := input12 * 23;
register3 := register5 + register3;
WHEN "00001000" =>
register2 := register4 + register2;
register4 := input13 * 24;
register5 := input14 * 25;
register6 := register6 + 27;
output2 <= register1(0 TO 1) & register3(0 TO 2);
WHEN "00001001" =>
register1 := register5 + register6;
WHEN "00001010" =>
register1 := register4 + register1;
WHEN "00001011" =>
register1 := ((NOT register1) + 1) XOR register1;
WHEN "00001100" =>
output3 <= register1(0 TO 1) & register2(0 TO 2);
WHEN OTHERS =>
NULL;
END CASE;
END PROCESS operations;
END mpegmv_hype_description; |
-------------------------------------------------------
--! @author Andrew Powell
--! @date March 17, 2017
--! @brief Contains the package and component declaration of the
--! Plasma-SoC's Timer Core. Please refer to the documentation
--! in plasoc_timer.vhd for more information.
-------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
package plasoc_timer_pack is
-- Default Interrupt Controller parameters. These values are modifiable. If these parameters are
-- modified, though, modifications will also be necessary for the corresponding header file.
constant default_timer_width : integer := 32; --! Defines the width of the timer's Trigger and Tick Value registers.
constant default_timer_axi_control_offset : integer := 0; --! For the Control register, defines the default offset from the instantiation's base address
constant default_timer_axi_control_start_bit_loc : integer := 0; --! For the Start bit, defines the bit location in the Control register.
constant default_timer_axi_control_reload_bit_loc : integer := 1; --! For the Reload bit, defines the bit location in the Control register.
constant default_timer_axi_control_ack_bit_loc : integer := 2; --! For the Ack bit, defines the bit location in the Control register.
constant default_timer_axi_control_done_bit_loc : integer := 3; --! For the Done bit, defines the bit location in the Control register.
constant default_timer_axi_trig_value_offset : integer := 4; --! For the Trigger Value register, defines the default offset from the instantiation's base address.
constant default_timer_axi_tick_value_offset : integer := 8; --! For the Tick Value register, defines the default offset from the instantiation's base address.
constant axi_resp_okay : std_logic_vector := "00";
component plasoc_timer is
generic (
timer_width : integer := default_timer_width;
axi_address_width : integer := 16;
axi_data_width : integer := 32;
axi_control_offset : integer := default_timer_axi_control_offset;
axi_control_start_bit_loc : integer := default_timer_axi_control_start_bit_loc;
axi_control_reload_bit_loc : integer := default_timer_axi_control_reload_bit_loc;
axi_control_ack_bit_loc : integer := default_timer_axi_control_ack_bit_loc;
axi_control_done_bit_loc : integer := default_timer_axi_control_done_bit_loc;
axi_trig_value_offset : integer := default_timer_axi_trig_value_offset;
axi_tick_value_offset : integer := default_timer_axi_tick_value_offset);
port (
aclk : in std_logic;
aresetn : in std_logic;
axi_awaddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_awprot : in std_logic_vector(2 downto 0);
axi_awvalid : in std_logic;
axi_awready : out std_logic;
axi_wvalid : in std_logic;
axi_wready : out std_logic;
axi_wdata : in std_logic_vector(axi_data_width-1 downto 0);
axi_wstrb : in std_logic_vector(axi_data_width/8-1 downto 0);
axi_bvalid : out std_logic;
axi_bready : in std_logic;
axi_bresp : out std_logic_vector(1 downto 0);
axi_araddr : in std_logic_vector(axi_address_width-1 downto 0);
axi_arprot : in std_logic_vector(2 downto 0);
axi_arvalid : in std_logic;
axi_arready : out std_logic;
axi_rdata : out std_logic_vector(axi_data_width-1 downto 0) := (others=>'0');
axi_rvalid : out std_logic;
axi_rready : in std_logic;
axi_rresp : out std_logic_vector(1 downto 0);
done : out std_logic);
end component;
end;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC data mode EPROC_OUT2 module
entity EPROC_OUT2_HDLC is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_HDLC;
architecture Behavioral of EPROC_OUT2_HDLC is
----------------------------------
----------------------------------
component hdlc_bist_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(8 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(8 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
----------------------------------
----------------------------------
signal bit_cnt,bit_cnt_r : std_logic_vector (2 downto 0) := (others=>'1');
signal two_bit_out,EdataOUT_s : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_cnt_ena,ce,ce_r,we,re_r,oe : std_logic := '0';
signal fifo_empty_r,isflag_r : std_logic := '1';
signal bitOUTclk,rst_fall,restart,bit_stuffing_case,re,ce_1st_clk,fifo_empty,bit_out,bit_out_r,isflag : std_logic;
signal byte_out : std_logic_vector (8 downto 0);
signal dataByte : std_logic_vector (8 downto 0) := (others=>'1');
signal byte_out_r : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_out_sr : std_logic_vector (4 downto 0) := (others=>'1');
signal bit_out_sr_clk0 : std_logic_vector (4 downto 0);
signal send_out_trig : std_logic := '0';
begin
bitOUTclk <= bitCLKx2; -- 2bit output
-------------------------------------------------------------------------------------------
-- restarting data requests after reset fall
-------------------------------------------------------------------------------------------
rst_fall_pulse: entity work.pulse_fall_pw01 port map(bitOUTclk,rst,rst_fall);
restart_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>10,pw=>1) port map(bitOUTclk,rst_fall,restart);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if restart = '1' then
ce <= '1';
end if;
ce_r <= ce;
end if;
end process;
--
ce_1st_clk_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitOUTclk,ce,ce_1st_clk);
--
-------------------------------------------------------------------------------------------
-- input latching @ bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if edataINrdy = '1' then
if edataIN(9 downto 8) = "11" then -- comma ('error')
dataByte <= (others=>'1');
we <= '0';
elsif edataIN(9 downto 8) = "01" or edataIN(9 downto 8) = "10" then -- eop/sop
dataByte <= '1' & HDLC_flag;
we <= '1';
else
dataByte <= '0' & edataIN(7 downto 0);
we <= '1';
end if;
else
we <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- HDLC bit stuffing FIFO
-------------------------------------------------------------------------------------------
bit_stuffing_FIFO: hdlc_bist_fifo
port map (
rst => rst,
wr_clk => bitCLKx4,
rd_clk => bitOUTclk,
din => dataByte,
wr_en => we,
rd_en => re,
dout => byte_out,
full => open,
empty => fifo_empty
);
-------------------------------------------------------------------------------------------
-- bit counter: counting 8 bit to serialize the out while pausing for zero-bit stuffing
-------------------------------------------------------------------------------------------
bit_stuffing_case <= '1' when (bit_out_sr_clk0 = "11111" and isflag_r = '0') else '0';
bit_cnt_ena <= ce and (not bit_stuffing_case);
re <= '1' when (bit_cnt = "111" and bit_cnt_ena = '1') else '0';
getDataTrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4,re,getDataTrig);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if ce = '1' then
if bit_cnt_ena = '1' then
bit_cnt <= bit_cnt + 1;
end if;
else
bit_cnt <= (others=>'1');
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- comma selector
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
re_r <= re;
fifo_empty_r <= fifo_empty;
end if;
end process;
--
isflag <= byte_out(8); --'1' when (byte_out = HDLC_flag) else '0';
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if re_r = '1' then
if fifo_empty_r = '1' then
byte_out_r <= (others=>'1'); --error flag, not HDLC_flag!
isflag_r <= '1';
else
byte_out_r <= byte_out(7 downto 0);
isflag_r <= isflag; -- no bit stuffing if flag is sent
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- bit selector
-------------------------------------------------------------------------------------------
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
bit_cnt_r <= bit_cnt;
end if;
end process;
--
process(bit_cnt_r,byte_out_r)
begin
case (bit_cnt_r) is
when "000" => bit_out <= byte_out_r(0);
when "001" => bit_out <= byte_out_r(1);
when "010" => bit_out <= byte_out_r(2);
when "011" => bit_out <= byte_out_r(3);
when "100" => bit_out <= byte_out_r(4);
when "101" => bit_out <= byte_out_r(5);
when "110" => bit_out <= byte_out_r(6);
when "111" => bit_out <= byte_out_r(7);
when others =>
end case;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
oe <= bit_cnt_ena;
end if;
end process;
--
bit_out_r <= (bit_out and oe) or (not ce_r);
bit_out_sr_clk0 <= bit_out_r & bit_out_sr(4 downto 1);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if rst = '1' then
bit_out_sr <= (others=>'1');
else
bit_out_sr <= bit_out_r & bit_out_sr(4 downto 1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
send_out_trig <= (not send_out_trig) and ce;
end if;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '1' then
two_bit_out(1) <= bit_out_r;
else
two_bit_out(0) <= bit_out_r;
end if;
end if;
end process;
--
process(bitOUTclk,rst)
begin
if rst = '1' then
EdataOUT_s <= (others=>'1');
elsif bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '0' and ce = '1' then
EdataOUT_s <= two_bit_out;
end if;
end if;
end process;
--
EdataOUT <= EdataOUT_s;
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC data mode EPROC_OUT2 module
entity EPROC_OUT2_HDLC is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_HDLC;
architecture Behavioral of EPROC_OUT2_HDLC is
----------------------------------
----------------------------------
component hdlc_bist_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(8 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(8 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
----------------------------------
----------------------------------
signal bit_cnt,bit_cnt_r : std_logic_vector (2 downto 0) := (others=>'1');
signal two_bit_out,EdataOUT_s : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_cnt_ena,ce,ce_r,we,re_r,oe : std_logic := '0';
signal fifo_empty_r,isflag_r : std_logic := '1';
signal bitOUTclk,rst_fall,restart,bit_stuffing_case,re,ce_1st_clk,fifo_empty,bit_out,bit_out_r,isflag : std_logic;
signal byte_out : std_logic_vector (8 downto 0);
signal dataByte : std_logic_vector (8 downto 0) := (others=>'1');
signal byte_out_r : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_out_sr : std_logic_vector (4 downto 0) := (others=>'1');
signal bit_out_sr_clk0 : std_logic_vector (4 downto 0);
signal send_out_trig : std_logic := '0';
begin
bitOUTclk <= bitCLKx2; -- 2bit output
-------------------------------------------------------------------------------------------
-- restarting data requests after reset fall
-------------------------------------------------------------------------------------------
rst_fall_pulse: entity work.pulse_fall_pw01 port map(bitOUTclk,rst,rst_fall);
restart_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>10,pw=>1) port map(bitOUTclk,rst_fall,restart);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if restart = '1' then
ce <= '1';
end if;
ce_r <= ce;
end if;
end process;
--
ce_1st_clk_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitOUTclk,ce,ce_1st_clk);
--
-------------------------------------------------------------------------------------------
-- input latching @ bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if edataINrdy = '1' then
if edataIN(9 downto 8) = "11" then -- comma ('error')
dataByte <= (others=>'1');
we <= '0';
elsif edataIN(9 downto 8) = "01" or edataIN(9 downto 8) = "10" then -- eop/sop
dataByte <= '1' & HDLC_flag;
we <= '1';
else
dataByte <= '0' & edataIN(7 downto 0);
we <= '1';
end if;
else
we <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- HDLC bit stuffing FIFO
-------------------------------------------------------------------------------------------
bit_stuffing_FIFO: hdlc_bist_fifo
port map (
rst => rst,
wr_clk => bitCLKx4,
rd_clk => bitOUTclk,
din => dataByte,
wr_en => we,
rd_en => re,
dout => byte_out,
full => open,
empty => fifo_empty
);
-------------------------------------------------------------------------------------------
-- bit counter: counting 8 bit to serialize the out while pausing for zero-bit stuffing
-------------------------------------------------------------------------------------------
bit_stuffing_case <= '1' when (bit_out_sr_clk0 = "11111" and isflag_r = '0') else '0';
bit_cnt_ena <= ce and (not bit_stuffing_case);
re <= '1' when (bit_cnt = "111" and bit_cnt_ena = '1') else '0';
getDataTrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4,re,getDataTrig);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if ce = '1' then
if bit_cnt_ena = '1' then
bit_cnt <= bit_cnt + 1;
end if;
else
bit_cnt <= (others=>'1');
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- comma selector
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
re_r <= re;
fifo_empty_r <= fifo_empty;
end if;
end process;
--
isflag <= byte_out(8); --'1' when (byte_out = HDLC_flag) else '0';
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if re_r = '1' then
if fifo_empty_r = '1' then
byte_out_r <= (others=>'1'); --error flag, not HDLC_flag!
isflag_r <= '1';
else
byte_out_r <= byte_out(7 downto 0);
isflag_r <= isflag; -- no bit stuffing if flag is sent
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- bit selector
-------------------------------------------------------------------------------------------
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
bit_cnt_r <= bit_cnt;
end if;
end process;
--
process(bit_cnt_r,byte_out_r)
begin
case (bit_cnt_r) is
when "000" => bit_out <= byte_out_r(0);
when "001" => bit_out <= byte_out_r(1);
when "010" => bit_out <= byte_out_r(2);
when "011" => bit_out <= byte_out_r(3);
when "100" => bit_out <= byte_out_r(4);
when "101" => bit_out <= byte_out_r(5);
when "110" => bit_out <= byte_out_r(6);
when "111" => bit_out <= byte_out_r(7);
when others =>
end case;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
oe <= bit_cnt_ena;
end if;
end process;
--
bit_out_r <= (bit_out and oe) or (not ce_r);
bit_out_sr_clk0 <= bit_out_r & bit_out_sr(4 downto 1);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if rst = '1' then
bit_out_sr <= (others=>'1');
else
bit_out_sr <= bit_out_r & bit_out_sr(4 downto 1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
send_out_trig <= (not send_out_trig) and ce;
end if;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '1' then
two_bit_out(1) <= bit_out_r;
else
two_bit_out(0) <= bit_out_r;
end if;
end if;
end process;
--
process(bitOUTclk,rst)
begin
if rst = '1' then
EdataOUT_s <= (others=>'1');
elsif bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '0' and ce = '1' then
EdataOUT_s <= two_bit_out;
end if;
end if;
end process;
--
EdataOUT <= EdataOUT_s;
--
end Behavioral;
|
----------------------------------------------------------------------------------
--! Company: EDAQ WIS.
--! Engineer: juna
--!
--! Create Date: 24/01/2016
--! Module Name: EPROC_OUT2_HDLC
--! Project Name: FELIX
----------------------------------------------------------------------------------
--! Use standard library
library IEEE,work;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use work.centralRouter_package.all;
use work.all;
--! HDLC data mode EPROC_OUT2 module
entity EPROC_OUT2_HDLC is
port(
bitCLK : in std_logic;
bitCLKx2 : in std_logic;
bitCLKx4 : in std_logic;
rst : in std_logic;
getDataTrig : out std_logic;
edataIN : in std_logic_vector (9 downto 0);
edataINrdy : in std_logic;
EdataOUT : out std_logic_vector(1 downto 0)
);
end EPROC_OUT2_HDLC;
architecture Behavioral of EPROC_OUT2_HDLC is
----------------------------------
----------------------------------
component hdlc_bist_fifo
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(8 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
dout : out std_logic_vector(8 downto 0);
full : out std_logic;
empty : out std_logic
);
end component;
----------------------------------
----------------------------------
signal bit_cnt,bit_cnt_r : std_logic_vector (2 downto 0) := (others=>'1');
signal two_bit_out,EdataOUT_s : std_logic_vector (1 downto 0) := (others=>'1');
signal bit_cnt_ena,ce,ce_r,we,re_r,oe : std_logic := '0';
signal fifo_empty_r,isflag_r : std_logic := '1';
signal bitOUTclk,rst_fall,restart,bit_stuffing_case,re,ce_1st_clk,fifo_empty,bit_out,bit_out_r,isflag : std_logic;
signal byte_out : std_logic_vector (8 downto 0);
signal dataByte : std_logic_vector (8 downto 0) := (others=>'1');
signal byte_out_r : std_logic_vector (7 downto 0) := (others=>'1');
signal bit_out_sr : std_logic_vector (4 downto 0) := (others=>'1');
signal bit_out_sr_clk0 : std_logic_vector (4 downto 0);
signal send_out_trig : std_logic := '0';
begin
bitOUTclk <= bitCLKx2; -- 2bit output
-------------------------------------------------------------------------------------------
-- restarting data requests after reset fall
-------------------------------------------------------------------------------------------
rst_fall_pulse: entity work.pulse_fall_pw01 port map(bitOUTclk,rst,rst_fall);
restart_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>10,pw=>1) port map(bitOUTclk,rst_fall,restart);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if restart = '1' then
ce <= '1';
end if;
ce_r <= ce;
end if;
end process;
--
ce_1st_clk_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitOUTclk,ce,ce_1st_clk);
--
-------------------------------------------------------------------------------------------
-- input latching @ bitCLKx4
-------------------------------------------------------------------------------------------
process(bitCLKx4)
begin
if bitCLKx4'event and bitCLKx4 = '1' then
if edataINrdy = '1' then
if edataIN(9 downto 8) = "11" then -- comma ('error')
dataByte <= (others=>'1');
we <= '0';
elsif edataIN(9 downto 8) = "01" or edataIN(9 downto 8) = "10" then -- eop/sop
dataByte <= '1' & HDLC_flag;
we <= '1';
else
dataByte <= '0' & edataIN(7 downto 0);
we <= '1';
end if;
else
we <= '0';
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- HDLC bit stuffing FIFO
-------------------------------------------------------------------------------------------
bit_stuffing_FIFO: hdlc_bist_fifo
port map (
rst => rst,
wr_clk => bitCLKx4,
rd_clk => bitOUTclk,
din => dataByte,
wr_en => we,
rd_en => re,
dout => byte_out,
full => open,
empty => fifo_empty
);
-------------------------------------------------------------------------------------------
-- bit counter: counting 8 bit to serialize the out while pausing for zero-bit stuffing
-------------------------------------------------------------------------------------------
bit_stuffing_case <= '1' when (bit_out_sr_clk0 = "11111" and isflag_r = '0') else '0';
bit_cnt_ena <= ce and (not bit_stuffing_case);
re <= '1' when (bit_cnt = "111" and bit_cnt_ena = '1') else '0';
getDataTrig_pulse: entity work.pulse_pdxx_pwxx generic map(pd=>0,pw=>1) port map(bitCLKx4,re,getDataTrig);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if ce = '1' then
if bit_cnt_ena = '1' then
bit_cnt <= bit_cnt + 1;
end if;
else
bit_cnt <= (others=>'1');
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- comma selector
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
re_r <= re;
fifo_empty_r <= fifo_empty;
end if;
end process;
--
isflag <= byte_out(8); --'1' when (byte_out = HDLC_flag) else '0';
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if re_r = '1' then
if fifo_empty_r = '1' then
byte_out_r <= (others=>'1'); --error flag, not HDLC_flag!
isflag_r <= '1';
else
byte_out_r <= byte_out(7 downto 0);
isflag_r <= isflag; -- no bit stuffing if flag is sent
end if;
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- bit selector
-------------------------------------------------------------------------------------------
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
bit_cnt_r <= bit_cnt;
end if;
end process;
--
process(bit_cnt_r,byte_out_r)
begin
case (bit_cnt_r) is
when "000" => bit_out <= byte_out_r(0);
when "001" => bit_out <= byte_out_r(1);
when "010" => bit_out <= byte_out_r(2);
when "011" => bit_out <= byte_out_r(3);
when "100" => bit_out <= byte_out_r(4);
when "101" => bit_out <= byte_out_r(5);
when "110" => bit_out <= byte_out_r(6);
when "111" => bit_out <= byte_out_r(7);
when others =>
end case;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
oe <= bit_cnt_ena;
end if;
end process;
--
bit_out_r <= (bit_out and oe) or (not ce_r);
bit_out_sr_clk0 <= bit_out_r & bit_out_sr(4 downto 1);
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if rst = '1' then
bit_out_sr <= (others=>'1');
else
bit_out_sr <= bit_out_r & bit_out_sr(4 downto 1);
end if;
end if;
end process;
--
-------------------------------------------------------------------------------------------
-- sending out 2 bits @ bitCLK
-------------------------------------------------------------------------------------------
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
send_out_trig <= (not send_out_trig) and ce;
end if;
end process;
--
process(bitOUTclk)
begin
if bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '1' then
two_bit_out(1) <= bit_out_r;
else
two_bit_out(0) <= bit_out_r;
end if;
end if;
end process;
--
process(bitOUTclk,rst)
begin
if rst = '1' then
EdataOUT_s <= (others=>'1');
elsif bitOUTclk'event and bitOUTclk = '1' then
if send_out_trig = '0' and ce = '1' then
EdataOUT_s <= two_bit_out;
end if;
end if;
end process;
--
EdataOUT <= EdataOUT_s;
--
end Behavioral;
|
---------------------------------------------------------------------------
-- Copyright 2015 - 2017 Systems Group, ETH Zurich
--
-- This hardware module is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License as published
-- by the Free Software Foundation, either version 3 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program. If not, see <http://www.gnu.org/licenses/>.
---------------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL ;
USE IEEE.std_logic_arith.ALL;
USE IEEE.std_logic_unsigned.ALL;
entity zk_session_Packetizer is
port (
clk : in std_logic;
rst : in std_logic;
in_valid : in std_logic;
in_ready : out std_logic;
in_data : in std_logic_vector(63 downto 0);
in_meta : in std_logic_vector(63 downto 0);
in_keep : in std_logic_vector(7 downto 0);
in_last : in std_logic;
out_valid : out std_logic;
out_ready : in std_logic;
out_last : out std_logic;
out_data : out std_logic_vector(63 downto 0);
out_meta : out std_logic_vector(63 downto 0)
);
end zk_session_Packetizer;
architecture beh of zk_session_Packetizer is
signal outValid : std_logic;
signal outReady : std_logic;
signal outLast : std_logic;
signal outFirst : std_logic;
signal outLength : std_logic_vector(15 downto 0);
signal outData : std_logic_vector(63 downto 0);
signal outMeta : std_logic_vector(63 downto 0);
begin
outValid <= in_valid;
in_ready <= outReady;
outData <= in_data;
outMeta <= in_data;
outLast <= '1' when outLength=0 else '0';
get_packets: process(clk)
begin
if (clk'event and clk='1') then
if (rst='1') then
outFirst <= '1';
outLength <= (others => '0');
outLength(0) <= '1';
else
if (outValid='1' and outReady='1') then
outLength <= outLength-1;
if (outFirst='1') then
if (outData(15+32 downto 32)/=0) then
outLength <= outData(15+32 downto 32);
end if;
outFirst <= '0';
end if;
if (outLength=0) then
outFirst <= '1';
outLength <= (others => '0');
outLength(0) <= '1';
end if;
end if;
end if;
end if;
end process;
out_valid <= outValid;
outReady <= out_ready;
out_data <= outData;
out_meta <= outMeta;
out_last <= outLast;
end beh;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
library UNIMACRO;
use UNIMACRO.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
entity AddBB is
port (
CLK : in std_logic;
RST : in std_logic;
VALID_IN : in std_logic;
READY_IN : in std_logic;
LEFT : in std_logic_vector(31 downto 0);
RIGHT : in std_logic_vector(31 downto 0);
VALID_OUT : out std_logic;
READY_OUT : out std_logic;
ADD_OUT : out std_logic_vector(31 downto 0)
);
end AddBB;
architecture arch of AddBB is
signal RESULT :std_logic_vector(31 downto 0);
-- END DSP48E1_inst_1
constant DELAY_ADD_SUB : positive := 2;
--
TYPE iBus_ADD_SUB is array(DELAY_ADD_SUB-1 downto 0) of std_logic;
--
signal ValidsRegBus_ADD_SUB : iBus_ADD_SUB := (others => '0');
--
COMPONENT logic_dff_block
Port (
D : in STD_LOGIC;
CLK : in STD_LOGIC;
RST : in STD_LOGIC;
Q : out STD_LOGIC
);
END COMPONENT;
begin
ADDSUB_MACRO_inst : ADDSUB_MACRO
generic map (
DEVICE => "7SERIES", -- Target Device: "VIRTEX5", "7SERIES", "SPARTAN6"
LATENCY => 2, -- Desired clock cycle latency, 0-2
WIDTH => 32) -- Input / Output bus width, 1-48
port map (
CARRYOUT => open, -- 1-bit carry-out output signal
RESULT => RESULT, -- Add/sub result output, width defined by WIDTH generic
A => LEFT, -- Input A bus, width defined by WIDTH generic
ADD_SUB => '1', -- 1-bit add/sub input, high selects add, low selects subtract
B => RIGHT, -- Input B bus, width defined by WIDTH generic
CARRYIN => '0', -- 1-bit carry-in input
CE => '1', -- 1-bit clock enable input
CLK =>CLK, -- 1-bit clock input
RST => RST -- 1-bit active high synchronous reset
);
validReg_ADD_int: for i in 0 to DELAY_ADD_SUB generate
begin
validdffLeft_ADD: if i = 0 generate
begin
valid_dff: component logic_dff_block
port map (
D => VALID_IN,
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate validdffLeft_ADD;
--
dffOthers_ADD: if (i > 0 AND i < DELAY_ADD_SUB) generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => ValidsRegBus_ADD_SUB(i)
);
end generate dffOthers_ADD;
--
dffRight_ADD: if i = DELAY_ADD_SUB generate
begin
valid_dff: component logic_dff_block
port map (
D => ValidsRegBus_ADD_SUB(i-1),
CLK => CLK,
RST => RST,
Q => VALID_OUT
);
end generate dffRight_ADD;
end generate validReg_ADD_int;
calc_result : process(clk)
begin
if rising_edge(clk) then
ADD_OUT <= RESULT;
end if;
end process;
READY_OUT <= READY_IN;
end architecture ; -- arch |
ENTITY fullAdder IS
PORT(a : in bit;
b : in bit;
cin : in bit;
s : out bit;
cout : out bit);
BEGIN
END ENTITY fullAdder;
ARCHITECTURE ARCH OF fullAdder IS
SIGNAL axorb : bit;
BEGIN
axorb <= (a xor b);
s <= (axorb xor cin);
cout <= ((axorb and cin) or (a and b));
END ARCHITECTURE fullAdder;
ENTITY main IS
PORT(a : in ARRAY(10#7# DOWNTO 10#0#) OF BIT;
b : in ARRAY(10#7# DOWNTO 10#0#) OF BIT;
s : out ARRAY(10#7# DOWNTO 10#0#) OF BIT;
cout : out BIT);
BEGIN
END ENTITY main;
ARCHITECTURE ARCH OF main IS
SIGNAL tmp : ARRAY(10#8# DOWNTO 10#0#) OF BIT;
BEGIN
tmp(0) <= '0';
cout <= tmp(8);
G__7999 : ENTITY fullAdder(ARCH) PORT MAP(a => a(0)
, b => b(0)
, cin => tmp(0)
, s => s(0)
, cout => tmp(1)
);
G__8000 : ENTITY fullAdder(ARCH) PORT MAP(a => a(1)
, b => b(1)
, cin => tmp(1)
, s => s(1)
, cout => tmp(2)
);
G__8001 : ENTITY fullAdder(ARCH) PORT MAP(a => a(2)
, b => b(2)
, cin => tmp(2)
, s => s(2)
, cout => tmp(3)
);
G__8002 : ENTITY fullAdder(ARCH) PORT MAP(a => a(3)
, b => b(3)
, cin => tmp(3)
, s => s(3)
, cout => tmp(4)
);
G__8003 : ENTITY fullAdder(ARCH) PORT MAP(a => a(4)
, b => b(4)
, cin => tmp(4)
, s => s(4)
, cout => tmp(5)
);
G__8004 : ENTITY fullAdder(ARCH) PORT MAP(a => a(5)
, b => b(5)
, cin => tmp(5)
, s => s(5)
, cout => tmp(6)
);
G__8005 : ENTITY fullAdder(ARCH) PORT MAP(a => a(6)
, b => b(6)
, cin => tmp(6)
, s => s(6)
, cout => tmp(7)
);
G__8006 : ENTITY fullAdder(ARCH) PORT MAP(a => a(7)
, b => b(7)
, cin => tmp(7)
, s => s(7)
, cout => tmp(8)
);
END ARCHITECTURE main;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_a_e
--
-- Generated
-- by: wig
-- on: Wed Nov 30 09:22:45 2005
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_a_e-e.vhd,v 1.3 2005/11/30 14:04:02 wig Exp $
-- $Date: 2005/11/30 14:04:02 $
-- $Log: inst_a_e-e.vhd,v $
-- Revision 1.3 2005/11/30 14:04:02 wig
-- Updated testcase references
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.71 2005/11/22 11:00:47 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.42 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_a_e
--
entity inst_a_e is
-- Generics:
-- No Generated Generics for Entity inst_a_e
-- Generated Port Declaration:
port(
-- Generated Port for Entity inst_a_e
gensig_1 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_10 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_2 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_3 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_4 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_5 : out std_ulogic_vector(7 downto 0); -- Generated signals, connecting a to b
gensig_6 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_7 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_8 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
gensig_9 : in std_ulogic_vector(7 downto 0); -- Generated signals, connecting b to a
port_mac_b : in std_ulogic_vector(3 downto 0) -- Macro test 0 k1_k2
-- End of Generated Port for Entity inst_a_e
);
end inst_a_e;
--
-- End of Generated Entity inst_a_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
library verilog;
use verilog.vl_types.all;
entity EX_MEM is
port(
clock : in vl_logic;
reset : in vl_logic;
ex_alu_result : in vl_logic_vector(15 downto 0);
mem_write_en : in vl_logic;
mem_write_data : in vl_logic_vector(15 downto 0);
write_back_en : in vl_logic;
write_back_dest : in vl_logic_vector(2 downto 0);
write_back_result_mux: in vl_logic;
RegExToMemOut : out vl_logic_vector(37 downto 0)
);
end EX_MEM;
|
-- pragma translate_off
use std.textio.all;
-- pragma translate_on
package version is
constant grlib_version : integer := 1401;
-- pragma translate_off
constant grlib_date : string := "20150506";
-- pragma translate_on
constant grlib_build : integer := 4156;
end;
|
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