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library ieee;
use ieee.std_logic_1164.all;
entity MULT is
port (a,b: in std_logic_vector(3 downto 0);
s: out std_logic_vector(3 downto 0));
end MULT;
architecture arch_MULT of MULT is
function deslocar(x: std_logic_vector(3 downto 0))
return std_logic_vector is
variable y: std_logic_vector(3 downto 0);
begin
for i in 3 downto 1 loop
y(i):=x(i-1);
end loop;
y(0):='0';
return y;
end;
function somador(a: std_logic_vector(3 downto 0);
b: std_logic_vector(3 downto 0))
return std_logic_vector is
variable vaium: std_logic;
variable soma: std_logic_vector(3 downto 0);
begin
vaium:='0';
for i in 0 to 3 loop
soma(i):=a(i) xor b(i) xor vaium;
vaium:=(a(i) and b(i)) or (b(i) and Vaium) or(vaium and a(i));
end loop;
return soma;
end;
begin
process(a,b)
variable aux1: std_logic_vector(3 downto 0);
variable aux2: std_logic_vector(3 downto 0);
variable vaium: std_logic;
begin
aux1:="0000";
aux2:=a;
vaium:= '0';
for i in 0 to 3 loop
aux1:=deslocar(aux1);
vaium:=aux2(3);
if vaium='1' then
aux1:=somador(aux1,b);
end if;
aux2:=deslocar(aux2);
end loop;
s<=aux1;
end process;
end arch_MULT;
|
entity attr9 is
end entity;
architecture test of attr9 is
begin
process is
type my_small_int is range 1 to 10;
begin
assert integer'value("1") = 1;
assert natural'value(" 12_3") = 123;
assert my_small_int'value("5 ") = 5;
assert boolean'value("true") = true;
assert boolean'value("FALSE") = false;
assert character'value("'x' ") = 'x';
wait;
end process;
end architecture;
|
entity attr9 is
end entity;
architecture test of attr9 is
begin
process is
type my_small_int is range 1 to 10;
begin
assert integer'value("1") = 1;
assert natural'value(" 12_3") = 123;
assert my_small_int'value("5 ") = 5;
assert boolean'value("true") = true;
assert boolean'value("FALSE") = false;
assert character'value("'x' ") = 'x';
wait;
end process;
end architecture;
|
entity attr9 is
end entity;
architecture test of attr9 is
begin
process is
type my_small_int is range 1 to 10;
begin
assert integer'value("1") = 1;
assert natural'value(" 12_3") = 123;
assert my_small_int'value("5 ") = 5;
assert boolean'value("true") = true;
assert boolean'value("FALSE") = false;
assert character'value("'x' ") = 'x';
wait;
end process;
end architecture;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: greth_rx
-- File: greth_rx.vhd
-- Author: Marko Isomaki
-- Description: Ethernet receiver
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library grlib;
use grlib.stdlib.all;
library eth;
use eth.grethpkg.all;
entity greth_rx is
generic(
nsync : integer range 1 to 2 := 2;
rmii : integer range 0 to 1 := 0;
multicast : integer range 0 to 1 := 0;
maxsize : integer := 1500;
gmiimode : integer range 0 to 1 := 0
);
port(
rst : in std_ulogic;
clk : in std_ulogic;
rxi : in host_rx_type;
rxo : out rx_host_type
);
attribute sync_set_reset of rst : signal is "true";
end entity;
architecture rtl of greth_rx is
-- constant maxsize : integer := 1518;
constant maxsizerx : unsigned(15 downto 0) :=
to_unsigned(maxsize + 18, 16);
constant minsize : integer := 64;
--receiver types
type rx_state_type is (idle, wait_sfd, data1, data2, errorst, report_status,
wait_report, check_crc, discard_packet);
type rx_reg_type is record
er : std_ulogic;
en : std_ulogic;
rxd : std_logic_vector(3 downto 0);
rxdp : std_logic_vector(3 downto 0);
crc : std_logic_vector(31 downto 0);
sync_start : std_ulogic;
gotframe : std_ulogic;
start : std_ulogic;
write : std_ulogic;
done : std_ulogic;
odd_nibble : std_ulogic;
lentype : std_logic_vector(15 downto 0);
ltfound : std_ulogic;
byte_count : std_logic_vector(10 downto 0);
data : std_logic_vector(31 downto 0);
dataout : std_logic_vector(31 downto 0);
rx_state : rx_state_type;
status : std_logic_vector(3 downto 0);
write_ack : std_logic_vector(nsync-1 downto 0);
done_ack : std_logic_vector(nsync downto 0);
rxen : std_logic_vector(1 downto 0);
got4b : std_ulogic;
mcasthash : std_logic_vector(5 downto 0);
hashlock : std_ulogic;
--rmii
enold : std_ulogic;
act : std_ulogic;
dv : std_ulogic;
cnt : std_logic_vector(3 downto 0);
rxd2 : std_logic_vector(1 downto 0);
speed : std_logic_vector(1 downto 0);
zero : std_ulogic;
end record;
--receiver signals
signal r, rin : rx_reg_type;
signal rxrst : std_ulogic;
signal vcc : std_ulogic;
-- attribute sync_set_reset : string;
attribute sync_set_reset of rxrst : signal is "true";
begin
vcc <= '1';
rx_rst : eth_rstgen
port map(rst, clk, vcc, rxrst, open);
rx : process(rxrst, r, rxi) is
variable v : rx_reg_type;
variable index : integer range 0 to 3;
variable crc_en : std_ulogic;
variable write_req : std_ulogic;
variable write_ack : std_ulogic;
variable done_ack : std_ulogic;
variable er : std_ulogic;
variable dv : std_ulogic;
variable act : std_ulogic;
variable rxd : std_logic_vector(3 downto 0);
begin
v := r; v.rxd := rxi.rxd(3 downto 0);
if rmii = 0 then
v.en := rxi.rx_dv;
else
v.en := rxi.rx_crs;
end if;
v.er := rxi.rx_er; write_req := '0'; crc_en := '0';
index := conv_integer(r.byte_count(1 downto 0));
--synchronization
v.rxen(1) := r.rxen(0); v.rxen(0) := rxi.enable;
v.write_ack(0) := rxi.writeack;
v.done_ack(0) := rxi.doneack;
if nsync = 2 then
v.write_ack(1) := r.write_ack(0);
v.done_ack(1) := r.done_ack(0);
end if;
write_ack := not (r.write xor r.write_ack(nsync-1));
done_ack := not (r.done xor r.done_ack(nsync-1));
--rmii/mii
if rmii = 0 then
er := r.er; dv := r.en; act := r.en; rxd := r.rxd;
else
--sync
v.speed(1) := r.speed(0); v.speed(0) := rxi.speed;
rxd := r.rxd(1 downto 0) & r.rxd2;
if r.cnt = "0000" then
v.cnt := "1001";
else
v.cnt := r.cnt - 1;
end if;
if v.cnt = "0000" then
v.zero := '1';
else
v.zero := '0';
end if;
act := r.act; er := '0';
if r.speed(1) = '0' then
if r.zero = '1' then
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
if r.dv = '0' then
v.rxd2 := r.rxd(1 downto 0);
end if;
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
else
dv := '0';
end if;
else
v.enold := r.en;
dv := r.en and r.dv;
v.dv := r.act and not r.dv;
v.rxd2 := r.rxd(1 downto 0);
if (r.enold or r.en) = '0' then
v.act := '0';
end if;
end if;
end if;
if (r.en and not r.act) = '1' then
if (rxd = "0101") and (r.speed(1) or
(not r.speed(1) and r.zero)) = '1' then
v.act := '1'; v.dv := '0'; v.rxdp := rxd;
end if;
end if;
if (dv = '1') then
v.rxdp := rxd;
end if;
if multicast = 1 then
if (r.byte_count(2 downto 0) = "110") and (r.hashlock = '0') then
v.mcasthash := r.crc(5 downto 0); v.hashlock := '1';
end if;
end if;
--fsm
case r.rx_state is
when idle =>
v.gotframe := '0'; v.status := (others => '0'); v.got4b := '0';
v.byte_count := (others => '0'); v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
if (dv and r.rxen(1)) = '1' then
if (rxd = "1101") and (r.rxdp = "0101") then
v.rx_state := data1; v.sync_start := not r.sync_start;
end if;
v.start := '0'; v.crc := (others => '1');
if er = '1' then v.status(2) := '1'; end if;
elsif dv = '1' then
v.rx_state := discard_packet;
end if;
when discard_packet =>
if act = '0' then v.rx_state := idle; end if;
when data1 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data2;
case index is
when 0 => v.data(27 downto 24) := rxd;
when 1 => v.data(19 downto 16) := rxd;
when 2 => v.data(11 downto 8) := rxd;
when 3 => v.data(3 downto 0) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if (r.byte_count(1 downto 0) = "00" and (r.start and act and dv) = '1') then
write_req := '1';
end if;
if er = '1' then v.status(2) := '1'; end if;
if conv_integer(r.byte_count) > maxsizerx then
v.rx_state := errorst; v.status(1) := '1';
v.byte_count := r.byte_count - 4;
end if;
v.got4b := v.byte_count(2) or r.got4b;
when data2 =>
if (act and dv) = '1' then
crc_en := '1';
v.odd_nibble := not r.odd_nibble; v.rx_state := data1;
v.byte_count := r.byte_count + 1; v.start := '1';
case index is
when 0 => v.data(31 downto 28) := rxd;
when 1 => v.data(23 downto 20) := rxd;
when 2 => v.data(15 downto 12) := rxd;
when 3 => v.data(7 downto 4) := rxd;
end case;
elsif act = '0' then
v.rx_state := check_crc;
end if;
if er = '1' then v.status(2) := '1'; end if;
v.got4b := v.byte_count(2) or r.got4b;
when check_crc =>
if r.crc /= X"C704DD7B" then
if r.odd_nibble = '1' then v.status(0) := '1';
else v.status(2) := '1'; end if;
end if;
if write_ack = '1' then
if r.got4b = '1' then
v.byte_count := r.byte_count - 4;
else
v.byte_count := (others => '0');
end if;
v.rx_state := report_status;
if conv_integer(r.byte_count) < minsize then
v.rx_state := wait_report; v.done := not r.done;
end if;
end if;
when errorst =>
if act = '0' then
v.rx_state := wait_report; v.done := not r.done;
v.gotframe := '1';
end if;
when report_status =>
v.done := not r.done; v.rx_state := wait_report;
v.gotframe := '1';
when wait_report =>
if done_ack = '1' then
if act = '1' then
v.rx_state := discard_packet;
else
v.rx_state := idle;
end if;
end if;
when others => null;
end case;
--write to fifo
if write_req = '1' then
if (r.status(3) or not write_ack) = '1' then
v.status(3) := '1';
else
v.dataout := r.data; v.write := not r.write;
end if;
if (r.byte_count(4 downto 2) = "100") and (r.ltfound = '0') then
v.lentype := r.data(31 downto 16) + 14; v.ltfound := '1';
end if;
end if;
if write_ack = '1' then
if rxi.writeok = '0' then v.status(3) := '1'; end if;
end if;
--crc generation
if crc_en = '1' then
v.crc := calccrc(rxd, r.crc);
end if;
if rxrst = '0' then
v.rx_state := idle; v.write := '0'; v.done := '0'; v.sync_start := '0';
v.done_ack := (others => '0');
v.gotframe := '0'; v.write_ack := (others => '0');
v.dv := '0'; v.cnt := (others => '0'); v.zero := '0';
v.byte_count := (others => '0'); v.lentype := (others => '0');
v.status := (others => '0'); v.got4b := '0'; v.odd_nibble := '0';
v.ltfound := '0';
if multicast = 1 then
v.hashlock := '0';
end if;
end if;
if rmii = 0 then
v.cnt := (others => '0'); v.zero := '0';
end if;
rin <= v;
rxo.dataout <= r.dataout;
rxo.start <= r.sync_start;
rxo.done <= r.done;
rxo.write <= r.write;
rxo.status <= r.status;
rxo.gotframe <= r.gotframe;
rxo.byte_count <= r.byte_count;
rxo.lentype <= r.lentype;
rxo.mcasthash <= r.mcasthash;
end process;
gmiimode0 : if gmiimode = 0 generate
rxregs0 : process(clk) is
begin
if rising_edge(clk) then
r <= rin;
end if;
end process;
end generate;
gmiimode1 : if gmiimode = 1 generate
rxregs1 : process(clk) is
begin
if rising_edge(clk) then
if (rxi.rx_en = '1' or rxrst = '0') then r <= rin; end if;
end if;
end process;
end generate;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity carry_sel_gen is
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end carry_sel_gen;
architecture STRUCTURAL of carry_sel_gen is
component rca
generic ( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end component;
component mux21
generic (
SIZE : integer
);
Port ( IN0: In std_logic_vector(N-1 downto 0);
IN1: In std_logic_vector(N-1 downto 0);
CTRL: In std_logic;
OUT1: Out std_logic_vector(N-1 downto 0));
end component;
constant zero : std_logic := '0';
constant one : std_logic := '1';
signal nocarry_sum_to_mux : std_logic_vector(N-1 downto 0);
signal carry_sum_to_mux : std_logic_vector(N-1 downto 0);
signal carry_carry_out : std_logic;
signal nocarry_carry_out : std_logic;
begin
rca_nocarry : rca
generic map (N => N)
port map (A,B,zero,nocarry_sum_to_mux,nocarry_carry_out);
rca_carry : rca
generic map (N => N)
port map (A,B,one,carry_sum_to_mux,carry_carry_out);
outmux : mux21
generic map (SIZE => N)
port map (nocarry_sum_to_mux,carry_sum_to_mux,Ci,S);
end STRUCTURAL;
|
library ieee;
use ieee.std_logic_1164.all;
entity carry_sel_gen is
generic( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end carry_sel_gen;
architecture STRUCTURAL of carry_sel_gen is
component rca
generic ( N : integer := 4);
Port ( A: In std_logic_vector(N-1 downto 0);
B: In std_logic_vector(N-1 downto 0);
Ci: In std_logic;
S: Out std_logic_vector(N-1 downto 0);
Co: Out std_logic);
end component;
component mux21
generic (
SIZE : integer
);
Port ( IN0: In std_logic_vector(N-1 downto 0);
IN1: In std_logic_vector(N-1 downto 0);
CTRL: In std_logic;
OUT1: Out std_logic_vector(N-1 downto 0));
end component;
constant zero : std_logic := '0';
constant one : std_logic := '1';
signal nocarry_sum_to_mux : std_logic_vector(N-1 downto 0);
signal carry_sum_to_mux : std_logic_vector(N-1 downto 0);
signal carry_carry_out : std_logic;
signal nocarry_carry_out : std_logic;
begin
rca_nocarry : rca
generic map (N => N)
port map (A,B,zero,nocarry_sum_to_mux,nocarry_carry_out);
rca_carry : rca
generic map (N => N)
port map (A,B,one,carry_sum_to_mux,carry_carry_out);
outmux : mux21
generic map (SIZE => N)
port map (nocarry_sum_to_mux,carry_sum_to_mux,Ci,S);
end STRUCTURAL;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc773.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p09n01i00773ent_a IS
port ( c1 : buffer integer ;
c2 : in integer );
END c01s01b01x02p09n01i00773ent_a;
ARCHITECTURE c01s01b01x02p09n01i00773arch_a OF c01s01b01x02p09n01i00773ent_a IS
BEGIN
c1 <= c2;
END c01s01b01x02p09n01i00773arch_a;
ENTITY c01s01b01x02p09n01i00773ent IS
port ( p1 : out integer ;
p2 : in integer );
END c01s01b01x02p09n01i00773ent;
ARCHITECTURE c01s01b01x02p09n01i00773arch OF c01s01b01x02p09n01i00773ent IS
component c01s01b01x02p09n01i00773ent_b
port ( c1 : buffer integer ;
c2 : in integer );
end component;
for L : c01s01b01x02p09n01i00773ent_b use entity work.c01s01b01x02p09n01i00773ent_a(c01s01b01x02p09n01i00773arch_a);
BEGIN
L : c01s01b01x02p09n01i00773ent_b port map (p1, p2);
--Failure here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x02p09n01i00773 - An actual of mode out cannot be associated with a formal port of mode buffer."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p09n01i00773arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc773.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p09n01i00773ent_a IS
port ( c1 : buffer integer ;
c2 : in integer );
END c01s01b01x02p09n01i00773ent_a;
ARCHITECTURE c01s01b01x02p09n01i00773arch_a OF c01s01b01x02p09n01i00773ent_a IS
BEGIN
c1 <= c2;
END c01s01b01x02p09n01i00773arch_a;
ENTITY c01s01b01x02p09n01i00773ent IS
port ( p1 : out integer ;
p2 : in integer );
END c01s01b01x02p09n01i00773ent;
ARCHITECTURE c01s01b01x02p09n01i00773arch OF c01s01b01x02p09n01i00773ent IS
component c01s01b01x02p09n01i00773ent_b
port ( c1 : buffer integer ;
c2 : in integer );
end component;
for L : c01s01b01x02p09n01i00773ent_b use entity work.c01s01b01x02p09n01i00773ent_a(c01s01b01x02p09n01i00773arch_a);
BEGIN
L : c01s01b01x02p09n01i00773ent_b port map (p1, p2);
--Failure here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x02p09n01i00773 - An actual of mode out cannot be associated with a formal port of mode buffer."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p09n01i00773arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc773.vhd,v 1.2 2001-10-26 16:30:27 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c01s01b01x02p09n01i00773ent_a IS
port ( c1 : buffer integer ;
c2 : in integer );
END c01s01b01x02p09n01i00773ent_a;
ARCHITECTURE c01s01b01x02p09n01i00773arch_a OF c01s01b01x02p09n01i00773ent_a IS
BEGIN
c1 <= c2;
END c01s01b01x02p09n01i00773arch_a;
ENTITY c01s01b01x02p09n01i00773ent IS
port ( p1 : out integer ;
p2 : in integer );
END c01s01b01x02p09n01i00773ent;
ARCHITECTURE c01s01b01x02p09n01i00773arch OF c01s01b01x02p09n01i00773ent IS
component c01s01b01x02p09n01i00773ent_b
port ( c1 : buffer integer ;
c2 : in integer );
end component;
for L : c01s01b01x02p09n01i00773ent_b use entity work.c01s01b01x02p09n01i00773ent_a(c01s01b01x02p09n01i00773arch_a);
BEGIN
L : c01s01b01x02p09n01i00773ent_b port map (p1, p2);
--Failure here
TESTING: PROCESS
BEGIN
assert FALSE
report "***FAILED TEST: c01s01b01x02p09n01i00773 - An actual of mode out cannot be associated with a formal port of mode buffer."
severity ERROR;
wait;
END PROCESS TESTING;
END c01s01b01x02p09n01i00773arch;
|
-- megafunction wizard: %LPM_COUNTER%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_counter
-- ============================================================
-- File Name: clockbuzzer.vhd
-- Megafunction Name(s):
-- lpm_counter
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY clockbuzzer IS
PORT
(
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END clockbuzzer;
ARCHITECTURE SYN OF clockbuzzer IS
SIGNAL sub_wire0 : STD_LOGIC ;
SIGNAL sub_wire1 : STD_LOGIC_VECTOR (29 DOWNTO 0);
COMPONENT lpm_counter
GENERIC (
lpm_direction : STRING;
lpm_modulus : NATURAL;
lpm_port_updown : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
cout : OUT STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (29 DOWNTO 0)
);
END COMPONENT;
BEGIN
cout <= sub_wire0;
q <= sub_wire1(29 DOWNTO 0);
lpm_counter_component : lpm_counter
GENERIC MAP (
lpm_direction => "UP",
lpm_modulus => 25000,
lpm_port_updown => "PORT_UNUSED",
lpm_type => "LPM_COUNTER",
lpm_width => 30
)
PORT MAP (
clock => clock,
cout => sub_wire0,
q => sub_wire1
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CNT_EN NUMERIC "0"
-- Retrieval info: PRIVATE: CarryIn NUMERIC "0"
-- Retrieval info: PRIVATE: CarryOut NUMERIC "1"
-- Retrieval info: PRIVATE: Direction NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
-- Retrieval info: PRIVATE: ModulusCounter NUMERIC "1"
-- Retrieval info: PRIVATE: ModulusValue NUMERIC "25000"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "30"
-- Retrieval info: CONSTANT: LPM_DIRECTION STRING "UP"
-- Retrieval info: CONSTANT: LPM_MODULUS NUMERIC "25000"
-- Retrieval info: CONSTANT: LPM_PORT_UPDOWN STRING "PORT_UNUSED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_COUNTER"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "30"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: cout 0 0 0 0 OUTPUT NODEFVAL cout
-- Retrieval info: USED_PORT: q 0 0 30 0 OUTPUT NODEFVAL q[29..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 30 0 @q 0 0 30 0
-- Retrieval info: CONNECT: cout 0 0 0 0 @cout 0 0 0 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL clockbuzzer_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: lpm
|
------------------------------------------------------------------------------------------------------------------------
-- n sychronizer of the async fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the n sychronizer.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj add an additional sync stage
-- 2011-11-25 V0.03 mairt omitted reset out
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer_g is
generic(N: natural);
port(
clk, reset: in std_logic;
in_async: in std_logic_vector(N-1 downto 0);
out_sync: out std_logic_vector(N-1 downto 0)
);
end synchronizer_g;
architecture two_ff_arch of synchronizer_g is
signal meta_reg, sync_reg, sync_reg1 : std_logic_vector(N-1 downto 0) := (others => '0');
signal meta_next, sync_next, sync_next1 : std_logic_vector(N-1 downto 0) := (others => '0');
begin
-- two registers
process(clk)--,reset)
begin
-- if (reset='1') then
-- meta_reg <= (others=>'0');
-- sync_reg <= (others=>'0');
-- sync_reg1 <= (others => '0');
if (clk'event and clk='1') then
meta_reg <= meta_next;
sync_reg <= sync_next;
sync_reg1 <= sync_next1;
end if;
end process;
-- next-state logic
meta_next <= in_async;
sync_next <= meta_reg;
sync_next1 <= sync_reg;
-- output
out_sync <= sync_reg1;
end two_ff_arch; |
------------------------------------------------------------------------------------------------------------------------
-- n sychronizer of the async fifo
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: A general implementation of a asynchronous fifo which is
-- using a dual port ram. This file is the n sychronizer.
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2011-09-22 V0.01 mairt first version
-- 2011-10-14 V0.02 zelenkaj add an additional sync stage
-- 2011-11-25 V0.03 mairt omitted reset out
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
entity synchronizer_g is
generic(N: natural);
port(
clk, reset: in std_logic;
in_async: in std_logic_vector(N-1 downto 0);
out_sync: out std_logic_vector(N-1 downto 0)
);
end synchronizer_g;
architecture two_ff_arch of synchronizer_g is
signal meta_reg, sync_reg, sync_reg1 : std_logic_vector(N-1 downto 0) := (others => '0');
signal meta_next, sync_next, sync_next1 : std_logic_vector(N-1 downto 0) := (others => '0');
begin
-- two registers
process(clk)--,reset)
begin
-- if (reset='1') then
-- meta_reg <= (others=>'0');
-- sync_reg <= (others=>'0');
-- sync_reg1 <= (others => '0');
if (clk'event and clk='1') then
meta_reg <= meta_next;
sync_reg <= sync_next;
sync_reg1 <= sync_next1;
end if;
end process;
-- next-state logic
meta_next <= in_async;
sync_next <= meta_reg;
sync_next1 <= sync_reg;
-- output
out_sync <= sync_reg1;
end two_ff_arch; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc926.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p23n01i00926ent IS
END c10s03b00x00p23n01i00926ent;
ARCHITECTURE c10s03b00x00p23n01i00926arch OF c10s03b00x00p23n01i00926ent IS
type std_logic is ( 'X', '0', '1', 'W', 'L', 'H', 'Z' );
type std_logic_vector is array ( natural range <> ) of std_logic;
function "+" ( l,r : bit_vector ) return bit_vector is
variable lr : bit_vector ( 1 to l'length ) := l;
variable rr : bit_vector ( 1 to r'length ) := r;
variable result : bit_vector ( 1 to l'length );
variable carry : bit := '0';
begin
for i in l'length downto 1 loop
result(i) := lr(i) xor rr(i) xor carry;
carry := (lr(i) and rr(i)) or
(rr(i) and carry) or
(lr(i) and carry);
end loop;
return (result);
end;
-- homograph
function "+" ( l,r : std_logic_vector ) return std_logic_vector is
begin
end;
signal a : bit_vector ( 15 downto 0 ) := B"0010001010100010";
signal b : bit_vector ( 15 downto 0 ) := B"0101111101011101";
signal s : bit_vector ( 15 downto 0 );
BEGIN
TESTING: PROCESS
BEGIN
s <= (a + b) after 10 ns;
wait for 11 ns;
assert NOT( s = B"1000000111111111" )
report "***PASSED TEST: c10s03b00x00p23n01i00926"
severity NOTE;
assert ( s = B"1000000111111111" )
report "***FAILED TEST: c10s03b00x00p23n01i00926 - If one of the two declarations is the implicit declaration of a predefined operation, the predefined operation is laways hidden by teh other homograph."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p23n01i00926arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc926.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p23n01i00926ent IS
END c10s03b00x00p23n01i00926ent;
ARCHITECTURE c10s03b00x00p23n01i00926arch OF c10s03b00x00p23n01i00926ent IS
type std_logic is ( 'X', '0', '1', 'W', 'L', 'H', 'Z' );
type std_logic_vector is array ( natural range <> ) of std_logic;
function "+" ( l,r : bit_vector ) return bit_vector is
variable lr : bit_vector ( 1 to l'length ) := l;
variable rr : bit_vector ( 1 to r'length ) := r;
variable result : bit_vector ( 1 to l'length );
variable carry : bit := '0';
begin
for i in l'length downto 1 loop
result(i) := lr(i) xor rr(i) xor carry;
carry := (lr(i) and rr(i)) or
(rr(i) and carry) or
(lr(i) and carry);
end loop;
return (result);
end;
-- homograph
function "+" ( l,r : std_logic_vector ) return std_logic_vector is
begin
end;
signal a : bit_vector ( 15 downto 0 ) := B"0010001010100010";
signal b : bit_vector ( 15 downto 0 ) := B"0101111101011101";
signal s : bit_vector ( 15 downto 0 );
BEGIN
TESTING: PROCESS
BEGIN
s <= (a + b) after 10 ns;
wait for 11 ns;
assert NOT( s = B"1000000111111111" )
report "***PASSED TEST: c10s03b00x00p23n01i00926"
severity NOTE;
assert ( s = B"1000000111111111" )
report "***FAILED TEST: c10s03b00x00p23n01i00926 - If one of the two declarations is the implicit declaration of a predefined operation, the predefined operation is laways hidden by teh other homograph."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p23n01i00926arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc926.vhd,v 1.2 2001-10-26 16:30:02 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c10s03b00x00p23n01i00926ent IS
END c10s03b00x00p23n01i00926ent;
ARCHITECTURE c10s03b00x00p23n01i00926arch OF c10s03b00x00p23n01i00926ent IS
type std_logic is ( 'X', '0', '1', 'W', 'L', 'H', 'Z' );
type std_logic_vector is array ( natural range <> ) of std_logic;
function "+" ( l,r : bit_vector ) return bit_vector is
variable lr : bit_vector ( 1 to l'length ) := l;
variable rr : bit_vector ( 1 to r'length ) := r;
variable result : bit_vector ( 1 to l'length );
variable carry : bit := '0';
begin
for i in l'length downto 1 loop
result(i) := lr(i) xor rr(i) xor carry;
carry := (lr(i) and rr(i)) or
(rr(i) and carry) or
(lr(i) and carry);
end loop;
return (result);
end;
-- homograph
function "+" ( l,r : std_logic_vector ) return std_logic_vector is
begin
end;
signal a : bit_vector ( 15 downto 0 ) := B"0010001010100010";
signal b : bit_vector ( 15 downto 0 ) := B"0101111101011101";
signal s : bit_vector ( 15 downto 0 );
BEGIN
TESTING: PROCESS
BEGIN
s <= (a + b) after 10 ns;
wait for 11 ns;
assert NOT( s = B"1000000111111111" )
report "***PASSED TEST: c10s03b00x00p23n01i00926"
severity NOTE;
assert ( s = B"1000000111111111" )
report "***FAILED TEST: c10s03b00x00p23n01i00926 - If one of the two declarations is the implicit declaration of a predefined operation, the predefined operation is laways hidden by teh other homograph."
severity ERROR;
wait;
END PROCESS TESTING;
END c10s03b00x00p23n01i00926arch;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use STD.textio.all; -- to read files
use work.lz4_pkg.all;
-- Test bench has no ports
entity lz4_tb is
end lz4_tb;
architecture behavior of lz4_tb is
signal clk_i : std_logic := '0';
signal reset_i : std_logic := '0';
signal entryStream_s : std_logic := '0';
signal outputStream_s : std_logic := '0';
signal outputFlag_s : std_logic := '0';
begin
uut: lz4_top port map (
clk_i => clk_i,
reset_i => reset_i,
entryStream_i => entryStream_s,
outputStream_o => outputStream_s,
outputFlag_o => outputFlag_s
);
-- Clock process definitions
clk_i_process: process
begin
clk_i <= '0';
wait for clk_period/2;
clk_i <= '1';
wait for clk_period/2;
end process;
reset_process: process
begin
reset_i <= '1';
wait for 72 ns;
reset_i <= '0';
wait;
end process;
readfile_process: process
file file_pointer_i : text;
variable r_char : character;
variable line_num_i : line;
variable line_content_i : character;
begin
wait for 5 ns;
if reset_i = '0' then
file_open(file_pointer_i, "./test-bench/test.txt.bit", READ_MODE);
while not endfile(file_pointer_i) loop
readline(file_pointer_i, line_num_i);
read(line_num_i, line_content_i);
r_char := line_content_i;
if (r_char = '0') then
entryStream_s <= '0';
elsif (r_char = '1') then
entryStream_s <= '1';
end if;
wait for 5 ns; -- wait between each value reading
end loop;
file_close(file_pointer_i);
-- send undefined values to mark the eof
for i in 0 to 7 loop
entryStream_s <= 'U';
end loop;
wait;
end if;
end process;
writefile_process: process
file file_pointer_o: text;
variable line_content_o : string(1 to 8000) := (others => '0');
variable line_num_o : line;
begin
file_open(file_pointer_o, "./test-bench/test.lz4", WRITE_MODE);
wait until (outputFlag_s = '1');
while (outputFlag_s = '1') loop
if rising_edge(clk_i) then
for i in 0 to 7999 loop
if (outputStream_s = '1') then
line_content_o(8000-i) := '1';
else
line_content_o(8000-i) := '0';
end if;
end loop;
end if;
end loop;
write(line_num_o, line_content_o);
writeline(file_pointer_o, line_num_o);
wait for 10 ns;
file_close(file_pointer_o);
wait;
end process;
dummy_test: process
begin
assert false report "end of tests" severity note;
wait; -- the final infinit loop
end process;
end;
|
------------------------------------------------------------------------------
-- Company: CPE233
-- Engineer: Jacob Hladky
------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity rat_wrapper is
Port( switches : in STD_LOGIC_VECTOR(7 downto 0);
buttons : in STD_LOGIC_VECTOR(2 downto 0);
rx : in STD_LOGIC;
tx : out STD_LOGIC;
hs : out STD_LOGIC;
vs : out STD_LOGIC;
rout : out STD_LOGIC_VECTOR(2 downto 0);
gout : out STD_LOGIC_VECTOR(2 downto 0);
bout : out STD_LOGIC_VECTOR(1 downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
sel : out STD_LOGIC_VECTOR(3 downto 0);
seg : out STD_LOGIC_VECTOR(7 downto 0);
leds : out STD_LOGIC_VECTOR(7 downto 0));
end rat_wrapper;
architecture rat_wrapper_a of rat_wrapper is
-- Declare RAT_CPU and I/O components ----------------------------------------
component rat_cpu
Port( in_port : in STD_LOGIC_VECTOR(7 downto 0);
rst : in STD_LOGIC;
int_in, clk : in STD_LOGIC;
out_port : out STD_LOGIC_VECTOR(7 downto 0);
port_id : out STD_LOGIC_VECTOR(7 downto 0);
io_oe : out STD_LOGIC);
end component;
component inputs is
Port( input_port : out STD_LOGIC_VECTOR(7 downto 0);
clk : in STD_LOGIC;
buttons : in STD_LOGIC_VECTOR(2 downto 0);
switches : in STD_LOGIC_VECTOR(7 downto 0);
uart_in : in STD_LOGIC_VECTOR(7 downto 0);
vga_in : in STD_LOGIC_VECTOR(7 downto 0);
port_id : in STD_LOGIC_VECTOR(7 downto 0));
end component;
component outputs is
Port( leds, seg : out STD_LOGIC_VECTOR(7 downto 0);
sel : out STD_LOGIC_VECTOR(3 downto 0);
uart_out : out STD_LOGIC_VECTOR(7 downto 0);
vga_we : out STD_LOGIC;
vga_wa : out STD_LOGIC_VECTOR(10 downto 0);
vga_wd : out STD_LOGIC_VECTOR(7 downto 0);
port_id : in STD_LOGIC_VECTOR(7 downto 0);
output_port : in STD_LOGIC_VECTOR(7 downto 0);
io_oe, clk : in STD_LOGIC);
end component;
component uart_wrapper is
Port( tx : out STD_LOGIC;
rx : in STD_LOGIC;
clk, rst : in STD_LOGIC;
int : out STD_LOGIC;
data_out : out STD_LOGIC_VECTOR(7 downto 0);
data_in : in STD_LOGIC_VECTOR(7 downto 0)); -- data going INTO the UART
end component;
component vgaDriverBuffer is
Port( clk, we : in STD_LOGIC;
wa : in STD_LOGIC_VECTOR(10 downto 0);
wd : in STD_LOGIC_VECTOR(7 downto 0);
rout, gout : out STD_LOGIC_VECTOR(2 downto 0);
bout : out STD_LOGIC_VECTOR(1 downto 0);
hs, vs : out STD_LOGIC;
pixelData : out STD_LOGIC_VECTOR(7 downto 0));
end component;
-- Signals for connecting RAT_CPU to RAT_wrapper -----------------------------
signal in_port_i : std_logic_vector(7 downto 0);
signal out_port_i : std_logic_vector(7 downto 0);
signal uart_in_i : std_logic_vector(7 downto 0);
signal uart_out_i : std_logic_vector(7 downto 0);
signal port_id_i : std_logic_vector(7 downto 0);
signal io_oe_i : std_logic;
signal int_i : std_logic;
signal wa_i : std_logic_vector(10 downto 0);
signal wd_i : std_logic_vector(7 downto 0);
signal we_i : std_logic;
signal pixel_data_i : std_logic_vector(7 downto 0);
begin
-- Instantiate RAT_CPU --------------------------------------------------------
rat_cpu1 : rat_cpu port map(
in_port => in_port_i,
out_port => out_port_i,
port_id => port_id_i,
rst => rst,
io_oe => io_oe_i,
int_in => int_i,
clk => clk);
-- Instantiate Inputs --------------------------------------------------------
inputs1 : inputs port map(
input_port => in_port_i,
clk => clk,
buttons => buttons,
switches => switches,
uart_in => uart_in_i,
vga_in => pixel_data_i,
port_id => port_id_i);
-- Instantiate Outputs --------------------------------------------------------
outputs1 : outputs port map(
leds => leds,
seg => seg,
sel => sel,
uart_out => uart_out_i,
vga_wa => wa_i,
vga_wd => wd_i,
vga_we => we_i,
port_id => port_id_i,
output_port => out_port_i,
io_oe => io_oe_i,
clk => clk);
-- Instantiate UART -----------------------------------------------------------
uart_wrapper1 : uart_wrapper port map(
tx => tx,
rx => rx,
clk => clk,
rst => rst,
int => int_i,
data_in => uart_out_i, -- data going OUT OF The board
data_out => uart_in_i); -- data going INTO the board
-- Instantiate VGA ------------------------------------------------------------
vga1 : vgaDriverBuffer port map(
clk => clk,
we => we_i,
wa => wa_i,
wd => wd_i,
rout => rout,
gout => gout,
bout => bout,
hs => hs,
vs => vs,
pixeldata => pixel_data_i);
end rat_wrapper_a; |
architecture RTL of FIFO is
attribute coordinate of comp_1:component is (0.0, 17.5);
ATTRIBUTE COORDINATE OF comp_1:component is (0.0, 17.5);
begin
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_174 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_174;
architecture augh of cmp_174 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
entity cmp_174 is
port (
eq : out std_logic;
in0 : in std_logic_vector(2 downto 0);
in1 : in std_logic_vector(2 downto 0)
);
end cmp_174;
architecture augh of cmp_174 is
signal tmp : std_logic;
begin
-- Compute the result
tmp <=
'0' when in0 /= in1 else
'1';
-- Set the outputs
eq <= tmp;
end architecture;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
|
-- (c) Copyright 1995-2017 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:user:ov7670_controller:1.0
-- IP Revision: 3
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY system_ov7670_controller_0_0 IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END system_ov7670_controller_0_0;
ARCHITECTURE system_ov7670_controller_0_0_arch OF system_ov7670_controller_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : STRING;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF system_ov7670_controller_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT ov7670_controller IS
PORT (
clk : IN STD_LOGIC;
resend : IN STD_LOGIC;
config_finished : OUT STD_LOGIC;
sioc : OUT STD_LOGIC;
siod : INOUT STD_LOGIC;
reset : OUT STD_LOGIC;
pwdn : OUT STD_LOGIC;
xclk : OUT STD_LOGIC
);
END COMPONENT ov7670_controller;
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF clk: SIGNAL IS "xilinx.com:signal:clock:1.0 clk CLK";
ATTRIBUTE X_INTERFACE_INFO OF reset: SIGNAL IS "xilinx.com:signal:reset:1.0 reset RST";
BEGIN
U0 : ov7670_controller
PORT MAP (
clk => clk,
resend => resend,
config_finished => config_finished,
sioc => sioc,
siod => siod,
reset => reset,
pwdn => pwdn,
xclk => xclk
);
END system_ov7670_controller_0_0_arch;
|
architecture RTL of FIFO is
constant C_WIDTH : integer := 16;
constant C_DEPTH : integer := 512;
constant C_WORD : integer := 1024;
begin
end architecture RTL;
|
-- generated with romgen v3.0.1r4 by MikeJ truhy and eD
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.Vcomponents.all;
entity e000 is
port (
CLK : in std_logic;
ADDR : in std_logic_vector(11 downto 0);
DATA : out std_logic_vector(7 downto 0)
);
end;
architecture RTL of e000 is
signal rom_addr : std_logic_vector(11 downto 0);
begin
p_addr : process(ADDR)
begin
rom_addr <= (others => '0');
rom_addr(11 downto 0) <= ADDR;
end process;
p_rom : process
begin
wait until rising_edge(CLK);
DATA <= (others => '0');
case rom_addr is
when x"000" => DATA <= x"2C";
when x"001" => DATA <= x"01";
when x"002" => DATA <= x"B0";
when x"003" => DATA <= x"70";
when x"004" => DATA <= x"03";
when x"005" => DATA <= x"4C";
when x"006" => DATA <= x"B2";
when x"007" => DATA <= x"C2";
when x"008" => DATA <= x"98";
when x"009" => DATA <= x"48";
when x"00A" => DATA <= x"8A";
when x"00B" => DATA <= x"48";
when x"00C" => DATA <= x"A2";
when x"00D" => DATA <= x"00";
when x"00E" => DATA <= x"8E";
when x"00F" => DATA <= x"CA";
when x"010" => DATA <= x"03";
when x"011" => DATA <= x"A9";
when x"012" => DATA <= x"2B";
when x"013" => DATA <= x"8D";
when x"014" => DATA <= x"0B";
when x"015" => DATA <= x"80";
when x"016" => DATA <= x"BD";
when x"017" => DATA <= x"8A";
when x"018" => DATA <= x"EB";
when x"019" => DATA <= x"29";
when x"01A" => DATA <= x"BF";
when x"01B" => DATA <= x"9D";
when x"01C" => DATA <= x"0D";
when x"01D" => DATA <= x"80";
when x"01E" => DATA <= x"E8";
when x"01F" => DATA <= x"C9";
when x"020" => DATA <= x"20";
when x"021" => DATA <= x"D0";
when x"022" => DATA <= x"F3";
when x"023" => DATA <= x"20";
when x"024" => DATA <= x"D6";
when x"025" => DATA <= x"E7";
when x"026" => DATA <= x"2C";
when x"027" => DATA <= x"01";
when x"028" => DATA <= x"B0";
when x"029" => DATA <= x"30";
when x"02A" => DATA <= x"0A";
when x"02B" => DATA <= x"A9";
when x"02C" => DATA <= x"3C";
when x"02D" => DATA <= x"8D";
when x"02E" => DATA <= x"0A";
when x"02F" => DATA <= x"02";
when x"030" => DATA <= x"A9";
when x"031" => DATA <= x"E0";
when x"032" => DATA <= x"8D";
when x"033" => DATA <= x"0B";
when x"034" => DATA <= x"02";
when x"035" => DATA <= x"68";
when x"036" => DATA <= x"AA";
when x"037" => DATA <= x"68";
when x"038" => DATA <= x"A8";
when x"039" => DATA <= x"4C";
when x"03A" => DATA <= x"B2";
when x"03B" => DATA <= x"C2";
when x"03C" => DATA <= x"08";
when x"03D" => DATA <= x"D8";
when x"03E" => DATA <= x"86";
when x"03F" => DATA <= x"E4";
when x"040" => DATA <= x"84";
when x"041" => DATA <= x"E5";
when x"042" => DATA <= x"AE";
when x"043" => DATA <= x"CA";
when x"044" => DATA <= x"03";
when x"045" => DATA <= x"BD";
when x"046" => DATA <= x"66";
when x"047" => DATA <= x"E0";
when x"048" => DATA <= x"C9";
when x"049" => DATA <= x"0D";
when x"04A" => DATA <= x"F0";
when x"04B" => DATA <= x"0A";
when x"04C" => DATA <= x"E8";
when x"04D" => DATA <= x"8E";
when x"04E" => DATA <= x"CA";
when x"04F" => DATA <= x"03";
when x"050" => DATA <= x"A6";
when x"051" => DATA <= x"E4";
when x"052" => DATA <= x"A4";
when x"053" => DATA <= x"E5";
when x"054" => DATA <= x"28";
when x"055" => DATA <= x"60";
when x"056" => DATA <= x"A9";
when x"057" => DATA <= x"94";
when x"058" => DATA <= x"8D";
when x"059" => DATA <= x"0A";
when x"05A" => DATA <= x"02";
when x"05B" => DATA <= x"A9";
when x"05C" => DATA <= x"FE";
when x"05D" => DATA <= x"8D";
when x"05E" => DATA <= x"0B";
when x"05F" => DATA <= x"02";
when x"060" => DATA <= x"A9";
when x"061" => DATA <= x"0D";
when x"062" => DATA <= x"48";
when x"063" => DATA <= x"4C";
when x"064" => DATA <= x"5C";
when x"065" => DATA <= x"FE";
when x"066" => DATA <= x"2A";
when x"067" => DATA <= x"4D";
when x"068" => DATA <= x"45";
when x"069" => DATA <= x"4E";
when x"06A" => DATA <= x"55";
when x"06B" => DATA <= x"0D";
when x"06C" => DATA <= x"00";
when x"06D" => DATA <= x"6C";
when x"06E" => DATA <= x"52";
when x"06F" => DATA <= x"00";
when x"070" => DATA <= x"A2";
when x"071" => DATA <= x"FF";
when x"072" => DATA <= x"D8";
when x"073" => DATA <= x"A0";
when x"074" => DATA <= x"00";
when x"075" => DATA <= x"20";
when x"076" => DATA <= x"76";
when x"077" => DATA <= x"F8";
when x"078" => DATA <= x"88";
when x"079" => DATA <= x"C8";
when x"07A" => DATA <= x"E8";
when x"07B" => DATA <= x"BD";
when x"07C" => DATA <= x"CD";
when x"07D" => DATA <= x"E0";
when x"07E" => DATA <= x"30";
when x"07F" => DATA <= x"18";
when x"080" => DATA <= x"D9";
when x"081" => DATA <= x"00";
when x"082" => DATA <= x"01";
when x"083" => DATA <= x"F0";
when x"084" => DATA <= x"F4";
when x"085" => DATA <= x"CA";
when x"086" => DATA <= x"E8";
when x"087" => DATA <= x"BD";
when x"088" => DATA <= x"CD";
when x"089" => DATA <= x"E0";
when x"08A" => DATA <= x"10";
when x"08B" => DATA <= x"FA";
when x"08C" => DATA <= x"E8";
when x"08D" => DATA <= x"B9";
when x"08E" => DATA <= x"00";
when x"08F" => DATA <= x"01";
when x"090" => DATA <= x"C9";
when x"091" => DATA <= x"2E";
when x"092" => DATA <= x"D0";
when x"093" => DATA <= x"DF";
when x"094" => DATA <= x"C8";
when x"095" => DATA <= x"CA";
when x"096" => DATA <= x"B0";
when x"097" => DATA <= x"E3";
when x"098" => DATA <= x"84";
when x"099" => DATA <= x"9A";
when x"09A" => DATA <= x"A4";
when x"09B" => DATA <= x"03";
when x"09C" => DATA <= x"84";
when x"09D" => DATA <= x"D5";
when x"09E" => DATA <= x"A4";
when x"09F" => DATA <= x"05";
when x"0A0" => DATA <= x"84";
when x"0A1" => DATA <= x"D6";
when x"0A2" => DATA <= x"A4";
when x"0A3" => DATA <= x"06";
when x"0A4" => DATA <= x"84";
when x"0A5" => DATA <= x"D7";
when x"0A6" => DATA <= x"A0";
when x"0A7" => DATA <= x"00";
when x"0A8" => DATA <= x"84";
when x"0A9" => DATA <= x"05";
when x"0AA" => DATA <= x"A0";
when x"0AB" => DATA <= x"01";
when x"0AC" => DATA <= x"84";
when x"0AD" => DATA <= x"06";
when x"0AE" => DATA <= x"A4";
when x"0AF" => DATA <= x"9A";
when x"0B0" => DATA <= x"84";
when x"0B1" => DATA <= x"03";
when x"0B2" => DATA <= x"85";
when x"0B3" => DATA <= x"53";
when x"0B4" => DATA <= x"BD";
when x"0B5" => DATA <= x"CE";
when x"0B6" => DATA <= x"E0";
when x"0B7" => DATA <= x"85";
when x"0B8" => DATA <= x"52";
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when x"2CB" => DATA <= x"7B";
when x"2CC" => DATA <= x"EC";
when x"2CD" => DATA <= x"4C";
when x"2CE" => DATA <= x"56";
when x"2CF" => DATA <= x"E3";
when x"2D0" => DATA <= x"20";
when x"2D1" => DATA <= x"D1";
when x"2D2" => DATA <= x"F7";
when x"2D3" => DATA <= x"50";
when x"2D4" => DATA <= x"52";
when x"2D5" => DATA <= x"4F";
when x"2D6" => DATA <= x"54";
when x"2D7" => DATA <= x"3F";
when x"2D8" => DATA <= x"EA";
when x"2D9" => DATA <= x"00";
when x"2DA" => DATA <= x"20";
when x"2DB" => DATA <= x"E0";
when x"2DC" => DATA <= x"E2";
when x"2DD" => DATA <= x"4C";
when x"2DE" => DATA <= x"2D";
when x"2DF" => DATA <= x"EC";
when x"2E0" => DATA <= x"20";
when x"2E1" => DATA <= x"76";
when x"2E2" => DATA <= x"F8";
when x"2E3" => DATA <= x"C9";
when x"2E4" => DATA <= x"0D";
when x"2E5" => DATA <= x"F0";
when x"2E6" => DATA <= x"0D";
when x"2E7" => DATA <= x"20";
when x"2E8" => DATA <= x"3E";
when x"2E9" => DATA <= x"ED";
when x"2EA" => DATA <= x"45";
when x"2EB" => DATA <= x"EE";
when x"2EC" => DATA <= x"C9";
when x"2ED" => DATA <= x"80";
when x"2EE" => DATA <= x"F0";
when x"2EF" => DATA <= x"04";
when x"2F0" => DATA <= x"45";
when x"2F1" => DATA <= x"EE";
when x"2F2" => DATA <= x"85";
when x"2F3" => DATA <= x"EE";
when x"2F4" => DATA <= x"60";
when x"2F5" => DATA <= x"20";
when x"2F6" => DATA <= x"E4";
when x"2F7" => DATA <= x"ED";
when x"2F8" => DATA <= x"4C";
when x"2F9" => DATA <= x"FE";
when x"2FA" => DATA <= x"E6";
when x"2FB" => DATA <= x"20";
when x"2FC" => DATA <= x"2D";
when x"2FD" => DATA <= x"EC";
when x"2FE" => DATA <= x"A0";
when x"2FF" => DATA <= x"00";
when x"300" => DATA <= x"84";
when x"301" => DATA <= x"9A";
when x"302" => DATA <= x"20";
when x"303" => DATA <= x"FE";
when x"304" => DATA <= x"E6";
when x"305" => DATA <= x"A4";
when x"306" => DATA <= x"9A";
when x"307" => DATA <= x"20";
when x"308" => DATA <= x"0C";
when x"309" => DATA <= x"EE";
when x"30A" => DATA <= x"84";
when x"30B" => DATA <= x"9A";
when x"30C" => DATA <= x"CC";
when x"30D" => DATA <= x"05";
when x"30E" => DATA <= x"21";
when x"30F" => DATA <= x"D0";
when x"310" => DATA <= x"F1";
when x"311" => DATA <= x"60";
when x"312" => DATA <= x"20";
when x"313" => DATA <= x"63";
when x"314" => DATA <= x"E7";
when x"315" => DATA <= x"A2";
when x"316" => DATA <= x"9C";
when x"317" => DATA <= x"20";
when x"318" => DATA <= x"93";
when x"319" => DATA <= x"F8";
when x"31A" => DATA <= x"F0";
when x"31B" => DATA <= x"04";
when x"31C" => DATA <= x"A9";
when x"31D" => DATA <= x"FF";
when x"31E" => DATA <= x"85";
when x"31F" => DATA <= x"9E";
when x"320" => DATA <= x"A2";
when x"321" => DATA <= x"9A";
when x"322" => DATA <= x"18";
when x"323" => DATA <= x"6C";
when x"324" => DATA <= x"0C";
when x"325" => DATA <= x"02";
when x"326" => DATA <= x"20";
when x"327" => DATA <= x"E7";
when x"328" => DATA <= x"ED";
when x"329" => DATA <= x"A2";
when x"32A" => DATA <= x"00";
when x"32B" => DATA <= x"A5";
when x"32C" => DATA <= x"9E";
when x"32D" => DATA <= x"10";
when x"32E" => DATA <= x"04";
when x"32F" => DATA <= x"A2";
when x"330" => DATA <= x"02";
when x"331" => DATA <= x"C8";
when x"332" => DATA <= x"C8";
when x"333" => DATA <= x"B9";
when x"334" => DATA <= x"08";
when x"335" => DATA <= x"21";
when x"336" => DATA <= x"95";
when x"337" => DATA <= x"9C";
when x"338" => DATA <= x"C8";
when x"339" => DATA <= x"E8";
when x"33A" => DATA <= x"E0";
when x"33B" => DATA <= x"08";
when x"33C" => DATA <= x"D0";
when x"33D" => DATA <= x"F5";
when x"33E" => DATA <= x"A5";
when x"33F" => DATA <= x"9C";
when x"340" => DATA <= x"85";
when x"341" => DATA <= x"F9";
when x"342" => DATA <= x"A5";
when x"343" => DATA <= x"9D";
when x"344" => DATA <= x"85";
when x"345" => DATA <= x"FA";
when x"346" => DATA <= x"A5";
when x"347" => DATA <= x"A0";
when x"348" => DATA <= x"85";
when x"349" => DATA <= x"FB";
when x"34A" => DATA <= x"A5";
when x"34B" => DATA <= x"A1";
when x"34C" => DATA <= x"85";
when x"34D" => DATA <= x"FC";
when x"34E" => DATA <= x"20";
when x"34F" => DATA <= x"5B";
when x"350" => DATA <= x"E3";
when x"351" => DATA <= x"A4";
when x"352" => DATA <= x"9A";
when x"353" => DATA <= x"20";
when x"354" => DATA <= x"FA";
when x"355" => DATA <= x"E6";
when x"356" => DATA <= x"A5";
when x"357" => DATA <= x"AD";
when x"358" => DATA <= x"85";
when x"359" => DATA <= x"AC";
when x"35A" => DATA <= x"60";
when x"35B" => DATA <= x"20";
when x"35C" => DATA <= x"8B";
when x"35D" => DATA <= x"EC";
when x"35E" => DATA <= x"24";
when x"35F" => DATA <= x"FD";
when x"360" => DATA <= x"30";
when x"361" => DATA <= x"03";
when x"362" => DATA <= x"4C";
when x"363" => DATA <= x"70";
when x"364" => DATA <= x"E3";
when x"365" => DATA <= x"20";
when x"366" => DATA <= x"9F";
when x"367" => DATA <= x"EE";
when x"368" => DATA <= x"20";
when x"369" => DATA <= x"B4";
when x"36A" => DATA <= x"E3";
when x"36B" => DATA <= x"A2";
when x"36C" => DATA <= x"01";
when x"36D" => DATA <= x"4C";
when x"36E" => DATA <= x"75";
when x"36F" => DATA <= x"E3";
when x"370" => DATA <= x"20";
when x"371" => DATA <= x"9F";
when x"372" => DATA <= x"EE";
when x"373" => DATA <= x"A2";
when x"374" => DATA <= x"02";
when x"375" => DATA <= x"A0";
when x"376" => DATA <= x"00";
when x"377" => DATA <= x"20";
when x"378" => DATA <= x"FB";
when x"379" => DATA <= x"EF";
when x"37A" => DATA <= x"91";
when x"37B" => DATA <= x"F9";
when x"37C" => DATA <= x"A5";
when x"37D" => DATA <= x"FB";
when x"37E" => DATA <= x"D0";
when x"37F" => DATA <= x"02";
when x"380" => DATA <= x"C6";
when x"381" => DATA <= x"FC";
when x"382" => DATA <= x"C6";
when x"383" => DATA <= x"FB";
when x"384" => DATA <= x"A5";
when x"385" => DATA <= x"FB";
when x"386" => DATA <= x"05";
when x"387" => DATA <= x"FC";
when x"388" => DATA <= x"F0";
when x"389" => DATA <= x"18";
when x"38A" => DATA <= x"C8";
when x"38B" => DATA <= x"D0";
when x"38C" => DATA <= x"EA";
when x"38D" => DATA <= x"E6";
when x"38E" => DATA <= x"FA";
when x"38F" => DATA <= x"CA";
when x"390" => DATA <= x"D0";
when x"391" => DATA <= x"E3";
when x"392" => DATA <= x"20";
when x"393" => DATA <= x"AE";
when x"394" => DATA <= x"EE";
when x"395" => DATA <= x"E6";
when x"396" => DATA <= x"84";
when x"397" => DATA <= x"D0";
when x"398" => DATA <= x"06";
when x"399" => DATA <= x"E6";
when x"39A" => DATA <= x"85";
when x"39B" => DATA <= x"D0";
when x"39C" => DATA <= x"02";
when x"39D" => DATA <= x"E6";
when x"39E" => DATA <= x"86";
when x"39F" => DATA <= x"4C";
when x"3A0" => DATA <= x"70";
when x"3A1" => DATA <= x"E3";
when x"3A2" => DATA <= x"C0";
when x"3A3" => DATA <= x"00";
when x"3A4" => DATA <= x"F0";
when x"3A5" => DATA <= x"04";
when x"3A6" => DATA <= x"20";
when x"3A7" => DATA <= x"B6";
when x"3A8" => DATA <= x"E3";
when x"3A9" => DATA <= x"CA";
when x"3AA" => DATA <= x"E0";
when x"3AB" => DATA <= x"00";
when x"3AC" => DATA <= x"F0";
when x"3AD" => DATA <= x"03";
when x"3AE" => DATA <= x"20";
when x"3AF" => DATA <= x"B4";
when x"3B0" => DATA <= x"E3";
when x"3B1" => DATA <= x"4C";
when x"3B2" => DATA <= x"AE";
when x"3B3" => DATA <= x"EE";
when x"3B4" => DATA <= x"A0";
when x"3B5" => DATA <= x"00";
when x"3B6" => DATA <= x"20";
when x"3B7" => DATA <= x"FB";
when x"3B8" => DATA <= x"EF";
when x"3B9" => DATA <= x"C8";
when x"3BA" => DATA <= x"D0";
when x"3BB" => DATA <= x"FA";
when x"3BC" => DATA <= x"60";
when x"3BD" => DATA <= x"38";
when x"3BE" => DATA <= x"4C";
when x"3BF" => DATA <= x"F2";
when x"3C0" => DATA <= x"E5";
when x"3C1" => DATA <= x"A2";
when x"3C2" => DATA <= x"00";
when x"3C3" => DATA <= x"20";
when x"3C4" => DATA <= x"F0";
when x"3C5" => DATA <= x"ED";
when x"3C6" => DATA <= x"86";
when x"3C7" => DATA <= x"EF";
when x"3C8" => DATA <= x"4C";
when x"3C9" => DATA <= x"56";
when x"3CA" => DATA <= x"E3";
when x"3CB" => DATA <= x"A2";
when x"3CC" => DATA <= x"FF";
when x"3CD" => DATA <= x"4C";
when x"3CE" => DATA <= x"C3";
when x"3CF" => DATA <= x"E3";
when x"3D0" => DATA <= x"20";
when x"3D1" => DATA <= x"12";
when x"3D2" => DATA <= x"E3";
when x"3D3" => DATA <= x"A4";
when x"3D4" => DATA <= x"03";
when x"3D5" => DATA <= x"20";
when x"3D6" => DATA <= x"51";
when x"3D7" => DATA <= x"E6";
when x"3D8" => DATA <= x"6C";
when x"3D9" => DATA <= x"9E";
when x"3DA" => DATA <= x"00";
when x"3DB" => DATA <= x"20";
when x"3DC" => DATA <= x"63";
when x"3DD" => DATA <= x"E7";
when x"3DE" => DATA <= x"A2";
when x"3DF" => DATA <= x"9C";
when x"3E0" => DATA <= x"20";
when x"3E1" => DATA <= x"65";
when x"3E2" => DATA <= x"FA";
when x"3E3" => DATA <= x"A2";
when x"3E4" => DATA <= x"A2";
when x"3E5" => DATA <= x"20";
when x"3E6" => DATA <= x"65";
when x"3E7" => DATA <= x"FA";
when x"3E8" => DATA <= x"A2";
when x"3E9" => DATA <= x"9E";
when x"3EA" => DATA <= x"20";
when x"3EB" => DATA <= x"93";
when x"3EC" => DATA <= x"F8";
when x"3ED" => DATA <= x"08";
when x"3EE" => DATA <= x"A5";
when x"3EF" => DATA <= x"9C";
when x"3F0" => DATA <= x"A6";
when x"3F1" => DATA <= x"9D";
when x"3F2" => DATA <= x"28";
when x"3F3" => DATA <= x"D0";
when x"3F4" => DATA <= x"04";
when x"3F5" => DATA <= x"85";
when x"3F6" => DATA <= x"9E";
when x"3F7" => DATA <= x"86";
when x"3F8" => DATA <= x"9F";
when x"3F9" => DATA <= x"85";
when x"3FA" => DATA <= x"A0";
when x"3FB" => DATA <= x"86";
when x"3FC" => DATA <= x"A1";
when x"3FD" => DATA <= x"84";
when x"3FE" => DATA <= x"03";
when x"3FF" => DATA <= x"20";
when x"400" => DATA <= x"76";
when x"401" => DATA <= x"FA";
when x"402" => DATA <= x"A2";
when x"403" => DATA <= x"9A";
when x"404" => DATA <= x"18";
when x"405" => DATA <= x"6C";
when x"406" => DATA <= x"0E";
when x"407" => DATA <= x"02";
when x"408" => DATA <= x"20";
when x"409" => DATA <= x"91";
when x"40A" => DATA <= x"E6";
when x"40B" => DATA <= x"20";
when x"40C" => DATA <= x"2D";
when x"40D" => DATA <= x"EC";
when x"40E" => DATA <= x"20";
when x"40F" => DATA <= x"63";
when x"410" => DATA <= x"E6";
when x"411" => DATA <= x"20";
when x"412" => DATA <= x"CB";
when x"413" => DATA <= x"E6";
when x"414" => DATA <= x"90";
when x"415" => DATA <= x"03";
when x"416" => DATA <= x"20";
when x"417" => DATA <= x"AD";
when x"418" => DATA <= x"E7";
when x"419" => DATA <= x"A5";
when x"41A" => DATA <= x"A0";
when x"41B" => DATA <= x"48";
when x"41C" => DATA <= x"A5";
when x"41D" => DATA <= x"A1";
when x"41E" => DATA <= x"48";
when x"41F" => DATA <= x"38";
when x"420" => DATA <= x"A5";
when x"421" => DATA <= x"A2";
when x"422" => DATA <= x"E5";
when x"423" => DATA <= x"A0";
when x"424" => DATA <= x"85";
when x"425" => DATA <= x"A0";
when x"426" => DATA <= x"A5";
when x"427" => DATA <= x"A3";
when x"428" => DATA <= x"E5";
when x"429" => DATA <= x"A1";
when x"42A" => DATA <= x"85";
when x"42B" => DATA <= x"A1";
when x"42C" => DATA <= x"A9";
when x"42D" => DATA <= x"00";
when x"42E" => DATA <= x"85";
when x"42F" => DATA <= x"A2";
when x"430" => DATA <= x"A9";
when x"431" => DATA <= x"02";
when x"432" => DATA <= x"85";
when x"433" => DATA <= x"A3";
when x"434" => DATA <= x"AC";
when x"435" => DATA <= x"05";
when x"436" => DATA <= x"21";
when x"437" => DATA <= x"F0";
when x"438" => DATA <= x"44";
when x"439" => DATA <= x"C0";
when x"43A" => DATA <= x"F8";
when x"43B" => DATA <= x"90";
when x"43C" => DATA <= x"09";
when x"43D" => DATA <= x"20";
when x"43E" => DATA <= x"D1";
when x"43F" => DATA <= x"F7";
when x"440" => DATA <= x"46";
when x"441" => DATA <= x"55";
when x"442" => DATA <= x"4C";
when x"443" => DATA <= x"4C";
when x"444" => DATA <= x"EA";
when x"445" => DATA <= x"00";
when x"446" => DATA <= x"20";
when x"447" => DATA <= x"DF";
when x"448" => DATA <= x"E4";
when x"449" => DATA <= x"4C";
when x"44A" => DATA <= x"52";
when x"44B" => DATA <= x"E4";
when x"44C" => DATA <= x"20";
when x"44D" => DATA <= x"15";
when x"44E" => DATA <= x"EE";
when x"44F" => DATA <= x"20";
when x"450" => DATA <= x"C0";
when x"451" => DATA <= x"E4";
when x"452" => DATA <= x"98";
when x"453" => DATA <= x"F0";
when x"454" => DATA <= x"02";
when x"455" => DATA <= x"90";
when x"456" => DATA <= x"F5";
when x"457" => DATA <= x"B0";
when x"458" => DATA <= x"0C";
when x"459" => DATA <= x"20";
when x"45A" => DATA <= x"D1";
when x"45B" => DATA <= x"F7";
when x"45C" => DATA <= x"4E";
when x"45D" => DATA <= x"4F";
when x"45E" => DATA <= x"20";
when x"45F" => DATA <= x"52";
when x"460" => DATA <= x"4F";
when x"461" => DATA <= x"4F";
when x"462" => DATA <= x"4D";
when x"463" => DATA <= x"EA";
when x"464" => DATA <= x"00";
when x"465" => DATA <= x"84";
when x"466" => DATA <= x"EA";
when x"467" => DATA <= x"AC";
when x"468" => DATA <= x"05";
when x"469" => DATA <= x"21";
when x"46A" => DATA <= x"C4";
when x"46B" => DATA <= x"EA";
when x"46C" => DATA <= x"F0";
when x"46D" => DATA <= x"0F";
when x"46E" => DATA <= x"B9";
when x"46F" => DATA <= x"07";
when x"470" => DATA <= x"20";
when x"471" => DATA <= x"99";
when x"472" => DATA <= x"0F";
when x"473" => DATA <= x"20";
when x"474" => DATA <= x"B9";
when x"475" => DATA <= x"07";
when x"476" => DATA <= x"21";
when x"477" => DATA <= x"99";
when x"478" => DATA <= x"0F";
when x"479" => DATA <= x"21";
when x"47A" => DATA <= x"88";
when x"47B" => DATA <= x"B0";
when x"47C" => DATA <= x"ED";
when x"47D" => DATA <= x"A2";
when x"47E" => DATA <= x"00";
when x"47F" => DATA <= x"B5";
when x"480" => DATA <= x"A5";
when x"481" => DATA <= x"99";
when x"482" => DATA <= x"08";
when x"483" => DATA <= x"20";
when x"484" => DATA <= x"C8";
when x"485" => DATA <= x"E8";
when x"486" => DATA <= x"E0";
when x"487" => DATA <= x"08";
when x"488" => DATA <= x"D0";
when x"489" => DATA <= x"F5";
when x"48A" => DATA <= x"B5";
when x"48B" => DATA <= x"9B";
when x"48C" => DATA <= x"88";
when x"48D" => DATA <= x"99";
when x"48E" => DATA <= x"08";
when x"48F" => DATA <= x"21";
when x"490" => DATA <= x"CA";
when x"491" => DATA <= x"D0";
when x"492" => DATA <= x"F7";
when x"493" => DATA <= x"20";
when x"494" => DATA <= x"FA";
when x"495" => DATA <= x"E6";
when x"496" => DATA <= x"68";
when x"497" => DATA <= x"85";
when x"498" => DATA <= x"9D";
when x"499" => DATA <= x"68";
when x"49A" => DATA <= x"85";
when x"49B" => DATA <= x"9C";
when x"49C" => DATA <= x"AC";
when x"49D" => DATA <= x"05";
when x"49E" => DATA <= x"21";
when x"49F" => DATA <= x"20";
when x"4A0" => DATA <= x"0C";
when x"4A1" => DATA <= x"EE";
when x"4A2" => DATA <= x"8C";
when x"4A3" => DATA <= x"05";
when x"4A4" => DATA <= x"21";
when x"4A5" => DATA <= x"20";
when x"4A6" => DATA <= x"7B";
when x"4A7" => DATA <= x"EC";
when x"4A8" => DATA <= x"A5";
when x"4A9" => DATA <= x"9C";
when x"4AA" => DATA <= x"85";
when x"4AB" => DATA <= x"F9";
when x"4AC" => DATA <= x"A5";
when x"4AD" => DATA <= x"9D";
when x"4AE" => DATA <= x"85";
when x"4AF" => DATA <= x"FA";
when x"4B0" => DATA <= x"A5";
when x"4B1" => DATA <= x"A1";
when x"4B2" => DATA <= x"85";
when x"4B3" => DATA <= x"FB";
when x"4B4" => DATA <= x"A5";
when x"4B5" => DATA <= x"A0";
when x"4B6" => DATA <= x"F0";
when x"4B7" => DATA <= x"02";
when x"4B8" => DATA <= x"E6";
when x"4B9" => DATA <= x"FB";
when x"4BA" => DATA <= x"20";
when x"4BB" => DATA <= x"F9";
when x"4BC" => DATA <= x"E4";
when x"4BD" => DATA <= x"4C";
when x"4BE" => DATA <= x"56";
when x"4BF" => DATA <= x"E3";
when x"4C0" => DATA <= x"B9";
when x"4C1" => DATA <= x"0E";
when x"4C2" => DATA <= x"21";
when x"4C3" => DATA <= x"20";
when x"4C4" => DATA <= x"1F";
when x"4C5" => DATA <= x"EE";
when x"4C6" => DATA <= x"85";
when x"4C7" => DATA <= x"A2";
when x"4C8" => DATA <= x"18";
when x"4C9" => DATA <= x"A9";
when x"4CA" => DATA <= x"FF";
when x"4CB" => DATA <= x"79";
when x"4CC" => DATA <= x"0C";
when x"4CD" => DATA <= x"21";
when x"4CE" => DATA <= x"B9";
when x"4CF" => DATA <= x"0F";
when x"4D0" => DATA <= x"21";
when x"4D1" => DATA <= x"79";
when x"4D2" => DATA <= x"0D";
when x"4D3" => DATA <= x"21";
when x"4D4" => DATA <= x"85";
when x"4D5" => DATA <= x"A3";
when x"4D6" => DATA <= x"B9";
when x"4D7" => DATA <= x"0E";
when x"4D8" => DATA <= x"21";
when x"4D9" => DATA <= x"29";
when x"4DA" => DATA <= x"0F";
when x"4DB" => DATA <= x"65";
when x"4DC" => DATA <= x"A2";
when x"4DD" => DATA <= x"85";
when x"4DE" => DATA <= x"A2";
when x"4DF" => DATA <= x"38";
when x"4E0" => DATA <= x"B9";
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when x"4E2" => DATA <= x"21";
when x"4E3" => DATA <= x"E5";
when x"4E4" => DATA <= x"A3";
when x"4E5" => DATA <= x"48";
when x"4E6" => DATA <= x"B9";
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when x"4E8" => DATA <= x"21";
when x"4E9" => DATA <= x"29";
when x"4EA" => DATA <= x"0F";
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when x"4EF" => DATA <= x"00";
when x"4F0" => DATA <= x"C5";
when x"4F1" => DATA <= x"A0";
when x"4F2" => DATA <= x"68";
when x"4F3" => DATA <= x"E5";
when x"4F4" => DATA <= x"A1";
when x"4F5" => DATA <= x"8A";
when x"4F6" => DATA <= x"E9";
when x"4F7" => DATA <= x"00";
when x"4F8" => DATA <= x"60";
when x"4F9" => DATA <= x"20";
when x"4FA" => DATA <= x"8B";
when x"4FB" => DATA <= x"EC";
when x"4FC" => DATA <= x"24";
when x"4FD" => DATA <= x"FD";
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when x"4FF" => DATA <= x"03";
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when x"501" => DATA <= x"16";
when x"502" => DATA <= x"E5";
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when x"504" => DATA <= x"52";
when x"505" => DATA <= x"E5";
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when x"507" => DATA <= x"FA";
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when x"509" => DATA <= x"B7";
when x"50A" => DATA <= x"EE";
when x"50B" => DATA <= x"20";
when x"50C" => DATA <= x"6E";
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when x"50F" => DATA <= x"65";
when x"510" => DATA <= x"E5";
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when x"512" => DATA <= x"01";
when x"513" => DATA <= x"4C";
when x"514" => DATA <= x"27";
when x"515" => DATA <= x"E5";
when x"516" => DATA <= x"A5";
when x"517" => DATA <= x"FB";
when x"518" => DATA <= x"C9";
when x"519" => DATA <= x"01";
when x"51A" => DATA <= x"D0";
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when x"51C" => DATA <= x"20";
when x"51D" => DATA <= x"52";
when x"51E" => DATA <= x"E5";
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when x"520" => DATA <= x"65";
when x"521" => DATA <= x"E5";
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when x"523" => DATA <= x"B7";
when x"524" => DATA <= x"EE";
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when x"526" => DATA <= x"02";
when x"527" => DATA <= x"20";
when x"528" => DATA <= x"6E";
when x"529" => DATA <= x"E5";
when x"52A" => DATA <= x"E6";
when x"52B" => DATA <= x"FA";
when x"52C" => DATA <= x"C6";
when x"52D" => DATA <= x"FB";
when x"52E" => DATA <= x"F0";
when x"52F" => DATA <= x"13";
when x"530" => DATA <= x"CA";
when x"531" => DATA <= x"D0";
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when x"533" => DATA <= x"20";
when x"534" => DATA <= x"D7";
when x"535" => DATA <= x"EE";
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when x"537" => DATA <= x"84";
when x"538" => DATA <= x"D0";
when x"539" => DATA <= x"06";
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when x"53B" => DATA <= x"85";
when x"53C" => DATA <= x"D0";
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when x"540" => DATA <= x"4C";
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when x"542" => DATA <= x"E5";
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when x"545" => DATA <= x"D0";
when x"546" => DATA <= x"08";
when x"547" => DATA <= x"20";
when x"548" => DATA <= x"EF";
when x"549" => DATA <= x"EB";
when x"54A" => DATA <= x"E6";
when x"54B" => DATA <= x"FA";
when x"54C" => DATA <= x"20";
when x"54D" => DATA <= x"6E";
when x"54E" => DATA <= x"E5";
when x"54F" => DATA <= x"4C";
when x"550" => DATA <= x"D7";
when x"551" => DATA <= x"EE";
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when x"553" => DATA <= x"48";
when x"554" => DATA <= x"A5";
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when x"556" => DATA <= x"85";
when x"557" => DATA <= x"FE";
when x"558" => DATA <= x"A5";
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when x"55A" => DATA <= x"85";
when x"55B" => DATA <= x"FF";
when x"55C" => DATA <= x"20";
when x"55D" => DATA <= x"EF";
when x"55E" => DATA <= x"EB";
when x"55F" => DATA <= x"20";
when x"560" => DATA <= x"71";
when x"561" => DATA <= x"EE";
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when x"563" => DATA <= x"AA";
when x"564" => DATA <= x"60";
when x"565" => DATA <= x"A5";
when x"566" => DATA <= x"FF";
when x"567" => DATA <= x"85";
when x"568" => DATA <= x"FA";
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when x"56B" => DATA <= x"85";
when x"56C" => DATA <= x"F9";
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when x"56E" => DATA <= x"A0";
when x"56F" => DATA <= x"00";
when x"570" => DATA <= x"B1";
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when x"572" => DATA <= x"20";
when x"573" => DATA <= x"FD";
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when x"575" => DATA <= x"C8";
when x"576" => DATA <= x"D0";
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when x"578" => DATA <= x"60";
when x"579" => DATA <= x"A4";
when x"57A" => DATA <= x"03";
when x"57B" => DATA <= x"C8";
when x"57C" => DATA <= x"20";
when x"57D" => DATA <= x"76";
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when x"57F" => DATA <= x"B9";
when x"580" => DATA <= x"FF";
when x"581" => DATA <= x"00";
when x"582" => DATA <= x"85";
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when x"584" => DATA <= x"85";
when x"585" => DATA <= x"AD";
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when x"587" => DATA <= x"20";
when x"588" => DATA <= x"63";
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when x"58B" => DATA <= x"2D";
when x"58C" => DATA <= x"EC";
when x"58D" => DATA <= x"A2";
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when x"58F" => DATA <= x"E8";
when x"590" => DATA <= x"BD";
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when x"592" => DATA <= x"01";
when x"593" => DATA <= x"C9";
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when x"595" => DATA <= x"D0";
when x"596" => DATA <= x"F8";
when x"597" => DATA <= x"E0";
when x"598" => DATA <= x"0E";
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when x"59A" => DATA <= x"03";
when x"59B" => DATA <= x"4C";
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when x"59F" => DATA <= x"D1";
when x"5A0" => DATA <= x"F7";
when x"5A1" => DATA <= x"4E";
when x"5A2" => DATA <= x"41";
when x"5A3" => DATA <= x"4D";
when x"5A4" => DATA <= x"45";
when x"5A5" => DATA <= x"3F";
when x"5A6" => DATA <= x"EA";
when x"5A7" => DATA <= x"00";
when x"5A8" => DATA <= x"A5";
when x"5A9" => DATA <= x"EE";
when x"5AA" => DATA <= x"20";
when x"5AB" => DATA <= x"AA";
when x"5AC" => DATA <= x"ED";
when x"5AD" => DATA <= x"20";
when x"5AE" => DATA <= x"16";
when x"5AF" => DATA <= x"EC";
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when x"5B1" => DATA <= x"63";
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when x"5B3" => DATA <= x"A0";
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when x"5B5" => DATA <= x"B9";
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when x"5B7" => DATA <= x"01";
when x"5B8" => DATA <= x"C9";
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when x"5BB" => DATA <= x"13";
when x"5BC" => DATA <= x"91";
when x"5BD" => DATA <= x"87";
when x"5BE" => DATA <= x"C0";
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when x"5C0" => DATA <= x"B0";
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when x"5C2" => DATA <= x"99";
when x"5C3" => DATA <= x"00";
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when x"5C5" => DATA <= x"4C";
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when x"5C7" => DATA <= x"E5";
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when x"5C9" => DATA <= x"F8";
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when x"5CB" => DATA <= x"C8";
when x"5CC" => DATA <= x"4C";
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when x"5CF" => DATA <= x"C0";
when x"5D0" => DATA <= x"0D";
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when x"5D2" => DATA <= x"15";
when x"5D3" => DATA <= x"A9";
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when x"5D5" => DATA <= x"91";
when x"5D6" => DATA <= x"87";
when x"5D7" => DATA <= x"C0";
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when x"5D9" => DATA <= x"B0";
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when x"5DC" => DATA <= x"00";
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when x"5E0" => DATA <= x"E5";
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when x"5E2" => DATA <= x"F8";
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when x"5E4" => DATA <= x"C8";
when x"5E5" => DATA <= x"4C";
when x"5E6" => DATA <= x"CF";
when x"5E7" => DATA <= x"E5";
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when x"5E9" => DATA <= x"26";
when x"5EA" => DATA <= x"EC";
when x"5EB" => DATA <= x"20";
when x"5EC" => DATA <= x"7B";
when x"5ED" => DATA <= x"EC";
when x"5EE" => DATA <= x"4C";
when x"5EF" => DATA <= x"E0";
when x"5F0" => DATA <= x"EB";
when x"5F1" => DATA <= x"18";
when x"5F2" => DATA <= x"08";
when x"5F3" => DATA <= x"20";
when x"5F4" => DATA <= x"63";
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when x"5F7" => DATA <= x"91";
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when x"5FA" => DATA <= x"BC";
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when x"5FC" => DATA <= x"20";
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when x"5FE" => DATA <= x"E6";
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when x"600" => DATA <= x"AC";
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when x"602" => DATA <= x"28";
when x"603" => DATA <= x"6A";
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when x"60A" => DATA <= x"20";
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when x"60F" => DATA <= x"E3";
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when x"620" => DATA <= x"20";
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when x"630" => DATA <= x"F9";
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when x"635" => DATA <= x"A5";
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when x"638" => DATA <= x"C8";
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when x"63C" => DATA <= x"AC";
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when x"640" => DATA <= x"EE";
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when x"648" => DATA <= x"85";
when x"649" => DATA <= x"EE";
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when x"64C" => DATA <= x"85";
when x"64D" => DATA <= x"AC";
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when x"650" => DATA <= x"00";
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when x"657" => DATA <= x"00";
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when x"659" => DATA <= x"9D";
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when x"65B" => DATA <= x"01";
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when x"65F" => DATA <= x"0D";
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when x"661" => DATA <= x"F4";
when x"662" => DATA <= x"60";
when x"663" => DATA <= x"A5";
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when x"665" => DATA <= x"4C";
when x"666" => DATA <= x"7E";
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when x"668" => DATA <= x"A0";
when x"669" => DATA <= x"0F";
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when x"66C" => DATA <= x"C9";
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when x"66E" => DATA <= x"D0";
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when x"670" => DATA <= x"20";
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when x"673" => DATA <= x"4E";
when x"674" => DATA <= x"4F";
when x"675" => DATA <= x"54";
when x"676" => DATA <= x"20";
when x"677" => DATA <= x"56";
when x"678" => DATA <= x"41";
when x"679" => DATA <= x"4C";
when x"67A" => DATA <= x"49";
when x"67B" => DATA <= x"44";
when x"67C" => DATA <= x"EA";
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when x"67E" => DATA <= x"C9";
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when x"680" => DATA <= x"D0";
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when x"682" => DATA <= x"20";
when x"683" => DATA <= x"D1";
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when x"685" => DATA <= x"44";
when x"686" => DATA <= x"49";
when x"687" => DATA <= x"53";
when x"688" => DATA <= x"4B";
when x"689" => DATA <= x"20";
when x"68A" => DATA <= x"50";
when x"68B" => DATA <= x"52";
when x"68C" => DATA <= x"4F";
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when x"68E" => DATA <= x"EA";
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when x"690" => DATA <= x"60";
when x"691" => DATA <= x"A0";
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when x"696" => DATA <= x"9A";
when x"697" => DATA <= x"00";
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when x"699" => DATA <= x"C8";
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when x"69C" => DATA <= x"90";
when x"69D" => DATA <= x"F5";
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when x"69F" => DATA <= x"20";
when x"6A0" => DATA <= x"A0";
when x"6A1" => DATA <= x"06";
when x"6A2" => DATA <= x"99";
when x"6A3" => DATA <= x"A5";
when x"6A4" => DATA <= x"00";
when x"6A5" => DATA <= x"88";
when x"6A6" => DATA <= x"10";
when x"6A7" => DATA <= x"FA";
when x"6A8" => DATA <= x"C8";
when x"6A9" => DATA <= x"B1";
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when x"6AB" => DATA <= x"C9";
when x"6AC" => DATA <= x"0D";
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when x"6AE" => DATA <= x"09";
when x"6AF" => DATA <= x"C0";
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when x"6B1" => DATA <= x"B0";
when x"6B2" => DATA <= x"06";
when x"6B3" => DATA <= x"99";
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when x"6B5" => DATA <= x"00";
when x"6B6" => DATA <= x"D0";
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when x"6B8" => DATA <= x"60";
when x"6B9" => DATA <= x"4C";
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when x"6BB" => DATA <= x"E5";
when x"6BC" => DATA <= x"20";
when x"6BD" => DATA <= x"CB";
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when x"6C0" => DATA <= x"F7";
when x"6C1" => DATA <= x"20";
when x"6C2" => DATA <= x"D1";
when x"6C3" => DATA <= x"F7";
when x"6C4" => DATA <= x"46";
when x"6C5" => DATA <= x"49";
when x"6C6" => DATA <= x"4C";
when x"6C7" => DATA <= x"45";
when x"6C8" => DATA <= x"3F";
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when x"6CA" => DATA <= x"00";
when x"6CB" => DATA <= x"20";
when x"6CC" => DATA <= x"2D";
when x"6CD" => DATA <= x"EC";
when x"6CE" => DATA <= x"A0";
when x"6CF" => DATA <= x"F8";
when x"6D0" => DATA <= x"20";
when x"6D1" => DATA <= x"0C";
when x"6D2" => DATA <= x"EE";
when x"6D3" => DATA <= x"CC";
when x"6D4" => DATA <= x"05";
when x"6D5" => DATA <= x"21";
when x"6D6" => DATA <= x"B0";
when x"6D7" => DATA <= x"20";
when x"6D8" => DATA <= x"B9";
when x"6D9" => DATA <= x"0F";
when x"6DA" => DATA <= x"20";
when x"6DB" => DATA <= x"29";
when x"6DC" => DATA <= x"7F";
when x"6DD" => DATA <= x"C5";
when x"6DE" => DATA <= x"AC";
when x"6DF" => DATA <= x"D0";
when x"6E0" => DATA <= x"EF";
when x"6E1" => DATA <= x"20";
when x"6E2" => DATA <= x"0D";
when x"6E3" => DATA <= x"EE";
when x"6E4" => DATA <= x"A2";
when x"6E5" => DATA <= x"06";
when x"6E6" => DATA <= x"B9";
when x"6E7" => DATA <= x"07";
when x"6E8" => DATA <= x"20";
when x"6E9" => DATA <= x"D5";
when x"6EA" => DATA <= x"A5";
when x"6EB" => DATA <= x"D0";
when x"6EC" => DATA <= x"05";
when x"6ED" => DATA <= x"88";
when x"6EE" => DATA <= x"CA";
when x"6EF" => DATA <= x"10";
when x"6F0" => DATA <= x"F5";
when x"6F1" => DATA <= x"60";
when x"6F2" => DATA <= x"88";
when x"6F3" => DATA <= x"CA";
when x"6F4" => DATA <= x"10";
when x"6F5" => DATA <= x"FC";
when x"6F6" => DATA <= x"30";
when x"6F7" => DATA <= x"D8";
when x"6F8" => DATA <= x"18";
when x"6F9" => DATA <= x"60";
when x"6FA" => DATA <= x"A5";
when x"6FB" => DATA <= x"EF";
when x"6FC" => DATA <= x"D0";
when x"6FD" => DATA <= x"64";
when x"6FE" => DATA <= x"B9";
when x"6FF" => DATA <= x"0F";
when x"700" => DATA <= x"20";
when x"701" => DATA <= x"29";
when x"702" => DATA <= x"7F";
when x"703" => DATA <= x"20";
when x"704" => DATA <= x"F4";
when x"705" => DATA <= x"FF";
when x"706" => DATA <= x"20";
when x"707" => DATA <= x"FD";
when x"708" => DATA <= x"F7";
when x"709" => DATA <= x"BE";
when x"70A" => DATA <= x"0F";
when x"70B" => DATA <= x"20";
when x"70C" => DATA <= x"10";
when x"70D" => DATA <= x"02";
when x"70E" => DATA <= x"A9";
when x"70F" => DATA <= x"23";
when x"710" => DATA <= x"20";
when x"711" => DATA <= x"F4";
when x"712" => DATA <= x"FF";
when x"713" => DATA <= x"A2";
when x"714" => DATA <= x"07";
when x"715" => DATA <= x"B9";
when x"716" => DATA <= x"08";
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when x"718" => DATA <= x"20";
when x"719" => DATA <= x"F4";
when x"71A" => DATA <= x"FF";
when x"71B" => DATA <= x"C8";
when x"71C" => DATA <= x"CA";
when x"71D" => DATA <= x"D0";
when x"71E" => DATA <= x"F6";
when x"71F" => DATA <= x"20";
when x"720" => DATA <= x"FD";
when x"721" => DATA <= x"F7";
when x"722" => DATA <= x"B9";
when x"723" => DATA <= x"02";
when x"724" => DATA <= x"21";
when x"725" => DATA <= x"20";
when x"726" => DATA <= x"02";
when x"727" => DATA <= x"F8";
when x"728" => DATA <= x"B9";
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when x"72A" => DATA <= x"21";
when x"72B" => DATA <= x"20";
when x"72C" => DATA <= x"02";
when x"72D" => DATA <= x"F8";
when x"72E" => DATA <= x"C8";
when x"72F" => DATA <= x"E8";
when x"730" => DATA <= x"C8";
when x"731" => DATA <= x"E0";
when x"732" => DATA <= x"02";
when x"733" => DATA <= x"90";
when x"734" => DATA <= x"EA";
when x"735" => DATA <= x"20";
when x"736" => DATA <= x"FD";
when x"737" => DATA <= x"F7";
when x"738" => DATA <= x"20";
when x"739" => DATA <= x"FD";
when x"73A" => DATA <= x"F7";
when x"73B" => DATA <= x"B9";
when x"73C" => DATA <= x"03";
when x"73D" => DATA <= x"21";
when x"73E" => DATA <= x"20";
when x"73F" => DATA <= x"1F";
when x"740" => DATA <= x"EE";
when x"741" => DATA <= x"20";
when x"742" => DATA <= x"0B";
when x"743" => DATA <= x"F8";
when x"744" => DATA <= x"B9";
when x"745" => DATA <= x"02";
when x"746" => DATA <= x"21";
when x"747" => DATA <= x"20";
when x"748" => DATA <= x"02";
when x"749" => DATA <= x"F8";
when x"74A" => DATA <= x"B9";
when x"74B" => DATA <= x"01";
when x"74C" => DATA <= x"21";
when x"74D" => DATA <= x"20";
when x"74E" => DATA <= x"02";
when x"74F" => DATA <= x"F8";
when x"750" => DATA <= x"20";
when x"751" => DATA <= x"FD";
when x"752" => DATA <= x"F7";
when x"753" => DATA <= x"B9";
when x"754" => DATA <= x"03";
when x"755" => DATA <= x"21";
when x"756" => DATA <= x"20";
when x"757" => DATA <= x"0B";
when x"758" => DATA <= x"F8";
when x"759" => DATA <= x"B9";
when x"75A" => DATA <= x"04";
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when x"75C" => DATA <= x"20";
when x"75D" => DATA <= x"02";
when x"75E" => DATA <= x"F8";
when x"75F" => DATA <= x"20";
when x"760" => DATA <= x"ED";
when x"761" => DATA <= x"FF";
when x"762" => DATA <= x"60";
when x"763" => DATA <= x"A2";
when x"764" => DATA <= x"00";
when x"765" => DATA <= x"A4";
when x"766" => DATA <= x"9A";
when x"767" => DATA <= x"20";
when x"768" => DATA <= x"76";
when x"769" => DATA <= x"F8";
when x"76A" => DATA <= x"C9";
when x"76B" => DATA <= x"22";
when x"76C" => DATA <= x"F0";
when x"76D" => DATA <= x"20";
when x"76E" => DATA <= x"C9";
when x"76F" => DATA <= x"0D";
when x"770" => DATA <= x"F0";
when x"771" => DATA <= x"0C";
when x"772" => DATA <= x"9D";
when x"773" => DATA <= x"40";
when x"774" => DATA <= x"01";
when x"775" => DATA <= x"E8";
when x"776" => DATA <= x"C8";
when x"777" => DATA <= x"B9";
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when x"779" => DATA <= x"01";
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when x"77C" => DATA <= x"D0";
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when x"77E" => DATA <= x"A9";
when x"77F" => DATA <= x"0D";
when x"780" => DATA <= x"9D";
when x"781" => DATA <= x"40";
when x"782" => DATA <= x"01";
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when x"784" => DATA <= x"40";
when x"785" => DATA <= x"85";
when x"786" => DATA <= x"9A";
when x"787" => DATA <= x"A9";
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when x"789" => DATA <= x"85";
when x"78A" => DATA <= x"9B";
when x"78B" => DATA <= x"A2";
when x"78C" => DATA <= x"9A";
when x"78D" => DATA <= x"60";
when x"78E" => DATA <= x"C8";
when x"78F" => DATA <= x"B9";
when x"790" => DATA <= x"00";
when x"791" => DATA <= x"01";
when x"792" => DATA <= x"C9";
when x"793" => DATA <= x"0D";
when x"794" => DATA <= x"F0";
when x"795" => DATA <= x"14";
when x"796" => DATA <= x"9D";
when x"797" => DATA <= x"40";
when x"798" => DATA <= x"01";
when x"799" => DATA <= x"E8";
when x"79A" => DATA <= x"C9";
when x"79B" => DATA <= x"22";
when x"79C" => DATA <= x"D0";
when x"79D" => DATA <= x"F0";
when x"79E" => DATA <= x"CA";
when x"79F" => DATA <= x"C8";
when x"7A0" => DATA <= x"B9";
when x"7A1" => DATA <= x"00";
when x"7A2" => DATA <= x"01";
when x"7A3" => DATA <= x"C9";
when x"7A4" => DATA <= x"22";
when x"7A5" => DATA <= x"D0";
when x"7A6" => DATA <= x"D7";
when x"7A7" => DATA <= x"E8";
when x"7A8" => DATA <= x"B0";
when x"7A9" => DATA <= x"E4";
when x"7AA" => DATA <= x"4C";
when x"7AB" => DATA <= x"9E";
when x"7AC" => DATA <= x"E5";
when x"7AD" => DATA <= x"B9";
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when x"7AF" => DATA <= x"20";
when x"7B0" => DATA <= x"30";
when x"7B1" => DATA <= x"19";
when x"7B2" => DATA <= x"B9";
when x"7B3" => DATA <= x"10";
when x"7B4" => DATA <= x"20";
when x"7B5" => DATA <= x"99";
when x"7B6" => DATA <= x"08";
when x"7B7" => DATA <= x"20";
when x"7B8" => DATA <= x"B9";
when x"7B9" => DATA <= x"10";
when x"7BA" => DATA <= x"21";
when x"7BB" => DATA <= x"99";
when x"7BC" => DATA <= x"08";
when x"7BD" => DATA <= x"21";
when x"7BE" => DATA <= x"C8";
when x"7BF" => DATA <= x"CC";
when x"7C0" => DATA <= x"05";
when x"7C1" => DATA <= x"21";
when x"7C2" => DATA <= x"90";
when x"7C3" => DATA <= x"EE";
when x"7C4" => DATA <= x"98";
when x"7C5" => DATA <= x"E9";
when x"7C6" => DATA <= x"08";
when x"7C7" => DATA <= x"8D";
when x"7C8" => DATA <= x"05";
when x"7C9" => DATA <= x"21";
when x"7CA" => DATA <= x"60";
when x"7CB" => DATA <= x"4C";
when x"7CC" => DATA <= x"D0";
when x"7CD" => DATA <= x"E2";
when x"7CE" => DATA <= x"53";
when x"7CF" => DATA <= x"44";
when x"7D0" => DATA <= x"44";
when x"7D1" => DATA <= x"4F";
when x"7D2" => DATA <= x"53";
when x"7D3" => DATA <= x"20";
when x"7D4" => DATA <= x"20";
when x"7D5" => DATA <= x"20";
when x"7D6" => DATA <= x"20";
when x"7D7" => DATA <= x"24";
when x"7D8" => DATA <= x"EE";
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when x"7DA" => DATA <= x"01";
when x"7DB" => DATA <= x"EC";
when x"7DC" => DATA <= x"A0";
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when x"7E0" => DATA <= x"23";
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when x"7E2" => DATA <= x"CE";
when x"7E3" => DATA <= x"E7";
when x"7E4" => DATA <= x"F0";
when x"7E5" => DATA <= x"0F";
when x"7E6" => DATA <= x"20";
when x"7E7" => DATA <= x"D1";
when x"7E8" => DATA <= x"F7";
when x"7E9" => DATA <= x"53";
when x"7EA" => DATA <= x"44";
when x"7EB" => DATA <= x"20";
when x"7EC" => DATA <= x"46";
when x"7ED" => DATA <= x"4F";
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when x"7EF" => DATA <= x"4D";
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when x"7F1" => DATA <= x"54";
when x"7F2" => DATA <= x"3F";
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when x"7F4" => DATA <= x"00";
when x"7F5" => DATA <= x"88";
when x"7F6" => DATA <= x"10";
when x"7F7" => DATA <= x"E6";
when x"7F8" => DATA <= x"A0";
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when x"7FA" => DATA <= x"B9";
when x"7FB" => DATA <= x"00";
when x"7FC" => DATA <= x"23";
when x"7FD" => DATA <= x"99";
when x"7FE" => DATA <= x"F0";
when x"7FF" => DATA <= x"00";
when x"800" => DATA <= x"88";
when x"801" => DATA <= x"10";
when x"802" => DATA <= x"F7";
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when x"804" => DATA <= x"70";
when x"805" => DATA <= x"8D";
when x"806" => DATA <= x"06";
when x"807" => DATA <= x"02";
when x"808" => DATA <= x"A9";
when x"809" => DATA <= x"E0";
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when x"80C" => DATA <= x"02";
when x"80D" => DATA <= x"A2";
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when x"80F" => DATA <= x"BD";
when x"810" => DATA <= x"2D";
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when x"813" => DATA <= x"0C";
when x"814" => DATA <= x"02";
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when x"816" => DATA <= x"10";
when x"817" => DATA <= x"F7";
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when x"81A" => DATA <= x"85";
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when x"81C" => DATA <= x"85";
when x"81D" => DATA <= x"AD";
when x"81E" => DATA <= x"49";
when x"81F" => DATA <= x"20";
when x"820" => DATA <= x"85";
when x"821" => DATA <= x"EE";
when x"822" => DATA <= x"85";
when x"823" => DATA <= x"C0";
when x"824" => DATA <= x"85";
when x"825" => DATA <= x"B9";
when x"826" => DATA <= x"85";
when x"827" => DATA <= x"BA";
when x"828" => DATA <= x"A0";
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when x"82A" => DATA <= x"84";
when x"82B" => DATA <= x"EF";
when x"82C" => DATA <= x"60";
when x"82D" => DATA <= x"26";
when x"82E" => DATA <= x"E3";
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when x"830" => DATA <= x"E4";
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when x"832" => DATA <= x"3E";
when x"833" => DATA <= x"ED";
when x"834" => DATA <= x"20";
when x"835" => DATA <= x"55";
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when x"837" => DATA <= x"20";
when x"838" => DATA <= x"F0";
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when x"83A" => DATA <= x"A2";
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when x"83C" => DATA <= x"A5";
when x"83D" => DATA <= x"83";
when x"83E" => DATA <= x"C5";
when x"83F" => DATA <= x"F1";
when x"840" => DATA <= x"D0";
when x"841" => DATA <= x"0D";
when x"842" => DATA <= x"A5";
when x"843" => DATA <= x"82";
when x"844" => DATA <= x"C5";
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when x"846" => DATA <= x"D0";
when x"847" => DATA <= x"07";
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when x"849" => DATA <= x"F0";
when x"84A" => DATA <= x"86";
when x"84B" => DATA <= x"F1";
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when x"84D" => DATA <= x"85";
when x"84E" => DATA <= x"E8";
when x"84F" => DATA <= x"A5";
when x"850" => DATA <= x"83";
when x"851" => DATA <= x"C5";
when x"852" => DATA <= x"F3";
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when x"854" => DATA <= x"0D";
when x"855" => DATA <= x"A5";
when x"856" => DATA <= x"82";
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when x"859" => DATA <= x"D0";
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when x"85B" => DATA <= x"86";
when x"85C" => DATA <= x"F2";
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when x"85E" => DATA <= x"F3";
when x"85F" => DATA <= x"4C";
when x"860" => DATA <= x"85";
when x"861" => DATA <= x"E8";
when x"862" => DATA <= x"A5";
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when x"864" => DATA <= x"C5";
when x"865" => DATA <= x"F5";
when x"866" => DATA <= x"D0";
when x"867" => DATA <= x"0D";
when x"868" => DATA <= x"A5";
when x"869" => DATA <= x"82";
when x"86A" => DATA <= x"C5";
when x"86B" => DATA <= x"F4";
when x"86C" => DATA <= x"D0";
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when x"86E" => DATA <= x"86";
when x"86F" => DATA <= x"F4";
when x"870" => DATA <= x"86";
when x"871" => DATA <= x"F5";
when x"872" => DATA <= x"4C";
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when x"874" => DATA <= x"E8";
when x"875" => DATA <= x"A5";
when x"876" => DATA <= x"83";
when x"877" => DATA <= x"C5";
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when x"879" => DATA <= x"D0";
when x"87A" => DATA <= x"0A";
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when x"87C" => DATA <= x"82";
when x"87D" => DATA <= x"C5";
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when x"87F" => DATA <= x"D0";
when x"880" => DATA <= x"04";
when x"881" => DATA <= x"86";
when x"882" => DATA <= x"F6";
when x"883" => DATA <= x"86";
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when x"885" => DATA <= x"A5";
when x"886" => DATA <= x"80";
when x"887" => DATA <= x"0A";
when x"888" => DATA <= x"AA";
when x"889" => DATA <= x"A5";
when x"88A" => DATA <= x"82";
when x"88B" => DATA <= x"95";
when x"88C" => DATA <= x"F0";
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when x"88E" => DATA <= x"83";
when x"88F" => DATA <= x"95";
when x"890" => DATA <= x"F1";
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when x"892" => DATA <= x"E0";
when x"893" => DATA <= x"EB";
when x"894" => DATA <= x"20";
when x"895" => DATA <= x"55";
when x"896" => DATA <= x"ED";
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when x"898" => DATA <= x"82";
when x"899" => DATA <= x"85";
when x"89A" => DATA <= x"92";
when x"89B" => DATA <= x"A5";
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when x"89D" => DATA <= x"85";
when x"89E" => DATA <= x"93";
when x"89F" => DATA <= x"20";
when x"8A0" => DATA <= x"55";
when x"8A1" => DATA <= x"ED";
when x"8A2" => DATA <= x"A5";
when x"8A3" => DATA <= x"82";
when x"8A4" => DATA <= x"85";
when x"8A5" => DATA <= x"94";
when x"8A6" => DATA <= x"A5";
when x"8A7" => DATA <= x"83";
when x"8A8" => DATA <= x"85";
when x"8A9" => DATA <= x"95";
when x"8AA" => DATA <= x"20";
when x"8AB" => DATA <= x"76";
when x"8AC" => DATA <= x"F8";
when x"8AD" => DATA <= x"C9";
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when x"8AF" => DATA <= x"F0";
when x"8B0" => DATA <= x"19";
when x"8B1" => DATA <= x"A4";
when x"8B2" => DATA <= x"03";
when x"8B3" => DATA <= x"B1";
when x"8B4" => DATA <= x"05";
when x"8B5" => DATA <= x"C9";
when x"8B6" => DATA <= x"0D";
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when x"8B8" => DATA <= x"11";
when x"8B9" => DATA <= x"85";
when x"8BA" => DATA <= x"96";
when x"8BB" => DATA <= x"C8";
when x"8BC" => DATA <= x"B1";
when x"8BD" => DATA <= x"05";
when x"8BE" => DATA <= x"C9";
when x"8BF" => DATA <= x"0D";
when x"8C0" => DATA <= x"D0";
when x"8C1" => DATA <= x"71";
when x"8C2" => DATA <= x"84";
when x"8C3" => DATA <= x"03";
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when x"8C5" => DATA <= x"31";
when x"8C6" => DATA <= x"C2";
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when x"8C8" => DATA <= x"CE";
when x"8C9" => DATA <= x"E8";
when x"8CA" => DATA <= x"A2";
when x"8CB" => DATA <= x"00";
when x"8CC" => DATA <= x"86";
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when x"8CF" => DATA <= x"ED";
when x"8D0" => DATA <= x"FF";
when x"8D1" => DATA <= x"A9";
when x"8D2" => DATA <= x"00";
when x"8D3" => DATA <= x"85";
when x"8D4" => DATA <= x"90";
when x"8D5" => DATA <= x"85";
when x"8D6" => DATA <= x"91";
when x"8D7" => DATA <= x"A6";
when x"8D8" => DATA <= x"92";
when x"8D9" => DATA <= x"A4";
when x"8DA" => DATA <= x"93";
when x"8DB" => DATA <= x"20";
when x"8DC" => DATA <= x"0D";
when x"8DD" => DATA <= x"EC";
when x"8DE" => DATA <= x"A0";
when x"8DF" => DATA <= x"0F";
when x"8E0" => DATA <= x"B1";
when x"8E1" => DATA <= x"87";
when x"8E2" => DATA <= x"30";
when x"8E3" => DATA <= x"1C";
when x"8E4" => DATA <= x"A5";
when x"8E5" => DATA <= x"96";
when x"8E6" => DATA <= x"F0";
when x"8E7" => DATA <= x"08";
when x"8E8" => DATA <= x"A0";
when x"8E9" => DATA <= x"00";
when x"8EA" => DATA <= x"B1";
when x"8EB" => DATA <= x"87";
when x"8EC" => DATA <= x"C5";
when x"8ED" => DATA <= x"96";
when x"8EE" => DATA <= x"D0";
when x"8EF" => DATA <= x"10";
when x"8F0" => DATA <= x"A6";
when x"8F1" => DATA <= x"92";
when x"8F2" => DATA <= x"A4";
when x"8F3" => DATA <= x"93";
when x"8F4" => DATA <= x"20";
when x"8F5" => DATA <= x"B7";
when x"8F6" => DATA <= x"ED";
when x"8F7" => DATA <= x"20";
when x"8F8" => DATA <= x"ED";
when x"8F9" => DATA <= x"FF";
when x"8FA" => DATA <= x"E6";
when x"8FB" => DATA <= x"90";
when x"8FC" => DATA <= x"D0";
when x"8FD" => DATA <= x"02";
when x"8FE" => DATA <= x"E6";
when x"8FF" => DATA <= x"91";
when x"900" => DATA <= x"E6";
when x"901" => DATA <= x"92";
when x"902" => DATA <= x"D0";
when x"903" => DATA <= x"02";
when x"904" => DATA <= x"E6";
when x"905" => DATA <= x"93";
when x"906" => DATA <= x"A5";
when x"907" => DATA <= x"93";
when x"908" => DATA <= x"C5";
when x"909" => DATA <= x"95";
when x"90A" => DATA <= x"90";
when x"90B" => DATA <= x"CB";
when x"90C" => DATA <= x"D0";
when x"90D" => DATA <= x"08";
when x"90E" => DATA <= x"A5";
when x"90F" => DATA <= x"92";
when x"910" => DATA <= x"C5";
when x"911" => DATA <= x"94";
when x"912" => DATA <= x"90";
when x"913" => DATA <= x"C3";
when x"914" => DATA <= x"F0";
when x"915" => DATA <= x"C1";
when x"916" => DATA <= x"20";
when x"917" => DATA <= x"ED";
when x"918" => DATA <= x"FF";
when x"919" => DATA <= x"20";
when x"91A" => DATA <= x"D1";
when x"91B" => DATA <= x"F7";
when x"91C" => DATA <= x"44";
when x"91D" => DATA <= x"49";
when x"91E" => DATA <= x"53";
when x"91F" => DATA <= x"4B";
when x"920" => DATA <= x"53";
when x"921" => DATA <= x"20";
when x"922" => DATA <= x"46";
when x"923" => DATA <= x"4F";
when x"924" => DATA <= x"55";
when x"925" => DATA <= x"4E";
when x"926" => DATA <= x"44";
when x"927" => DATA <= x"3A";
when x"928" => DATA <= x"EA";
when x"929" => DATA <= x"A6";
when x"92A" => DATA <= x"90";
when x"92B" => DATA <= x"A4";
when x"92C" => DATA <= x"91";
when x"92D" => DATA <= x"20";
when x"92E" => DATA <= x"88";
when x"92F" => DATA <= x"ED";
when x"930" => DATA <= x"4C";
when x"931" => DATA <= x"ED";
when x"932" => DATA <= x"FF";
when x"933" => DATA <= x"20";
when x"934" => DATA <= x"D1";
when x"935" => DATA <= x"F7";
when x"936" => DATA <= x"46";
when x"937" => DATA <= x"49";
when x"938" => DATA <= x"4C";
when x"939" => DATA <= x"54";
when x"93A" => DATA <= x"45";
when x"93B" => DATA <= x"52";
when x"93C" => DATA <= x"3F";
when x"93D" => DATA <= x"EA";
when x"93E" => DATA <= x"00";
when x"93F" => DATA <= x"20";
when x"940" => DATA <= x"F0";
when x"941" => DATA <= x"ED";
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when x"943" => DATA <= x"00";
when x"944" => DATA <= x"86";
when x"945" => DATA <= x"80";
when x"946" => DATA <= x"A5";
when x"947" => DATA <= x"80";
when x"948" => DATA <= x"48";
when x"949" => DATA <= x"20";
when x"94A" => DATA <= x"0B";
when x"94B" => DATA <= x"F8";
when x"94C" => DATA <= x"A9";
when x"94D" => DATA <= x"3A";
when x"94E" => DATA <= x"20";
when x"94F" => DATA <= x"F4";
when x"950" => DATA <= x"FF";
when x"951" => DATA <= x"68";
when x"952" => DATA <= x"20";
when x"953" => DATA <= x"AA";
when x"954" => DATA <= x"ED";
when x"955" => DATA <= x"30";
when x"956" => DATA <= x"18";
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when x"958" => DATA <= x"16";
when x"959" => DATA <= x"EC";
when x"95A" => DATA <= x"A0";
when x"95B" => DATA <= x"0F";
when x"95C" => DATA <= x"B1";
when x"95D" => DATA <= x"87";
when x"95E" => DATA <= x"C9";
when x"95F" => DATA <= x"FF";
when x"960" => DATA <= x"F0";
when x"961" => DATA <= x"0D";
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when x"963" => DATA <= x"82";
when x"964" => DATA <= x"A4";
when x"965" => DATA <= x"83";
when x"966" => DATA <= x"20";
when x"967" => DATA <= x"B7";
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when x"969" => DATA <= x"20";
when x"96A" => DATA <= x"ED";
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when x"96C" => DATA <= x"4C";
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when x"96F" => DATA <= x"20";
when x"970" => DATA <= x"D1";
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when x"972" => DATA <= x"20";
when x"973" => DATA <= x"20";
when x"974" => DATA <= x"20";
when x"975" => DATA <= x"2D";
when x"976" => DATA <= x"EA";
when x"977" => DATA <= x"20";
when x"978" => DATA <= x"ED";
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when x"97C" => DATA <= x"A5";
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when x"980" => DATA <= x"D0";
when x"981" => DATA <= x"C4";
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when x"983" => DATA <= x"ED";
when x"984" => DATA <= x"FF";
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when x"986" => DATA <= x"55";
when x"987" => DATA <= x"ED";
when x"988" => DATA <= x"20";
when x"989" => DATA <= x"F0";
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when x"98B" => DATA <= x"20";
when x"98C" => DATA <= x"16";
when x"98D" => DATA <= x"EC";
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when x"99C" => DATA <= x"EB";
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when x"99E" => DATA <= x"55";
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when x"9A0" => DATA <= x"20";
when x"9A1" => DATA <= x"F0";
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when x"9A3" => DATA <= x"20";
when x"9A4" => DATA <= x"16";
when x"9A5" => DATA <= x"EC";
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when x"9A7" => DATA <= x"68";
when x"9A8" => DATA <= x"E6";
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when x"9AA" => DATA <= x"0F";
when x"9AB" => DATA <= x"A9";
when x"9AC" => DATA <= x"0F";
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when x"9AF" => DATA <= x"20";
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when x"9B2" => DATA <= x"4C";
when x"9B3" => DATA <= x"E0";
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when x"9B5" => DATA <= x"20";
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when x"9B8" => DATA <= x"A9";
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when x"9BA" => DATA <= x"85";
when x"9BB" => DATA <= x"90";
when x"9BC" => DATA <= x"85";
when x"9BD" => DATA <= x"91";
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when x"9BF" => DATA <= x"92";
when x"9C0" => DATA <= x"85";
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when x"9C3" => DATA <= x"94";
when x"9C4" => DATA <= x"85";
when x"9C5" => DATA <= x"95";
when x"9C6" => DATA <= x"A6";
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when x"9C9" => DATA <= x"95";
when x"9CA" => DATA <= x"20";
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when x"9CD" => DATA <= x"A0";
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when x"9D1" => DATA <= x"C9";
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when x"9D3" => DATA <= x"F0";
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when x"9DB" => DATA <= x"29";
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when x"A0C" => DATA <= x"A4";
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when x"A0F" => DATA <= x"88";
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when x"A14" => DATA <= x"20";
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when x"A18" => DATA <= x"4B";
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when x"A1A" => DATA <= x"20";
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when x"A1E" => DATA <= x"45";
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when x"A4C" => DATA <= x"59";
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when x"A4F" => DATA <= x"4C";
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when x"A51" => DATA <= x"FF";
when x"A52" => DATA <= x"20";
when x"A53" => DATA <= x"ED";
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when x"A55" => DATA <= x"A0";
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when x"A5E" => DATA <= x"4C";
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when x"A60" => DATA <= x"EB";
when x"A61" => DATA <= x"20";
when x"A62" => DATA <= x"55";
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when x"A6C" => DATA <= x"A9";
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when x"A70" => DATA <= x"20";
when x"A71" => DATA <= x"26";
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when x"A73" => DATA <= x"4C";
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when x"A76" => DATA <= x"20";
when x"A77" => DATA <= x"E0";
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when x"A7C" => DATA <= x"A9";
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when x"A7E" => DATA <= x"85";
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when x"A80" => DATA <= x"85";
when x"A81" => DATA <= x"91";
when x"A82" => DATA <= x"A6";
when x"A83" => DATA <= x"90";
when x"A84" => DATA <= x"A4";
when x"A85" => DATA <= x"91";
when x"A86" => DATA <= x"20";
when x"A87" => DATA <= x"0D";
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when x"A89" => DATA <= x"A0";
when x"A8A" => DATA <= x"0F";
when x"A8B" => DATA <= x"B1";
when x"A8C" => DATA <= x"87";
when x"A8D" => DATA <= x"C9";
when x"A8E" => DATA <= x"F0";
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when x"A90" => DATA <= x"2A";
when x"A91" => DATA <= x"E6";
when x"A92" => DATA <= x"90";
when x"A93" => DATA <= x"D0";
when x"A94" => DATA <= x"02";
when x"A95" => DATA <= x"E6";
when x"A96" => DATA <= x"91";
when x"A97" => DATA <= x"A5";
when x"A98" => DATA <= x"91";
when x"A99" => DATA <= x"C9";
when x"A9A" => DATA <= x"03";
when x"A9B" => DATA <= x"90";
when x"A9C" => DATA <= x"E5";
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when x"A9E" => DATA <= x"08";
when x"A9F" => DATA <= x"A5";
when x"AA0" => DATA <= x"90";
when x"AA1" => DATA <= x"C9";
when x"AA2" => DATA <= x"FE";
when x"AA3" => DATA <= x"90";
when x"AA4" => DATA <= x"DD";
when x"AA5" => DATA <= x"F0";
when x"AA6" => DATA <= x"DB";
when x"AA7" => DATA <= x"20";
when x"AA8" => DATA <= x"D1";
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when x"AAA" => DATA <= x"4E";
when x"AAB" => DATA <= x"4F";
when x"AAC" => DATA <= x"20";
when x"AAD" => DATA <= x"44";
when x"AAE" => DATA <= x"49";
when x"AAF" => DATA <= x"53";
when x"AB0" => DATA <= x"4B";
when x"AB1" => DATA <= x"20";
when x"AB2" => DATA <= x"46";
when x"AB3" => DATA <= x"4F";
when x"AB4" => DATA <= x"55";
when x"AB5" => DATA <= x"4E";
when x"AB6" => DATA <= x"44";
when x"AB7" => DATA <= x"EA";
when x"AB8" => DATA <= x"4C";
when x"AB9" => DATA <= x"EB";
when x"ABA" => DATA <= x"EA";
when x"ABB" => DATA <= x"A5";
when x"ABC" => DATA <= x"90";
when x"ABD" => DATA <= x"85";
when x"ABE" => DATA <= x"82";
when x"ABF" => DATA <= x"A5";
when x"AC0" => DATA <= x"91";
when x"AC1" => DATA <= x"85";
when x"AC2" => DATA <= x"83";
when x"AC3" => DATA <= x"A5";
when x"AC4" => DATA <= x"EE";
when x"AC5" => DATA <= x"85";
when x"AC6" => DATA <= x"80";
when x"AC7" => DATA <= x"A9";
when x"AC8" => DATA <= x"00";
when x"AC9" => DATA <= x"20";
when x"ACA" => DATA <= x"3A";
when x"ACB" => DATA <= x"E8";
when x"ACC" => DATA <= x"20";
when x"ACD" => DATA <= x"D1";
when x"ACE" => DATA <= x"F7";
when x"ACF" => DATA <= x"44";
when x"AD0" => DATA <= x"49";
when x"AD1" => DATA <= x"53";
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when x"AD4" => DATA <= x"EA";
when x"AD5" => DATA <= x"20";
when x"AD6" => DATA <= x"A3";
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when x"AD8" => DATA <= x"20";
when x"AD9" => DATA <= x"D1";
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when x"ADB" => DATA <= x"20";
when x"ADC" => DATA <= x"49";
when x"ADD" => DATA <= x"4E";
when x"ADE" => DATA <= x"20";
when x"ADF" => DATA <= x"44";
when x"AE0" => DATA <= x"52";
when x"AE1" => DATA <= x"49";
when x"AE2" => DATA <= x"56";
when x"AE3" => DATA <= x"45";
when x"AE4" => DATA <= x"20";
when x"AE5" => DATA <= x"EA";
when x"AE6" => DATA <= x"A5";
when x"AE7" => DATA <= x"EE";
when x"AE8" => DATA <= x"20";
when x"AE9" => DATA <= x"0B";
when x"AEA" => DATA <= x"F8";
when x"AEB" => DATA <= x"4C";
when x"AEC" => DATA <= x"ED";
when x"AED" => DATA <= x"FF";
when x"AEE" => DATA <= x"20";
when x"AEF" => DATA <= x"55";
when x"AF0" => DATA <= x"ED";
when x"AF1" => DATA <= x"20";
when x"AF2" => DATA <= x"F0";
when x"AF3" => DATA <= x"ED";
when x"AF4" => DATA <= x"20";
when x"AF5" => DATA <= x"16";
when x"AF6" => DATA <= x"EC";
when x"AF7" => DATA <= x"20";
when x"AF8" => DATA <= x"68";
when x"AF9" => DATA <= x"E6";
when x"AFA" => DATA <= x"20";
when x"AFB" => DATA <= x"7E";
when x"AFC" => DATA <= x"E6";
when x"AFD" => DATA <= x"20";
when x"AFE" => DATA <= x"D1";
when x"AFF" => DATA <= x"F7";
when x"B00" => DATA <= x"46";
when x"B01" => DATA <= x"4F";
when x"B02" => DATA <= x"52";
when x"B03" => DATA <= x"4D";
when x"B04" => DATA <= x"41";
when x"B05" => DATA <= x"54";
when x"B06" => DATA <= x"20";
when x"B07" => DATA <= x"44";
when x"B08" => DATA <= x"49";
when x"B09" => DATA <= x"53";
when x"B0A" => DATA <= x"4B";
when x"B0B" => DATA <= x"3A";
when x"B0C" => DATA <= x"EA";
when x"B0D" => DATA <= x"20";
when x"B0E" => DATA <= x"A3";
when x"B0F" => DATA <= x"ED";
when x"B10" => DATA <= x"20";
when x"B11" => DATA <= x"F5";
when x"B12" => DATA <= x"ED";
when x"B13" => DATA <= x"48";
when x"B14" => DATA <= x"20";
when x"B15" => DATA <= x"F4";
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when x"B17" => DATA <= x"68";
when x"B18" => DATA <= x"C9";
when x"B19" => DATA <= x"59";
when x"B1A" => DATA <= x"F0";
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when x"B1C" => DATA <= x"4C";
when x"B1D" => DATA <= x"ED";
when x"B1E" => DATA <= x"FF";
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when x"B20" => DATA <= x"67";
when x"B21" => DATA <= x"EA";
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when x"B23" => DATA <= x"ED";
when x"B24" => DATA <= x"FF";
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when x"B26" => DATA <= x"20";
when x"B27" => DATA <= x"A2";
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when x"B29" => DATA <= x"9D";
when x"B2A" => DATA <= x"00";
when x"B2B" => DATA <= x"20";
when x"B2C" => DATA <= x"9D";
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when x"B2E" => DATA <= x"21";
when x"B2F" => DATA <= x"E8";
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when x"B31" => DATA <= x"F7";
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when x"B34" => DATA <= x"8D";
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when x"B36" => DATA <= x"21";
when x"B37" => DATA <= x"A9";
when x"B38" => DATA <= x"01";
when x"B39" => DATA <= x"8D";
when x"B3A" => DATA <= x"06";
when x"B3B" => DATA <= x"21";
when x"B3C" => DATA <= x"A9";
when x"B3D" => DATA <= x"90";
when x"B3E" => DATA <= x"8D";
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when x"B40" => DATA <= x"21";
when x"B41" => DATA <= x"20";
when x"B42" => DATA <= x"7B";
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when x"B44" => DATA <= x"A0";
when x"B45" => DATA <= x"00";
when x"B46" => DATA <= x"A2";
when x"B47" => DATA <= x"00";
when x"B48" => DATA <= x"BD";
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when x"B4B" => DATA <= x"91";
when x"B4C" => DATA <= x"87";
when x"B4D" => DATA <= x"C8";
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when x"B50" => DATA <= x"08";
when x"B51" => DATA <= x"D0";
when x"B52" => DATA <= x"F5";
when x"B53" => DATA <= x"BD";
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when x"B55" => DATA <= x"20";
when x"B56" => DATA <= x"91";
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when x"B58" => DATA <= x"C8";
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when x"B5A" => DATA <= x"E0";
when x"B5B" => DATA <= x"0D";
when x"B5C" => DATA <= x"D0";
when x"B5D" => DATA <= x"F5";
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when x"B5F" => DATA <= x"26";
when x"B60" => DATA <= x"EC";
when x"B61" => DATA <= x"4C";
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when x"B63" => DATA <= x"EB";
when x"B64" => DATA <= x"20";
when x"B65" => DATA <= x"3E";
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when x"B67" => DATA <= x"20";
when x"B68" => DATA <= x"55";
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when x"B6B" => DATA <= x"F0";
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when x"B6D" => DATA <= x"20";
when x"B6E" => DATA <= x"01";
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when x"B76" => DATA <= x"99";
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when x"B79" => DATA <= x"A5";
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when x"B7B" => DATA <= x"99";
when x"B7C" => DATA <= x"01";
when x"B7D" => DATA <= x"23";
when x"B7E" => DATA <= x"4C";
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when x"B80" => DATA <= x"EC";
when x"B81" => DATA <= x"20";
when x"B82" => DATA <= x"F0";
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when x"B84" => DATA <= x"20";
when x"B85" => DATA <= x"ED";
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when x"B87" => DATA <= x"20";
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when x"B8A" => DATA <= x"53";
when x"B8B" => DATA <= x"44";
when x"B8C" => DATA <= x"44";
when x"B8D" => DATA <= x"4F";
when x"B8E" => DATA <= x"53";
when x"B8F" => DATA <= x"20";
when x"B90" => DATA <= x"56";
when x"B91" => DATA <= x"32";
when x"B92" => DATA <= x"2E";
when x"B93" => DATA <= x"33";
when x"B94" => DATA <= x"45";
when x"B95" => DATA <= x"EA";
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when x"B9C" => DATA <= x"A0";
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when x"BA0" => DATA <= x"B9";
when x"BA1" => DATA <= x"30";
when x"BA2" => DATA <= x"E1";
when x"BA3" => DATA <= x"30";
when x"BA4" => DATA <= x"08";
when x"BA5" => DATA <= x"20";
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when x"BA8" => DATA <= x"C8";
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when x"BAA" => DATA <= x"4C";
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when x"BAC" => DATA <= x"EB";
when x"BAD" => DATA <= x"E0";
when x"BAE" => DATA <= x"04";
when x"BAF" => DATA <= x"F0";
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when x"BB1" => DATA <= x"A9";
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when x"BB3" => DATA <= x"20";
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when x"BB6" => DATA <= x"CA";
when x"BB7" => DATA <= x"D0";
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when x"BB9" => DATA <= x"B9";
when x"BBA" => DATA <= x"30";
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when x"BBD" => DATA <= x"02";
when x"BBE" => DATA <= x"F8";
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when x"BC0" => DATA <= x"31";
when x"BC1" => DATA <= x"E1";
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when x"BC3" => DATA <= x"02";
when x"BC4" => DATA <= x"F8";
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when x"BC6" => DATA <= x"20";
when x"BC7" => DATA <= x"20";
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when x"BCA" => DATA <= x"C8";
when x"BCB" => DATA <= x"C8";
when x"BCC" => DATA <= x"B9";
when x"BCD" => DATA <= x"30";
when x"BCE" => DATA <= x"E1";
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when x"BD0" => DATA <= x"E6";
when x"BD1" => DATA <= x"D0";
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when x"BD3" => DATA <= x"B9";
when x"BD4" => DATA <= x"31";
when x"BD5" => DATA <= x"E1";
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when x"BDC" => DATA <= x"EB";
when x"BDD" => DATA <= x"4C";
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when x"BDF" => DATA <= x"FF";
when x"BE0" => DATA <= x"A5";
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when x"BE2" => DATA <= x"29";
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when x"C18" => DATA <= x"A4";
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when x"C1A" => DATA <= x"4C";
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when x"C1C" => DATA <= x"EC";
when x"C1D" => DATA <= x"20";
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when x"C20" => DATA <= x"20";
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when x"C24" => DATA <= x"88";
when x"C25" => DATA <= x"EE";
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when x"C2C" => DATA <= x"EC";
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when x"C30" => DATA <= x"80";
when x"C31" => DATA <= x"F0";
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when x"C33" => DATA <= x"4C";
when x"C34" => DATA <= x"78";
when x"C35" => DATA <= x"EC";
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when x"C3C" => DATA <= x"0C";
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when x"C40" => DATA <= x"4E";
when x"C41" => DATA <= x"4F";
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when x"C44" => DATA <= x"49";
when x"C45" => DATA <= x"53";
when x"C46" => DATA <= x"4B";
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when x"C48" => DATA <= x"00";
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when x"C4C" => DATA <= x"A0";
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when x"C50" => DATA <= x"85";
when x"C51" => DATA <= x"F8";
when x"C52" => DATA <= x"C9";
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when x"C55" => DATA <= x"10";
when x"C56" => DATA <= x"20";
when x"C57" => DATA <= x"D1";
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when x"C59" => DATA <= x"55";
when x"C5A" => DATA <= x"4E";
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when x"C5C" => DATA <= x"4F";
when x"C5D" => DATA <= x"52";
when x"C5E" => DATA <= x"4D";
when x"C5F" => DATA <= x"41";
when x"C60" => DATA <= x"54";
when x"C61" => DATA <= x"54";
when x"C62" => DATA <= x"45";
when x"C63" => DATA <= x"44";
when x"C64" => DATA <= x"EA";
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when x"C66" => DATA <= x"20";
when x"C67" => DATA <= x"6C";
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when x"C69" => DATA <= x"20";
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when x"C6C" => DATA <= x"20";
when x"C6D" => DATA <= x"F8";
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when x"C70" => DATA <= x"71";
when x"C71" => DATA <= x"EE";
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when x"C73" => DATA <= x"EE";
when x"C74" => DATA <= x"09";
when x"C75" => DATA <= x"80";
when x"C76" => DATA <= x"85";
when x"C77" => DATA <= x"EE";
when x"C78" => DATA <= x"A5";
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when x"C7A" => DATA <= x"60";
when x"C7B" => DATA <= x"20";
when x"C7C" => DATA <= x"E3";
when x"C7D" => DATA <= x"EC";
when x"C7E" => DATA <= x"20";
when x"C7F" => DATA <= x"F8";
when x"C80" => DATA <= x"EB";
when x"C81" => DATA <= x"20";
when x"C82" => DATA <= x"88";
when x"C83" => DATA <= x"EE";
when x"C84" => DATA <= x"A5";
when x"C85" => DATA <= x"EE";
when x"C86" => DATA <= x"09";
when x"C87" => DATA <= x"80";
when x"C88" => DATA <= x"85";
when x"C89" => DATA <= x"EE";
when x"C8A" => DATA <= x"60";
when x"C8B" => DATA <= x"A5";
when x"C8C" => DATA <= x"EE";
when x"C8D" => DATA <= x"20";
when x"C8E" => DATA <= x"AA";
when x"C8F" => DATA <= x"ED";
when x"C90" => DATA <= x"20";
when x"C91" => DATA <= x"E3";
when x"C92" => DATA <= x"EC";
when x"C93" => DATA <= x"A5";
when x"C94" => DATA <= x"A3";
when x"C95" => DATA <= x"4A";
when x"C96" => DATA <= x"66";
when x"C97" => DATA <= x"FD";
when x"C98" => DATA <= x"18";
when x"C99" => DATA <= x"65";
when x"C9A" => DATA <= x"84";
when x"C9B" => DATA <= x"85";
when x"C9C" => DATA <= x"84";
when x"C9D" => DATA <= x"A5";
when x"C9E" => DATA <= x"A2";
when x"C9F" => DATA <= x"29";
when x"CA0" => DATA <= x"0F";
when x"CA1" => DATA <= x"F0";
when x"CA2" => DATA <= x"04";
when x"CA3" => DATA <= x"69";
when x"CA4" => DATA <= x"80";
when x"CA5" => DATA <= x"85";
when x"CA6" => DATA <= x"84";
when x"CA7" => DATA <= x"A5";
when x"CA8" => DATA <= x"85";
when x"CA9" => DATA <= x"69";
when x"CAA" => DATA <= x"00";
when x"CAB" => DATA <= x"85";
when x"CAC" => DATA <= x"85";
when x"CAD" => DATA <= x"A5";
when x"CAE" => DATA <= x"86";
when x"CAF" => DATA <= x"69";
when x"CB0" => DATA <= x"00";
when x"CB1" => DATA <= x"85";
when x"CB2" => DATA <= x"86";
when x"CB3" => DATA <= x"60";
when x"CB4" => DATA <= x"E8";
when x"CB5" => DATA <= x"86";
when x"CB6" => DATA <= x"84";
when x"CB7" => DATA <= x"D0";
when x"CB8" => DATA <= x"01";
when x"CB9" => DATA <= x"C8";
when x"CBA" => DATA <= x"84";
when x"CBB" => DATA <= x"85";
when x"CBC" => DATA <= x"A9";
when x"CBD" => DATA <= x"00";
when x"CBE" => DATA <= x"85";
when x"CBF" => DATA <= x"86";
when x"CC0" => DATA <= x"85";
when x"CC1" => DATA <= x"87";
when x"CC2" => DATA <= x"85";
when x"CC3" => DATA <= x"88";
when x"CC4" => DATA <= x"A2";
when x"CC5" => DATA <= x"04";
when x"CC6" => DATA <= x"46";
when x"CC7" => DATA <= x"85";
when x"CC8" => DATA <= x"66";
when x"CC9" => DATA <= x"84";
when x"CCA" => DATA <= x"66";
when x"CCB" => DATA <= x"87";
when x"CCC" => DATA <= x"CA";
when x"CCD" => DATA <= x"D0";
when x"CCE" => DATA <= x"F7";
when x"CCF" => DATA <= x"46";
when x"CD0" => DATA <= x"85";
when x"CD1" => DATA <= x"66";
when x"CD2" => DATA <= x"84";
when x"CD3" => DATA <= x"26";
when x"CD4" => DATA <= x"88";
when x"CD5" => DATA <= x"18";
when x"CD6" => DATA <= x"A5";
when x"CD7" => DATA <= x"87";
when x"CD8" => DATA <= x"69";
when x"CD9" => DATA <= x"00";
when x"CDA" => DATA <= x"85";
when x"CDB" => DATA <= x"87";
when x"CDC" => DATA <= x"A5";
when x"CDD" => DATA <= x"88";
when x"CDE" => DATA <= x"69";
when x"CDF" => DATA <= x"23";
when x"CE0" => DATA <= x"85";
when x"CE1" => DATA <= x"88";
when x"CE2" => DATA <= x"60";
when x"CE3" => DATA <= x"A9";
when x"CE4" => DATA <= x"00";
when x"CE5" => DATA <= x"85";
when x"CE6" => DATA <= x"84";
when x"CE7" => DATA <= x"85";
when x"CE8" => DATA <= x"85";
when x"CE9" => DATA <= x"85";
when x"CEA" => DATA <= x"86";
when x"CEB" => DATA <= x"85";
when x"CEC" => DATA <= x"8B";
when x"CED" => DATA <= x"A5";
when x"CEE" => DATA <= x"83";
when x"CEF" => DATA <= x"85";
when x"CF0" => DATA <= x"8A";
when x"CF1" => DATA <= x"A5";
when x"CF2" => DATA <= x"82";
when x"CF3" => DATA <= x"85";
when x"CF4" => DATA <= x"89";
when x"CF5" => DATA <= x"20";
when x"CF6" => DATA <= x"1A";
when x"CF7" => DATA <= x"ED";
when x"CF8" => DATA <= x"20";
when x"CF9" => DATA <= x"2A";
when x"CFA" => DATA <= x"ED";
when x"CFB" => DATA <= x"20";
when x"CFC" => DATA <= x"1A";
when x"CFD" => DATA <= x"ED";
when x"CFE" => DATA <= x"20";
when x"CFF" => DATA <= x"2A";
when x"D00" => DATA <= x"ED";
when x"D01" => DATA <= x"20";
when x"D02" => DATA <= x"23";
when x"D03" => DATA <= x"ED";
when x"D04" => DATA <= x"20";
when x"D05" => DATA <= x"2A";
when x"D06" => DATA <= x"ED";
when x"D07" => DATA <= x"18";
when x"D08" => DATA <= x"A9";
when x"D09" => DATA <= x"20";
when x"D0A" => DATA <= x"65";
when x"D0B" => DATA <= x"84";
when x"D0C" => DATA <= x"85";
when x"D0D" => DATA <= x"84";
when x"D0E" => DATA <= x"A9";
when x"D0F" => DATA <= x"00";
when x"D10" => DATA <= x"65";
when x"D11" => DATA <= x"85";
when x"D12" => DATA <= x"85";
when x"D13" => DATA <= x"85";
when x"D14" => DATA <= x"A9";
when x"D15" => DATA <= x"00";
when x"D16" => DATA <= x"65";
when x"D17" => DATA <= x"86";
when x"D18" => DATA <= x"85";
when x"D19" => DATA <= x"86";
when x"D1A" => DATA <= x"A2";
when x"D1B" => DATA <= x"03";
when x"D1C" => DATA <= x"20";
when x"D1D" => DATA <= x"23";
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when x"D35" => DATA <= x"85";
when x"D36" => DATA <= x"85";
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when x"EBB" => DATA <= x"58";
when x"EBC" => DATA <= x"20";
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when x"EC0" => DATA <= x"03";
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when x"EC3" => DATA <= x"EE";
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when x"EC5" => DATA <= x"FE";
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when x"ECD" => DATA <= x"4F";
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when x"ED0" => DATA <= x"52";
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when x"ED2" => DATA <= x"41";
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when x"ED4" => DATA <= x"59";
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when x"EF2" => DATA <= x"EA";
when x"EF3" => DATA <= x"EA";
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when x"EFA" => DATA <= x"03";
when x"EFB" => DATA <= x"8C";
when x"EFC" => DATA <= x"D5";
when x"EFD" => DATA <= x"03";
when x"EFE" => DATA <= x"A0";
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when x"F00" => DATA <= x"48";
when x"F01" => DATA <= x"29";
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when x"F03" => DATA <= x"8D";
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when x"F0C" => DATA <= x"00";
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when x"F0F" => DATA <= x"40";
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when x"F12" => DATA <= x"B8";
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when x"F15" => DATA <= x"68";
when x"F16" => DATA <= x"2A";
when x"F17" => DATA <= x"88";
when x"F18" => DATA <= x"D0";
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when x"F1A" => DATA <= x"AC";
when x"F1B" => DATA <= x"D5";
when x"F1C" => DATA <= x"03";
when x"F1D" => DATA <= x"AE";
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when x"F20" => DATA <= x"60";
when x"F21" => DATA <= x"A2";
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when x"F23" => DATA <= x"86";
when x"F24" => DATA <= x"04";
when x"F25" => DATA <= x"A9";
when x"F26" => DATA <= x"00";
when x"F27" => DATA <= x"95";
when x"F28" => DATA <= x"16";
when x"F29" => DATA <= x"95";
when x"F2A" => DATA <= x"25";
when x"F2B" => DATA <= x"95";
when x"F2C" => DATA <= x"34";
when x"F2D" => DATA <= x"95";
when x"F2E" => DATA <= x"43";
when x"F2F" => DATA <= x"A9";
when x"F30" => DATA <= x"40";
when x"F31" => DATA <= x"20";
when x"F32" => DATA <= x"6E";
when x"F33" => DATA <= x"EF";
when x"F34" => DATA <= x"C9";
when x"F35" => DATA <= x"01";
when x"F36" => DATA <= x"D0";
when x"F37" => DATA <= x"18";
when x"F38" => DATA <= x"A9";
when x"F39" => DATA <= x"69";
when x"F3A" => DATA <= x"20";
when x"F3B" => DATA <= x"6E";
when x"F3C" => DATA <= x"EF";
when x"F3D" => DATA <= x"F0";
when x"F3E" => DATA <= x"13";
when x"F3F" => DATA <= x"A9";
when x"F40" => DATA <= x"00";
when x"F41" => DATA <= x"8D";
when x"F42" => DATA <= x"D1";
when x"F43" => DATA <= x"03";
when x"F44" => DATA <= x"A9";
when x"F45" => DATA <= x"41";
when x"F46" => DATA <= x"20";
when x"F47" => DATA <= x"6E";
when x"F48" => DATA <= x"EF";
when x"F49" => DATA <= x"F0";
when x"F4A" => DATA <= x"07";
when x"F4B" => DATA <= x"CE";
when x"F4C" => DATA <= x"D1";
when x"F4D" => DATA <= x"03";
when x"F4E" => DATA <= x"D0";
when x"F4F" => DATA <= x"F4";
when x"F50" => DATA <= x"18";
when x"F51" => DATA <= x"60";
when x"F52" => DATA <= x"38";
when x"F53" => DATA <= x"60";
when x"F54" => DATA <= x"A9";
when x"F55" => DATA <= x"E0";
when x"F56" => DATA <= x"8D";
when x"F57" => DATA <= x"00";
when x"F58" => DATA <= x"B8";
when x"F59" => DATA <= x"A9";
when x"F5A" => DATA <= x"FE";
when x"F5B" => DATA <= x"8D";
when x"F5C" => DATA <= x"02";
when x"F5D" => DATA <= x"B8";
when x"F5E" => DATA <= x"A9";
when x"F5F" => DATA <= x"E0";
when x"F60" => DATA <= x"A2";
when x"F61" => DATA <= x"A0";
when x"F62" => DATA <= x"A0";
when x"F63" => DATA <= x"58";
when x"F64" => DATA <= x"8D";
when x"F65" => DATA <= x"00";
when x"F66" => DATA <= x"B8";
when x"F67" => DATA <= x"8E";
when x"F68" => DATA <= x"00";
when x"F69" => DATA <= x"B8";
when x"F6A" => DATA <= x"88";
when x"F6B" => DATA <= x"D0";
when x"F6C" => DATA <= x"F7";
when x"F6D" => DATA <= x"60";
when x"F6E" => DATA <= x"48";
when x"F6F" => DATA <= x"AD";
when x"F70" => DATA <= x"2B";
when x"F71" => DATA <= x"02";
when x"F72" => DATA <= x"F0";
when x"F73" => DATA <= x"34";
when x"F74" => DATA <= x"20";
when x"F75" => DATA <= x"AB";
when x"F76" => DATA <= x"EF";
when x"F77" => DATA <= x"20";
when x"F78" => DATA <= x"FB";
when x"F79" => DATA <= x"EF";
when x"F7A" => DATA <= x"68";
when x"F7B" => DATA <= x"20";
when x"F7C" => DATA <= x"FD";
when x"F7D" => DATA <= x"EF";
when x"F7E" => DATA <= x"A6";
when x"F7F" => DATA <= x"04";
when x"F80" => DATA <= x"B5";
when x"F81" => DATA <= x"43";
when x"F82" => DATA <= x"20";
when x"F83" => DATA <= x"FD";
when x"F84" => DATA <= x"EF";
when x"F85" => DATA <= x"B5";
when x"F86" => DATA <= x"34";
when x"F87" => DATA <= x"20";
when x"F88" => DATA <= x"FD";
when x"F89" => DATA <= x"EF";
when x"F8A" => DATA <= x"B5";
when x"F8B" => DATA <= x"25";
when x"F8C" => DATA <= x"20";
when x"F8D" => DATA <= x"FD";
when x"F8E" => DATA <= x"EF";
when x"F8F" => DATA <= x"B5";
when x"F90" => DATA <= x"16";
when x"F91" => DATA <= x"20";
when x"F92" => DATA <= x"FD";
when x"F93" => DATA <= x"EF";
when x"F94" => DATA <= x"A9";
when x"F95" => DATA <= x"95";
when x"F96" => DATA <= x"20";
when x"F97" => DATA <= x"FD";
when x"F98" => DATA <= x"EF";
when x"F99" => DATA <= x"A0";
when x"F9A" => DATA <= x"00";
when x"F9B" => DATA <= x"88";
when x"F9C" => DATA <= x"F0";
when x"F9D" => DATA <= x"07";
when x"F9E" => DATA <= x"20";
when x"F9F" => DATA <= x"FB";
when x"FA0" => DATA <= x"EF";
when x"FA1" => DATA <= x"29";
when x"FA2" => DATA <= x"FF";
when x"FA3" => DATA <= x"30";
when x"FA4" => DATA <= x"F6";
when x"FA5" => DATA <= x"C9";
when x"FA6" => DATA <= x"00";
when x"FA7" => DATA <= x"60";
when x"FA8" => DATA <= x"4C";
when x"FA9" => DATA <= x"62";
when x"FAA" => DATA <= x"EE";
when x"FAB" => DATA <= x"A9";
when x"FAC" => DATA <= x"80";
when x"FAD" => DATA <= x"D0";
when x"FAE" => DATA <= x"02";
when x"FAF" => DATA <= x"A9";
when x"FB0" => DATA <= x"A0";
when x"FB1" => DATA <= x"2C";
when x"FB2" => DATA <= x"2B";
when x"FB3" => DATA <= x"02";
when x"FB4" => DATA <= x"30";
when x"FB5" => DATA <= x"08";
when x"FB6" => DATA <= x"8D";
when x"FB7" => DATA <= x"00";
when x"FB8" => DATA <= x"B8";
when x"FB9" => DATA <= x"A2";
when x"FBA" => DATA <= x"00";
when x"FBB" => DATA <= x"CA";
when x"FBC" => DATA <= x"D0";
when x"FBD" => DATA <= x"FD";
when x"FBE" => DATA <= x"60";
when x"FBF" => DATA <= x"A0";
when x"FC0" => DATA <= x"00";
when x"FC1" => DATA <= x"8D";
when x"FC2" => DATA <= x"D1";
when x"FC3" => DATA <= x"03";
when x"FC4" => DATA <= x"88";
when x"FC5" => DATA <= x"F0";
when x"FC6" => DATA <= x"09";
when x"FC7" => DATA <= x"20";
when x"FC8" => DATA <= x"FB";
when x"FC9" => DATA <= x"EF";
when x"FCA" => DATA <= x"CD";
when x"FCB" => DATA <= x"D1";
when x"FCC" => DATA <= x"03";
when x"FCD" => DATA <= x"D0";
when x"FCE" => DATA <= x"F5";
when x"FCF" => DATA <= x"60";
when x"FD0" => DATA <= x"20";
when x"FD1" => DATA <= x"D1";
when x"FD2" => DATA <= x"F7";
when x"FD3" => DATA <= x"20";
when x"FD4" => DATA <= x"20";
when x"FD5" => DATA <= x"52";
when x"FD6" => DATA <= x"45";
when x"FD7" => DATA <= x"53";
when x"FD8" => DATA <= x"50";
when x"FD9" => DATA <= x"4F";
when x"FDA" => DATA <= x"4E";
when x"FDB" => DATA <= x"53";
when x"FDC" => DATA <= x"45";
when x"FDD" => DATA <= x"20";
when x"FDE" => DATA <= x"45";
when x"FDF" => DATA <= x"52";
when x"FE0" => DATA <= x"52";
when x"FE1" => DATA <= x"4F";
when x"FE2" => DATA <= x"52";
when x"FE3" => DATA <= x"EA";
when x"FE4" => DATA <= x"00";
when x"FE5" => DATA <= x"A6";
when x"FE6" => DATA <= x"04";
when x"FE7" => DATA <= x"A5";
when x"FE8" => DATA <= x"84";
when x"FE9" => DATA <= x"0A";
when x"FEA" => DATA <= x"95";
when x"FEB" => DATA <= x"25";
when x"FEC" => DATA <= x"A5";
when x"FED" => DATA <= x"85";
when x"FEE" => DATA <= x"2A";
when x"FEF" => DATA <= x"95";
when x"FF0" => DATA <= x"34";
when x"FF1" => DATA <= x"A5";
when x"FF2" => DATA <= x"86";
when x"FF3" => DATA <= x"2A";
when x"FF4" => DATA <= x"95";
when x"FF5" => DATA <= x"43";
when x"FF6" => DATA <= x"A9";
when x"FF7" => DATA <= x"00";
when x"FF8" => DATA <= x"95";
when x"FF9" => DATA <= x"16";
when x"FFA" => DATA <= x"60";
when x"FFB" => DATA <= x"A9";
when x"FFC" => DATA <= x"FF";
when x"FFD" => DATA <= x"6C";
when x"FFE" => DATA <= x"3E";
when x"FFF" => DATA <= x"02";
when others => DATA <= (others => '0');
end case;
end process;
end RTL;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
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`protect key_block
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|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
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`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 17760)
`protect data_block
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|
`protect begin_protected
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`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
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`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
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`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 16496)
`protect data_block
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`protect end_protected
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ece324_latency_tracker is
port( response : in std_logic;
pulse : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
missed : out std_logic_vector(15 downto 0);
latency : out std_logic_vector (15 downto 0)
);
end ece324_latency_tracker;
architecture Behavioral of ece324_latency_tracker is
signal responded, pulsed, enabled : std_logic;
signal respondedReset, pulsedReset : std_logic;
signal count : std_logic_vector(15 downto 0);
signal misses : std_logic_vector(15 downto 0);
signal currentLatency : std_logic_vector(15 downto 0);
begin
-- sync response to the clock
syncResponse: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(response = '1' and respondedReset = '0') then
responded <= '1';
respondedReset <= '1';
elsif(responded = '1') then
responded <= '0';
elsif(response = '0') then
respondedReset <= '0';
end if;
end if;
end process;
-- sync pulse to the clock
syncPulse: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(pulse = '1' and pulsedReset = '0') then
pulsed <= '1';
pulsedReset <= '1';
elsif(pulsed = '1') then
pulsed <= '0';
elsif(pulse = '0') then
pulsedReset <= '0';
end if;
end if;
end process;
-- enable the counter on a pulse
enabler: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(responded = '1' or reset = '1') then
enabled <= '0';
else
enabled <= pulsed or enabled;
end if;
end if;
end process;
-- latency counter
latcount: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(responded = '1' or reset = '1') then
count <= "0000000000000000";
elsif(enabled = '1' and enable = '1') then
count <= count + 1;
end if;
end if;
end process;
-- missed pulses counter
misscount: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(reset = '1') then
misses <= "0000000000000000";
elsif(enabled = '1' and enable = '1' and pulsed = '1') then
misses <= misses + 1;
end if;
end if;
end process;
-- maximum latency register
latregister: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(reset = '1') then
currentLatency <= "0000000000000000";
elsif(count > currentLatency) then
currentLatency <= count;
end if;
end if;
end process;
-- assign our outputs
missed <= misses;
latency <= currentLatency;
end Behavioral; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity ece324_latency_tracker is
port( response : in std_logic;
pulse : in std_logic;
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
missed : out std_logic_vector(15 downto 0);
latency : out std_logic_vector (15 downto 0)
);
end ece324_latency_tracker;
architecture Behavioral of ece324_latency_tracker is
signal responded, pulsed, enabled : std_logic;
signal respondedReset, pulsedReset : std_logic;
signal count : std_logic_vector(15 downto 0);
signal misses : std_logic_vector(15 downto 0);
signal currentLatency : std_logic_vector(15 downto 0);
begin
-- sync response to the clock
syncResponse: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(response = '1' and respondedReset = '0') then
responded <= '1';
respondedReset <= '1';
elsif(responded = '1') then
responded <= '0';
elsif(response = '0') then
respondedReset <= '0';
end if;
end if;
end process;
-- sync pulse to the clock
syncPulse: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(pulse = '1' and pulsedReset = '0') then
pulsed <= '1';
pulsedReset <= '1';
elsif(pulsed = '1') then
pulsed <= '0';
elsif(pulse = '0') then
pulsedReset <= '0';
end if;
end if;
end process;
-- enable the counter on a pulse
enabler: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(responded = '1' or reset = '1') then
enabled <= '0';
else
enabled <= pulsed or enabled;
end if;
end if;
end process;
-- latency counter
latcount: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(responded = '1' or reset = '1') then
count <= "0000000000000000";
elsif(enabled = '1' and enable = '1') then
count <= count + 1;
end if;
end if;
end process;
-- missed pulses counter
misscount: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(reset = '1') then
misses <= "0000000000000000";
elsif(enabled = '1' and enable = '1' and pulsed = '1') then
misses <= misses + 1;
end if;
end if;
end process;
-- maximum latency register
latregister: process(clk)
begin
if(clk'EVENT and clk = '1') then
if(reset = '1') then
currentLatency <= "0000000000000000";
elsif(count > currentLatency) then
currentLatency <= count;
end if;
end if;
end process;
-- assign our outputs
missed <= misses;
latency <= currentLatency;
end Behavioral; |
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc149.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00149ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p14n01i00149ent;
ARCHITECTURE c04s03b02x02p14n01i00149arch OF c04s03b02x02p14n01i00149ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a11: INTEGER := 57;
VARIABLE a12: INTEGER := 57;
VARIABLE a13: INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>convb(INTEGER'HIGH),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
IF (a1 = 102) THEN
ASSERT false REPORT "PASS: Function call uses function to convert type of actual" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(add=>convb(-33),i3=>2,i1=>a3,i2=>a2,i4=>a11);
WAIT FOR 1 ns;
IF (a11 = 7) THEN
ASSERT false REPORT "PASS: Function call uses function to convert actual to false" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(add=>TRUE,i3=>conv1('1'),i2=>conv1('1'),i1=>conv1('0'),i4=>a12);
WAIT FOR 1 ns;
IF (a12 = 67) THEN
ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(15,5,5,convb(-1),a13);
WAIT FOR 1 ns;
IF (a13 = 5) THEN
ASSERT false REPORT "PASS: No named association used" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
assert NOT( a1 = 102 and
a11= 7 and
a12= 67 and
a13= 5 )
report "***PASSED TEST: c04s03b02x02p14n01i00149"
severity NOTE;
assert ( a1 = 102 and
a11= 7 and
a12= 67 and
a13= 5 )
report "***FAILED TEST: c04s03b02x02p14n01i00149 - Function call uses function to convert type of actual."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00149arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc149.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00149ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p14n01i00149ent;
ARCHITECTURE c04s03b02x02p14n01i00149arch OF c04s03b02x02p14n01i00149ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a11: INTEGER := 57;
VARIABLE a12: INTEGER := 57;
VARIABLE a13: INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>convb(INTEGER'HIGH),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
IF (a1 = 102) THEN
ASSERT false REPORT "PASS: Function call uses function to convert type of actual" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(add=>convb(-33),i3=>2,i1=>a3,i2=>a2,i4=>a11);
WAIT FOR 1 ns;
IF (a11 = 7) THEN
ASSERT false REPORT "PASS: Function call uses function to convert actual to false" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(add=>TRUE,i3=>conv1('1'),i2=>conv1('1'),i1=>conv1('0'),i4=>a12);
WAIT FOR 1 ns;
IF (a12 = 67) THEN
ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(15,5,5,convb(-1),a13);
WAIT FOR 1 ns;
IF (a13 = 5) THEN
ASSERT false REPORT "PASS: No named association used" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
assert NOT( a1 = 102 and
a11= 7 and
a12= 67 and
a13= 5 )
report "***PASSED TEST: c04s03b02x02p14n01i00149"
severity NOTE;
assert ( a1 = 102 and
a11= 7 and
a12= 67 and
a13= 5 )
report "***FAILED TEST: c04s03b02x02p14n01i00149 - Function call uses function to convert type of actual."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00149arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc149.vhd,v 1.2 2001-10-26 16:29:41 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p14n01i00149ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p14n01i00149ent;
ARCHITECTURE c04s03b02x02p14n01i00149arch OF c04s03b02x02p14n01i00149ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a11: INTEGER := 57;
VARIABLE a12: INTEGER := 57;
VARIABLE a13: INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>convb(INTEGER'HIGH),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
IF (a1 = 102) THEN
ASSERT false REPORT "PASS: Function call uses function to convert type of actual" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(add=>convb(-33),i3=>2,i1=>a3,i2=>a2,i4=>a11);
WAIT FOR 1 ns;
IF (a11 = 7) THEN
ASSERT false REPORT "PASS: Function call uses function to convert actual to false" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(add=>TRUE,i3=>conv1('1'),i2=>conv1('1'),i1=>conv1('0'),i4=>a12);
WAIT FOR 1 ns;
IF (a12 = 67) THEN
ASSERT false REPORT "PASS: Function call uses same actual twice" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
addup(15,5,5,convb(-1),a13);
WAIT FOR 1 ns;
IF (a13 = 5) THEN
ASSERT false REPORT "PASS: No named association used" SEVERITY note;
ELSE
ASSERT false REPORT "FAIL: Function call fails" SEVERITY note;
END IF;
WAIT FOR 1 ns;
assert NOT( a1 = 102 and
a11= 7 and
a12= 67 and
a13= 5 )
report "***PASSED TEST: c04s03b02x02p14n01i00149"
severity NOTE;
assert ( a1 = 102 and
a11= 7 and
a12= 67 and
a13= 5 )
report "***FAILED TEST: c04s03b02x02p14n01i00149 - Function call uses function to convert type of actual."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p14n01i00149arch;
|
-- -------------------------------------------------------------
--
-- File Name: hdlsrc/ifft_16_bit/RADIX22FFT_SDNF2_4_block.vhd
-- Created: 2017-03-28 01:00:37
--
-- Generated by MATLAB 9.1 and HDL Coder 3.9
--
-- -------------------------------------------------------------
-- -------------------------------------------------------------
--
-- Module: RADIX22FFT_SDNF2_4_block
-- Source Path: ifft_16_bit/IFFT HDL Optimized/RADIX22FFT_SDNF2_4
-- Hierarchy Level: 2
--
-- -------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.std_logic_1164.ALL;
USE IEEE.numeric_std.ALL;
ENTITY RADIX22FFT_SDNF2_4_block IS
PORT( clk : IN std_logic;
reset : IN std_logic;
enb : IN std_logic;
rotate_3 : IN std_logic; -- ufix1
dout_2_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_2_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_re : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_im : IN std_logic_vector(16 DOWNTO 0); -- sfix17
dout_1_vld : IN std_logic;
softReset : IN std_logic;
dout_3_re : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_3_im : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_re_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_im_1 : OUT std_logic_vector(16 DOWNTO 0); -- sfix17
dout_4_vld : OUT std_logic
);
END RADIX22FFT_SDNF2_4_block;
ARCHITECTURE rtl OF RADIX22FFT_SDNF2_4_block IS
-- Signals
SIGNAL dout_2_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_2_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_re_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_im_signed : signed(16 DOWNTO 0); -- sfix17
SIGNAL Radix22ButterflyG2_NF_din_vld_dly : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_din_vld_dly_next : std_logic;
SIGNAL Radix22ButterflyG2_NF_btf1_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf1_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_re_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL Radix22ButterflyG2_NF_btf2_im_reg_next : signed(17 DOWNTO 0); -- sfix18
SIGNAL dout_3_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_3_im_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_re_tmp : signed(16 DOWNTO 0); -- sfix17
SIGNAL dout_4_im_tmp : signed(16 DOWNTO 0); -- sfix17
BEGIN
dout_2_re_signed <= signed(dout_2_re);
dout_2_im_signed <= signed(dout_2_im);
dout_4_re_signed <= signed(dout_4_re);
dout_4_im_signed <= signed(dout_4_im);
-- Radix22ButterflyG2_NF
Radix22ButterflyG2_NF_process : PROCESS (clk, reset)
BEGIN
IF reset = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= '0';
Radix22ButterflyG2_NF_btf1_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf1_im_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_re_reg <= to_signed(16#00000#, 18);
Radix22ButterflyG2_NF_btf2_im_reg <= to_signed(16#00000#, 18);
ELSIF clk'EVENT AND clk = '1' THEN
IF enb = '1' THEN
Radix22ButterflyG2_NF_din_vld_dly <= Radix22ButterflyG2_NF_din_vld_dly_next;
Radix22ButterflyG2_NF_btf1_re_reg <= Radix22ButterflyG2_NF_btf1_re_reg_next;
Radix22ButterflyG2_NF_btf1_im_reg <= Radix22ButterflyG2_NF_btf1_im_reg_next;
Radix22ButterflyG2_NF_btf2_re_reg <= Radix22ButterflyG2_NF_btf2_re_reg_next;
Radix22ButterflyG2_NF_btf2_im_reg <= Radix22ButterflyG2_NF_btf2_im_reg_next;
END IF;
END IF;
END PROCESS Radix22ButterflyG2_NF_process;
Radix22ButterflyG2_NF_output : PROCESS (Radix22ButterflyG2_NF_din_vld_dly, Radix22ButterflyG2_NF_btf1_re_reg,
Radix22ButterflyG2_NF_btf1_im_reg, Radix22ButterflyG2_NF_btf2_re_reg,
Radix22ButterflyG2_NF_btf2_im_reg, dout_2_re_signed, dout_2_im_signed,
dout_4_re_signed, dout_4_im_signed, dout_1_vld, rotate_3)
VARIABLE sra_temp : signed(17 DOWNTO 0);
VARIABLE sra_temp_0 : signed(17 DOWNTO 0);
VARIABLE sra_temp_1 : signed(17 DOWNTO 0);
VARIABLE sra_temp_2 : signed(17 DOWNTO 0);
BEGIN
Radix22ButterflyG2_NF_btf1_re_reg_next <= Radix22ButterflyG2_NF_btf1_re_reg;
Radix22ButterflyG2_NF_btf1_im_reg_next <= Radix22ButterflyG2_NF_btf1_im_reg;
Radix22ButterflyG2_NF_btf2_re_reg_next <= Radix22ButterflyG2_NF_btf2_re_reg;
Radix22ButterflyG2_NF_btf2_im_reg_next <= Radix22ButterflyG2_NF_btf2_im_reg;
Radix22ButterflyG2_NF_din_vld_dly_next <= dout_1_vld;
IF rotate_3 /= '0' THEN
IF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_2_re_signed, 18) + resize(dout_4_im_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_2_re_signed, 18) - resize(dout_4_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_2_im_signed, 18) + resize(dout_4_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_2_im_signed, 18) - resize(dout_4_re_signed, 18);
END IF;
ELSIF dout_1_vld = '1' THEN
Radix22ButterflyG2_NF_btf1_re_reg_next <= resize(dout_2_re_signed, 18) + resize(dout_4_re_signed, 18);
Radix22ButterflyG2_NF_btf2_re_reg_next <= resize(dout_2_re_signed, 18) - resize(dout_4_re_signed, 18);
Radix22ButterflyG2_NF_btf1_im_reg_next <= resize(dout_2_im_signed, 18) + resize(dout_4_im_signed, 18);
Radix22ButterflyG2_NF_btf2_im_reg_next <= resize(dout_2_im_signed, 18) - resize(dout_4_im_signed, 18);
END IF;
sra_temp := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_re_reg, 1);
dout_3_re_tmp <= sra_temp(16 DOWNTO 0);
sra_temp_0 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf1_im_reg, 1);
dout_3_im_tmp <= sra_temp_0(16 DOWNTO 0);
sra_temp_1 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_re_reg, 1);
dout_4_re_tmp <= sra_temp_1(16 DOWNTO 0);
sra_temp_2 := SHIFT_RIGHT(Radix22ButterflyG2_NF_btf2_im_reg, 1);
dout_4_im_tmp <= sra_temp_2(16 DOWNTO 0);
dout_4_vld <= Radix22ButterflyG2_NF_din_vld_dly;
END PROCESS Radix22ButterflyG2_NF_output;
dout_3_re <= std_logic_vector(dout_3_re_tmp);
dout_3_im <= std_logic_vector(dout_3_im_tmp);
dout_4_re_1 <= std_logic_vector(dout_4_re_tmp);
dout_4_im_1 <= std_logic_vector(dout_4_im_tmp);
END rtl;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer: Peter Fall
--
-- Create Date: 16:20:42 06/01/2011
-- Design Name:
-- Module Name: IPv4 - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
-- handle simple IP RX and TX
-- doesnt handle seg & reass
-- dest MAC addr resolution through ARP layer
-- Handle IPv4 protocol
-- Respond to ARP requests and replies
-- Ignore pkts that are not IP
-- Ignore pkts that are not addressed to us--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Revision 0.02 - separated RX and TX clocks
-- Revision 0.03 - Added mac_data_out_first
-- Additional Comments:
--
----------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.axi.all;
use work.ipv4_types.all;
use work.arp_types.all;
entity IPv4 is
Port (
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
ip_rx : out ipv4_rx_type;
-- system control signals
rx_clk : in STD_LOGIC;
tx_clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- system status signals
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC; -- indicates last data in frame
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
end IPv4;
architecture structural of IPv4 is
COMPONENT IPv4_TX
PORT(
-- IP Layer signals
ip_tx_start : in std_logic;
ip_tx : in ipv4_tx_type; -- IP tx cxns
ip_tx_result : out std_logic_vector (1 downto 0); -- tx status (changes during transmission)
ip_tx_data_out_ready : out std_logic; -- indicates IP TX is ready to take data
-- system signals
clk : in STD_LOGIC; -- same clock used to clock mac data and ip data
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
our_mac_address : in std_logic_vector (47 downto 0);
-- ARP lookup signals
arp_req_req : out arp_req_req_type;
arp_req_rslt : in arp_req_rslt_type;
-- MAC layer TX signals
mac_tx_req : out std_logic; -- indicates that ip wants access to channel (stays up for as long as tx)
mac_tx_granted : in std_logic; -- indicates that access to channel has been granted
mac_data_out_ready : in std_logic; -- indicates system ready to consume data
mac_data_out_valid : out std_logic; -- indicates data out is valid
mac_data_out_first : out std_logic; -- with data out valid indicates the first byte of a frame
mac_data_out_last : out std_logic; -- with data out valid indicates the last byte of a frame
mac_data_out : out std_logic_vector (7 downto 0) -- ethernet frame (from dst mac addr through to last byte of frame)
);
END COMPONENT;
COMPONENT IPv4_RX
PORT(
-- IP Layer signals
ip_rx : out ipv4_rx_type;
ip_rx_start : out std_logic; -- indicates receipt of ip frame.
-- system signals
clk : in STD_LOGIC;
reset : in STD_LOGIC;
our_ip_address : in STD_LOGIC_VECTOR (31 downto 0);
rx_pkt_count : out STD_LOGIC_VECTOR(7 downto 0); -- number of IP pkts received for us
-- MAC layer RX signals
mac_data_in : in STD_LOGIC_VECTOR (7 downto 0); -- ethernet frame (from dst mac addr through to last byte of frame)
mac_data_in_valid : in STD_LOGIC; -- indicates data_in valid on clock
mac_data_in_last : in STD_LOGIC -- indicates last data in frame
);
END COMPONENT;
begin
TX : IPv4_TX PORT MAP (
ip_tx_start => ip_tx_start,
ip_tx => ip_tx,
ip_tx_result => ip_tx_result,
ip_tx_data_out_ready=> ip_tx_data_out_ready,
clk => tx_clk,
reset => reset,
our_ip_address => our_ip_address,
our_mac_address => our_mac_address,
arp_req_req => arp_req_req,
arp_req_rslt => arp_req_rslt,
mac_tx_req => mac_tx_req,
mac_tx_granted => mac_tx_granted,
mac_data_out_ready => mac_data_out_ready,
mac_data_out_valid => mac_data_out_valid,
mac_data_out_first => mac_data_out_first,
mac_data_out_last => mac_data_out_last,
mac_data_out => mac_data_out
);
RX : IPv4_RX PORT MAP (
ip_rx => ip_rx,
ip_rx_start => ip_rx_start,
clk => rx_clk,
reset => reset,
our_ip_address => our_ip_address,
rx_pkt_count => rx_pkt_count,
mac_data_in => mac_data_in,
mac_data_in_valid => mac_data_in_valid,
mac_data_in_last => mac_data_in_last
);
end structural;
|
library ieee;
use ieee.std_logic_1164.all;
library work;
use work.pkg_6502_defs.all;
entity proc_core is
generic (
vector_page : std_logic_vector(15 downto 4) := X"FFF";
support_bcd : boolean := true );
port(
clock : in std_logic;
clock_en : in std_logic := '1';
reset : in std_logic;
ready : in std_logic := '1';
irq_n : in std_logic := '1';
nmi_n : in std_logic := '1';
so_n : in std_logic := '1';
carry : out std_logic;
sync_out : out std_logic;
interrupt_ack: out std_logic;
pc_out : out std_logic_vector(15 downto 0);
addr_out : out std_logic_vector(16 downto 0);
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
read_write_n : out std_logic );
end proc_core;
architecture structural of proc_core is
signal index_carry : std_logic;
signal pc_carry : std_logic;
signal branch_taken : boolean;
signal i_reg : std_logic_vector(7 downto 0);
signal d_reg : std_logic_vector(7 downto 0);
signal a_reg : std_logic_vector(7 downto 0);
signal x_reg : std_logic_vector(7 downto 0);
signal y_reg : std_logic_vector(7 downto 0);
signal s_reg : std_logic_vector(7 downto 0);
signal p_reg : std_logic_vector(7 downto 0);
signal latch_dreg : std_logic;
signal reg_update : std_logic;
signal flags_update : std_logic;
signal copy_d2p : std_logic;
signal sync : std_logic;
signal rwn : std_logic;
signal a_mux : t_amux;
signal pc_oper : t_pc_oper;
signal s_oper : t_sp_oper;
signal adl_oper : t_adl_oper;
signal adh_oper : t_adh_oper;
signal dout_mux : t_dout_mux;
signal alu_out : std_logic_vector(7 downto 0);
signal impl_out : std_logic_vector(7 downto 0);
signal mem_out : std_logic_vector(7 downto 0);
signal mem_n : std_logic;
signal mem_z : std_logic;
signal mem_c : std_logic;
signal set_a : std_logic;
signal set_x : std_logic;
signal set_y : std_logic;
signal set_s : std_logic;
signal vect_addr : std_logic_vector(3 downto 0);
signal interrupt : std_logic;
signal vectoring : std_logic;
signal nmi_done : std_logic;
signal set_i_flag : std_logic;
signal vect_sel : std_logic_vector(2 downto 1);
signal flags_imm : std_logic;
signal new_flags : std_logic_vector(7 downto 0);
signal n_out : std_logic;
signal v_out : std_logic;
signal c_out : std_logic;
signal z_out : std_logic;
signal d_out : std_logic;
signal i_out : std_logic;
signal a16 : std_logic;
attribute keep : string;
attribute keep of interrupt : signal is "true";
begin
carry <= p_reg(0);
new_flags(7) <= n_out;
new_flags(6) <= v_out;
new_flags(5) <= '1';
new_flags(4) <= p_reg(4);
new_flags(3) <= d_out;
new_flags(2) <= i_out;
new_flags(1) <= z_out;
new_flags(0) <= c_out;
ctrl: entity work.proc_control
port map (
clock => clock,
clock_en => clock_en,
ready => ready,
reset => reset,
interrupt => interrupt,
vectoring => vectoring,
taking_intr => interrupt_ack,
vect_sel => vect_sel,
nmi_done => nmi_done,
set_i_flag => set_i_flag,
vect_addr => vect_addr,
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
sync => sync,
latch_dreg => latch_dreg,
reg_update => reg_update,
flags_update => flags_update,
copy_d2p => copy_d2p,
a16 => a16,
rwn => rwn,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper );
oper: entity work.data_oper
generic map (
support_bcd => support_bcd )
port map (
inst => i_reg,
n_in => p_reg(7),
v_in => p_reg(6),
z_in => p_reg(1),
c_in => p_reg(0),
d_in => p_reg(3),
i_in => p_reg(2),
data_in => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
alu_out => alu_out,
mem_out => mem_out,
mem_c => mem_c,
mem_z => mem_z,
mem_n => mem_n,
impl_out => impl_out,
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
flags_imm => flags_imm,
n_out => n_out,
v_out => v_out,
z_out => z_out,
c_out => c_out,
d_out => d_out,
i_out => i_out );
regs: entity work.proc_registers
generic map (
vector_page => vector_page )
port map (
clock => clock,
clock_en => clock_en,
ready => ready,
reset => reset,
-- package pins
data_in => data_in,
data_out => data_out,
so_n => so_n,
-- data from "data_oper"
alu_data => alu_out,
mem_data => mem_out,
mem_c => mem_c,
mem_z => mem_z,
mem_n => mem_n,
new_flags => new_flags,
flags_imm => flags_imm,
-- from implied handler
set_a => set_a,
set_x => set_x,
set_y => set_y,
set_s => set_s,
set_data => impl_out,
-- from interrupt controller
vect_addr => vect_addr,
-- from processor state machine and decoder
sync => sync,
rwn => rwn,
latch_dreg => latch_dreg,
set_i_flag => set_i_flag,
vectoring => vectoring,
reg_update => reg_update,
flags_update => flags_update,
copy_d2p => copy_d2p,
a_mux => a_mux,
dout_mux => dout_mux,
pc_oper => pc_oper,
s_oper => s_oper,
adl_oper => adl_oper,
adh_oper => adh_oper,
-- outputs to processor state machine
i_reg => i_reg,
index_carry => index_carry,
pc_carry => pc_carry,
branch_taken => branch_taken,
-- register outputs
addr_out => addr_out(15 downto 0),
d_reg => d_reg,
a_reg => a_reg,
x_reg => x_reg,
y_reg => y_reg,
s_reg => s_reg,
p_reg => p_reg,
pc_out => pc_out );
intr: entity work.proc_interrupt
port map (
clock => clock,
clock_en => clock_en,
reset => reset,
irq_n => irq_n,
nmi_n => nmi_n,
i_flag => p_reg(2),
interrupt => interrupt,
nmi_done => nmi_done,
reset_done => set_i_flag,
vect_sel => vect_sel );
read_write_n <= rwn;
addr_out(16) <= a16;
sync_out <= sync;
end structural;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2697.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p05n01i02697ent IS
END c13s04b01x00p05n01i02697ent;
ARCHITECTURE c13s04b01x00p05n01i02697arch OF c13s04b01x00p05n01i02697ent IS
constant a : real := 2.34;
constant b : real := 2.3_4;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a=b )
report "***PASSED TEST: c13s04b01x00p05n01i02697"
severity NOTE;
assert ( a=b )
report "***FAILED TEST: c13s04b01x00p05n01i02697 - The underline character inserted between adjacent digits of a real literal should not affect the value of this abstract literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p05n01i02697arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2697.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p05n01i02697ent IS
END c13s04b01x00p05n01i02697ent;
ARCHITECTURE c13s04b01x00p05n01i02697arch OF c13s04b01x00p05n01i02697ent IS
constant a : real := 2.34;
constant b : real := 2.3_4;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a=b )
report "***PASSED TEST: c13s04b01x00p05n01i02697"
severity NOTE;
assert ( a=b )
report "***FAILED TEST: c13s04b01x00p05n01i02697 - The underline character inserted between adjacent digits of a real literal should not affect the value of this abstract literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p05n01i02697arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2697.vhd,v 1.2 2001-10-26 16:29:49 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c13s04b01x00p05n01i02697ent IS
END c13s04b01x00p05n01i02697ent;
ARCHITECTURE c13s04b01x00p05n01i02697arch OF c13s04b01x00p05n01i02697ent IS
constant a : real := 2.34;
constant b : real := 2.3_4;
BEGIN
TESTING: PROCESS
BEGIN
assert NOT( a=b )
report "***PASSED TEST: c13s04b01x00p05n01i02697"
severity NOTE;
assert ( a=b )
report "***FAILED TEST: c13s04b01x00p05n01i02697 - The underline character inserted between adjacent digits of a real literal should not affect the value of this abstract literal."
severity ERROR;
wait;
END PROCESS TESTING;
END c13s04b01x00p05n01i02697arch;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY RF_tb IS
END RF_tb;
ARCHITECTURE behavior OF RF_tb IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT RF
PORT(
rs1 : IN std_logic_vector(5 downto 0);
rs2 : IN std_logic_vector(5 downto 0);
rd : IN std_logic_vector(5 downto 0);
DWR : IN std_logic_vector(31 downto 0);
rst : IN std_logic;
Crs1 : OUT std_logic_vector(31 downto 0);
Crs2 : OUT std_logic_vector(31 downto 0)
);
END COMPONENT;
--Inputs
signal rs1 : std_logic_vector(5 downto 0) := (others => '0');
signal rs2 : std_logic_vector(5 downto 0) := (others => '0');
signal rd : std_logic_vector(5 downto 0) := (others => '0');
signal DWR : std_logic_vector(31 downto 0) := (others => '0');
signal rst : std_logic := '0';
--Outputs
signal Crs1 : std_logic_vector(31 downto 0);
signal Crs2 : std_logic_vector(31 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: RF PORT MAP (
rs1 => rs1,
rs2 => rs2,
rd => rd,
DWR => DWR,
rst => rst,
Crs1 => Crs1,
Crs2 => Crs2
);
-- Stimulus process
stim_proc: process
begin
rst<='1';
wait for 20 ns;
rst<='0';
rs1<=(others=>'0');
rs2<="000101";
rd<="000001";
DWR<="00000000000000000000000000000101";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="111000";
rd<="010000";
DWR<="11111111111111111111111111111000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000100";
rd<="010001";
DWR<="00000000000000000000000000000100";
wait for 40 ns;
rs1<="000001";
rs2<="000010";
rd<="011000";
DWR<="00000000000000000000000000010100";
wait for 40 ns;
rs1<="010001";
rs2<="000001";
rd<="011001";
DWR<="00000000000000000000000000000010";
wait for 40 ns;
rs1<=(others=>'0');
rs2<=(others=>'0');
rd<=(others=>'0');
DWR<="00000000000000000000000000000000";
wait for 40 ns;
rs1<="000001";
rs2<="000011";
rd<="100000";
DWR<="00000000000000000000000000001000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<=(others=>'0');
rd<=(others=>'0');
DWR<="00000000000000000000000000000000";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000100";
rd<=(others=>'0');
DWR<="11111111111111111111111111111100";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="000001";
rd<="000010";
DWR<="00000000000000000000000000000101";
wait for 40 ns;
rs1<=(others=>'0');
rs2<="010000";
rd<="001000";
DWR<="11111111111111111111111111111000";
wait for 40 ns;
rst<='1';
rs1<="000001";
rs2<="000010";
rd<="001101";
DWR<="00000000000000000000000000001100";
wait;
end process;
END;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity lead_lag_diff is
port ( signal clk : in std_logic; -- clock
quantity input : in real;
quantity output : out real );
end entity lead_lag_diff;
----------------------------------------------------------------
architecture bhv of lead_lag_diff is
constant k : real := 400.0; -- normalize gain
signal z_out : real := 0.0;
begin
proc : process (clk)
variable zi_dly1 : real := 0.0; -- input delayed 1 clk cycle
variable zo_dly1 : real := 0.0; -- output delayed 1 clk cycle
variable z_new : real := 0.0; -- new output value this clk cycle
begin
zo_dly1 := z_out; -- store previous output value
z_new := 0.6163507 * input - 0.6144184 * zi_dly1 + 0.2307692 * zo_dly1;
zi_dly1 := input; -- store previous input value
z_out <= z_new;
end process;
output == k * z_out'ramp(100.0e-9); -- ensure continuous transitions on output
end bhv;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity lead_lag_diff is
port ( signal clk : in std_logic; -- clock
quantity input : in real;
quantity output : out real );
end entity lead_lag_diff;
----------------------------------------------------------------
architecture bhv of lead_lag_diff is
constant k : real := 400.0; -- normalize gain
signal z_out : real := 0.0;
begin
proc : process (clk)
variable zi_dly1 : real := 0.0; -- input delayed 1 clk cycle
variable zo_dly1 : real := 0.0; -- output delayed 1 clk cycle
variable z_new : real := 0.0; -- new output value this clk cycle
begin
zo_dly1 := z_out; -- store previous output value
z_new := 0.6163507 * input - 0.6144184 * zi_dly1 + 0.2307692 * zo_dly1;
zi_dly1 := input; -- store previous input value
z_out <= z_new;
end process;
output == k * z_out'ramp(100.0e-9); -- ensure continuous transitions on output
end bhv;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
library ieee; use ieee.std_logic_1164.all;
entity lead_lag_diff is
port ( signal clk : in std_logic; -- clock
quantity input : in real;
quantity output : out real );
end entity lead_lag_diff;
----------------------------------------------------------------
architecture bhv of lead_lag_diff is
constant k : real := 400.0; -- normalize gain
signal z_out : real := 0.0;
begin
proc : process (clk)
variable zi_dly1 : real := 0.0; -- input delayed 1 clk cycle
variable zo_dly1 : real := 0.0; -- output delayed 1 clk cycle
variable z_new : real := 0.0; -- new output value this clk cycle
begin
zo_dly1 := z_out; -- store previous output value
z_new := 0.6163507 * input - 0.6144184 * zi_dly1 + 0.2307692 * zo_dly1;
zi_dly1 := input; -- store previous input value
z_out <= z_new;
end process;
output == k * z_out'ramp(100.0e-9); -- ensure continuous transitions on output
end bhv;
|
--Part of Mano Basic Computer
--Behzad Mokhtari; [email protected]
--Sahand University of Technology; sut.ac.ir
--Licensed under GPLv3
--Devices
Library IEEE; use IEEE.std_logic_1164.ALL;
Library manoBasic; use manoBasic.defines.all;
package devices is
component Decoder is
generic(N: integer:=4);
port(
I: in std_logic_vector(n-1 downto 0);
E: in std_logic;
Q: out std_logic_vector(2**n-1 downto 0)
);
end component Decoder;
component Multiplexer is
generic(N: integer:=3);
port(
Q: out std_logic;
E: in std_logic:= '1';
S: in std_logic_vector(n-1 downto 0);
I: in std_logic_vector(2**n-1 downto 0)
);
end component;
component flipflopD is
port(
D : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
Q : buffer std_logic;
nQ : buffer std_logic
);
end component flipflopD;
component flipflopJK is
port(
J : in std_logic;
K : in std_logic;
CLK : in std_logic;
CLR : in std_logic;
Q : buffer std_logic;
nQ : buffer std_logic
);
end component flipflopJK;
component reg is
generic(width: integer := sizeof_Word);
port(
INC :in std_logic;
LD :in std_logic;
CLR :in std_logic;
CLK :in std_logic;
Di :in std_logic_vector(width-1 downto 0);
Do :buffer std_logic_vector(width-1 downto 0);
Dno :buffer std_logic_vector(width-1 downto 0);
Co :out std_logic
);
end component reg;
component fulladder is
generic(width: integer := sizeof_Word);
port(
Ci: in std_logic;
A: in std_logic_vector(width-1 downto 0);
B: in std_logic_vector(width-1 downto 0);
S: out std_logic_vector(width-1 downto 0);
Co: out std_logic
);
end component fulladder;
component Timer is
port(
CLK: in std_logic;
CLR: in std_logic;
EN : in std_logic;
T: out std_logic_vector(7 downto 0)
);
end component Timer;
component ALU is
generic(width: integer := sizeof_Word);
port(
Ei: in std_logic;
Eo: out std_logic;
IP: in std_logic_vector(7 downto 0);
AC: in word;
DR: in word;
Q: out word;
cAND: in std_logic;
cADD: in std_logic;
cDR : in std_logic;
cINR: in std_logic;
cCOM: in std_logic;
cSHR: in std_logic;
cSHL: in std_logic
);
end component ALU;
component Memory is
generic(FILENAME: string:=hexFileMEM);
port(
CLK:in std_logic;
ADR:in adr;
ENR:in std_logic;
ENW:in std_logic;
DTW:in word;
DTR:out word
);
end component Memory;
component busLine is
port(
Ar: in adr;
PC: in word;
DR: in word;
AC: in word;
IR: in word;
TR: in word;
Mm: in word;
S: in ctrlBUS;
Q: out word
);
end component busLine;
end devices; |
configuration conf of repro is
for behav
for c : comp
use entity work.comp;
for behav
for c2 : comp2
use entity work.comp2 (behav);
end for;
end for;
end for;
end for;
end conf;
architecture behav of comp2 is
begin
assert s = '1';
end behav;
|
configuration conf of repro is
for behav
for c : comp
use entity work.comp;
for behav
for c2 : comp2
use entity work.comp2 (behav);
end for;
end for;
end for;
end for;
end conf;
architecture behav of comp2 is
begin
assert s = '1';
end behav;
|
configuration conf of repro is
for behav
for c : comp
use entity work.comp;
for behav
for c2 : comp2
use entity work.comp2 (behav);
end for;
end for;
end for;
end for;
end conf;
architecture behav of comp2 is
begin
assert s = '1';
end behav;
|
-- **********************************************************
-- Corso di Reti Logiche - Progetto Registratore Portatile
-- Andrea Carrer - 729101
-- Modulo VGA_Adapter.vhd
-- Versione 1.01 - 14.03.2013
-- **********************************************************
-- **********************************************************
-- Modulo trovato in rete, convertito da Verilog a VHDL
-- e successivamente adattato al progetto.
-- Ho utilizzato la risoluzione 320x240 monocromatica.
-- Occupazione totale di memoria: 76800 bit.
-- **********************************************************
--VGA Adapter
------------------
--
--This is an implementation of a VGA Adapter. The adapter uses VGA mode signalling to initiate
--a 640x480 resolution mode on a computer monitor, with a refresh rate of approximately 60Hz.
--It is designed for easy use in an early digital logic design course to facilitate student
--projects on the Altera DE1 Educational board.
--
--This implementation of the VGA adapter can display images of varying colour depth at a resolution of
--320x240 or 160x120 superpixels. The concept of superpixels is introduced to reduce the amount of on-chip
--memory used by the adapter. The following table shows the number of bits of on-chip memory used by
--the adapter in various resolutions and colour depths.
--
---------------------------------------------------------------------------------------------------------------------------------
--Resolution | Mono | 8 colours | 64 colours | 512 colours | 4096 colours | 32768 colours | 262144 colours | 2097152 colours |
---------------------------------------------------------------------------------------------------------------------------------
--160x120 | 19200 | 57600 | 115200 | 172800 | 230400 | 288000 | 345600 | 403200 |
--320x240 | 78600 | 230400 | ############## Does not fit ############################################################## |
---------------------------------------------------------------------------------------------------------------------------------
--
--By default the adapter works at the resolution of 320x240 with 8 colours. To set the adapter in any of
--the other modes, the adapter must be instantiated with specific parameters. These parameters are:
--- RESOLUTION - a string that should be either "320x240" or "160x120".
--- MONOCHROME - a string that should be "TRUE" if you only want black and white colours, and "FALSE"
-- otherwise.
--- BITS_PER_COLOUR_CHANNEL - an integer specifying how many bits are available to describe each colour
-- (R,G,B). A default value of 1 indicates that 1 bit will be used for red
-- channel, 1 for green channel and 1 for blue channel. This allows 8 colours
-- to be used.
--
--In addition to the above parameters, a BACKGROUND_IMAGE parameter can be specified. The parameter
--refers to a memory initilization file (MIF) which contains the initial contents of video memory.
--By specifying the initial contents of the memory we can force the adapter to initially display an
--image of our choice. Please note that the image described by the BACKGROUND_IMAGE file will only
--be valid right after your program the DE2 board. If your circuit draws a single pixel on the screen,
--the video memory will be altered and screen contents will be changed. In order to restore the background
--image your circuti will have to redraw the background image pixel by pixel, or you will have to
--reprogram the DE2 board, thus allowing the video memory to be rewritten.
--
--To use the module connect the vga_adapter to your circuit. Your circuit should produce a value for
--inputs X, Y and plot. When plot is high, at the next positive edge of the input clock the vga_adapter
--will change the contents of the video memory for the pixel at location (X,Y). At the next redraw
--cycle the VGA controller will update the contants of the screen by reading the video memory and copying
--it over to the screen. Since the monitor screen has no memory, the VGA controller has to copy the
--contents of the video memory to the screen once every 60th of a second to keep the image stable. Thus,
--the video memory should not be used for other purposes as it may interfere with the operation of the
--VGA Adapter.
--
--As a final note, ensure that the following conditions are met when using this module:
--1. You are implementing the the VGA Adapter on the Altera DE2 board. Using another board may change
-- the amount of memory you can use, the clock generation mechanism, as well as pin assignments required
-- to properly drive the VGA digital-to-analog converter.
--2. Outputs VGA_* should exist in your top level design. They should be assigned pin locations on the
-- Altera DE2 board as specified by the DE2_pin_assignments.csv file.
--3. The input clock must have a frequency of 50 MHz with a 50% duty cycle. On the Altera DE2 board
-- PIN_N2 is the source for the 50MHz clock.
--
--During compilation with Quartus II you may receive the following warnings:
--- Warning: Variable or input pin "clocken1" is defined but never used
--- Warning: Pin "VGA_SYNC" stuck at VCC
--- Warning: Found xx output pins without output pin load capacitance assignment
--These warnings can be ignored. The first warning is generated, because the software generated
--memory module contains an input called "clocken1" and it does not drive logic. The second warning
--indicates that the VGA_SYNC signal is always high. This is intentional. The final warning is
--generated for the purposes of power analysis. It will persist unless the output pins are assigned
--output capacitance. Leaving the capacitance values at 0 pf did not affect the operation of the module.
--
--If you see any other warnings relating to the vga_adapter, be sure to examine them carefully. They may
--cause your circuit to malfunction.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
library Altera_mf;
use altera_mf.altera_mf_components.all;
entity VGA_Adapter is port(
resetn: in std_logic;
clock: in std_logic;
clock_25: in std_logic;
colour: in std_logic;
x: in std_logic_vector(8 downto 0); -- Coordinata x
y: in std_logic_vector(7 downto 0); -- Coordinata y
plot: in std_logic; -- Quando e'=1, il pixel (x,y) cambierà' colore (bisogna plottare)
-- Segnali per il DAC per pilotare il monitor.
VGA_R: out std_logic_vector(9 downto 0);
VGA_G: out std_logic_vector(9 downto 0);
VGA_B: out std_logic_vector(9 downto 0);
VGA_HS: out std_logic;
VGA_VS: out std_logic;
VGA_BLANK: out std_logic;
VGA_SYNC: out std_logic
);
end VGA_Adapter;
architecture behaviour of VGA_Adapter is
component VGA_CalcoloIndirizzo is port (
x : in std_logic_vector(8 downto 0);
y : in std_logic_vector(7 downto 0);
mem_address : out std_logic_vector(16 downto 0)
);
end component;
component VGA_Controller is port(
vga_clock: in std_logic;
resetn: in std_logic;
pixel_colour: in std_logic_vector(0 downto 0);
memory_address: out std_logic_vector(16 downto 0);
VGA_R: out std_logic_vector(9 downto 0) register;
VGA_G: out std_logic_vector(9 downto 0) register;
VGA_B: out std_logic_vector(9 downto 0) register;
VGA_HS: out std_logic register;
VGA_VS: out std_logic register;
VGA_BLANK: out std_logic register;
VGA_SYNC: out std_logic -- VGA sync e' sempre a 1.
);
end component;
signal valid_320x240: std_logic; -- Serve a specificare che le coordinate siano in un range valido.
signal writeEn: std_logic; -- Serve ad abilitare la scrittura della memoria video d un certo pixcel (x,y)
signal to_ctrl_colour: std_logic; -- Pixel letto dal controller VGA
signal user_to_video_memory_addr: std_logic_vector(16 downto 0); -- Indirizzo di memoria per scrivere le coordnate (x,y)
signal controller_to_video_memory_addr: std_logic_vector(16 downto 0); -- Indirizzo di memoria per leggere le coordnate (x,y)
signal vcc: std_logic := '1'; -- Serve al VGA Adapter
signal gnd: std_logic := '0'; -- Serve al VGA Adapter
begin
-- Controllo validita' coordinate
valid_320x240 <= '1' when (
(x >= "000000000")
and (x < "101000000") -- x < 320
and (y >= "00000000")
and (y < "11110000")); -- y < 240
-- Controllo abilitazione scrittura
writeEn <= '1' when (plot='1') and (valid_320x240='1') else '0';
-- Converte le coordinate in un indirizzo di memoria
CoordinatesTranslator : VGA_CalcoloIndirizzo port map(
x => x,
y => y,
mem_address => user_to_video_memory_addr
);
-- Allocazione memoria video
VideoMemory : altsyncram
generic map (
WIDTH_A => 1,
WIDTH_B => 1,
INTENDED_DEVICE_FAMILY => "Cyclone II",
OPERATION_MODE => "DUAL_PORT",
WIDTHAD_A => 17,
NUMWORDS_A => 76800,
WIDTHAD_B => 17,
NUMWORDS_B => 76800,
OUTDATA_REG_B => "CLOCK1",
ADDRESS_REG_B => "CLOCK1",
CLOCK_ENABLE_INPUT_A => "BYPASS",
CLOCK_ENABLE_INPUT_B => "BYPASS",
CLOCK_ENABLE_OUTPUT_B => "BYPASS",
POWER_UP_UNINITIALIZED => "FALSE"
)
port map (
wren_a => writeEn,
wren_b => gnd,
clock0 => clock, -- write clock
clock1 => clock_25, -- read clock
clocken0 => vcc, -- write enable clock
clocken1 => vcc, -- read enable clock
address_a => user_to_video_memory_addr,
address_b => controller_to_video_memory_addr,
data_a(0) => colour, -- data in
q_b(0) => to_ctrl_colour -- data out
);
-- Istanza del controller VGA
VGAcontroller : VGA_Controller port map (
vga_clock => clock_25,
resetn => resetn,
pixel_colour(0) => to_ctrl_colour,
memory_address => controller_to_video_memory_addr,
VGA_R => VGA_R,
VGA_G => VGA_G,
VGA_B => VGA_B,
VGA_HS => VGA_HS,
VGA_VS => VGA_VS,
VGA_BLANK => VGA_BLANK,
VGA_SYNC => VGA_SYNC
);
end behaviour; |
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`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 10960)
`protect data_block
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`protect end_protected
|
-- $Id: mult_gen_pkg_v11_2.vhd,v 1.5 2011/03/17 13:01:31 gordono Exp $
--------------------------------------------------------------------------------
-- (c) Copyright 2006 - 2009 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
-- Master package for Multiplier core
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library xilinxcorelib;
use xilinxcorelib.bip_utils_pkg_v2_0.all;
package mult_gen_pkg_v11_2 is
-----------------------------------------------------------------------------
-- Constants and functions for use all over the core
-----------------------------------------------------------------------------
-- enable/disable debug output from functions
constant debug : boolean := false;
-- enable assert statements to debug progress through function hierarchy
constant fn_debug : boolean := false;
-- enable debug output for CCM functions
constant ccm_debug : boolean := false;
-- enumerated constants for c_mult_type
constant LUT : integer := 0;
constant EMBEDDED_MULT : integer := 1;
constant FIXED_CCM : integer := 2;
-- enumerated constants for c_optimize_goal
constant EMB_MULT_RESOURCES : integer := 0;
constant CORE_SPEED : integer := 1;
-- enumerated constants for the on/off pins e.g. CE, SCLR
constant MG_NO : integer := 0;
constant MG_YES : integer := 1;
-- enumerated constants for c_ccm_imp
constant DIST_MEM : integer := 0;
constant BRAM : integer := 1;
constant MULTS : integer := 2;
constant CSD : integer := 3;
constant PIPELINE_CFG_BREAKPT : integer := 1000000000;
constant MAX_PIPE_STAGES : integer := 30;
constant MAX_PRODUCT_WIDTH : integer := 128;
-- constants for the 3 possible hybrid configurations
constant BASE_MULT : integer := 0; -- no fabric required - just use the base DSP48 or Mult18x18 multiplier
constant ONE_MULT : integer := 1; -- fabric multiplier only needed on one side of the partial-product array
constant TWO_MULT : integer := 2; -- 2 fabric multipliers and a fabric adder needed around the embedded mult array
-- default generics for all core components etc.
constant DEF_C_VERBOSITY : integer := 0;
constant DEF_C_MODEL_TYPE : integer := 1;
constant DEF_C_XDEVICEFAMILY : string := "no_family";
constant DEF_C_A_WIDTH : integer := 18;
constant DEF_C_A_TYPE : integer := 0;
constant DEF_C_B_WIDTH : integer := 18;
constant DEF_C_B_TYPE : integer := 0;
constant DEF_C_OUT_HIGH : integer := 35;
constant DEF_C_OUT_LOW : integer := 0;
constant DEF_C_MULT_TYPE : integer := EMBEDDED_MULT;
constant DEF_C_OPTIMIZE_GOAL : integer := CORE_SPEED;
constant DEF_C_HAS_CE : integer := MG_NO;
constant DEF_C_HAS_SCLR : integer := MG_NO;
constant DEF_C_CE_OVERRIDES_SCLR : integer := MG_NO;
constant DEF_C_LATENCY : integer := 1;
constant DEF_C_CCM_IMP : integer := DIST_MEM;
constant DEF_C_B_VALUE : string := "111111111111111111";
constant DEF_C_HAS_ZERO_DETECT : integer := MG_NO;
constant DEF_C_ROUND_OUTPUT : integer := MG_NO;
constant DEF_C_ROUND_PT : integer := 0;
constant DSP_P_WIDTH : integer := 48;
-----------------------------------------------------------------------------
-- TYPES AND RECORDS
-----------------------------------------------------------------------------
-- record to define the widths of all the ports that may be required when building a block-based multiplier
type PORT_ASPECTS is record
a : integer; -- size of port A
b : integer; -- size of port B
m : integer; -- size of M register after mult
c : integer; -- size of port C
p : integer; -- size of port P
end record PORT_ASPECTS;
-- a record to store the width of the a and b operands and if they should be
-- swapped internally for the best mapping/resource use
type WIDTH_REC is record
a : integer;
b : integer;
a_type : integer;
b_type : integer;
swap : boolean;
end record WIDTH_REC;
type BLOCK_MULT_REC is record
a_width : integer; -- width of A operand on block mult
a_type : integer; -- datatype of A operand on block mult
b_width : integer; -- width of B operand on block mult
b_type : integer; -- datatype of B operand on block mult
end record BLOCK_MULT_REC;
type ONE_MULT_REC is record
a : integer; -- width of A input to fabric mult
b : integer; -- width of B input to fabric mult
a_type : integer; -- type of A input to fabric mult
b_type : integer; -- type of B input to fabric mult
out_width : integer; -- output width of fabric mult
bypass : integer; -- number of bypass bits
a_offset : integer; -- the offset on the A operand due to the mult configuration and # bypass bits
b_offset : integer; -- the offset on the B operand due to the mult configuration and # bypass bits
end record ONE_MULT_REC;
type TWO_MULT_REC is record
a_top : integer; -- width of A operand on top fabric mult
b_top : integer; -- width of B operand on top fabric mult
a_type_top : integer; -- type of A operand on top fabric mult
b_type_top : integer; -- type of B operand on top fabric mult
out_width_top : integer; -- output width of top fabric mult
a_side : integer; -- width of A operand on side fabric mult
b_side : integer; -- width of B operand on side fabric mult
a_type_side : integer; -- type of A operand on side fabric mult
b_type_side : integer; -- type of B operand on side fabric mult
out_width_side : integer; -- output width of side fabric mult
mult_bypass : integer; -- number of bypass bits from top fabric mult
add_bypass : integer; -- number of bypass bits from fabric adder
a_offset : integer; -- offset for A operand into block multiplier
b_offset : integer; -- offset for B operand into block multiplier
end record TWO_MULT_REC;
-- Record holding the resolved generics with any user misconfiguration or
-- invalid settings removed
type T_RESOLVED_GENERICS is record
R_A_WIDTH : integer;
R_A_TYPE : integer;
R_B_WIDTH : integer;
R_B_TYPE : integer;
R_OUT_HIGH : integer;
R_OUT_LOW : integer;
R_MULT_TYPE : integer;
R_OPT_GOAL : integer;
R_HAS_CE : integer;
R_HAS_SCLR : integer;
R_CE_OVERRIDES_SCLR : integer;
R_LATENCY : integer;
R_CCM_IMP : integer;
R_B_VALUE : string(1 to 64);
R_HAS_ZERO_DETECT : integer;
R_ROUND_OUTPUT : integer;
R_ROUND_PT : integer;
end record T_RESOLVED_GENERICS;
-- record to hold details of the DSP48 partial products so they can all be passed
-- back from a single function
type R_DSP_PP is record
a_pp : integer;
b_pp : integer;
extra_b_pp : integer;
end record R_DSP_PP;
-- record to hold the resource counts for use by the core's GUI
type R_MULT_RESOURCES is record
LUTs : integer;
DSPs : integer;
MULT18X18s : integer;
BRAMS : integer;
end record R_MULT_RESOURCES;
-----------------------------------------------------------------------------
-- FUNCTIONS
-----------------------------------------------------------------------------
-- purpose: validates the generics for the whole core, traps any bad combinations
function check_generics(c_xdevicefamily : string;
a_width, a_type, b_width, b_type : integer;
out_high, out_low : integer;
mult_type, opt_goal : integer;
has_ce, has_sclr, ce_overrides_sclr : integer;
latency, ccm_imp : integer;
b_value : string;
has_zero_detect, round_output, round_pt : integer) return T_RESOLVED_GENERICS;
-- purpose: catches the case where the xdevicefamily is Spartan-3E, 3A or 3ADSP and modifies the family info accordingly
-- There aren't any shared functions to do this, but the only piece of IP where this really matters is the multiplier
-- function modify_family(family_str : string) return string;
-- converts a std_logic bit to an integer representation
function sl_to_int(sl : std_logic) return integer;
-- reports the 'logarithm' (base 2) of an INTEGER
function mult_gen_log2(x : integer) return integer;
-- reports the 'logarithm' (base 2) of an INTEGER
-- the value it returns is constrained to the integer value
-- e.g. log(4) = 2, log(6) = 2, log(8) = 3, log(10) = 3
function mult_gen_log2d(x : integer) return integer;
-- purpose: calculates the a_pp and b_pp partial product configurations for
-- DSP48 multipliers, and deals with irregular structures used for some optimisations
function calc_dsp48_pps (family : string; op_width : WIDTH_REC) return R_DSP_PP;
-- purpose: calculates term number for LUT6 mult
function func_term_number(an : integer; bn : integer; s : integer) return integer;
-- purpose: calculates number of adder layers for LUT6 mult
function adder_layer_number_calc(width : integer) return integer;
-- purpose: works out for the multiplier specification provided what the fully-pipelined latency will be
-- This is the public interface to the core's latency function
function mult_gen_v11_2_calc_fully_pipelined_latency (family : string; a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp : integer; b_value : string) return integer;
-- purpose: works out for the multiplier specification provided what the fully-pipelined latency will be
-- Used when calling the multiplier from inside another core
function mult_gen_v11_2_calc_fully_pipelined_latency_internal (family : string; a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp : integer; b_value : string; standalone : integer := 1) return integer;
-- purpose: works out if the operands need to be swapped around and generates the correct widths for them
-- these values can then be used to control the wire swapping in the hardware generation
function get_true_widths(family : string; c_a_width, c_b_width, c_a_type, c_b_type : integer; port_size : PORT_ASPECTS) return WIDTH_REC;
-- purpose: works out how many partial products are required for the A operand (number of DSPs/MULT18X18s)
function calc_a_pp(family : string; op_width : WIDTH_REC) return integer;
-- purpose: works out how many partial products are required for the B operand (number of DSPs/MULT18X18s)
-- note that there is no family restriction here because MULT18X18, DSP48 and DSP48E
-- both have 18-bit B ports on the multiplier
function calc_b_pp(op_width : WIDTH_REC) return integer;
-- purpose: works out how many partial products are required for the A operand (number of DSPs/MULT18X18s)
function hybrid_calc_a_pp(family : string; op_width : WIDTH_REC) return integer;
-- purpose: works out how many partial products are required for the B operand (number of DSPs/MULT18X18s)
-- note that there is no family restriction here because MULT18X18, DSP48 and DSP48E
-- both have 18-bit B ports on the multiplier
function hybrid_calc_b_pp(family : string; op_width : WIDTH_REC) return integer;
-- purpose: works out which configuration of hybrid is required based on the input operand widths
-- and types and the multiplier primitive being used
function get_hybrid_configuration(family : string;
a_pp, b_pp : integer;
op_width : WIDTH_REC;
port_size : PORT_ASPECTS)return integer;
-- purpose: works out the operand widths and types for the block multiplier subcomponent
function get_block_mult_cfg (family : string;
a_pp, b_pp : integer;
op_width : WIDTH_REC;
hybrid_cfg : integer;
port_size : PORT_ASPECTS) return BLOCK_MULT_REC;
function get_one_mult_cfg(width : WIDTH_REC;
block_a_width, block_a_type, block_b_width, block_b_type : integer;
hybrid_cfg : integer;
port_size : PORT_ASPECTS) return ONE_MULT_REC;
-- purpose: works out the required operand widths of the fabric multiplier for the 'two mult' case
function get_two_mult_cfg(op_width : WIDTH_REC;
a_width, a_type, b_width, b_type : integer;
hybrid_cfg : integer) return TWO_MULT_REC;
-- purpose: works out fully-pipelined latency of a LUT multiplier
function fab_mult_full_pipe_lat(a_width, b_width : integer) return integer;
-- purpose: works out how many pipeline stages a particular configuration of DSPs or MULT18s needs
-- for max performance
function get_emb_mult_max_pipe_stages (family : string; a_pp, b_pp : integer) return integer;
-- purpose: works out the depth of the adder tree on the LUT multiplier(s)
-- to see what the maximum fully-pipelined latency will be
function get_LUT_max_pipe_stages (one_mult_cfg : ONE_MULT_REC; two_mult_cfg : TWO_MULT_REC; hybrid_configuration : integer) return integer;
-- purpose: checks to see if the constant has any zeros at the MSB (left) side of the string and
-- returns an integer to say how many consecutive zeros there are
-- These zeros don't need to go through the multiplier, so we could save some
-- logic in a few cases
-- If the constant is of signed type, we need to keep one of the leading zeros
-- If the constant is signed though, we can also check for leading ones and
-- trim them, stopping when we find "10" when searching from the left-hand side
function get_trimmed_leading_bits (b_value : string; b_type : integer; mult_type : integer) return integer;
-- purpose: counts the number of LSB zeros in the supplied constant STRING
-- If the bits are zero, we don't need to pass these bits into the multiplier
-- and we can just right-shift the output by these number of bits
function get_output_scaling (b_value : string; b_type : integer; mult_type : integer) return integer;
-- purpose: checks if the constant is all-zeros, in which case there is no point in creating logic!
function check_b_value_all_zeros (b_value : string; b_value_length : integer) return boolean;
-- -- purpose: returns the c_family equivalent of a string value
-- function t_device_family_to_c_family (family : string) return string;
-- -- purpose: returns the c_xdevicefamily equivalent of a string value
-- function t_device_family_to_c_xdevicefamily (family : string) return string;
-- purpose: checks if the constant string represents a power of two
function check_const_power_of_two (b_value : string; b_type, mult_type : integer) return boolean;
-------------------------------------------------------------------------------
-- Functions, constants, types imported from ccm_pkg.vhd
-------------------------------------------------------------------------------
constant C_DISTRIBUTED : integer := 0;
constant C_SP_BLOCK : integer := 1;
constant C_DP_BLOCK : integer := 2;
constant NEW_LINE : string(1 to 1) := (1 => LF); -- FOR ASSERTION REPORTS
constant A_MAX_WIDTH : integer := 64;
-- a_max_width is the only thing that needs to be modified in order to
-- support wider input busses
-- max number of partial products - add 2 as contingency for a_signed
constant MAX_NUM_PPS : integer := (A_MAX_WIDTH+2)/4;
function calc_reqd_b_value(b_value : string;
b_width : integer;
b_type : integer;
reqd_b_width : integer) return string;
function bitstorep_string(a_value : string;
a_type : integer) return integer;--natural;
function calc_shift_bits(b_value : string;
b_constant : integer) return integer;
function get_rom_addr_width(family : string; mem_type : integer) return integer;
function calc_a_input_width(operand_width, has_a_signed, rom_addr_width, b_constant : integer) return integer;
function calc_num_pps(a_width, rom_addr_width : integer) return integer;
-- TYPE for storing information about symmetric adders
type adder_info_type is record
a_input : integer;
b_input : integer;
a_width : integer;
b_width : integer;
b_type : integer;
b_pipe_regs : integer;
scale_by : integer;
drop_lsbs : integer;
out_width : integer;
pipe_stages : integer; -- new in V9.0!
row : integer; -- redundant
col : integer; -- redundant
height_limit : integer; -- redundant
height : integer; -- redundant
has_o : boolean; -- redundant
has_q : boolean; -- redundant
place_above_mem : boolean; -- redundant
end record;
function calc_adder_level(adder_num, max_add_levels : integer) return integer;
function calc_last_pp_input_width(operand_width, has_a_signed,
rom_addr_width, b_constant : integer) return integer;
function calc_pp_width(b_width : integer;
b_type : integer;
b_value : string;
b_constant : integer;
a_width : integer;
a_type : integer;
has_a_signed : integer;
last_pp : boolean;
full_prod : boolean) return integer;
function calc_last_pp_adder(num_pps : integer;
max_add_levels : integer;
num_adders : integer;
num_extra_adders : integer) return integer;
function calc_last_rom_contents(b_width : integer;
a_width : integer;
a_type : integer;
b_type : integer;
has_a_signed : integer;
rom_addr_width : integer;
rom_depth : integer;
rom_width : integer;
start_bit : integer;
b_value : string;
b_constant : integer;
num_rom_bits : integer;
number_of_pps : integer;
a_signed_extension : boolean) return bit_vector;
function calc_rom_contents(b_width : integer;
b_type : integer;
rom_addr_width : integer;
rom_depth : integer;
rom_width : integer;
start_bit : integer;
b_value : string;
num_rom_bits : integer) return bit_vector;
function calc_rom_start_bit(b_width : integer;
b_value : string;
b_constant : integer;
pp_width : integer;
a_type : integer;
rom_has_a_signed : integer;
mem_type : integer;
mem_addr_width : integer;
pipeline : integer;
num_adders : integer;
has_q : integer;
last_mem : boolean) return integer;
function calc_num_extra_adders(num_pps, max_num_pps : integer) return integer;
function get_mem_type(family : string;
mem_type : integer;
bram_addr_width : integer;
has_swapb : integer;
a_width : integer;
a_type : integer;
has_a_signed : integer;
b_constant : integer;
has_o : integer) return integer;
function bitsneededtorepresent(a_value : integer) return integer;--(a_value : natural) return natural;
function bitstorep_bv(a_value : bit_vector;
a_type : integer;
a_positive : boolean) return integer;--natural;
function mult_gen_max_of(i0, i1 : integer) return integer;
function multiply_bv(a, b : bit_vector; a_signed, b_signed : boolean) return bit_vector;
function natural_to_bit_vector(in_val : in integer; length : in integer) return bit_vector; --(in_val : in natural; length : in natural) return bit_vector;
function mult_gen_select_string(i0 : string; i1 : string; sel : boolean) return string;
function select_val(i0 : integer; i1 : integer; sel : boolean) return integer;
function select_val_int(i0 : integer; i1 : integer; sel : integer) return integer;
function mult_gen_str_to_bv(bitsin : string; nbits : integer) return bit_vector;
function mult_gen_bv_to_str(bitsin : bit_vector; nbits : integer) return string;
function slv_to_str(bitsin : std_logic_vector; nbits : integer) return string;
-----------------------------------------------------------------------------
-- Functions, types, constants from ccm_mem_utils
-----------------------------------------------------------------------------
-- Cannot have a dist mem > 'deepest_dist_mem' - have to use block mem
constant deepest_dist_mem : integer := 256;--natural := 256;
constant c_automatic : integer := -1;
function calc_depth(reqd_depth : integer; mem_type : integer) return integer;
-----------------------------------------------------------------------------
-- Functions to be translated by VTFC for use only in the GUI
-----------------------------------------------------------------------------
function calc_lut_mult_resources (c_a_width, c_b_width : integer) return integer;
function calc_hybrid_emb_mults (family : string; op_width : WIDTH_REC) return integer;
function calc_hybrid_luts (family : string; op_width : WIDTH_REC) return integer;
function calc_emb_mults (family : string; op_width : WIDTH_REC) return integer;
function calc_reqd_b_width (c_b_value : string; c_b_width, c_b_type : integer; reloadable : boolean) return integer;
function mult_gen_v11_2_luts (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer;
function mult_gen_v11_2_mults (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer;
function mult_gen_v11_2_brams (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer;
function mult_gen_v11_2_gui_resources (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return R_MULT_RESOURCES;
function get_port_sizes (family : string) return PORT_ASPECTS;
end package mult_gen_pkg_v11_2;
package body mult_gen_pkg_v11_2 is
-- purpose: validates the generics for the whole core, traps any bad combinations
function check_generics(c_xdevicefamily : string;
a_width, a_type, b_width, b_type : integer;
out_high, out_low : integer;
mult_type, opt_goal : integer;
has_ce, has_sclr, ce_overrides_sclr : integer;
latency, ccm_imp : integer;
b_value : string;
has_zero_detect, round_output, round_pt : integer) return T_RESOLVED_GENERICS is
variable r_generics : T_RESOLVED_GENERICS;
begin -- FUNCTION check_generics
-- Assign the incoming generics to the record elements
-- We will update them as required when the checks are performed
-- before the record is returned
r_generics.R_A_WIDTH := a_width;
r_generics.R_A_TYPE := a_type;
r_generics.R_B_WIDTH := b_width;
r_generics.R_B_TYPE := b_type;
r_generics.R_OUT_HIGH := out_high;
r_generics.R_OUT_LOW := out_low;
r_generics.R_MULT_TYPE := mult_type;
r_generics.R_OPT_GOAL := opt_goal;
r_generics.R_HAS_CE := has_ce;
r_generics.R_HAS_SCLR := has_sclr;
r_generics.R_CE_OVERRIDES_SCLR := ce_overrides_sclr;
r_generics.R_LATENCY := latency;
r_generics.R_CCM_IMP := ccm_imp;
-- This syntax ensures that the string for the constant
-- will be represented as (1 to N) throughout the core
-- This is necessary for VTFC support
r_generics.R_B_VALUE(1 to b_value'length) := b_value;
r_generics.R_HAS_ZERO_DETECT := has_zero_detect;
r_generics.R_ROUND_OUTPUT := round_output;
r_generics.R_ROUND_PT := round_pt;
-- check that the A and B types are valid
assert r_generics.R_A_TYPE = C_SIGNED or r_generics.R_A_TYPE = C_UNSIGNED report "ERROR: mult_gen: c_a_type should be 0 (signed) or 1 (unsigned)" severity failure;
assert r_generics.R_B_TYPE = C_SIGNED or r_generics.R_B_TYPE = C_UNSIGNED report "ERROR: mult_gen: c_b_type should be 0 (signed) or 1 (unsigned)" severity failure;
-- check that the port widths are valid, based on the operand types and the multiplier type
-- assert r_generics.R_A_WIDTH+r_generics.R_A_TYPE >= 2 and r_generics.R_A_WIDTH < 65 report "ERROR: mult_gen: c_a_width must be in the range 2->64 for signed data and 1->64 for unsigned data" severity failure;
-- assert r_generics.R_B_WIDTH+r_generics.R_B_TYPE >= 2 and r_generics.R_B_WIDTH < 65 report "ERROR: mult_gen: c_b_width must be in the range 2->64 for signed data and 1->64 for unsigned data" severity failure;
-- check that MULT_TYPE is valid
assert r_generics.R_MULT_TYPE = LUT or r_generics.R_MULT_TYPE = EMBEDDED_MULT or r_generics.R_MULT_TYPE = FIXED_CCM report "ERROR: mult_gen: c_mult_type must be 0, 1 or 2" severity failure;
-- check that opt_goal is valid
if r_generics.R_MULT_TYPE = EMBEDDED_MULT then
if r_generics.R_OPT_GOAL /= EMB_MULT_RESOURCES and r_generics.R_OPT_GOAL /= CORE_SPEED then
report "WARNING: mult_gen: c_optimize_goal must be 0 (optimize for embedded mult resources) or 1 (optimize for core speed). Optimizing for speed..." severity warning;
r_generics.R_OPT_GOAL := CORE_SPEED;
end if;
else
-- don't care - generic doesn't apply to CCM or LUT mult
null;
end if;
-- check has_ce, has_sclr, ce_overrides_sclr
assert r_generics.R_HAS_CE = MG_NO or r_generics.R_HAS_CE = MG_YES report "ERROR: mult_gen: c_has_ce must be 0 or 1" severity failure;
if r_generics.R_HAS_CE /= 0 and r_generics.R_LATENCY = 0 then
report "WARNING: mult_gen: c_has_ce is set to 1, but no clock enable is required as the core latency is zero. Setting c_has_ce to 0 internally" severity warning;
r_generics.R_HAS_CE := 0;
end if;
assert r_generics.R_HAS_SCLR = MG_NO or r_generics.R_HAS_SCLR = MG_YES report "ERROR: mult_gen: c_has_sclr must be 0 or 1" severity failure;
if r_generics.R_HAS_SCLR /= 0 and r_generics.R_LATENCY = 0 then
report "WARNING: mult_gen: c_has_sclr is set to 1, but no synchronous clear is required as the core latency is zero. Setting c_has_sclr to 0 internally" severity warning;
r_generics.R_HAS_SCLR := 0;
end if;
if r_generics.R_HAS_SCLR = MG_YES and r_generics.R_HAS_ZERO_DETECT = MG_YES then
report "ERROR: mult_gen: c_has_sclr must be set to 0 if c_has_zero_detect is to be used" severity failure;
end if;
assert r_generics.R_CE_OVERRIDES_SCLR = MG_NO or r_generics.R_CE_OVERRIDES_SCLR = MG_YES report "ERROR: mult_gen: c_ce_overrides_sclr must be 0 or 1" severity failure;
-- check latency is valid, and account for auto-pipelining
if r_generics.R_LATENCY = -1 then
-- let the core decide on the optimum number of pipeline stages
r_generics.R_LATENCY := mult_gen_v11_2_calc_fully_pipelined_latency(C_XDEVICEFAMILY, r_generics.R_A_WIDTH, r_generics.R_A_TYPE, r_generics.R_B_WIDTH, r_generics.R_B_TYPE, r_generics.R_MULT_TYPE, r_generics.R_OPT_GOAL, r_generics.R_CCM_IMP, r_generics.R_B_VALUE);
assert not(debug) report "INFO: mult_gen: The core calculated that " & integer'image(r_generics.R_LATENCY) & " pipeline stages are required for this multiplier" severity note;
else
-- just check that the supplied latency value is in the supported range(s)
assert (r_generics.R_LATENCY >= 0 and r_generics.R_LATENCY <= MAX_PIPE_STAGES) or r_generics.R_LATENCY >= PIPELINE_CFG_BREAKPT report "ERROR: mult_gen: C_LATENCY must be > 0 and < " & integer'image(MAX_PIPE_STAGES) & " (or >= " & integer'image(PIPELINE_CFG_BREAKPT) & " for bit pattern mode)" severity failure;
end if;
-- check ccm_imp is valid - depends on MULT_TYPE
if r_generics.R_MULT_TYPE = FIXED_CCM then
assert r_generics.R_CCM_IMP = DIST_MEM or r_generics.R_CCM_IMP = BRAM or r_generics.R_CCM_IMP = MULTS report "ERROR: mult_gen: c_ccm_imp must be 0, 1 or 2" severity failure;
else
-- we don't care - it's a parallel multiplier - set it to zero
r_generics.R_CCM_IMP := 0;
null;
end if;
-- check b_value is not a null string if it's a CCM
if r_generics.R_MULT_TYPE = FIXED_CCM then
assert r_generics.R_B_VALUE'length /= 0 report "ERROR: mult_gen: c_b_value string length is zero" severity failure;
else
-- we don't care, as b_value's not used
r_generics.R_B_VALUE(1 to 64) := (others => 'Z');
null;
end if;
if r_generics.R_MULT_TYPE = LUT or r_generics.R_MULT_TYPE = EMBEDDED_MULT then
assert r_generics.R_HAS_ZERO_DETECT = MG_NO or r_generics.R_HAS_ZERO_DETECT = MG_YES report "ERROR: mult_gen: c_has_zero_detect must be 0 or 1" severity failure;
else
assert r_generics.R_HAS_ZERO_DETECT = MG_NO report "WARNING: mult_gen: Zero Detection is only supported for parallel multipliers" severity warning;
r_generics.R_HAS_ZERO_DETECT := 0;
end if;
if r_generics.R_MULT_TYPE = EMBEDDED_MULT and (supports_dsp48(C_XDEVICEFAMILY) = 1 or supports_dsp48e(C_XDEVICEFAMILY) > 0) then
assert r_generics.R_ROUND_OUTPUT = MG_NO or r_generics.R_ROUND_OUTPUT = MG_YES report "ERROR: mult_gen: c_round_output must be 0 or 1" severity failure;
if supports_dsp48(C_XDEVICEFAMILY) = 1 and r_generics.R_ROUND_OUTPUT = MG_YES then
assert r_generics.R_A_WIDTH+r_generics.R_A_TYPE <= 18 and r_generics.R_B_WIDTH+r_generics.R_B_TYPE <= 18 report "ERROR: mult_gen: Symmetric rounding is only supported for a single DSP48 in Virtex-4" severity failure;
elsif supports_dsp48e(C_XDEVICEFAMILY) > 0 and r_generics.R_ROUND_OUTPUT = MG_YES then
assert r_generics.R_A_WIDTH+r_generics.R_A_TYPE <= 25 and r_generics.R_B_WIDTH+r_generics.R_B_TYPE <= 18 report "ERROR: mult_gen: Symmetric rounding is only supported for a single DSP48E in Virtex-5" severity failure;
end if;
else
-- don't allow rounding for other multipliers - expensive
assert r_generics.R_ROUND_OUTPUT = MG_NO report "WARNING: mult_gen: Rounding is only supported for Virtex-4 and Virtex-5 DSP48(E)-based multipliers" severity warning;
r_generics.R_ROUND_OUTPUT := 0;
end if;
return r_generics;
end function check_generics;
function sl_to_int(sl : std_logic) return integer is
begin -- FUNCTION sl_to_int
if sl = '1' then
return 1;
else
return 0;
end if;
end function sl_to_int;
function mult_gen_log2(x : integer) return integer is
variable y : integer;
variable two_to_the_y : integer;
begin
y := 0;
two_to_the_y := 1;
while (two_to_the_y < x) loop
y := y+1;
two_to_the_y := two_to_the_y * 2;
end loop;
return y;
end mult_gen_log2;
function mult_gen_log2d(x : integer) return integer is
variable y : integer;
variable two_to_the_y : integer;
begin
y := 0;
two_to_the_y := 1;
while (two_to_the_y < x) loop
y := y+1;
two_to_the_y := two_to_the_y * 2;
end loop;
if two_to_the_y > x then
y := y - 1;
end if;
return y;
end mult_gen_log2d;
-- purpose: figures out the number of PPs in each dimension of the multiplier array
-- may require an extra PP for optimised DSP48E-based implementations
function calc_dsp48_pps (family : string; op_width : WIDTH_REC) return R_DSP_PP is
variable pps : R_DSP_PP := (a_pp => 0, b_pp => 0, extra_b_pp => 0);
begin -- function calc_pps
if supports_dsp48e(family) = 0 then
-- no asymmetric multiplier...
pps.a_pp := calc_a_pp(family, op_width);
pps.b_pp := calc_b_pp(op_width);
pps.extra_b_pp := 0;
else
-- scope for some optimisations to reduce DSP count
pps.a_pp := calc_a_pp(family, op_width);
if (op_width.a > 42 and op_width.a <= 59 and op_width.b > 52 and op_width.b <= 59)
or (op_width.a > 25 and op_width.a <= 42 and op_width.b > 35 and op_width.b <= 42)
or (op_width.a > 25 and op_width.a <= 42 and op_width.b > 52 and op_width.b <= 59) then
-- can perform this multiply in only 10 DSPs, rather than 12.
-- subtract one row from B, and one to the extra_b_pp element
-- this should yield a_pp = 3, b_pp = 3, extra_b_pp = 1
pps.b_pp := calc_b_pp(op_width) - 1;
pps.extra_b_pp := 1;
else
pps.b_pp := calc_b_pp(op_width);
pps.extra_b_pp := 0;
end if;
end if;
return pps;
end function calc_dsp48_pps;
function func_term_number(an : integer; bn : integer; s : integer) return integer is
variable mn : integer;
begin
mn := bn;
if (an = bn) then
return 2*mn+s-1;
else
return 2*mn+s;
end if;
end function func_term_number;
function adder_layer_number_calc(width : integer) return integer is
variable layer_counter : integer := 0;
variable adder_counter : integer;
variable input_counter : integer;
begin
input_counter := width;
while input_counter > 1 loop
layer_counter := layer_counter + 1;
adder_counter := input_counter/3;
if adder_counter = 0 and input_counter = 2 then -- Final two-input counter
adder_counter := 1;
input_counter := 1;
else
input_counter := input_counter - adder_counter*3; -- count the unused inputs
input_counter := input_counter + adder_counter; -- add the outputs from the adders
end if;
-- report "ADDER TREE: Adder number is " & integer'image(adder_counter) &", output = "&integer'image(input_counter) &" in layer "& integer'image(layer_counter);
end loop;
-- report "Layer number is " & integer'image(layer_counter) severity note;
return layer_counter;
end function adder_layer_number_calc;
function mult_gen_v11_2_calc_fully_pipelined_latency (family : string;
a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp : integer;
b_value : string) return integer is
begin
return mult_gen_v11_2_calc_fully_pipelined_latency_internal(family, a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp, b_value, 1);
end function mult_gen_v11_2_calc_fully_pipelined_latency;
-- If 'standalone' is set to 1, the latency of a Spartan-6 multiplier will be
-- 2 cycles. If 'standalone' = 0, we assume that the adder will be used, so
-- the latency will be 3 cycles
function mult_gen_v11_2_calc_fully_pipelined_latency_internal (family : string;
a_width, a_type, b_width, b_type, mult_type, opt_goal, ccm_imp : integer;
b_value : string;
standalone : integer := 1) return integer is
-- General use variables
variable latency : integer := 0;
variable a_pp : integer := 0;
variable b_pp : integer := 0;
variable num_pp : integer := 0;
variable dsp_pps : R_DSP_PP := (a_pp => 0, b_pp => 0, extra_b_pp => 0);
variable op_width : WIDTH_REC;
variable port_size : PORT_ASPECTS := get_port_sizes(family);
-- variables for the CCM calculations
variable rom_latency : integer := 0;
variable rom_addr_width : integer := 0;
variable a_input_width : integer := 0;
variable num_pps : integer := 0;
variable const_power_of_two : boolean := false;
variable const_is_zero : boolean := false;
-- variables for the hybrid configurations
variable widths : WIDTH_REC;
variable block_mult_pipeline : integer;
variable block_mult_output_pipeline : integer;
variable hybrid_cfg : integer;
variable block_mult_cfg : BLOCK_MULT_REC;
variable one_mult_cfg : ONE_MULT_REC;
variable two_mult_cfg : TWO_MULT_REC;
variable top_mult_a_width : integer := 0;
variable top_mult_b_width : integer := 0;
variable side_mult_a_width : integer := 0;
variable side_mult_b_width : integer := 0;
variable deepest_lut_mult_tree : integer := 0;
variable deepest_pipeline : integer := 0;
variable adder_latency : integer := 0;
variable fab_prereg : integer := 0;
variable Creg : integer := 0;
-- variables for the embedded mult CCM
variable reqd_b_value : string(1 to calc_reqd_b_width(b_value,b_width, b_type, false));
variable trimmed_msbs : integer := 0;
variable trimmed_lsbs : integer := 0;
-- variables for LUT6 mult (area optimised)
variable sign_correction : integer := 0;
variable a_digit_number, b_digit_number : integer := 0;
begin -- FUNCTION mult_gen_v11_2_calc_fully_pipelined_latency_internal
if mult_type = FIXED_CCM then
-- check to see if the constant is exactly a (positive) power of 2
-- use this to set up the latency of the fixed CCM later on
trimmed_msbs := get_trimmed_leading_bits(b_value, b_type, mult_type);
trimmed_lsbs := calc_shift_bits(b_value, 1);
const_power_of_two := check_const_power_of_two(b_value, b_type, mult_type);
-- b_width should represent the length of the b_value string - required
-- for VTFC support, as 'length cannot be used
const_is_zero := check_b_value_all_zeros(b_value, b_width);
end if;
-- swap the operands around to get the best operand size for each PORT
-- Any invalid families will be caught in this routine
op_width := get_true_widths(family, a_width, b_width, a_type, b_type, port_size);
case mult_type is
when LUT =>
if opt_goal = CORE_SPEED then
if get_min(a_width, b_width) = 1 then
latency := 1;
else
latency := mult_gen_log2(get_min(a_width, b_width));
end if;
else
if a_type = 1 and b_type = 1 then
-- unsigned
sign_correction := 0;
else
sign_correction := 1;
end if;
a_digit_number := (mult_gen_max_of(a_width, b_width)+2)/3;
b_digit_number := (get_min(a_width, b_width)+2)/3;
latency := adder_layer_number_calc(func_term_number(a_digit_number, b_digit_number, sign_correction)) + 1;
end if;
when EMBEDDED_MULT =>
case opt_goal is
when CORE_SPEED =>
-- To account for possible extra DSP in V5 optimised cases
dsp_pps := calc_dsp48_pps(family, op_width);
num_pp := (dsp_pps.a_pp * dsp_pps.b_pp) + dsp_pps.extra_b_pp;
a_pp := dsp_pps.a_pp;
b_pp := dsp_pps.b_pp;
if supports_dsp48(family) = 1 or supports_dsp48e(family) > 0 then
-- latency is determined by # DSP48(E)s used - call a_pp and b_pp calculation functions
latency := num_pp + 2; -- A/Breg + Mreg in first DSP + Pregs in all DSPs above it in the column
elsif supports_dsp48a(family) > 0 then
-- There's no simple formula to work out what the latency will
-- be based on the number of DSPs. It depends how many wireshifts we need in
-- the fabric (i.e. how many times the C port needs to be used)
if a_pp = 1 and b_pp = 1 then
if supports_dsp48a1(family) > 0 and standalone = 1 then
-- 2-cycle mult in Spartan-6
latency := 2;
else
latency := 3;
end if;
elsif a_pp = 2 and b_pp = 1 then
latency := 5;
elsif a_pp = 3 and b_pp = 1 then
latency := 7;
elsif a_pp = 4 and b_pp = 1 then
latency := 9;
elsif a_pp = 2 and b_pp = 2 then
latency := 8;
elsif a_pp = 3 and b_pp = 2 then
latency := 11;
elsif a_pp = 3 and b_pp = 3 then
latency := 15;
elsif a_pp = 4 and b_pp = 2 then
latency := 14;
elsif a_pp = 4 and b_pp = 3 then
latency := 19;
elsif a_pp = 4 and b_pp = 4 then
latency := 24;
end if;
elsif supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 then
-- latency is determined by depth of adder tree required, which is determined by the number of Mult18x18s required
-- Add two for the register stage and fabric register in V2 and S3 multipliers, add 3 for the
-- Mult18x18SIO in S3E - 2 for the multiplier and 1 for the post-output fabric
latency := mult_gen_log2(num_pp) + 2 + (boolean'pos(supports_mult18x18sio(family) = 1));
else
report "ERROR: invalid family caught in EMB_MULT/CORE_SPEED in mult_gen_v11_2_calc_fully_pipelined_latency"
severity failure;
end if;
when EMB_MULT_RESOURCES =>
-- fully-pipelined latency depends on if the fabric portion or the
-- embedded mult portion is deeper in terms of registers
-- Account for operand swapping
if a_width > b_width then
widths.a := a_width;
widths.a_type := a_type;
widths.b := b_width;
widths.b_type := b_type;
op_width.a := a_width;
op_width.a_type := a_type;
op_width.b := b_width;
op_width.b_type := b_type;
else
widths.a := b_width;
widths.a_type := b_type;
widths.b := a_width;
widths.b_type := a_type;
op_width.a := b_width;
op_width.a_type := b_type;
op_width.b := a_width;
op_width.b_type := a_type;
end if;
assert not(debug) report "widths.a " & integer'image(widths.a) severity note;
assert not(debug) report "widths.a_type " & integer'image(widths.a_type) severity note;
assert not(debug) report "widths.b " & integer'image(widths.b) severity note;
assert not(debug) report "widths.b_type " & integer'image(widths.b_type) severity note;
if supports_dsp48(family) = 1 or supports_dsp48e(family) > 0 or supports_dsp48a(family) > 0 then
-- New approach
-- Consider paths to the adder in the DSP48x
-- Areg/Breg + Mreg gives 2 cycles of latency
block_mult_pipeline := 2;
-- The pipeline after the DSP48x adder is defined by the number
-- of DSPs used (number of registers in the P cascade)
a_pp := hybrid_calc_a_pp(family, op_width);
b_pp := hybrid_calc_b_pp(family, op_width);
block_mult_output_pipeline := a_pp * b_pp;
assert not(debug) report "a_pp " & integer'image(a_pp) severity note;
assert not(debug) report "b_pp " & integer'image(b_pp) severity note;
assert not(debug) report "block_mult_output_pipeline " & integer'image(block_mult_output_pipeline) severity note;
assert not(debug) report "block_mult_output_pipeline is " & integer'image(block_mult_output_pipeline) severity note;
hybrid_cfg := get_hybrid_configuration(family, a_pp, b_pp, widths, port_size);
block_mult_cfg := get_block_mult_cfg (family, a_pp, b_pp, widths, hybrid_cfg, port_size);
assert not(debug) report "hybrid_cfg is " & integer'image(hybrid_cfg) severity note;
assert not(debug) report "block_mult_cfg.a_width " & integer'image(block_mult_cfg.a_width) severity note;
assert not(debug) report "block_mult_cfg.a_type " & integer'image(block_mult_cfg.a_type) severity note;
assert not(debug) report "block_mult_cfg.b_width " & integer'image(block_mult_cfg.b_width) severity note;
assert not(debug) report "block_mult_cfg.b_type " & integer'image(block_mult_cfg.b_type) severity note;
if hybrid_cfg = ONE_MULT then
one_mult_cfg := get_one_mult_cfg(widths,
block_mult_cfg.a_width, block_mult_cfg.a_type, block_mult_cfg.b_width, block_mult_cfg.b_type,
hybrid_cfg, port_size);
top_mult_a_width := one_mult_cfg.a;
top_mult_b_width := one_mult_cfg.b;
side_mult_a_width := 0;
side_mult_b_width := 0;
assert not(debug) report "top_mult_a_width = " & integer'image(top_mult_a_width) severity note;
assert not(debug) report "top_mult_b_width = " & integer'image(top_mult_b_width) severity note;
assert not(debug) report "side_mult_a_width = " & integer'image(side_mult_a_width) severity note;
assert not(debug) report "side_mult_b_width = " & integer'image(side_mult_b_width) severity note;
deepest_lut_mult_tree := fab_mult_full_pipe_lat(top_mult_a_width, top_mult_b_width);
elsif hybrid_cfg = TWO_MULT then
two_mult_cfg := get_two_mult_cfg(widths, block_mult_cfg.a_width, block_mult_cfg.a_type, block_mult_cfg.b_width, block_mult_cfg.b_type, hybrid_cfg);
top_mult_a_width := two_mult_cfg.a_top;
top_mult_b_width := two_mult_cfg.b_top;
side_mult_a_width := two_mult_cfg.a_side;
side_mult_b_width := two_mult_cfg.b_side;
assert not(debug) report "top_mult_a_width = " & integer'image(top_mult_a_width) severity note;
assert not(debug) report "top_mult_b_width = " & integer'image(top_mult_b_width) severity note;
assert not(debug) report "side_mult_a_width = " & integer'image(side_mult_a_width) severity note;
assert not(debug) report "side_mult_b_width = " & integer'image(side_mult_b_width) severity note;
deepest_lut_mult_tree := mult_gen_max_of(fab_mult_full_pipe_lat(top_mult_a_width, top_mult_b_width), fab_mult_full_pipe_lat(side_mult_a_width, side_mult_b_width));
end if;
if hybrid_cfg = BASE_MULT then
adder_latency := 0;
Creg := 0;
elsif hybrid_cfg = ONE_MULT then
adder_latency := 0;
Creg := 1;
elsif hybrid_cfg = TWO_MULT then
adder_latency := 1;
Creg := 1;
end if;
assert not(debug) report "deepest_lut_mult_tree is " & integer'image(deepest_lut_mult_tree) severity note;
-- Work out the deepest path to the adder in the LS DSP48
deepest_pipeline := mult_gen_max_of(block_mult_pipeline, (deepest_lut_mult_tree + adder_latency + Creg));
-- Don't actually need the pre-register for best performance...
fab_prereg := 0;
latency := fab_prereg + deepest_pipeline + block_mult_output_pipeline;
elsif supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 then
-- calc number of emb mults
-- calc_tree_latency via mult_gen_log2 routine
-- if V2 or S3, add 2 to tree lat
-- if S3E, add 3 to tree lat
-- get configuration of hybrid
-- get widths of lut mults
-- get max depth of the lut mults, if they are required
-- work out max depth from lut mults and the embedded mult
-- add in any adder latency to this final value
a_pp := hybrid_calc_a_pp(family, op_width);
b_pp := hybrid_calc_b_pp(family, op_width);
num_pp := a_pp * b_pp;
-- work out the latency of the adder tree based on the number
-- on embedded multipliers used, and then add the latency of
-- the embedded multipliers themselves for best performance
if supports_mult18x18s(family) = 1 then
block_mult_pipeline := mult_gen_log2(num_pp) + 2;
elsif supports_mult18x18sio(family) = 1 then
block_mult_pipeline := mult_gen_log2(num_pp) + 3;
end if;
hybrid_cfg := get_hybrid_configuration(family, a_pp, b_pp, widths, port_size);
block_mult_cfg := get_block_mult_cfg (family, a_pp, b_pp, widths, hybrid_cfg, port_size);
if hybrid_cfg = ONE_MULT then
one_mult_cfg := get_one_mult_cfg(widths,
block_mult_cfg.a_width, block_mult_cfg.a_type, block_mult_cfg.b_width, block_mult_cfg.b_type,
hybrid_cfg, port_size);
top_mult_a_width := one_mult_cfg.a;
top_mult_b_width := one_mult_cfg.b;
side_mult_a_width := 0;
side_mult_b_width := 0;
deepest_lut_mult_tree := fab_mult_full_pipe_lat(top_mult_a_width, top_mult_b_width);
elsif hybrid_cfg = TWO_MULT then
two_mult_cfg := get_two_mult_cfg(widths, block_mult_cfg.a_width, block_mult_cfg.a_type, block_mult_cfg.b_width, block_mult_cfg.b_type, hybrid_cfg);
top_mult_a_width := two_mult_cfg.a_top;
top_mult_b_width := two_mult_cfg.b_top;
side_mult_a_width := two_mult_cfg.a_side;
side_mult_b_width := two_mult_cfg.b_side;
deepest_lut_mult_tree := mult_gen_max_of(fab_mult_full_pipe_lat(top_mult_a_width, top_mult_b_width), fab_mult_full_pipe_lat(side_mult_a_width, side_mult_b_width));
end if;
if hybrid_cfg = BASE_MULT then
adder_latency := 0;
elsif hybrid_cfg = ONE_MULT then
adder_latency := 0;
elsif hybrid_cfg = TWO_MULT then
adder_latency := 1;
end if;
deepest_pipeline := mult_gen_max_of(block_mult_pipeline, (deepest_lut_mult_tree + adder_latency));
-- Add one cycle of latency for the register on the final adder
-- which sums all the partial products together
latency := deepest_pipeline + 1;
else
report "ERROR: invalid family caught in EMB_MULT/EMB_MULT_RESOURCES in mult_gen_v11_2_calc_fully_pipelined_latency"
severity failure;
end if;
when others => null;
end case;
when FIXED_CCM =>
if const_power_of_two or const_is_zero then
-- can perform the multiply just by bit-shifting - no logic required
-- or just generate constant zeros at the output
latency := 0;
else
case ccm_imp is
when DIST_MEM =>
rom_latency := 1;
if supports_lut6(family) = 1 then
rom_addr_width := 6;
else
rom_addr_width := 4;
end if;
a_input_width := calc_a_input_width(a_width, 0, rom_addr_width, 0);
num_pps := calc_num_pps(a_input_width, rom_addr_width);
-- log2 function will return 0 if 0 is input, which works for this application
latency := mult_gen_log2((num_pps * boolean'pos(num_pps > 1))) + rom_latency;
when BRAM =>
if supports_ramb18(family) > 0 or supports_ramb16bwer(family) > 0 or supports_ramb16(family) = 1 then
-- add 1 cycle for speed-up register
rom_latency := 3;
else
rom_latency := 2;
end if;
-- Fixed width for all supported families (18K BRAM)
rom_addr_width := 9;
a_input_width := calc_a_input_width(a_width, 0, rom_addr_width, 0);
num_pps := calc_num_pps(a_input_width, rom_addr_width);
-- log2 function will return 0 if 0 is input, which works for this application
latency := mult_gen_log2((num_pps * boolean'pos(num_pps > 1))) + rom_latency;
when MULTS =>
reqd_b_value := calc_reqd_b_value(b_value, b_width, b_type, calc_reqd_b_width(b_value,b_width, b_type, false));
-- modify op_width.b to reflect the number of bits from the
-- constant value that actually need to go through the multiplier
trimmed_lsbs := get_output_scaling(b_value, b_type, mult_type);
trimmed_msbs := get_trimmed_leading_bits(b_value, b_type, mult_type);
-- Completely reset the op_width record contents
op_width := get_true_widths(family, a_width, (reqd_b_value'length - (trimmed_lsbs + trimmed_msbs)), a_type, b_type, port_size);
-- calc_dsp48_pps will work for mult18x18-based families too!
dsp_pps := calc_dsp48_pps(family, op_width);
num_pp := (dsp_pps.a_pp * dsp_pps.b_pp) + dsp_pps.extra_b_pp;
a_pp := dsp_pps.a_pp;
b_pp := dsp_pps.b_pp;
if supports_dsp48(family) = 1 or supports_dsp48e(family) > 0 then
-- latency is determined by # DSP48(E)s used - call a_pp and b_pp calculation functions
latency := num_pp + 2; -- A/Breg + Mreg in first DSP + Pregs in all DSPs above it in the column
elsif supports_dsp48a(family) > 0 then
-- There's no simple formula to work out what the latency will
-- be based on the number of DSPs. It depends how many wireshifts we need in
-- the fabric (i.e. how many times the C port needs to be used)
if a_pp = 1 and b_pp = 1 then
if supports_dsp48a1(family) > 0 and standalone = 1 then
-- 2-cycle mult in Spartan-6
latency := 2;
else
latency := 3;
end if;
elsif a_pp = 2 and b_pp = 1 then
latency := 5;
elsif a_pp = 3 and b_pp = 1 then
latency := 7;
elsif a_pp = 4 and b_pp = 1 then
latency := 9;
elsif a_pp = 2 and b_pp = 2 then
latency := 8;
elsif a_pp = 3 and b_pp = 2 then
latency := 11;
elsif a_pp = 3 and b_pp = 3 then
latency := 15;
elsif a_pp = 4 and b_pp = 2 then
latency := 14;
elsif a_pp = 4 and b_pp = 3 then
latency := 19;
elsif a_pp = 4 and b_pp = 4 then
latency := 24;
end if;
elsif supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 then
-- latency is determined by depth of adder tree required, which is determined by the number of Mult18x18s required
-- Add one for the register stage in V2 and S3 multipliers, add 3 for the Mult18x18SIO in S3E - 2 for the multiplier and 1 for the post-output fabric
latency := mult_gen_log2(num_pp) + 2 + (boolean'pos(supports_mult18x18sio(family) = 1));
else
report "ERROR: invalid family caught in FIXED_CCM/MULTS in mult_gen_v11_2_calc_fully_pipelined_latency"
severity failure;
end if;
when CSD =>
report "WARNING: The core cannot calculate the fully-pipelined latency - check XST log (if available)" severity warning;
latency := 0;
when others =>
report "ERROR: invalid c_ccm_imp caught in mult_gen_v11_2_calc_fully_pipelined_latency" severity failure;
end case;
end if;
when others =>
report "ERROR: invalid mult_type caught in mult_gen_v11_2_calc_fully_pipelined_latency" severity failure;
end case;
return latency;
end function mult_gen_v11_2_calc_fully_pipelined_latency_internal;
-- purpose: works out if the operands need to be swapped around and generates the correct widths for them
-- these values can then be used to control the wire swapping in the hardware generation
function get_true_widths(family : string;
c_a_width, c_b_width, c_a_type, c_b_type : integer;
port_size : PORT_ASPECTS) return WIDTH_REC is
variable ret : WIDTH_REC := (a => 0, b => 0, a_type => 0, b_type => 0, swap => false);
constant full_a_width : integer := c_a_width+c_a_type;
constant full_b_width : integer := c_b_width+c_b_type;
variable a_pp_1, a_pp_2 : integer := 0;
variable b_pp_1, b_pp_2 : integer := 0;
variable res_1, res_2 : integer := 0;
variable widths : WIDTH_REC := (a => 0, b => 0, a_type => 0, b_type => 0, swap => false);
begin -- FUNCTION get_true_widths
assert not(fn_debug) report "entered get_true_widths" severity note;
if supports_dsp48(family) = 1 or supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 or supports_dsp48a(family) > 0 then
-- All the families with 18x18 multipliers, be they mult18s or DSP primitives
if full_a_width >= full_b_width then
-- no swapping required
ret.swap := false;
if c_a_type = C_SIGNED then
ret.a := c_a_width;
elsif c_a_type = C_UNSIGNED then
ret.a := c_a_width+1;
end if;
if c_b_type = C_SIGNED then
ret.b := c_b_width;
elsif c_b_type = C_UNSIGNED then
ret.b := c_b_width+1;
end if;
ret.a_type := c_a_type;
ret.b_type := c_b_type;
else
-- need to swap the operands around
ret.swap := true;
if c_b_type = 0 then
ret.a := c_b_width;
elsif c_b_type = 1 then
ret.a := c_b_width+1;
end if;
if c_a_type = C_SIGNED then
ret.b := c_a_width;
elsif c_a_type = C_UNSIGNED then
ret.b := c_a_width+1;
end if;
ret.a_type := c_b_type;
ret.b_type := c_a_type;
end if;
elsif supports_dsp48e(family) > 0 then
-- Harder to work out when we need to swap the operands over here
-- because of the asymmetric multiplier - more efficient for some widths not to swap the operands!
-- Check to see if the operand sizes as they are supplied to the core
-- fit one of the optimal array configurations - if not, we want to
-- swap A and B over since that will fit one of the patterns
-- i.e. 42x64 and 64x42 will both be implemented on an a_pp=2, b_pp=4
-- array rather than using the (much larger) a_pp=4, b_pp=3 array
-- don't swap operands over - the last argument doesn't matter here!
widths := (a => c_a_width, b => c_b_width, a_type => c_a_type, b_type => c_b_type, swap => false);
a_pp_1 := calc_a_pp(family, widths);
b_pp_1 := calc_b_pp(widths);
-- swap the operands over - the last argument doesn't matter here!
widths := (a => c_b_width, b => c_a_width, a_type => c_b_type, b_type => c_a_type, swap => false);
a_pp_2 := calc_a_pp(family, widths);
b_pp_2 := calc_b_pp(widths);
-- compare the two results - pick the smallest one!
res_1 := a_pp_1 * b_pp_1;
res_2 := a_pp_2 * b_pp_2;
assert not(debug) report "res_1 (a_pp_1 * b_pp_1) is " & integer'image(res_1);
assert not(debug) report "res_2 (a_pp_2 * b_pp_2) is " & integer'image(res_2);
if res_1 <= res_2 then
-- leave as is - don't swap the operands
ret.swap := false;
if c_a_type = C_SIGNED then
ret.a := c_a_width;
elsif c_a_type = C_UNSIGNED then
ret.a := c_a_width+1;
end if;
if c_b_type = C_SIGNED then
ret.b := c_b_width;
elsif c_b_type = C_UNSIGNED then
ret.b := c_b_width+1;
end if;
ret.a_type := c_a_type;
ret.b_type := c_b_type;
else
-- operand sizes don't fit one of the optimal patterns,
-- so swap them around so that they will fit one of the patterns
ret.swap := true;
assert not(debug) report "swapping operands internally" severity note;
if c_b_type = 0 then
ret.a := c_b_width;
elsif c_b_type = 1 then
ret.a := c_b_width+1;
end if;
if c_a_type = C_SIGNED then
ret.b := c_a_width;
elsif c_a_type = C_UNSIGNED then
ret.b := c_a_width+1;
end if;
ret.a_type := c_b_type;
ret.b_type := c_a_type;
end if;
else
report "ERROR: mult_pkg.vhd: invalid family " & family & " caught in dsp.vhd/get_true_widths()"
severity error;
end if;
-- if an operand is smaller than the port width for a DSP,
-- round it up so it uses the full port width - this helps when the
-- multiplier is to be inferred
if ret.a < port_size.a then
ret.a := port_size.a;
end if;
if ret.b < port_size.b then
ret.b := port_size.b;
end if;
assert not(fn_debug) report "leaving get_true_widths" severity note;
return ret;
end function get_true_widths;
-- purpose: works out how many partial products are required for the A operand (number of DSPs)
function calc_a_pp(family : string; op_width : WIDTH_REC) return integer is
variable a_pp : integer := 0;
constant width_minus_18 : integer := op_width.a - 18;
constant width_minus_25 : integer := op_width.a - 25;
constant width_gt_18 : boolean := (op_width.a > 18);
constant width_gt_25 : boolean := (op_width.a > 25);
constant arg1 : integer := (width_minus_18/17)*boolean'pos(width_gt_18);
constant arg2 : integer := boolean'pos(width_minus_18 mod 17 /= 0 and width_gt_18);
constant arg11 : integer := (width_minus_25/17)*boolean'pos(width_gt_25);
constant arg21 : integer := boolean'pos(width_minus_25 mod 17 /= 0 and width_gt_25);
constant supports_25bit_mult : boolean := (supports_dsp48e(family) > 0);
begin -- FUNCTION calc_a_pp
assert not(fn_debug) report "entered calc_a_pp" severity note;
assert not(debug) report "op_width.a is " & integer'image(op_width.a) severity note;
if supports_25bit_mult then
a_pp := 1 + arg11 + arg21;
else
a_pp := 1 + arg1 + arg2;
end if;
assert not(debug) report "a_pp count: " & integer'image(a_pp) severity note;
assert not(fn_debug) report "leaving calc_a_pp" severity note;
return a_pp;
end function calc_a_pp;
-- purpose: works out how many partial products are required for the B operand (number of DSPs)
-- note that there is no family restriction here because DSP48 and DSP48E
-- both have 18-bit B ports on the multiplier
function calc_b_pp(op_width : WIDTH_REC) return integer is
variable b_pp : integer := 0;
constant width_minus_18 : integer := op_width.b - 18;
constant width_gt_18 : boolean := (op_width.b > 18);
constant arg1 : integer := (width_minus_18/17)*boolean'pos(width_gt_18);
constant arg2 : integer := boolean'pos(width_minus_18 mod 17 /= 0 and width_gt_18);
begin -- FUNCTION calc_b_pp
assert not(fn_debug) report "entered calc_b_pp" severity note;
assert not(debug) report "op_width.b is " & integer'image(op_width.b) severity note;
b_pp := 1 + arg1 + arg2;
assert not(debug) report "b_pp count: " & integer'image(b_pp) severity note;
assert not(fn_debug) report "leaving calc_b_pp" severity note;
return b_pp;
end function calc_b_pp;
-- purpose: works out how many partial products are required for the A operand (number of DSPs/MULT18X18s)
function hybrid_calc_a_pp(family : string; op_width : WIDTH_REC) return integer is
variable a_pp : integer := 0;
constant port_size_a : integer := 18+(7*boolean'pos(supports_dsp48e(family) > 0));
variable found_match : boolean := false;
constant a : integer := op_width.a+op_width.a_type;
constant b : integer := op_width.b+op_width.b_type;
begin -- FUNCTION hybrid_calc_a_pp
if supports_dsp48e(family) > 0 then
-- pick out the particular configurations that are supported
-- widths will be swapped so that the largest is on the A operand
-- perform the PP allocation in reverse order so that we don't need to trap as many cases
if op_width.a+op_width.a_type >= 42 and op_width.b+op_width.b_type >= 35 then
-- 2x2 configuration
a_pp := 2;
assert not(debug) report "DSP48E 2x2 configuration - a_pp" severity note;
elsif op_width.a+op_width.a_type >= 35 then
-- could implement a 2x1 or 1x2 array here - depends on the operand
-- widths to get best logic utilisation
if a >= 35 and a < 42 and b >= 25 then
-- 1x2 - shorter carry chain
a_pp := 1;
elsif a >= 42 and b >= 25 then
-- 2x1 - no choice
a_pp := 2;
elsif a >= 35 and a < 42 and b < 25 then
-- 1x2
a_pp := 1;
elsif a >= 42 and b < 25 then
a_pp := 2;
elsif a >= 42 and b >= 25 then
a_pp := 2;
end if;
elsif (op_width.a+op_width.a_type >= 25 and op_width.b+op_width.b_type >= 18)
or (op_width.a+op_width.a_type <= 25 and op_width.b+op_width.b_type >= 18)
or (op_width.a+op_width.a_type >= 25 and op_width.b+op_width.b_type <= 18) then
-- 1x1 CONFIGURATION
a_pp := 1;
assert not(debug) report "DSP48E 1x1 configuration - a_pp" severity note;
elsif op_width.a+op_width.a_type <= 25 and op_width.b+op_width.b_type <= 18 then
-- base mult - no fabric
a_pp := 1;
assert not(debug) report "DSP48E base mult configuration - a_pp" severity note;
end if;
else
a_pp := calc_a_pp(family, op_width);
if (op_width.a-(port_size_a)) mod 17 /= 0 and op_width.a > port_size_a then
a_pp := a_pp-1;
end if;
end if;
assert not(debug) report "hybrid a_pp count: " & integer'image(a_pp) severity note;
return a_pp;
end function hybrid_calc_a_pp;
-- purpose: works out how many partial products are required for the B operand (number of DSPs/MULT18X18s)
-- note that there is no family restriction here because MULT18X18, DSP48 and DSP48E
-- both have 18-bit B ports on the multiplier
function hybrid_calc_b_pp(family : string; op_width : WIDTH_REC) return integer is
variable b_pp : integer := 0;
variable int_width : integer := op_width.b;
constant port_size_b : integer := 18;
variable found_match : boolean := false;
constant a : integer := op_width.a+op_width.a_type;
constant b : integer := op_width.b+op_width.b_type;
begin -- FUNCTION hybrid_calc_b_pp
if supports_dsp48e(family) > 0 then
-- widths will be swapped so that the largest is on the A operand
-- perform the PP allocation in reverse order so that we don't need to trap as many cases
if op_width.a+op_width.a_type >= 42 and op_width.b+op_width.b_type >= 35 then
-- 2x2 configuration
b_pp := 2;
assert not(debug) report "DSP48E 2x2 configuration - b_pp" severity note;
elsif op_width.a+op_width.a_type >= 35 then
-- could implement a 2x1 or 1x2 array here - depends on the operand
-- widths to get best logic utilisation
if a >= 35 and a < 42 and b >= 25 then
-- 1x2 - shorter carry chain
b_pp := 2;
elsif a >= 42 and b >= 25 then
-- 2x1 - no choice
b_pp := 1;
elsif a >= 35 and a < 42 and b < 25 then
-- 1x2
b_pp := 2;
elsif a >= 42 and b < 25 then
b_pp := 1;
elsif a >= 42 and b >= 25 then
b_pp := 1;
end if;
elsif (op_width.a+op_width.a_type >= 25 and op_width.b+op_width.b_type >= 18)
or (op_width.a+op_width.a_type <= 25 and op_width.b+op_width.b_type >= 18)
or (op_width.a+op_width.a_type >= 25 and op_width.b+op_width.b_type <= 18) then
-- 1x1 CONFIGURATION
b_pp := 1;
assert not(debug) report "DSP48E 1x1 configuration - b_pp" severity note;
elsif op_width.a+op_width.a_type <= 25 and op_width.b+op_width.b_type <= 18 then
-- base mult - no fabric
b_pp := 1;
assert not(debug) report "DSP48E base mult configuration - b_pp" severity note;
end if;
else
b_pp := calc_b_pp(op_width);
if (op_width.b-(port_size_b)) mod 17 /= 0 and op_width.b > port_size_b then
b_pp := b_pp-1;
end if;
end if;
assert not(debug) report "hybrid b_pp count: " & integer'image(b_pp) severity note;
return b_pp;
end function hybrid_calc_b_pp;
-- purpose: works out which configuration of hybrid is required based on the input operand widths
-- and types and the multiplier primitive being used
function get_hybrid_configuration(family : string;
a_pp, b_pp : integer;
op_width : WIDTH_REC;
port_size : PORT_ASPECTS)return integer is
variable full_a_width : integer := 0;
variable full_b_width : integer := 0;
variable ret : integer := 99; -- error code - should always be assigned later
constant right_shift : integer := 17;
begin -- FUNCTION get_hybrid_configuration
full_a_width := op_width.a+op_width.a_type;
full_b_width := op_width.b+op_width.b_type;
assert not(debug) report "full_a_width is " & integer'image(full_a_width) severity note;
assert not(debug) report "full_b_width is " & integer'image(full_b_width) severity note;
if a_pp = 1 and b_pp = 1 then
if full_a_width <= port_size.a and full_b_width <= port_size.b then
ret := BASE_MULT;
assert not(debug) report "1x1 base mult" severity note;
elsif (full_a_width > port_size.a and full_b_width <= port_size.b) or (full_a_width <= port_size.a and full_b_width > port_size.b) then
ret := ONE_MULT;
assert not(debug) report "1x1 one fabric mult" severity note;
elsif full_a_width > port_size.a and full_b_width > port_size.b then
ret := TWO_MULT;
assert not(debug) report "1x1 two fabric mults" severity note;
end if;
elsif (a_pp = 2 and b_pp = 1) then
if full_a_width <= port_size.a+right_shift and full_b_width <= port_size.b then
ret := BASE_MULT;
assert not(debug) report "2x1 base mult" severity note;
elsif (full_a_width > port_size.a+right_shift and full_b_width <= port_size.b) or (full_a_width <= port_size.a+right_shift and full_b_width >= port_size.b) then
ret := ONE_MULT;
assert not(debug) report "2x1 one fabric mult" severity note;
elsif full_a_width > port_size.a+right_shift and full_b_width >= port_size.b then
ret := TWO_MULT;
assert not(debug) report "2x1 two fabric mults" severity note;
end if;
elsif a_pp = 1 and b_pp = 2 then
if (full_b_width <= port_size.a and full_a_width <= port_size.b+right_shift) then
ret := BASE_MULT;
assert not(debug) report "1x2 base mult" severity note;
elsif (full_b_width <= port_size.a and full_a_width >= port_size.b+right_shift) or (full_b_width >= port_size.a and full_a_width <= port_size.b+right_shift) then
ret := ONE_MULT;
assert not(debug) report "1x2 one fabric mult" severity note;
elsif (full_b_width > port_size.a and full_a_width > port_size.b+right_shift) then
ret := TWO_MULT;
assert not(debug) report "1x2 two fabric mults" severity note;
end if;
elsif a_pp = 2 and b_pp = 2 then
if full_a_width <= port_size.a+right_shift and full_b_width <= port_size.b+right_shift then
ret := BASE_MULT;
assert not(debug) report "2x2 base mult" severity note;
elsif (full_a_width > port_size.a+right_shift and full_b_width <= port_size.b+right_shift) or (full_a_width <= port_size.a+right_shift and full_b_width > port_size.b+right_shift) then
ret := ONE_MULT;
assert not(debug) report "2x2 one fabric mult" severity note;
elsif full_a_width > port_size.a+right_shift and full_b_width > port_size.b+right_shift then
ret := TWO_MULT;
assert not(debug) report "2x2 two fabric mults" severity note;
end if;
end if;
assert not(debug) report "hybrid_configuration is " & integer'image(ret) severity note;
assert ret /= 99 report "no valid configuration found" severity failure;
return ret;
end function get_hybrid_configuration;
-- purpose: works out the operand widths and types for the block multiplier subcomponent
function get_block_mult_cfg (family : string;
a_pp, b_pp : integer;
op_width : WIDTH_REC;
hybrid_cfg : integer;
port_size : PORT_ASPECTS) return BLOCK_MULT_REC is
variable ret : BLOCK_MULT_REC;
constant wire_shift : integer := 17;
variable mult_blocks : integer := 0;
constant a_width : integer := op_width.a;
constant a_type : integer := op_width.a_type;
constant b_width : integer := op_width.b;
constant b_type : integer := op_width.b_type;
variable a_port_size : integer := 0;
variable b_port_size : integer := 0;
begin -- FUNCTION get_block_mult_cfg
if a_width < port_size.a then
a_port_size := a_width;
else
a_port_size := port_size.a;
end if;
if b_width < port_size.b then
b_port_size := b_width;
else
b_port_size := port_size.b;
end if;
if a_pp = 1 and b_pp = 1 then
ret.a_width := a_port_size - boolean'pos(a_type = C_UNSIGNED and a_width >= port_size.a);
ret.b_width := b_port_size - boolean'pos(b_type = C_UNSIGNED and b_width >= port_size.b);
ret.a_type := a_type;
ret.b_type := b_type;
mult_blocks := 1;
elsif a_pp = 2 and b_pp = 1 then
ret.a_width := port_size.a+wire_shift - boolean'pos(a_type = C_UNSIGNED and a_width >= port_size.a);
ret.b_width := b_port_size - boolean'pos(b_type = C_UNSIGNED and b_width >= port_size.b);
ret.a_type := a_type;
ret.b_type := b_type;
mult_blocks := 2;
elsif a_pp = 1 and b_pp = 2 then
-- the operands will be swapped around so that the A operand is the largest
-- this means that we need to swap the a_type and b_type values over so
-- that they remain correct w.r.t. the operand widths
ret.a_width := port_size.b+wire_shift - boolean'pos(a_type = C_UNSIGNED);
ret.b_width := a_port_size - boolean'pos(b_type = C_UNSIGNED);
ret.a_type := a_type;
ret.b_type := b_type;
mult_blocks := 2;
elsif a_pp = 2 and b_pp = 2 then
ret.a_width := port_size.a+wire_shift - boolean'pos(a_type = C_UNSIGNED);
ret.b_width := port_size.b+wire_shift - boolean'pos(b_type = C_UNSIGNED);
ret.a_type := a_type;
ret.b_type := b_type;
mult_blocks := 4;
end if;
assert not(debug) report "Building hybrid around a " & integer'image(ret.a_width) & "x" & integer'image(ret.b_width) & " multiplier using " & integer'image(mult_blocks) & " block multipliers" severity note;
assert not(debug) report CR & "block_mult_cfg is: " &
CR & "a_width: " & integer'image(ret.a_width) &
CR & "b_width: " & integer'image(ret.b_width) &
CR & "a_type: " & integer'image(ret.a_type) &
CR & "b_type: " & integer'image(ret.b_type) & CR severity note;
return ret;
end function get_block_mult_cfg;
-- purpose: works out the required operand widths of the fabric multiplier for the 'one mult' case
function get_one_mult_cfg(width : WIDTH_REC;
block_a_width, block_a_type, block_b_width, block_b_type : integer;
hybrid_cfg : integer;
port_size : PORT_ASPECTS) return ONE_MULT_REC is
constant x_width : integer := block_a_width;
constant y_width : integer := block_b_width;
variable ret : ONE_MULT_REC;
variable print_debug : boolean := false;
begin -- FUNCTION get_one_mult_cfg
-- set defaults to avoid MTI disappearing...
ret.a := 0;
ret.b := 0;
ret.a_type := 0;
ret.b_type := 0;
ret.out_width := 0;
ret.bypass := 0;
ret.a_offset := 0;
ret.b_offset := 0;
assert not(debug) report "-------------------------------------------------------"
& CR & "get_one_mult_cfg width.a: " & integer'image(width.a) &
CR & "get_one_mult_cfg width.a_type: " & integer'image(width.a_type) &
CR & "get_one_mult_cfg width.b: " & integer'image(width.b) &
CR & "get_one_mult_cfg width.b_type: " & integer'image(width.b_type) &
CR & "get_one_mult_cfg hybrid_cfg " & integer'image(hybrid_cfg) &
CR & "get_one_mult_cfg x_width " &integer'image(x_width) &
CR & "get_one_mult_cfg y_width " & integer'image(y_width) &
CR & "-------------------------------------------------------" severity note;
if (width.a > x_width and (width.b <= y_width or y_width < port_size.b)) and hybrid_cfg = ONE_MULT then
assert not(debug) report "a_width > x_width and b_width <= y_width" severity note;
ret.a := width.a-x_width;
ret.b := width.b;
ret.a_type := C_UNSIGNED;
ret.b_type := width.b_type;
ret.bypass := ret.a;
ret.b_offset := 0;
ret.a_offset := ret.a;
print_debug := true;
end if;
-- this one doesn't work - do we even need this clause since the operands
-- are always swapped to make A the largest? What about the 1x2 V5 case?
if (width.a <= x_width and (width.b > y_width or y_width < port_size.b)) and hybrid_cfg = ONE_MULT then
assert not(debug) report "a_width <= x_width and b_width > y_width" severity note;
ret.a := width.a;
ret.b := width.b-y_width;
ret.a_type := width.a_type;
ret.b_type := C_UNSIGNED;
ret.bypass := ret.b;
ret.b_offset := ret.b;
ret.a_offset := 0;
print_debug := true;
end if;
ret.out_width := ret.a+ret.b;
assert not(debug) report CR & "one_mult_cfg is: " &
CR & "a: " & integer'image(ret.a) &
CR & "b: " & integer'image(ret.b) &
CR & "a_type: " & integer'image(ret.a_type) &
CR & "b_type: " & integer'image(ret.b_type) &
CR & "bypass: " & integer'image(ret.bypass) &
CR & "a_offset: " & integer'image(ret.a_offset) &
CR & "b_offset: " & integer'image(ret.b_offset) & CR severity note;
return ret;
end function get_one_mult_cfg;
-- purpose: works out the required operand widths of the fabric multiplier for the 'two mult' case
function get_two_mult_cfg(op_width : WIDTH_REC;
a_width, a_type, b_width, b_type : integer;
hybrid_cfg : integer) return TWO_MULT_REC is
constant x_width : integer := a_width;
constant y_width : integer := b_width;
variable ret : TWO_MULT_REC;
variable print_debug : boolean := false;
constant full_width_a : integer := op_width.a; --+op_width.a_type;
constant full_width_b : integer := op_width.b; --+op_width.b_type;
begin -- FUNCTION get_two_mult_cfg
-- set defaults to avoid MTI disappearing...
ret.a_top := 0;
ret.b_top := 0;
ret.a_type_top := 0;
ret.b_type_top := 0;
ret.out_width_top := 0;
ret.a_side := 0;
ret.b_side := 0;
ret.a_type_side := 0;
ret.b_type_side := 0;
ret.out_width_side := 0;
ret.mult_bypass := 0;
ret.add_bypass := 0;
ret.a_offset := 0;
ret.b_offset := 0;
assert not(debug) report "get_two_mult_cfg x_width is " & integer'image(x_width) severity note;
assert not(debug) report "get_two_mult_cfg y_width is " & integer'image(y_width) severity note;
assert not(debug) report "get_two_mult_cfg full_width_a is " & integer'image(full_width_a) severity note;
assert not(debug) report "get_two_mult_cfg full_width_b is " & integer'image(full_width_b) severity note;
if (full_width_a >= x_width and full_width_b >= y_width) and hybrid_cfg = TWO_MULT then -- condition for this configuration to be valid
-- The code above will automatically swap the operands so that the largest is
-- on the A bus. Because we only make 2 cuts in the partial product
-- array, this means that we want to make the A operand shorter than the B
-- operand to balance out the carry chain lengths for e.g. 22x20 multipliers
-- top fabric mult
ret.a_top := x_width;
ret.b_top := full_width_b - y_width;
ret.a_type_top := a_type;
ret.b_type_top := C_UNSIGNED;
ret.out_width_top := ret.a_top + ret.b_top;
-- side fabric mult
ret.a_side := full_width_a - x_width;
ret.b_side := full_width_b;
ret.a_type_side := C_UNSIGNED;
ret.b_type_side := b_type;
ret.out_width_side := ret.a_side + ret.b_side;
-- bypass vectors
ret.mult_bypass := ret.a_side;
ret.add_bypass := ret.b_top;
-- offsets for the block mult array inputs
ret.a_offset := ret.a_side;
ret.b_offset := ret.b_top;
print_debug := true;
elsif (full_width_b >= x_width and full_width_a >= y_width) and hybrid_cfg = TWO_MULT then
-- top fabric mult
ret.a_top := y_width;
ret.b_top := full_width_b - x_width;
ret.a_type_top := a_type;
ret.b_type_top := C_UNSIGNED;
ret.out_width_top := ret.a_top + ret.b_top;
-- side fabric mult
ret.a_side := full_width_a - y_width;
ret.b_side := full_width_b;
ret.a_type_side := C_UNSIGNED;
ret.b_type_side := b_type;
ret.out_width_side := ret.a_side + ret.b_side;
-- bypass vectors
ret.mult_bypass := ret.a_side;
ret.add_bypass := ret.b_top;
-- offsets for the block mult array inputs
ret.a_offset := ret.a_side;
ret.b_offset := ret.b_top;
print_debug := true;
end if;
assert not(debug) report CR & "two_mult_cfg is: " &
CR & "a_top: " & integer'image(ret.a_top) &
CR & "b_top: " & integer'image(ret.b_top) &
CR & "a_type_top: " & integer'image(ret.a_type_top) &
CR & "b_type_top: " & integer'image(ret.b_type_top) &
CR & "out_width_top: " & integer'image(ret.out_width_top) &
CR & "a_side: " & integer'image(ret.a_side) &
CR & "b_side: " & integer'image(ret.b_side) &
CR & "a_type_side: " & integer'image(ret.a_type_side) &
CR & "b_type_side: " & integer'image(ret.b_type_side) &
CR & "out_width_side: " & integer'image(ret.out_width_side) &
CR & "mult_bypass: " & integer'image(ret.mult_bypass) &
CR & "add_bypass: " & integer'image(ret.add_bypass) &
CR & "a_offset: " & integer'image(ret.a_offset) &
CR & "b_offset: " & integer'image(ret.b_offset) & CR severity note;
return ret;
end function get_two_mult_cfg;
-- purpose: works out the fully-pipelined latency of a LUT multiplier
function fab_mult_full_pipe_lat(a_width, b_width : integer) return integer is
variable b : integer := 0;
begin -- FUNCTION fab_mult_full_pipe_lat
b := get_min(a_width, b_width);
if b = 1 then
-- Need to trap this, otherwise a 35x1 multiplier would have a
-- fully-pipelined latency of zero!
return 1;
else
return mult_gen_log2(b);
end if;
end function fab_mult_full_pipe_lat;
-- purpose: works out how many pipeline stages a particular configuration of DSP blocks needs
function get_emb_mult_max_pipe_stages (family : string; a_pp, b_pp : integer) return integer is
variable ret : integer := 0;
begin -- FUNCTION get_DSP_max_pipe_stages
if supports_dsp48(family) = 1 or supports_dsp48e(family) > 0 then
if a_pp = 1 and b_pp = 1 then
ret := 3;
elsif a_pp = 2 and b_pp = 1 then
ret := 4;
elsif a_pp = 1 and b_pp = 2 then
ret := 4;
elsif a_pp = 2 and b_pp = 2 then
ret := 6;
else
ret := 99; -- unsupported configuration
report "ERROR: caught unsupported hybrid configuration in get_DSP_max_pipe_stages in mult_pkg"
severity failure;
end if;
elsif supports_dsp48a(family) > 0 then
-- There's no simple formula to work out what the latency will
-- be based on the number of DSPs. It depends how many wireshifts we need in
-- the fabric (i.e. how many times the C port needs to be used)
if a_pp = 1 and b_pp = 1 then
ret := 3;
elsif a_pp = 2 and b_pp = 1 then
ret := 5;
elsif a_pp = 2 and b_pp = 2 then
ret := 8;
else
ret := 99; -- unsupported configuration
report "ERROR: caught unsupported hybrid configuration in get_DSP_max_pipe_stages in mult_pkg"
severity failure;
end if;
elsif supports_mult18x18s(family) = 1 or supports_mult18x18sio(family) = 1 then
-- number of pipeline stages dictated by number of partial products
-- which determines the depth of the adder tree + registers in and
-- after the multiplier block
ret := mult_gen_log2(a_pp * b_pp) + 2;
if supports_mult18x18sio(family) = 1 then
-- add another register for after the multiplier blocks
ret := ret + 1;
end if;
else
report "ERROR: caught invalid family in get_emb_mult_max_pipe_stages"
severity failure;
end if;
return ret;
end function get_emb_mult_max_pipe_stages;
-- purpose: works out the depth of the adder tree on the LUT multiplier(s)
-- to see what the maximum fully-pipelined latency will be
function get_LUT_max_pipe_stages (one_mult_cfg : ONE_MULT_REC; two_mult_cfg : TWO_MULT_REC; hybrid_configuration : integer) return integer is
variable true_b_width_side : integer := 0;
variable true_b_width_top : integer := 0;
variable ret : integer := 0;
begin -- FUNCTION get_LUT_max_pipe_stages
if hybrid_configuration = 0 then
ret := 0;
elsif hybrid_configuration = 1 then
-- only one fabric multiplier - use one_mult_cfg
ret := fab_mult_full_pipe_lat(one_mult_cfg.a, one_mult_cfg.b);
elsif hybrid_configuration = 2 then
-- two fabric multipliers - work out which is the largest aka deepest
true_b_width_top := get_min(two_mult_cfg.a_top, two_mult_cfg.b_top);
true_b_width_side := get_min(two_mult_cfg.a_side, two_mult_cfg.b_side);
if true_b_width_top > true_b_width_side then
ret := mult_gen_log2(true_b_width_top);
else
ret := mult_gen_log2(true_b_width_side);
end if;
else
report "ERROR: invalid hybrid configuration value caught in get_LUT_max_pipe_stages in mult_pkg"
severity failure;
ret := 99;
end if;
return ret;
end function get_LUT_max_pipe_stages;
-- purpose: counts the number of LSB zeros in the supplied constant STRING
-- If the bits are zero, we don't need to pass these bits into the multiplier
-- and we can just right-shift the output by these number of bits
function get_output_scaling (b_value : string; b_type : integer; mult_type : integer)return integer is
variable shift : integer := 0;
variable can_trim : boolean := true;
variable all_ones : string(1 to b_value'length-1);
begin -- FUNCTION get_output_scaling
-- VTFC doesn't support (others => '1') assignment to a string
-- so we have to initialise the variable this way instead
for i in 1 to all_ones'length loop
all_ones(i) := '1';
end loop; -- i
if mult_type = FIXED_CCM then
-- first check if the constant is a negative power of 2
-- if it is, we can't trim the LS zeros
-- Assume that the input string will always be (1 to N) ranged
-- for support by VTFC
if b_value(b_value'high) = '0' and b_value(b_value'low to b_value'high-1) = all_ones then
can_trim := false;
end if;
if can_trim then
-- start at the LSB and work our way left gaining bit significance
for i in b_value'high downto b_value'low loop
if b_value(i) = '1' then
exit;
else
shift := shift + 1;
end if;
end loop; -- i
end if;
-- OLD CODE - COVERS ALL POSSIBLE STRING ORIENTATIONS
-- if b_value'ascending then
-- if b_value(b_value'right) = '0' and b_value(b_value'left to b_value'right-1) = all_ones then
-- can_trim := false;
-- end if;
-- else
-- if b_value(b_value'right) = '0' and b_value(b_value'left downto b_value'right+1) = all_ones then
-- can_trim := false;
-- end if;
-- end if;
-- if can_trim then
-- -- start at the LSB and work our way left gaining bit significance
-- -- Account for the strings being TO or DOWNTO
-- if b_value'ascending then
-- for i in b_value'right downto b_value'left loop
-- if b_value(i) = '1' then
-- exit;
-- else
-- shift := shift + 1;
-- end if;
-- end loop; -- i
-- else -- b_value'descending
-- for i in b_value'right to b_value'left loop
-- if b_value(i) = '1' then
-- exit;
-- else
-- shift := shift + 1;
-- end if;
-- end loop; -- i
-- end if;
-- end if;
assert not(debug) report "shift value is " & integer'image(shift) severity note;
end if;
return shift;
end function get_output_scaling;
-- purpose: checks to see if the constant has any zeros at the MSB (left) side of the string and
-- returns an integer to say how many consecutive zeros there are
-- These zeros don't need to go through the multiplier, so we could save some
-- logic in a few cases
-- If the constant is of signed type, we need to keep one of the leading zeros
-- If the constant is signed though, we can also check for leading ones and
-- trim them, stopping when we find "10" when searching from the left-hand side
function get_trimmed_leading_bits (b_value : string; b_type : integer; mult_type : integer) return integer is
variable zeros_to_trim : integer := 0;
variable ones_to_trim : integer := 0;
variable bits_to_trim : integer := 0;
begin -- FUNCTION get_trimmed_leading_bits
-- To make this function compatible with VTFC (for the GUI), we need to do
-- away with the 'ascending, 'left, 'right attributes and use only 'length,
-- 'low and 'high. This is based on the assumption that only strings with
-- (1 to N) ranges will be passed into this function
if mult_type = FIXED_CCM then
for i in b_value'low to b_value'high loop
if b_value(i) = '1' then
exit;
else
zeros_to_trim := zeros_to_trim + 1;
end if;
end loop; -- i
-- New loop for V10.0 that avoids the array indexing error for -1
if b_type = C_SIGNED and zeros_to_trim = 0 then
for i in b_value'low to b_value'high loop
if b_value(i) = '1' then
if i+1 <= b_value'high then
if b_value(i+1) = '0' then
exit;
end if;
else
null;
end if;
else
ones_to_trim := ones_to_trim + 1;
end if;
end loop; -- i
end if;
-- OLD CODE - COVERS THE ASCENDING AND DESCENDING STRING CASES
-- BUT DOESN'T SUPPORT VTFC
-- if mult_type = FIXED_CCM then
-- -- Account for the strings being TO or DOWNTO
-- if b_value'ascending then
-- for i in b_value'left to b_value'right loop
-- if b_value(i) = '1' then
-- exit;
-- else
-- zeros_to_trim := zeros_to_trim + 1;
-- end if;
-- end loop; -- i
-- else -- b_value'descending
-- for i in b_value'left downto b_value'right loop
-- if b_value(i) = '1' then
-- exit;
-- else
-- zeros_to_trim := zeros_to_trim + 1;
-- end if;
-- end loop; -- i
-- end if;
-- -- New loop for V10.0 that avoids the array indexing error for -1
-- if b_type = C_SIGNED and zeros_to_trim = 0 then
-- -- Account for the strings being TO or DOWNTO
-- if b_value'ascending then
-- for i in b_value'left to b_value'right loop
-- if b_value(i) = '1' then
-- if i+1 <= b_value'right then
-- if b_value(i+1) = '0' then
-- exit;
-- end if;
-- else
-- null;
-- end if;
-- else
-- ones_to_trim := ones_to_trim + 1;
-- end if;
-- end loop; -- i
-- else -- b_value'descending
-- for i in b_value'left downto b_value'right loop
-- if b_value(i) = '1' then
-- if i-1 >= b_value'right then
-- if b_value(i-1) = '0' then
-- exit;
-- end if;
-- else
-- null;
-- end if;
-- else
-- ones_to_trim := ones_to_trim + 1;
-- end if;
-- end loop; -- i
-- end if;
-- end if;
-- need to keep the MSB zero in the signed case to allow for correct
-- operand extension in the subcores
if b_type = C_SIGNED and zeros_to_trim > 0 then
zeros_to_trim := zeros_to_trim - 1;
end if;
bits_to_trim := ones_to_trim + zeros_to_trim; -- only one of these will be non-zero
assert not(debug) report "trimming " & integer'image(bits_to_trim) & " leading ones or zeros" severity note;
end if;
return bits_to_trim;
end function get_trimmed_leading_bits;
-- purpose: checks if the constant is all-zeros, in which case there is no point in creating logic!
function check_b_value_all_zeros (b_value : string; b_value_length : integer) return boolean is
variable ret : boolean := false;
begin -- FUNCTION check_b_value_all_zeros
for i in 1 to b_value_length loop
if b_value(i) = '1' then
ret := false;
exit;
end if;
ret := true;
end loop; -- i
assert ret = false report "b_value constant is exactly zero - no logic will be created" severity warning;
return ret;
end function check_b_value_all_zeros;
function check_const_power_of_two (b_value : string; b_type, mult_type : integer) return boolean is
variable trimmed_msbs : integer := get_trimmed_leading_bits(b_value, b_type, mult_type);
variable trimmed_lsbs : integer := calc_shift_bits(b_value, boolean'pos(mult_type = FIXED_CCM));
variable ret : boolean := false;
begin
-- Assume that the input string has a range of (1 to N) for VTFC support
if b_value(b_value'low) = '1' and b_type = C_SIGNED then
-- signed constant - can't represent by shifting alone
ret := false;
else
ret := (b_value'length - (trimmed_lsbs + trimmed_msbs) = 1);
end if;
-- OLD CODE - COVERS ALL POSSIBLE STRINGS
-- if b_value'ascending then
-- if b_value(b_value'low) = '1' and b_type = C_SIGNED then
-- -- signed constant - can't represent by shifting alone
-- ret := false;
-- else
-- ret := (b_value'length - (trimmed_lsbs + trimmed_msbs) = 1);
-- end if;
-- else -- b_value'descending
-- if b_value(b_value'high) = '1' and b_type = C_SIGNED then
-- -- signed constant - can't represent by shifting alone
-- ret := false;
-- else
-- ret := (b_value'length - (trimmed_lsbs + trimmed_msbs) = 1);
-- end if;
-- end if;
return ret;
end function check_const_power_of_two;
-------------------------------------------------------------------------------
-- Functions imported from ccm_pkg.vhd
-------------------------------------------------------------------------------
function calc_reqd_b_value(b_value : string;
b_width : integer;
b_type : integer;
reqd_b_width : integer) return string is
constant b_lsb : integer := b_value'high;
variable b_bit : integer;
variable reqd_b_value : string(1 to reqd_b_width);
begin
for bit in 1 to reqd_b_width loop
b_bit := bit + b_lsb - reqd_b_width;
if b_bit > 0 then
reqd_b_value(bit) := b_value(b_bit);
else
if b_type = C_SIGNED then
reqd_b_value(bit) := b_value(1);
else
reqd_b_value(bit) := '0';
end if; -- b_type
end if; -- b_bit
end loop;
assert not(ccm_debug) report "calc_reqd_b_value returning " & reqd_b_value severity note;
return reqd_b_value;
end calc_reqd_b_value;
function bitstorep_string(a_value : string;
a_type : integer) return integer is
variable return_value : integer;
begin
return_value := a_value'length;
if a_type = C_UNSIGNED then
-- a_value represents an unsigned number
-- FOR i IN a_value'RANGE LOOP -- Doesn't work with XCC
for i in a_value'low to a_value'high loop
if a_value(i) = '1' then
exit; -- EXIT when the msb is found
elsif a_value(i) = '0' then
return_value := return_value - 1;
else
null;
end if;
end loop;
else
-- a_value represents a signed number
-- Look for ms '1' followed by a '0'
-- FOR i IN a_value'RANGE LOOP -- Doesn't work with XCC
for i in a_value'low to a_value'high loop
if a_value(i) = '1' then
if i < a_value'high then
if a_value(i+1) = '0' then
exit; -- EXIT when the msb is found
else
return_value := return_value - 1;
end if;
else
exit; -- EXIT when end of STRING reached
end if;
elsif a_value(i) = '0' then
return_value := return_value - 1;
else
null;
end if;
end loop;
end if;
if return_value <= 0 then
return 1;
else
return return_value;
end if;
end bitstorep_string;
function calc_shift_bits(b_value : string;
b_constant : integer) return integer is
variable bit : integer;
variable shift_bits : integer;
begin
shift_bits := 0;
assert not(ccm_debug) report "calc_shift_bits params: " & b_value & " " & integer'image(b_constant) severity note;
if b_constant /= 0 then
bit := b_value'high;
while (bit >= b_value'low) loop
if b_value(bit) = '0' then
shift_bits := shift_bits + 1;
else
exit;
end if;
bit := bit - 1;
end loop;
end if;
if shift_bits >= b_value'high then
shift_bits := 0; -- All zeroes value
end if;
assert not(ccm_debug) report "calc_shift_bits returning " & integer'image(shift_bits) severity note;
return shift_bits;
end calc_shift_bits;
function get_rom_addr_width(family : string; mem_type : integer) return integer is
begin
if mem_type = C_DISTRIBUTED then
if supports_lut6(family) = 1 then
assert not(debug) report "distributed ram address width is 6 - 64x1 RAM (LUT6)" severity note;
return 6;
else
assert not(debug) report "distributed ram address width is 4 - 16x1 RAM (LUT4)" severity note;
return 4;
end if;
else
-- use a 9-bit address width
-- use the 18K BRAM for V5 as well
return 9;
end if;
end get_rom_addr_width;
function calc_a_input_width(operand_width, has_a_signed, rom_addr_width, b_constant : integer) return integer is
variable effective_op_width : integer;
begin
if has_a_signed = 0 or b_constant = 0 then
effective_op_width := operand_width;
else
-- Allow extra input for 'a_signed'
effective_op_width := operand_width + 1;
end if;
if (effective_op_width mod rom_addr_width = 0) then
return effective_op_width;
else
return effective_op_width + rom_addr_width - (effective_op_width mod rom_addr_width);
end if;
end calc_a_input_width;
function calc_num_pps(a_width, rom_addr_width : integer) return integer is
begin
if (a_width mod rom_addr_width /= 0) then
return (a_width / rom_addr_width) + 1;
else
return (a_width / rom_addr_width);
end if;
end calc_num_pps;
------------------------------------------------------------------------------
-- Returns the number of input bits required by the last partial product ROM.
-- Does not include a_signed bit.
------------------------------------------------------------------------------
function calc_last_pp_input_width(operand_width, has_a_signed,
rom_addr_width, b_constant : integer) return integer is
begin
if (operand_width mod rom_addr_width /= 0) then
return operand_width mod rom_addr_width;
else
-- There is an extra pp in this case due to the msb and 'a_signed' having
-- to have a separate LUT
if has_a_signed /= 0 and b_constant /= 0 then
return 1;
else
return rom_addr_width;
end if;
end if;
end calc_last_pp_input_width;
------------------------------------------------------------------------------
-- Calculate amount to delay signal which drives addsub add input.
------------------------------------------------------------------------------
function calc_add_lastpp_delay(reg_a_b_inputs : integer;
pipeline : integer;
num_pipe_stages : integer) return integer is
variable delay : integer;
begin
if reg_a_b_inputs = 0 then
delay := 0;
else
delay := 1;
end if;
if pipeline /= 0 then
delay := num_pipe_stages + 1; -- Add 1 for RAM output register
end if;
return delay;
end calc_add_lastpp_delay;
------------------------------------------------------------------------------
-- Only the product bits from 'start_bit' upwards are stored in the ROMs
-- because the bits below 'start_bit' are one of the address bits.
--
-- e.g. ROM output(0) = I0 if b(0)='1'
-- ROM output(1) = I1 if b(1:0)='01'
-- ROM output(2) = I2 if b(2:0)='001'
-- .. ..
-- ROM output(n) = In if b(n:0)='0...01'
------------------------------------------------------------------------------
function calc_rom_start_bit(b_width : integer;
b_value : string;
b_constant : integer;
pp_width : integer;
a_type : integer;
rom_has_a_signed : integer;
mem_type : integer;
mem_addr_width : integer;
pipeline : integer;
num_adders : integer;
has_q : integer;
last_mem : boolean) return integer is
variable b_bit : integer;
variable start_bit : integer;
begin
start_bit := 0;
b_bit := b_value'high; -- STRINGs go from 1 to N (lsb = N)
if b_bit > 1 and b_constant /= 0 and mem_type = C_DISTRIBUTED and rom_has_a_signed = 0
and ((num_adders > 0 and pipeline = 0) or (num_adders = 0 and has_q = 0)) then
if b_value(b_bit) = '1' then
start_bit := 1;
while start_bit < pp_width loop
-- Increment start_bit if 1st bit = '1' and next ms bit = '0'
if b_bit > b_value'low then
b_bit := b_bit - 1;
if b_value(b_bit) = '0' then
start_bit := start_bit + 1;
else
exit;
end if;
else
start_bit := start_bit + 1;
end if; -- b_bit > b_value'LOW
end loop; -- WHILE ...
end if; -- b_value(b_value'HIGH) = '1'
end if; -- b_constant /= 0
-- Do not allow start_bit to exceed mem_addr_width if last mem and
-- a is signed
if last_mem and a_type = C_SIGNED and start_bit > mem_addr_width then
start_bit := mem_addr_width;
end if;
return start_bit;
end calc_rom_start_bit;
-- andreww restructured calc_rom_contents to work better with XST
-- previously the call the multiply_bv was made within the nested FOR loops,
-- which could result in extra memory overhead. Moving this outside to an independent
-- FOR loop and assembling a constant array is much easier on XST
-- 16 November 2005
function calc_rom_contents(b_width : integer;
b_type : integer;
rom_addr_width : integer;
rom_depth : integer;
rom_width : integer;
start_bit : integer;
b_value : string;
num_rom_bits : integer) return bit_vector is
variable b_value_bv : bit_vector(b_width-1 downto 0);
variable prod : bit_vector(rom_addr_width+b_width-1 downto 0);
variable rom_contents : bit_vector(num_rom_bits-1 downto 0);
-- new things
type T_PROD is array (0 to rom_depth-1) of bit_vector(rom_addr_width+b_width-1 downto 0);
variable prod_array : T_PROD;
variable prod_el : bit_vector(rom_addr_width+b_width-1 downto 0);
begin
b_value_bv := mult_gen_str_to_bv(b_value, b_width);
for rom_addr in 0 to rom_depth-1 loop
prod_array(rom_addr) := multiply_bv(natural_to_bit_vector(rom_addr, rom_addr_width), b_value_bv, false, (b_type = C_SIGNED));
end loop; -- rom_addr
for rom_addr in 0 to rom_depth-1 loop
-- Multiply rom_addr by c_b_value
-- get the bit vector out of the array
prod_el := prod_array(rom_addr);
rom_contents((rom_addr*rom_width + rom_width-1) downto (rom_addr*rom_width + 0)) := prod_el((rom_width-1 + start_bit) downto (0 + start_bit));
end loop;
return rom_contents;
end calc_rom_contents;
------------------------------------------------------------------------------
--
-- Last ROM contents differ because 'a' may not occupy the full address bus
-- and the MSB of 'a' may be a sign bit.
--
-- c_has_a_signed=0 (a=3 bits) c_has_a_signed/=0 (a=2 bits)
-- Location Contents Location Contents
-- 0 0 * B 0 0 * B
-- 1 1 * B 1 1 * B
-- 2 2 * B 2 2 * B
-- 3 3 * B 3 3 * B
-- 4 4 * B <-- 2**(a_width-1) 4 0 * B <-- 2**(a_width-1)
-- 5 3 * B 5 -1 * B
-- 6 2 * B 6 -2 * B
-- 7 1 * B 7 -1 * B
-- 8 Don't care 8 Don't care
-- etc etc
--
-- If b is not constant then last ROM is just the same as all the others.
------------------------------------------------------------------------------
function calc_last_rom_contents(b_width : integer;
a_width : integer; -- not incl a_signed
a_type : integer;
b_type : integer;
has_a_signed : integer;
rom_addr_width : integer;
rom_depth : integer;
rom_width : integer;
start_bit : integer;
b_value : string;
b_constant : integer;
num_rom_bits : integer;
number_of_pps : integer;
a_signed_extension : boolean) return bit_vector is
constant a_signed : boolean := ((a_type = C_SIGNED) or (has_a_signed /= 0));
constant max_val : integer := 2**(a_width-1);
constant prod_width : integer := a_width + b_width;
variable b_value_bv : bit_vector(b_width-1 downto 0);
variable prod : bit_vector(prod_width-1 downto 0);
variable rom_contents : bit_vector(num_rom_bits-1 downto 0);
variable debug_string : string(1 to prod_width);
begin
if (has_a_signed = 0 and a_type = C_UNSIGNED) or (b_constant = 0) then
return calc_rom_contents(b_width, b_type, a_width, rom_depth, rom_width, start_bit, b_value, num_rom_bits);
else
b_value_bv := mult_gen_str_to_bv(b_value, b_width);
for rom_addr in 0 to rom_depth-1 loop
-- Multiply rom_addr by c_b_value
prod := multiply_bv(natural_to_bit_vector(rom_addr, a_width), b_value_bv, a_signed, (b_type = C_SIGNED));
rom_contents((rom_addr*rom_width + rom_width-1) downto (rom_addr*rom_width + 0)) := prod((rom_width-1 + start_bit) downto (0 + start_bit));
end loop;
return rom_contents;
end if;
end calc_last_rom_contents;
------------------------------------------------------------------------------
-- Return adder level within the symmetric tree for a given adder number.
-- Adder numbers start from 0. Level 1 is the level nearest the pprods.
------------------------------------------------------------------------------
function calc_adder_level(adder_num, max_add_levels : integer) return integer is
type num_al_type is array(1 to max_add_levels) of integer;
variable add_level : integer;
variable num_al : num_al_type;
begin
for i in 1 to max_add_levels loop
num_al(i) := 0;
end loop;
add_level := 1;
for i in 0 to (adder_num-1) loop
num_al(add_level) := num_al(add_level) + 1;
if (num_al(add_level) = 2) then
num_al(add_level) := 0;
add_level := add_level + 1;
else
add_level := 1;
end if;
end loop;
return add_level;
end calc_adder_level;
------------------------------------------------------------------------------
-- Return the adder number of the adder whose b input is the last partial
-- product. Adders are numbered 0 to n.
------------------------------------------------------------------------------
function calc_last_pp_adder(num_pps : integer;
max_add_levels : integer;
num_adders : integer;
num_extra_adders : integer) return integer is
variable add_num : integer;
begin
if num_extra_adders > 0 and (num_pps mod 2 /= 0) then
-- First extra adder is the last pp adder
return num_adders-num_extra_adders;
else
add_num := 0;
for p in 0 to num_pps-2 loop
for l in 1 to max_add_levels loop
if ((p+1) mod 2**l = 0) then
add_num := add_num + 1;
end if;
end loop; -- l
end loop; -- p
return add_num;
end if; -- num_extra_adders > 0 ...
end calc_last_pp_adder;
------------------------------------------------------------------------------
--
-- Calculate number of extra add stages to place at the right.
-- Input parameter is total number of partial products.
--
-- Algorithm is (for max_num_pps = 8 example)
-- add_count := 0
-- pps=8? Yes --> Done
-- pps>8? Yes --> Subtract 8, increment add_count, (pps=4?) Yes --> Done
-- pps>4? Yes --> Subtract 4, increment add_count, (pps=2?) Yes --> Done
-- pps>2? Yes --> Subtract 2, increment add_count, Done
-- Done
------------------------------------------------------------------------------
function calc_num_extra_adders(num_pps, max_num_pps : integer)
return integer is
variable adder_count : integer;
variable pps_group : integer;
variable pps_remaining : integer;
begin
pps_remaining := num_pps;
pps_group := max_num_pps;
adder_count := 0;
while ((pps_group > 1) and (pps_group /= pps_remaining)) loop
if (pps_remaining > pps_group) then
adder_count := adder_count + 1;
pps_remaining := pps_remaining - pps_group;
end if;
pps_group := pps_group / 2;
end loop;
return adder_count;
end calc_num_extra_adders;
------------------------------------------------------------------------------
-- Return width of partial or full product
-- Set full_prod to TRUE if width of total final product is to be returned.
------------------------------------------------------------------------------
function calc_pp_width(b_width : integer;
b_type : integer;
b_value : string;
b_constant : integer;
a_width : integer;
a_type : integer;
has_a_signed : integer;
last_pp : boolean;
full_prod : boolean) return integer is
variable a_all_1s : bit_vector(a_width-1 downto 0);
variable b_all_1s : bit_vector(b_width-1 downto 0);
-- a_type is always unsigned for partial products if b is not constant
constant act_a_type : integer :=
select_val(a_type, C_UNSIGNED, b_constant = 0 and not(full_prod));
constant act_a_sgnd : integer :=
select_val(has_a_signed, 0, b_constant = 0 and not(full_prod));
variable min_a : bit_vector(a_width-1 downto 0);
variable a_value_bv : bit_vector(a_width-1 downto 0);
variable b_value_bv : bit_vector(b_width-1 downto 0);
variable pp_width : integer;
variable pp_width_a_negative : integer;
begin
assert not(ccm_debug) report "calc_pp_width args "
& integer'image(b_width)
& " " & integer'image(b_type)
& " " & b_value
& " " & integer'image(b_constant)
& " " & integer'image(a_width)
& " " & integer'image(a_type)
& " " & integer'image(has_a_signed)
& " " & boolean'image(last_pp)
& " " & boolean'image(full_prod) severity note;
-- Workaround for VTFC not handling bit_vector type correctly
for i in a_width-1 downto 0 loop
a_all_1s(i) := '1';
end loop; -- i
for i in b_width-1 downto 0 loop
b_all_1s(i) := '1';
end loop; -- i
assert not(ccm_debug) report "0: pp_width is " & integer'image(pp_width) severity note;
if b_width = 1 and b_type = C_UNSIGNED then
if b_value(b_value'high) = '0' and b_constant /= 0 then
pp_width := 1; -- Special case for multiplying by 0
else
pp_width := a_width;
-- a_signed is not part of pp input if b_constant/=0
if last_pp and act_a_sgnd /= 0 then
pp_width := pp_width + 1;
end if;
end if; -- b_value
else
-- Return minimum number of bits to represent maximum possible pp value
if b_constant = 0 then
if b_type = C_UNSIGNED then
-- Must assume max possible B value
b_value_bv := b_all_1s;
else
if b_width > 1 then
-- Use loop assignment for VTFC support
for i in b_width-2 downto 0 loop
b_value_bv(i) := '0';
end loop; -- i
end if;
b_value_bv(b_width-1) := '1';
end if; -- b_type = C_UNSIGNED
else
b_value_bv := mult_gen_str_to_bv(b_value, b_width);
end if;
-- A input always treated as unsigned except for last pp
if not(last_pp) or act_a_type = C_UNSIGNED then
if a_width = 1 and b_value_bv = b_all_1s and b_type /= C_UNSIGNED and b_constant /= 0 then
pp_width := 1; -- -1 * (0 or 1) only needs 1 bit
else
pp_width := bitstorep_bv(multiply_bv(a_all_1s, b_value_bv, false, (b_type = C_SIGNED)), b_type, (b_type /= C_SIGNED));
end if; -- a_width = 1 AND ...
-- a_signed input has effect on last PP
elsif act_a_sgnd /= 0 then -- 1 is added later
pp_width := bitstorep_bv(multiply_bv(a_all_1s, b_value_bv, false, (b_type = C_SIGNED)), b_type, (b_type /= C_SIGNED));
-- Add 1 to last pp width if extra bit has to be added due to
-- c_has_a_signed as above result always +ve if b_type unsigned
if b_type = C_UNSIGNED then
pp_width := pp_width + 1;
else
-- Get minimum possible A value
if a_width > 1 then
-- Use loop assignment for VTFC support
for i in a_width-1 downto 0 loop
a_value_bv(i) := '0';
end loop; -- i
end if;
a_value_bv(a_width-1) := '1';
-- Min A * Min B to get max +ve output
pp_width_a_negative := bitstorep_bv(multiply_bv(a_value_bv, b_value_bv, true, true), C_UNSIGNED, true); -- -ve (A) * -ve (B) = +ve
if pp_width_a_negative >= pp_width then
pp_width := pp_width + 1;
end if;
end if;
else -- last_pp and a_type=C_SIGNED and c_has_a_signed=0
if a_width = 1 then -- Worst case = -1
pp_width := bitstorep_bv(multiply_bv("11", b_value_bv, true, (b_type = C_SIGNED)), C_SIGNED, (b_type = C_SIGNED));
else
-- Lowest possible A value
-- Use loop assignment for VTFC support
for i in a_width-1 downto 0 loop
min_a(i) := '0';
end loop; -- i
min_a(a_width-1) := '1';
-- Determine type of widest possible PP
-- -ve * -ve = +ve, -ve * +ve = -ve
pp_width := bitstorep_bv(multiply_bv(min_a, b_value_bv, true, (b_type = C_SIGNED)), C_SIGNED, (b_type = C_SIGNED));
end if;
end if; -- NOT(last_pp) OR ...
end if;
assert not(ccm_debug) report "INFO: pp_width calculated as " & integer'image(pp_width) severity note;
return pp_width;
end calc_pp_width;
------------------------------------------------------------------------------
-- Sometimes specified c_mem_type parameter is illegal. Check and change to a
-- legal value if necessary.
------------------------------------------------------------------------------
function get_mem_type(family : string;
mem_type : integer;
bram_addr_width : integer;
has_swapb : integer;
a_width : integer;
a_type : integer;
has_a_signed : integer;
b_constant : integer;
has_o : integer) return integer is
constant rom_addr_width : integer := get_rom_addr_width(family, mem_type);
constant a_input_width : integer := calc_a_input_width(a_width, has_a_signed, rom_addr_width, b_constant);
constant number_of_pps : integer := calc_num_pps(a_input_width, rom_addr_width);
constant need_addsub : boolean := b_constant = 0 and (a_type /= C_UNSIGNED or has_a_signed /= 0);
-- Single PP but need an addsub to negate result
constant need_0_minus_pp : boolean := need_addsub and number_of_pps <= 1;
constant number_of_adders : integer := select_val(number_of_pps-1, 1, need_0_minus_pp);
variable mem_type_i : integer;
begin
if mem_type /= C_DISTRIBUTED and has_swapb = 0 and has_o /= 0 and number_of_adders < 1 then
mem_type_i := C_DISTRIBUTED;
report "ERROR: CCM - the O output is not available with block memory " &
"and this parameter combination." & new_line &
" Select distributed memory if the O " &
"output is required in this case." & new_line
severity failure;
else
mem_type_i := mem_type;
end if;
return mem_type_i;
end get_mem_type;
-----------------------------------------------------------------------------
-- FUNCTIONS FROM CCM_UTILS_V9_0
-----------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Return number of bits required to represent the supplied parameter
--------------------------------------------------------------------------------
function bitsneededtorepresent(a_value : integer) return integer is--(a_value : natural) return natural is
variable return_value : integer := 1;
begin
for i in 30 downto 0 loop
if a_value >= 2**i then
return_value := i+1;
exit;
end if;
end loop;
return return_value;
end bitsneededtorepresent;
-------------------------------------------------------------------------------
-- bitstorep_bv updated by andreww 19th May 06 - Worked correctly with MTI 6.1e,
-- but not with XST I.31 - simplified code to ease debug
-- Assumes that the bit_vector a_value is a DOWNTO vector
-------------------------------------------------------------------------------
function bitstorep_bv(a_value : bit_vector;
a_type : integer;
a_positive : boolean) return integer is
variable str_rep : string(1 to a_value'length);
variable return_value : integer := a_value'length;
begin
-- assert not(ccm_debug) report "bitstorep_bv args " & slv_to_str(bv_to_slv(a_value)) & " " & integer'image(a_type) & " " & boolean'image(a_positive) severity note;
-- For VTFC support, we need to convert to a string before analysing the
-- vector. Only 'length, 'low and 'high are supported by VTFC at present.
-- Assumes that the bit_vector is DOWNTO and has LSB at index zero
for i in str_rep'low-1 to str_rep'high-1 loop
if a_value(i) = '1' then
str_rep(i+1) := '1';
elsif a_value(i) = '0' then
str_rep(i+1) := '0';
else
report "ERROR: mult_gen: non-binary value caught in bitstorep_bv"
severity failure;
end if;
end loop; -- i
if a_type = C_UNSIGNED then
-- str_rep represents an unsigned number
for i in str_rep'high downto str_rep'low loop
if str_rep(i) = '1' then
exit; -- EXIT when the msb is found
elsif str_rep(i) = '0' then
return_value := return_value - 1;
end if;
end loop;
else
-- str_rep represents a signed number
if a_positive then
-- Look for ms '1' then add 1 for a leading 0
for i in str_rep'high downto str_rep'low loop
if i-1 > 0 then
if str_rep(i) = '0' and str_rep(i-1) = '1' then
exit;
else
return_value := return_value - 1;
end if;
else
exit;
end if;
end loop; -- i
else
-- Look for ms '1' followed by a '0'
for i in str_rep'high downto str_rep'low loop
if i-1 > 0 then
if str_rep(i) = '1' and str_rep(i-1) = '0' then
exit;
else
return_value := return_value - 1;
end if;
else
exit;
end if;
end loop; -- i
end if; -- a_positive
end if;
if return_value <= 0 then
return 1;
elsif a_type /= c_unsigned and return_value <= 2 then
return 2; -- always need at least 2 bits to represent signed numbers
else
return return_value;
end if;
end bitstorep_bv;
--------------------------------------------------------------------------------
-- Convert STD_LOGIC_VECTOR to STRING
-- Assumes STRING is of type (n TO n+length-1) with MSB in 'n' position.
-- Returns STD_LOGIC_VECTOR of type (nbits-1 DOWNTO 0) with LSB in 0 position.
--------------------------------------------------------------------------------
function slv_to_str(bitsin : std_logic_vector; nbits : integer) return string is
variable ret : string(1 to nbits);
variable bit_num : integer;
begin
ret := (others => '0');
bit_num := 1;
for i in bitsin'range loop
if bitsin(i) = '1' then
ret(bit_num) := '1';
elsif bitsin(i) = '0' then
ret(bit_num) := '0';
elsif (bitsin(i) = 'L') then
ret(bit_num) := 'L';
elsif (bitsin(i) = 'H') then
ret(bit_num) := 'H';
elsif (bitsin(i) = 'Z') then
ret(bit_num) := 'Z';
elsif (bitsin(i) = 'W') then
ret(bit_num) := 'W';
elsif (bitsin(i) = 'U') then
ret(bit_num) := 'U';
elsif (bitsin(i) = 'X') then
ret(bit_num) := 'X';
elsif (bitsin(i) = '-') then
ret(bit_num) := '-';
else
report "ERROR: invalid character passed to slv_to_str function." &
new_line
severity failure;
end if;
bit_num := bit_num + 1;
if bit_num > nbits then
exit; -- Ignore ms bits in SLV if SLV is longer than STRING
end if;
end loop;
return ret;
end slv_to_str;
--------------------------------------------------------------------------------
-- Return i0 if sel = 0, i1 if sel = 1
--------------------------------------------------------------------------------
function mult_gen_max_of(i0, i1 : integer) return integer is
begin
if (i0 > i1) then
return i0;
else
return i1;
end if;
end mult_gen_max_of;
-------------------------------------------------------------------------------
-- function modified by andreww 13th May 06 - need to account for signed and
-- unsigned products
-------------------------------------------------------------------------------
use ieee.std_logic_signed.all;
function multiply_bv(a, b : bit_vector; a_signed, b_signed : boolean) return bit_vector is
constant a_slv : std_logic_vector(a'range) := to_stdlogicvector(a);
constant b_slv : std_logic_vector(b'range) := to_stdlogicvector(b);
variable ai : std_logic_vector(a'high+1 downto a'low);
variable bi : std_logic_vector(b'high+1 downto b'low);
variable prod : std_logic_vector(ai'length+bi'length-1 downto 0);
-- create an intermediate variable to assign the bit_vector into
-- if we don't do this and return directly from the to_bitvector function,
-- XST assumes that the returned bit_vector is (0 TO N-1) rather than the
-- (N-1 downto 0) that we require (and all other functions assume...)
variable prod_slv : std_logic_vector(a'length+b'length-1 downto 0);
variable prod_bv : bit_vector(a'length+b'length-1 downto 0);
begin
-- assert not(ccm_debug) report "multiply_bv args " & slv_to_str(bv_to_slv(a)) & " " & slv_to_str(bv_to_slv(b)) & " " & boolean'image(a_signed) & " " & boolean'image(b_signed) severity note;
-- -- Original code in v11.0 - this doesn't work with modelsim 6.4a/b (at least)
-- if a_signed then
-- ai := std_logic_vector(resize(signed(to_Stdlogicvector(a)), ai'length));
-- else
-- ai := std_logic_vector(resize(unsigned(to_Stdlogicvector(a)), ai'length));
-- end if;
-- if b_signed then
-- bi := std_logic_vector(resize(signed(to_Stdlogicvector(b)), bi'length));
-- else
-- bi := std_logic_vector(resize(unsigned(to_Stdlogicvector(b)), bi'length));
-- end if;
if a_signed then
ai := std_logic_vector(resize(signed(a_slv), ai'length));
else
ai := std_logic_vector(resize(unsigned(a_slv), ai'length));
end if;
if b_signed then
bi := std_logic_vector(resize(signed(b_slv), bi'length));
else
bi := std_logic_vector(resize(unsigned(b_slv), bi'length));
end if;
-- since we've manually sign- (or zero-) extended, we can perform a signed multiplication
prod := ieee.std_logic_signed."*"(ai, bi);
-- return only the necessary width - don't use the resize() function here as it can give the wrong results
prod_bv := to_bitvector(prod(a'length+b'length-1 downto 0)); -- this line doesn't work with VTFC - no arguments passed to to_bitvector
return prod_bv;
end multiply_bv;
--------------------------------------------------------------------------------
-- Convert NATURAL to BIT_VECTOR
-- The ls length bits of in_val are returned.
--------------------------------------------------------------------------------
function natural_to_bit_vector(in_val : in integer; length : in integer)
return bit_vector is
variable temp : integer := in_val;
variable result : bit_vector(length-1 downto 0) := (others => '0');
begin
result := to_bitvector(std_logic_vector(resize(to_unsigned(in_val, 32), length)));
return result;
end natural_to_bit_vector;
--------------------------------------------------------------------------------
-- Return i0 if sel = FALSE, i1 if sel = TRUE
--------------------------------------------------------------------------------
function mult_gen_select_string(i0 : string; i1 : string; sel : boolean)
return string is
begin
if sel then
return i1;
else
return i0;
end if; -- sel
end mult_gen_select_string;
--------------------------------------------------------------------------------
-- Return i0 if sel = FALSE, i1 if sel = TRUE
--------------------------------------------------------------------------------
function select_val(i0 : integer; i1 : integer; sel : boolean) return integer is
begin
if sel then
return i1;
else
return i0;
end if; -- sel
end select_val;
function select_val_int(i0 : integer; i1 : integer; sel : integer) return integer is
begin
if sel = 1 then
return i1;
else
return i0;
end if; -- sel
end select_val_int;
--------------------------------------------------------------------------------
-- Convert STRING to BIT_VECTOR
-- Assumes STRING is of type (n TO n+length-1) with MSB in 'n' position.
-- Returns BIT_VECTOR of type (nbits-1 DOWNTO 0) with LSB in 0 position.
--------------------------------------------------------------------------------
function mult_gen_str_to_bv(bitsin : string; nbits : integer) return bit_vector is
variable ret : bit_vector(nbits-1 downto 0);
variable bit_num : integer;
begin
ret := (others => '0');
if (bitsin'length = 0) then -- Make all '0's
return ret;
end if;
bit_num := 0;
-- FOR i IN bitsin'REVERSE_RANGE LOOP -- doesn't work with XCC
for i in bitsin'high downto bitsin'low loop
if bitsin(i) = '1' then
ret(bit_num) := '1';
elsif bitsin(i) = '0' then
ret(bit_num) := '0';
else
report "ERROR: non 0 or 1 character passed to mult_gen_str_to_bv function. String passed in was: " & bitsin
severity failure;
end if;
bit_num := bit_num + 1;
if bit_num >= nbits then
exit; -- Ignore ms characters in STRING if STRING is longer than BV
end if;
end loop;
return ret;
end mult_gen_str_to_bv;
function mult_gen_bv_to_str(bitsin : bit_vector; nbits : integer) return string is
variable ret : string(1 to bitsin'length);
variable bit_num : integer;
begin
ret := (others => '0');
if (bitsin'length = 0) then -- Make all '0's
return ret;
end if;
bit_num := 0;
for i in bitsin'high downto bitsin'low loop
if bitsin(i) = '1' then
ret(bit_num) := '1';
elsif bitsin(i) = '0' then
ret(bit_num) := '0';
else
report "ERROR: non 0 or 1 character passed to mult_gen_bv_to_str function"
severity failure;
end if;
bit_num := bit_num + 1;
if bit_num >= nbits then
exit; -- Ignore ms characters in bit_vector if bit_vector is longer than string
end if;
end loop;
return ret;
end mult_gen_bv_to_str;
-----------------------------------------------------------------------------
-- functions imported from ccm_mem_utils_v9.0.vhd
function calc_depth(reqd_depth : integer; mem_type : integer) return integer is
variable extra : integer := 0;
variable addr_width : integer := bitsneededtorepresent(reqd_depth-1);
begin
if mem_type = c_distributed then
extra := reqd_depth mod 2**addr_width; --16;
if (extra = 0) then
return reqd_depth;
else
return (reqd_depth + (2**addr_width) - extra); --16 - extra);
end if;
else
-- Must be block mem. Block mems must be 16, 32, 64, 128, 256 or n * 256 deep
if reqd_depth <= 16 then
return 16;
elsif reqd_depth <= 256 then
return 2**(bitsneededtorepresent(reqd_depth-1));
else
return 256 + (256 * ((reqd_depth-1)/256));
end if; -- reqd_depth
end if; -- mem_type
end calc_depth;
-----------------------------------------------------------------------------
-- Resource estimation functions to be converted by VTFC
-----------------------------------------------------------------------------
-- purpose: this routine works out the LUT count for the LUT multiplier in a
-- LUT4 binary adder structure and is accurate to +/- 1-% of characterisation data
function calc_lut_mult_resources (c_a_width, c_b_width : integer) return integer is
-- calculation variables
variable opa : integer := 0;
variable opb : integer := 0;
variable PPs : integer := 0;
variable carrychainlength : integer := 0;
variable treestages : integer := 0;
variable stage1adders, stage2adders, stage3adders, stage4adders, stage5adders : integer := 0;
-- the final return value
variable lutcount : integer := 0;
begin -- function calc_lut_mult_resources
opa := mult_gen_max_of(c_a_width, c_b_width);
opb := get_min(c_a_width, c_b_width);
assert not(debug) report " opa is " & integer'image(opa);
assert not(debug) report " opb is " & integer'image(opb);
-- work out how many PP generators there are
if (opb mod 2) /= 0 then
PPs := (opb+1)/2;
else
PPs := opb / 2;
end if;
carrychainlength := opa + 2;
-- Set the lut count for the PP generators to be rounded down if PPs is odd
-- - the LUTs will be sucked into the adder tree
if opb > 1 then
lutcount := (opb / 2) * carrychainlength;
else
lutcount := opa;
end if;
if (opb mod 2) /= 0 and PPs > 1 then
lutcount := lutcount + opb;
end if;
case PPs is
when 1 => treestages := 0;
when 2 => treestages := 1;
when 3 to 4 => treestages := 2;
when 5 to 8 => treestages := 3;
when 9 to 16 => treestages := 4;
when 17 to 32 => treestages := 5;
when others => null;
end case;
case PPs is
when 1 =>
stage1adders := 0;
stage2adders := 0;
stage3adders := 0;
stage4adders := 0;
stage5adders := 0;
when 2 =>
stage1adders := 1;
stage2adders := 0;
stage3adders := 0;
stage4adders := 0;
stage5adders := 0;
when 3 =>
stage1adders := 1;
stage2adders := 1;
stage3adders := 0;
stage4adders := 0;
stage5adders := 0;
when 4 =>
stage1adders := 2;
stage2adders := 1;
stage3adders := 0;
stage4adders := 0;
stage5adders := 0;
when 5 =>
stage1adders := 2;
stage2adders := 1;
stage3adders := 1;
stage4adders := 0;
stage5adders := 0;
when 6 =>
stage1adders := 3;
stage2adders := 1;
stage3adders := 1;
stage4adders := 0;
stage5adders := 0;
when 7 =>
stage1adders := 3;
stage2adders := 2;
stage3adders := 1;
stage4adders := 0;
stage5adders := 0;
when 8 =>
stage1adders := 4;
stage2adders := 2;
stage3adders := 1;
stage4adders := 0;
stage5adders := 0;
when 9 =>
stage1adders := 4;
stage2adders := 2;
stage3adders := 1;
stage4adders := 1;
stage5adders := 0;
when 10 =>
stage1adders := 5;
stage2adders := 2;
stage3adders := 1;
stage4adders := 1;
stage5adders := 0;
when 11 =>
stage1adders := 5;
stage2adders := 2;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 12 =>
stage1adders := 6;
stage2adders := 3;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 13 =>
stage1adders := 6;
stage2adders := 3;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 14 =>
stage1adders := 7;
stage2adders := 2;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 15 =>
stage1adders := 7;
stage2adders := 3;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 16 =>
stage1adders := 8;
stage2adders := 4;
stage3adders := 2;
stage4adders := 1;
stage5adders := 0;
when 17 =>
stage1adders := 8;
stage2adders := 4;
stage3adders := 2;
stage4adders := 1;
stage5adders := 1;
when 18 =>
stage1adders := 9;
stage2adders := 4;
stage3adders := 2;
stage4adders := 1;
stage5adders := 1;
when 19 =>
stage1adders := 9;
stage2adders := 5;
stage3adders := 2;
stage4adders := 1;
stage5adders := 1;
when 20 =>
stage1adders := 10;
stage2adders := 5;
stage3adders := 2;
stage4adders := 1;
stage5adders := 1;
when 21 =>
stage1adders := 10;
stage2adders := 5;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 22 =>
stage1adders := 11;
stage2adders := 6;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 23 =>
stage1adders := 11;
stage2adders := 6;
stage3adders := 3;
stage4adders := 2;
stage5adders := 1;
when 24 =>
stage1adders := 12;
stage2adders := 6;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 25 =>
stage1adders := 12;
stage2adders := 7;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 26 =>
stage1adders := 13;
stage2adders := 7;
stage3adders := 3;
stage4adders := 1;
stage5adders := 1;
when 27 =>
stage1adders := 13;
stage2adders := 7;
stage3adders := 3;
stage4adders := 2;
stage5adders := 1;
when 28 =>
stage1adders := 14;
stage2adders := 7;
stage3adders := 3;
stage4adders := 2;
stage5adders := 1;
when 29 =>
stage1adders := 14;
stage2adders := 7;
stage3adders := 4;
stage4adders := 2;
stage5adders := 1;
when 30 =>
stage1adders := 15;
stage2adders := 7;
stage3adders := 4;
stage4adders := 2;
stage5adders := 1;
when 31 =>
stage1adders := 15;
stage2adders := 8;
stage3adders := 4;
stage4adders := 2;
stage5adders := 1;
when 32 =>
stage1adders := 16;
stage2adders := 8;
stage3adders := 4;
stage4adders := 2;
stage5adders := 1;
when others => null;
end case;
lutcount := lutcount + (stage1adders * carrychainlength);
lutcount := lutcount + (stage2adders * (carrychainlength+2));
lutcount := lutcount + (stage3adders * (carrychainlength+2+4));
lutcount := lutcount + (stage4adders * (carrychainlength+2+4+8));
lutcount := lutcount + (stage5adders * (carrychainlength+2+4+8+16));
return lutcount;
end function calc_lut_mult_resources;
-- purpose: Calculates number of embedded multipliers used to build a
-- hybrid multiplier
function calc_hybrid_emb_mults (
family : string;
op_width : WIDTH_REC) return integer is
variable a_pp : integer := hybrid_calc_a_pp(family, op_width);
variable b_pp : integer := hybrid_calc_b_pp(family, op_width);
variable mults : integer := 0;
begin -- function calc_hybrid_emb_mults
mults := a_pp * b_pp;
return mults;
end function calc_hybrid_emb_mults;
-- purpose: calculates roughly how many LUTs are used in building a given
-- hybrid multiplier
function calc_hybrid_luts (
family : string;
op_width : WIDTH_REC) return integer is
-- calculation variables and constants
constant BASE_MULT : integer := 0;
constant ONE_MULT : integer := 1;
constant TWO_MULT : integer := 2;
constant wire_shift : integer := 17;
-- set up the port sizes for all families
constant port_size : PORT_ASPECTS := (a => 18+(7*boolean'pos(supports_dsp48e(family) > 0)), b => 18, m => 36+(7*boolean'pos(supports_dsp48e(family) > 0)), c => 48, p => 48);
variable hybrid_cfg : integer := 0;
variable a_pp : integer := 0;
variable b_pp : integer := 0;
variable top_mult_a_width : integer := 0;
variable top_mult_b_width : integer := 0;
variable side_mult_a_width : integer := 0;
variable side_mult_b_width : integer := 0;
variable block_a_width : integer := 0;
variable block_b_width : integer := 0;
variable a_port_size : integer := 0;
variable b_port_size : integer := 0;
variable x_width : integer := 0;
variable y_width : integer := 0;
variable block_a_type : integer := 0;
variable block_b_type : integer := 0;
variable largest_output : integer := 0;
-- final return value
variable lutcount : integer := 0;
begin -- function calc_hybrid_luts
---------------------------------------------------------------------------
-- This code was translated from the Tcl's calc_hybrid_lut_mult_dimensions()
---------------------------------------------------------------------------
a_pp := hybrid_calc_a_pp(family, op_width);
b_pp := hybrid_calc_b_pp(family, op_width);
a_port_size := mult_gen_max_of(op_width.a, port_size.a);
b_port_size := mult_gen_max_of(op_width.b, port_size.b);
if a_pp = 1 and b_pp = 1 then
-- one mult block
block_a_width := a_port_size;
if op_width.a_type = C_UNSIGNED and op_width.a >= port_size.a then
block_a_width := block_a_width - 1;
end if;
block_b_width := port_size.b;
if op_width.b_type = C_UNSIGNED and op_width.b >= port_size.b then
block_b_width := block_b_width - 1;
end if;
block_a_type := op_width.a_type;
block_b_type := op_width.b_type;
elsif a_pp = 2 and b_pp = 1 then
-- two mult blocks
block_a_width := port_size.a+wire_shift;
if op_width.a_type = C_UNSIGNED and op_width.a >= port_size.a then
block_a_width := block_a_width - 1;
end if;
block_b_width := port_size.b;
if op_width.b_type = C_UNSIGNED and op_width.b >= port_size.b then
block_b_width := block_b_width - 1;
end if;
block_a_type := op_width.a_type;
block_b_type := op_width.b_type;
elsif a_pp = 1 and b_pp = 2 then
-- two mult blocks
-- The operands will be swapped arund so that the A operand is the
-- largest. This means that we need to swap the a_type and b_type values over
-- so that they remain correct w.r.t. the operand widths
block_a_width := port_size.b+wire_shift;
if op_width.a_type = C_UNSIGNED then
block_a_width := block_a_width - 1;
end if;
block_b_width := port_size.a;
if op_width.b_type = C_UNSIGNED then
block_b_width := block_b_width - 1;
end if;
-- REVISIT: andreww: is there a bug here? should these values be swapped?
block_a_type := op_width.a_type;
block_b_type := op_width.b_type;
elsif a_pp = 2 and b_pp = 2 then
-- four mult blocks
block_a_width := port_size.a+wire_shift;
if op_width.a_type = C_UNSIGNED then
block_a_width := block_a_width - 1;
end if;
block_b_width := port_size.b+wire_shift;
if op_width.b_type = C_UNSIGNED then
block_b_width := block_b_width - 1;
end if;
block_a_type := op_width.a_type;
block_b_type := op_width.b_type;
end if;
hybrid_cfg := get_hybrid_configuration(family, a_pp, b_pp, op_width, port_size);
x_width := block_a_width;
y_width := block_b_width;
if (op_width.a > x_width and (op_width.b <= y_width or y_width < port_size.b)) and hybrid_cfg = ONE_MULT then
top_mult_a_width := op_width.a - x_width;
top_mult_b_width := op_width.b;
end if;
if (op_width.a <= x_width and (op_width.b > y_width or y_width < port_size.b)) and hybrid_cfg = ONE_MULT then
top_mult_a_width := op_width.a;
top_mult_b_width := op_width.b - y_width;
end if;
-- set up cfg for two LUT mults
-- this is the code from get_two_mult_cfg in the HDL
-- Also need to account for the fabric adder here
if op_width.a >= x_width and op_width.b >= y_width and hybrid_cfg = TWO_MULT then
-- The code above will automatically swap the operands so that the largest is
-- on the A bus. Because we only make 2 cuts in the partial product
-- array, this means that we want to make the A operand shorter than the B
-- operand to balance out the carry chain lengths for e.g. 22x20 multipliers
-- top fabric mult
top_mult_a_width := x_width;
top_mult_b_width := op_width.b - y_width;
-- side fabric mult
side_mult_a_width := op_width.a - x_width;
side_mult_b_width := op_width.b;
elsif op_width.b >= x_width and op_width.a >= y_width and hybrid_cfg = TWO_MULT then
-- top fabric mult
top_mult_a_width := y_width;
top_mult_b_width := op_width.b - x_width;
-- side fabric mult
side_mult_a_width := op_width.a - x_width;
side_mult_b_width := op_width.b;
end if;
---------------------------------------------------------------------------
-- End code translated from the Tcl's calc_hybrid_lut_mult_dimensions()
---------------------------------------------------------------------------
if hybrid_cfg = ONE_MULT then
lutcount := calc_lut_mult_resources(top_mult_a_width, top_mult_b_width);
elsif hybrid_cfg = TWO_MULT then
lutcount := (calc_lut_mult_resources(top_mult_a_width, top_mult_b_width)) + (calc_lut_mult_resources(side_mult_a_width, side_mult_b_width));
end if;
if hybrid_cfg = TWO_MULT then
if supports_dsp48e(family) > 0 or supports_dsp48(family) = 1 or supports_dsp48a(family) > 0 then
-- Use the LS adder - no extra logic unless it's a TWO_MULT case
largest_output := mult_gen_max_of(top_mult_a_width+top_mult_b_width, side_mult_a_width+side_mult_b_width);
-- add in the LUTs (roughly) for the adder bringing together the two fabric PPs
lutcount := lutcount + largest_output + 1;
else
-- Virtex-2, Spartan-3 etc. - always require at least 1 extra adder, two if it's a TWO_MULT configuration
largest_output := mult_gen_max_of(top_mult_a_width+top_mult_b_width, side_mult_a_width+side_mult_b_width);
-- add in the LUTs (roughly) fo rthe adder bringing together the two fabric PPs
lutcount := lutcount + largest_output + 1;
-- now add in the LUTs for the adder which brings together the output
-- of the large mult - this shoudl be 1 bit more than the output width of the
-- embedded mult part
lutcount := lutcount + block_a_width + block_b_width;
end if;
end if;
return lutcount;
end function calc_hybrid_luts;
-- purpose: works out how many embedded multipliers (DSPs or 18x18s) will be
-- used for a particular configuration
function calc_emb_mults (
family : string;
op_width : WIDTH_REC) return integer is
variable dsp_pps : R_DSP_PP;
variable a_pp, b_pp : integer := 0;
variable mults : integer := 0;
begin -- function calc_emb_mults
assert not(fn_debug) report "entered calc_emb_mults" severity note;
if has_dsp(family) then
assert not(fn_debug) report "calling calc_dsp48_pps for DSPs" severity note;
dsp_pps := calc_dsp48_pps(family, op_width);
mults := (dsp_pps.a_pp * dsp_pps.b_pp) + dsp_pps.extra_b_pp;
else
a_pp := calc_a_pp(family, op_width);
b_pp := calc_b_pp(op_width);
mults := a_pp * b_pp;
end if;
assert not(fn_debug) report "leaving calc_emb_mults" severity note;
return mults;
end function calc_emb_mults;
function calc_reqd_b_width (c_b_value : string; c_b_width, c_b_type : integer; reloadable : boolean) return integer is
begin
return select_val (c_b_width, bitstorep_string(c_b_value, c_b_type), not(reloadable));
end function calc_reqd_b_width;
function mult_gen_v11_2_luts (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer is
constant rec : R_MULT_RESOURCES := mult_gen_v11_2_gui_resources(family, c_a_width, c_a_type, c_b_width, c_b_type, c_mult_type, c_optimize_goal, c_latency, c_ccm_imp, c_b_value);
constant luts : integer := rec.LUTs;
begin
return luts;
end function mult_gen_v11_2_luts;
function mult_gen_v11_2_mults (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer is
constant rec : R_MULT_RESOURCES := mult_gen_v11_2_gui_resources(family, c_a_width, c_a_type, c_b_width, c_b_type, c_mult_type, c_optimize_goal, c_latency, c_ccm_imp, c_b_value);
constant mults : integer := rec.MULT18X18s + rec.DSPs; -- only one of these values will be non-zero
begin
return mults;
end function mult_gen_v11_2_mults;
function mult_gen_v11_2_brams (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return integer is
constant rec : R_MULT_RESOURCES := mult_gen_v11_2_gui_resources(family, c_a_width, c_a_type, c_b_width, c_b_type, c_mult_type, c_optimize_goal, c_latency, c_ccm_imp, c_b_value);
constant brams : integer := rec.BRAMs;
begin
return brams;
end function mult_gen_v11_2_brams;
-- purpose: calculates the FPGA resources for all supported multiplier configurations
-- For use with VTFC to provide resource counts in the mult_gen CoreGen GUI
function mult_gen_v11_2_gui_resources (
family : string;
c_a_width : integer;
c_a_type : integer;
c_b_width : integer;
c_b_type : integer;
c_mult_type : integer;
c_optimize_goal : integer;
c_latency : integer;
c_ccm_imp : integer;
c_b_value : string)
return R_MULT_RESOURCES is
-- The values we will eventually return
variable mult_resources : R_MULT_RESOURCES := (LUTs => 0, DSPs => 0, MULT18X18s => 0, BRAMs => 0);
-- Intermediate variables and constants
constant port_size : PORT_ASPECTS := get_port_sizes(family);
constant op_width : WIDTH_REC := get_true_widths(family, c_a_width, c_b_width, c_a_type, c_b_type, port_size);
constant reloadable : boolean := false;
variable number_of_pps : integer := 0;
variable pp_width : integer := 0;
variable last_pp_width : integer := 0;
variable need_addsub : boolean := false;
variable need_0_minus_pp : boolean := false;
variable trimmed_msbs : integer := 0;
variable trimmed_lsbs : integer := 0;
variable num_brams : integer := 0;
variable adder_luts : integer := 0;
variable b_length : integer := 0;
variable new_b_width : integer := 0;
variable largest_pp : integer := 0;
variable reqd_b_value : string(1 to calc_reqd_b_width(c_b_value, c_b_width, c_b_type, false));
variable number_of_adders : integer := 0;
begin -- function mult_gen_v11_2_gui_resources
assert not(fn_debug) report "entered mult_gen_v11_2_gui_resources" severity note;
case c_mult_type is
when LUT =>
mult_resources.LUTs := calc_lut_mult_resources(c_a_width, c_b_width);
mult_resources.DSPs := 0;
mult_resources.MULT18X18s := 0;
mult_resources.BRAMs := 0;
when EMBEDDED_MULT =>
if supports_dsp48e(family) > 0 or supports_dsp48(family) = 1 or supports_dsp48a(family) > 0 then
-- DSP-based implementations
case c_optimize_goal is
when EMB_MULT_RESOURCES =>
assert false report "WARNING: The LUT results (maybe also the DSP result) will be wrong because the widths need to swapped so A is largest" severity warning;
mult_resources.DSPs := calc_hybrid_emb_mults(family, op_width);
mult_resources.LUTs := calc_hybrid_luts(family, op_width);
mult_resources.MULT18X18s := 0;
mult_resources.BRAMs := 0;
when CORE_SPEED =>
assert not(fn_debug) report "calling calc_emb_mults" severity note;
mult_resources.DSPs := calc_emb_mults(family, op_width);
mult_resources.LUTs := 0;
mult_resources.MULT18X18s := 0;
mult_resources.BRAMs := 0;
when others =>
null;
end case;
else
case c_optimize_goal is
-- Mult18x18-based implementations
when EMB_MULT_RESOURCES =>
assert false report "WARNING: The LUT results (maybe also the DSP result) will be wrong because the widths need to swapped so A is largest" severity warning;
mult_resources.DSPs := 0;
mult_resources.LUTs := calc_hybrid_luts(family, op_width);
mult_resources.MULT18X18s := calc_hybrid_emb_mults(family, op_width);
mult_resources.BRAMs := 0;
when CORE_SPEED =>
mult_resources.DSPs := 0;
mult_resources.LUTs := 0;
mult_resources.MULT18X18s := calc_emb_mults(family, op_width);
mult_resources.BRAMs := 0;
when others =>
null;
end case;
end if;
when FIXED_CCM =>
if check_const_power_of_two(c_b_value, c_b_type, c_mult_type) then
-- constant is a power of two
mult_resources.DSPs := 0;
mult_resources.LUTs := 0;
mult_resources.MULT18X18s := 0;
mult_resources.BRAMS := 0;
else
case c_ccm_imp is
when DIST_MEM =>
mult_resources.DSPs := 0;
mult_resources.MULT18X18s := 0;
mult_resources.BRAMs := 0;
number_of_pps := calc_num_pps(calc_a_input_width(c_b_width, 0, get_rom_addr_width(family, c_ccm_imp), 1), get_rom_addr_width(family, c_ccm_imp));
pp_width := calc_pp_width(c_b_width, c_b_type, c_b_value, 1, c_a_width, c_a_type, 0, false, false);
last_pp_width := calc_pp_width(c_b_width, c_b_type, c_b_value, 1, c_a_width, c_a_type, 0, true, false);
need_addsub := false;
need_0_minus_pp := false;
number_of_adders := select_val(number_of_pps-1, 1, need_0_minus_pp);
adder_luts := (number_of_adders * mult_gen_max_of(pp_width, last_pp_width));
mult_resources.LUTs := ((number_of_pps-1)*pp_width) + last_pp_width + adder_luts;
when BRAM =>
mult_resources.DSPs := 0;
mult_resources.MULT18X18s := 0;
number_of_pps := calc_num_pps(calc_a_input_width(c_b_width, 0, get_rom_addr_width(family, c_ccm_imp), 1), get_rom_addr_width(family, c_ccm_imp));
pp_width := calc_pp_width(c_b_width, c_b_type, c_b_value, 1, c_a_width, c_a_type, 0, false, false);
last_pp_width := calc_pp_width(c_b_width, c_b_type, c_b_value, 1, c_a_width, c_a_type, 0, true, false);
need_addsub := false;
need_0_minus_pp := false;
number_of_adders := select_val(number_of_pps-1, 1, need_0_minus_pp);
num_brams := (number_of_pps + 1) / 2;
if num_brams > 1 then
largest_pp := mult_gen_max_of(pp_width, last_pp_width);
adder_luts := (number_of_adders * largest_pp) - (largest_pp / 2);
else
adder_luts := 0;
end if;
mult_resources.LUTs := adder_luts;
if supports_dsp48e(family) > 0 then
-- we can pack 2x 18K BRAMs into a 36K BRAM, so need further division here to give
-- true number of BRAM blocks - need to round up to account for odd # BRAMs
-- This will indicate that a whole 36K is used, even though only half may actually be
if num_brams > 1 then
mult_resources.BRAMs := (num_brams + 1) / 2;
end if;
else
mult_resources.BRAMs := num_brams;
end if;
when MULTS =>
reqd_b_value := calc_reqd_b_value(c_b_value, c_b_width, c_b_type, calc_reqd_b_width(c_b_value, c_b_width, c_b_type, false));
b_length := reqd_b_value'length;
trimmed_msbs := get_trimmed_leading_bits(c_b_value, c_b_type, c_mult_type);
trimmed_lsbs := calc_shift_bits(reqd_b_value, 1);
new_b_width := b_length - (trimmed_msbs + trimmed_lsbs);
mult_resources.BRAMS := 0;
if supports_dsp48e(family) > 0 or supports_dsp48(family) = 1 or supports_dsp48a(family) > 0 then
mult_resources.DSPs := calc_emb_mults(family, op_width);
mult_resources.MULT18X18s := 0;
mult_resources.LUTs := 0;
else
mult_resources.DSPs := 0;
mult_resources.MULT18X18s := calc_emb_mults(family, op_width);
mult_resources.LUTs := 0;
end if;
when others =>
null;
end case;
end if;
when others =>
null;
end case;
return mult_resources;
end function mult_gen_v11_2_gui_resources;
function get_port_sizes (family : string) return PORT_ASPECTS is
variable port_size : PORT_ASPECTS;
begin
-- set up the port sizes for all families
port_size.a := 18+(7*boolean'pos(supports_dsp48e(family) > 0));
port_size.b := 18;
port_size.m := 36+(7*boolean'pos(supports_dsp48e(family) > 0));
port_size.c := 48;
port_size.p := 48;
return port_size;
end function get_port_sizes;
end package body mult_gen_pkg_v11_2;
|
--!
--! @file: my_package.vhd
--! @brief: example9_2
--! @author: Antonio Gutierrez
--! @date: 2013-11-27
--!
--!
--------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_all;
--------------------------------------
package my_package is
function order_and_fill(input : unsigned; bits: natural) return unsigned
end package my_package;
------------------------------
package body my_package is
function order_and_fill(input : unsigned; bits: natural) return unsigned is
variable a: unsigned(input'length-1 downto 0);
variable result: unsigned(bits-1 downto 0);
begin
-- check input size
assert (input'length <= bits)
report "Improper input size!"
severity failure;
-- organize input
if (input'left > input'right) then
a := input;
else
for1: for i in a'range loop
a(i) := input(input'left + i);
end loop for1;
end if;
-- fill with zeros
if (a'length < bits) then
result(bits-1 downto a'length) := (others => '0');
result(a'length-1 downto 0) := a;
else
result := a;
end if;
return result;
end function order_and_fill;
end package body my_package;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity LIFO_T is
end LIFO_T;
architecture Beh of LIFO_T is
component LIFO is
generic(
-- øèíà àäðåñà
m: integer := 2;
-- øèíà äàííûõ
n: integer := 2
);
port (
-- ñèíõðîíèçàöèÿ
CLK: in std_logic;
-- ñèãíàë óïðàâëåíèÿ ÷òåíèåì/çàïèñüþ
WR: in std_logic;
-- äâóíàïðàâëåííàÿ øèíà äàííûõ
DB: inout std_logic_vector (n-1 downto 0);
EMPTY: out std_logic;
FULL: out std_logic
);
end component;
signal CLK: std_logic := '0';
signal WR: std_logic := '0';
signal DB: std_logic_vector(1 downto 0) := "00";
signal empty: std_logic;
signal full: std_logic;
constant CLK_Period: time := 10 ns;
begin
ULIFO: LIFO port map(
CLK => CLK,
WR => WR,
DB => DB,
empty => empty,
full => full
);
CLK_Process: process
begin
CLK <= '0';
wait for CLK_Period/2;
CLK <= '1';
wait for CLK_Period/2;
end process;
main: process
begin
wait for clk_period;
WR <= '0';
DB <= "11";
wait for clk_period;
DB <= "10";
wait for clk_period;
DB <= "01";
wait for clk_period;
WR <= '1';
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait for clk_period;
DB <= "ZZ";
wait;
end process;
end Beh; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Segment7Decoder is
port (bcd : in bit_vector(3 downto 0); --BCD input
segment7 : out bit_vector(6 downto 0) -- 7 bit decoded output.
);
end Segment7Decoder;
--'a' corresponds to MSB of segment7 and g corresponds to LSB of segment7.
architecture Behavioral of Segment7Decoder is
begin
process (bcd)
BEGIN
case bcd is
when "0000"=> segment7 <="1000000"; -- '0'
when "0001"=> segment7 <="1111001"; -- '1'
when "0010"=> segment7 <="0100100"; -- '2'
when "0011"=> segment7 <="0110000"; -- '3'
when "0100"=> segment7 <="0011001"; -- '4'
when "0101"=> segment7 <="0010010"; -- '5'
when "0110"=> segment7 <="0000010"; -- '6'
when "0111"=> segment7 <="1111000"; -- '7'
when "1000"=> segment7 <="0000000"; -- '8'
when "1001"=> segment7 <="0010000"; -- '9'
--nothing is displayed when a number more than 9 is given as input.
when others=> segment7 <="1111111";
end case;
end process;
end Behavioral; |
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity core is
Port ( clock : in STD_LOGIC;
extReset : in STD_LOGIC;
cmd : in STD_LOGIC_VECTOR (39 downto 0);
execute : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputClock : in STD_LOGIC;
sampleReady50 : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end core;
architecture Behavioral of core is
COMPONENT decoder
PORT ( opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic
);
END COMPONENT;
COMPONENT flags
PORT(
data : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
write : IN std_logic;
demux : OUT std_logic;
filter : OUT std_logic;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
END COMPONENT;
COMPONENT sync is
PORT (
input : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT sampler
PORT(
input : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
exClock : in std_logic;
external : in std_logic;
data : IN std_logic_vector(23 downto 0);
wrDivider : IN std_logic;
sample : OUT std_logic_vector(31 downto 0);
ready : OUT std_logic;
ready50 : out std_logic
);
END COMPONENT;
COMPONENT trigger
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : IN std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : IN std_logic_vector(3 downto 0);
wrValue : IN std_logic_vector(3 downto 0);
wrConfig : IN std_logic_vector(3 downto 0);
arm : IN std_logic;
demuxed : in std_logic;
run : out STD_LOGIC
);
END COMPONENT;
COMPONENT controller
PORT(
clock : IN std_logic;
reset : in std_logic;
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
wrSize : in std_logic;
run : in std_logic;
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector(31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
END COMPONENT;
COMPONENT rle_enc
PORT(
clock : IN std_logic;
reset : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
validIn : IN std_logic;
enable : IN std_logic;
dataOut : OUT std_logic_vector(31 downto 0);
validOut : OUT std_logic
);
END COMPONENT;
signal opcode : std_logic_vector (7 downto 0);
signal data, rleOut : std_logic_vector (31 downto 0);
signal sample, syncedInput : std_logic_vector (31 downto 0);
signal sampleClock, run, reset, rleValid, rleEnable : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted, wrFlags, sampleReady: std_logic;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= extReset or resetCmd;
-- select between internal and external sampling clock
BUFGMUX_intex: BUFGMUX
port map (
O => sampleClock, -- Clock MUX output
I0 => clock, -- Clock0 input
I1 => inputClock, -- Clock1 input
S => flagExternal -- Clock select input
);
Inst_decoder: decoder PORT MAP(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd
);
Inst_flags: flags PORT MAP(
data => data(8 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
rle => rleEnable
);
Inst_sync: sync PORT MAP(
input => input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedInput
);
Inst_sampler: sampler PORT MAP(
input => syncedInput,
clock => clock,
exClock => inputClock, -- use sampleClock?
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
ready50 => sampleReady50
);
Inst_trigger: trigger PORT MAP(
input => sample,
inputReady => sampleReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run
);
Inst_controller: controller PORT MAP(
clock => clock,
reset => reset,
input => rleOut,
inputReady => rleValid,
data => data,
wrSize => wrsize,
run => run,
busy => outputBusy,
send => outputSend,
output => output,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
Inst_rle_enc: rle_enc PORT MAP(
clock => clock,
reset => reset,
dataIn => sample,
validIn => sampleReady,
enable => rleEnable,
dataOut => rleOut,
validOut => rleValid
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity core is
Port ( clock : in STD_LOGIC;
extReset : in STD_LOGIC;
cmd : in STD_LOGIC_VECTOR (39 downto 0);
execute : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputClock : in STD_LOGIC;
sampleReady50 : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end core;
architecture Behavioral of core is
COMPONENT decoder
PORT ( opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic
);
END COMPONENT;
COMPONENT flags
PORT(
data : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
write : IN std_logic;
demux : OUT std_logic;
filter : OUT std_logic;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
END COMPONENT;
COMPONENT sync is
PORT (
input : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT sampler
PORT(
input : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
exClock : in std_logic;
external : in std_logic;
data : IN std_logic_vector(23 downto 0);
wrDivider : IN std_logic;
sample : OUT std_logic_vector(31 downto 0);
ready : OUT std_logic;
ready50 : out std_logic
);
END COMPONENT;
COMPONENT trigger
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : IN std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : IN std_logic_vector(3 downto 0);
wrValue : IN std_logic_vector(3 downto 0);
wrConfig : IN std_logic_vector(3 downto 0);
arm : IN std_logic;
demuxed : in std_logic;
run : out STD_LOGIC
);
END COMPONENT;
COMPONENT controller
PORT(
clock : IN std_logic;
reset : in std_logic;
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
wrSize : in std_logic;
run : in std_logic;
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector(31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
END COMPONENT;
COMPONENT rle_enc
PORT(
clock : IN std_logic;
reset : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
validIn : IN std_logic;
enable : IN std_logic;
dataOut : OUT std_logic_vector(31 downto 0);
validOut : OUT std_logic
);
END COMPONENT;
signal opcode : std_logic_vector (7 downto 0);
signal data, rleOut : std_logic_vector (31 downto 0);
signal sample, syncedInput : std_logic_vector (31 downto 0);
signal sampleClock, run, reset, rleValid, rleEnable : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted, wrFlags, sampleReady: std_logic;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= extReset or resetCmd;
-- select between internal and external sampling clock
BUFGMUX_intex: BUFGMUX
port map (
O => sampleClock, -- Clock MUX output
I0 => clock, -- Clock0 input
I1 => inputClock, -- Clock1 input
S => flagExternal -- Clock select input
);
Inst_decoder: decoder PORT MAP(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd
);
Inst_flags: flags PORT MAP(
data => data(8 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
rle => rleEnable
);
Inst_sync: sync PORT MAP(
input => input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedInput
);
Inst_sampler: sampler PORT MAP(
input => syncedInput,
clock => clock,
exClock => inputClock, -- use sampleClock?
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
ready50 => sampleReady50
);
Inst_trigger: trigger PORT MAP(
input => sample,
inputReady => sampleReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run
);
Inst_controller: controller PORT MAP(
clock => clock,
reset => reset,
input => rleOut,
inputReady => rleValid,
data => data,
wrSize => wrsize,
run => run,
busy => outputBusy,
send => outputSend,
output => output,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
Inst_rle_enc: rle_enc PORT MAP(
clock => clock,
reset => reset,
dataIn => sample,
validIn => sampleReady,
enable => rleEnable,
dataOut => rleOut,
validOut => rleValid
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity core is
Port ( clock : in STD_LOGIC;
extReset : in STD_LOGIC;
cmd : in STD_LOGIC_VECTOR (39 downto 0);
execute : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputClock : in STD_LOGIC;
sampleReady50 : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end core;
architecture Behavioral of core is
COMPONENT decoder
PORT ( opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic
);
END COMPONENT;
COMPONENT flags
PORT(
data : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
write : IN std_logic;
demux : OUT std_logic;
filter : OUT std_logic;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
END COMPONENT;
COMPONENT sync is
PORT (
input : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT sampler
PORT(
input : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
exClock : in std_logic;
external : in std_logic;
data : IN std_logic_vector(23 downto 0);
wrDivider : IN std_logic;
sample : OUT std_logic_vector(31 downto 0);
ready : OUT std_logic;
ready50 : out std_logic
);
END COMPONENT;
COMPONENT trigger
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : IN std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : IN std_logic_vector(3 downto 0);
wrValue : IN std_logic_vector(3 downto 0);
wrConfig : IN std_logic_vector(3 downto 0);
arm : IN std_logic;
demuxed : in std_logic;
run : out STD_LOGIC
);
END COMPONENT;
COMPONENT controller
PORT(
clock : IN std_logic;
reset : in std_logic;
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
wrSize : in std_logic;
run : in std_logic;
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector(31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
END COMPONENT;
COMPONENT rle_enc
PORT(
clock : IN std_logic;
reset : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
validIn : IN std_logic;
enable : IN std_logic;
dataOut : OUT std_logic_vector(31 downto 0);
validOut : OUT std_logic
);
END COMPONENT;
signal opcode : std_logic_vector (7 downto 0);
signal data, rleOut : std_logic_vector (31 downto 0);
signal sample, syncedInput : std_logic_vector (31 downto 0);
signal sampleClock, run, reset, rleValid, rleEnable : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted, wrFlags, sampleReady: std_logic;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= extReset or resetCmd;
-- select between internal and external sampling clock
BUFGMUX_intex: BUFGMUX
port map (
O => sampleClock, -- Clock MUX output
I0 => clock, -- Clock0 input
I1 => inputClock, -- Clock1 input
S => flagExternal -- Clock select input
);
Inst_decoder: decoder PORT MAP(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd
);
Inst_flags: flags PORT MAP(
data => data(8 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
rle => rleEnable
);
Inst_sync: sync PORT MAP(
input => input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedInput
);
Inst_sampler: sampler PORT MAP(
input => syncedInput,
clock => clock,
exClock => inputClock, -- use sampleClock?
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
ready50 => sampleReady50
);
Inst_trigger: trigger PORT MAP(
input => sample,
inputReady => sampleReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run
);
Inst_controller: controller PORT MAP(
clock => clock,
reset => reset,
input => rleOut,
inputReady => rleValid,
data => data,
wrSize => wrsize,
run => run,
busy => outputBusy,
send => outputSend,
output => output,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
Inst_rle_enc: rle_enc PORT MAP(
clock => clock,
reset => reset,
dataIn => sample,
validIn => sampleReady,
enable => rleEnable,
dataOut => rleOut,
validOut => rleValid
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- core.vhd
--
-- Copyright (C) 2006 Michael Poppitz
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
-- General Public License for more details.
--
-- You should have received a copy of the GNU General Public License along
-- with this program; if not, write to the Free Software Foundation, Inc.,
-- 51 Franklin St, Fifth Floor, Boston, MA 02110, USA
--
----------------------------------------------------------------------------------
--
-- Details: http://www.sump.org/projects/analyzer/
--
-- The core contains all "platform independent" modules and provides a
-- simple interface to those components. The core makes the analyzer
-- memory type and computer interface independent.
--
-- This module also provides a better target for test benches as commands can
-- be sent to the core easily.
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;
entity core is
Port ( clock : in STD_LOGIC;
extReset : in STD_LOGIC;
cmd : in STD_LOGIC_VECTOR (39 downto 0);
execute : in STD_LOGIC;
input : in STD_LOGIC_VECTOR (31 downto 0);
inputClock : in STD_LOGIC;
sampleReady50 : out STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0);
outputSend : out STD_LOGIC;
outputBusy : in STD_LOGIC;
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
end core;
architecture Behavioral of core is
COMPONENT decoder
PORT ( opcode : in STD_LOGIC_VECTOR (7 downto 0);
execute : in std_logic;
clock : in std_logic;
wrtrigmask : out std_logic_vector(3 downto 0);
wrtrigval : out std_logic_vector(3 downto 0);
wrtrigcfg : out std_logic_vector(3 downto 0);
wrspeed : out STD_LOGIC;
wrsize : out std_logic;
wrFlags : out std_logic;
arm : out std_logic;
reset : out std_logic
);
END COMPONENT;
COMPONENT flags
PORT(
data : IN std_logic_vector(8 downto 0);
clock : IN std_logic;
write : IN std_logic;
demux : OUT std_logic;
filter : OUT std_logic;
external : out std_logic;
inverted : out std_logic;
rle : out std_logic
);
END COMPONENT;
COMPONENT sync is
PORT (
input : in STD_LOGIC_VECTOR (31 downto 0);
clock : in STD_LOGIC;
enableFilter : in STD_LOGIC;
enableDemux : in STD_LOGIC;
falling : in STD_LOGIC;
output : out STD_LOGIC_VECTOR (31 downto 0)
);
END COMPONENT;
COMPONENT sampler
PORT(
input : IN std_logic_vector(31 downto 0);
clock : IN std_logic;
exClock : in std_logic;
external : in std_logic;
data : IN std_logic_vector(23 downto 0);
wrDivider : IN std_logic;
sample : OUT std_logic_vector(31 downto 0);
ready : OUT std_logic;
ready50 : out std_logic
);
END COMPONENT;
COMPONENT trigger
PORT(
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : IN std_logic_vector(31 downto 0);
clock : in std_logic;
reset : in std_logic;
wrMask : IN std_logic_vector(3 downto 0);
wrValue : IN std_logic_vector(3 downto 0);
wrConfig : IN std_logic_vector(3 downto 0);
arm : IN std_logic;
demuxed : in std_logic;
run : out STD_LOGIC
);
END COMPONENT;
COMPONENT controller
PORT(
clock : IN std_logic;
reset : in std_logic;
input : IN std_logic_vector(31 downto 0);
inputReady : in std_logic;
data : in std_logic_vector(31 downto 0);
wrSize : in std_logic;
run : in std_logic;
busy : in std_logic;
send : out std_logic;
output : out std_logic_vector(31 downto 0);
memoryIn : in STD_LOGIC_VECTOR (31 downto 0);
memoryOut : out STD_LOGIC_VECTOR (31 downto 0);
memoryRead : out STD_LOGIC;
memoryWrite : out STD_LOGIC
);
END COMPONENT;
COMPONENT rle_enc
PORT(
clock : IN std_logic;
reset : IN std_logic;
dataIn : IN std_logic_vector(31 downto 0);
validIn : IN std_logic;
enable : IN std_logic;
dataOut : OUT std_logic_vector(31 downto 0);
validOut : OUT std_logic
);
END COMPONENT;
signal opcode : std_logic_vector (7 downto 0);
signal data, rleOut : std_logic_vector (31 downto 0);
signal sample, syncedInput : std_logic_vector (31 downto 0);
signal sampleClock, run, reset, rleValid, rleEnable : std_logic;
signal wrtrigmask, wrtrigval, wrtrigcfg : std_logic_vector(3 downto 0);
signal wrDivider, wrsize, arm, resetCmd: std_logic;
signal flagDemux, flagFilter, flagExternal, flagInverted, wrFlags, sampleReady: std_logic;
begin
data <= cmd(39 downto 8);
opcode <= cmd(7 downto 0);
reset <= extReset or resetCmd;
-- select between internal and external sampling clock
BUFGMUX_intex: BUFGMUX
port map (
O => sampleClock, -- Clock MUX output
I0 => clock, -- Clock0 input
I1 => inputClock, -- Clock1 input
S => flagExternal -- Clock select input
);
Inst_decoder: decoder PORT MAP(
opcode => opcode,
execute => execute,
clock => clock,
wrtrigmask => wrtrigmask,
wrtrigval => wrtrigval,
wrtrigcfg => wrtrigcfg,
wrspeed => wrDivider,
wrsize => wrsize,
wrFlags => wrFlags,
arm => arm,
reset => resetCmd
);
Inst_flags: flags PORT MAP(
data => data(8 downto 0),
clock => clock,
write => wrFlags,
demux => flagDemux,
filter => flagFilter,
external => flagExternal,
inverted => flagInverted,
rle => rleEnable
);
Inst_sync: sync PORT MAP(
input => input,
clock => sampleClock,
enableFilter => flagFilter,
enableDemux => flagDemux,
falling => flagInverted,
output => syncedInput
);
Inst_sampler: sampler PORT MAP(
input => syncedInput,
clock => clock,
exClock => inputClock, -- use sampleClock?
external => flagExternal,
data => data(23 downto 0),
wrDivider => wrDivider,
sample => sample,
ready => sampleReady,
ready50 => sampleReady50
);
Inst_trigger: trigger PORT MAP(
input => sample,
inputReady => sampleReady,
data => data,
clock => clock,
reset => reset,
wrMask => wrtrigmask,
wrValue => wrtrigval,
wrConfig => wrtrigcfg,
arm => arm,
demuxed => flagDemux,
run => run
);
Inst_controller: controller PORT MAP(
clock => clock,
reset => reset,
input => rleOut,
inputReady => rleValid,
data => data,
wrSize => wrsize,
run => run,
busy => outputBusy,
send => outputSend,
output => output,
memoryIn => memoryIn,
memoryOut => memoryOut,
memoryRead => memoryRead,
memoryWrite => memoryWrite
);
Inst_rle_enc: rle_enc PORT MAP(
clock => clock,
reset => reset,
dataIn => sample,
validIn => sampleReady,
enable => rleEnable,
dataOut => rleOut,
validOut => rleValid
);
end Behavioral;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Codeword_Generator_n_m_v2
-- Module Name: Codeword_Generator_n_m_v2
-- Project Name: McEliece QD-Goppa Encoder
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- The first and only step in QD-Goppa Code encoding.
-- This circuit transforms an k-bit message into a valid n-bit codeword.
-- The transformation is an multiplication of a message of k-bits by the
-- Generator matrix G. The Generator matrix is composed of Identity Matrix and
-- another matrix A. For this reason the first k bits of the codeword are equal
-- to the message, only the last n-k bits are computed. This circuit works only
-- only for QD-Goppa codes, where matrix A is composed of dyadic matrices and
-- can be stored only by the first row of each dyadic matrix.
-- Matrix A is supposed to be stored with a word with the same size as dyadic matrix rows.
-- Also, each dyadic matrix row followed by each one, in a row-wise pattern.
--
-- This circuit process n+m bits at time, each time is 1 cycle.
-- n and m are represented as number_of_multipliers_per_acc and number_of_accs parameters.
-- This circuit is efficient however it process in two steps:
-- First it copies k bits.
-- Second compute the last n-k bits.
-- To decrease response time, both operations are done in parallel in version n_m_v3.
--
-- The circuits parameters
--
-- number_of_multipliers_per_acc :
--
-- The number of matrix rows and message values calculate at once in one or more accumulators.
-- On this implementation this value, must be the same of number_of_accs,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
--
-- number_of_accs :
--
-- The number of matrix columns and codeword values calculate at once.
-- On this implementation this value, must be the same of number_of_multipliers_per_acc,
-- because of copy message. When copying message message values loaded must be same stored in codeword.
--
-- length_message :
--
-- Length in bits of message size and also part of matrix size.
--
-- size_message :
--
-- The number of bits necessary to store the message. The ceil(log2(lenght_message))
--
-- length_codeword :
--
-- Length in bits of codeword size and also part of matrix size.
--
-- size_codeword :
--
-- The number of bits necessary to store the codeword. The ceil(log2(legth_codeword))
--
-- size_dyadic_matrix :
--
-- The number of bits necessary to store one row of the dyadic matrix.
-- It is also the ceil(log2(number of errors in the code))
--
-- number_dyadic_matrices :
--
-- The number of dyadic matrices present in matrix A.
--
-- size_number_dyadic_matrices :
--
-- The number of bits necessary to store the number of dyadic matrices.
-- The ceil(log2(number_dyadic_matrices))
--
-- Dependencies:
--
-- VHDL-93
-- IEEE.NUMERIC_STD_ALL;
--
-- controller_codeword_generator_2 Rev 1.0
-- adder_gf_2_m Rev 1.0
-- register_nbits Rev 1.0
-- register_rst_nbits Rev 1.0
-- counter_rst_nbits Rev 1.0
-- counter_rst_set_nbits Rev 1.0
--
-- Revision:
-- Revision 1.00 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity codeword_generator_n_m_v2 is
Generic(
-- QD-GOPPA [2528, 2144, 32, 12] --
number_of_multipliers_per_acc : integer := 4;
number_of_accs : integer := 4;
length_message : integer := 2144;
size_message : integer := 12;
length_codeword : integer := 2528;
size_codeword : integer := 12;
size_dyadic_matrix : integer := 5;
number_dyadic_matrices : integer := 804;
size_number_dyadic_matrices : integer := 10
-- QD-GOPPA [2816, 2048, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2048;
-- size_message : integer := 12;
-- length_codeword : integer := 2816;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 384;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [3328, 2560, 64, 12] --
-- number_of_multipliers_per_acc : integer := 1;
-- number_of_accs : integer := 1;
-- length_message : integer := 2560;
-- size_message : integer := 12;
-- length_codeword : integer := 3328;
-- size_codeword : integer := 12;
-- size_dyadic_matrix : integer := 6;
-- number_dyadic_matrices : integer := 480;
-- size_number_dyadic_matrices : integer := 9
-- QD-GOPPA [7296, 5632, 128, 13] --
-- number_of_multipliers_per_acc : integer := 128;
-- number_of_accs : integer := 128;
-- length_message : integer := 5632;
-- size_message : integer := 13;
-- length_codeword : integer := 7296;
-- size_codeword : integer := 13;
-- size_dyadic_matrix : integer := 7;
-- number_dyadic_matrices : integer := 572;
-- size_number_dyadic_matrices : integer := 10
);
Port(
codeword : in STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
matrix : in STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
message : in STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
clk : in STD_LOGIC;
rst : in STD_LOGIC;
new_codeword : out STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
write_enable_new_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC;
address_codeword : out STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
address_message : out STD_LOGIC_VECTOR((size_message - 1) downto 0);
address_matrix : out STD_LOGIC_VECTOR((size_dyadic_matrix + size_number_dyadic_matrices - 1) downto 0)
);
end codeword_generator_n_m_v2;
architecture RTL of codeword_generator_n_m_v2 is
component controller_codeword_generator_2
Port(
clk : in STD_LOGIC;
rst : in STD_LOGIC;
limit_ctr_dyadic_column_q : in STD_LOGIC;
limit_ctr_dyadic_row_q : in STD_LOGIC;
limit_ctr_address_message_q : in STD_LOGIC;
limit_ctr_address_codeword_q : in STD_LOGIC;
zero_ctr_address_message_q : in STD_LOGIC;
write_enable_new_codeword : out STD_LOGIC;
external_matrix_ce : out STD_LOGIC;
message_added_to_codeword : out STD_LOGIC;
reg_codeword_ce : out STD_LOGIC;
reg_codeword_rst : out STD_LOGIC;
reg_message_ce : out STD_LOGIC;
reg_matrix_ce : out STD_LOGIC;
ctr_dyadic_column_ce : out STD_LOGIC;
ctr_dyadic_column_rst : out STD_LOGIC;
ctr_dyadic_row_ce : out STD_LOGIC;
ctr_dyadic_row_rst : out STD_LOGIC;
ctr_dyadic_matrices_ce : out STD_LOGIC;
ctr_dyadic_matrices_rst : out STD_LOGIC;
ctr_address_base_message_ce : out STD_LOGIC;
ctr_address_base_message_rst : out STD_LOGIC;
ctr_address_base_codeword_ce : out STD_LOGIC;
ctr_address_base_codeword_rst : out STD_LOGIC;
ctr_address_base_codeword_set : out STD_LOGIC;
internal_codeword : out STD_LOGIC;
codeword_finalized : out STD_LOGIC
);
end component;
component register_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component register_rst_nbits
Generic (size : integer);
Port (
d : in STD_LOGIC_VECTOR ((size - 1) downto 0);
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component counter_rst_set_nbits
Generic (
size : integer;
increment_value : integer
);
Port (
clk : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
set : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
set_value : in STD_LOGIC_VECTOR ((size - 1) downto 0);
q : out STD_LOGIC_VECTOR ((size - 1) downto 0)
);
end component;
component adder_gf_2_m
Generic(
gf_2_m : integer := 1;
number_of_elements : integer range 2 to integer'high := 2
);
Port(
a : in STD_LOGIC_VECTOR(((gf_2_m)*(number_of_elements) - 1) downto 0);
o : out STD_LOGIC_VECTOR((gf_2_m - 1) downto 0)
);
end component;
signal reg_codeword_d : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_codeword_ce : STD_LOGIC;
signal reg_codeword_rst : STD_LOGIC;
constant reg_codeword_rst_value : STD_LOGIC_VECTOR := "0";
signal reg_codeword_q : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal reg_message_d : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_message_ce : STD_LOGIC;
signal reg_message_q : STD_LOGIC_VECTOR((number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_d : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal reg_matrix_ce : STD_LOGIC;
signal reg_matrix_q : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal external_matrix_d : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal external_matrix_ce : STD_LOGIC;
signal external_matrix_q : STD_LOGIC_VECTOR((2**size_dyadic_matrix - 1) downto 0);
signal ctr_dyadic_column_ce : STD_LOGIC;
signal ctr_dyadic_column_rst : STD_LOGIC;
constant ctr_dyadic_column_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_column_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_column_q : STD_LOGIC;
signal ctr_dyadic_row_ce : STD_LOGIC;
signal ctr_dyadic_row_rst : STD_LOGIC;
constant ctr_dyadic_row_rst_value : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_dyadic_row_q : STD_LOGIC_VECTOR((size_dyadic_matrix - 1) downto 0);
signal limit_ctr_dyadic_row_q : STD_LOGIC;
signal ctr_dyadic_matrices_ce : STD_LOGIC;
signal ctr_dyadic_matrices_rst : STD_LOGIC;
constant ctr_dyadic_matrices_rst_value : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0) := (others => '0');
signal ctr_dyadic_matrices_q : STD_LOGIC_VECTOR((size_number_dyadic_matrices - 1) downto 0);
signal ctr_address_base_message_ce : STD_LOGIC;
signal ctr_address_base_message_rst : STD_LOGIC;
constant ctr_address_base_message_rst_value : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0) := (others => '0');
signal ctr_address_base_message_q : STD_LOGIC_VECTOR((size_message - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_message_q : STD_LOGIC;
signal zero_ctr_address_message_q : STD_LOGIC;
signal ctr_address_base_codeword_ce : STD_LOGIC;
signal ctr_address_base_codeword_rst : STD_LOGIC;
signal ctr_address_base_codeword_set : STD_LOGIC;
constant ctr_address_base_codeword_rst_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := (others => '0');
constant ctr_address_base_codeword_set_value : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0) := std_logic_vector(to_unsigned(length_message/2**size_dyadic_matrix, size_codeword - size_dyadic_matrix));
signal ctr_address_base_codeword_q : STD_LOGIC_VECTOR((size_codeword - size_dyadic_matrix - 1) downto 0);
signal limit_ctr_address_codeword_q : STD_LOGIC;
signal internal_address_codeword : STD_LOGIC_VECTOR((size_codeword - 1) downto 0);
signal internal_address_message : STD_LOGIC_VECTOR((size_message - 1) downto 0);
signal internal_address_matrix : STD_LOGIC_VECTOR(((size_dyadic_matrix + size_number_dyadic_matrices) - 1) downto 0);
signal internal_codeword : STD_LOGIC;
signal internal_new_codeword : STD_LOGIC_VECTOR((number_of_accs - 1) downto 0);
signal message_added_to_codeword : STD_LOGIC;
signal partial_product : STD_LOGIC_VECTOR((number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
signal accumulated_values : STD_LOGIC_VECTOR((number_of_accs*(number_of_multipliers_per_acc+1) - 1) downto 0);
signal dyadic_matrix_address : STD_LOGIC_VECTOR(((size_dyadic_matrix)*number_of_accs*number_of_multipliers_per_acc - 1) downto 0);
begin
controller : controller_codeword_generator_2
Port Map(
clk => clk,
rst => rst,
limit_ctr_dyadic_column_q => limit_ctr_dyadic_column_q,
limit_ctr_dyadic_row_q => limit_ctr_dyadic_row_q,
limit_ctr_address_message_q => limit_ctr_address_message_q,
limit_ctr_address_codeword_q => limit_ctr_address_codeword_q,
zero_ctr_address_message_q => zero_ctr_address_message_q,
write_enable_new_codeword => write_enable_new_codeword,
external_matrix_ce => external_matrix_ce,
message_added_to_codeword => message_added_to_codeword ,
reg_codeword_ce => reg_codeword_ce,
reg_codeword_rst => reg_codeword_rst,
reg_message_ce => reg_message_ce,
reg_matrix_ce => reg_matrix_ce,
ctr_dyadic_column_ce => ctr_dyadic_column_ce,
ctr_dyadic_column_rst => ctr_dyadic_column_rst,
ctr_dyadic_row_ce => ctr_dyadic_row_ce,
ctr_dyadic_row_rst => ctr_dyadic_row_rst,
ctr_dyadic_matrices_ce => ctr_dyadic_matrices_ce,
ctr_dyadic_matrices_rst => ctr_dyadic_matrices_rst,
ctr_address_base_message_ce => ctr_address_base_message_ce,
ctr_address_base_message_rst => ctr_address_base_message_rst,
ctr_address_base_codeword_ce => ctr_address_base_codeword_ce,
ctr_address_base_codeword_rst => ctr_address_base_codeword_rst,
ctr_address_base_codeword_set => ctr_address_base_codeword_set,
internal_codeword => internal_codeword,
codeword_finalized => codeword_finalized
);
cod_accumulators : for I in 0 to (number_of_accs - 1) generate
cod_multipliers : for J in 0 to (number_of_multipliers_per_acc - 1) generate
reg_matrix_I_J : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_matrix_d((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J)),
clk => clk,
ce => reg_matrix_ce,
q => reg_matrix_q((I*number_of_multipliers_per_acc + J) downto (I*number_of_multipliers_per_acc + J))
);
dyadic_matrix_address(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix))) <= ((std_logic_vector(unsigned(ctr_dyadic_column_q)+to_unsigned(I, ctr_dyadic_column_q'length))) xor (std_logic_vector(unsigned(ctr_dyadic_row_q)+to_unsigned(J, ctr_dyadic_row_q'length)-number_of_multipliers_per_acc)));
reg_matrix_d(I*number_of_multipliers_per_acc + J) <= external_matrix_q(to_integer(unsigned(dyadic_matrix_address(((I*number_of_multipliers_per_acc + J + 1)*(size_dyadic_matrix) - 1) downto ((I*number_of_multipliers_per_acc + J)*(size_dyadic_matrix))))));
partial_product((I*number_of_multipliers_per_acc + J)) <= reg_message_q(J) and reg_matrix_q((I*number_of_multipliers_per_acc + J));
end generate;
end generate;
accumulators : for I in 0 to (number_of_accs - 1) generate
adder_I : adder_gf_2_m
Generic Map(
gf_2_m => 1,
number_of_elements => number_of_multipliers_per_acc+1
)
Port Map(
a => accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)),
o => internal_new_codeword(I downto I)
);
reg_acc_I : register_rst_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_codeword_d(I downto I),
clk => clk,
ce => reg_codeword_ce,
rst => reg_codeword_rst,
rst_value => reg_codeword_rst_value,
q => reg_codeword_q(I downto I)
);
accumulated_values(((I + 1)*(number_of_multipliers_per_acc+1) - 1) downto I*(number_of_multipliers_per_acc+1)) <= partial_product(((I + 1)*number_of_multipliers_per_acc - 1) downto I*number_of_multipliers_per_acc) & reg_codeword_q(I downto I);
end generate;
multipliers : for I in 0 to (number_of_multipliers_per_acc - 1) generate
reg_vector_I : register_nbits
Generic Map(
size => 1
)
Port Map(
d => reg_message_d(I downto I),
clk => clk,
ce => reg_message_ce,
q => reg_message_q(I downto I)
);
end generate;
external_matrix : register_nbits
Generic Map(
size => 2**size_dyadic_matrix
)
Port Map(
d => external_matrix_d,
clk => clk,
ce => external_matrix_ce,
q => external_matrix_q
);
ctr_dyadic_column : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_accs
)
Port Map(
clk => clk,
ce => ctr_dyadic_column_ce,
rst => ctr_dyadic_column_rst,
rst_value => ctr_dyadic_column_rst_value,
q => ctr_dyadic_column_q
);
ctr_dyadic_row : counter_rst_nbits
Generic Map(
size => size_dyadic_matrix,
increment_value => number_of_multipliers_per_acc
)
Port Map(
clk => clk,
ce => ctr_dyadic_row_ce,
rst => ctr_dyadic_row_rst,
rst_value => ctr_dyadic_row_rst_value,
q => ctr_dyadic_row_q
);
ctr_dyadic_matrices : counter_rst_nbits
Generic Map(
size => size_number_dyadic_matrices,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_dyadic_matrices_ce,
rst => ctr_dyadic_matrices_rst,
rst_value => ctr_dyadic_matrices_rst_value,
q => ctr_dyadic_matrices_q
);
ctr_address_base_vector : counter_rst_nbits
Generic Map(
size => size_message - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_message_ce,
rst => ctr_address_base_message_rst,
rst_value => ctr_address_base_message_rst_value,
q => ctr_address_base_message_q
);
ctr_address_base_acc : counter_rst_set_nbits
Generic Map(
size => size_codeword - size_dyadic_matrix,
increment_value => 1
)
Port Map(
clk => clk,
ce => ctr_address_base_codeword_ce,
set => ctr_address_base_codeword_set,
rst => ctr_address_base_codeword_rst,
set_value => ctr_address_base_codeword_set_value,
rst_value => ctr_address_base_codeword_rst_value,
q => ctr_address_base_codeword_q
);
external_matrix_d <= matrix;
new_codeword <= reg_message_q xor reg_codeword_q when message_added_to_codeword = '1' else
internal_new_codeword;
reg_codeword_d <= internal_new_codeword when internal_codeword = '1' else
codeword;
reg_message_d <= message;
internal_address_message <= ctr_address_base_message_q & ctr_dyadic_row_q;
internal_address_codeword <= ctr_address_base_codeword_q & ctr_dyadic_column_q;
internal_address_matrix((size_number_dyadic_matrices + size_dyadic_matrix - 1) downto size_dyadic_matrix) <= ctr_dyadic_matrices_q;
internal_address_matrix((size_dyadic_matrix - 1) downto 0) <= (others => '0');
address_codeword <= internal_address_codeword;
address_message <= internal_address_message;
address_matrix <= internal_address_matrix;
limit_ctr_dyadic_column_q <= '1' when ctr_dyadic_column_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_accs, ctr_dyadic_column_q'length)) else '0';
limit_ctr_dyadic_row_q <= '1' when ctr_dyadic_row_q = std_logic_vector(to_unsigned(2**size_dyadic_matrix - number_of_multipliers_per_acc, ctr_dyadic_row_q'length)) else '0';
limit_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(length_message - number_of_multipliers_per_acc, size_message)) else '0';
limit_ctr_address_codeword_q <= '1' when internal_address_codeword((size_codeword - 1) downto 0) = std_logic_vector(to_unsigned(length_codeword - number_of_accs, size_codeword)) else '0';
zero_ctr_address_message_q <= '1' when internal_address_message((size_message - 1) downto 0) = std_logic_vector(to_unsigned(0, size_message)) else '0';
end RTL; |
library verilog;
use verilog.vl_types.all;
entity DiceGame_controller_vlg_check_tst is
port(
Lose : in vl_logic;
Roll : in vl_logic;
Win : in vl_logic;
sampler_rx : in vl_logic
);
end DiceGame_controller_vlg_check_tst;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity maxPool_process is
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end entity;
architecture rtl of maxPool_process is
--------------------------------------------------------------------------
-- Signals
--------------------------------------------------------------------------
signal connect_data : std_logic_vector (PIXEL_SIZE - 1 downto 0);
signal connect_dv : std_logic;
signal connect_fv : std_logic;
--------------------------------------------------------------------------
-- components
--------------------------------------------------------------------------
component poolH
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
--------------------------------------------------------------------------
component poolV
generic(
PIXEL_SIZE : integer;
IMAGE_WIDTH : integer;
KERNEL_SIZE : integer
);
port(
clk : in std_logic;
reset_n : in std_logic;
enable : in std_logic;
in_data : in std_logic_vector (PIXEL_SIZE - 1 downto 0);
in_dv : in std_logic;
in_fv : in std_logic;
out_data : out std_logic_vector (PIXEL_SIZE - 1 downto 0);
out_dv : out std_logic;
out_fv : out std_logic
);
end component;
--------------------------------------------------------------------------
begin
poolV_inst : poolV
generic map (
PIXEL_SIZE => PIXEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map (
clk => clk,
reset_n => reset_n,
enable => enable,
in_data => in_data,
in_dv => in_dv,
in_fv => in_fv,
out_data => connect_data,
out_dv => connect_dv,
out_fv => connect_fv
);
------------------------------------------------------------------------
poolh_inst : poolH
generic map (
PIXEL_SIZE => PIXEL_SIZE,
KERNEL_SIZE => KERNEL_SIZE,
IMAGE_WIDTH => IMAGE_WIDTH
)
port map (
clk => clk,
reset_n => reset_n,
enable => enable,
in_data => connect_data,
in_dv => connect_dv,
in_fv => connect_fv,
out_data => out_data,
out_dv => out_dv,
out_fv => out_fv
);
end rtl;
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in T_Lcycle;
P : in std_logic_vector(7 downto 0);
LCycle : out T_Lcycle;
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
Set_Addr_To : out T_Set_Addr_To; -- PC Adder,S,AD,BA
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
signal ALUmore:std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
lCycle <= Cycle_1;
Set_BusA_To <= Set_BusA_To_ABC;
Set_Addr_To <= Set_Addr_To_PBR;
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
ALUmore <= '0';
case IR(7 downto 5) is
when "100" => -- covers $8x,$9x
case IR(1 downto 0) is
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
Set_BusA_To <= Set_BusA_To_Y;
if IR(4 downto 2)="111" then -- SYA ($9C)
Write_Data <= Write_Data_YB;
else
Write_Data <= Write_Data_Y;
end if;
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
Set_BusA_To <= Set_BusA_To_X;
if IR(4 downto 2)="111" then -- SXA ($9E)
Write_Data <= Write_Data_XB;
else
Write_Data <= Write_Data_X;
end if;
when "11" => -- IR: $83,$87,$8B,$8F,$93,$97,$9B,$9F
if IR(4 downto 2)="110" then -- SHS ($9B)
Set_BusA_To <= Set_BusA_To_AAX;
LDS <= '1';
else
Set_BusA_To <= Set_BusA_To_ABC;
end if;
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
Write_Data <= Write_Data_AXB;
else
Write_Data <= Write_Data_AX;
end if;
when others => -- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
Write_Data <= Write_Data_ABC;
end case;
when "101" => -- covers $Ax,$Bx
Set_BusA_To <= Set_BusA_To_DI;
case IR(1 downto 0) is
when "00" => -- IR: $A0,$A4,$A8,$AC,$B0,$B4,$B8,$BC
if IR(4) /= '1' or IR(2) /= '0' then--only for $A0,$A4,$A8,$AC or $B4,$BC
LDY <= '1';
end if;
when "01" => -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
LDA <= '1';
when "10" => -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
LDX <= '1';
when others => -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF (undoc)
LDX <= '1';
LDA <= '1';
if IR(4 downto 2)="110" then -- LAS (BB)
Set_BusA_To <= Set_BusA_To_S;
LDS <= '1';
end if;
end case;
when "110" => -- covers $Cx,$Dx
case IR(1 downto 0) is
when "00" => -- IR: $C0,$C4,$C8,$CC,$D0,$D4,$D8,$DC
if IR(4) = '0' then--only for $Cx
LDY <= '1';
end if;
Set_BusA_To <= Set_BusA_To_Y;
when others => -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD, $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE, $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when "111" => -- covers $Ex,$Fx
case IR(1 downto 0) is
when "00" => -- IR: $E0,$E4,$E8,$EC,$F0,$F4,$F8,$FC
if IR(4) = '0' then -- only $Ex
LDX <= '1';
end if;
Set_BusA_To <= Set_BusA_To_X;
when others => -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD, $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE, $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers $0x-$7x, $Cx-$Fx x=2,3,6,7,A,B,E,F, for 6502 undocs
if IR=x"eb" then
Set_BusA_To <= Set_BusA_To_ABC; -- alternate SBC ($EB)
else
Set_BusA_To <= Set_BusA_To_DI;
end if;
end if;
case IR(4 downto 0) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $08,$28,$48,$68,$88,$A8,$C8,$E8
-- $0A,$2A,$4A,$6A,$8A,$AA,$CA,$EA
-- $18,$38,$58,$78,$98,$B8,$D8,$F8
-- $1A,$3A,$5A,$7A,$9A,$BA,$DA,$FA
when "00000" | "01000" | "01010" | "11000" | "11010" =>
-- Implied
case IR is
when x"00" =>
-- BRK ($00)
lCycle <= Cycle_6;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_2 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_P;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
Jump <= "10";
when others =>
end case;
when x"20" => -- JSR ($20)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"40" => -- RTI ($40)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Set_BusA_To <= Set_BusA_To_DI;
when Cycle_4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"60" => -- RTS ($60)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_4 =>
Jump <= "10";
when Cycle_5 =>
Jump <= "01";
when others =>
end case;
when x"08" | x"48" | x"5a" | x"da" => -- PHP, PHA, PHY*, PHX* ($08,$48,$5A,$DA)
lCycle <= Cycle_2;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case MCycle is
when Cycle_1 =>
if mode/="00" or IR(1)='0' then --wrong on 6502
Write <= '1';
case IR(7 downto 4) is
when "0000" =>
Write_Data <= Write_Data_P;
when "0100" =>
Write_Data <= Write_Data_ABC;
when "0101" =>
if Mode /= "00" then
Write_Data <= Write_Data_Y;
else
Write <= '0';
end if;
when "1101" =>
if Mode /= "00" then
Write_Data <= Write_Data_X;
else
Write <= '0';
end if;
when others =>
end case;
Set_Addr_To <= Set_Addr_To_SP;
end if;
when Cycle_2 =>
Dec_S <= '1';
when others =>
end case;
when x"28" | x"68" | x"7a" | x"fa" => -- PLP, PLA, PLY*, PLX* ($28,$68,$7A,$FA)
lCycle <= Cycle_3;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case IR(7 downto 4) is
when "0010" =>--plp
LDP <= '1';
when "0110" =>--pla
LDA <= '1';
when "0111" =>--ply not for 6502
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>--plx not for 6502
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case MCycle is
when Cycle_sync =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
SaveP <= '1';
end if;
when Cycle_1 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
end if;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_DI;
when others =>
end case;
when x"a0" | x"c0" | x"e0" => -- LDY, CPY, CPX ($A0,$C0,$E0)
-- Immediate
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when x"88" => -- DEY ($88)
LDY <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_Y;
when others =>
end case;
when x"ca" => -- DEX ($CA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_X;
when others =>
end case;
when x"1a" | x"3a" => -- INC*, DEC* ($1A,$3A)
if Mode /= "00" then
LDA <= '1'; -- A
else
lCycle <= Cycle_1;--undoc 2 cycle nop
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"0a" | x"2a" | x"4a" | x"6a" => -- ASL, ROL, LSR, ROR ($0A,$2A,$4A,$6A)
LDA <= '1'; -- A
Set_BusA_To <= Set_BusA_To_ABC;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"8a" | x"98" => -- TYA, TXA ($8A,$98)
LDA <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"aa" | x"a8" => -- TAX, TAY ($AA,$A8)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
when x"9a" => -- TXS ($9A)
LDS <= '1'; -- will be set only in Cycle_sync
when x"ba" => -- TSX ($BA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"80" => -- undoc: NOP imm2 ($80)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when others => -- others ($0A,$EA, $18,$38,$58,$78,$B8,$C8,$D8,$E8,$F8)
case MCycle is
when Cycle_sync =>
when others =>
end case;
end case;
-- IR: $01,$21,$41,$61,$81,$A1,$C1,$E1
-- $03,$23,$43,$63,$83,$A3,$C3,$E3
when "00001" | "00011" =>
-- Zero Page Indexed Indirect (d,x)
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($01,$21,$41,$61,$C1,$E1,$03,$23,$43,$63,$C3,$E3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
BAAdd <= "01";
LDBAL <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5=>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
Write <= '1';
LDDI<='1';
end if;
when Cycle_6=>
Write <= '1';
LDALU<='1';
SaveP<='1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $09,$29,$49,$69,$89,$A9,$C9,$E9
when "01001" =>
-- Immediate
if IR(7 downto 5)/="100" then -- all except undoc. NOP imm2 (not $89)
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
-- IR: $0B,$2B,$4B,$6B,$8B,$AB,$CB,$EB
when "01011" =>
if Mode="00" then
-- Immediate undoc for 6500
case IR(7 downto 5) is
when "010"|"011"|"000"|"001" =>--ALR,ARR
Set_BusA_To<=Set_BusA_To_DA;
LDA <= '1';
when "100" =>--XAA
Set_BusA_To<=Set_BusA_To_DAX;
LDA <= '1';
when "110" =>--SAX (SBX)
Set_BusA_To<=Set_BusA_To_AAX;
LDX <= '1';
when "101" =>--OAL
Set_BusA_To<=Set_BusA_To_DAO;
LDA <= '1';
when others=>
LDA <= '1';
end case;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
end if;
-- IR: $02,$22,$42,$62,$82,$A2,$C2,$E2
-- $12,$32,$52,$72,$92,$B2,$D2,$F2
when "00010" | "10010" =>
-- Immediate, SKB, KIL
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
if IR = "10100010" then
-- LDX ($A2)
Jump <= "01";
LDX <= '1'; -- Moved, Lorenz test showed X changing on SKB (NOPx)
elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then
-- undoc: NOP imm2
Jump <= "01";
else
-- KIL !!!
end if;
when others =>
end case;
-- IR: $04,$24,$44,$64,$84,$A4,$C4,$E4
when "00100" =>
-- Zero Page
lCycle <= Cycle_2;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--24=BIT zpg
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group)
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
-- IR: $05,$25,$45,$65,$85,$A5,$C5,$E5
-- $06,$26,$46,$66,$86,$A6,$C6,$E6
-- $07,$27,$47,$67,$87,$A7,$C7,$E7
when "00101" | "00110" | "00111" =>
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
lCycle <= Cycle_4;
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
if Mode="00" and IR(0)='1' then
Set_BusA_To<=Set_BusA_To_ABC;
ALUmore <= '1'; -- For undoc DCP/DCM support
LDDI <= '1'; -- requires DIN to reflect DOUT!
end if;
when others =>
end case;
else
lCycle <= Cycle_2;
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
end if;
-- IR: $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "01100" =>
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then -- JMP ($4C,$6C)
if IR(5) = '0' then
lCycle <= Cycle_2;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
when Cycle_2 =>
Jump <= "10";
when others =>
end case;
else
lCycle <= Cycle_4;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when Cycle_2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10";
end if;
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
end if;
when Cycle_3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when Cycle_4 =>
Jump <= "10";
when others =>
end case;
end if;
else
lCycle <= Cycle_3;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--2c-BIT
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--80, sty, the only write in this group
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED
-- $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE
-- $0F,$2F,$4F,$6F,$8F,$AF,$CF,$EF
when "01101" | "01110" | "01111" =>
-- Absolute
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then -- ($0E,$2E,$4E,$6E,$CE,$EE, $0F,$2F,$4F,$6F,$CF,$EF)
-- Read-Modify-Write
lCycle <= Cycle_5;
if Mode="00" and IR(0) = '1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" then -- all but $8D, $8E, $8F, $AD, $AE, $AF ($AD does set LDA in an earlier case statement)
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--8d
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
when "10000" =>
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
lCycle <= Cycle_3; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
lCycle <= Cycle_1;
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case MCycle is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when Cycle_1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when Cycle_2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when Cycle_3 =>
when others => null; -- Do nothing.
end case;
-- IR: $11,$31,$51,$71,$91,$B1,$D1,$F1
-- $13,$33,$53,$73,$93,$B3,$D3,$F3
when "10001" | "10011" =>
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($11,$31,$51,$71,$D1,$F1,$13,$33,$53,$73,$D3,$F3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_6 =>
LDALU<='1';
SaveP<='1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To<=Set_BusA_To_ABC;
when others =>
end case;
-- IR: $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $15,$35,$55,$75,$95,$B5,$D5,$F5
-- $16,$36,$56,$76,$96,$B6,$D6,$F6
-- $17,$37,$57,$77,$97,$B7,$D7,$F7
when "10100" | "10101" | "10110" | "10111" =>
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($16,$36,$56,$76,$D6,$F6, $17,$37,$57,$77,$D7,$F7)
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then -- The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
if Mode="00" and IR(0)='1' then
LDDI<='1';
end if;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" and IR(0)='1' then -- dont LDA on undoc skip
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
-- Added this check for Y reg. use, added undocs
if (IR(3 downto 1) = "011") then -- ($16,$36,$56,$76,$96,$B6,$D6,$F6,$17,$37,$57,$77,$97,$B7,$D7,$F7)
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then -- ($14,$34,$15,$35,$16,$36,$17,$37) the only write instruction
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 => null;
when others =>
end case;
end if;
-- IR: $19,$39,$59,$79,$99,$B9,$D9,$F9
-- $1B,$3B,$5B,$7B,$9B,$BB,$DB,$FB
when "11001" | "11011" =>
-- Absolute Y
lCycle <= Cycle_4;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_6;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--99/9b
Write <= '1';
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 => -- just for undoc
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_5 =>
Write <= '1';
LDALU<='1';
Set_Addr_To <= Set_Addr_To_BA;
SaveP<='1';
when Cycle_6 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
-- $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD
-- $1E,$3E,$5E,$7E,$9E,$BE,$DE,$FE
-- $1F,$3F,$5F,$7F,$9F,$BF,$DF,$FF
when "11100" | "11101" | "11110" | "11111" =>
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($1E,$3E,$5E,$7E,$DE,$FE, $1F,$3F,$5F,$7F,$DF,$FF)
-- Read-Modify-Write
lCycle <= Cycle_6;
if Mode="00" and IR(0)='1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_X;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
end if;
when others =>
end case;
else -- ($1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC, $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD, $9E,$BE,$9F,$BF)
lCycle <= Cycle_4;--Or 3 if not page crossing
if IR(7 downto 6) /= "10" then
if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then
LDA <= '1';
end if;
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
-- special case $BE which uses Y reg as index!!
if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then
Set_BusA_To <= Set_BusA_To_Y;
else
Set_BusA_To <= Set_BusA_To_X;
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then -- ($9E,$9F)
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
when others =>
end case;
end if;
when others =>
end case;
end process;
process (IR, MCycle, Mode,ALUmore)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
case IR(4 downto 2) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $04,$24,$44,$64,$84,$A4,$C4,$E4
-- $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" => -- CP ($C0,$C4,$CC,$E0,$E4,$EC)
ALU_Op <= ALU_OP_CMP;
when "101" => -- LD ($A0,$A4,$AC)
ALU_Op <= ALU_OP_EQ2;
when "001" => -- BIT ($20,$24,$2C - $20 is ignored, as its a jmp)
ALU_Op <= ALU_OP_BIT;
when others => -- other, NOP/ST ($x0,$x4,$xC)
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $08,$28,$48,$68,$88,$A8,$C8,$E8
when "010" =>
case IR(7 downto 5) is
when "111" | "110" => -- IN ($C8,$E8)
ALU_Op <= ALU_OP_INC;
when "100" => -- DEY ($88)
ALU_Op <= ALU_OP_DEC;
when others => -- LD
ALU_Op <= ALU_OP_EQ2;
end case;
-- IR: $18,$38,$58,$78,$98,$B8,$D8,$F8
when "110" =>
case IR(7 downto 5) is
when "100" => -- TYA ($98)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
-- $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
when others =>
case IR(7 downto 5) is
when "101" => -- LD ($B0,$B4,$BC)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
end case;
when "01" => -- OR
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $01,$05,$09,$0D,$11,$15,$19,$1D
ALU_Op<=ALU_OP_OR;
when 1=> -- IR: $21,$25,$29,$2D,$31,$35,$39,$3D
ALU_Op<=ALU_OP_AND;
when 2=> -- IR: $41,$45,$49,$4D,$51,$55,$59,$5D
ALU_Op<=ALU_OP_EOR;
when 3=> -- IR: $61,$65,$69,$6D,$71,$75,$79,$7D
ALU_Op<=ALU_OP_ADC;
when 4=>-- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=> -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=> -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD
ALU_Op<=ALU_OP_CMP;
when others=> -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD
ALU_Op<=ALU_OP_SBC;
end case;
when "10" =>
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $02,$06,$0A,$0E,$12,$16,$1A,$1E
ALU_Op<=ALU_OP_ASL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00011010,$1A -> INC acc, not on 6502
ALU_Op <= ALU_OP_INC;
end if;
when 1=> -- IR: $22,$26,$2A,$2E,$32,$36,$3A,$3E
ALU_Op<=ALU_OP_ROL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00111010,$3A -> DEC acc, not on 6502
ALU_Op <= ALU_OP_DEC;
end if;
when 2=> -- IR: $42,$46,$4A,$4E,$52,$56,$5A,$5E
ALU_Op<=ALU_OP_LSR;
when 3=> -- IR: $62,$66,$6A,$6E,$72,$76,$7A,$7E
ALU_Op<=ALU_OP_ROR;
when 4=> -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
ALU_Op<=ALU_OP_BIT;
if IR(4 downto 2) = "010" then -- 10001010, $8A -> TXA
ALU_Op <= ALU_OP_EQ2;
else -- 100xxx10, $82,$86,$8E,$92,$96,$9A,$9E
ALU_Op <= ALU_OP_EQ1;
end if;
when 5=> -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=> -- IR: $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE
ALU_Op<=ALU_OP_DEC;
when others=> -- IR: $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE
ALU_Op<=ALU_OP_INC;
end case;
when others => -- "11" undoc double alu ops
case(to_integer(unsigned(IR(7 downto 5)))) is
-- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF
when 5 =>
if IR=x"bb" then--LAS
ALU_Op <= ALU_OP_AND;
else
ALU_Op <= ALU_OP_EQ2;
end if;
-- IR: $03,$07,$0B,$0F,$13,$17,$1B,$1F
-- $23,$27,$2B,$2F,$33,$37,$3B,$3F
-- $43,$47,$4B,$4F,$53,$57,$5B,$5F
-- $63,$67,$6B,$6F,$73,$77,$7B,$7F
-- $83,$87,$8B,$8F,$93,$97,$9B,$9F
-- $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
-- $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
when others =>
if IR=x"6b" then -- ARR
ALU_Op<=ALU_OP_ARR;
elsif IR=x"8b" then -- ARR
ALU_Op<=ALU_OP_XAA; -- we can't use the bit operation as we don't set all flags...
elsif IR=x"0b" or IR=x"2b" then -- ANC
ALU_Op<=ALU_OP_ANC;
elsif IR=x"eb" then -- alternate SBC
ALU_Op<=ALU_OP_SBC;
elsif ALUmore='1' then
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
else
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=>
ALU_Op<=ALU_OP_DEC;
if IR(4 downto 2)="010" then -- $6B
ALU_Op<=ALU_OP_SAX; -- special SAX (SBX) case
end if;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
end if;
end case;
end case;
end process;
end;
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in T_Lcycle;
P : in std_logic_vector(7 downto 0);
LCycle : out T_Lcycle;
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
Set_Addr_To : out T_Set_Addr_To; -- PC Adder,S,AD,BA
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
signal ALUmore:std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
lCycle <= Cycle_1;
Set_BusA_To <= Set_BusA_To_ABC;
Set_Addr_To <= Set_Addr_To_PBR;
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
ALUmore <= '0';
case IR(7 downto 5) is
when "100" => -- covers $8x,$9x
case IR(1 downto 0) is
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
Set_BusA_To <= Set_BusA_To_Y;
if IR(4 downto 2)="111" then -- SYA ($9C)
Write_Data <= Write_Data_YB;
else
Write_Data <= Write_Data_Y;
end if;
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
Set_BusA_To <= Set_BusA_To_X;
if IR(4 downto 2)="111" then -- SXA ($9E)
Write_Data <= Write_Data_XB;
else
Write_Data <= Write_Data_X;
end if;
when "11" => -- IR: $83,$87,$8B,$8F,$93,$97,$9B,$9F
if IR(4 downto 2)="110" then -- SHS ($9B)
Set_BusA_To <= Set_BusA_To_AAX;
LDS <= '1';
else
Set_BusA_To <= Set_BusA_To_ABC;
end if;
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
Write_Data <= Write_Data_AXB;
else
Write_Data <= Write_Data_AX;
end if;
when others => -- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
Write_Data <= Write_Data_ABC;
end case;
when "101" => -- covers $Ax,$Bx
Set_BusA_To <= Set_BusA_To_DI;
case IR(1 downto 0) is
when "00" => -- IR: $A0,$A4,$A8,$AC,$B0,$B4,$B8,$BC
if IR(4) /= '1' or IR(2) /= '0' then--only for $A0,$A4,$A8,$AC or $B4,$BC
LDY <= '1';
end if;
when "01" => -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
LDA <= '1';
when "10" => -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
LDX <= '1';
when others => -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF (undoc)
LDX <= '1';
LDA <= '1';
if IR(4 downto 2)="110" then -- LAS (BB)
Set_BusA_To <= Set_BusA_To_S;
LDS <= '1';
end if;
end case;
when "110" => -- covers $Cx,$Dx
case IR(1 downto 0) is
when "00" => -- IR: $C0,$C4,$C8,$CC,$D0,$D4,$D8,$DC
if IR(4) = '0' then--only for $Cx
LDY <= '1';
end if;
Set_BusA_To <= Set_BusA_To_Y;
when others => -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD, $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE, $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when "111" => -- covers $Ex,$Fx
case IR(1 downto 0) is
when "00" => -- IR: $E0,$E4,$E8,$EC,$F0,$F4,$F8,$FC
if IR(4) = '0' then -- only $Ex
LDX <= '1';
end if;
Set_BusA_To <= Set_BusA_To_X;
when others => -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD, $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE, $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers $0x-$7x, $Cx-$Fx x=2,3,6,7,A,B,E,F, for 6502 undocs
if IR=x"eb" then
Set_BusA_To <= Set_BusA_To_ABC; -- alternate SBC ($EB)
else
Set_BusA_To <= Set_BusA_To_DI;
end if;
end if;
case IR(4 downto 0) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $08,$28,$48,$68,$88,$A8,$C8,$E8
-- $0A,$2A,$4A,$6A,$8A,$AA,$CA,$EA
-- $18,$38,$58,$78,$98,$B8,$D8,$F8
-- $1A,$3A,$5A,$7A,$9A,$BA,$DA,$FA
when "00000" | "01000" | "01010" | "11000" | "11010" =>
-- Implied
case IR is
when x"00" =>
-- BRK ($00)
lCycle <= Cycle_6;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_2 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_P;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
Jump <= "10";
when others =>
end case;
when x"20" => -- JSR ($20)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"40" => -- RTI ($40)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Set_BusA_To <= Set_BusA_To_DI;
when Cycle_4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"60" => -- RTS ($60)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_4 =>
Jump <= "10";
when Cycle_5 =>
Jump <= "01";
when others =>
end case;
when x"08" | x"48" | x"5a" | x"da" => -- PHP, PHA, PHY*, PHX* ($08,$48,$5A,$DA)
lCycle <= Cycle_2;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case MCycle is
when Cycle_1 =>
if mode/="00" or IR(1)='0' then --wrong on 6502
Write <= '1';
case IR(7 downto 4) is
when "0000" =>
Write_Data <= Write_Data_P;
when "0100" =>
Write_Data <= Write_Data_ABC;
when "0101" =>
if Mode /= "00" then
Write_Data <= Write_Data_Y;
else
Write <= '0';
end if;
when "1101" =>
if Mode /= "00" then
Write_Data <= Write_Data_X;
else
Write <= '0';
end if;
when others =>
end case;
Set_Addr_To <= Set_Addr_To_SP;
end if;
when Cycle_2 =>
Dec_S <= '1';
when others =>
end case;
when x"28" | x"68" | x"7a" | x"fa" => -- PLP, PLA, PLY*, PLX* ($28,$68,$7A,$FA)
lCycle <= Cycle_3;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case IR(7 downto 4) is
when "0010" =>--plp
LDP <= '1';
when "0110" =>--pla
LDA <= '1';
when "0111" =>--ply not for 6502
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>--plx not for 6502
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case MCycle is
when Cycle_sync =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
SaveP <= '1';
end if;
when Cycle_1 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
end if;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_DI;
when others =>
end case;
when x"a0" | x"c0" | x"e0" => -- LDY, CPY, CPX ($A0,$C0,$E0)
-- Immediate
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when x"88" => -- DEY ($88)
LDY <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_Y;
when others =>
end case;
when x"ca" => -- DEX ($CA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_X;
when others =>
end case;
when x"1a" | x"3a" => -- INC*, DEC* ($1A,$3A)
if Mode /= "00" then
LDA <= '1'; -- A
else
lCycle <= Cycle_1;--undoc 2 cycle nop
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"0a" | x"2a" | x"4a" | x"6a" => -- ASL, ROL, LSR, ROR ($0A,$2A,$4A,$6A)
LDA <= '1'; -- A
Set_BusA_To <= Set_BusA_To_ABC;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"8a" | x"98" => -- TYA, TXA ($8A,$98)
LDA <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"aa" | x"a8" => -- TAX, TAY ($AA,$A8)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
when x"9a" => -- TXS ($9A)
LDS <= '1'; -- will be set only in Cycle_sync
when x"ba" => -- TSX ($BA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"80" => -- undoc: NOP imm2 ($80)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when others => -- others ($0A,$EA, $18,$38,$58,$78,$B8,$C8,$D8,$E8,$F8)
case MCycle is
when Cycle_sync =>
when others =>
end case;
end case;
-- IR: $01,$21,$41,$61,$81,$A1,$C1,$E1
-- $03,$23,$43,$63,$83,$A3,$C3,$E3
when "00001" | "00011" =>
-- Zero Page Indexed Indirect (d,x)
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($01,$21,$41,$61,$C1,$E1,$03,$23,$43,$63,$C3,$E3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
BAAdd <= "01";
LDBAL <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5=>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
Write <= '1';
LDDI<='1';
end if;
when Cycle_6=>
Write <= '1';
LDALU<='1';
SaveP<='1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $09,$29,$49,$69,$89,$A9,$C9,$E9
when "01001" =>
-- Immediate
if IR(7 downto 5)/="100" then -- all except undoc. NOP imm2 (not $89)
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
-- IR: $0B,$2B,$4B,$6B,$8B,$AB,$CB,$EB
when "01011" =>
if Mode="00" then
-- Immediate undoc for 6500
case IR(7 downto 5) is
when "010"|"011"|"000"|"001" =>--ALR,ARR
Set_BusA_To<=Set_BusA_To_DA;
LDA <= '1';
when "100" =>--XAA
Set_BusA_To<=Set_BusA_To_DAX;
LDA <= '1';
when "110" =>--SAX (SBX)
Set_BusA_To<=Set_BusA_To_AAX;
LDX <= '1';
when "101" =>--OAL
Set_BusA_To<=Set_BusA_To_DAO;
LDA <= '1';
when others=>
LDA <= '1';
end case;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
end if;
-- IR: $02,$22,$42,$62,$82,$A2,$C2,$E2
-- $12,$32,$52,$72,$92,$B2,$D2,$F2
when "00010" | "10010" =>
-- Immediate, SKB, KIL
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
if IR = "10100010" then
-- LDX ($A2)
Jump <= "01";
LDX <= '1'; -- Moved, Lorenz test showed X changing on SKB (NOPx)
elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then
-- undoc: NOP imm2
Jump <= "01";
else
-- KIL !!!
end if;
when others =>
end case;
-- IR: $04,$24,$44,$64,$84,$A4,$C4,$E4
when "00100" =>
-- Zero Page
lCycle <= Cycle_2;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--24=BIT zpg
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group)
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
-- IR: $05,$25,$45,$65,$85,$A5,$C5,$E5
-- $06,$26,$46,$66,$86,$A6,$C6,$E6
-- $07,$27,$47,$67,$87,$A7,$C7,$E7
when "00101" | "00110" | "00111" =>
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
lCycle <= Cycle_4;
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
if Mode="00" and IR(0)='1' then
Set_BusA_To<=Set_BusA_To_ABC;
ALUmore <= '1'; -- For undoc DCP/DCM support
LDDI <= '1'; -- requires DIN to reflect DOUT!
end if;
when others =>
end case;
else
lCycle <= Cycle_2;
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
end if;
-- IR: $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "01100" =>
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then -- JMP ($4C,$6C)
if IR(5) = '0' then
lCycle <= Cycle_2;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
when Cycle_2 =>
Jump <= "10";
when others =>
end case;
else
lCycle <= Cycle_4;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when Cycle_2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10";
end if;
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
end if;
when Cycle_3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when Cycle_4 =>
Jump <= "10";
when others =>
end case;
end if;
else
lCycle <= Cycle_3;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--2c-BIT
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--80, sty, the only write in this group
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED
-- $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE
-- $0F,$2F,$4F,$6F,$8F,$AF,$CF,$EF
when "01101" | "01110" | "01111" =>
-- Absolute
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then -- ($0E,$2E,$4E,$6E,$CE,$EE, $0F,$2F,$4F,$6F,$CF,$EF)
-- Read-Modify-Write
lCycle <= Cycle_5;
if Mode="00" and IR(0) = '1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" then -- all but $8D, $8E, $8F, $AD, $AE, $AF ($AD does set LDA in an earlier case statement)
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--8d
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
when "10000" =>
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
lCycle <= Cycle_3; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
lCycle <= Cycle_1;
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case MCycle is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when Cycle_1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when Cycle_2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when Cycle_3 =>
when others => null; -- Do nothing.
end case;
-- IR: $11,$31,$51,$71,$91,$B1,$D1,$F1
-- $13,$33,$53,$73,$93,$B3,$D3,$F3
when "10001" | "10011" =>
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($11,$31,$51,$71,$D1,$F1,$13,$33,$53,$73,$D3,$F3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_6 =>
LDALU<='1';
SaveP<='1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To<=Set_BusA_To_ABC;
when others =>
end case;
-- IR: $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $15,$35,$55,$75,$95,$B5,$D5,$F5
-- $16,$36,$56,$76,$96,$B6,$D6,$F6
-- $17,$37,$57,$77,$97,$B7,$D7,$F7
when "10100" | "10101" | "10110" | "10111" =>
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($16,$36,$56,$76,$D6,$F6, $17,$37,$57,$77,$D7,$F7)
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then -- The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
if Mode="00" and IR(0)='1' then
LDDI<='1';
end if;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" and IR(0)='1' then -- dont LDA on undoc skip
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
-- Added this check for Y reg. use, added undocs
if (IR(3 downto 1) = "011") then -- ($16,$36,$56,$76,$96,$B6,$D6,$F6,$17,$37,$57,$77,$97,$B7,$D7,$F7)
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then -- ($14,$34,$15,$35,$16,$36,$17,$37) the only write instruction
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 => null;
when others =>
end case;
end if;
-- IR: $19,$39,$59,$79,$99,$B9,$D9,$F9
-- $1B,$3B,$5B,$7B,$9B,$BB,$DB,$FB
when "11001" | "11011" =>
-- Absolute Y
lCycle <= Cycle_4;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_6;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--99/9b
Write <= '1';
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 => -- just for undoc
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_5 =>
Write <= '1';
LDALU<='1';
Set_Addr_To <= Set_Addr_To_BA;
SaveP<='1';
when Cycle_6 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
-- $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD
-- $1E,$3E,$5E,$7E,$9E,$BE,$DE,$FE
-- $1F,$3F,$5F,$7F,$9F,$BF,$DF,$FF
when "11100" | "11101" | "11110" | "11111" =>
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($1E,$3E,$5E,$7E,$DE,$FE, $1F,$3F,$5F,$7F,$DF,$FF)
-- Read-Modify-Write
lCycle <= Cycle_6;
if Mode="00" and IR(0)='1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_X;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
end if;
when others =>
end case;
else -- ($1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC, $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD, $9E,$BE,$9F,$BF)
lCycle <= Cycle_4;--Or 3 if not page crossing
if IR(7 downto 6) /= "10" then
if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then
LDA <= '1';
end if;
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
-- special case $BE which uses Y reg as index!!
if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then
Set_BusA_To <= Set_BusA_To_Y;
else
Set_BusA_To <= Set_BusA_To_X;
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then -- ($9E,$9F)
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
when others =>
end case;
end if;
when others =>
end case;
end process;
process (IR, MCycle, Mode,ALUmore)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
case IR(4 downto 2) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $04,$24,$44,$64,$84,$A4,$C4,$E4
-- $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" => -- CP ($C0,$C4,$CC,$E0,$E4,$EC)
ALU_Op <= ALU_OP_CMP;
when "101" => -- LD ($A0,$A4,$AC)
ALU_Op <= ALU_OP_EQ2;
when "001" => -- BIT ($20,$24,$2C - $20 is ignored, as its a jmp)
ALU_Op <= ALU_OP_BIT;
when others => -- other, NOP/ST ($x0,$x4,$xC)
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $08,$28,$48,$68,$88,$A8,$C8,$E8
when "010" =>
case IR(7 downto 5) is
when "111" | "110" => -- IN ($C8,$E8)
ALU_Op <= ALU_OP_INC;
when "100" => -- DEY ($88)
ALU_Op <= ALU_OP_DEC;
when others => -- LD
ALU_Op <= ALU_OP_EQ2;
end case;
-- IR: $18,$38,$58,$78,$98,$B8,$D8,$F8
when "110" =>
case IR(7 downto 5) is
when "100" => -- TYA ($98)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
-- $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
when others =>
case IR(7 downto 5) is
when "101" => -- LD ($B0,$B4,$BC)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
end case;
when "01" => -- OR
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $01,$05,$09,$0D,$11,$15,$19,$1D
ALU_Op<=ALU_OP_OR;
when 1=> -- IR: $21,$25,$29,$2D,$31,$35,$39,$3D
ALU_Op<=ALU_OP_AND;
when 2=> -- IR: $41,$45,$49,$4D,$51,$55,$59,$5D
ALU_Op<=ALU_OP_EOR;
when 3=> -- IR: $61,$65,$69,$6D,$71,$75,$79,$7D
ALU_Op<=ALU_OP_ADC;
when 4=>-- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=> -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=> -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD
ALU_Op<=ALU_OP_CMP;
when others=> -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD
ALU_Op<=ALU_OP_SBC;
end case;
when "10" =>
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $02,$06,$0A,$0E,$12,$16,$1A,$1E
ALU_Op<=ALU_OP_ASL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00011010,$1A -> INC acc, not on 6502
ALU_Op <= ALU_OP_INC;
end if;
when 1=> -- IR: $22,$26,$2A,$2E,$32,$36,$3A,$3E
ALU_Op<=ALU_OP_ROL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00111010,$3A -> DEC acc, not on 6502
ALU_Op <= ALU_OP_DEC;
end if;
when 2=> -- IR: $42,$46,$4A,$4E,$52,$56,$5A,$5E
ALU_Op<=ALU_OP_LSR;
when 3=> -- IR: $62,$66,$6A,$6E,$72,$76,$7A,$7E
ALU_Op<=ALU_OP_ROR;
when 4=> -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
ALU_Op<=ALU_OP_BIT;
if IR(4 downto 2) = "010" then -- 10001010, $8A -> TXA
ALU_Op <= ALU_OP_EQ2;
else -- 100xxx10, $82,$86,$8E,$92,$96,$9A,$9E
ALU_Op <= ALU_OP_EQ1;
end if;
when 5=> -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=> -- IR: $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE
ALU_Op<=ALU_OP_DEC;
when others=> -- IR: $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE
ALU_Op<=ALU_OP_INC;
end case;
when others => -- "11" undoc double alu ops
case(to_integer(unsigned(IR(7 downto 5)))) is
-- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF
when 5 =>
if IR=x"bb" then--LAS
ALU_Op <= ALU_OP_AND;
else
ALU_Op <= ALU_OP_EQ2;
end if;
-- IR: $03,$07,$0B,$0F,$13,$17,$1B,$1F
-- $23,$27,$2B,$2F,$33,$37,$3B,$3F
-- $43,$47,$4B,$4F,$53,$57,$5B,$5F
-- $63,$67,$6B,$6F,$73,$77,$7B,$7F
-- $83,$87,$8B,$8F,$93,$97,$9B,$9F
-- $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
-- $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
when others =>
if IR=x"6b" then -- ARR
ALU_Op<=ALU_OP_ARR;
elsif IR=x"8b" then -- ARR
ALU_Op<=ALU_OP_XAA; -- we can't use the bit operation as we don't set all flags...
elsif IR=x"0b" or IR=x"2b" then -- ANC
ALU_Op<=ALU_OP_ANC;
elsif IR=x"eb" then -- alternate SBC
ALU_Op<=ALU_OP_SBC;
elsif ALUmore='1' then
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
else
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=>
ALU_Op<=ALU_OP_DEC;
if IR(4 downto 2)="010" then -- $6B
ALU_Op<=ALU_OP_SAX; -- special SAX (SBX) case
end if;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
end if;
end case;
end case;
end process;
end;
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in T_Lcycle;
P : in std_logic_vector(7 downto 0);
LCycle : out T_Lcycle;
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
Set_Addr_To : out T_Set_Addr_To; -- PC Adder,S,AD,BA
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
signal ALUmore:std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
lCycle <= Cycle_1;
Set_BusA_To <= Set_BusA_To_ABC;
Set_Addr_To <= Set_Addr_To_PBR;
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
ALUmore <= '0';
case IR(7 downto 5) is
when "100" => -- covers $8x,$9x
case IR(1 downto 0) is
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
Set_BusA_To <= Set_BusA_To_Y;
if IR(4 downto 2)="111" then -- SYA ($9C)
Write_Data <= Write_Data_YB;
else
Write_Data <= Write_Data_Y;
end if;
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
Set_BusA_To <= Set_BusA_To_X;
if IR(4 downto 2)="111" then -- SXA ($9E)
Write_Data <= Write_Data_XB;
else
Write_Data <= Write_Data_X;
end if;
when "11" => -- IR: $83,$87,$8B,$8F,$93,$97,$9B,$9F
if IR(4 downto 2)="110" then -- SHS ($9B)
Set_BusA_To <= Set_BusA_To_AAX;
LDS <= '1';
else
Set_BusA_To <= Set_BusA_To_ABC;
end if;
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
Write_Data <= Write_Data_AXB;
else
Write_Data <= Write_Data_AX;
end if;
when others => -- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
Write_Data <= Write_Data_ABC;
end case;
when "101" => -- covers $Ax,$Bx
Set_BusA_To <= Set_BusA_To_DI;
case IR(1 downto 0) is
when "00" => -- IR: $A0,$A4,$A8,$AC,$B0,$B4,$B8,$BC
if IR(4) /= '1' or IR(2) /= '0' then--only for $A0,$A4,$A8,$AC or $B4,$BC
LDY <= '1';
end if;
when "01" => -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
LDA <= '1';
when "10" => -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
LDX <= '1';
when others => -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF (undoc)
LDX <= '1';
LDA <= '1';
if IR(4 downto 2)="110" then -- LAS (BB)
Set_BusA_To <= Set_BusA_To_S;
LDS <= '1';
end if;
end case;
when "110" => -- covers $Cx,$Dx
case IR(1 downto 0) is
when "00" => -- IR: $C0,$C4,$C8,$CC,$D0,$D4,$D8,$DC
if IR(4) = '0' then--only for $Cx
LDY <= '1';
end if;
Set_BusA_To <= Set_BusA_To_Y;
when others => -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD, $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE, $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when "111" => -- covers $Ex,$Fx
case IR(1 downto 0) is
when "00" => -- IR: $E0,$E4,$E8,$EC,$F0,$F4,$F8,$FC
if IR(4) = '0' then -- only $Ex
LDX <= '1';
end if;
Set_BusA_To <= Set_BusA_To_X;
when others => -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD, $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE, $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers $0x-$7x, $Cx-$Fx x=2,3,6,7,A,B,E,F, for 6502 undocs
if IR=x"eb" then
Set_BusA_To <= Set_BusA_To_ABC; -- alternate SBC ($EB)
else
Set_BusA_To <= Set_BusA_To_DI;
end if;
end if;
case IR(4 downto 0) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $08,$28,$48,$68,$88,$A8,$C8,$E8
-- $0A,$2A,$4A,$6A,$8A,$AA,$CA,$EA
-- $18,$38,$58,$78,$98,$B8,$D8,$F8
-- $1A,$3A,$5A,$7A,$9A,$BA,$DA,$FA
when "00000" | "01000" | "01010" | "11000" | "11010" =>
-- Implied
case IR is
when x"00" =>
-- BRK ($00)
lCycle <= Cycle_6;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_2 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_P;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
Jump <= "10";
when others =>
end case;
when x"20" => -- JSR ($20)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"40" => -- RTI ($40)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Set_BusA_To <= Set_BusA_To_DI;
when Cycle_4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"60" => -- RTS ($60)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_4 =>
Jump <= "10";
when Cycle_5 =>
Jump <= "01";
when others =>
end case;
when x"08" | x"48" | x"5a" | x"da" => -- PHP, PHA, PHY*, PHX* ($08,$48,$5A,$DA)
lCycle <= Cycle_2;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case MCycle is
when Cycle_1 =>
if mode/="00" or IR(1)='0' then --wrong on 6502
Write <= '1';
case IR(7 downto 4) is
when "0000" =>
Write_Data <= Write_Data_P;
when "0100" =>
Write_Data <= Write_Data_ABC;
when "0101" =>
if Mode /= "00" then
Write_Data <= Write_Data_Y;
else
Write <= '0';
end if;
when "1101" =>
if Mode /= "00" then
Write_Data <= Write_Data_X;
else
Write <= '0';
end if;
when others =>
end case;
Set_Addr_To <= Set_Addr_To_SP;
end if;
when Cycle_2 =>
Dec_S <= '1';
when others =>
end case;
when x"28" | x"68" | x"7a" | x"fa" => -- PLP, PLA, PLY*, PLX* ($28,$68,$7A,$FA)
lCycle <= Cycle_3;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case IR(7 downto 4) is
when "0010" =>--plp
LDP <= '1';
when "0110" =>--pla
LDA <= '1';
when "0111" =>--ply not for 6502
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>--plx not for 6502
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case MCycle is
when Cycle_sync =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
SaveP <= '1';
end if;
when Cycle_1 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
end if;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_DI;
when others =>
end case;
when x"a0" | x"c0" | x"e0" => -- LDY, CPY, CPX ($A0,$C0,$E0)
-- Immediate
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when x"88" => -- DEY ($88)
LDY <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_Y;
when others =>
end case;
when x"ca" => -- DEX ($CA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_X;
when others =>
end case;
when x"1a" | x"3a" => -- INC*, DEC* ($1A,$3A)
if Mode /= "00" then
LDA <= '1'; -- A
else
lCycle <= Cycle_1;--undoc 2 cycle nop
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"0a" | x"2a" | x"4a" | x"6a" => -- ASL, ROL, LSR, ROR ($0A,$2A,$4A,$6A)
LDA <= '1'; -- A
Set_BusA_To <= Set_BusA_To_ABC;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"8a" | x"98" => -- TYA, TXA ($8A,$98)
LDA <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"aa" | x"a8" => -- TAX, TAY ($AA,$A8)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
when x"9a" => -- TXS ($9A)
LDS <= '1'; -- will be set only in Cycle_sync
when x"ba" => -- TSX ($BA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"80" => -- undoc: NOP imm2 ($80)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when others => -- others ($0A,$EA, $18,$38,$58,$78,$B8,$C8,$D8,$E8,$F8)
case MCycle is
when Cycle_sync =>
when others =>
end case;
end case;
-- IR: $01,$21,$41,$61,$81,$A1,$C1,$E1
-- $03,$23,$43,$63,$83,$A3,$C3,$E3
when "00001" | "00011" =>
-- Zero Page Indexed Indirect (d,x)
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($01,$21,$41,$61,$C1,$E1,$03,$23,$43,$63,$C3,$E3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
BAAdd <= "01";
LDBAL <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5=>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
Write <= '1';
LDDI<='1';
end if;
when Cycle_6=>
Write <= '1';
LDALU<='1';
SaveP<='1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $09,$29,$49,$69,$89,$A9,$C9,$E9
when "01001" =>
-- Immediate
if IR(7 downto 5)/="100" then -- all except undoc. NOP imm2 (not $89)
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
-- IR: $0B,$2B,$4B,$6B,$8B,$AB,$CB,$EB
when "01011" =>
if Mode="00" then
-- Immediate undoc for 6500
case IR(7 downto 5) is
when "010"|"011"|"000"|"001" =>--ALR,ARR
Set_BusA_To<=Set_BusA_To_DA;
LDA <= '1';
when "100" =>--XAA
Set_BusA_To<=Set_BusA_To_DAX;
LDA <= '1';
when "110" =>--SAX (SBX)
Set_BusA_To<=Set_BusA_To_AAX;
LDX <= '1';
when "101" =>--OAL
Set_BusA_To<=Set_BusA_To_DAO;
LDA <= '1';
when others=>
LDA <= '1';
end case;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
end if;
-- IR: $02,$22,$42,$62,$82,$A2,$C2,$E2
-- $12,$32,$52,$72,$92,$B2,$D2,$F2
when "00010" | "10010" =>
-- Immediate, SKB, KIL
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
if IR = "10100010" then
-- LDX ($A2)
Jump <= "01";
LDX <= '1'; -- Moved, Lorenz test showed X changing on SKB (NOPx)
elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then
-- undoc: NOP imm2
Jump <= "01";
else
-- KIL !!!
end if;
when others =>
end case;
-- IR: $04,$24,$44,$64,$84,$A4,$C4,$E4
when "00100" =>
-- Zero Page
lCycle <= Cycle_2;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--24=BIT zpg
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group)
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
-- IR: $05,$25,$45,$65,$85,$A5,$C5,$E5
-- $06,$26,$46,$66,$86,$A6,$C6,$E6
-- $07,$27,$47,$67,$87,$A7,$C7,$E7
when "00101" | "00110" | "00111" =>
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
lCycle <= Cycle_4;
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
if Mode="00" and IR(0)='1' then
Set_BusA_To<=Set_BusA_To_ABC;
ALUmore <= '1'; -- For undoc DCP/DCM support
LDDI <= '1'; -- requires DIN to reflect DOUT!
end if;
when others =>
end case;
else
lCycle <= Cycle_2;
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
end if;
-- IR: $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "01100" =>
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then -- JMP ($4C,$6C)
if IR(5) = '0' then
lCycle <= Cycle_2;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
when Cycle_2 =>
Jump <= "10";
when others =>
end case;
else
lCycle <= Cycle_4;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when Cycle_2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10";
end if;
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
end if;
when Cycle_3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when Cycle_4 =>
Jump <= "10";
when others =>
end case;
end if;
else
lCycle <= Cycle_3;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--2c-BIT
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--80, sty, the only write in this group
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED
-- $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE
-- $0F,$2F,$4F,$6F,$8F,$AF,$CF,$EF
when "01101" | "01110" | "01111" =>
-- Absolute
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then -- ($0E,$2E,$4E,$6E,$CE,$EE, $0F,$2F,$4F,$6F,$CF,$EF)
-- Read-Modify-Write
lCycle <= Cycle_5;
if Mode="00" and IR(0) = '1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" then -- all but $8D, $8E, $8F, $AD, $AE, $AF ($AD does set LDA in an earlier case statement)
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--8d
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
when "10000" =>
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
lCycle <= Cycle_3; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
lCycle <= Cycle_1;
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case MCycle is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when Cycle_1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when Cycle_2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when Cycle_3 =>
when others => null; -- Do nothing.
end case;
-- IR: $11,$31,$51,$71,$91,$B1,$D1,$F1
-- $13,$33,$53,$73,$93,$B3,$D3,$F3
when "10001" | "10011" =>
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($11,$31,$51,$71,$D1,$F1,$13,$33,$53,$73,$D3,$F3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_6 =>
LDALU<='1';
SaveP<='1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To<=Set_BusA_To_ABC;
when others =>
end case;
-- IR: $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $15,$35,$55,$75,$95,$B5,$D5,$F5
-- $16,$36,$56,$76,$96,$B6,$D6,$F6
-- $17,$37,$57,$77,$97,$B7,$D7,$F7
when "10100" | "10101" | "10110" | "10111" =>
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($16,$36,$56,$76,$D6,$F6, $17,$37,$57,$77,$D7,$F7)
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then -- The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
if Mode="00" and IR(0)='1' then
LDDI<='1';
end if;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" and IR(0)='1' then -- dont LDA on undoc skip
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
-- Added this check for Y reg. use, added undocs
if (IR(3 downto 1) = "011") then -- ($16,$36,$56,$76,$96,$B6,$D6,$F6,$17,$37,$57,$77,$97,$B7,$D7,$F7)
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then -- ($14,$34,$15,$35,$16,$36,$17,$37) the only write instruction
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 => null;
when others =>
end case;
end if;
-- IR: $19,$39,$59,$79,$99,$B9,$D9,$F9
-- $1B,$3B,$5B,$7B,$9B,$BB,$DB,$FB
when "11001" | "11011" =>
-- Absolute Y
lCycle <= Cycle_4;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_6;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--99/9b
Write <= '1';
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 => -- just for undoc
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_5 =>
Write <= '1';
LDALU<='1';
Set_Addr_To <= Set_Addr_To_BA;
SaveP<='1';
when Cycle_6 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
-- $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD
-- $1E,$3E,$5E,$7E,$9E,$BE,$DE,$FE
-- $1F,$3F,$5F,$7F,$9F,$BF,$DF,$FF
when "11100" | "11101" | "11110" | "11111" =>
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($1E,$3E,$5E,$7E,$DE,$FE, $1F,$3F,$5F,$7F,$DF,$FF)
-- Read-Modify-Write
lCycle <= Cycle_6;
if Mode="00" and IR(0)='1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_X;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
end if;
when others =>
end case;
else -- ($1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC, $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD, $9E,$BE,$9F,$BF)
lCycle <= Cycle_4;--Or 3 if not page crossing
if IR(7 downto 6) /= "10" then
if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then
LDA <= '1';
end if;
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
-- special case $BE which uses Y reg as index!!
if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then
Set_BusA_To <= Set_BusA_To_Y;
else
Set_BusA_To <= Set_BusA_To_X;
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then -- ($9E,$9F)
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
when others =>
end case;
end if;
when others =>
end case;
end process;
process (IR, MCycle, Mode,ALUmore)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
case IR(4 downto 2) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $04,$24,$44,$64,$84,$A4,$C4,$E4
-- $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" => -- CP ($C0,$C4,$CC,$E0,$E4,$EC)
ALU_Op <= ALU_OP_CMP;
when "101" => -- LD ($A0,$A4,$AC)
ALU_Op <= ALU_OP_EQ2;
when "001" => -- BIT ($20,$24,$2C - $20 is ignored, as its a jmp)
ALU_Op <= ALU_OP_BIT;
when others => -- other, NOP/ST ($x0,$x4,$xC)
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $08,$28,$48,$68,$88,$A8,$C8,$E8
when "010" =>
case IR(7 downto 5) is
when "111" | "110" => -- IN ($C8,$E8)
ALU_Op <= ALU_OP_INC;
when "100" => -- DEY ($88)
ALU_Op <= ALU_OP_DEC;
when others => -- LD
ALU_Op <= ALU_OP_EQ2;
end case;
-- IR: $18,$38,$58,$78,$98,$B8,$D8,$F8
when "110" =>
case IR(7 downto 5) is
when "100" => -- TYA ($98)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
-- $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
when others =>
case IR(7 downto 5) is
when "101" => -- LD ($B0,$B4,$BC)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
end case;
when "01" => -- OR
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $01,$05,$09,$0D,$11,$15,$19,$1D
ALU_Op<=ALU_OP_OR;
when 1=> -- IR: $21,$25,$29,$2D,$31,$35,$39,$3D
ALU_Op<=ALU_OP_AND;
when 2=> -- IR: $41,$45,$49,$4D,$51,$55,$59,$5D
ALU_Op<=ALU_OP_EOR;
when 3=> -- IR: $61,$65,$69,$6D,$71,$75,$79,$7D
ALU_Op<=ALU_OP_ADC;
when 4=>-- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=> -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=> -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD
ALU_Op<=ALU_OP_CMP;
when others=> -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD
ALU_Op<=ALU_OP_SBC;
end case;
when "10" =>
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $02,$06,$0A,$0E,$12,$16,$1A,$1E
ALU_Op<=ALU_OP_ASL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00011010,$1A -> INC acc, not on 6502
ALU_Op <= ALU_OP_INC;
end if;
when 1=> -- IR: $22,$26,$2A,$2E,$32,$36,$3A,$3E
ALU_Op<=ALU_OP_ROL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00111010,$3A -> DEC acc, not on 6502
ALU_Op <= ALU_OP_DEC;
end if;
when 2=> -- IR: $42,$46,$4A,$4E,$52,$56,$5A,$5E
ALU_Op<=ALU_OP_LSR;
when 3=> -- IR: $62,$66,$6A,$6E,$72,$76,$7A,$7E
ALU_Op<=ALU_OP_ROR;
when 4=> -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
ALU_Op<=ALU_OP_BIT;
if IR(4 downto 2) = "010" then -- 10001010, $8A -> TXA
ALU_Op <= ALU_OP_EQ2;
else -- 100xxx10, $82,$86,$8E,$92,$96,$9A,$9E
ALU_Op <= ALU_OP_EQ1;
end if;
when 5=> -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=> -- IR: $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE
ALU_Op<=ALU_OP_DEC;
when others=> -- IR: $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE
ALU_Op<=ALU_OP_INC;
end case;
when others => -- "11" undoc double alu ops
case(to_integer(unsigned(IR(7 downto 5)))) is
-- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF
when 5 =>
if IR=x"bb" then--LAS
ALU_Op <= ALU_OP_AND;
else
ALU_Op <= ALU_OP_EQ2;
end if;
-- IR: $03,$07,$0B,$0F,$13,$17,$1B,$1F
-- $23,$27,$2B,$2F,$33,$37,$3B,$3F
-- $43,$47,$4B,$4F,$53,$57,$5B,$5F
-- $63,$67,$6B,$6F,$73,$77,$7B,$7F
-- $83,$87,$8B,$8F,$93,$97,$9B,$9F
-- $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
-- $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
when others =>
if IR=x"6b" then -- ARR
ALU_Op<=ALU_OP_ARR;
elsif IR=x"8b" then -- ARR
ALU_Op<=ALU_OP_XAA; -- we can't use the bit operation as we don't set all flags...
elsif IR=x"0b" or IR=x"2b" then -- ANC
ALU_Op<=ALU_OP_ANC;
elsif IR=x"eb" then -- alternate SBC
ALU_Op<=ALU_OP_SBC;
elsif ALUmore='1' then
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
else
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=>
ALU_Op<=ALU_OP_DEC;
if IR(4 downto 2)="010" then -- $6B
ALU_Op<=ALU_OP_SAX; -- special SAX (SBX) case
end if;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
end if;
end case;
end case;
end process;
end;
|
-- ****
-- T65(b) core. In an effort to merge and maintain bug fixes ....
--
-- See list of changes in T65 top file (T65.vhd)...
--
-- ****
-- 65xx compatible microprocessor core
--
-- FPGAARCADE SVN: $Id: T65_MCode.vhd 1234 2015-02-28 20:14:50Z wolfgang.scherr $
--
-- Copyright (c) 2002...2015
-- Daniel Wallner (jesus <at> opencores <dot> org)
-- Mike Johnson (mikej <at> fpgaarcade <dot> com)
-- Wolfgang Scherr (WoS <at> pin4 <dot> at>
-- Morten Leikvoll ()
--
-- All rights reserved
--
-- Redistribution and use in source and synthezised forms, with or without
-- modification, are permitted provided that the following conditions are met:
--
-- Redistributions of source code must retain the above copyright notice,
-- this list of conditions and the following disclaimer.
--
-- Redistributions in synthesized form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- Neither the name of the author nor the names of other contributors may
-- be used to endorse or promote products derived from this software without
-- specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
-- THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
-- PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE
-- LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-- CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-- SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-- INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-- CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-- ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Please report bugs to the author(s), but before you do so, please
-- make sure that this is not a derivative work and that
-- you have the latest version of this file.
--
-- Limitations :
-- See in T65 top file (T65.vhd)...
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
use work.T65_Pack.all;
entity T65_MCode is
port(
Mode : in std_logic_vector(1 downto 0); -- "00" => 6502, "01" => 65C02, "10" => 65816
IR : in std_logic_vector(7 downto 0);
MCycle : in T_Lcycle;
P : in std_logic_vector(7 downto 0);
LCycle : out T_Lcycle;
ALU_Op : out T_ALU_Op;
Set_BusA_To : out T_Set_BusA_To; -- DI,A,X,Y,S,P,DA,DAO,DAX,AAX
Set_Addr_To : out T_Set_Addr_To; -- PC Adder,S,AD,BA
Write_Data : out T_Write_Data; -- DL,A,X,Y,S,P,PCL,PCH,AX,AXB,XB,YB
Jump : out std_logic_vector(1 downto 0); -- PC,++,DIDL,Rel
BAAdd : out std_logic_vector(1 downto 0); -- None,DB Inc,BA Add,BA Adj
BreakAtNA : out std_logic;
ADAdd : out std_logic;
AddY : out std_logic;
PCAdd : out std_logic;
Inc_S : out std_logic;
Dec_S : out std_logic;
LDA : out std_logic;
LDP : out std_logic;
LDX : out std_logic;
LDY : out std_logic;
LDS : out std_logic;
LDDI : out std_logic;
LDALU : out std_logic;
LDAD : out std_logic;
LDBAL : out std_logic;
LDBAH : out std_logic;
SaveP : out std_logic;
Write : out std_logic
);
end T65_MCode;
architecture rtl of T65_MCode is
signal Branch : std_logic;
signal ALUmore:std_logic;
begin
with IR(7 downto 5) select
Branch <= not P(Flag_N) when "000",
P(Flag_N) when "001",
not P(Flag_V) when "010",
P(Flag_V) when "011",
not P(Flag_C) when "100",
P(Flag_C) when "101",
not P(Flag_Z) when "110",
P(Flag_Z) when others;
process (IR, MCycle, P, Branch, Mode)
begin
lCycle <= Cycle_1;
Set_BusA_To <= Set_BusA_To_ABC;
Set_Addr_To <= Set_Addr_To_PBR;
Write_Data <= Write_Data_DL;
Jump <= (others => '0');
BAAdd <= "00";
BreakAtNA <= '0';
ADAdd <= '0';
PCAdd <= '0';
Inc_S <= '0';
Dec_S <= '0';
LDA <= '0';
LDP <= '0';
LDX <= '0';
LDY <= '0';
LDS <= '0';
LDDI <= '0';
LDALU <= '0';
LDAD <= '0';
LDBAL <= '0';
LDBAH <= '0';
SaveP <= '0';
Write <= '0';
AddY <= '0';
ALUmore <= '0';
case IR(7 downto 5) is
when "100" => -- covers $8x,$9x
case IR(1 downto 0) is
when "00" => -- IR: $80,$84,$88,$8C,$90,$94,$98,$9C
Set_BusA_To <= Set_BusA_To_Y;
if IR(4 downto 2)="111" then -- SYA ($9C)
Write_Data <= Write_Data_YB;
else
Write_Data <= Write_Data_Y;
end if;
when "10" => -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
Set_BusA_To <= Set_BusA_To_X;
if IR(4 downto 2)="111" then -- SXA ($9E)
Write_Data <= Write_Data_XB;
else
Write_Data <= Write_Data_X;
end if;
when "11" => -- IR: $83,$87,$8B,$8F,$93,$97,$9B,$9F
if IR(4 downto 2)="110" then -- SHS ($9B)
Set_BusA_To <= Set_BusA_To_AAX;
LDS <= '1';
else
Set_BusA_To <= Set_BusA_To_ABC;
end if;
if IR(4 downto 2)="111" or IR(4 downto 2)="110" or IR(4 downto 2)="100" then -- SHA ($9F, $93), SHS ($9B)
Write_Data <= Write_Data_AXB;
else
Write_Data <= Write_Data_AX;
end if;
when others => -- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
Write_Data <= Write_Data_ABC;
end case;
when "101" => -- covers $Ax,$Bx
Set_BusA_To <= Set_BusA_To_DI;
case IR(1 downto 0) is
when "00" => -- IR: $A0,$A4,$A8,$AC,$B0,$B4,$B8,$BC
if IR(4) /= '1' or IR(2) /= '0' then--only for $A0,$A4,$A8,$AC or $B4,$BC
LDY <= '1';
end if;
when "01" => -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
LDA <= '1';
when "10" => -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
LDX <= '1';
when others => -- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF (undoc)
LDX <= '1';
LDA <= '1';
if IR(4 downto 2)="110" then -- LAS (BB)
Set_BusA_To <= Set_BusA_To_S;
LDS <= '1';
end if;
end case;
when "110" => -- covers $Cx,$Dx
case IR(1 downto 0) is
when "00" => -- IR: $C0,$C4,$C8,$CC,$D0,$D4,$D8,$DC
if IR(4) = '0' then--only for $Cx
LDY <= '1';
end if;
Set_BusA_To <= Set_BusA_To_Y;
when others => -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD, $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE, $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when "111" => -- covers $Ex,$Fx
case IR(1 downto 0) is
when "00" => -- IR: $E0,$E4,$E8,$EC,$F0,$F4,$F8,$FC
if IR(4) = '0' then -- only $Ex
LDX <= '1';
end if;
Set_BusA_To <= Set_BusA_To_X;
when others => -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD, $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE, $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
Set_BusA_To <= Set_BusA_To_ABC;
end case;
when others =>
end case;
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers $0x-$7x, $Cx-$Fx x=2,3,6,7,A,B,E,F, for 6502 undocs
if IR=x"eb" then
Set_BusA_To <= Set_BusA_To_ABC; -- alternate SBC ($EB)
else
Set_BusA_To <= Set_BusA_To_DI;
end if;
end if;
case IR(4 downto 0) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $08,$28,$48,$68,$88,$A8,$C8,$E8
-- $0A,$2A,$4A,$6A,$8A,$AA,$CA,$EA
-- $18,$38,$58,$78,$98,$B8,$D8,$F8
-- $1A,$3A,$5A,$7A,$9A,$BA,$DA,$FA
when "00000" | "01000" | "01010" | "11000" | "11010" =>
-- Implied
case IR is
when x"00" =>
-- BRK ($00)
lCycle <= Cycle_6;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_2 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_P;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
Jump <= "10";
when others =>
end case;
when x"20" => -- JSR ($20)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCH;
Write <= '1';
when Cycle_3 =>
Dec_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Write_Data <= Write_Data_PCL;
Write <= '1';
when Cycle_4 =>
Dec_S <= '1';
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"40" => -- RTI ($40)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
Set_BusA_To <= Set_BusA_To_DI;
when Cycle_4 =>
LDP <= '1';
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_5 =>
Jump <= "10";
when others =>
end case;
when x"60" => -- RTS ($60)
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_3 =>
Inc_S <= '1';
LDDI <= '1';
Set_Addr_To <= Set_Addr_To_SP;
when Cycle_4 =>
Jump <= "10";
when Cycle_5 =>
Jump <= "01";
when others =>
end case;
when x"08" | x"48" | x"5a" | x"da" => -- PHP, PHA, PHY*, PHX* ($08,$48,$5A,$DA)
lCycle <= Cycle_2;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case MCycle is
when Cycle_1 =>
if mode/="00" or IR(1)='0' then --wrong on 6502
Write <= '1';
case IR(7 downto 4) is
when "0000" =>
Write_Data <= Write_Data_P;
when "0100" =>
Write_Data <= Write_Data_ABC;
when "0101" =>
if Mode /= "00" then
Write_Data <= Write_Data_Y;
else
Write <= '0';
end if;
when "1101" =>
if Mode /= "00" then
Write_Data <= Write_Data_X;
else
Write <= '0';
end if;
when others =>
end case;
Set_Addr_To <= Set_Addr_To_SP;
end if;
when Cycle_2 =>
Dec_S <= '1';
when others =>
end case;
when x"28" | x"68" | x"7a" | x"fa" => -- PLP, PLA, PLY*, PLX* ($28,$68,$7A,$FA)
lCycle <= Cycle_3;
if Mode = "00" and IR(1) = '1' then--2 cycle nop
lCycle <= Cycle_1;
end if;
case IR(7 downto 4) is
when "0010" =>--plp
LDP <= '1';
when "0110" =>--pla
LDA <= '1';
when "0111" =>--ply not for 6502
if Mode /= "00" then
LDY <= '1';
end if;
when "1111" =>--plx not for 6502
if Mode /= "00" then
LDX <= '1';
end if;
when others =>
end case;
case MCycle is
when Cycle_sync =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
SaveP <= '1';
end if;
when Cycle_1 =>
if Mode /= "00" or IR(1) = '0' then--wrong on 6502
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
end if;
when Cycle_2 =>
Inc_S <= '1';
Set_Addr_To <= Set_Addr_To_SP;
LDP <= '0';
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_DI;
when others =>
end case;
when x"a0" | x"c0" | x"e0" => -- LDY, CPY, CPX ($A0,$C0,$E0)
-- Immediate
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when x"88" => -- DEY ($88)
LDY <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_Y;
when others =>
end case;
when x"ca" => -- DEX ($CA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_X;
when others =>
end case;
when x"1a" | x"3a" => -- INC*, DEC* ($1A,$3A)
if Mode /= "00" then
LDA <= '1'; -- A
else
lCycle <= Cycle_1;--undoc 2 cycle nop
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"0a" | x"2a" | x"4a" | x"6a" => -- ASL, ROL, LSR, ROR ($0A,$2A,$4A,$6A)
LDA <= '1'; -- A
Set_BusA_To <= Set_BusA_To_ABC;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"8a" | x"98" => -- TYA, TXA ($8A,$98)
LDA <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
when others =>
end case;
when x"aa" | x"a8" => -- TAX, TAY ($AA,$A8)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
when x"9a" => -- TXS ($9A)
LDS <= '1'; -- will be set only in Cycle_sync
when x"ba" => -- TSX ($BA)
LDX <= '1';
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Set_BusA_To <= Set_BusA_To_S;
when others =>
end case;
when x"80" => -- undoc: NOP imm2 ($80)
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
when others => -- others ($0A,$EA, $18,$38,$58,$78,$B8,$C8,$D8,$E8,$F8)
case MCycle is
when Cycle_sync =>
when others =>
end case;
end case;
-- IR: $01,$21,$41,$61,$81,$A1,$C1,$E1
-- $03,$23,$43,$63,$83,$A3,$C3,$E3
when "00001" | "00011" =>
-- Zero Page Indexed Indirect (d,x)
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($01,$21,$41,$61,$C1,$E1,$03,$23,$43,$63,$C3,$E3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
BAAdd <= "01";
LDBAL <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDBAH <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5=>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
Write <= '1';
LDDI<='1';
end if;
when Cycle_6=>
Write <= '1';
LDALU<='1';
SaveP<='1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $09,$29,$49,$69,$89,$A9,$C9,$E9
when "01001" =>
-- Immediate
if IR(7 downto 5)/="100" then -- all except undoc. NOP imm2 (not $89)
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
-- IR: $0B,$2B,$4B,$6B,$8B,$AB,$CB,$EB
when "01011" =>
if Mode="00" then
-- Immediate undoc for 6500
case IR(7 downto 5) is
when "010"|"011"|"000"|"001" =>--ALR,ARR
Set_BusA_To<=Set_BusA_To_DA;
LDA <= '1';
when "100" =>--XAA
Set_BusA_To<=Set_BusA_To_DAX;
LDA <= '1';
when "110" =>--SAX (SBX)
Set_BusA_To<=Set_BusA_To_AAX;
LDX <= '1';
when "101" =>--OAL
Set_BusA_To<=Set_BusA_To_DAO;
LDA <= '1';
when others=>
LDA <= '1';
end case;
case MCycle is
when Cycle_1 =>
Jump <= "01";
when others =>
end case;
end if;
-- IR: $02,$22,$42,$62,$82,$A2,$C2,$E2
-- $12,$32,$52,$72,$92,$B2,$D2,$F2
when "00010" | "10010" =>
-- Immediate, SKB, KIL
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
if IR = "10100010" then
-- LDX ($A2)
Jump <= "01";
LDX <= '1'; -- Moved, Lorenz test showed X changing on SKB (NOPx)
elsif IR(7 downto 4)="1000" or IR(7 downto 4)="1100" or IR(7 downto 4)="1110" then
-- undoc: NOP imm2
Jump <= "01";
else
-- KIL !!!
end if;
when others =>
end case;
-- IR: $04,$24,$44,$64,$84,$A4,$C4,$E4
when "00100" =>
-- Zero Page
lCycle <= Cycle_2;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--24=BIT zpg
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then--84=sty zpg (the only write in this group)
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
-- IR: $05,$25,$45,$65,$85,$A5,$C5,$E5
-- $06,$26,$46,$66,$86,$A6,$C6,$E6
-- $07,$27,$47,$67,$87,$A7,$C7,$E7
when "00101" | "00110" | "00111" =>
-- Zero Page
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then--covers 0x-7x,cx-fx x=2,3,6,7,a,b,e,f, for 6502 undocs
-- Read-Modify-Write
lCycle <= Cycle_4;
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
if Mode="00" and IR(0)='1' then
Set_BusA_To<=Set_BusA_To_ABC;
ALUmore <= '1'; -- For undoc DCP/DCM support
LDDI <= '1'; -- requires DIN to reflect DOUT!
end if;
when others =>
end case;
else
lCycle <= Cycle_2;
if IR(7 downto 6) /= "10" then
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
if IR(7 downto 5) = "100" then
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
when others =>
end case;
end if;
-- IR: $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "01100" =>
-- Absolute
if IR(7 downto 6) = "01" and IR(4 downto 0) = "01100" then -- JMP ($4C,$6C)
if IR(5) = '0' then
lCycle <= Cycle_2;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
when Cycle_2 =>
Jump <= "10";
when others =>
end case;
else
lCycle <= Cycle_4;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDDI <= '1';
LDBAL <= '1';
when Cycle_2 =>
LDBAH <= '1';
if Mode /= "00" then
Jump <= "10";
end if;
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
end if;
when Cycle_3 =>
LDDI <= '1';
if Mode = "00" then
Set_Addr_To <= Set_Addr_To_BA;
BAAdd <= "01"; -- DB Inc
else
Jump <= "01";
end if;
when Cycle_4 =>
Jump <= "10";
when others =>
end case;
end if;
else
lCycle <= Cycle_3;
case MCycle is
when Cycle_sync =>
if IR(7 downto 5) = "001" then--2c-BIT
SaveP <= '1';
end if;
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--80, sty, the only write in this group
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $0D,$2D,$4D,$6D,$8D,$AD,$CD,$ED
-- $0E,$2E,$4E,$6E,$8E,$AE,$CE,$EE
-- $0F,$2F,$4F,$6F,$8F,$AF,$CF,$EF
when "01101" | "01110" | "01111" =>
-- Absolute
if IR(7 downto 6) /= "10" and IR(1) = '1' and (mode="00" or IR(0)='0') then -- ($0E,$2E,$4E,$6E,$CE,$EE, $0F,$2F,$4F,$6F,$CF,$EF)
-- Read-Modify-Write
lCycle <= Cycle_5;
if Mode="00" and IR(0) = '1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
Write <= '1';
LDALU <= '1';
SaveP <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" then -- all but $8D, $8E, $8F, $AD, $AE, $AF ($AD does set LDA in an earlier case statement)
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
LDBAH <= '1';
if IR(7 downto 5) = "100" then--8d
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
when others =>
end case;
end if;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
when "10000" =>
-- Relative
-- This circuit dictates when the last
-- microcycle occurs for the branch depending on
-- whether or not the branch is taken and if a page
-- is crossed...
if (Branch = '1') then
lCycle <= Cycle_3; -- We're done @ T3 if branching...upper
-- level logic will stop at T2 if no page cross
-- (See the Break signal)
else
lCycle <= Cycle_1;
end if;
-- This decodes the current microcycle and takes the
-- proper course of action...
case MCycle is
-- On the T1 microcycle, increment the program counter
-- and instruct the upper level logic to fetch the offset
-- from the Din bus and store it in the data latches. This
-- will be the last microcycle if the branch isn't taken.
when Cycle_1 =>
Jump <= "01"; -- Increments the PC by one (PC will now be PC+2)
-- from microcycle T0.
LDDI <= '1'; -- Tells logic in top level (T65.vhd) to route
-- the Din bus to the memory data latch (DL)
-- so that the branch offset is fetched.
-- In microcycle T2, tell the logic in the top level to
-- add the offset. If the most significant byte of the
-- program counter (i.e. the current "page") does not need
-- updating, we are done here...the Break signal at the
-- T65.vhd level takes care of that...
when Cycle_2 =>
Jump <= "11"; -- Tell the PC Jump logic to use relative mode.
PCAdd <= '1'; -- This tells the PC adder to update itself with
-- the current offset recently fetched from
-- memory.
-- The following is microcycle T3 :
-- The program counter should be completely updated
-- on this cycle after the page cross is detected.
-- We don't need to do anything here...
when Cycle_3 =>
when others => null; -- Do nothing.
end case;
-- IR: $11,$31,$51,$71,$91,$B1,$D1,$F1
-- $13,$33,$53,$73,$93,$B3,$D3,$F3
when "10001" | "10011" =>
lCycle <= Cycle_5;
if IR(7 downto 6) /= "10" then -- ($11,$31,$51,$71,$D1,$F1,$13,$33,$53,$73,$D3,$F3)
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_7;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
LDBAL <= '1';
BAAdd <= "01"; -- DB Inc
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
BAAdd <= "11"; -- BA Adj
if IR(7 downto 5) = "100" then
Write <= '1';
elsif IR(1)='0' or IR=x"B3" then -- Dont do this on $x3, except undoc LAXiy $B3 (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_6 =>
LDALU<='1';
SaveP<='1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_7 =>
ALUmore <= '1';
Set_BusA_To<=Set_BusA_To_ABC;
when others =>
end case;
-- IR: $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $15,$35,$55,$75,$95,$B5,$D5,$F5
-- $16,$36,$56,$76,$96,$B6,$D6,$F6
-- $17,$37,$57,$77,$97,$B7,$D7,$F7
when "10100" | "10101" | "10110" | "10111" =>
-- Zero Page, X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($16,$36,$56,$76,$D6,$F6, $17,$37,$57,$77,$D7,$F7)
-- Read-Modify-Write
if Mode="00" and IR(0)='1' then
LDA<='1';
end if;
lCycle <= Cycle_5;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 =>
LDDI <= '1';
if Mode="00" then -- The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_4 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
if Mode="00" and IR(0)='1' then
LDDI<='1';
end if;
when Cycle_5 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1'; -- For undoc DCP/DCM support
Set_BusA_To<=Set_BusA_To_ABC;
end if;
when others =>
end case;
else
lCycle <= Cycle_3;
if IR(7 downto 6) /= "10" and IR(0)='1' then -- dont LDA on undoc skip
LDA <= '1';
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDAD <= '1';
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_2 =>
ADAdd <= '1';
-- Added this check for Y reg. use, added undocs
if (IR(3 downto 1) = "011") then -- ($16,$36,$56,$76,$96,$B6,$D6,$F6,$17,$37,$57,$77,$97,$B7,$D7,$F7)
AddY <= '1';
end if;
if IR(7 downto 5) = "100" then -- ($14,$34,$15,$35,$16,$36,$17,$37) the only write instruction
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_ZPG;
when Cycle_3 => null;
when others =>
end case;
end if;
-- IR: $19,$39,$59,$79,$99,$B9,$D9,$F9
-- $1B,$3B,$5B,$7B,$9B,$BB,$DB,$FB
when "11001" | "11011" =>
-- Absolute Y
lCycle <= Cycle_4;
if IR(7 downto 6) /= "10" then
LDA <= '1';
if Mode="00" and IR(1)='1' then
lCycle <= Cycle_6;
end if;
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_Y;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then--99/9b
Write <= '1';
elsif IR(1)='0' or IR=x"BB" then -- Dont do this on $xB, except undoc $BB (says real CPU and Lorenz tests)
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 => -- just for undoc
if Mode="00" and IR(1)='1' and IR(7 downto 6)/="10" then
Set_Addr_To <= Set_Addr_To_BA;
LDDI<='1';
Write <= '1';
end if;
when Cycle_5 =>
Write <= '1';
LDALU<='1';
Set_Addr_To <= Set_Addr_To_BA;
SaveP<='1';
when Cycle_6 =>
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
when others =>
end case;
-- IR: $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
-- $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD
-- $1E,$3E,$5E,$7E,$9E,$BE,$DE,$FE
-- $1F,$3F,$5F,$7F,$9F,$BF,$DF,$FF
when "11100" | "11101" | "11110" | "11111" =>
-- Absolute X
if IR(7 downto 6) /= "10" and IR(1) = '1' and (Mode="00" or IR(0)='0') then -- ($1E,$3E,$5E,$7E,$DE,$FE, $1F,$3F,$5F,$7F,$DF,$FF)
-- Read-Modify-Write
lCycle <= Cycle_6;
if Mode="00" and IR(0)='1' then
LDA <= '1';
end if;
case MCycle is
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
Set_BusA_To <= Set_BusA_To_X;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
LDDI <= '1';
if Mode="00" then--The old 6500 writes back what is just read, before changing. The 65c does another read
Write <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_5 =>
LDALU <= '1';
SaveP <= '1';
Write <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_6 =>
if Mode="00" and IR(0)='1' then
ALUmore <= '1';
Set_BusA_To <= Set_BusA_To_ABC;
end if;
when others =>
end case;
else -- ($1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC, $1D,$3D,$5D,$7D,$9D,$BD,$DD,$FD, $9E,$BE,$9F,$BF)
lCycle <= Cycle_4;--Or 3 if not page crossing
if IR(7 downto 6) /= "10" then
if Mode/="00" or IR(4)='0' or IR(1 downto 0)/="00" then
LDA <= '1';
end if;
end if;
case MCycle is
when Cycle_sync =>
when Cycle_1 =>
Jump <= "01";
LDBAL <= '1';
when Cycle_2 =>
Jump <= "01";
-- special case $BE which uses Y reg as index!!
if(IR(7 downto 6)="10" and IR(4 downto 1)="1111") then
Set_BusA_To <= Set_BusA_To_Y;
else
Set_BusA_To <= Set_BusA_To_X;
end if;
BAAdd <= "10"; -- BA Add
LDBAH <= '1';
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_3 =>
BAAdd <= "11"; -- BA adj
if IR(7 downto 5) = "100" then -- ($9E,$9F)
Write <= '1';
else
BreakAtNA <= '1';
end if;
Set_Addr_To <= Set_Addr_To_BA;
when Cycle_4 =>
when others =>
end case;
end if;
when others =>
end case;
end process;
process (IR, MCycle, Mode,ALUmore)
begin
-- ORA, AND, EOR, ADC, NOP, LD, CMP, SBC
-- ASL, ROL, LSR, ROR, BIT, LD, DEC, INC
case IR(1 downto 0) is
when "00" =>
case IR(4 downto 2) is
-- IR: $00,$20,$40,$60,$80,$A0,$C0,$E0
-- $04,$24,$44,$64,$84,$A4,$C4,$E4
-- $0C,$2C,$4C,$6C,$8C,$AC,$CC,$EC
when "000" | "001" | "011" =>
case IR(7 downto 5) is
when "110" | "111" => -- CP ($C0,$C4,$CC,$E0,$E4,$EC)
ALU_Op <= ALU_OP_CMP;
when "101" => -- LD ($A0,$A4,$AC)
ALU_Op <= ALU_OP_EQ2;
when "001" => -- BIT ($20,$24,$2C - $20 is ignored, as its a jmp)
ALU_Op <= ALU_OP_BIT;
when others => -- other, NOP/ST ($x0,$x4,$xC)
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $08,$28,$48,$68,$88,$A8,$C8,$E8
when "010" =>
case IR(7 downto 5) is
when "111" | "110" => -- IN ($C8,$E8)
ALU_Op <= ALU_OP_INC;
when "100" => -- DEY ($88)
ALU_Op <= ALU_OP_DEC;
when others => -- LD
ALU_Op <= ALU_OP_EQ2;
end case;
-- IR: $18,$38,$58,$78,$98,$B8,$D8,$F8
when "110" =>
case IR(7 downto 5) is
when "100" => -- TYA ($98)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
-- IR: $10,$30,$50,$70,$90,$B0,$D0,$F0
-- $14,$34,$54,$74,$94,$B4,$D4,$F4
-- $1C,$3C,$5C,$7C,$9C,$BC,$DC,$FC
when others =>
case IR(7 downto 5) is
when "101" => -- LD ($B0,$B4,$BC)
ALU_Op <= ALU_OP_EQ2;
when others =>
ALU_Op <= ALU_OP_EQ1;
end case;
end case;
when "01" => -- OR
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $01,$05,$09,$0D,$11,$15,$19,$1D
ALU_Op<=ALU_OP_OR;
when 1=> -- IR: $21,$25,$29,$2D,$31,$35,$39,$3D
ALU_Op<=ALU_OP_AND;
when 2=> -- IR: $41,$45,$49,$4D,$51,$55,$59,$5D
ALU_Op<=ALU_OP_EOR;
when 3=> -- IR: $61,$65,$69,$6D,$71,$75,$79,$7D
ALU_Op<=ALU_OP_ADC;
when 4=>-- IR: $81,$85,$89,$8D,$91,$95,$99,$9D
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=> -- IR: $A1,$A5,$A9,$AD,$B1,$B5,$B9,$BD
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=> -- IR: $C1,$C5,$C9,$CD,$D1,$D5,$D9,$DD
ALU_Op<=ALU_OP_CMP;
when others=> -- IR: $E1,$E5,$E9,$ED,$F1,$F5,$F9,$FD
ALU_Op<=ALU_OP_SBC;
end case;
when "10" =>
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=> -- IR: $02,$06,$0A,$0E,$12,$16,$1A,$1E
ALU_Op<=ALU_OP_ASL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00011010,$1A -> INC acc, not on 6502
ALU_Op <= ALU_OP_INC;
end if;
when 1=> -- IR: $22,$26,$2A,$2E,$32,$36,$3A,$3E
ALU_Op<=ALU_OP_ROL;
if IR(4 downto 2) = "110" and Mode/="00" then -- 00111010,$3A -> DEC acc, not on 6502
ALU_Op <= ALU_OP_DEC;
end if;
when 2=> -- IR: $42,$46,$4A,$4E,$52,$56,$5A,$5E
ALU_Op<=ALU_OP_LSR;
when 3=> -- IR: $62,$66,$6A,$6E,$72,$76,$7A,$7E
ALU_Op<=ALU_OP_ROR;
when 4=> -- IR: $82,$86,$8A,$8E,$92,$96,$9A,$9E
ALU_Op<=ALU_OP_BIT;
if IR(4 downto 2) = "010" then -- 10001010, $8A -> TXA
ALU_Op <= ALU_OP_EQ2;
else -- 100xxx10, $82,$86,$8E,$92,$96,$9A,$9E
ALU_Op <= ALU_OP_EQ1;
end if;
when 5=> -- IR: $A2,$A6,$AA,$AE,$B2,$B6,$BA,$BE
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=> -- IR: $C2,$C6,$CA,$CE,$D2,$D6,$DA,$DE
ALU_Op<=ALU_OP_DEC;
when others=> -- IR: $E2,$E6,$EA,$EE,$F2,$F6,$FA,$FE
ALU_Op<=ALU_OP_INC;
end case;
when others => -- "11" undoc double alu ops
case(to_integer(unsigned(IR(7 downto 5)))) is
-- IR: $A3,$A7,$AB,$AF,$B3,$B7,$BB,$BF
when 5 =>
if IR=x"bb" then--LAS
ALU_Op <= ALU_OP_AND;
else
ALU_Op <= ALU_OP_EQ2;
end if;
-- IR: $03,$07,$0B,$0F,$13,$17,$1B,$1F
-- $23,$27,$2B,$2F,$33,$37,$3B,$3F
-- $43,$47,$4B,$4F,$53,$57,$5B,$5F
-- $63,$67,$6B,$6F,$73,$77,$7B,$7F
-- $83,$87,$8B,$8F,$93,$97,$9B,$9F
-- $C3,$C7,$CB,$CF,$D3,$D7,$DB,$DF
-- $E3,$E7,$EB,$EF,$F3,$F7,$FB,$FF
when others =>
if IR=x"6b" then -- ARR
ALU_Op<=ALU_OP_ARR;
elsif IR=x"8b" then -- ARR
ALU_Op<=ALU_OP_XAA; -- we can't use the bit operation as we don't set all flags...
elsif IR=x"0b" or IR=x"2b" then -- ANC
ALU_Op<=ALU_OP_ANC;
elsif IR=x"eb" then -- alternate SBC
ALU_Op<=ALU_OP_SBC;
elsif ALUmore='1' then
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_OR;
when 1=>
ALU_Op<=ALU_OP_AND;
when 2=>
ALU_Op<=ALU_OP_EOR;
when 3=>
ALU_Op<=ALU_OP_ADC;
when 4=>
ALU_Op<=ALU_OP_EQ1; -- STA
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDA
when 6=>
ALU_Op<=ALU_OP_CMP;
when others=>
ALU_Op<=ALU_OP_SBC;
end case;
else
case(to_integer(unsigned(IR(7 downto 5)))) is
when 0=>
ALU_Op<=ALU_OP_ASL;
when 1=>
ALU_Op<=ALU_OP_ROL;
when 2=>
ALU_Op<=ALU_OP_LSR;
when 3=>
ALU_Op<=ALU_OP_ROR;
when 4=>
ALU_Op<=ALU_OP_BIT;
when 5=>
ALU_Op<=ALU_OP_EQ2; -- LDX
when 6=>
ALU_Op<=ALU_OP_DEC;
if IR(4 downto 2)="010" then -- $6B
ALU_Op<=ALU_OP_SAX; -- special SAX (SBX) case
end if;
when others=>
ALU_Op<=ALU_OP_INC;
end case;
end if;
end case;
end case;
end process;
end;
|
-- $Id: sys_conf_sim.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2018-2019 by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_w11a_br_as7 (for simulation)
--
-- Dependencies: -
-- Tool versions: viv 2017.2-2018.3; ghdl 0.34-0.35
-- Revision History:
-- Date Rev Version Comment
-- 2019-04-28 1142 1.1.1 add sys_conf_ibd_m9312
-- 2019-02-09 1110 1.1 use typ for DL,PC,LP; add dz11,ibtst
-- 2018-09-22 1050 1.0.2 add sys_conf_dmpcnt
-- 2018-09-08 1043 1.0.1 add sys_conf_ibd_kw11p
-- 2018-08-11 1038 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
-- configure clocks --------------------------------------------------------
constant sys_conf_clksys_vcodivide : positive := 1;
constant sys_conf_clksys_vcomultiply : positive := 8; -- vco 800 MHz
constant sys_conf_clksys_outdivide : positive := 10; -- sys 80 MHz
constant sys_conf_clksys_gentype : string := "MMCM";
-- dual clock design, clkser = 120 MHz
constant sys_conf_clkser_vcodivide : positive := 1;
constant sys_conf_clkser_vcomultiply : positive := 12; -- vco 1200 MHz
constant sys_conf_clkser_outdivide : positive := 10; -- sys 120 MHz
constant sys_conf_clkser_gentype : string := "PLL";
-- configure rlink and hio interfaces --------------------------------------
constant sys_conf_ser2rri_cdinit : integer := 1-1; -- 1 cycle/bit in sim
constant sys_conf_hio_debounce : boolean := false; -- no debouncers
-- configure memory controller ---------------------------------------------
constant sys_conf_memctl_mawidth : positive := 4;
constant sys_conf_memctl_nblock : positive := 16;
-- configure debug and monitoring units ------------------------------------
constant sys_conf_rbmon_awidth : integer := 0; -- no rbmon to save BRAMs
constant sys_conf_ibmon_awidth : integer := 0; -- no ibmon to save BRAMs
constant sys_conf_ibtst : boolean := true;
constant sys_conf_dmscnt : boolean := false;
constant sys_conf_dmpcnt : boolean := true;
constant sys_conf_dmhbpt_nunit : integer := 2; -- use 0 to disable
constant sys_conf_dmcmon_awidth : integer := 0; -- no dmcmon to save BRAMs
constant sys_conf_rbd_sysmon : boolean := true; -- SYSMON(XADC)
-- configure w11 cpu core --------------------------------------------------
-- sys_conf_mem_losize is highest 64 byte MMU block number
-- the bram_memcnt uses 4*4kB memory blocks => 1 MEM block = 256 MMU blocks
constant sys_conf_mem_losize : natural := 256*sys_conf_memctl_nblock-1;
constant sys_conf_cache_fmiss : slbit := '0'; -- cache enabled
constant sys_conf_cache_twidth : integer := 9; -- 8kB cache
-- configure w11 system devices --------------------------------------------
-- configure character and communication devices
-- typ for DL,DZ,PC,LP: -1->none; 0->unbuffered; 4-7 buffered (typ=AWIDTH)
constant sys_conf_ibd_dl11_0 : integer := 6; -- 1st DL11
constant sys_conf_ibd_dl11_1 : integer := 6; -- 2nd DL11
constant sys_conf_ibd_dz11 : integer := 6; -- DZ11
constant sys_conf_ibd_pc11 : integer := 6; -- PC11
constant sys_conf_ibd_lp11 : integer := 7; -- LP11
constant sys_conf_ibd_deuna : boolean := true; -- DEUNA
-- configure mass storage devices
constant sys_conf_ibd_rk11 : boolean := true; -- RK11
constant sys_conf_ibd_rl11 : boolean := true; -- RL11
constant sys_conf_ibd_rhrp : boolean := true; -- RHRP
constant sys_conf_ibd_tm11 : boolean := true; -- TM11
-- configure other devices
constant sys_conf_ibd_iist : boolean := true; -- IIST
constant sys_conf_ibd_kw11p : boolean := true; -- KW11P
constant sys_conf_ibd_m9312 : boolean := true; -- M9312
-- derived constants =======================================================
constant sys_conf_clksys : integer :=
((100000000/sys_conf_clksys_vcodivide)*sys_conf_clksys_vcomultiply) /
sys_conf_clksys_outdivide;
constant sys_conf_clksys_mhz : integer := sys_conf_clksys/1000000;
constant sys_conf_clkser : integer :=
((100000000/sys_conf_clkser_vcodivide)*sys_conf_clkser_vcomultiply) /
sys_conf_clkser_outdivide;
constant sys_conf_clkser_mhz : integer := sys_conf_clkser/1000000;
end package sys_conf;
|
library verilog;
use verilog.vl_types.all;
entity altera_avalon_mm_clock_crossing_bridge is
generic(
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH: integer := 1;
COMMAND_FIFO_DEPTH: integer := 4;
RESPONSE_FIFO_DEPTH: integer := 4;
MASTER_SYNC_DEPTH: integer := 2;
SLAVE_SYNC_DEPTH: integer := 2;
BYTEEN_WIDTH : vl_notype
);
port(
s0_clk : in vl_logic;
s0_reset : in vl_logic;
m0_clk : in vl_logic;
m0_reset : in vl_logic;
s0_waitrequest : out vl_logic;
s0_readdata : out vl_logic_vector;
s0_readdatavalid: out vl_logic;
s0_burstcount : in vl_logic_vector;
s0_writedata : in vl_logic_vector;
s0_address : in vl_logic_vector;
s0_write : in vl_logic;
s0_read : in vl_logic;
s0_byteenable : in vl_logic_vector;
s0_debugaccess : in vl_logic;
m0_waitrequest : in vl_logic;
m0_readdata : in vl_logic_vector;
m0_readdatavalid: in vl_logic;
m0_burstcount : out vl_logic_vector;
m0_writedata : out vl_logic_vector;
m0_address : out vl_logic_vector;
m0_write : out vl_logic;
m0_read : out vl_logic;
m0_byteenable : out vl_logic_vector;
m0_debugaccess : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of SYMBOL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of HDL_ADDR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of BURSTCOUNT_WIDTH : constant is 1;
attribute mti_svvh_generic_type of COMMAND_FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RESPONSE_FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of MASTER_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of SLAVE_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of BYTEEN_WIDTH : constant is 3;
end altera_avalon_mm_clock_crossing_bridge;
|
library verilog;
use verilog.vl_types.all;
entity altera_avalon_mm_clock_crossing_bridge is
generic(
DATA_WIDTH : integer := 32;
SYMBOL_WIDTH : integer := 8;
HDL_ADDR_WIDTH : integer := 10;
BURSTCOUNT_WIDTH: integer := 1;
COMMAND_FIFO_DEPTH: integer := 4;
RESPONSE_FIFO_DEPTH: integer := 4;
MASTER_SYNC_DEPTH: integer := 2;
SLAVE_SYNC_DEPTH: integer := 2;
BYTEEN_WIDTH : vl_notype
);
port(
s0_clk : in vl_logic;
s0_reset : in vl_logic;
m0_clk : in vl_logic;
m0_reset : in vl_logic;
s0_waitrequest : out vl_logic;
s0_readdata : out vl_logic_vector;
s0_readdatavalid: out vl_logic;
s0_burstcount : in vl_logic_vector;
s0_writedata : in vl_logic_vector;
s0_address : in vl_logic_vector;
s0_write : in vl_logic;
s0_read : in vl_logic;
s0_byteenable : in vl_logic_vector;
s0_debugaccess : in vl_logic;
m0_waitrequest : in vl_logic;
m0_readdata : in vl_logic_vector;
m0_readdatavalid: in vl_logic;
m0_burstcount : out vl_logic_vector;
m0_writedata : out vl_logic_vector;
m0_address : out vl_logic_vector;
m0_write : out vl_logic;
m0_read : out vl_logic;
m0_byteenable : out vl_logic_vector;
m0_debugaccess : out vl_logic
);
attribute mti_svvh_generic_type : integer;
attribute mti_svvh_generic_type of DATA_WIDTH : constant is 1;
attribute mti_svvh_generic_type of SYMBOL_WIDTH : constant is 1;
attribute mti_svvh_generic_type of HDL_ADDR_WIDTH : constant is 1;
attribute mti_svvh_generic_type of BURSTCOUNT_WIDTH : constant is 1;
attribute mti_svvh_generic_type of COMMAND_FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of RESPONSE_FIFO_DEPTH : constant is 1;
attribute mti_svvh_generic_type of MASTER_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of SLAVE_SYNC_DEPTH : constant is 1;
attribute mti_svvh_generic_type of BYTEEN_WIDTH : constant is 3;
end altera_avalon_mm_clock_crossing_bridge;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1937.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01937ent IS
END c07s02b01x00p01n04i01937ent;
ARCHITECTURE c07s02b01x00p01n04i01937arch OF c07s02b01x00p01n04i01937ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a and b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01937 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01937arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1937.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01937ent IS
END c07s02b01x00p01n04i01937ent;
ARCHITECTURE c07s02b01x00p01n04i01937arch OF c07s02b01x00p01n04i01937ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a and b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01937 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01937arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1937.vhd,v 1.2 2001-10-26 16:30:14 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s02b01x00p01n04i01937ent IS
END c07s02b01x00p01n04i01937ent;
ARCHITECTURE c07s02b01x00p01n04i01937arch OF c07s02b01x00p01n04i01937ent IS
BEGIN
TESTING: PROCESS
type array_one is array (positive range <>) of boolean;
variable x : array_one( 1 to 10);
variable y : array_one(1 to 5);
variable z : array_one(1 to 10);
type array_two is array (positive range <>) of bit;
variable a : array_two( 1 to 10);
variable b : array_two(1 to 5);
variable c : array_two(1 to 10);
BEGIN
c := (a and b); -- Failure_here
assert FALSE
report "***FAILED TEST: c07s02b01x00p01n04i01937 - Operands should be arrays of the same length."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s02b01x00p01n04i01937arch;
|
-------------------------------------------------------------------------------
--
-- (C) COPYRIGHT 2010 Gideon's Logic Architectures'
--
-------------------------------------------------------------------------------
--
-- Author: Gideon Zweijtzer (gideon.zweijtzer (at) gmail.com)
--
-- Note that this file is copyrighted, and is not supposed to be used in other
-- projects without written permission from the author.
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.my_math_pkg.all;
use work.io_bus_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity sid_filter is
port (
clock : in std_logic;
reset : in std_logic;
io_req : in t_io_req := c_io_req_init;
io_resp : out t_io_resp;
filt_co : in unsigned(10 downto 0);
filt_res : in unsigned(3 downto 0);
valid_in : in std_logic := '0';
error_out : out std_logic;
input : in signed(17 downto 0);
high_pass : out signed(17 downto 0);
band_pass : out signed(17 downto 0);
low_pass : out signed(17 downto 0);
valid_out : out std_logic );
end entity;
architecture dsvf of sid_filter is
signal filter_q : signed(17 downto 0);
signal filter_f : signed(17 downto 0);
signal input_sc : signed(21 downto 0);
signal filt_ram : std_logic_vector(15 downto 0);
signal xa : signed(17 downto 0);
signal xb : signed(17 downto 0);
signal sum_b : signed(21 downto 0);
signal sub_a : signed(21 downto 0);
signal sub_b : signed(21 downto 0);
signal x_reg : signed(21 downto 0) := (others => '0');
signal bp_reg : signed(21 downto 0);
signal hp_reg : signed(21 downto 0);
signal lp_reg : signed(21 downto 0);
signal temp_reg : signed(21 downto 0);
signal error : std_logic := '0';
signal program_counter : integer range 0 to 15;
signal instruction : std_logic_vector(7 downto 0);
type t_byte_array is array(natural range <>) of std_logic_vector(7 downto 0);
alias xa_select : std_logic is instruction(0);
alias xb_select : std_logic is instruction(1);
alias sub_a_sel : std_logic is instruction(2);
alias sub_b_sel : std_logic is instruction(3);
alias sum_to_lp : std_logic is instruction(4);
alias sum_to_bp : std_logic is instruction(5);
alias sub_to_hp : std_logic is instruction(6);
alias mult_enable : std_logic is instruction(7);
-- operations to execute the filter:
-- bp_f = f * bp_reg
-- q_contrib = q * bp_reg
-- lp = bp_f + lp_reg
-- temp = input - lp
-- hp = temp - q_contrib
-- hp_f = f * hp
-- bp = hp_f + bp_reg
-- bp_reg = bp
-- lp_reg = lp
-- x_reg = f * bp_reg -- 10000000 -- 80
-- lp_reg = x_reg + lp_reg -- 00010010 -- 12
-- q_contrib = q * bp_reg -- 10000001 -- 81
-- temp = input - lp -- 00000000 -- 00 (can be merged with previous!)
-- hp_reg = temp - q_contrib -- 01001100 -- 4C
-- x_reg = f * hp_reg -- 10000010 -- 82
-- bp_reg = x_reg + bp_reg -- 00100000 -- 20
constant c_program : t_byte_array := (X"80", X"12", X"81", X"4C", X"82", X"20");
signal io_rdata : std_logic_vector(7 downto 0);
signal io_coef_en : std_logic;
signal io_coef_en_d : std_logic;
begin
-- Derive the actual 'f' and 'q' parameters
i_q_table: entity work.Q_table
port map (
Q_reg => filt_res,
filter_q => filter_q ); -- 2.16 format
-- I prefer to infer ram than to instantiate a vendor specific
-- block, but this is the fastest, as the sizes of the ports differ.
-- Secondly, a nice init value can be given, for as long as we don't connect
-- the IO bus.
i_filt_coef: RAMB16_S9_S18
generic map (
INIT_00 => X"0329032803280327032703260326032503240324032303230322032203210320",
INIT_01 => X"03320332033103300330032f032f032e032e032d032c032c032b032b032a032a",
INIT_02 => X"033b033b033a033a033903380338033703370336033603350334033403330333",
INIT_03 => X"034403440343034303420341034103400340033f033f033e033e033d033c033c",
INIT_04 => X"035603550354035303510350034f034e034d034c034b03490348034703460345",
INIT_05 => X"03680367036603650364036203610360035f035e035d035c035b035903580357",
INIT_06 => X"037a037903780377037603750374037203710370036f036e036d036c036a0369",
INIT_07 => X"038d038b038a038903880387038603850383038203810380037f037e037d037c",
INIT_08 => X"03b803b603b303b003ad03aa03a703a403a2039f039c0399039603930391038e",
INIT_09 => X"03e603e303e003dd03db03d803d503d203cf03cc03c903c703c403c103be03bb",
INIT_0A => X"04130411040e040b04080405040203ff03fd03fa03f703f403f103ee03ec03e9",
INIT_0B => X"0441043e043b0438043604330430042d042a042704240422041f041c04190416",
INIT_0C => X"04aa04a3049d0496048f04880481047a0474046d0466045f04580451044b0444",
INIT_0D => X"05170511050a050304fc04f504ee04e804e104da04d304cc04c504bf04b804b1",
INIT_0E => X"0585057e0577057005690562055c0555054e05470540053a0533052c0525051e",
INIT_0F => X"05f205eb05e405dd05d705d005c905c205bb05b405ae05a705a005990592058b",
INIT_10 => X"072c0717070306ee06da06c506b1069d06880674065f064b06360622060d05f9",
INIT_11 => X"0874085f084b08360822080d07f907e407d007bb07a70792077e076907550740",
INIT_12 => X"09bb09a70992097e096909550940092c0917090308ee08da08c508b1089c0888",
INIT_13 => X"0b030aee0ada0ac50ab10a9c0a880a740a5f0a4b0a360a220a0d09f909e409d0",
INIT_14 => X"0dd30da40d760d470d190cea0cbb0c8d0c5e0c2f0c010bd20ba30b750b460b17",
INIT_15 => X"10bd108f1060103210030fd40fa60f770f480f1a0eeb0ebc0e8e0e5f0e300e02",
INIT_16 => X"13a81379134b131c12ed12bf129012611233120411d511a711781149111b10ec",
INIT_17 => X"169216641635160615d815a9157a154c151d14ee14c0149114621434140513d7",
INIT_18 => X"1b6c1b1c1acc1a7d1a2d19dd198e193e18ee189f184f17ff17b01760171116c1",
INIT_19 => X"206620161fc71f771f271ed81e881e381de91d991d491cfa1caa1c5a1c0b1bbb",
INIT_1A => X"26b5264f25e92582251c24b5244f23e92382231c22b5224f21e92182211c20b5",
INIT_1B => X"2d1c2cb52c4f2be92b822b1c2ab52a4f29e92982291c28b5284f27e92782271c",
INIT_1C => X"34d8345a33dd336032e3326631e9316b30ee30712ff42f772efa2e7d2dff2d82",
INIT_1D => X"3caa3c2d3bb03b333ab53a3839bb393e38c1384437c7374936cc364f35d23555",
INIT_1E => X"467d45dd453e449f43ff436042c14222418240e340443fa43f053e663dc63d27",
INIT_1F => X"54b95381524851104fff4eee4ddd4ccc4c164b604aaa49f4493e488847d2471c",
INIT_20 => X"4ac84a3149994901486a47d2473a46a2460b457344db4444438e42d84222416b",
INIT_21 => X"54b55416537752d85238519950fa505a4fbb4f1c4e7d4ddd4d3e4c9f4bff4b60",
INIT_22 => X"5d555ccc5c445bbb5b335aaa5a2159995910588857ff577756ee566655dd5555",
INIT_23 => X"65dd655564cc644463bb633362aa62216199611060885fff5f775eee5e665ddd",
INIT_24 => X"6e106d8e6d0b6c886c056b826aff6a7c69fa697768f4687167ee676b66e96666",
INIT_25 => X"763e75bb753874b5743273b0732d72aa722771a47121709f701c6f996f166e93",
INIT_26 => X"7e6b7de87d667ce37c607bdd7b5a7ad77a5579d2794f78cc784977c6774476c1",
INIT_27 => X"8699861685938510848d840b83888305828281ff817c80fa80777ff47f717eee",
INIT_28 => X"8f718ee38e558dc68d388caa8c1c8b8d8aff8a7189e3895588c6883887aa871c",
INIT_29 => X"985597c6973896aa961c958d94ff947193e3935592c6923891aa911c908d8fff",
INIT_2A => X"a138a0aaa01c9f8d9eff9e719de39d559cc69c389baa9b1c9a8d99ff997198e3",
INIT_2B => X"aa1ca98da8ffa871a7e3a755a6c6a638a5aaa51ca48da3ffa371a2e3a255a1c6",
INIT_2C => X"b2ffb271b1e3b154b0c6b038afaaaf1cae8dadffad71ace3ac54abc6ab38aaaa",
INIT_2D => X"bbe3bb54bac6ba38b9aab91cb88db7ffb771b6e3b654b5c6b538b4aab41cb38d",
INIT_2E => X"c4c6c438c3aac31cc28dc1ffc171c0e3c054bfc6bf38beaabe1cbd8dbcffbc71",
INIT_2F => X"cdaacd1ccc8dcbffcb71cae3ca54c9c6c938c8aac81cc78dc6ffc671c5e3c554",
INIT_30 => X"d338d2e3d28dd238d1e3d18dd138d0e3d08dd038cfe3cf8dcf38cee3ce8dce38",
INIT_31 => X"d88dd838d7e3d78dd738d6e3d68dd638d5e3d58dd538d4e3d48dd438d3e3d38d",
INIT_32 => X"dde3dd8ddd38dce3dc8ddc38dbe3db8ddb38dae3da8dda38d9e3d98dd938d8e3",
INIT_33 => X"e338e2e3e28de238e1e3e18de138e0e3e08de038dfe3df8ddf38dee3de8dde38",
INIT_34 => X"e738e6f9e6bbe67ce63ee5ffe5c0e582e543e505e4c6e488e449e40ae3cce38d",
INIT_35 => X"eb21eae3eaa4ea65ea27e9e8e9aae96be92de8eee8afe871e832e7f4e7b5e777",
INIT_36 => X"ef0aeeccee8dee4fee10edd2ed93ed54ed16ecd7ec99ec5aec1bebddeb9eeb60",
INIT_37 => X"f2f4f2b5f276f238f1f9f1bbf17cf13ef0fff0c0f082f043f005efc6ef88ef49",
INIT_38 => X"f532f510f4eef4ccf4aaf488f465f443f421f3fff3ddf3bbf399f376f354f332",
INIT_39 => X"f754f732f710f6eef6ccf6aaf688f665f643f621f5fff5ddf5bbf599f576f554",
INIT_3A => X"f976f954f932f910f8eef8ccf8aaf888f865f843f821f7fff7ddf7bbf799f776",
INIT_3B => X"fb99fb76fb54fb32fb10faeefaccfaaafa88fa65fa43fa21f9fff9ddf9bbf999",
INIT_3C => X"fcbdfcacfc9afc89fc78fc67fc56fc44fc33fc22fc11fc00fbeefbddfbccfbbb",
INIT_3D => X"fdd0fdbffdaefd9cfd8bfd7afd69fd58fd46fd35fd24fd13fd02fcf0fcdffcce",
INIT_3E => X"fee3fed2fec1feb0fe9efe8dfe7cfe6bfe5afe48fe37fe26fe15fe04fdf2fde1",
INIT_3F => X"fff6ffe5ffd4ffc3ffb2ffa0ff8fff7eff6dff5cff4aff39ff28ff17ff06fef4" )
port map (
DOA => io_rdata,
DOPA => open,
ADDRA => std_logic_vector(io_req.address(10 downto 0)),
CLKA => clock,
DIA => io_req.data,
DIPA => "0",
ENA => io_coef_en,
SSRA => '0',
WEA => io_req.write,
DOB => filt_ram,
DOPB => open,
ADDRB => std_logic_vector(filt_co(10 downto 1)),
CLKB => clock,
DIB => X"0000",
DIPB => "00",
ENB => '1',
SSRB => '0',
WEB => '0' );
io_coef_en <= io_req.read or io_req.write;
io_coef_en_d <= io_coef_en when rising_edge(clock);
io_resp.ack <= io_coef_en_d;
io_resp.data <= X"00"; --io_rdata when io_coef_en_d = '1' else X"00";
process(clock)
begin
if rising_edge(clock) then
filter_f <= "00" & signed(filt_ram(15 downto 0));
end if;
end process;
--input_sc <= input;
input_sc <= shift_right(input, 1) & "0000";
-- now perform the arithmetic
xa <= filter_f when xa_select='0' else filter_q;
xb <= bp_reg(21 downto 4) when xb_select='0' else hp_reg (21 downto 4);
sum_b <= bp_reg when xb_select='0' else lp_reg;
sub_a <= input_sc when sub_a_sel='0' else temp_reg;
sub_b <= lp_reg when sub_b_sel='0' else x_reg;
process(clock)
variable x_result : signed(35 downto 0);
variable sum_result : signed(21 downto 0);
variable sub_result : signed(21 downto 0);
begin
if rising_edge(clock) then
x_result := xa * xb;
if mult_enable='1' then
x_reg <= x_result(33 downto 12);
if (x_result(35 downto 33) /= "000") and (x_result(35 downto 33) /= "111") then
error <= not error;
end if;
end if;
sum_result := sum_limit(x_reg, sum_b);
if sum_to_lp='1' then
lp_reg <= sum_result;
end if;
if sum_to_bp='1' then
bp_reg <= sum_result;
end if;
sub_result := sub_limit(sub_a, sub_b);
temp_reg <= sub_result;
if sub_to_hp='1' then
hp_reg <= sub_result;
end if;
-- control part
instruction <= (others => '0');
if reset='1' then
hp_reg <= (others => '0');
lp_reg <= (others => '0');
bp_reg <= (others => '0');
program_counter <= 0;
elsif valid_in = '1' then
program_counter <= 0;
else
if program_counter /= 15 then
program_counter <= program_counter + 1;
end if;
if program_counter < c_program'length then
instruction <= c_program(program_counter);
end if;
end if;
if program_counter = c_program'length then
valid_out <= '1';
else
valid_out <= '0';
end if;
end if;
end process;
high_pass <= hp_reg(21 downto 4);
band_pass <= bp_reg(21 downto 4);
low_pass <= lp_reg(21 downto 4);
error_out <= error;
end dsvf;
|
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
-- Copyright (c) 1990 UCI CADLAB, Dept. of ICS
-- Author : Sanjiv Narayan ([email protected])
--
-- Updated 7/8/91 by Sanjiv and Frank
--
-- updated by Champaka Ramachandran 16/10/92
--
--***************************************************************************
use work.TYPES.all;
package MVL7_functions is
function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR;
function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR;
function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function I2B( Number : integer ; len : integer ) return MVL7_VECTOR;
function B2I( v2 : MVL7_VECTOR ) return integer;
function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7;
function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7;
function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function SUM( v2 : MVL7_VECTOR ) return integer;
function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR;
function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR;
function INC( x : MVL7_VECTOR ) return MVL7_VECTOR;
function CARRY_ADD( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "-"( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
-- truth table for "WiredOr" function
constant tbl_WIREDOR: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', 'X', '1', 'X', 'X', 'L', 'H'), -- | X |
('X', '0', '1', '0', '0', 'L', 'H'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z |
('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W |
('L', 'L', '1', 'L', 'W', 'L', 'W'), -- | L |
('H', 'H', '1', 'H', 'W', 'W', 'H')); -- | H |
function WiredOr (V: MVL7_VECTOR) return MVL7;
end;
package body MVL7_functions is
--***************************************************************************
function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
variable I: integer;
begin
v1 := v2;
for I in v1'high downto (v1'low + 1) loop
shift_val(I) := v1(I - 1);
end loop ;
shift_val(v1'low) := fill;
return shift_val;
end;
--***************************************************************************
function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHL(v1,'0');
end loop ;
return v1;
end;
--***************************************************************************
function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHL(v1,'1');
end loop ;
return v1;
end;
--***************************************************************************
function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
for I in v1'low to (v1'high - 1) loop
shift_val(I) := v1(I + 1);
end loop ;
shift_val(v1'high) := fill;
return shift_val;
end;
--***************************************************************************
function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHR(v1,'0');
end loop ;
return v1;
end;
--***************************************************************************
function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHR(v1,'1');
end loop ;
return v1;
end;
--***************************************************************************
function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for i in 1 to dist loop
v1 := SHR(v1,v1(v1'low));
end loop ;
return v1;
end;
--***************************************************************************
function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for i in 1 to dist loop
v1 := SHL(v1,v1(v1'high));
end loop ;
return v1;
end;
--***************************************************************************
function I2B( Number : integer ; len : integer ) return MVL7_VECTOR is
variable temp: MVL7_VECTOR (len - 1 downto 0);
variable NUM: integer:=0;
variable QUOTIENT: integer:=0;
begin
QUOTIENT := Number;
for I in 0 to len - 1 loop
NUM := 0;
while QUOTIENT > 1 loop
QUOTIENT := QUOTIENT - 2;
NUM := NUM + 1;
end loop ;
case QUOTIENT is
when 1 =>
temp(I) := '1';
when 0 =>
temp(I) := '0';
when others =>
null;
end case;
QUOTIENT := NUM;
end loop ;
return temp;
end;
--***************************************************************************
function B2I( v2 : MVL7_VECTOR ) return integer is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable SUM: integer:=0;
begin
v1 := v2;
for N in v1'low to v1'high loop
if v1(N) = '1' then
SUM := SUM + (2 ** (N - v1'low));
end if;
end loop ;
return SUM;
end;
--***************************************************************************
function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
variable I: INTEGER;
begin
v1 := v2;
for I in v1'low to v1'high loop
if v1(I) = '0' then
temp(i) := '1';
else
temp(i) := '0';
end if;
end loop ;
return temp;
end;
--***************************************************************************
function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
temp := comp(v1);
temp := INC(temp);
return temp;
end;
--***************************************************************************
function "-" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector -: operands of unequal lengths" severity FAILURE;
SUM := I2B(B2I(v1) - B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR is
variable v: MVL7_VECTOR (x'high downto x'low);
begin
v := x;
return I2B(B2I(v) - 1,v'length);
end;
--***************************************************************************
function CARRY_ADD( x1: MVL7_VECTOR ; x2: MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (x1'high - x1'low + 1 downto 0);
-- + 1 is for carry
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7vector carry add:operands of unequal lengths"
severity FAILURE;
SUM := I2B(B2I(v1) + B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector +: operands of unequal lengths" severity FAILURE;
SUM := I2B(B2I(v1) + B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function INC( x : MVL7_VECTOR ) return MVL7_VECTOR is
variable v: MVL7_VECTOR (x'high downto x'low);
begin
v := x;
return I2B(B2I(v) + 1,v'length);
end;
--***************************************************************************
function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7 is
begin
if ((SUM(v1) mod 2) = 1) then
return '0';
else
return '1';
end if;
end;
--***************************************************************************
function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7 is
begin
if ((SUM(v1) mod 2) = 1) then
return '1';
else
return '0';
end if;
end;
--***************************************************************************
function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
for I in v1'high downto v1'low loop
temp(I) := v1(v1'high - I + v1'low);
end loop ;
return temp;
end;
--***************************************************************************
function SUM( v2 : MVL7_VECTOR ) return integer is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable count: integer:=0;
begin
v1 := v2;
for I in v1'high downto v1'low loop
if (v1(I) = '1') then
count := count + 1;
end if;
end loop ;
return count;
end;
--***************************************************************************
function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR is
begin
return I2B(B2I(v),width);
end;
--***************************************************************************
function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable PROD: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector MUL: operands of unequal lengths" severity FAILURE;
PROD := I2B(B2I(v1) * B2I(v2),PROD'length);
return (PROD);
end;
--***************************************************************************
function WiredOr (V: MVL7_VECTOR) return MVL7 is
variable result: MVL7;
begin
result := 'Z';
for i in V'range loop
result := tbl_WIREDOr(result, V(i));
exit when result = '1';
end loop;
return result;
end WiredOr;
--***************************************************************************
end; |
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
-- Copyright (c) 1990 UCI CADLAB, Dept. of ICS
-- Author : Sanjiv Narayan ([email protected])
--
-- Updated 7/8/91 by Sanjiv and Frank
--
-- updated by Champaka Ramachandran 16/10/92
--
--***************************************************************************
use work.TYPES.all;
package MVL7_functions is
function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR;
function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR;
function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function I2B( Number : integer ; len : integer ) return MVL7_VECTOR;
function B2I( v2 : MVL7_VECTOR ) return integer;
function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7;
function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7;
function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function SUM( v2 : MVL7_VECTOR ) return integer;
function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR;
function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR;
function INC( x : MVL7_VECTOR ) return MVL7_VECTOR;
function CARRY_ADD( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "-"( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
-- truth table for "WiredOr" function
constant tbl_WIREDOR: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', 'X', '1', 'X', 'X', 'L', 'H'), -- | X |
('X', '0', '1', '0', '0', 'L', 'H'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z |
('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W |
('L', 'L', '1', 'L', 'W', 'L', 'W'), -- | L |
('H', 'H', '1', 'H', 'W', 'W', 'H')); -- | H |
function WiredOr (V: MVL7_VECTOR) return MVL7;
end;
package body MVL7_functions is
--***************************************************************************
function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
variable I: integer;
begin
v1 := v2;
for I in v1'high downto (v1'low + 1) loop
shift_val(I) := v1(I - 1);
end loop ;
shift_val(v1'low) := fill;
return shift_val;
end;
--***************************************************************************
function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHL(v1,'0');
end loop ;
return v1;
end;
--***************************************************************************
function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHL(v1,'1');
end loop ;
return v1;
end;
--***************************************************************************
function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
for I in v1'low to (v1'high - 1) loop
shift_val(I) := v1(I + 1);
end loop ;
shift_val(v1'high) := fill;
return shift_val;
end;
--***************************************************************************
function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHR(v1,'0');
end loop ;
return v1;
end;
--***************************************************************************
function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHR(v1,'1');
end loop ;
return v1;
end;
--***************************************************************************
function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for i in 1 to dist loop
v1 := SHR(v1,v1(v1'low));
end loop ;
return v1;
end;
--***************************************************************************
function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for i in 1 to dist loop
v1 := SHL(v1,v1(v1'high));
end loop ;
return v1;
end;
--***************************************************************************
function I2B( Number : integer ; len : integer ) return MVL7_VECTOR is
variable temp: MVL7_VECTOR (len - 1 downto 0);
variable NUM: integer:=0;
variable QUOTIENT: integer:=0;
begin
QUOTIENT := Number;
for I in 0 to len - 1 loop
NUM := 0;
while QUOTIENT > 1 loop
QUOTIENT := QUOTIENT - 2;
NUM := NUM + 1;
end loop ;
case QUOTIENT is
when 1 =>
temp(I) := '1';
when 0 =>
temp(I) := '0';
when others =>
null;
end case;
QUOTIENT := NUM;
end loop ;
return temp;
end;
--***************************************************************************
function B2I( v2 : MVL7_VECTOR ) return integer is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable SUM: integer:=0;
begin
v1 := v2;
for N in v1'low to v1'high loop
if v1(N) = '1' then
SUM := SUM + (2 ** (N - v1'low));
end if;
end loop ;
return SUM;
end;
--***************************************************************************
function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
variable I: INTEGER;
begin
v1 := v2;
for I in v1'low to v1'high loop
if v1(I) = '0' then
temp(i) := '1';
else
temp(i) := '0';
end if;
end loop ;
return temp;
end;
--***************************************************************************
function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
temp := comp(v1);
temp := INC(temp);
return temp;
end;
--***************************************************************************
function "-" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector -: operands of unequal lengths" severity FAILURE;
SUM := I2B(B2I(v1) - B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR is
variable v: MVL7_VECTOR (x'high downto x'low);
begin
v := x;
return I2B(B2I(v) - 1,v'length);
end;
--***************************************************************************
function CARRY_ADD( x1: MVL7_VECTOR ; x2: MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (x1'high - x1'low + 1 downto 0);
-- + 1 is for carry
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7vector carry add:operands of unequal lengths"
severity FAILURE;
SUM := I2B(B2I(v1) + B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector +: operands of unequal lengths" severity FAILURE;
SUM := I2B(B2I(v1) + B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function INC( x : MVL7_VECTOR ) return MVL7_VECTOR is
variable v: MVL7_VECTOR (x'high downto x'low);
begin
v := x;
return I2B(B2I(v) + 1,v'length);
end;
--***************************************************************************
function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7 is
begin
if ((SUM(v1) mod 2) = 1) then
return '0';
else
return '1';
end if;
end;
--***************************************************************************
function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7 is
begin
if ((SUM(v1) mod 2) = 1) then
return '1';
else
return '0';
end if;
end;
--***************************************************************************
function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
for I in v1'high downto v1'low loop
temp(I) := v1(v1'high - I + v1'low);
end loop ;
return temp;
end;
--***************************************************************************
function SUM( v2 : MVL7_VECTOR ) return integer is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable count: integer:=0;
begin
v1 := v2;
for I in v1'high downto v1'low loop
if (v1(I) = '1') then
count := count + 1;
end if;
end loop ;
return count;
end;
--***************************************************************************
function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR is
begin
return I2B(B2I(v),width);
end;
--***************************************************************************
function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable PROD: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector MUL: operands of unequal lengths" severity FAILURE;
PROD := I2B(B2I(v1) * B2I(v2),PROD'length);
return (PROD);
end;
--***************************************************************************
function WiredOr (V: MVL7_VECTOR) return MVL7 is
variable result: MVL7;
begin
result := 'Z';
for i in V'range loop
result := tbl_WIREDOr(result, V(i));
exit when result = '1';
end loop;
return result;
end WiredOr;
--***************************************************************************
end; |
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
-- Copyright (c) 1990 UCI CADLAB, Dept. of ICS
-- Author : Sanjiv Narayan ([email protected])
--
-- Updated 7/8/91 by Sanjiv and Frank
--
-- updated by Champaka Ramachandran 16/10/92
--
--***************************************************************************
use work.TYPES.all;
package MVL7_functions is
function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR;
function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR;
function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function I2B( Number : integer ; len : integer ) return MVL7_VECTOR;
function B2I( v2 : MVL7_VECTOR ) return integer;
function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7;
function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7;
function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function SUM( v2 : MVL7_VECTOR ) return integer;
function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR;
function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR;
function INC( x : MVL7_VECTOR ) return MVL7_VECTOR;
function CARRY_ADD( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "-"( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
-- truth table for "WiredOr" function
constant tbl_WIREDOR: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', 'X', '1', 'X', 'X', 'L', 'H'), -- | X |
('X', '0', '1', '0', '0', 'L', 'H'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z |
('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W |
('L', 'L', '1', 'L', 'W', 'L', 'W'), -- | L |
('H', 'H', '1', 'H', 'W', 'W', 'H')); -- | H |
function WiredOr (V: MVL7_VECTOR) return MVL7;
end;
package body MVL7_functions is
--***************************************************************************
function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
variable I: integer;
begin
v1 := v2;
for I in v1'high downto (v1'low + 1) loop
shift_val(I) := v1(I - 1);
end loop ;
shift_val(v1'low) := fill;
return shift_val;
end;
--***************************************************************************
function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHL(v1,'0');
end loop ;
return v1;
end;
--***************************************************************************
function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHL(v1,'1');
end loop ;
return v1;
end;
--***************************************************************************
function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
for I in v1'low to (v1'high - 1) loop
shift_val(I) := v1(I + 1);
end loop ;
shift_val(v1'high) := fill;
return shift_val;
end;
--***************************************************************************
function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHR(v1,'0');
end loop ;
return v1;
end;
--***************************************************************************
function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHR(v1,'1');
end loop ;
return v1;
end;
--***************************************************************************
function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for i in 1 to dist loop
v1 := SHR(v1,v1(v1'low));
end loop ;
return v1;
end;
--***************************************************************************
function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for i in 1 to dist loop
v1 := SHL(v1,v1(v1'high));
end loop ;
return v1;
end;
--***************************************************************************
function I2B( Number : integer ; len : integer ) return MVL7_VECTOR is
variable temp: MVL7_VECTOR (len - 1 downto 0);
variable NUM: integer:=0;
variable QUOTIENT: integer:=0;
begin
QUOTIENT := Number;
for I in 0 to len - 1 loop
NUM := 0;
while QUOTIENT > 1 loop
QUOTIENT := QUOTIENT - 2;
NUM := NUM + 1;
end loop ;
case QUOTIENT is
when 1 =>
temp(I) := '1';
when 0 =>
temp(I) := '0';
when others =>
null;
end case;
QUOTIENT := NUM;
end loop ;
return temp;
end;
--***************************************************************************
function B2I( v2 : MVL7_VECTOR ) return integer is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable SUM: integer:=0;
begin
v1 := v2;
for N in v1'low to v1'high loop
if v1(N) = '1' then
SUM := SUM + (2 ** (N - v1'low));
end if;
end loop ;
return SUM;
end;
--***************************************************************************
function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
variable I: INTEGER;
begin
v1 := v2;
for I in v1'low to v1'high loop
if v1(I) = '0' then
temp(i) := '1';
else
temp(i) := '0';
end if;
end loop ;
return temp;
end;
--***************************************************************************
function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
temp := comp(v1);
temp := INC(temp);
return temp;
end;
--***************************************************************************
function "-" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector -: operands of unequal lengths" severity FAILURE;
SUM := I2B(B2I(v1) - B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR is
variable v: MVL7_VECTOR (x'high downto x'low);
begin
v := x;
return I2B(B2I(v) - 1,v'length);
end;
--***************************************************************************
function CARRY_ADD( x1: MVL7_VECTOR ; x2: MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (x1'high - x1'low + 1 downto 0);
-- + 1 is for carry
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7vector carry add:operands of unequal lengths"
severity FAILURE;
SUM := I2B(B2I(v1) + B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector +: operands of unequal lengths" severity FAILURE;
SUM := I2B(B2I(v1) + B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function INC( x : MVL7_VECTOR ) return MVL7_VECTOR is
variable v: MVL7_VECTOR (x'high downto x'low);
begin
v := x;
return I2B(B2I(v) + 1,v'length);
end;
--***************************************************************************
function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7 is
begin
if ((SUM(v1) mod 2) = 1) then
return '0';
else
return '1';
end if;
end;
--***************************************************************************
function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7 is
begin
if ((SUM(v1) mod 2) = 1) then
return '1';
else
return '0';
end if;
end;
--***************************************************************************
function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
for I in v1'high downto v1'low loop
temp(I) := v1(v1'high - I + v1'low);
end loop ;
return temp;
end;
--***************************************************************************
function SUM( v2 : MVL7_VECTOR ) return integer is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable count: integer:=0;
begin
v1 := v2;
for I in v1'high downto v1'low loop
if (v1(I) = '1') then
count := count + 1;
end if;
end loop ;
return count;
end;
--***************************************************************************
function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR is
begin
return I2B(B2I(v),width);
end;
--***************************************************************************
function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable PROD: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector MUL: operands of unequal lengths" severity FAILURE;
PROD := I2B(B2I(v1) * B2I(v2),PROD'length);
return (PROD);
end;
--***************************************************************************
function WiredOr (V: MVL7_VECTOR) return MVL7 is
variable result: MVL7;
begin
result := 'Z';
for i in V'range loop
result := tbl_WIREDOr(result, V(i));
exit when result = '1';
end loop;
return result;
end WiredOr;
--***************************************************************************
end; |
--***************************************************************************
-- VHDL BIT_VECTOR Operations for MVL7 type
--
-- Copyright (c) 1990 UCI CADLAB, Dept. of ICS
-- Author : Sanjiv Narayan ([email protected])
--
-- Updated 7/8/91 by Sanjiv and Frank
--
-- updated by Champaka Ramachandran 16/10/92
--
--***************************************************************************
use work.TYPES.all;
package MVL7_functions is
function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR;
function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR;
function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR;
function I2B( Number : integer ; len : integer ) return MVL7_VECTOR;
function B2I( v2 : MVL7_VECTOR ) return integer;
function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7;
function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7;
function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR;
function SUM( v2 : MVL7_VECTOR ) return integer;
function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR;
function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR;
function INC( x : MVL7_VECTOR ) return MVL7_VECTOR;
function CARRY_ADD( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "-"( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR;
-- truth table for "WiredOr" function
constant tbl_WIREDOR: MVL7_TABLE :=
-- -----------------------------------------------
-- | X 0 1 Z W L H | |
-- -----------------------------------------------
(('X', 'X', '1', 'X', 'X', 'L', 'H'), -- | X |
('X', '0', '1', '0', '0', 'L', 'H'), -- | 0 |
('1', '1', '1', '1', '1', '1', '1'), -- | 1 |
('X', '0', '1', 'Z', 'W', 'L', 'H'), -- | Z |
('X', '0', '1', 'W', 'W', 'W', 'W'), -- | W |
('L', 'L', '1', 'L', 'W', 'L', 'W'), -- | L |
('H', 'H', '1', 'H', 'W', 'W', 'H')); -- | H |
function WiredOr (V: MVL7_VECTOR) return MVL7;
end;
package body MVL7_functions is
--***************************************************************************
function SHL( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
variable I: integer;
begin
v1 := v2;
for I in v1'high downto (v1'low + 1) loop
shift_val(I) := v1(I - 1);
end loop ;
shift_val(v1'low) := fill;
return shift_val;
end;
--***************************************************************************
function SHL0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHL(v1,'0');
end loop ;
return v1;
end;
--***************************************************************************
function SHL1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHL(v1,'1');
end loop ;
return v1;
end;
--***************************************************************************
function SHR( v2 : MVL7_VECTOR ; fill : MVL7 ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable shift_val: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
for I in v1'low to (v1'high - 1) loop
shift_val(I) := v1(I + 1);
end loop ;
shift_val(v1'high) := fill;
return shift_val;
end;
--***************************************************************************
function SHR0( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHR(v1,'0');
end loop ;
return v1;
end;
--***************************************************************************
function SHR1( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for I in 1 to dist loop
v1 := SHR(v1,'1');
end loop ;
return v1;
end;
--***************************************************************************
function ROTR( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for i in 1 to dist loop
v1 := SHR(v1,v1(v1'low));
end loop ;
return v1;
end;
--***************************************************************************
function ROTL( v2 : MVL7_VECTOR ; dist : INTEGER ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable I: INTEGER;
begin
v1 := v2;
for i in 1 to dist loop
v1 := SHL(v1,v1(v1'high));
end loop ;
return v1;
end;
--***************************************************************************
function I2B( Number : integer ; len : integer ) return MVL7_VECTOR is
variable temp: MVL7_VECTOR (len - 1 downto 0);
variable NUM: integer:=0;
variable QUOTIENT: integer:=0;
begin
QUOTIENT := Number;
for I in 0 to len - 1 loop
NUM := 0;
while QUOTIENT > 1 loop
QUOTIENT := QUOTIENT - 2;
NUM := NUM + 1;
end loop ;
case QUOTIENT is
when 1 =>
temp(I) := '1';
when 0 =>
temp(I) := '0';
when others =>
null;
end case;
QUOTIENT := NUM;
end loop ;
return temp;
end;
--***************************************************************************
function B2I( v2 : MVL7_VECTOR ) return integer is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable SUM: integer:=0;
begin
v1 := v2;
for N in v1'low to v1'high loop
if v1(N) = '1' then
SUM := SUM + (2 ** (N - v1'low));
end if;
end loop ;
return SUM;
end;
--***************************************************************************
function COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
variable I: INTEGER;
begin
v1 := v2;
for I in v1'low to v1'high loop
if v1(I) = '0' then
temp(i) := '1';
else
temp(i) := '0';
end if;
end loop ;
return temp;
end;
--***************************************************************************
function TWOs_COMP( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
temp := comp(v1);
temp := INC(temp);
return temp;
end;
--***************************************************************************
function "-" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector -: operands of unequal lengths" severity FAILURE;
SUM := I2B(B2I(v1) - B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function DEC( x : MVL7_VECTOR ) return MVL7_VECTOR is
variable v: MVL7_VECTOR (x'high downto x'low);
begin
v := x;
return I2B(B2I(v) - 1,v'length);
end;
--***************************************************************************
function CARRY_ADD( x1: MVL7_VECTOR ; x2: MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (x1'high - x1'low + 1 downto 0);
-- + 1 is for carry
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7vector carry add:operands of unequal lengths"
severity FAILURE;
SUM := I2B(B2I(v1) + B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function "+" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable SUM: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector +: operands of unequal lengths" severity FAILURE;
SUM := I2B(B2I(v1) + B2I(v2),SUM'length);
return (SUM);
end;
--***************************************************************************
function INC( x : MVL7_VECTOR ) return MVL7_VECTOR is
variable v: MVL7_VECTOR (x'high downto x'low);
begin
v := x;
return I2B(B2I(v) + 1,v'length);
end;
--***************************************************************************
function ODD_PARITY( v1 : MVL7_VECTOR ) return MVL7 is
begin
if ((SUM(v1) mod 2) = 1) then
return '0';
else
return '1';
end if;
end;
--***************************************************************************
function EVEN_PARITY( v1 : MVL7_VECTOR ) return MVL7 is
begin
if ((SUM(v1) mod 2) = 1) then
return '1';
else
return '0';
end if;
end;
--***************************************************************************
function REVERSE( v2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable temp: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := v2;
for I in v1'high downto v1'low loop
temp(I) := v1(v1'high - I + v1'low);
end loop ;
return temp;
end;
--***************************************************************************
function SUM( v2 : MVL7_VECTOR ) return integer is
variable v1: MVL7_VECTOR (v2'high downto v2'low);
variable count: integer:=0;
begin
v1 := v2;
for I in v1'high downto v1'low loop
if (v1(I) = '1') then
count := count + 1;
end if;
end loop ;
return count;
end;
--***************************************************************************
function PAD( v : MVL7_VECTOR ; width : integer ) return MVL7_VECTOR is
begin
return I2B(B2I(v),width);
end;
--***************************************************************************
function "*" ( x1 : MVL7_VECTOR ; x2 : MVL7_VECTOR ) return MVL7_VECTOR is
variable v1: MVL7_VECTOR (x1'high - x1'low downto 0);
variable v2: MVL7_VECTOR (x2'high - x2'low downto 0);
variable PROD: MVL7_VECTOR (v1'high downto v1'low);
begin
v1 := x1;
v2 := x2;
assert v1'length = v2'length
report "MVL7 vector MUL: operands of unequal lengths" severity FAILURE;
PROD := I2B(B2I(v1) * B2I(v2),PROD'length);
return (PROD);
end;
--***************************************************************************
function WiredOr (V: MVL7_VECTOR) return MVL7 is
variable result: MVL7;
begin
result := 'Z';
for i in V'range loop
result := tbl_WIREDOr(result, V(i));
exit when result = '1';
end loop;
return result;
end WiredOr;
--***************************************************************************
end; |
-- register file circuit
-- contains 31 32-bit general-purpose registers, plus 1 register that is always hardcoded to 0
-- all code (c) copyright 2016 Jay Valentine, released under the MIT license
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity register_file is
port (
-- read addresses
a_addr : in std_logic_vector(4 downto 0);
b_addr : in std_logic_vector(4 downto 0);
-- read data
a_data : out std_logic_vector(31 downto 0);
b_data : out std_logic_vector(31 downto 0);
-- write address, enable, clock and data
wr_addr : in std_logic_vector(4 downto 0);
wr_data : in std_logic_vector(31 downto 0);
wr_enable : in std_logic;
wr_clk : in std_logic;
-- async reset
rst : in std_logic
);
end entity register_file;
architecture register_file_arch of register_file is
-- signal declarations
-- registers
signal r01 : std_logic_vector(31 downto 0);
signal r02 : std_logic_vector(31 downto 0);
signal r03 : std_logic_vector(31 downto 0);
signal r04 : std_logic_vector(31 downto 0);
signal r05 : std_logic_vector(31 downto 0);
signal r06 : std_logic_vector(31 downto 0);
signal r07 : std_logic_vector(31 downto 0);
signal r08 : std_logic_vector(31 downto 0);
signal r09 : std_logic_vector(31 downto 0);
signal r10 : std_logic_vector(31 downto 0);
signal r11 : std_logic_vector(31 downto 0);
signal r12 : std_logic_vector(31 downto 0);
signal r13 : std_logic_vector(31 downto 0);
signal r14 : std_logic_vector(31 downto 0);
signal r15 : std_logic_vector(31 downto 0);
signal r16 : std_logic_vector(31 downto 0);
signal r17 : std_logic_vector(31 downto 0);
signal r18 : std_logic_vector(31 downto 0);
signal r19 : std_logic_vector(31 downto 0);
signal r20 : std_logic_vector(31 downto 0);
signal r21 : std_logic_vector(31 downto 0);
signal r22 : std_logic_vector(31 downto 0);
signal r23 : std_logic_vector(31 downto 0);
signal r24 : std_logic_vector(31 downto 0);
signal r25 : std_logic_vector(31 downto 0);
signal r26 : std_logic_vector(31 downto 0);
signal r27 : std_logic_vector(31 downto 0);
signal r28 : std_logic_vector(31 downto 0);
signal r29 : std_logic_vector(31 downto 0);
signal r30 : std_logic_vector(31 downto 0);
signal r31 : std_logic_vector(31 downto 0);
-- constant r0 which is hardcoded 0
constant r00 : std_logic_vector(31 downto 0) := (others => '0');
begin
-- design implementation
registers : process(a_addr, b_addr, wr_clk, rst)
begin
-- if reset high, clear all registers
if rst = '1' then
r01 <= r00;
r02 <= r00;
r03 <= r00;
r04 <= r00;
r05 <= r00;
r06 <= r00;
r07 <= r00;
r08 <= r00;
r09 <= r00;
r10 <= r00;
r11 <= r00;
r12 <= r00;
r13 <= r00;
r14 <= r00;
r15 <= r00;
r16 <= r00;
r17 <= r00;
r18 <= r00;
r19 <= r00;
r20 <= r00;
r21 <= r00;
r22 <= r00;
r23 <= r00;
r24 <= r00;
r25 <= r00;
r26 <= r00;
r27 <= r00;
r28 <= r00;
r29 <= r00;
r30 <= r00;
r31 <= r00;
else
-- reading from registers, outputting to ports a and b
-- case statements for a
case a_addr is
-- 32 register cases, including r00
when "00000" => a_data <= r00;
when "00001" => a_data <= r01;
when "00010" => a_data <= r02;
when "00011" => a_data <= r03;
when "00100" => a_data <= r04;
when "00101" => a_data <= r05;
when "00110" => a_data <= r06;
when "00111" => a_data <= r07;
when "01000" => a_data <= r08;
when "01001" => a_data <= r09;
when "01010" => a_data <= r10;
when "01011" => a_data <= r11;
when "01100" => a_data <= r12;
when "01101" => a_data <= r13;
when "01110" => a_data <= r14;
when "01111" => a_data <= r15;
when "10000" => a_data <= r16;
when "10001" => a_data <= r17;
when "10010" => a_data <= r18;
when "10011" => a_data <= r19;
when "10100" => a_data <= r20;
when "10101" => a_data <= r21;
when "10110" => a_data <= r22;
when "10111" => a_data <= r23;
when "11000" => a_data <= r24;
when "11001" => a_data <= r25;
when "11010" => a_data <= r26;
when "11011" => a_data <= r27;
when "11100" => a_data <= r28;
when "11101" => a_data <= r29;
when "11110" => a_data <= r30;
when "11111" => a_data <= r31;
-- exception case
when others => a_data <= r00;
end case;
-- case statements for b
case b_addr is
-- 32 register cases, including r00
when "00000" => b_data <= r00;
when "00001" => b_data <= r01;
when "00010" => b_data <= r02;
when "00011" => b_data <= r03;
when "00100" => b_data <= r04;
when "00101" => b_data <= r05;
when "00110" => b_data <= r06;
when "00111" => b_data <= r07;
when "01000" => b_data <= r08;
when "01001" => b_data <= r09;
when "01010" => b_data <= r10;
when "01011" => b_data <= r11;
when "01100" => b_data <= r12;
when "01101" => b_data <= r13;
when "01110" => b_data <= r14;
when "01111" => b_data <= r15;
when "10000" => b_data <= r16;
when "10001" => b_data <= r17;
when "10010" => b_data <= r18;
when "10011" => b_data <= r19;
when "10100" => b_data <= r20;
when "10101" => b_data <= r21;
when "10110" => b_data <= r22;
when "10111" => b_data <= r23;
when "11000" => b_data <= r24;
when "11001" => b_data <= r25;
when "11010" => b_data <= r26;
when "11011" => b_data <= r27;
when "11100" => b_data <= r28;
when "11101" => b_data <= r29;
when "11110" => b_data <= r30;
when "11111" => b_data <= r31;
-- exception case
when others => b_data <= r00;
end case;
-- writing to registers
if rising_edge(wr_clk) then
if wr_enable = '1' then
-- case statement for writing to register
case wr_addr is
-- note exclusion of address 00000, r00 cannot be written to
when "00001" => r01 <= wr_data;
when "00010" => r02 <= wr_data;
when "00011" => r03 <= wr_data;
when "00100" => r04 <= wr_data;
when "00101" => r05 <= wr_data;
when "00110" => r06 <= wr_data;
when "00111" => r07 <= wr_data;
when "01000" => r08 <= wr_data;
when "01001" => r09 <= wr_data;
when "01010" => r10 <= wr_data;
when "01011" => r11 <= wr_data;
when "01100" => r12 <= wr_data;
when "01101" => r13 <= wr_data;
when "01110" => r14 <= wr_data;
when "01111" => r15 <= wr_data;
when "10000" => r16 <= wr_data;
when "10001" => r17 <= wr_data;
when "10010" => r18 <= wr_data;
when "10011" => r19 <= wr_data;
when "10100" => r20 <= wr_data;
when "10101" => r21 <= wr_data;
when "10110" => r22 <= wr_data;
when "10111" => r23 <= wr_data;
when "11000" => r24 <= wr_data;
when "11001" => r25 <= wr_data;
when "11010" => r26 <= wr_data;
when "11011" => r27 <= wr_data;
when "11100" => r28 <= wr_data;
when "11101" => r29 <= wr_data;
when "11110" => r30 <= wr_data;
when "11111" => r31 <= wr_data;
end case;
end if;
end if;
end if;
end process registers;
end architecture register_file_arch; |
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in integer );
end entity;
architecture test of e2 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e3 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e3 is
begin
end architecture;
-------------------------------------------------------------------------------
entity foo is
end entity;
architecture test of foo is
component e1 is
generic (
g : integer);
port (
x : in integer;
y : out integer);
end component;
component e2 is
generic (
g : integer);
port (
y : out integer);
end component;
component e3 is
generic (
g : integer);
port (
x : in bit;
y : out integer);
end component;
signal x : integer;
signal y : integer;
begin
e1_1: e1 -- OK
generic map (
g => 5 )
port map (
x => x,
y => y);
e2_1: e2 -- Error
generic map (
g => 5 )
port map (
y => y);
e3_1: e3 -- Error
generic map (
g => 5 )
port map (
x => '1',
y => y);
end architecture;
|
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in integer );
end entity;
architecture test of e2 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e3 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e3 is
begin
end architecture;
-------------------------------------------------------------------------------
entity foo is
end entity;
architecture test of foo is
component e1 is
generic (
g : integer);
port (
x : in integer;
y : out integer);
end component;
component e2 is
generic (
g : integer);
port (
y : out integer);
end component;
component e3 is
generic (
g : integer);
port (
x : in bit;
y : out integer);
end component;
signal x : integer;
signal y : integer;
begin
e1_1: e1 -- OK
generic map (
g => 5 )
port map (
x => x,
y => y);
e2_1: e2 -- Error
generic map (
g => 5 )
port map (
y => y);
e3_1: e3 -- Error
generic map (
g => 5 )
port map (
x => '1',
y => y);
end architecture;
|
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in integer );
end entity;
architecture test of e2 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e3 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e3 is
begin
end architecture;
-------------------------------------------------------------------------------
entity foo is
end entity;
architecture test of foo is
component e1 is
generic (
g : integer);
port (
x : in integer;
y : out integer);
end component;
component e2 is
generic (
g : integer);
port (
y : out integer);
end component;
component e3 is
generic (
g : integer);
port (
x : in bit;
y : out integer);
end component;
signal x : integer;
signal y : integer;
begin
e1_1: e1 -- OK
generic map (
g => 5 )
port map (
x => x,
y => y);
e2_1: e2 -- Error
generic map (
g => 5 )
port map (
y => y);
e3_1: e3 -- Error
generic map (
g => 5 )
port map (
x => '1',
y => y);
end architecture;
|
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in integer );
end entity;
architecture test of e2 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e3 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e3 is
begin
end architecture;
-------------------------------------------------------------------------------
entity foo is
end entity;
architecture test of foo is
component e1 is
generic (
g : integer);
port (
x : in integer;
y : out integer);
end component;
component e2 is
generic (
g : integer);
port (
y : out integer);
end component;
component e3 is
generic (
g : integer);
port (
x : in bit;
y : out integer);
end component;
signal x : integer;
signal y : integer;
begin
e1_1: e1 -- OK
generic map (
g => 5 )
port map (
x => x,
y => y);
e2_1: e2 -- Error
generic map (
g => 5 )
port map (
y => y);
e3_1: e3 -- Error
generic map (
g => 5 )
port map (
x => '1',
y => y);
end architecture;
|
entity e1 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e1 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e2 is
generic ( g : integer );
port (
x : in integer );
end entity;
architecture test of e2 is
begin
end architecture;
-------------------------------------------------------------------------------
entity e3 is
generic ( g : integer );
port (
x : in integer;
y : out integer );
end entity;
architecture test of e3 is
begin
end architecture;
-------------------------------------------------------------------------------
entity foo is
end entity;
architecture test of foo is
component e1 is
generic (
g : integer);
port (
x : in integer;
y : out integer);
end component;
component e2 is
generic (
g : integer);
port (
y : out integer);
end component;
component e3 is
generic (
g : integer);
port (
x : in bit;
y : out integer);
end component;
signal x : integer;
signal y : integer;
begin
e1_1: e1 -- OK
generic map (
g => 5 )
port map (
x => x,
y => y);
e2_1: e2 -- Error
generic map (
g => 5 )
port map (
y => y);
e3_1: e3 -- Error
generic map (
g => 5 )
port map (
x => '1',
y => y);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity pl_console is
port(
RESET : In std_logic;
user_clk : In std_logic;
user_wren : In std_logic;
user_rden : In std_logic;
UART_CTL : Out std_logic;
UART_BUSY : In std_logic;
UART_DATA : Out std_logic_vector(7 DOWNTO 0);
MOTOR_1 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_2 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_3 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_4 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_5 : Out std_logic_vector(15 DOWNTO 0);
MOTOR_6 : Out std_logic_vector(15 DOWNTO 0);
user_wstrb : In std_logic_vector(3 DOWNTO 0);
user_wr_data : In std_logic_vector(31 DOWNTO 0);
user_addr : In std_logic_vector(31 DOWNTO 0);
user_rd_data : Out std_logic_vector(31 DOWNTO 0);
GPIO_LED : OUT std_logic_vector(3 DOWNTO 0)
);
end entity;
architecture beh of pl_console is
type demo_mem is array(0 TO 31) of std_logic_vector(7 DOWNTO 0);
signal lite_addr : integer range 0 to 31;
signal motor1 : std_logic_vector(15 DOWNTO 0);
signal motor2 : std_logic_vector(15 DOWNTO 0);
signal motor3 : std_logic_vector(15 DOWNTO 0);
signal motor4 : std_logic_vector(15 DOWNTO 0);
signal motor5 : std_logic_vector(15 DOWNTO 0);
signal motor6 : std_logic_vector(15 DOWNTO 0);
signal litearray0 : demo_mem;
signal litearray1 : demo_mem;
signal litearray2 : demo_mem;
signal litearray3 : demo_mem;
begin
lite_addr <= conv_integer(user_addr(6 DOWNTO 2));
process(RESET,user_clk,UART_BUSY)
type StateType is(S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15,S16);
variable state : StateType := S0;
begin
if RESET = '0' then
state:= S0;
UART_CTL <= '0';
elsif rising_edge(user_clk) then
case state is
when S0 =>
UART_CTL <= '0';
UART_DATA <= x"00";
state := S1;
when S1 =>
UART_DATA <= motor1(15 DOWNTO 8);
state := S2;
when S2 =>
UART_CTL <= '1';
state := S3;
when S3 =>
UART_CTL <= '1';
state := S4;
when S4 =>
if UART_BUSY = '1' then
UART_CTL <= '0';
state := S5;
end if;
when S5 =>
UART_DATA <= motor1(7 DOWNTO 0);
state := S6;
when S6 =>
UART_CTL <= '1';
state := S7;
when S7 =>
UART_CTL <= '1';
state := S8;
when S8=>
if UART_BUSY = '1' then
UART_CTL <= '0';
state := S9;
end if;
when S9 =>
UART_DATA <= motor6(15 DOWNTO 8);
state := S10;
when S10 =>
UART_CTL <= '1';
state := S11;
when S11 =>
UART_CTL <= '1';
state := S12;
when S12 =>
if UART_BUSY = '1' then
UART_CTL <= '0';
state := S13;
end if;
when S13 =>
UART_DATA <= motor6(7 DOWNTO 0);
state := S14;
when S14 =>
UART_CTL <= '1';
state := S15;
when S15 =>
UART_CTL <= '1';
state := S16;
when S16 =>
if UART_BUSY = '1' then
UART_CTL <= '0';
state := S0;
end if;
when others =>
state := S0;
end case;
end if;
end process;
process (user_clk)
variable sys_status : std_logic_vector(31 DOWNTO 0);
begin
if (user_clk'event and user_clk = '1') then
if (user_wstrb(0) = '1') then
litearray0(lite_addr) <= user_wr_data(7 DOWNTO 0);
end if;
if (user_wstrb(1) = '1') then
litearray1(lite_addr) <= user_wr_data(15 DOWNTO 8);
end if;
if (user_wstrb(2) = '1') then
litearray2(lite_addr) <= user_wr_data(23 DOWNTO 16);
end if;
if (user_wstrb(3) = '1') then
litearray3(lite_addr) <= user_wr_data(31 DOWNTO 24);
end if;
if (user_rden = '1') then
user_rd_data <= litearray3(lite_addr) & litearray2(lite_addr) &
litearray1(lite_addr) & litearray0(lite_addr);
end if;
if (lite_addr = 1) then
GPIO_LED <= user_wr_data(31 DOWNTO 28);
motor1 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 2) then
motor2 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 3) then
motor3 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 4) then
motor4 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 5) then
motor5 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
if (lite_addr = 6) then
motor6 <= litearray3(lite_addr) & litearray2(lite_addr);
end if;
MOTOR_1 <= motor1;
MOTOR_2 <= motor2;
MOTOR_3 <= motor3;
MOTOR_4 <= motor4;
MOTOR_5 <= motor5;
MOTOR_6 <= motor6;
-- GPIO_LED <= "0101";
-- if (user_clk'event and user_clk = '1') then
-- if (user_wren = '1') then
---- litearray(lite_addr) <= user_wr_data;
-- sys_status := user_wr_data;
-- end if;
-- if (user_rden = '1') then
---- user_rd_data <= litearray(lite_addr);
-- user_rd_data <= sys_status;
-- end if;
-- end if;
end if;
end process;
end architecture;
|
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:11:31 PM
-- Design Name:
-- Module Name: AE - AE_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AE is
Port (
P3 : in STD_LOGIC; -- Control signal 3
P2 : in STD_LOGIC; -- Conrtol signal 2
P1 : in STD_LOGIC; -- Conrtol signal 1
P0 : in STD_LOGIC; -- Conrtol signal 0
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end AE;
architecture AE_Func of AE is
signal Temp1 : STD_LOGIC;
signal Temp2 : STD_LOGIC;
begin
-- P1(P2 xor B)
Temp1 <= P2 and P1 and (not B);
Temp2 <= (not P2) and P1 and B;
Y <= Temp1 or Temp2;
end AE_Func;
|
----------------------------------------------------------------------------------
-- Clarkson University
-- EE466/566 Computer Architecture Fall 2016
-- Project Name: Project1, 4-Bit ALU Design
--
-- Student Name : Zhiliu Yang
-- Student ID : 0754659
-- Major : Electrical and Computer Engineering
-- Email : [email protected]
-- Instructor Name: Dr. Chen Liu
-- Date : 09-25-2016
--
-- Create Date: 09/25/2016 04:11:31 PM
-- Design Name:
-- Module Name: AE - AE_Func
-- Target Devices:
-- Tool Versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity AE is
Port (
P3 : in STD_LOGIC; -- Control signal 3
P2 : in STD_LOGIC; -- Conrtol signal 2
P1 : in STD_LOGIC; -- Conrtol signal 1
P0 : in STD_LOGIC; -- Conrtol signal 0
A : in STD_LOGIC;
B : in STD_LOGIC;
Y : out STD_LOGIC);
end AE;
architecture AE_Func of AE is
signal Temp1 : STD_LOGIC;
signal Temp2 : STD_LOGIC;
begin
-- P1(P2 xor B)
Temp1 <= P2 and P1 and (not B);
Temp2 <= (not P2) and P1 and B;
Y <= Temp1 or Temp2;
end AE_Func;
|
-- megafunction wizard: %ALTACCUMULATE%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: altaccumulate
-- ============================================================
-- File Name: A.vhd
-- Megafunction Name(s):
-- altaccumulate
--
-- Simulation Library Files(s):
-- altera_mf
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.0 Build 184 04/29/2009 SP 1 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY altera_mf;
USE altera_mf.all;
ENTITY A IS
PORT
(
aclr : IN STD_LOGIC := '0';
clken : IN STD_LOGIC := '1';
clock : IN STD_LOGIC := '0';
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END A;
ARCHITECTURE SYN OF a IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (4 DOWNTO 0);
COMPONENT altaccumulate
GENERIC (
lpm_representation : STRING;
lpm_type : STRING;
width_in : NATURAL;
width_out : NATURAL
);
PORT (
clken : IN STD_LOGIC ;
aclr : IN STD_LOGIC ;
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
result : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
);
END COMPONENT;
BEGIN
result <= sub_wire0(4 DOWNTO 0);
altaccumulate_component : altaccumulate
GENERIC MAP (
lpm_representation => "UNSIGNED",
lpm_type => "altaccumulate",
width_in => 4,
width_out => 5
)
PORT MAP (
clken => clken,
aclr => aclr,
clock => clock,
data => data,
result => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "1"
-- Retrieval info: PRIVATE: ADD_SUB NUMERIC "0"
-- Retrieval info: PRIVATE: CIN NUMERIC "0"
-- Retrieval info: PRIVATE: CLKEN NUMERIC "1"
-- Retrieval info: PRIVATE: COUT NUMERIC "0"
-- Retrieval info: PRIVATE: EXTRA_LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "ACEX1K"
-- Retrieval info: PRIVATE: LATENCY NUMERIC "0"
-- Retrieval info: PRIVATE: LPM_REPRESENTATION NUMERIC "1"
-- Retrieval info: PRIVATE: OVERFLOW NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: WIDTH_IN NUMERIC "4"
-- Retrieval info: PRIVATE: WIDTH_OUT NUMERIC "5"
-- Retrieval info: CONSTANT: LPM_REPRESENTATION STRING "UNSIGNED"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altaccumulate"
-- Retrieval info: CONSTANT: WIDTH_IN NUMERIC "4"
-- Retrieval info: CONSTANT: WIDTH_OUT NUMERIC "5"
-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-- Retrieval info: USED_PORT: clken 0 0 0 0 INPUT VCC clken
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT GND clock
-- Retrieval info: USED_PORT: data 0 0 4 0 INPUT NODEFVAL data[3..0]
-- Retrieval info: USED_PORT: result 0 0 5 0 OUTPUT NODEFVAL result[4..0]
-- Retrieval info: CONNECT: @data 0 0 4 0 data 0 0 4 0
-- Retrieval info: CONNECT: result 0 0 5 0 @result 0 0 5 0
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: @clken 0 0 0 0 clken 0 0 0 0
-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_inst.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL A_wave*.jpg FALSE
-- Retrieval info: LIB_FILE: altera_mf
|
---------------------------------------------------------------------------------------------------
-- PICO 1802 Tiny BASIC - 4K x 8 RAM module
---------------------------------------------------------------------------------------------------
-- Generic synchronous RAM entity
-- When not selected, the outputs are driven low, allowing the system data bus to OR all data bus
-- sources togeather.
---------------------------------------------------------------------------------------------------
-- This file is part of the PICO 1802 Tiny BASIC Project
-- Copyright 2016, Steve Teal: [email protected]
--
-- This source file may be used and distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work contains the original
-- copyright notice and the associated disclaimer.
--
-- This source file is free software; you can redistribute it and/or modify it under the terms
-- of the GNU Lesser General Public License as published by the Free Software Foundation,
-- either version 3 of the License, or (at your option) any later version.
--
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
--
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-3.0.en.html
---------------------------------------------------------------------------------------------------
-- Steve Teal, Northamptonshire, United Kingdom
---------------------------------------------------------------------------------------------------
library ieee ;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity ram is
port(
clock: in std_logic;
cs_n: in std_logic;
rd_n: in std_logic;
wr_n: in std_logic;
address: in std_logic_vector(11 downto 0);
data_in: in std_logic_vector(7 downto 0);
data_out: out std_logic_vector(7 downto 0));
end ram;
architecture rtl of ram is
type ram_type is array (0 to 4095) of std_logic_vector(7 downto 0);
signal ram : ram_type;
begin
process(clock)
begin
if(rising_edge(clock))then
if(cs_n = '0' and wr_n = '0')then
ram(to_integer(unsigned(address))) <= data_in;
end if;
end if;
end process;
process(clock)
begin
if(rising_edge(clock))then
if(cs_n = '0' and rd_n = '0')then
data_out <= ram(to_integer(unsigned(address)));
else
data_out <= "00000000";
end if;
end if;
end process;
end rtl;
|
library foo;
entity test is end;
|
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