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-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
-- Date : Sun May 28 18:34:41 2017
-- Host : GILAMONSTER running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode synth_stub -rename_top system_zed_hdmi_0_0 -prefix
-- system_zed_hdmi_0_0_ system_zed_hdmi_0_0_stub.vhdl
-- Design : system_zed_hdmi_0_0
-- Purpose : Stub declaration of top-level module interface
-- Device : xc7z020clg484-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity system_zed_hdmi_0_0 is
Port (
clk : in STD_LOGIC;
clk_x2 : in STD_LOGIC;
clk_100 : in STD_LOGIC;
active : in STD_LOGIC;
hsync : in STD_LOGIC;
vsync : in STD_LOGIC;
rgb888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
hdmi_clk : out STD_LOGIC;
hdmi_hsync : out STD_LOGIC;
hdmi_vsync : out STD_LOGIC;
hdmi_d : out STD_LOGIC_VECTOR ( 15 downto 0 );
hdmi_de : out STD_LOGIC;
hdmi_scl : out STD_LOGIC;
hdmi_sda : inout STD_LOGIC
);
end system_zed_hdmi_0_0;
architecture stub of system_zed_hdmi_0_0 is
attribute syn_black_box : boolean;
attribute black_box_pad_pin : string;
attribute syn_black_box of stub : architecture is true;
attribute black_box_pad_pin of stub : architecture is "clk,clk_x2,clk_100,active,hsync,vsync,rgb888[23:0],hdmi_clk,hdmi_hsync,hdmi_vsync,hdmi_d[15:0],hdmi_de,hdmi_scl,hdmi_sda";
attribute x_core_info : string;
attribute x_core_info of stub : architecture is "zed_hdmi,Vivado 2016.4";
begin
end;
|
-- Prosoft VHDL tests.
--
-- Copyright (C) 2011 Prosoft.
--
-- Author: Zefirov, Karavaev.
--
-- This is a set of simplest tests for isolated tests of VHDL features.
--
-- Nothing more than standard package should be required.
--
-- Categories: entity, architecture, process, after, if-then-else, enumerations, array, record, case, for-loop, signals-attributes.
use work.std_logic_1164_for_tst.all;
entity ENT00016_Test_Bench is
end ENT00016_Test_Bench;
architecture ARCH00016_Test_Bench of ENT00016_Test_Bench is
type std_array_array is array (0 to 3, 1 to 4) of std_ulogic;
signal I_saa : std_array_array := (others => x"B");
signal I_saa_lv : std_array_array;
subtype byte is bit_vector(7 downto 0);
subtype byte2 is bit_vector(0 to 7);
signal b1 : byte := x"00";
signal b1_lv : byte;
signal b2 : byte2 := x"00";
signal b2_lv : byte2;
type bit_array_array is array (0 to 3, 4 downto 1) of bit;
signal I_baa : bit_array_array := (others => x"A");
signal I_baa_lv : bit_array_array;
type NatArray is array (natural range <>) of natural;
type std_array is array (0 to 7) of std_logic;
signal I_sa : std_array := "10101010";
signal I_sa_lv : std_array;
type enum is (a_v, b_v, c_v, d_v, e_v, f_v);
type enum_array is array (integer range <>) of enum;
type rec is record
f1 : integer;
f2 : boolean;
f3 : bit;
f4 : enum;
f5 : enum_array(0 to 3);
f6 : NatArray(7 downto 0);
f7 : bit_vector(7 downto 0);
end record;
type rec_array is array (integer range <>) of rec;
signal e : enum := a_v;
signal e_lv : enum;
signal ea : enum_array(0 to 3) := (others => a_v);
signal ea_lv : enum_array(0 to 3);
signal r : rec := (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
);
signal r_lv : rec;
signal ra : rec_array(0 to 3) := (others => (
f1 => 10
, f2 => true
, f3 => '1'
, f4 => a_v
, f5 => (others => a_v)
, f6 => (0 => 10, 7 => 3, others => 0)
, f7 => x"33"
)
);
signal ra_lv : rec_array(0 to 3);
signal bv : bit_vector(15 downto 0) := x"CCCC";
signal bv_lv : bit_vector(15 downto 0);
signal clk : std_ulogic := '0';
signal clk2 : std_ulogic := '0';
signal clk_lv : std_ulogic;
signal clk2_lv : std_ulogic;
begin
clk_lv <= clk'Last_value;
clk2_lv <= clk2'Last_value;
bv_lv <= bv'Last_value;
ra_lv <= ra'Last_value;
r_lv <= r'Last_value;
ea_lv <= ea'Last_value;
e_lv <= e'Last_value;
I_sa_lv <= I_sa'Last_value;
I_baa_lv <= I_baa'Last_value;
I_saa_lv <= I_saa'Last_value;
b1_lv <= b1'Last_value;
b2_lv <= b2'Last_value;
clk <= not clk after 1 us;
clk2 <= not clk2 after 3 us;
process (clk)
begin
if clk'event and clk = '1' then
b1 <= b1(6 downto 0) & not b1(7);
case e is
when a_v => e <= b_v;
when b_v => e <= c_v;
when c_v => e <= d_v;
when d_v => e <= e_v;
when e_v => e <= f_v;
when f_v => e <= a_v;
end case;
ea(0) <= e;
ea_loop: for i in 1 to ea'length-1 loop
ea(i) <= ea(i-1);
end loop ea_loop;
elsif falling_edge(clk) then
bv <= bv(bv'left-1 downto bv'low) & bv(bv'high);
r.f1 <= r.f1 + 1;
r.f2 <= not r.f2;
r.f3 <= not r.f3;
r.f4 <= e;
r.f5 <= ea;
r_f6_loop: for i in r.f6'low to r.f6'high loop
r.f6(i) <= r.f6(i) + 1;
end loop r_f6_loop;
r.f7 <= r.f7(6 downto 0) & r.f7(7);
ra(ra'high) <= r;
ra_loop: for i in ra'high-1 downto 0 loop
ra(i) <= ra(i+1);
end loop;
end if;
end process;
process (clk2)
begin
if rising_edge(clk2) then
I_sa <= I_sa(I_sa'length-1) & I_sa(0 to I_sa'length-2);
elsif clk2'event and clk2 = '0' then
I_saa_loop_1: for i in 0 to 3 loop
I_saa_loop_2: for j in 1 to 4 loop
I_saa(i,j) <= I_sa(i+j);
end loop I_saa_loop_2;
end loop I_saa_loop_1;
I_baa_loop_1: for i in 0 to 3 loop
I_baa_loop_2: for j in 1 to 4 loop
I_baa(i,j) <= bv(i*j);
end loop I_baa_loop_2;
end loop I_baa_loop_1;
end if;
end process;
end ARCH00016_Test_Bench ; |
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 20:51:13 07/09/2016
-- Design Name:
-- Module Name: audio_scancode_to_divisor - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity audio_scancode_to_divisor is port (
scancode : in STD_LOGIC_VECTOR(7 downto 0);
clock_divisor : out INTEGER);
end audio_scancode_to_divisor;
architecture Behavioral of audio_scancode_to_divisor is
begin
process(scancode)
begin
case scancode is
when "00100011" => clock_divisor <= 3367000; -- 297 Hz (d')
when "00100100" => clock_divisor <= 30303000; -- 330 Hz (e')
when "00101011" => clock_divisor <= 284091000; -- 352 Hz (f')
when "00110100" => clock_divisor <= 25252; -- 396 Hz (g')
when "00011100" => clock_divisor <= 22727; -- 440 Hz (a')
when "00110011" => clock_divisor <= 2020; -- 495 Hz (h')
when others => clock_divisor <= 378788; -- 264 Hz (c');
end case;
end process;
end Behavioral;
|
-- NEED RESULT: ARCH00511: The expression in an initialization specification may be globally static passed
-------------------------------------------------------------------------------
--
-- Copyright (c) 1989 by Intermetrics, Inc.
-- All rights reserved.
--
-------------------------------------------------------------------------------
--
-- TEST NAME:
--
-- CT00511
--
-- AUTHOR:
--
-- G. Tominovich
--
-- TEST OBJECTIVES:
--
-- 5.2 (5)
-- 5.2 (6)
-- 5.2 (8)
-- 5.2 (10)
--
-- DESIGN UNIT ORDERING:
--
-- ENT00511(ARCH00511)
-- ENT00511_Test_Bench(ARCH00511_Test_Bench)
--
-- REVISION HISTORY:
--
-- 10-AUG-1987 - initial revision
--
-- NOTES:
--
-- self-checking
--
use WORK.STANDARD_TYPES.all ;
entity ENT00511 is
generic (
g_boolean_1 : in boolean
; g_bit_1 : in bit
; g_severity_level_1 : in severity_level
; g_character_1 : in character
; g_st_enum1_1 : in st_enum1
; g_integer_1 : in integer
; g_st_int1_1 : in st_int1
; g_time_1 : in time
; g_st_phys1_1 : in st_phys1
; g_real_1 : in real
; g_st_real1_1 : in st_real1
; g_st_rec1_1 : in st_rec1
; g_st_rec2_1 : in st_rec2
; g_st_rec3_1 : in st_rec3
; g_st_arr1_1 : in st_arr1
; g_st_arr2_1 : in st_arr2
; g_st_arr3_1 : in st_arr3
);
end ENT00511;
--
--
architecture ARCH00511 of ENT00511 is
signal S_boolean : boolean := g_boolean_1 ;
--
signal S_bit : bit := g_bit_1 ;
--
signal S_severity_level : severity_level := g_severity_level_1 ;
--
signal S_character : character := g_character_1 ;
--
signal S_st_enum1 : st_enum1 := g_st_enum1_1 ;
--
signal S_integer : integer := g_integer_1 ;
--
signal S_st_int1 : st_int1 := g_st_int1_1 ;
--
signal S_time : time := g_time_1 ;
--
signal S_st_phys1 : st_phys1 := g_st_phys1_1 ;
--
signal S_real : real := g_real_1 ;
--
signal S_st_real1 : st_real1 := g_st_real1_1 ;
--
signal S_st_rec1 : st_rec1 := g_st_rec1_1 ;
--
signal S_st_rec2 : st_rec2 := g_st_rec2_1 ;
--
signal S_st_rec3 : st_rec3 := g_st_rec3_1 ;
--
signal S_st_arr1 : st_arr1 := g_st_arr1_1 ;
--
signal S_st_arr2 : st_arr2 := g_st_arr2_1 ;
--
signal S_st_arr3 : st_arr3 := g_st_arr3_1 ;
--
--
begin
process
variable correct : boolean := true;
begin
correct := correct and
(S_boolean = c_boolean_1) ;
correct := correct and
(S_bit = c_bit_1) ;
correct := correct and
(S_severity_level = c_severity_level_1) ;
correct := correct and
(S_character = c_character_1) ;
correct := correct and
(S_st_enum1 = c_st_enum1_1) ;
correct := correct and
(S_integer = c_integer_1) ;
correct := correct and
(S_st_int1 = c_st_int1_1) ;
correct := correct and
(S_time = c_time_1) ;
correct := correct and
(S_st_phys1 = c_st_phys1_1) ;
correct := correct and
(S_real = c_real_1) ;
correct := correct and
(S_st_real1 = c_st_real1_1) ;
correct := correct and
(S_st_rec1 = c_st_rec1_1) ;
correct := correct and
(S_st_rec2 = c_st_rec2_1) ;
correct := correct and
(S_st_rec3 = c_st_rec3_1) ;
correct := correct and
(S_st_arr1 = c_st_arr1_1) ;
correct := correct and
(S_st_arr2 = c_st_arr2_1) ;
correct := correct and
(S_st_arr3 = c_st_arr3_1) ;
test_report ( "ARCH00511" ,
"The expression in an initialization specification "&
"may be globally static" ,
correct );
wait ;
end process ;
end ARCH00511 ;
--
--
entity ENT00511_Test_Bench is
end ENT00511_Test_Bench ;
--
use WORK.STANDARD_TYPES.all ;
architecture ARCH00511_Test_Bench of ENT00511_Test_Bench is
begin
L1:
block
component UUT
generic (
g_boolean_1 : in boolean
; g_bit_1 : in bit
; g_severity_level_1 : in severity_level
; g_character_1 : in character
; g_st_enum1_1 : in st_enum1
; g_integer_1 : in integer
; g_st_int1_1 : in st_int1
; g_time_1 : in time
; g_st_phys1_1 : in st_phys1
; g_real_1 : in real
; g_st_real1_1 : in st_real1
; g_st_rec1_1 : in st_rec1
; g_st_rec2_1 : in st_rec2
; g_st_rec3_1 : in st_rec3
; g_st_arr1_1 : in st_arr1
; g_st_arr2_1 : in st_arr2
; g_st_arr3_1 : in st_arr3
) ;
end component ;
for CIS1 : UUT use entity WORK.ENT00511 ( ARCH00511 ) ;
begin
CIS1 : UUT
generic map (
c_boolean_1
, c_bit_1
, c_severity_level_1
, c_character_1
, c_st_enum1_1
, c_integer_1
, c_st_int1_1
, c_time_1
, c_st_phys1_1
, c_real_1
, c_st_real1_1
, c_st_rec1_1
, c_st_rec2_1
, c_st_rec3_1
, c_st_arr1_1
, c_st_arr2_1
, c_st_arr3_1
)
;
end block L1 ;
end ARCH00511_Test_Bench ;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use ieee.std_logic_unsigned.all;
entity keyboard is
port (
CLOCK : in std_logic;
nRESET : in std_logic;
CLKEN_1MHZ : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
KEYOUT : out std_logic_vector(5 downto 0);
ROW : in std_logic_vector(3 downto 0);
ESC_IN : in std_logic;
BREAK_IN : in std_logic;
SHIFT_OUT : out std_logic;
CTRL_OUT : out std_logic;
REPEAT_OUT : out std_logic;
BREAK_OUT : out std_logic;
TURBO : out std_logic_vector(1 downto 0);
ESC_OUT : out std_logic;
Joystick1 : in std_logic_vector (7 downto 0);
Joystick2 : in std_logic_vector (7 downto 0)
);
end entity;
architecture rtl of keyboard is
component ps2_intf is
generic (filter_length : positive := 8);
port(
CLK : in std_logic;
nRESET : in std_logic;
PS2_CLK : in std_logic;
PS2_DATA : in std_logic;
DATA : out std_logic_vector(7 downto 0);
VALID : out std_logic;
error : out std_logic
);
end component;
signal keyb_data : std_logic_vector(7 downto 0);
signal keyb_valid : std_logic;
signal keyb_error : std_logic;
type key_matrix is array(0 to 15) of std_logic_vector(7 downto 0);
signal keys : key_matrix;
signal col : unsigned(3 downto 0);
signal release : std_logic;
signal extended : std_logic;
signal key_data : std_logic_vector(7 downto 0);
signal ESC_IN1 : std_logic;
signal BREAK_IN1 : std_logic;
begin
ps2 : ps2_intf port map (
CLOCK,
nRESET,
PS2_CLK,
PS2_DATA,
keyb_data,
keyb_valid,
keyb_error);
process(keys, ROW)
begin
key_data <= keys(conv_integer(ROW(3 downto 0)));
-- 0 U R D L F
if (ROW = "0000") then
KEYOUT <= key_data(5 downto 0) and
('1' & Joystick1(0) & Joystick1(3) & Joystick1(1) & Joystick1(2) & Joystick1(5));
elsif (ROW = "0001") then
KEYOUT <= key_data(5 downto 0) and
('1' & Joystick2(0) & Joystick2(3) & Joystick2(1) & Joystick2(2) & Joystick2(5));
else
KEYOUT <= key_data(5 downto 0);
end if;
end process;
process(CLOCK, nRESET)
begin
if nRESET = '0' then
release <= '0';
extended <= '0';
TURBO <= "00";
BREAK_OUT <= '1';
SHIFT_OUT <= '1';
CTRL_OUT <= '1';
REPEAT_OUT <= '1';
ESC_IN1 <= ESC_IN;
BREAK_IN1 <= BREAK_IN;
keys(0) <= (others => '1');
keys(1) <= (others => '1');
keys(2) <= (others => '1');
keys(3) <= (others => '1');
keys(4) <= (others => '1');
keys(5) <= (others => '1');
keys(6) <= (others => '1');
keys(7) <= (others => '1');
keys(8) <= (others => '1');
keys(9) <= (others => '1');
keys(10) <= (others => '1');
keys(11) <= (others => '1');
keys(12) <= (others => '1');
keys(13) <= (others => '1');
keys(14) <= (others => '1');
keys(15) <= (others => '1');
elsif rising_edge(CLOCK) then
-- handle the escape key seperately, as it's value also depends on ESC_IN
if keyb_valid = '1' and keyb_data = X"76" then
keys(0)(5) <= release;
elsif ESC_IN /= ESC_IN1 then
keys(0)(5) <= ESC_IN;
end if;
ESC_IN1 <= ESC_IN;
-- handle the break key seperately, as it's value also depends on BREAK_IN
if keyb_valid = '1' and keyb_data = X"09" then
BREAK_OUT <= release;
elsif BREAK_IN /= BREAK_IN1 then
BREAK_OUT <= BREAK_IN;
end if;
BREAK_IN1 <= BREAK_IN;
if keyb_valid = '1' then
if keyb_data = X"e0" then
extended <= '1';
elsif keyb_data = X"f0" then
release <= '1';
else
release <= '0';
extended <= '0';
case keyb_data is
when X"05" => TURBO <= "00"; -- F1 (1MHz)
when X"06" => TURBO <= "01"; -- F2 (2MMz)
when X"04" => TURBO <= "10"; -- F3 (4MHz)
when X"0C" => TURBO <= "11"; -- F4 (8MHz)
-- when X"09" => BREAK_OUT <= release; -- F10 (BREAK)
when X"11" => REPEAT_OUT <= release; -- LEFT ALT (SHIFT LOCK)
when X"12" | X"59" =>
if (extended = '0') then -- Ignore fake shifts
SHIFT_OUT <= release; -- Left SHIFT -- Right SHIFT
end if;
when X"14" => CTRL_OUT <= release; -- LEFT/RIGHT CTRL (CTRL)
-----------------------------------------------------
-- process matrix
-----------------------------------------------------
when X"29" => keys(9)(0) <= release; -- SPACE
when X"54" => keys(8)(0) <= release; -- [
when X"5D" => keys(7)(0) <= release; -- \
when X"5B" => keys(6)(0) <= release; -- ]
when X"0D" => keys(5)(0) <= release; -- UP
when X"58" => keys(4)(0) <= release; -- CAPS LOCK
when X"74" => keys(3)(0) <= release; -- RIGHT
when X"75" => keys(2)(0) <= release; -- UP
when X"5A" => keys(6)(1) <= release; -- RETURN
when X"69" => keys(5)(1) <= release; -- END (COPY)
when X"66" => keys(4)(1) <= release; -- BACKSPACE (DELETE)
when X"45" => keys(3)(1) <= release; -- 0
when X"16" => keys(2)(1) <= release; -- 1
when X"1E" => keys(1)(1) <= release; -- 2
when X"26" => keys(0)(1) <= release; -- 3
when X"25" => keys(9)(2) <= release; -- 4
when X"2E" => keys(8)(2) <= release; -- 5
when X"36" => keys(7)(2) <= release; -- 6
when X"3D" => keys(6)(2) <= release; -- 7
when X"3E" => keys(5)(2) <= release; -- 8
when X"46" => keys(4)(2) <= release; -- 9
when X"52" => keys(3)(2) <= release; -- ' full colon substitute
when X"4C" => keys(2)(2) <= release; -- ;
when X"41" => keys(1)(2) <= release; -- ,
when X"4E" => keys(0)(2) <= release; -- -
when X"49" => keys(9)(3) <= release; -- .
when X"4A" => keys(8)(3) <= release; -- /
when X"55" => keys(7)(3) <= release; -- @ (TAB)
when X"1C" => keys(6)(3) <= release; -- A
when X"32" => keys(5)(3) <= release; -- B
when X"21" => keys(4)(3) <= release; -- C
when X"23" => keys(3)(3) <= release; -- D
when X"24" => keys(2)(3) <= release; -- E
when X"2B" => keys(1)(3) <= release; -- F
when X"34" => keys(0)(3) <= release; -- G
when X"33" => keys(9)(4) <= release; -- H
when X"43" => keys(8)(4) <= release; -- I
when X"3B" => keys(7)(4) <= release; -- J
when X"42" => keys(6)(4) <= release; -- K
when X"4B" => keys(5)(4) <= release; -- L
when X"3A" => keys(4)(4) <= release; -- M
when X"31" => keys(3)(4) <= release; -- N
when X"44" => keys(2)(4) <= release; -- O
when X"4D" => keys(1)(4) <= release; -- P
when X"15" => keys(0)(4) <= release; -- Q
when X"2D" => keys(9)(5) <= release; -- R
when X"1B" => keys(8)(5) <= release; -- S
when X"2C" => keys(7)(5) <= release; -- T
when X"3C" => keys(6)(5) <= release; -- U
when X"2A" => keys(5)(5) <= release; -- V
when X"1D" => keys(4)(5) <= release; -- W
when X"22" => keys(3)(5) <= release; -- X
when X"35" => keys(2)(5) <= release; -- Y
when X"1A" => keys(1)(5) <= release; -- Z
-- when X"76" => keys(0)(5) <= release; -- ESCAPE
when others => null;
end case;
end if;
end if;
end if;
end process;
ESC_OUT <= keys(0)(5);
end architecture;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:50:17 04/04/2016
-- Design Name:
-- Module Name: cpt_iter - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
use work.CONSTANTS.all;
use work.CONFIG_MANDELBROT.all;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity cpt_iter is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
inib : in std_logic;
endcalcul : in STD_LOGIC;
iter : out STD_LOGIC_VECTOR(ITER_RANGE-1 downto 0));
end cpt_iter;
architecture Behavioral of cpt_iter is
Signal iterS : unsigned(ITER_RANGE-1 downto 0);
begin
process(reset,clock)
begin
if reset='1' then
iterS<=to_unsigned(5,ITER_RANGE);
elsif rising_edge(clock) then
if inib = '1' then
if endcalcul ='1' then
if iterS < (ITER_MAX-10) then
iterS<=iterS+1;
else
iterS<=to_unsigned(10,ITER_RANGE);
end if;
end if;
end if;
end if;
end process;
iter<=std_logic_vector(iterS);
end Behavioral; |
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity sounds is
port(
clk, reset: in std_logic;
enable: in std_logic;
period: in std_logic_vector(18 downto 0);
volume: in std_logic_vector(2 downto 0);
speaker: out std_logic
);
end sounds;
architecture generator of sounds is
signal counter, counter_next: std_logic_vector(18 downto 0);
signal pulse_width: std_logic_vector(17 downto 0);
begin
process(clk, reset)
begin
if reset = '1' then
counter <= (others => '0');
elsif clk'event and clk = '0' then
counter <= counter_next;
end if;
end process;
-- duty cycle:
-- max: 50% (18 downto 1)
-- min: 0.78% (18 downto 7)
-- off when given 0 (18 downto 0)!
pulse_width <= period(18 downto conv_integer(volume));
counter_next <= (others => '0') when counter = period else
counter + 1;
speaker <= '1' when (enable = '1' and counter < pulse_width) else '0';
end generator; |
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
library work;
use work.zpu_config.all;
entity wbmux2 is
generic (
select_line: integer;
address_high: integer:=31;
address_low: integer:=2
);
port (
wb_clk_i: in std_logic;
wb_rst_i: in std_logic;
-- Master
m_wb_dat_o: out std_logic_vector(31 downto 0);
m_wb_dat_i: in std_logic_vector(31 downto 0);
m_wb_adr_i: in std_logic_vector(address_high downto address_low);
m_wb_sel_i: in std_logic_vector(3 downto 0);
m_wb_cti_i: in std_logic_vector(2 downto 0);
m_wb_we_i: in std_logic;
m_wb_cyc_i: in std_logic;
m_wb_stb_i: in std_logic;
m_wb_ack_o: out std_logic;
-- Slave 0 signals
s0_wb_dat_i: in std_logic_vector(31 downto 0);
s0_wb_dat_o: out std_logic_vector(31 downto 0);
s0_wb_adr_o: out std_logic_vector(address_high downto address_low);
s0_wb_sel_o: out std_logic_vector(3 downto 0);
s0_wb_cti_o: out std_logic_vector(2 downto 0);
s0_wb_we_o: out std_logic;
s0_wb_cyc_o: out std_logic;
s0_wb_stb_o: out std_logic;
s0_wb_ack_i: in std_logic;
-- Slave 1 signals
s1_wb_dat_i: in std_logic_vector(31 downto 0);
s1_wb_dat_o: out std_logic_vector(31 downto 0);
s1_wb_adr_o: out std_logic_vector(address_high downto address_low);
s1_wb_sel_o: out std_logic_vector(3 downto 0);
s1_wb_cti_o: out std_logic_vector(2 downto 0);
s1_wb_we_o: out std_logic;
s1_wb_cyc_o: out std_logic;
s1_wb_stb_o: out std_logic;
s1_wb_ack_i: in std_logic
);
end entity wbmux2;
architecture behave of wbmux2 is
signal select_zero: std_logic;
begin
select_zero<='1' when m_wb_adr_i(select_line)='0' else '0';
s0_wb_dat_o <= m_wb_dat_i;
s0_wb_adr_o <= m_wb_adr_i;
s0_wb_stb_o <= m_wb_stb_i;
s0_wb_we_o <= m_wb_we_i;
s0_wb_cti_o <= m_wb_cti_i;
s0_wb_sel_o <= m_wb_sel_i;
s1_wb_dat_o <= m_wb_dat_i;
s1_wb_adr_o <= m_wb_adr_i;
s1_wb_stb_o <= m_wb_stb_i;
s1_wb_we_o <= m_wb_we_i;
s1_wb_cti_o <= m_wb_cti_i;
s1_wb_sel_o <= m_wb_sel_i;
process(m_wb_cyc_i,select_zero)
begin
if m_wb_cyc_i='0' then
s0_wb_cyc_o<='0';
s1_wb_cyc_o<='0';
else
s0_wb_cyc_o<=select_zero;
s1_wb_cyc_o<=not select_zero;
end if;
end process;
process(select_zero,s1_wb_dat_i,s0_wb_dat_i,s0_wb_ack_i,s1_wb_ack_i)
begin
if select_zero='0' then
m_wb_dat_o<=s1_wb_dat_i;
m_wb_ack_o<=s1_wb_ack_i;
else
m_wb_dat_o<=s0_wb_dat_i;
m_wb_ack_o<=s0_wb_ack_i;
end if;
end process;
end behave;
|
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:54:31 06/24/2015
-- Design Name:
-- Module Name: asd - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity IfftControl is
generic(
CARRIERS : INTEGER :=128 --
);
Port (
reset : in STD_LOGIC;
clk : in STD_LOGIC;
IfftEnable: in STD_LOGIC;
start : out STD_LOGIC;
cp_len : out STD_LOGIC_VECTOR(6 DOWNTO 0);
cp_len_we : out STD_LOGIC;
unload : out STD_LOGIC;
fwd_inv : out STD_LOGIC;
fwd_inv_we : out STD_LOGIC;
rfd : in STD_LOGIC);
end IfftControl;
architecture Behavioral of IfftControl is
--declaracion de estados
type estado is (reposo,
-- leyendo,
inicio,
activo);
--señales
signal estado_actual, estado_nuevo: estado;
-- signal datoIn : STD_LOGIC_VECTOR (15 downto 0);
-- signal outReal, outImag : STD_LOGIC_VECTOR (7 downto 0);
-- signal dire_actual, dire_nuevo: STD_LOGIC_VECTOR(6 downto 0);
-- signal addra, p_addra : INTEGER RANGE 0 to CARRIERS; -- deberia ser carriers -1 pero sino no detectamos que es mayor por que desborda
begin
cp_len<="0001100"; --configuracion prefijo ciclico
fwd_inv <='0'; -- inversa ifft
--proceso sincrono
sinc: process(reset, clk)
begin
if(reset='1') then
estado_actual <= reposo;
elsif (clk='1' and clk'event) then
estado_actual <= estado_nuevo;
end if;
end process;
comb: process (estado_actual, ifftEnable, rfd)
begin
estado_nuevo<= estado_actual;
start <='0';
cp_len_we <='0';
unload <='1';
fwd_inv_we<='0';
case estado_actual is
when reposo =>
if ifftEnable='1' then
estado_nuevo<= inicio;
else
estado_nuevo <=reposo;
end if;
when inicio =>
--Conexiones con el core de FFT
start <='1';
cp_len_we <='1';
fwd_inv_we<='1';
--saltamos a otro estado
estado_nuevo<= activo;
when activo =>
start <='0';
--saltamos a otro estado
if rfd='1' then
estado_nuevo<= activo;
else
estado_nuevo <= reposo;
end if;
end case;
end process;
end Behavioral;
|
---------------------------------------------------------------------------
-- Company : ARMadeus Systems
-- Author(s) : Fabien Marteau
--
-- Creation Date : 20/07/2008
-- File : rstext_syscon.vhd
--
-- Abstract : wishbone syscon with external reset
--
---------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
---------------------------------------------------------------------------
Entity rstext_syscon is
---------------------------------------------------------------------------
generic(
invert_reset : std_logic := '0' -- 0 : not invert, 1: invert
);
port
(
-- external signals
ext_clk : in std_logic ;
ext_rst_n : in std_logic ;
--internal signals
gls_clk : out std_logic ;
gls_reset : out std_logic
);
end entity;
---------------------------------------------------------------------------
Architecture rstext_syscon_1 of rstext_syscon is
---------------------------------------------------------------------------
signal rff1 : std_logic ;
begin
gls_clk <= ext_clk;
reset_synchroniser : process (ext_clk,ext_rst_n)
begin
if ext_rst_n = not invert_reset then
rff1 <= '1';
gls_reset <= '1';
elsif rising_edge(ext_clk) then
rff1 <= '0';
gls_reset <= rff1;
end if;
end process reset_synchroniser;
end architecture rstext_syscon_1;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of cyclone3_pll is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY"
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
-- Must use operation_mode other than "ZERO_DELAY_BUFFER" due to
-- tool issues with ZERO_DELAY_BUFFER and non-existent output clock
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 5,
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_cycloneiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_cycloneiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component cyclone3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : cyclone3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_cycloneiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5P6ORZXA is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5P6ORZXA is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5P6ORZXA is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5P6ORZXA is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5P6ORZXA is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5P6ORZXA is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; |
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library altera;
use altera.alt_dspbuilder_package.all;
library lpm;
use lpm.lpm_components.all;
entity alt_dspbuilder_cast_GN5P6ORZXA is
generic ( round : natural := 0;
saturate : natural := 0);
port(
input : in std_logic_vector(23 downto 0);
output : out std_logic_vector(23 downto 0));
end entity;
architecture rtl of alt_dspbuilder_cast_GN5P6ORZXA is
Begin
-- Output - I/O assignment from Simulink Block "Output"
Outputi : alt_dspbuilder_SBF generic map(
width_inl=> 24 + 1 ,
width_inr=> 0,
width_outl=> 24,
width_outr=> 0,
lpm_signed=> BusIsSigned ,
round=> round,
satur=> saturate)
port map (
xin(23 downto 0) => input,
xin(24) => '0', yout => output
);
end architecture; |
entity vunit5 is
end entity;
architecture test of vunit5 is
type rec is record
f : bit_vector;
end record;
procedure proc (f : bit_vector) is
variable r : rec(f(f'length - 1 downto 0));
begin
r.f := f;
end procedure;
begin
end architecture;
|
-------------------------------------------------------------------------------
--
--! Title : 8b/10b Decoder
--! Design : 10-bit to 8-bit Decoder
-- Project : 8000 - 8b10b_encdec
--! Author : Ken Boyette
--! Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_dec.vhd
-- Version : 1.0
-- Generated : 09.27.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 10-bit to 9-bit encoding.
-- It accepts 10-bit encoded parallel data input and generates 8-bit decoded
-- data output in accordance with the 8b/10b standard method. This method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek. The method
-- WAS granted a U.S. Patent #4,486,739 in 1984; now expired.
--
-- The parallel 10-bit Binary input represent 1024 possible values, called
-- characters - only 268 of which are valid.
--
-- The input is a 10-bit encoded character whose bits are identified as:
-- AI, BI, CI, DI, EI, II, FI, GI, HI, JI (Least Significant to Most)
--
-- In addition to 256 data output characters, there are 12 special control
-- or K, characters defined for command and synchronization use.
--
-- The eight data output bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
--
-- The output, KO, is used to indicate the output value is one of the
-- control characters.
--
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent. The Figures
-- referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--! 8b/10b Decoder by Critia Computer, Inc.
entity dec_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (AH) -- syncronous now (13 JUL 2015)
RBYTECLK : in std_logic ; -- Master synchronous receive byte clock
AI, BI, CI, DI, EI, II : in std_logic ;
FI, GI, HI, JI : in std_logic ; -- Encoded input (LS..MS)
KO : out std_logic ; -- Control (K) character indicator (AH)
HO, GO, FO, EO, DO, CO, BO, AO : out std_logic -- Decoded out (MS..LS)
);
end dec_8b10b;
architecture behavioral of dec_8b10b is
-- Signals to tie things together
signal ANEB, CNED, EEI, P13, P22, P31 : std_logic := '0'; -- Figure 10 Signals
signal IKA, IKB, IKC : std_logic := '0'; -- Figure 11 Signals
signal XA, XB, XC, XD, XE : std_logic := '0'; -- Figure 12 Signals
signal OR121, OR122, OR123, OR124, OR125, OR126, OR127 : std_logic := '0';
signal XF, XG, XH : std_logic := '0'; -- Figure 13 Signals
signal OR131, OR132, OR133, OR134, IOR134 : std_logic := '0';
begin
--
-- 6b Input Function (Reference: Figure 10)
--
-- One 1 and three 0's
P13 <= (ANEB and (not CI and not DI))
or (CNED and (not AI and not BI)) ;
-- Three 1's and one 0
P31 <= (ANEB and CI and DI)
or (CNED and AI and BI) ;
-- Two 1's and two 0's
P22 <= (AI and BI and (not CI and not DI))
or (CI and DI and (not AI and not BI))
or (ANEB and CNED) ;
-- Intermediate term for "AI is Not Equal to BI"
ANEB <= AI xor BI ;
-- Intermediate term for "CI is Not Equal to DI"
CNED <= CI xor DI ;
-- Intermediate term for "E is Equal to I"
EEI <= EI xnor II ;
--
-- K Decoder - Figure 11
--
-- Intermediate terms
IKA <= (CI and DI and EI and II)
or (not CI and not DI and not EI and not II) ;
IKB <= P13 and (not EI and II and GI and HI and JI) ;
IKC <= P31 and (EI and not II and not GI and not HI and not JI) ;
-- PROCESS: KFN; Determine K output
-- original:
-- KFN: process (RESET, RBYTECLK, IKA, IKB, IKC)
-- begin
-- if RESET = '1' then
-- KO <= '0';
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- KO <= IKA or IKB or IKC;
-- end if;
-- end process KFN;
KFN: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
KO <= '0';
else
KO <= IKA or IKB or IKC;
end if;
end if;
end process KFN;
--
-- 5b Decoder Figure 12
--
-- Logic to determine complimenting A,B,C,D,E,I inputs
OR121 <= (P22 and (not AI and not CI and EEI))
or (P13 and not EI) ;
OR122 <= (AI and BI and EI and II)
or (not CI and not DI and not EI and not II)
or (P31 and II) ;
OR123 <= (P31 and II)
or (P22 and BI and CI and EEI)
or (P13 and DI and EI and II) ;
OR124 <= (P22 and AI and CI and EEI)
or (P13 and not EI) ;
OR125 <= (P13 and not EI)
or (not CI and not DI and not EI and not II)
or (not AI and not BI and not EI and not II) ;
OR126 <= (P22 and not AI and not CI and EEI)
or (P13 and not II) ;
OR127 <= (P13 and DI and EI and II)
or (P22 and not BI and not CI and EEI) ;
XA <= OR127
or OR121
or OR122 ;
XB <= OR122
or OR123
or OR124 ;
XC <= OR121
or OR123
or OR125 ;
XD <= OR122
or OR124
or OR127 ;
XE <= OR125
or OR126
or OR127 ;
-- PROCESS: DEC5B; Generate and latch LS 5 decoded bits
-- original:
-- DEC5B: process (RESET, RBYTECLK, XA, XB, XC, XD, XE, AI, BI, CI, DI, EI)
-- begin
-- if RESET = '1' then
-- AO <= '0' ;
-- BO <= '0' ;
-- CO <= '0' ;
-- DO <= '0' ;
-- EO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- AO <= XA XOR AI ; -- Least significant bit 0
-- BO <= XB XOR BI ;
-- CO <= XC XOR CI ;
-- DO <= XD XOR DI ;
-- EO <= XE XOR EI ; -- Most significant bit 6
-- end if;
-- end process DEC5B;
DEC5B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
else
AO <= XA XOR AI ; -- Least significant bit 0
BO <= XB XOR BI ;
CO <= XC XOR CI ;
DO <= XD XOR DI ;
EO <= XE XOR EI ; -- Most significant bit 6
end if;
end if;
end process DEC5B;
--
-- 3b Decoder - Figure 13
--
-- Logic for complimenting F,G,H outputs
OR131 <= (GI and HI and JI)
or (FI and HI and JI)
or (IOR134);
OR132 <= (FI and GI and JI)
or (not FI and not GI and not HI)
or (not FI and not GI and HI and JI);
OR133 <= (not FI and not HI and not JI)
or (IOR134)
or (not GI and not HI and not JI) ;
OR134 <= (not GI and not HI and not JI)
or (FI and HI and JI)
or (IOR134) ;
IOR134 <= (not (HI and JI))
and (not (not HI and not JI))
and (not CI and not DI and not EI and not II) ;
XF <= OR131
or OR132 ;
XG <= OR132
or OR133 ;
XH <= OR132
or OR134 ;
-- PROCESS: DEC3B; Generate and latch MS 3 decoded bits
-- original:
-- DEC3B: process (RESET, RBYTECLK, XF, XG, XH, FI, GI, HI)
-- begin
-- if RESET = '1' then
-- FO <= '0' ;
-- GO <= '0' ;
-- HO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK ='0' then
-- FO <= XF XOR FI ; -- Least significant bit 7
-- GO <= XG XOR GI ;
-- HO <= XH XOR HI ; -- Most significant bit 10
-- end if;
-- end process DEC3B ;
DEC3B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK ='0' then
if RESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
else
FO <= XF XOR FI ; -- Least significant bit 7
GO <= XG XOR GI ;
HO <= XH XOR HI ; -- Most significant bit 10
end if;
end if;
end process DEC3B ;
end behavioral;
|
-------------------------------------------------------------------------------
--
--! Title : 8b/10b Decoder
--! Design : 10-bit to 8-bit Decoder
-- Project : 8000 - 8b10b_encdec
--! Author : Ken Boyette
--! Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_dec.vhd
-- Version : 1.0
-- Generated : 09.27.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 10-bit to 9-bit encoding.
-- It accepts 10-bit encoded parallel data input and generates 8-bit decoded
-- data output in accordance with the 8b/10b standard method. This method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek. The method
-- WAS granted a U.S. Patent #4,486,739 in 1984; now expired.
--
-- The parallel 10-bit Binary input represent 1024 possible values, called
-- characters - only 268 of which are valid.
--
-- The input is a 10-bit encoded character whose bits are identified as:
-- AI, BI, CI, DI, EI, II, FI, GI, HI, JI (Least Significant to Most)
--
-- In addition to 256 data output characters, there are 12 special control
-- or K, characters defined for command and synchronization use.
--
-- The eight data output bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
--
-- The output, KO, is used to indicate the output value is one of the
-- control characters.
--
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent. The Figures
-- referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--! 8b/10b Decoder by Critia Computer, Inc.
entity dec_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (AH) -- syncronous now (13 JUL 2015)
RBYTECLK : in std_logic ; -- Master synchronous receive byte clock
AI, BI, CI, DI, EI, II : in std_logic ;
FI, GI, HI, JI : in std_logic ; -- Encoded input (LS..MS)
KO : out std_logic ; -- Control (K) character indicator (AH)
HO, GO, FO, EO, DO, CO, BO, AO : out std_logic -- Decoded out (MS..LS)
);
end dec_8b10b;
architecture behavioral of dec_8b10b is
-- Signals to tie things together
signal ANEB, CNED, EEI, P13, P22, P31 : std_logic := '0'; -- Figure 10 Signals
signal IKA, IKB, IKC : std_logic := '0'; -- Figure 11 Signals
signal XA, XB, XC, XD, XE : std_logic := '0'; -- Figure 12 Signals
signal OR121, OR122, OR123, OR124, OR125, OR126, OR127 : std_logic := '0';
signal XF, XG, XH : std_logic := '0'; -- Figure 13 Signals
signal OR131, OR132, OR133, OR134, IOR134 : std_logic := '0';
begin
--
-- 6b Input Function (Reference: Figure 10)
--
-- One 1 and three 0's
P13 <= (ANEB and (not CI and not DI))
or (CNED and (not AI and not BI)) ;
-- Three 1's and one 0
P31 <= (ANEB and CI and DI)
or (CNED and AI and BI) ;
-- Two 1's and two 0's
P22 <= (AI and BI and (not CI and not DI))
or (CI and DI and (not AI and not BI))
or (ANEB and CNED) ;
-- Intermediate term for "AI is Not Equal to BI"
ANEB <= AI xor BI ;
-- Intermediate term for "CI is Not Equal to DI"
CNED <= CI xor DI ;
-- Intermediate term for "E is Equal to I"
EEI <= EI xnor II ;
--
-- K Decoder - Figure 11
--
-- Intermediate terms
IKA <= (CI and DI and EI and II)
or (not CI and not DI and not EI and not II) ;
IKB <= P13 and (not EI and II and GI and HI and JI) ;
IKC <= P31 and (EI and not II and not GI and not HI and not JI) ;
-- PROCESS: KFN; Determine K output
-- original:
-- KFN: process (RESET, RBYTECLK, IKA, IKB, IKC)
-- begin
-- if RESET = '1' then
-- KO <= '0';
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- KO <= IKA or IKB or IKC;
-- end if;
-- end process KFN;
KFN: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
KO <= '0';
else
KO <= IKA or IKB or IKC;
end if;
end if;
end process KFN;
--
-- 5b Decoder Figure 12
--
-- Logic to determine complimenting A,B,C,D,E,I inputs
OR121 <= (P22 and (not AI and not CI and EEI))
or (P13 and not EI) ;
OR122 <= (AI and BI and EI and II)
or (not CI and not DI and not EI and not II)
or (P31 and II) ;
OR123 <= (P31 and II)
or (P22 and BI and CI and EEI)
or (P13 and DI and EI and II) ;
OR124 <= (P22 and AI and CI and EEI)
or (P13 and not EI) ;
OR125 <= (P13 and not EI)
or (not CI and not DI and not EI and not II)
or (not AI and not BI and not EI and not II) ;
OR126 <= (P22 and not AI and not CI and EEI)
or (P13 and not II) ;
OR127 <= (P13 and DI and EI and II)
or (P22 and not BI and not CI and EEI) ;
XA <= OR127
or OR121
or OR122 ;
XB <= OR122
or OR123
or OR124 ;
XC <= OR121
or OR123
or OR125 ;
XD <= OR122
or OR124
or OR127 ;
XE <= OR125
or OR126
or OR127 ;
-- PROCESS: DEC5B; Generate and latch LS 5 decoded bits
-- original:
-- DEC5B: process (RESET, RBYTECLK, XA, XB, XC, XD, XE, AI, BI, CI, DI, EI)
-- begin
-- if RESET = '1' then
-- AO <= '0' ;
-- BO <= '0' ;
-- CO <= '0' ;
-- DO <= '0' ;
-- EO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- AO <= XA XOR AI ; -- Least significant bit 0
-- BO <= XB XOR BI ;
-- CO <= XC XOR CI ;
-- DO <= XD XOR DI ;
-- EO <= XE XOR EI ; -- Most significant bit 6
-- end if;
-- end process DEC5B;
DEC5B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
else
AO <= XA XOR AI ; -- Least significant bit 0
BO <= XB XOR BI ;
CO <= XC XOR CI ;
DO <= XD XOR DI ;
EO <= XE XOR EI ; -- Most significant bit 6
end if;
end if;
end process DEC5B;
--
-- 3b Decoder - Figure 13
--
-- Logic for complimenting F,G,H outputs
OR131 <= (GI and HI and JI)
or (FI and HI and JI)
or (IOR134);
OR132 <= (FI and GI and JI)
or (not FI and not GI and not HI)
or (not FI and not GI and HI and JI);
OR133 <= (not FI and not HI and not JI)
or (IOR134)
or (not GI and not HI and not JI) ;
OR134 <= (not GI and not HI and not JI)
or (FI and HI and JI)
or (IOR134) ;
IOR134 <= (not (HI and JI))
and (not (not HI and not JI))
and (not CI and not DI and not EI and not II) ;
XF <= OR131
or OR132 ;
XG <= OR132
or OR133 ;
XH <= OR132
or OR134 ;
-- PROCESS: DEC3B; Generate and latch MS 3 decoded bits
-- original:
-- DEC3B: process (RESET, RBYTECLK, XF, XG, XH, FI, GI, HI)
-- begin
-- if RESET = '1' then
-- FO <= '0' ;
-- GO <= '0' ;
-- HO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK ='0' then
-- FO <= XF XOR FI ; -- Least significant bit 7
-- GO <= XG XOR GI ;
-- HO <= XH XOR HI ; -- Most significant bit 10
-- end if;
-- end process DEC3B ;
DEC3B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK ='0' then
if RESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
else
FO <= XF XOR FI ; -- Least significant bit 7
GO <= XG XOR GI ;
HO <= XH XOR HI ; -- Most significant bit 10
end if;
end if;
end process DEC3B ;
end behavioral;
|
-------------------------------------------------------------------------------
--
--! Title : 8b/10b Decoder
--! Design : 10-bit to 8-bit Decoder
-- Project : 8000 - 8b10b_encdec
--! Author : Ken Boyette
--! Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_dec.vhd
-- Version : 1.0
-- Generated : 09.27.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 10-bit to 9-bit encoding.
-- It accepts 10-bit encoded parallel data input and generates 8-bit decoded
-- data output in accordance with the 8b/10b standard method. This method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek. The method
-- WAS granted a U.S. Patent #4,486,739 in 1984; now expired.
--
-- The parallel 10-bit Binary input represent 1024 possible values, called
-- characters - only 268 of which are valid.
--
-- The input is a 10-bit encoded character whose bits are identified as:
-- AI, BI, CI, DI, EI, II, FI, GI, HI, JI (Least Significant to Most)
--
-- In addition to 256 data output characters, there are 12 special control
-- or K, characters defined for command and synchronization use.
--
-- The eight data output bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
--
-- The output, KO, is used to indicate the output value is one of the
-- control characters.
--
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent. The Figures
-- referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--! 8b/10b Decoder by Critia Computer, Inc.
entity dec_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (AH) -- syncronous now (13 JUL 2015)
RBYTECLK : in std_logic ; -- Master synchronous receive byte clock
AI, BI, CI, DI, EI, II : in std_logic ;
FI, GI, HI, JI : in std_logic ; -- Encoded input (LS..MS)
KO : out std_logic ; -- Control (K) character indicator (AH)
HO, GO, FO, EO, DO, CO, BO, AO : out std_logic -- Decoded out (MS..LS)
);
end dec_8b10b;
architecture behavioral of dec_8b10b is
-- Signals to tie things together
signal ANEB, CNED, EEI, P13, P22, P31 : std_logic := '0'; -- Figure 10 Signals
signal IKA, IKB, IKC : std_logic := '0'; -- Figure 11 Signals
signal XA, XB, XC, XD, XE : std_logic := '0'; -- Figure 12 Signals
signal OR121, OR122, OR123, OR124, OR125, OR126, OR127 : std_logic := '0';
signal XF, XG, XH : std_logic := '0'; -- Figure 13 Signals
signal OR131, OR132, OR133, OR134, IOR134 : std_logic := '0';
begin
--
-- 6b Input Function (Reference: Figure 10)
--
-- One 1 and three 0's
P13 <= (ANEB and (not CI and not DI))
or (CNED and (not AI and not BI)) ;
-- Three 1's and one 0
P31 <= (ANEB and CI and DI)
or (CNED and AI and BI) ;
-- Two 1's and two 0's
P22 <= (AI and BI and (not CI and not DI))
or (CI and DI and (not AI and not BI))
or (ANEB and CNED) ;
-- Intermediate term for "AI is Not Equal to BI"
ANEB <= AI xor BI ;
-- Intermediate term for "CI is Not Equal to DI"
CNED <= CI xor DI ;
-- Intermediate term for "E is Equal to I"
EEI <= EI xnor II ;
--
-- K Decoder - Figure 11
--
-- Intermediate terms
IKA <= (CI and DI and EI and II)
or (not CI and not DI and not EI and not II) ;
IKB <= P13 and (not EI and II and GI and HI and JI) ;
IKC <= P31 and (EI and not II and not GI and not HI and not JI) ;
-- PROCESS: KFN; Determine K output
-- original:
-- KFN: process (RESET, RBYTECLK, IKA, IKB, IKC)
-- begin
-- if RESET = '1' then
-- KO <= '0';
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- KO <= IKA or IKB or IKC;
-- end if;
-- end process KFN;
KFN: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
KO <= '0';
else
KO <= IKA or IKB or IKC;
end if;
end if;
end process KFN;
--
-- 5b Decoder Figure 12
--
-- Logic to determine complimenting A,B,C,D,E,I inputs
OR121 <= (P22 and (not AI and not CI and EEI))
or (P13 and not EI) ;
OR122 <= (AI and BI and EI and II)
or (not CI and not DI and not EI and not II)
or (P31 and II) ;
OR123 <= (P31 and II)
or (P22 and BI and CI and EEI)
or (P13 and DI and EI and II) ;
OR124 <= (P22 and AI and CI and EEI)
or (P13 and not EI) ;
OR125 <= (P13 and not EI)
or (not CI and not DI and not EI and not II)
or (not AI and not BI and not EI and not II) ;
OR126 <= (P22 and not AI and not CI and EEI)
or (P13 and not II) ;
OR127 <= (P13 and DI and EI and II)
or (P22 and not BI and not CI and EEI) ;
XA <= OR127
or OR121
or OR122 ;
XB <= OR122
or OR123
or OR124 ;
XC <= OR121
or OR123
or OR125 ;
XD <= OR122
or OR124
or OR127 ;
XE <= OR125
or OR126
or OR127 ;
-- PROCESS: DEC5B; Generate and latch LS 5 decoded bits
-- original:
-- DEC5B: process (RESET, RBYTECLK, XA, XB, XC, XD, XE, AI, BI, CI, DI, EI)
-- begin
-- if RESET = '1' then
-- AO <= '0' ;
-- BO <= '0' ;
-- CO <= '0' ;
-- DO <= '0' ;
-- EO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- AO <= XA XOR AI ; -- Least significant bit 0
-- BO <= XB XOR BI ;
-- CO <= XC XOR CI ;
-- DO <= XD XOR DI ;
-- EO <= XE XOR EI ; -- Most significant bit 6
-- end if;
-- end process DEC5B;
DEC5B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
else
AO <= XA XOR AI ; -- Least significant bit 0
BO <= XB XOR BI ;
CO <= XC XOR CI ;
DO <= XD XOR DI ;
EO <= XE XOR EI ; -- Most significant bit 6
end if;
end if;
end process DEC5B;
--
-- 3b Decoder - Figure 13
--
-- Logic for complimenting F,G,H outputs
OR131 <= (GI and HI and JI)
or (FI and HI and JI)
or (IOR134);
OR132 <= (FI and GI and JI)
or (not FI and not GI and not HI)
or (not FI and not GI and HI and JI);
OR133 <= (not FI and not HI and not JI)
or (IOR134)
or (not GI and not HI and not JI) ;
OR134 <= (not GI and not HI and not JI)
or (FI and HI and JI)
or (IOR134) ;
IOR134 <= (not (HI and JI))
and (not (not HI and not JI))
and (not CI and not DI and not EI and not II) ;
XF <= OR131
or OR132 ;
XG <= OR132
or OR133 ;
XH <= OR132
or OR134 ;
-- PROCESS: DEC3B; Generate and latch MS 3 decoded bits
-- original:
-- DEC3B: process (RESET, RBYTECLK, XF, XG, XH, FI, GI, HI)
-- begin
-- if RESET = '1' then
-- FO <= '0' ;
-- GO <= '0' ;
-- HO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK ='0' then
-- FO <= XF XOR FI ; -- Least significant bit 7
-- GO <= XG XOR GI ;
-- HO <= XH XOR HI ; -- Most significant bit 10
-- end if;
-- end process DEC3B ;
DEC3B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK ='0' then
if RESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
else
FO <= XF XOR FI ; -- Least significant bit 7
GO <= XG XOR GI ;
HO <= XH XOR HI ; -- Most significant bit 10
end if;
end if;
end process DEC3B ;
end behavioral;
|
-------------------------------------------------------------------------------
--
--! Title : 8b/10b Decoder
--! Design : 10-bit to 8-bit Decoder
-- Project : 8000 - 8b10b_encdec
--! Author : Ken Boyette
--! Company : Critia Computer, Inc.
--
-------------------------------------------------------------------------------
--
-- File : 8b10b_dec.vhd
-- Version : 1.0
-- Generated : 09.27.2006
-- By : Itf2Vhdl ver. 1.20
--
-------------------------------------------------------------------------------
--
-- Description :
-- This module provides 10-bit to 9-bit encoding.
-- It accepts 10-bit encoded parallel data input and generates 8-bit decoded
-- data output in accordance with the 8b/10b standard method. This method was
-- described in the 1983 IBM publication "A DC-Balanced, Partitioned-Block,
-- 8B/10B Transmission Code" by A.X. Widmer and P.A. Franaszek. The method
-- WAS granted a U.S. Patent #4,486,739 in 1984; now expired.
--
-- The parallel 10-bit Binary input represent 1024 possible values, called
-- characters - only 268 of which are valid.
--
-- The input is a 10-bit encoded character whose bits are identified as:
-- AI, BI, CI, DI, EI, II, FI, GI, HI, JI (Least Significant to Most)
--
-- In addition to 256 data output characters, there are 12 special control
-- or K, characters defined for command and synchronization use.
--
-- The eight data output bits are identified as:
-- HI, GI, FI, EI, DI, CI, BI, AI (Most Significant to Least)
--
-- The output, KO, is used to indicate the output value is one of the
-- control characters.
--
-- All inputs and outputs are synchronous with an externally supplied
-- byte rate clock BYTECLK.
-- The encoded output is valid one clock after the input.
-- There is a reset input, RESET, to reset the logic. The next rising
-- BYTECLK after RESET is deasserted latches valid input data.
--
-- Note: This VHDL structure closely follows the discrete logic defined
-- in the original article and the subsequent patent. The Figures
-- referenced are those in the patent.
-------------------------------------------------------------------------------
-- This program is licensed under the GPL
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
--! 8b/10b Decoder by Critia Computer, Inc.
entity dec_8b10b is
port(
RESET : in std_logic ; -- Global asynchronous reset (AH) -- syncronous now (13 JUL 2015)
RBYTECLK : in std_logic ; -- Master synchronous receive byte clock
AI, BI, CI, DI, EI, II : in std_logic ;
FI, GI, HI, JI : in std_logic ; -- Encoded input (LS..MS)
KO : out std_logic ; -- Control (K) character indicator (AH)
HO, GO, FO, EO, DO, CO, BO, AO : out std_logic -- Decoded out (MS..LS)
);
end dec_8b10b;
architecture behavioral of dec_8b10b is
-- Signals to tie things together
signal ANEB, CNED, EEI, P13, P22, P31 : std_logic := '0'; -- Figure 10 Signals
signal IKA, IKB, IKC : std_logic := '0'; -- Figure 11 Signals
signal XA, XB, XC, XD, XE : std_logic := '0'; -- Figure 12 Signals
signal OR121, OR122, OR123, OR124, OR125, OR126, OR127 : std_logic := '0';
signal XF, XG, XH : std_logic := '0'; -- Figure 13 Signals
signal OR131, OR132, OR133, OR134, IOR134 : std_logic := '0';
begin
--
-- 6b Input Function (Reference: Figure 10)
--
-- One 1 and three 0's
P13 <= (ANEB and (not CI and not DI))
or (CNED and (not AI and not BI)) ;
-- Three 1's and one 0
P31 <= (ANEB and CI and DI)
or (CNED and AI and BI) ;
-- Two 1's and two 0's
P22 <= (AI and BI and (not CI and not DI))
or (CI and DI and (not AI and not BI))
or (ANEB and CNED) ;
-- Intermediate term for "AI is Not Equal to BI"
ANEB <= AI xor BI ;
-- Intermediate term for "CI is Not Equal to DI"
CNED <= CI xor DI ;
-- Intermediate term for "E is Equal to I"
EEI <= EI xnor II ;
--
-- K Decoder - Figure 11
--
-- Intermediate terms
IKA <= (CI and DI and EI and II)
or (not CI and not DI and not EI and not II) ;
IKB <= P13 and (not EI and II and GI and HI and JI) ;
IKC <= P31 and (EI and not II and not GI and not HI and not JI) ;
-- PROCESS: KFN; Determine K output
-- original:
-- KFN: process (RESET, RBYTECLK, IKA, IKB, IKC)
-- begin
-- if RESET = '1' then
-- KO <= '0';
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- KO <= IKA or IKB or IKC;
-- end if;
-- end process KFN;
KFN: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
KO <= '0';
else
KO <= IKA or IKB or IKC;
end if;
end if;
end process KFN;
--
-- 5b Decoder Figure 12
--
-- Logic to determine complimenting A,B,C,D,E,I inputs
OR121 <= (P22 and (not AI and not CI and EEI))
or (P13 and not EI) ;
OR122 <= (AI and BI and EI and II)
or (not CI and not DI and not EI and not II)
or (P31 and II) ;
OR123 <= (P31 and II)
or (P22 and BI and CI and EEI)
or (P13 and DI and EI and II) ;
OR124 <= (P22 and AI and CI and EEI)
or (P13 and not EI) ;
OR125 <= (P13 and not EI)
or (not CI and not DI and not EI and not II)
or (not AI and not BI and not EI and not II) ;
OR126 <= (P22 and not AI and not CI and EEI)
or (P13 and not II) ;
OR127 <= (P13 and DI and EI and II)
or (P22 and not BI and not CI and EEI) ;
XA <= OR127
or OR121
or OR122 ;
XB <= OR122
or OR123
or OR124 ;
XC <= OR121
or OR123
or OR125 ;
XD <= OR122
or OR124
or OR127 ;
XE <= OR125
or OR126
or OR127 ;
-- PROCESS: DEC5B; Generate and latch LS 5 decoded bits
-- original:
-- DEC5B: process (RESET, RBYTECLK, XA, XB, XC, XD, XE, AI, BI, CI, DI, EI)
-- begin
-- if RESET = '1' then
-- AO <= '0' ;
-- BO <= '0' ;
-- CO <= '0' ;
-- DO <= '0' ;
-- EO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK = '0' then
-- AO <= XA XOR AI ; -- Least significant bit 0
-- BO <= XB XOR BI ;
-- CO <= XC XOR CI ;
-- DO <= XD XOR DI ;
-- EO <= XE XOR EI ; -- Most significant bit 6
-- end if;
-- end process DEC5B;
DEC5B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK = '0' then
if RESET = '1' then
AO <= '0' ;
BO <= '0' ;
CO <= '0' ;
DO <= '0' ;
EO <= '0' ;
else
AO <= XA XOR AI ; -- Least significant bit 0
BO <= XB XOR BI ;
CO <= XC XOR CI ;
DO <= XD XOR DI ;
EO <= XE XOR EI ; -- Most significant bit 6
end if;
end if;
end process DEC5B;
--
-- 3b Decoder - Figure 13
--
-- Logic for complimenting F,G,H outputs
OR131 <= (GI and HI and JI)
or (FI and HI and JI)
or (IOR134);
OR132 <= (FI and GI and JI)
or (not FI and not GI and not HI)
or (not FI and not GI and HI and JI);
OR133 <= (not FI and not HI and not JI)
or (IOR134)
or (not GI and not HI and not JI) ;
OR134 <= (not GI and not HI and not JI)
or (FI and HI and JI)
or (IOR134) ;
IOR134 <= (not (HI and JI))
and (not (not HI and not JI))
and (not CI and not DI and not EI and not II) ;
XF <= OR131
or OR132 ;
XG <= OR132
or OR133 ;
XH <= OR132
or OR134 ;
-- PROCESS: DEC3B; Generate and latch MS 3 decoded bits
-- original:
-- DEC3B: process (RESET, RBYTECLK, XF, XG, XH, FI, GI, HI)
-- begin
-- if RESET = '1' then
-- FO <= '0' ;
-- GO <= '0' ;
-- HO <= '0' ;
-- elsif RBYTECLK'event and RBYTECLK ='0' then
-- FO <= XF XOR FI ; -- Least significant bit 7
-- GO <= XG XOR GI ;
-- HO <= XH XOR HI ; -- Most significant bit 10
-- end if;
-- end process DEC3B ;
DEC3B: process (RBYTECLK)
begin
if RBYTECLK'event and RBYTECLK ='0' then
if RESET = '1' then
FO <= '0' ;
GO <= '0' ;
HO <= '0' ;
else
FO <= XF XOR FI ; -- Least significant bit 7
GO <= XG XOR GI ;
HO <= XH XOR HI ; -- Most significant bit 10
end if;
end if;
end process DEC3B ;
end behavioral;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-src.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
use qsim.qsim_types.all;
use random.random.all;
architecture source of test_bench is
signal a : arc_type;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(0),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => a,
info_detail => info_detail );
monitor : process is
variable L : line;
begin
wait on a;
write(L, string'("monitor: at "));
write(L, now, unit => ns);
write(L, string'(" received "));
write(L, a.token, ns);
writeline(output, L);
end process monitor;
end architecture source;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-src.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
use qsim.qsim_types.all;
use random.random.all;
architecture source of test_bench is
signal a : arc_type;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(0),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => a,
info_detail => info_detail );
monitor : process is
variable L : line;
begin
wait on a;
write(L, string'("monitor: at "));
write(L, now, unit => ns);
write(L, string'(" received "));
write(L, a.token, ns);
writeline(output, L);
end process monitor;
end architecture source;
|
-- Copyright (C) 1996 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: ch_19_tb-src.vhd,v 1.3 2001-10-26 16:29:36 paw Exp $
-- $Revision: 1.3 $
--
-- ---------------------------------------------------------------------
library qsim;
library random;
use std.textio.all;
use qsim.qsim_types.all;
use random.random.all;
architecture source of test_bench is
signal a : arc_type;
signal info_detail : info_detail_type := trace;
begin
source1 : entity qsim.source(behavior)
generic map ( name => "source1",
distribution => fixed, mean_inter_arrival_time => 100 ns,
seed => sample_seeds(0),
time_unit => ns,
info_file_name => "source1.dat" )
port map ( out_arc => a,
info_detail => info_detail );
monitor : process is
variable L : line;
begin
wait on a;
write(L, string'("monitor: at "));
write(L, now, unit => ns);
write(L, string'(" received "));
write(L, a.token, ns);
writeline(output, L);
end process monitor;
end architecture source;
|
library ieee;
use ieee.std_logic_1164.all;
entity revrng01 is
port (a : std_logic_vector (7 downto 0);
o : out std_logic_vector (7 downto 0));
end revrng01;
architecture behav of revrng01 is
function rev (v : std_logic_vector) return std_logic_vector
is
variable temp : std_logic_vector(v'reverse_range);
begin
for i in v'range loop
temp (i) := v (i);
end loop;
return temp;
end rev;
begin
o <= rev (a);
end behav;
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY UNISIM;
USE UNISIM.Vcomponents.ALL;
ENTITY decod_diz_decod_diz_sch_tb IS
END decod_diz_decod_diz_sch_tb;
ARCHITECTURE behavioral OF decod_diz_decod_diz_sch_tb IS
COMPONENT decod_diz
PORT( S_diz : OUT STD_LOGIC_VECTOR (6 DOWNTO 0);
E : IN STD_LOGIC_VECTOR (3 DOWNTO 0));
END COMPONENT;
SIGNAL S_diz : STD_LOGIC_VECTOR (6 DOWNTO 0);
SIGNAL E : STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
UUT: decod_diz PORT MAP(
S_diz => S_diz,
E => E
);
E <= "0000", "1010" after 20ns;
END;
|
---------------------------------------------------------------------------
--
-- (c) Copyright 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
---------------------------------------------------------------------------
-- Description:
-- This is an example testbench for the DDS Compiler
-- LogiCORE module. The testbench has been generated by the Xilinx
-- CORE Generator software to accompany the netlist you have generated.
--
-- This testbench is for demonstration purposes only. See note below for
-- instructions on how to use it with the netlist created for your core.
--
-- See the DDS Compiler datasheet for further information about this core.
--
---------------------------------------------------------------------------
-- Using this testbench
--
-- This testbench instantiates your generated DDS Compiler core
-- named "nco".
--
-- There are two versions of your core that you can use in this testbench:
-- the XilinxCoreLib behavioral model or the generated netlist.
--
-- 1. XilinxCoreLib behavioral model
-- Compile nco.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
-- 2. Generated netlist
-- Execute the following command in the directory containing your CORE
-- Generator output files, to create a VHDL netlist:
--
-- netgen -sim -ofmt vhdl nco.ngc nco_netlist.vhd
--
-- Compile nco_netlist.vhd into the work library. See your
-- simulator documentation for more information on how to do this.
--
---------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity tb_nco is
end tb_nco;
architecture tb of tb_nco is
-----------------------------------------------------------------------
-- Timing constants
-----------------------------------------------------------------------
constant CLOCK_PERIOD : time := 100 ns;
constant T_HOLD : time := 10 ns;
constant T_STROBE : time := CLOCK_PERIOD - (1 ns);
-----------------------------------------------------------------------
-- DUT input signals
-----------------------------------------------------------------------
-- General inputs
signal aclk : std_logic := '0'; -- the master clock
-- Data master channel signals
signal m_axis_data_tvalid : std_logic := '0'; -- payload is valid
signal m_axis_data_tdata : std_logic_vector(15 downto 0) := (others => '0'); -- data payload
-----------------------------------------------------------------------
-- Aliases for AXI channel TDATA and TUSER fields
-- These are a convenience for viewing data in a simulator waveform viewer.
-- If using ModelSim or Questa, add "-voptargs=+acc=n" to the vsim command
-- to prevent the simulator optimizing away these signals.
-----------------------------------------------------------------------
-- Data master channel alias signals
signal m_axis_data_tdata_cosine : std_logic_vector(9 downto 0) := (others => '0');
-- Alias signals for each separate TDM channel (these are 1 cycle delayed relative to the above alias signals)
signal m_axis_data_channel : integer := 0; -- indicates TDM channel number of data master channel outputs
signal m_axis_data_tdata_cosine_c0 : std_logic_vector(9 downto 0) := (others => '0');
signal m_axis_data_tdata_cosine_c1 : std_logic_vector(9 downto 0) := (others => '0');
begin
-----------------------------------------------------------------------
-- Instantiate the DUT
-----------------------------------------------------------------------
dut : entity work.nco
port map (
aclk => aclk
,m_axis_data_tvalid => m_axis_data_tvalid
,m_axis_data_tdata => m_axis_data_tdata
);
-----------------------------------------------------------------------
-- Generate clock
-----------------------------------------------------------------------
clock_gen : process
begin
aclk <= '0';
wait for CLOCK_PERIOD;
loop
aclk <= '0';
wait for CLOCK_PERIOD/2;
aclk <= '1';
wait for CLOCK_PERIOD/2;
end loop;
end process clock_gen;
-----------------------------------------------------------------------
-- Generate inputs
-----------------------------------------------------------------------
stimuli : process
begin
-- Drive inputs T_HOLD time after rising edge of clock
wait until rising_edge(aclk);
wait for T_HOLD;
-- Run for long enough to produce 5 periods of outputs
wait for CLOCK_PERIOD * 125018;
-- End of test
report "Not a real failure. Simulation finished successfully." severity failure;
wait;
end process stimuli;
-----------------------------------------------------------------------
-- Check outputs
-----------------------------------------------------------------------
check_outputs : process
variable check_ok : boolean := true;
begin
-- Check outputs T_STROBE time after rising edge of clock
wait until rising_edge(aclk);
wait for T_STROBE;
-- Do not check the output payload values, as this requires the behavioral model
-- which would make this demonstration testbench unwieldy.
-- Instead, check the protocol of the data master channel:
-- check that the payload is valid (not X) when TVALID is high
if m_axis_data_tvalid = '1' then
if is_x(m_axis_data_tdata) then
report "ERROR: m_axis_data_tdata is invalid when m_axis_data_tvalid is high" severity error;
check_ok := false;
end if;
end if;
assert check_ok
report "ERROR: terminating test with failures." severity failure;
end process check_outputs;
-----------------------------------------------------------------------
-- Assign TDATA fields to aliases, for easy simulator waveform viewing
-----------------------------------------------------------------------
-- Data master channel alias signals: update these only when they are valid
m_axis_data_tdata_cosine <= m_axis_data_tdata(9 downto 0) when m_axis_data_tvalid = '1';
-- Data master channel alias signals for each TDM channel
-- Note that these are one cycle later than the overall data master channel signals
process (aclk)
begin
if rising_edge(aclk) then
if m_axis_data_tvalid = '1' then
if m_axis_data_channel = 1 then
m_axis_data_channel <= 0;
else
m_axis_data_channel <= m_axis_data_channel + 1;
end if;
if m_axis_data_channel = 0 then
m_axis_data_tdata_cosine_c0 <= m_axis_data_tdata(9 downto 0);
elsif m_axis_data_channel = 1 then
m_axis_data_tdata_cosine_c1 <= m_axis_data_tdata(9 downto 0);
end if;
end if;
end if;
end process;
end tb;
|
architecture RTL of FIFO is
begin
PROC_LABEL : process
begin
end process;
-- Violations below
PROC_LABEL : process
begin
end process;
PROC_LABEL : process
begin
end process;
end architecture RTL;
|
architecture RTL of FIFO is
begin
PROC_LABEL : process
begin
end process;
-- Violations below
PROC_LABEL : process
begin
end process;
PROC_LABEL : process
begin
end process;
end architecture RTL;
|
--Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------
--Tool Version: Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016
--Date : Sun Apr 09 10:19:58 2017
--Host : GILAMONSTER running 64-bit major release (build 9200)
--Command : generate_target system.bd
--Design : system
--Purpose : IP block netlist
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity system is
port (
DDR_addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_ba : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_cas_n : inout STD_LOGIC;
DDR_ck_n : inout STD_LOGIC;
DDR_ck_p : inout STD_LOGIC;
DDR_cke : inout STD_LOGIC;
DDR_cs_n : inout STD_LOGIC;
DDR_dm : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dq : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_dqs_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_dqs_p : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_odt : inout STD_LOGIC;
DDR_ras_n : inout STD_LOGIC;
DDR_reset_n : inout STD_LOGIC;
DDR_we_n : inout STD_LOGIC;
FIXED_IO_ddr_vrn : inout STD_LOGIC;
FIXED_IO_ddr_vrp : inout STD_LOGIC;
FIXED_IO_mio : inout STD_LOGIC_VECTOR ( 53 downto 0 );
FIXED_IO_ps_clk : inout STD_LOGIC;
FIXED_IO_ps_porb : inout STD_LOGIC;
FIXED_IO_ps_srstb : inout STD_LOGIC;
config_finished_0 : out STD_LOGIC;
config_finished_1 : out STD_LOGIC;
data_0 : in STD_LOGIC_VECTOR ( 7 downto 0 );
data_1 : in STD_LOGIC_VECTOR ( 7 downto 0 );
gclk : out STD_LOGIC;
href_0 : in STD_LOGIC;
pclk_0 : in STD_LOGIC;
pclk_1 : in STD_LOGIC;
resend_0 : in STD_LOGIC;
resend_1 : in STD_LOGIC;
sioc_0 : out STD_LOGIC;
sioc_1 : out STD_LOGIC;
siod_0 : inout STD_LOGIC;
siod_1 : inout STD_LOGIC;
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_hs : out STD_LOGIC;
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_vs : out STD_LOGIC;
vsync_0 : in STD_LOGIC;
xclk_0 : out STD_LOGIC;
xclk_1 : out STD_LOGIC
);
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of system : entity is "system,IP_Integrator,{x_ipVendor=xilinx.com,x_ipLibrary=BlockDiagram,x_ipName=system,x_ipVersion=1.00.a,x_ipLanguage=VHDL,numBlks=7,numReposBlks=7,numNonXlnxBlks=1,numHierBlks=0,maxHierDepth=0,numSysgenBlks=0,numHlsBlks=0,numHdlrefBlks=0,numPkgbdBlks=0,bdsource=USER,da_ps7_cnt=1,synth_mode=OOC_per_IP}";
attribute HW_HANDOFF : string;
attribute HW_HANDOFF of system : entity is "system.hwdef";
end system;
architecture STRUCTURE of system is
component system_processing_system7_0_0 is
port (
TTC0_WAVE0_OUT : out STD_LOGIC;
TTC0_WAVE1_OUT : out STD_LOGIC;
TTC0_WAVE2_OUT : out STD_LOGIC;
USB0_PORT_INDCTL : out STD_LOGIC_VECTOR ( 1 downto 0 );
USB0_VBUS_PWRSELECT : out STD_LOGIC;
USB0_VBUS_PWRFAULT : in STD_LOGIC;
M_AXI_GP0_ARVALID : out STD_LOGIC;
M_AXI_GP0_AWVALID : out STD_LOGIC;
M_AXI_GP0_BREADY : out STD_LOGIC;
M_AXI_GP0_RREADY : out STD_LOGIC;
M_AXI_GP0_WLAST : out STD_LOGIC;
M_AXI_GP0_WVALID : out STD_LOGIC;
M_AXI_GP0_ARID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_AWID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_WID : out STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_ARBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_ARSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWBURST : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWLOCK : out STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_AWSIZE : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_AWPROT : out STD_LOGIC_VECTOR ( 2 downto 0 );
M_AXI_GP0_ARADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_AWADDR : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_WDATA : out STD_LOGIC_VECTOR ( 31 downto 0 );
M_AXI_GP0_ARCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ARQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWCACHE : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWLEN : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_AWQOS : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_WSTRB : out STD_LOGIC_VECTOR ( 3 downto 0 );
M_AXI_GP0_ACLK : in STD_LOGIC;
M_AXI_GP0_ARREADY : in STD_LOGIC;
M_AXI_GP0_AWREADY : in STD_LOGIC;
M_AXI_GP0_BVALID : in STD_LOGIC;
M_AXI_GP0_RLAST : in STD_LOGIC;
M_AXI_GP0_RVALID : in STD_LOGIC;
M_AXI_GP0_WREADY : in STD_LOGIC;
M_AXI_GP0_BID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_RID : in STD_LOGIC_VECTOR ( 11 downto 0 );
M_AXI_GP0_BRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RRESP : in STD_LOGIC_VECTOR ( 1 downto 0 );
M_AXI_GP0_RDATA : in STD_LOGIC_VECTOR ( 31 downto 0 );
FCLK_CLK0 : out STD_LOGIC;
FCLK_RESET0_N : out STD_LOGIC;
MIO : inout STD_LOGIC_VECTOR ( 53 downto 0 );
DDR_CAS_n : inout STD_LOGIC;
DDR_CKE : inout STD_LOGIC;
DDR_Clk_n : inout STD_LOGIC;
DDR_Clk : inout STD_LOGIC;
DDR_CS_n : inout STD_LOGIC;
DDR_DRSTB : inout STD_LOGIC;
DDR_ODT : inout STD_LOGIC;
DDR_RAS_n : inout STD_LOGIC;
DDR_WEB : inout STD_LOGIC;
DDR_BankAddr : inout STD_LOGIC_VECTOR ( 2 downto 0 );
DDR_Addr : inout STD_LOGIC_VECTOR ( 14 downto 0 );
DDR_VRN : inout STD_LOGIC;
DDR_VRP : inout STD_LOGIC;
DDR_DM : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQ : inout STD_LOGIC_VECTOR ( 31 downto 0 );
DDR_DQS_n : inout STD_LOGIC_VECTOR ( 3 downto 0 );
DDR_DQS : inout STD_LOGIC_VECTOR ( 3 downto 0 );
PS_SRSTB : inout STD_LOGIC;
PS_CLK : inout STD_LOGIC;
PS_PORB : inout STD_LOGIC
);
end component system_processing_system7_0_0;
component system_clk_wiz_0_0 is
port (
resetn : in STD_LOGIC;
clk_in1 : in STD_LOGIC;
clk_out1 : out STD_LOGIC;
locked : out STD_LOGIC
);
end component system_clk_wiz_0_0;
component system_zed_vga_0_0 is
port (
rgb565 : in STD_LOGIC_VECTOR ( 15 downto 0 );
vga_r : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_g : out STD_LOGIC_VECTOR ( 3 downto 0 );
vga_b : out STD_LOGIC_VECTOR ( 3 downto 0 )
);
end component system_zed_vga_0_0;
component system_vga_sync_0_0 is
port (
clk_25 : in STD_LOGIC;
rst : in STD_LOGIC;
active : out STD_LOGIC;
hsync : out STD_LOGIC;
vsync : out STD_LOGIC;
xaddr : out STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : out STD_LOGIC_VECTOR ( 9 downto 0 )
);
end component system_vga_sync_0_0;
component system_vga_color_test_0_0 is
port (
clk_25 : in STD_LOGIC;
xaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
yaddr : in STD_LOGIC_VECTOR ( 9 downto 0 );
rgb : out STD_LOGIC_VECTOR ( 23 downto 0 )
);
end component system_vga_color_test_0_0;
component system_inverter_0_0 is
port (
x : in STD_LOGIC;
x_not : out STD_LOGIC
);
end component system_inverter_0_0;
component system_rgb888_to_rgb565_0_0 is
port (
rgb_888 : in STD_LOGIC_VECTOR ( 23 downto 0 );
rgb_565 : out STD_LOGIC_VECTOR ( 15 downto 0 )
);
end component system_rgb888_to_rgb565_0_0;
signal clk_wiz_0_clk_out1 : STD_LOGIC;
signal inverter_0_x_not : STD_LOGIC;
signal processing_system7_0_DDR_ADDR : STD_LOGIC_VECTOR ( 14 downto 0 );
signal processing_system7_0_DDR_BA : STD_LOGIC_VECTOR ( 2 downto 0 );
signal processing_system7_0_DDR_CAS_N : STD_LOGIC;
signal processing_system7_0_DDR_CKE : STD_LOGIC;
signal processing_system7_0_DDR_CK_N : STD_LOGIC;
signal processing_system7_0_DDR_CK_P : STD_LOGIC;
signal processing_system7_0_DDR_CS_N : STD_LOGIC;
signal processing_system7_0_DDR_DM : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQ : STD_LOGIC_VECTOR ( 31 downto 0 );
signal processing_system7_0_DDR_DQS_N : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_DQS_P : STD_LOGIC_VECTOR ( 3 downto 0 );
signal processing_system7_0_DDR_ODT : STD_LOGIC;
signal processing_system7_0_DDR_RAS_N : STD_LOGIC;
signal processing_system7_0_DDR_RESET_N : STD_LOGIC;
signal processing_system7_0_DDR_WE_N : STD_LOGIC;
signal processing_system7_0_FCLK_CLK0 : STD_LOGIC;
signal processing_system7_0_FCLK_RESET0_N : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRN : STD_LOGIC;
signal processing_system7_0_FIXED_IO_DDR_VRP : STD_LOGIC;
signal processing_system7_0_FIXED_IO_MIO : STD_LOGIC_VECTOR ( 53 downto 0 );
signal processing_system7_0_FIXED_IO_PS_CLK : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_PORB : STD_LOGIC;
signal processing_system7_0_FIXED_IO_PS_SRSTB : STD_LOGIC;
signal rgb888_to_rgb565_0_rgb_565 : STD_LOGIC_VECTOR ( 15 downto 0 );
signal vga_color_test_0_rgb : STD_LOGIC_VECTOR ( 23 downto 0 );
signal vga_sync_0_hsync : STD_LOGIC;
signal vga_sync_0_vsync : STD_LOGIC;
signal vga_sync_0_xaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal vga_sync_0_yaddr : STD_LOGIC_VECTOR ( 9 downto 0 );
signal zed_vga_0_vga_b : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zed_vga_0_vga_g : STD_LOGIC_VECTOR ( 3 downto 0 );
signal zed_vga_0_vga_r : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_clk_wiz_0_locked_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED : STD_LOGIC;
signal NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED : STD_LOGIC_VECTOR ( 2 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED : STD_LOGIC_VECTOR ( 31 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED : STD_LOGIC_VECTOR ( 11 downto 0 );
signal NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_vga_sync_0_active_UNCONNECTED : STD_LOGIC;
begin
gclk <= processing_system7_0_FCLK_CLK0;
vga_b(3 downto 0) <= zed_vga_0_vga_b(3 downto 0);
vga_g(3 downto 0) <= zed_vga_0_vga_g(3 downto 0);
vga_hs <= vga_sync_0_hsync;
vga_r(3 downto 0) <= zed_vga_0_vga_r(3 downto 0);
vga_vs <= vga_sync_0_vsync;
config_finished_0 <= 'Z';
config_finished_1 <= 'Z';
sioc_0 <= 'Z';
sioc_1 <= 'Z';
xclk_0 <= 'Z';
xclk_1 <= 'Z';
clk_wiz_0: component system_clk_wiz_0_0
port map (
clk_in1 => processing_system7_0_FCLK_CLK0,
clk_out1 => clk_wiz_0_clk_out1,
locked => NLW_clk_wiz_0_locked_UNCONNECTED,
resetn => processing_system7_0_FCLK_RESET0_N
);
inverter_0: component system_inverter_0_0
port map (
x => processing_system7_0_FCLK_RESET0_N,
x_not => inverter_0_x_not
);
processing_system7_0: component system_processing_system7_0_0
port map (
DDR_Addr(14 downto 0) => DDR_addr(14 downto 0),
DDR_BankAddr(2 downto 0) => DDR_ba(2 downto 0),
DDR_CAS_n => DDR_cas_n,
DDR_CKE => DDR_cke,
DDR_CS_n => DDR_cs_n,
DDR_Clk => DDR_ck_p,
DDR_Clk_n => DDR_ck_n,
DDR_DM(3 downto 0) => DDR_dm(3 downto 0),
DDR_DQ(31 downto 0) => DDR_dq(31 downto 0),
DDR_DQS(3 downto 0) => DDR_dqs_p(3 downto 0),
DDR_DQS_n(3 downto 0) => DDR_dqs_n(3 downto 0),
DDR_DRSTB => DDR_reset_n,
DDR_ODT => DDR_odt,
DDR_RAS_n => DDR_ras_n,
DDR_VRN => FIXED_IO_ddr_vrn,
DDR_VRP => FIXED_IO_ddr_vrp,
DDR_WEB => DDR_we_n,
FCLK_CLK0 => processing_system7_0_FCLK_CLK0,
FCLK_RESET0_N => processing_system7_0_FCLK_RESET0_N,
MIO(53 downto 0) => FIXED_IO_mio(53 downto 0),
M_AXI_GP0_ACLK => processing_system7_0_FCLK_CLK0,
M_AXI_GP0_ARADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_ARBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARID_UNCONNECTED(11 downto 0),
M_AXI_GP0_ARLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_ARPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_ARREADY => '0',
M_AXI_GP0_ARSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_ARSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_ARVALID => NLW_processing_system7_0_M_AXI_GP0_ARVALID_UNCONNECTED,
M_AXI_GP0_AWADDR(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWADDR_UNCONNECTED(31 downto 0),
M_AXI_GP0_AWBURST(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWBURST_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWCACHE(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWCACHE_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWID_UNCONNECTED(11 downto 0),
M_AXI_GP0_AWLEN(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLEN_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWLOCK(1 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWLOCK_UNCONNECTED(1 downto 0),
M_AXI_GP0_AWPROT(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWPROT_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWQOS(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWQOS_UNCONNECTED(3 downto 0),
M_AXI_GP0_AWREADY => '0',
M_AXI_GP0_AWSIZE(2 downto 0) => NLW_processing_system7_0_M_AXI_GP0_AWSIZE_UNCONNECTED(2 downto 0),
M_AXI_GP0_AWVALID => NLW_processing_system7_0_M_AXI_GP0_AWVALID_UNCONNECTED,
M_AXI_GP0_BID(11 downto 0) => B"000000000000",
M_AXI_GP0_BREADY => NLW_processing_system7_0_M_AXI_GP0_BREADY_UNCONNECTED,
M_AXI_GP0_BRESP(1 downto 0) => B"00",
M_AXI_GP0_BVALID => '0',
M_AXI_GP0_RDATA(31 downto 0) => B"00000000000000000000000000000000",
M_AXI_GP0_RID(11 downto 0) => B"000000000000",
M_AXI_GP0_RLAST => '0',
M_AXI_GP0_RREADY => NLW_processing_system7_0_M_AXI_GP0_RREADY_UNCONNECTED,
M_AXI_GP0_RRESP(1 downto 0) => B"00",
M_AXI_GP0_RVALID => '0',
M_AXI_GP0_WDATA(31 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WDATA_UNCONNECTED(31 downto 0),
M_AXI_GP0_WID(11 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WID_UNCONNECTED(11 downto 0),
M_AXI_GP0_WLAST => NLW_processing_system7_0_M_AXI_GP0_WLAST_UNCONNECTED,
M_AXI_GP0_WREADY => '0',
M_AXI_GP0_WSTRB(3 downto 0) => NLW_processing_system7_0_M_AXI_GP0_WSTRB_UNCONNECTED(3 downto 0),
M_AXI_GP0_WVALID => NLW_processing_system7_0_M_AXI_GP0_WVALID_UNCONNECTED,
PS_CLK => FIXED_IO_ps_clk,
PS_PORB => FIXED_IO_ps_porb,
PS_SRSTB => FIXED_IO_ps_srstb,
TTC0_WAVE0_OUT => NLW_processing_system7_0_TTC0_WAVE0_OUT_UNCONNECTED,
TTC0_WAVE1_OUT => NLW_processing_system7_0_TTC0_WAVE1_OUT_UNCONNECTED,
TTC0_WAVE2_OUT => NLW_processing_system7_0_TTC0_WAVE2_OUT_UNCONNECTED,
USB0_PORT_INDCTL(1 downto 0) => NLW_processing_system7_0_USB0_PORT_INDCTL_UNCONNECTED(1 downto 0),
USB0_VBUS_PWRFAULT => '0',
USB0_VBUS_PWRSELECT => NLW_processing_system7_0_USB0_VBUS_PWRSELECT_UNCONNECTED
);
rgb888_to_rgb565_0: component system_rgb888_to_rgb565_0_0
port map (
rgb_565(15 downto 0) => rgb888_to_rgb565_0_rgb_565(15 downto 0),
rgb_888(23 downto 0) => vga_color_test_0_rgb(23 downto 0)
);
vga_color_test_0: component system_vga_color_test_0_0
port map (
clk_25 => clk_wiz_0_clk_out1,
rgb(23 downto 0) => vga_color_test_0_rgb(23 downto 0),
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
vga_sync_0: component system_vga_sync_0_0
port map (
active => NLW_vga_sync_0_active_UNCONNECTED,
clk_25 => clk_wiz_0_clk_out1,
hsync => vga_sync_0_hsync,
rst => inverter_0_x_not,
vsync => vga_sync_0_vsync,
xaddr(9 downto 0) => vga_sync_0_xaddr(9 downto 0),
yaddr(9 downto 0) => vga_sync_0_yaddr(9 downto 0)
);
zed_vga_0: component system_zed_vga_0_0
port map (
rgb565(15 downto 0) => rgb888_to_rgb565_0_rgb_565(15 downto 0),
vga_b(3 downto 0) => zed_vga_0_vga_b(3 downto 0),
vga_g(3 downto 0) => zed_vga_0_vga_g(3 downto 0),
vga_r(3 downto 0) => zed_vga_0_vga_r(3 downto 0)
);
end STRUCTURE;
|
-- Counts clock cycles elapsed since system startup
-- FIXME Maybe use a separate clock? VGA for example?
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.arch_defs.all;
use work.utils.all;
entity mmio_tsc is
port (
-- static
addr : in addr_t;
din: in word_t;
dout: out word_t;
size : in std_logic_vector(1 downto 0); -- is also enable when = "00"
wr : in std_logic;
en : in std_logic;
clk : in std_logic;
trap : out traps_t := TRAP_NONE
);
end mmio_tsc;
architecture mmio of mmio_tsc is
constant reading : std_logic := '0';
signal tstamp : word_t := ZERO;
signal data_out : word_t;
begin
dout <= data_out when en = '1' and wr = '0' else HI_Z;
process(clk) begin
if rising_edge(clk) then
if size /= "00" and en = '1' then
case wr is
when reading => data_out <= tstamp;
when others => null;
end case;
end if;
tstamp <= vec_increment(tstamp);
end if;
end process;
end;
|
--------------------------------------------------------------------------------
-- UART Receiver 19200/8N1 --
--------------------------------------------------------------------------------
-- Copyright (C)2011 Mathias Hörtnagl <[email protected]> --
-- --
-- This program is free software: you can redistribute it and/or modify --
-- it under the terms of the GNU General Public License as published by --
-- the Free Software Foundation, either version 3 of the License, or --
-- (at your option) any later version. --
-- --
-- This program is distributed in the hope that it will be useful, --
-- but WITHOUT ANY WARRANTY; without even the implied warranty of --
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the --
-- GNU General Public License for more details. --
-- --
-- You should have received a copy of the GNU General Public License --
-- along with this program. If not, see <http://www.gnu.org/licenses/>. --
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iwb.all;
use work.iuart.all;
entity uartr is
port(
si : in slave_in_t;
so : out slave_out_t;
-- Non-Wishbone Signals
RS232_DCE_RXD : in std_logic
);
end uartr;
architecture rtl of uartr is
type state_t is (Idle, Start, Data, Stop, Ack, Ack2);
type receiver_t is record
s : state_t; -- Receiver state.
n : natural range 0 to 15; -- Tick counter.
m : natural range 0 to 7; -- Data bits counter.
d : std_logic_vector(7 downto 0); -- Data bits shift register.
end record;
type rx_t is record
tick : std_logic;
rst : std_logic;
ack : std_logic;
end record;
signal rcv, rcvin : receiver_t;
signal rx : rx_t;
begin
-----------------------------------------------------------------------------
-- Receiver Rate Generator --
-----------------------------------------------------------------------------
rx_rate : counter
generic map(
FREQ => 50,
RATE => 19200
)
port map(
clk => si.clk,
rst => rx.rst,
tick => rx.tick
);
-----------------------------------------------------------------------------
-- Receiver Controller --
-----------------------------------------------------------------------------
receiver : process(RS232_DCE_RXD, rcv, rx.tick, si)
begin
rcvin <= rcv;
rx.rst <= '0';
rx.ack <= '0';
case rcv.s is
-- Wait for receive signal to be set low - Start of new data package.
when Idle =>
rx.rst <= '1';
if RS232_DCE_RXD = '0' then
rcvin.n <= 0;
rcvin.s <= Start;
end if;
when Start =>
if rx.tick = '1' then
if rcv.n = 7 then
rcvin.n <= 0;
rcvin.m <= 0;
rcvin.s <= Data;
else
rcvin.n <= rcv.n + 1;
end if;
end if;
-- Shift in all data bits. Least significant bit first.
when Data =>
if rx.tick = '1' then
if rcv.n = 15 then
rcvin.n <= 0;
rcvin.d <= RS232_DCE_RXD & rcv.d(7 downto 1);
if rcv.m = 7 then
rcvin.s <= Stop;
else
rcvin.m <= rcv.m + 1;
end if;
else
rcvin.n <= rcv.n + 1;
end if;
end if;
when Stop =>
if rx.tick = '1' then
if rcv.n = 15 then
rcvin.s <= Ack;
else
rcvin.n <= rcv.n + 1;
end if;
end if;
when Ack =>
if wb_read(si) then
rx.ack <= '1';
rcvin.s <= Ack2;
end if;
when Ack2 =>
rx.ack <= '1';
if si.stb = '0' then
rcvin.s <= Idle;
end if;
end case;
end process;
so.dat <= x"0000" & rx.ack & "0000000" & rcv.d;
so.ack <= rx.ack;
-----------------------------------------------------------------------------
-- Registers --
-----------------------------------------------------------------------------
reg : process(si.clk)
begin
if rising_edge(si.clk) then
rcv <= rcvin;
if si.rst = '1' then
rcv.s <= Idle;
end if;
end if;
end process;
end rtl; |
-------------------------------------------------------------------------------
--
-- File: AD96xx_92xxSPI_Model.vhd
-- Author: Tudor Gherman
-- Original Project: ZmodScopeController
-- Date: 11 Dec. 2020
--
-------------------------------------------------------------------------------
-- (c) 2020 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Simulation model for the AD9648 ADC. Currently only the configuration SPI
-- interface implemented. The following conditions are tested:
-- 1. sSpiClk pulse high and low times are respected
-- 2. sSpiClk maximum and minimum (optional) frequency
-- 3. sCS to sSPI_Clk setup and hold times are respected
-- 4. sCS has no glitches during the 1 data byte transaction supported
-- 5. decodes command word and input data for write transactions
-- 6. generates output data byte for read transactions
-- 7. sSDIO to sSPI_Clk setup and hold times are respected
-- 8. No transitions occur on sSDIO and sCS during the idle state
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.PkgZmodADC.all;
entity AD96xx_92xxSPI_Model is
Generic (
-- Parameter identifying the Zmod:
-- 0 -> Zmod Scope 1410 - 105 (AD9648)
-- 1 -> Zmod Scope 1010 - 40 (AD9204)
-- 2 -> Zmod Scope 1010 - 125 (AD9608)
-- 3 -> Zmod Scope 1210 - 40 (AD9231)
-- 4 -> Zmod Scope 1210 - 125 (AD9628)
-- 5 -> Zmod Scope 1410 - 40 (AD9251)
-- 6 -> Zmod Scope 1410 - 125 (AD9648)
kZmodID : integer range 0 to 6 := 0;
-- The number of data bits for the data phase of the transaction:
-- only 8 data bits currently supported.
kDataWidth : integer range 0 to 63 := 8;
-- The number of bits of the command phase of the SPI transaction.
kCommandWidth : integer range 0 to 63 := 8
);
Port (
-- 100MHz clock used by the AD9648_RegisterDecode block
SysClk100 : in STD_LOGIC;
-- Reset signal asynchronously asserted and synchronously
-- de-asserted (in SysClk100 domain)
asRst_n : in STD_LOGIC;
-- When InsertError is asserted the model produces an erroneous
-- reading for register address x01
InsertError : in STD_LOGIC;
-- 2 wire SPI interface
sSPI_Clk : in STD_LOGIC;
sSDIO : inout STD_LOGIC := 'Z';
sCS : in STD_LOGIC
);
end AD96xx_92xxSPI_Model;
architecture Behavioral of AD96xx_92xxSPI_Model is
signal sR_W_Decode : std_logic;
signal sWidthDecode : std_logic_vector(1 downto 0);
signal sAddrDecode : std_logic_vector(kCommandWidth - 4 downto 0);
signal sAddrDecodeReady : std_logic;
signal sDataWriteDecodeReady : std_logic;
signal sTransactionInProgress : boolean := false;
signal sDataDecode : std_logic_vector(kDataWidth-1 downto 0);
signal sSPI_ClkRising : time := 0 ns;
signal sSPI_ClkCounter : integer := 0;
signal sLastSPI_ClkEdge : time := 0ns;
signal sLastSPI_ClkRisingEdge : time := 0ns;
signal sSclkHigh : time := 0ns;
signal sRegDataOut : std_logic_vector(kDataWidth-1 downto 0) := x"00";
begin
AD9648_RegisterDecode_inst: entity work.AD96xx_92xx_RegisterDecode
Generic Map(
kZmodID => kZmodID,
kAddrWidth => kCommandWidth-3,
kRegDataWidth => kDataWidth
)
Port Map(
SysClk100 => SysClk100,
asRst_n => asRst_n,
InsertError => InsertError,
sDataWriteDecodeReady => sDataWriteDecodeReady,
sAddrDecodeReady => sAddrDecodeReady,
sDataDecode => sDataDecode,
sAddrDecode => sAddrDecode,
sRegDataOut => sRegDataOut
);
-- ADC Main process; checks for:
-- 1. sSpiClk pulse high and low times are respected.
-- 2. sSpiClk maximum and minimum (optional) frequency.
-- 3. sCS to sSPI_Clk setup and hold times are respected.
-- 4. sCS has no glitches during the 1 data byte transaction supported.
-- 5. decodes command word and input data for write transactions.
-- 6. generates output data byte for read transactions.
-- A sSPI_Clk falling edge is expected before sCS is pulled high.
ADC_Main: process
begin
sAddrDecodeReady <= '0';
sDataWriteDecodeReady <= '0';
if (sCS /= '0') then
wait until sCS = '0';
end if;
sSPI_ClkCounter <= 0;
sTransactionInProgress <= true;
sSDIO <= 'Z';
-- Wait for first sSPI_Clk rising edge
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
-- First clock rising edge detected
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
sR_W_Decode <= sSDIO;
-- Check sCS to sSPI_Clk setup time
assert ((sCS'delayed'last_event) >= ktS)
report "setup time between sCS and sSPI_Clk is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktS) & LF & HT & HT &
"Actual: " & time'image(sCS'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk pulse width high for MSB
wait until sSPI_Clk = '0';
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "sSPI_Clk pulse width high is smaller than minimum allowed for command MSB." & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Repeat for the following kCommandWidth-1 sSPI_Clk periods
for i in (kCommandWidth - 2) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for command bit" & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
if (i = kCommandWidth - 2) then
sWidthDecode(1) <= sSDIO;
elsif (i = kCommandWidth - 3) then
sWidthDecode(0) <= sSDIO;
else
sAddrDecode(i) <= sSDIO;
if (i=0) then
sAddrDecodeReady <= '1';
end if;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for command bit" & integer'image(i)& LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Drive first data byte when bus changes direction
if (i=0) then
if (sR_W_Decode = '1') then
sSDIO <= sRegDataOut(7);
end if;
sAddrDecodeReady <= '0';
end if;
end loop;
for i in (kDataWidth - 1) downto 0 loop
wait until sSPI_Clk = '1';
sSPI_ClkCounter <= sSPI_ClkCounter + 1;
sLastSPI_ClkRisingEdge <= now;
-- Check sSPI_Clk pulse width low
assert ((sSPI_Clk'delayed'last_event) >= kSclkLow)
report "sSPI_Clk pulse width low is smaller than minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is smaller than the max allowed
assert ((sSPI_Clk'delayed'last_event + sSclkHigh) >= kSclkT_Min)
report "sSPI_Clk period is smaller than the minimum allowed for data bit " & integer'image(i+1) & LF & HT & HT &
"Expected: " & time'image(kSclkT_Min) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event + sSclkHigh)
severity ERROR;
-- Check sSPI_Clk frequency (measure between two consecutive rising edges) is higher than the min allowed
-- assert ((aSclkLow + sSclkHigh) <= kSclkT_Max)
-- report "sSPI_Clk period is higher than the maximum allowed." & LF & HT & HT &
-- "Expected: " & time'image(kSclkT_Max) & LF & HT & HT &
-- "Actual: " & time'image(aSclkLow + sSclkHigh)
-- severity ERROR;
-- Sample sSDIO on rising edge for write operations
if (sR_W_Decode = '0') then
sDataDecode(i) <= sSDIO;
end if;
-- Wait sSPI_Clk falling edge
wait until sSPI_Clk = '0';
-- Check sSPI_Clk pulse width high
assert ((sSPI_Clk'delayed'last_event) >= kSclkHigh)
report "aSCK pulse width high is smaller than minimum allowed for data bit" & integer'image(i) & LF & HT & HT &
"Expected: " & time'image(kSclkHigh) & LF & HT & HT &
"Actual: " & time'image(sSPI_Clk'delayed'last_event)
severity ERROR;
sSclkHigh <= sSPI_Clk'delayed'last_event;
-- Assign SDIO on falling edge for read operations
if (sR_W_Decode = '1') then
if (i > 0) then
sSDIO <= sRegDataOut(i-1);
else
sSDIO <= 'Z';
end if;
else
if (i=0) then
sDataWriteDecodeReady <= '1';
end if;
end if;
end loop;
sLastSPI_ClkEdge <= now;
sTransactionInProgress <= false;
wait until sCS = '1';
-- Check hold time between SCLK and sCS
assert ((now - sLastSPI_ClkRisingEdge) >= ktH)
report "Hold time (sCS to sSPI_Clk) is smaller than the minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktH) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkRisingEdge)
severity ERROR;
-- Check if no more than 24 bits transferred
assert ((now - sLastSPI_ClkEdge) = sSPI_Clk'last_event)
report "More than 24 bits transfered for current transaction." & LF & HT & HT
severity FAILURE;
-- Check last sSPI_Clk pulse low duration
assert ((now - sLastSPI_ClkEdge) >= kSclkLow)
report "aSCK pulse width low is smaller than minimum allowed data bit 0" & LF & HT & HT &
"Expected: " & time'image(kSclkLow) & LF & HT & HT &
"Actual: " & time'image(now - sLastSPI_ClkEdge)
severity ERROR;
end process ADC_Main;
-- Check if sCS low pulse is held low for the entire transaction
CheckCS: process
begin
if (sCS /= '0') then
wait until sCS = '0';
end if;
wait until sCS = '1';
assert (sTransactionInProgress = false)
report "CS pulse high during transaction." & LF & HT & HT
severity FAILURE;
end process CheckCS;
-- Check if sSDIO to sSPI_Clk setup time is respected
CheckSetup: process
begin
if (sSPI_Clk /= '0') then
wait until sSPI_Clk = '0';
end if;
wait until sSPI_Clk = '1';
sSPI_ClkRising <= now;
-- Check Setup Time
assert (sSDIO'last_active >= ktDS)
report "Setup time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDS) & LF & HT & HT &
"Actual: " & time'image(sSDIO'last_active)
severity ERROR;
end process CheckSetup;
-- Check if sSDIO to sSPI_Clk hold time is respected
CheckHold: process
begin
-- Wait for first clock rising edge
wait until sSPI_ClkRising /= 0 ns;
-- Wait for SDIO next bit to be assigned
wait until sSDIO'event;
-- Check Hold Time
assert ((now - sSPI_ClkRising) >= ktDH)
report "Hold time (data to sSPI_Clk) is smaller than minimum allowed." & LF & HT & HT &
"Expected: " & time'image(ktDH) & LF & HT & HT &
"Actual: " & time'image(now - sSPI_ClkRising)
severity ERROR;
end process CheckHold;
-- Check sSDIO idle condition
CheckSDIO_Idle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSDIO = '0')
report "SDIO idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSDIO signal and check if they occur during the idle state (sCS = '1');
wait until sSDIO'event;
assert (sCS = '0')
report "SDIO idle condition not respected."
severity WARNING;
end process CheckSDIO_Idle;
CheckSPI_ClkIdle: process
begin
wait until now /= 0 ps;
if (sCS = '0') then
wait until sCS = '1';
end if;
-- Check that sSDIO is in '0' when entering the idle state
assert (sSPI_Clk = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
-- Monitor all changes on the sSPI_Clk signal and check if they occur during the idle state (sCS = '1');
wait until sSPI_Clk'event;
assert (sCS = '0')
report "sSPI_Clk idle condition not respected."
severity WARNING;
end process CheckSPI_ClkIdle;
end Behavioral; |
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_SYNC is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
Q : out vl_logic
);
end F2DSS_ACE_MISC_SYNC;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_SYNC is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
Q : out vl_logic
);
end F2DSS_ACE_MISC_SYNC;
|
library verilog;
use verilog.vl_types.all;
entity F2DSS_ACE_MISC_SYNC is
port(
PCLK : in vl_logic;
PRESETN : in vl_logic;
D : in vl_logic;
Q : out vl_logic
);
end F2DSS_ACE_MISC_SYNC;
|
architecture rtl of fifo is
type t_record is
record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is
record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is
record
a : std_logic;
b : std_logic;
end record t_record;
type t_record is record a : std_logic; b : std_logic; end record;
type t_record is record
a : std_logic;
b : std_logic;
end record t_record;
begin
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator v8.4 Core - Top-level core wrapper
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: ssd_command_fifo_top_wrapper.vhd
--
-- Description:
-- This file is needed for core instantiation in production testbench
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
entity ssd_command_fifo_top_wrapper is
PORT (
CLK : IN STD_LOGIC;
BACKUP : IN STD_LOGIC;
BACKUP_MARKER : IN STD_LOGIC;
DIN : IN STD_LOGIC_VECTOR(128-1 downto 0);
PROG_EMPTY_THRESH : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_EMPTY_THRESH_ASSERT : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_EMPTY_THRESH_NEGATE : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH_ASSERT : IN STD_LOGIC_VECTOR(6-1 downto 0);
PROG_FULL_THRESH_NEGATE : IN STD_LOGIC_VECTOR(6-1 downto 0);
RD_CLK : IN STD_LOGIC;
RD_EN : IN STD_LOGIC;
RD_RST : IN STD_LOGIC;
RST : IN STD_LOGIC;
SRST : IN STD_LOGIC;
WR_CLK : IN STD_LOGIC;
WR_EN : IN STD_LOGIC;
WR_RST : IN STD_LOGIC;
INJECTDBITERR : IN STD_LOGIC;
INJECTSBITERR : IN STD_LOGIC;
ALMOST_EMPTY : OUT STD_LOGIC;
ALMOST_FULL : OUT STD_LOGIC;
DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
DOUT : OUT STD_LOGIC_VECTOR(128-1 downto 0);
EMPTY : OUT STD_LOGIC;
FULL : OUT STD_LOGIC;
OVERFLOW : OUT STD_LOGIC;
PROG_EMPTY : OUT STD_LOGIC;
PROG_FULL : OUT STD_LOGIC;
VALID : OUT STD_LOGIC;
RD_DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
UNDERFLOW : OUT STD_LOGIC;
WR_ACK : OUT STD_LOGIC;
WR_DATA_COUNT : OUT STD_LOGIC_VECTOR(7-1 downto 0);
SBITERR : OUT STD_LOGIC;
DBITERR : OUT STD_LOGIC;
-- AXI Global Signal
M_ACLK : IN std_logic;
S_ACLK : IN std_logic;
S_ARESETN : IN std_logic;
M_ACLK_EN : IN std_logic;
S_ACLK_EN : IN std_logic;
-- AXI Full/Lite Slave Write Channel (write side)
S_AXI_AWID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_AWLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_AWSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_AWCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_AWQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_AWUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_AWVALID : IN std_logic;
S_AXI_AWREADY : OUT std_logic;
S_AXI_WID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_WDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXI_WSTRB : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_WLAST : IN std_logic;
S_AXI_WUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_WVALID : IN std_logic;
S_AXI_WREADY : OUT std_logic;
S_AXI_BID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_BRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_BUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_BVALID : OUT std_logic;
S_AXI_BREADY : IN std_logic;
-- AXI Full/Lite Master Write Channel (Read side)
M_AXI_AWID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_AWLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_AWSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_AWCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_AWQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_AWUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_AWVALID : OUT std_logic;
M_AXI_AWREADY : IN std_logic;
M_AXI_WID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_WDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXI_WSTRB : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_WLAST : OUT std_logic;
M_AXI_WUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_WVALID : OUT std_logic;
M_AXI_WREADY : IN std_logic;
M_AXI_BID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_BRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_BUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_BVALID : IN std_logic;
M_AXI_BREADY : OUT std_logic;
-- AXI Full/Lite Slave Read Channel (Write side)
S_AXI_ARID : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARADDR : IN std_logic_vector(32-1 DOWNTO 0);
S_AXI_ARLEN : IN std_logic_vector(8-1 DOWNTO 0);
S_AXI_ARSIZE : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARBURST : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARLOCK : IN std_logic_vector(2-1 DOWNTO 0);
S_AXI_ARCACHE : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARPROT : IN std_logic_vector(3-1 DOWNTO 0);
S_AXI_ARQOS : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARREGION : IN std_logic_vector(4-1 DOWNTO 0);
S_AXI_ARUSER : IN std_logic_vector(1-1 DOWNTO 0);
S_AXI_ARVALID : IN std_logic;
S_AXI_ARREADY : OUT std_logic;
S_AXI_RID : OUT std_logic_vector(4-1 DOWNTO 0);
S_AXI_RDATA : OUT std_logic_vector(64-1 DOWNTO 0);
S_AXI_RRESP : OUT std_logic_vector(2-1 DOWNTO 0);
S_AXI_RLAST : OUT std_logic;
S_AXI_RUSER : OUT std_logic_vector(1-1 DOWNTO 0);
S_AXI_RVALID : OUT std_logic;
S_AXI_RREADY : IN std_logic;
-- AXI Full/Lite Master Read Channel (Read side)
M_AXI_ARID : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARADDR : OUT std_logic_vector(32-1 DOWNTO 0);
M_AXI_ARLEN : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXI_ARSIZE : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARBURST : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARLOCK : OUT std_logic_vector(2-1 DOWNTO 0);
M_AXI_ARCACHE : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARPROT : OUT std_logic_vector(3-1 DOWNTO 0);
M_AXI_ARQOS : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARREGION : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXI_ARUSER : OUT std_logic_vector(1-1 DOWNTO 0);
M_AXI_ARVALID : OUT std_logic;
M_AXI_ARREADY : IN std_logic;
M_AXI_RID : IN std_logic_vector(4-1 DOWNTO 0);
M_AXI_RDATA : IN std_logic_vector(64-1 DOWNTO 0);
M_AXI_RRESP : IN std_logic_vector(2-1 DOWNTO 0);
M_AXI_RLAST : IN std_logic;
M_AXI_RUSER : IN std_logic_vector(1-1 DOWNTO 0);
M_AXI_RVALID : IN std_logic;
M_AXI_RREADY : OUT std_logic;
-- AXI Streaming Slave Signals (Write side)
S_AXIS_TVALID : IN std_logic;
S_AXIS_TREADY : OUT std_logic;
S_AXIS_TDATA : IN std_logic_vector(64-1 DOWNTO 0);
S_AXIS_TSTRB : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TKEEP : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TLAST : IN std_logic;
S_AXIS_TID : IN std_logic_vector(8-1 DOWNTO 0);
S_AXIS_TDEST : IN std_logic_vector(4-1 DOWNTO 0);
S_AXIS_TUSER : IN std_logic_vector(4-1 DOWNTO 0);
-- AXI Streaming Master Signals (Read side)
M_AXIS_TVALID : OUT std_logic;
M_AXIS_TREADY : IN std_logic;
M_AXIS_TDATA : OUT std_logic_vector(64-1 DOWNTO 0);
M_AXIS_TSTRB : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TKEEP : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TLAST : OUT std_logic;
M_AXIS_TID : OUT std_logic_vector(8-1 DOWNTO 0);
M_AXIS_TDEST : OUT std_logic_vector(4-1 DOWNTO 0);
M_AXIS_TUSER : OUT std_logic_vector(4-1 DOWNTO 0);
-- AXI Full/Lite Write Address Channel Signals
AXI_AW_INJECTSBITERR : IN std_logic;
AXI_AW_INJECTDBITERR : IN std_logic;
AXI_AW_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AW_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AW_SBITERR : OUT std_logic;
AXI_AW_DBITERR : OUT std_logic;
AXI_AW_OVERFLOW : OUT std_logic;
AXI_AW_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Data Channel Signals
AXI_W_INJECTSBITERR : IN std_logic;
AXI_W_INJECTDBITERR : IN std_logic;
AXI_W_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_W_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_W_SBITERR : OUT std_logic;
AXI_W_DBITERR : OUT std_logic;
AXI_W_OVERFLOW : OUT std_logic;
AXI_W_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Write Response Channel Signals
AXI_B_INJECTSBITERR : IN std_logic;
AXI_B_INJECTDBITERR : IN std_logic;
AXI_B_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_B_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_B_SBITERR : OUT std_logic;
AXI_B_DBITERR : OUT std_logic;
AXI_B_OVERFLOW : OUT std_logic;
AXI_B_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Address Channel Signals
AXI_AR_INJECTSBITERR : IN std_logic;
AXI_AR_INJECTDBITERR : IN std_logic;
AXI_AR_PROG_FULL_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_PROG_EMPTY_THRESH : IN std_logic_vector(4-1 DOWNTO 0);
AXI_AR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_WR_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_RD_DATA_COUNT : OUT std_logic_vector(4 DOWNTO 0);
AXI_AR_SBITERR : OUT std_logic;
AXI_AR_DBITERR : OUT std_logic;
AXI_AR_OVERFLOW : OUT std_logic;
AXI_AR_UNDERFLOW : OUT std_logic;
-- AXI Full/Lite Read Data Channel Signals
AXI_R_INJECTSBITERR : IN std_logic;
AXI_R_INJECTDBITERR : IN std_logic;
AXI_R_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXI_R_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXI_R_SBITERR : OUT std_logic;
AXI_R_DBITERR : OUT std_logic;
AXI_R_OVERFLOW : OUT std_logic;
AXI_R_UNDERFLOW : OUT std_logic;
-- AXI Streaming FIFO Related Signals
AXIS_INJECTSBITERR : IN std_logic;
AXIS_INJECTDBITERR : IN std_logic;
AXIS_PROG_FULL_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_PROG_EMPTY_THRESH : IN std_logic_vector(10-1 DOWNTO 0);
AXIS_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_WR_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_RD_DATA_COUNT : OUT std_logic_vector(10 DOWNTO 0);
AXIS_SBITERR : OUT std_logic;
AXIS_DBITERR : OUT std_logic;
AXIS_OVERFLOW : OUT std_logic;
AXIS_UNDERFLOW : OUT std_logic);
end ssd_command_fifo_top_wrapper;
architecture xilinx of ssd_command_fifo_top_wrapper is
SIGNAL clk_i : std_logic;
component ssd_command_fifo_top is
PORT (
CLK : IN std_logic;
DATA_COUNT : OUT std_logic_vector(7-1 DOWNTO 0);
RST : IN std_logic;
WR_EN : IN std_logic;
RD_EN : IN std_logic;
DIN : IN std_logic_vector(128-1 DOWNTO 0);
DOUT : OUT std_logic_vector(128-1 DOWNTO 0);
FULL : OUT std_logic;
EMPTY : OUT std_logic);
end component;
begin
clk_i <= CLK;
fg1 : ssd_command_fifo_top
PORT MAP (
CLK => clk_i,
DATA_COUNT => data_count,
RST => rst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
end xilinx;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task3_TB\Task3_tb2.vhd
-- Generated : 10/18/14 16:08:55
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task3.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task3_ent_tb2 is
end entity Task3_ent_tb2;
architecture Task3_arch_tb2 of Task3_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task3 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task3;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_Sreg0_type is (S0, S1, S2, S3, S4, any_state);
signal test_Sreg0 : test_Sreg0_type;
begin
UUT : Task3
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_Sreg0 <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_Sreg0 <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_Sreg0 <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_Sreg0 <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_Sreg0 <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
-- Test length 11
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task3_arch_tb2;
configuration Task3_cfg_tb2 of Task3_ent_tb2 is
for Task3_arch_tb2
for UUT : Task3 use entity work.Task3(Beh);
end for;
end for;
end Task3_cfg_tb2;
|
-------------------------------------------------------------------------------
--
-- Title : No Title
-- Design :
-- Author : Shadowmaker
-- Company : Home
--
-------------------------------------------------------------------------------
--
-- File : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task3_TB\Task3_tb2.vhd
-- Generated : 10/18/14 16:08:55
-- From : E:\Embedded\Projects\POCP\Lab05\Lab05\src\Task3.asf
-- By : ASFTEST ver. v.2.1.3 build 56, August 25, 2005
--
-------------------------------------------------------------------------------
--
-- Description :
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
library IEEE;
use IEEE.STD_LOGIC_TEXTIO.all;
use STD.TEXTIO.all;
entity Task3_ent_tb2 is
end entity Task3_ent_tb2;
architecture Task3_arch_tb2 of Task3_ent_tb2 is
constant delay_wr_in : Time := 5 ns;
constant delay_pos_edge : Time := 5 ns;
constant delay_wr_out : Time := 5 ns;
constant delay_neg_edge : Time := 5 ns;
file RESULTS : Text open WRITE_MODE is "results.txt";
procedure WRITE_RESULTS(
constant CLK : in Std_logic;
constant RST : in Std_logic;
constant IP : in Std_logic_Vector (3 downto 0);
constant OP : in Std_logic_Vector (1 downto 0)
) is
variable l_out : Line;
begin
WRITE(l_out, now, right, 15, ps);
-- write input signals
WRITE(l_out, CLK, right, 8);
WRITE(l_out, RST, right, 8);
WRITE(l_out, IP, right, 11);
-- write output signals
WRITE(l_out, OP, right, 9);
WRITELINE(RESULTS, l_out);
end;
component Task3 is
port(
CLK : in Std_logic;
RST : in Std_logic;
IP : in Std_logic_Vector (3 downto 0);
OP :out Std_logic_Vector (1 downto 0));
end component; -- Task3;
signal CLK : Std_logic;
signal RST : Std_logic;
signal IP : Std_logic_Vector (3 downto 0);
signal OP : Std_logic_Vector (1 downto 0);
signal cycle_num : Integer; -- takt number
-- this signal is added for compare test simulation results only
type test_Sreg0_type is (S0, S1, S2, S3, S4, any_state);
signal test_Sreg0 : test_Sreg0_type;
begin
UUT : Task3
port map(
CLK => CLK,
RST => RST,
IP => IP,
OP => OP);
STIMULI : process
begin
-- Test for all transition of finite state machine
CLK <= '0';
cycle_num <= 0;
wait for delay_wr_in;
RST <= '1';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 1;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S0;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S0
CLK <= '0';
cycle_num <= 2;
wait for delay_wr_in;
RST <= '0';
IP <= "0011";
wait for delay_pos_edge;
test_Sreg0 <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 3;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
CLK <= '0';
cycle_num <= 4;
wait for delay_wr_in;
RST <= '0';
IP <= "1111";
wait for delay_pos_edge;
test_Sreg0 <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 5;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S4;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S4
CLK <= '0';
cycle_num <= 6;
wait for delay_wr_in;
RST <= '0';
IP <= "1101";
wait for delay_pos_edge;
test_Sreg0 <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 7;
wait for delay_wr_in;
RST <= '0';
IP <= "0001";
wait for delay_pos_edge;
test_Sreg0 <= S3;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S3
CLK <= '0';
cycle_num <= 8;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 9;
wait for delay_wr_in;
RST <= '0';
IP <= "0000";
wait for delay_pos_edge;
test_Sreg0 <= S2;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S2
CLK <= '0';
cycle_num <= 10;
wait for delay_wr_in;
RST <= '0';
IP <= "1100";
wait for delay_pos_edge;
test_Sreg0 <= S1;
CLK <= '1';
wait for delay_wr_out;
wait for delay_neg_edge; -- S1
-- Test length 11
wait; -- stop simulation
end process; -- STIMULI;
WRITE_RESULTS(CLK,RST,IP,OP);
end architecture Task3_arch_tb2;
configuration Task3_cfg_tb2 of Task3_ent_tb2 is
for Task3_arch_tb2
for UUT : Task3 use entity work.Task3(Beh);
end for;
end for;
end Task3_cfg_tb2;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity Loop_loop_height_hbi_rom is
generic(
dwidth : integer := 8;
awidth : integer := 8;
mem_size : integer := 256
);
port (
addr0 : in std_logic_vector(awidth-1 downto 0);
ce0 : in std_logic;
q0 : out std_logic_vector(dwidth-1 downto 0);
addr1 : in std_logic_vector(awidth-1 downto 0);
ce1 : in std_logic;
q1 : out std_logic_vector(dwidth-1 downto 0);
addr2 : in std_logic_vector(awidth-1 downto 0);
ce2 : in std_logic;
q2 : out std_logic_vector(dwidth-1 downto 0);
clk : in std_logic
);
end entity;
architecture rtl of Loop_loop_height_hbi_rom is
signal addr0_tmp : std_logic_vector(awidth-1 downto 0);
signal addr1_tmp : std_logic_vector(awidth-1 downto 0);
signal addr2_tmp : std_logic_vector(awidth-1 downto 0);
type mem_array is array (0 to mem_size-1) of std_logic_vector (dwidth-1 downto 0);
signal mem0 : mem_array := (
0 => "00000000", 1 => "00001100", 2 => "00010001", 3 => "00010110",
4 => "00011001", 5 => "00011101", 6 => "00100000", 7 => "00100011",
8 => "00100101", 9 => "00101000", 10 => "00101010", 11 => "00101100",
12 => "00101111", 13 => "00110001", 14 => "00110011", 15 => "00110101",
16 => "00110111", 17 => "00111001", 18 => "00111010", 19 => "00111100",
20 => "00111110", 21 => "01000000", 22 => "01000001", 23 => "01000011",
24 => "01000101", 25 => "01000110", 26 => "01001000", 27 => "01001001",
28 => "01001011", 29 => "01001100", 30 => "01001110", 31 => "01001111",
32 => "01010000", 33 => "01010010", 34 => "01010011", 35 => "01010101",
36 => "01010110", 37 => "01010111", 38 => "01011001", 39 => "01011010",
40 => "01011011", 41 => "01011100", 42 => "01011110", 43 => "01011111",
44 => "01100000", 45 => "01100001", 46 => "01100010", 47 => "01100100",
48 => "01100101", 49 => "01100110", 50 => "01100111", 51 => "01101000",
52 => "01101001", 53 => "01101011", 54 => "01101100", 55 => "01101101",
56 => "01101110", 57 => "01101111", 58 => "01110000", 59 => "01110001",
60 => "01110010", 61 => "01110011", 62 => "01110100", 63 => "01110101",
64 => "01110110", 65 => "01110111", 66 => "01111000", 67 => "01111001",
68 => "01111010", 69 => "01111011", 70 => "01111100", 71 => "01111101",
72 => "01111110", 73 => "01111111", 74 => "10000000", 75 => "10000001",
76 => "10000010", 77 => "10000011", 78 => "10000100", 79 => "10000101",
80 => "10000110", 81 => "10000111", 82 => "10001000", 83 => "10001001",
84 => "10001010", 85 to 86=> "10001011", 87 => "10001100", 88 => "10001101",
89 => "10001110", 90 => "10001111", 91 => "10010000", 92 => "10010001",
93 to 94=> "10010010", 95 => "10010011", 96 => "10010100", 97 => "10010101",
98 => "10010110", 99 => "10010111", 100 to 101=> "10011000", 102 => "10011001",
103 => "10011010", 104 => "10011011", 105 => "10011100", 106 to 107=> "10011101",
108 => "10011110", 109 => "10011111", 110 => "10100000", 111 to 112=> "10100001",
113 => "10100010", 114 => "10100011", 115 => "10100100", 116 to 117=> "10100101",
118 => "10100110", 119 => "10100111", 120 => "10101000", 121 to 122=> "10101001",
123 => "10101010", 124 => "10101011", 125 to 126=> "10101100", 127 => "10101101",
128 => "10101110", 129 to 130=> "10101111", 131 => "10110000", 132 => "10110001",
133 to 134=> "10110010", 135 => "10110011", 136 => "10110100", 137 to 138=> "10110101",
139 => "10110110", 140 to 141=> "10110111", 142 => "10111000", 143 => "10111001",
144 to 145=> "10111010", 146 => "10111011", 147 to 148=> "10111100", 149 => "10111101",
150 => "10111110", 151 to 152=> "10111111", 153 => "11000000", 154 to 155=> "11000001",
156 => "11000010", 157 to 158=> "11000011", 159 => "11000100", 160 => "11000101",
161 to 162=> "11000110", 163 => "11000111", 164 to 165=> "11001000", 166 => "11001001",
167 to 168=> "11001010", 169 => "11001011", 170 to 171=> "11001100", 172 => "11001101",
173 to 174=> "11001110", 175 => "11001111", 176 to 177=> "11010000", 178 to 179=> "11010001",
180 => "11010010", 181 to 182=> "11010011", 183 => "11010100", 184 to 185=> "11010101",
186 => "11010110", 187 to 188=> "11010111", 189 => "11011000", 190 to 191=> "11011001",
192 to 193=> "11011010", 194 => "11011011", 195 to 196=> "11011100", 197 => "11011101",
198 to 199=> "11011110", 200 to 201=> "11011111", 202 => "11100000", 203 to 204=> "11100001",
205 to 206=> "11100010", 207 => "11100011", 208 to 209=> "11100100", 210 => "11100101",
211 to 212=> "11100110", 213 to 214=> "11100111", 215 => "11101000", 216 to 217=> "11101001",
218 to 219=> "11101010", 220 => "11101011", 221 to 222=> "11101100", 223 to 224=> "11101101",
225 to 226=> "11101110", 227 => "11101111", 228 to 229=> "11110000", 230 to 231=> "11110001",
232 => "11110010", 233 to 234=> "11110011", 235 to 236=> "11110100", 237 to 238=> "11110101",
239 => "11110110", 240 to 241=> "11110111", 242 to 243=> "11111000", 244 to 245=> "11111001",
246 => "11111010", 247 to 248=> "11111011", 249 to 250=> "11111100", 251 to 252=> "11111101",
253 to 254=> "11111110", 255 => "11111111" );
signal mem1 : mem_array := (
0 => "00000000", 1 => "00001100", 2 => "00010001", 3 => "00010110",
4 => "00011001", 5 => "00011101", 6 => "00100000", 7 => "00100011",
8 => "00100101", 9 => "00101000", 10 => "00101010", 11 => "00101100",
12 => "00101111", 13 => "00110001", 14 => "00110011", 15 => "00110101",
16 => "00110111", 17 => "00111001", 18 => "00111010", 19 => "00111100",
20 => "00111110", 21 => "01000000", 22 => "01000001", 23 => "01000011",
24 => "01000101", 25 => "01000110", 26 => "01001000", 27 => "01001001",
28 => "01001011", 29 => "01001100", 30 => "01001110", 31 => "01001111",
32 => "01010000", 33 => "01010010", 34 => "01010011", 35 => "01010101",
36 => "01010110", 37 => "01010111", 38 => "01011001", 39 => "01011010",
40 => "01011011", 41 => "01011100", 42 => "01011110", 43 => "01011111",
44 => "01100000", 45 => "01100001", 46 => "01100010", 47 => "01100100",
48 => "01100101", 49 => "01100110", 50 => "01100111", 51 => "01101000",
52 => "01101001", 53 => "01101011", 54 => "01101100", 55 => "01101101",
56 => "01101110", 57 => "01101111", 58 => "01110000", 59 => "01110001",
60 => "01110010", 61 => "01110011", 62 => "01110100", 63 => "01110101",
64 => "01110110", 65 => "01110111", 66 => "01111000", 67 => "01111001",
68 => "01111010", 69 => "01111011", 70 => "01111100", 71 => "01111101",
72 => "01111110", 73 => "01111111", 74 => "10000000", 75 => "10000001",
76 => "10000010", 77 => "10000011", 78 => "10000100", 79 => "10000101",
80 => "10000110", 81 => "10000111", 82 => "10001000", 83 => "10001001",
84 => "10001010", 85 to 86=> "10001011", 87 => "10001100", 88 => "10001101",
89 => "10001110", 90 => "10001111", 91 => "10010000", 92 => "10010001",
93 to 94=> "10010010", 95 => "10010011", 96 => "10010100", 97 => "10010101",
98 => "10010110", 99 => "10010111", 100 to 101=> "10011000", 102 => "10011001",
103 => "10011010", 104 => "10011011", 105 => "10011100", 106 to 107=> "10011101",
108 => "10011110", 109 => "10011111", 110 => "10100000", 111 to 112=> "10100001",
113 => "10100010", 114 => "10100011", 115 => "10100100", 116 to 117=> "10100101",
118 => "10100110", 119 => "10100111", 120 => "10101000", 121 to 122=> "10101001",
123 => "10101010", 124 => "10101011", 125 to 126=> "10101100", 127 => "10101101",
128 => "10101110", 129 to 130=> "10101111", 131 => "10110000", 132 => "10110001",
133 to 134=> "10110010", 135 => "10110011", 136 => "10110100", 137 to 138=> "10110101",
139 => "10110110", 140 to 141=> "10110111", 142 => "10111000", 143 => "10111001",
144 to 145=> "10111010", 146 => "10111011", 147 to 148=> "10111100", 149 => "10111101",
150 => "10111110", 151 to 152=> "10111111", 153 => "11000000", 154 to 155=> "11000001",
156 => "11000010", 157 to 158=> "11000011", 159 => "11000100", 160 => "11000101",
161 to 162=> "11000110", 163 => "11000111", 164 to 165=> "11001000", 166 => "11001001",
167 to 168=> "11001010", 169 => "11001011", 170 to 171=> "11001100", 172 => "11001101",
173 to 174=> "11001110", 175 => "11001111", 176 to 177=> "11010000", 178 to 179=> "11010001",
180 => "11010010", 181 to 182=> "11010011", 183 => "11010100", 184 to 185=> "11010101",
186 => "11010110", 187 to 188=> "11010111", 189 => "11011000", 190 to 191=> "11011001",
192 to 193=> "11011010", 194 => "11011011", 195 to 196=> "11011100", 197 => "11011101",
198 to 199=> "11011110", 200 to 201=> "11011111", 202 => "11100000", 203 to 204=> "11100001",
205 to 206=> "11100010", 207 => "11100011", 208 to 209=> "11100100", 210 => "11100101",
211 to 212=> "11100110", 213 to 214=> "11100111", 215 => "11101000", 216 to 217=> "11101001",
218 to 219=> "11101010", 220 => "11101011", 221 to 222=> "11101100", 223 to 224=> "11101101",
225 to 226=> "11101110", 227 => "11101111", 228 to 229=> "11110000", 230 to 231=> "11110001",
232 => "11110010", 233 to 234=> "11110011", 235 to 236=> "11110100", 237 to 238=> "11110101",
239 => "11110110", 240 to 241=> "11110111", 242 to 243=> "11111000", 244 to 245=> "11111001",
246 => "11111010", 247 to 248=> "11111011", 249 to 250=> "11111100", 251 to 252=> "11111101",
253 to 254=> "11111110", 255 => "11111111" );
attribute syn_rom_style : string;
attribute syn_rom_style of mem0 : signal is "block_rom";
attribute syn_rom_style of mem1 : signal is "block_rom";
attribute ROM_STYLE : string;
attribute ROM_STYLE of mem0 : signal is "block";
attribute ROM_STYLE of mem1 : signal is "block";
begin
memory_access_guard_0: process (addr0)
begin
addr0_tmp <= addr0;
--synthesis translate_off
if (CONV_INTEGER(addr0) > mem_size-1) then
addr0_tmp <= (others => '0');
else
addr0_tmp <= addr0;
end if;
--synthesis translate_on
end process;
memory_access_guard_1: process (addr1)
begin
addr1_tmp <= addr1;
--synthesis translate_off
if (CONV_INTEGER(addr1) > mem_size-1) then
addr1_tmp <= (others => '0');
else
addr1_tmp <= addr1;
end if;
--synthesis translate_on
end process;
memory_access_guard_2: process (addr2)
begin
addr2_tmp <= addr2;
--synthesis translate_off
if (CONV_INTEGER(addr2) > mem_size-1) then
addr2_tmp <= (others => '0');
else
addr2_tmp <= addr2;
end if;
--synthesis translate_on
end process;
p_rom_access: process (clk)
begin
if (clk'event and clk = '1') then
if (ce0 = '1') then
q0 <= mem0(CONV_INTEGER(addr0_tmp));
end if;
if (ce1 = '1') then
q1 <= mem0(CONV_INTEGER(addr1_tmp));
end if;
if (ce2 = '1') then
q2 <= mem1(CONV_INTEGER(addr2_tmp));
end if;
end if;
end process;
end rtl;
Library IEEE;
use IEEE.std_logic_1164.all;
entity Loop_loop_height_hbi is
generic (
DataWidth : INTEGER := 8;
AddressRange : INTEGER := 256;
AddressWidth : INTEGER := 8);
port (
reset : IN STD_LOGIC;
clk : IN STD_LOGIC;
address0 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address1 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0);
address2 : IN STD_LOGIC_VECTOR(AddressWidth - 1 DOWNTO 0);
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR(DataWidth - 1 DOWNTO 0));
end entity;
architecture arch of Loop_loop_height_hbi is
component Loop_loop_height_hbi_rom is
port (
clk : IN STD_LOGIC;
addr0 : IN STD_LOGIC_VECTOR;
ce0 : IN STD_LOGIC;
q0 : OUT STD_LOGIC_VECTOR;
addr1 : IN STD_LOGIC_VECTOR;
ce1 : IN STD_LOGIC;
q1 : OUT STD_LOGIC_VECTOR;
addr2 : IN STD_LOGIC_VECTOR;
ce2 : IN STD_LOGIC;
q2 : OUT STD_LOGIC_VECTOR);
end component;
begin
Loop_loop_height_hbi_rom_U : component Loop_loop_height_hbi_rom
port map (
clk => clk,
addr0 => address0,
ce0 => ce0,
q0 => q0,
addr1 => address1,
ce1 => ce1,
q1 => q1,
addr2 => address2,
ce2 => ce2,
q2 => q2);
end architecture;
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fr6FKzf1Gg==
`protect end_protected
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of inst_shadow_10_e
--
-- Generated
-- by: wig
-- on: Mon Jun 26 17:00:36 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_10_e-rtl-a.vhd,v 1.3 2006/07/04 09:54:10 wig Exp $
-- $Date: 2006/07/04 09:54:10 $
-- $Log: inst_shadow_10_e-rtl-a.vhd,v $
-- Revision 1.3 2006/07/04 09:54:10 wig
-- Update more testcases, add configuration/cfgfile
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.90 2006/06/22 07:13:21 wig Exp
--
-- Generator: mix_0.pl Revision: 1.46 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of inst_shadow_10_e
--
architecture rtl of inst_shadow_10_e is
--
-- Generated Constant Declarations
--
--
-- Generated Components
--
--
-- Generated Signal List
--
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
--
-- Generated Signal Assignments
--
--
-- Generated Instances and Port Mappings
--
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
--------------------------------------------------------------------------------
-- Copyright 2014 Madhu Siddalingaiah
--
-- Licensed under the Apache License, Version 2.0 (the "License");
-- you may not use this file except in compliance with the License.
-- You may obtain a copy of the License at
--
-- http://www.apache.org/licenses/LICENSE-2.0
--
-- Unless required by applicable law or agreed to in writing, software
-- distributed under the License is distributed on an "AS IS" BASIS,
-- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-- See the License for the specific language governing permissions and
-- limitations under the License.
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Entity: ControlUnit
-- Date: 2014-10-31
-- Author: Madhu
--
-- Description:
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
-- Avoid using ieee.std_logic_arith.all
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity ControlUnit is
generic (
DATA_WIDTH : integer := 16;
PM_DEPTH : natural := 16
);
port (
reset : in std_logic;
clock : in std_logic;
load_enable : in std_logic;
run_enable : in std_logic;
pm_data_in : in std_logic_vector ( 16 - 1 downto 0 );
halt_flag : out std_logic
);
end ControlUnit;
-- f ddddddd ssssssss
-- 1 module module
-- 0 module immediate
-- module 0 - prefix
architecture arch of ControlUnit is
component ProgramMemory
generic (
DATA_WIDTH : integer;
ADDRESS_WIDTH : integer;
DEPTH : natural
);
port (
reset : in std_logic;
clock : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
pc_in : in std_logic_vector(ADDRESS_WIDTH-1 downto 0);
data_out : out std_logic_vector(DATA_WIDTH-1 downto 0);
pc_out : out std_logic_vector(ADDRESS_WIDTH-1 downto 0);
memory_write : in std_logic;
pc_write : in std_logic
);
end component;
component ArithmeticUnit
generic (
DATA_WIDTH : integer;
ADDRESS_WIDTH : integer;
DEPTH : natural
);
port (
reset : in std_logic;
clock : in std_logic;
address : in std_logic_vector ( ADDRESS_WIDTH - 1 downto 0 );
data_in : in std_logic_vector ( DATA_WIDTH - 1 downto 0 );
data_out : out std_logic_vector ( DATA_WIDTH - 1 downto 0 );
read_enable : in std_logic;
write_enable : in std_logic;
busy : out std_logic
);
end component;
constant SUBSYSTEM_WIDTH : integer := 3;
constant DEST_BASE : integer := 8;
constant UNIT_WIDTH : integer := 4;
constant IMM_BIT : integer := DEST_BASE+3;
constant SHORT_IMM_BIT : integer := DEST_BASE-1;
constant SHORT_IMM_WIDTH : integer := SHORT_IMM_BIT-1;
constant UNIT_PM : integer := 1;
constant UNIT_ARITH : integer := 2;
constant NUM_UNITS : integer := 16;
type DataBusArray is array (NUM_UNITS-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0);
type AddrBusArray is array (NUM_UNITS-1 downto 0) of std_logic_vector(SUBSYSTEM_WIDTH-1 downto 0);
signal data_in, data_out : DataBusArray;
signal address : AddrBusArray;
signal read_enable, write_enable, busy : std_logic_vector(0 to NUM_UNITS-1);
signal instruction, code_data_out : std_logic_vector(DATA_WIDTH-1 downto 0);
signal l_reset, l_clock, code_read_enable : std_logic;
begin
au : ArithmeticUnit
generic map(
DATA_WIDTH => DATA_WIDTH,
ADDRESS_WIDTH => SUBSYSTEM_WIDTH,
DEPTH => 32
)
port map(
reset => l_reset,
clock => l_clock,
address => address(UNIT_ARITH),
data_in => data_in(UNIT_ARITH),
data_out => data_out(UNIT_ARITH),
read_enable => read_enable(UNIT_ARITH),
write_enable => write_enable(UNIT_ARITH),
busy => busy(UNIT_ARITH)
);
statemachine: block
type state_type is (LOAD, PREFETCH, EXEC, HALT);
signal state : state_type := LOAD;
signal dest_sub_system, src_sub_system : std_logic_vector( SUBSYSTEM_WIDTH - 1 downto 0 );
signal short_immediate : std_logic_vector( SHORT_IMM_WIDTH - 1 downto 0 );
signal imm_flag, long_imm_flag : std_logic;
begin
l_reset <= reset;
l_clock <= clock;
imm_flag <= instruction(IMM_BIT);
long_imm_flag <= instruction(SHORT_IMM_BIT);
short_immediate <= instruction(SHORT_IMM_WIDTH - 1 downto 0);
dest_sub_system <= instruction(IMM_BIT - 1 downto DEST_BASE);
src_sub_system <= instruction(SUBSYSTEM_WIDTH - 1 downto 0);
process(clock, reset)
variable dest_unit, src_unit : integer;
begin
if reset = '1' then
state <= LOAD;
halt_flag <= '0';
code_read_enable <= '0';
read_enable <= (others => '0');
write_enable <= (others => '0');
elsif rising_edge(clock) then
read_enable <= (others => '0');
write_enable <= (others => '0');
case state is
when LOAD =>
if load_enable = '0' and run_enable = '1' then
state <= PREFETCH;
elsif load_enable = '1' then
address(UNIT_PM) <= std_logic_vector(to_unsigned(1, address(UNIT_PM)'length));
data_in(UNIT_PM) <= pm_data_in;
write_enable(UNIT_PM) <= '1';
end if;
when PREFETCH =>
state <= EXEC;
code_read_enable <= '1';
when EXEC =>
if to_integer(unsigned(instruction(DATA_WIDTH - 1 downto 0))) = 1 then
state <= HALT;
else
state <= EXEC;
src_unit := to_integer(unsigned(instruction(DEST_BASE - 1 downto UNIT_WIDTH)));
dest_unit := to_integer(unsigned(instruction(DATA_WIDTH - 1 downto IMM_BIT+1)));
address(dest_unit) <= dest_sub_system;
if imm_flag = '1' then
if long_imm_flag = '0' then
data_in(dest_unit) <= std_logic_vector(resize(signed(short_immediate), data_in(dest_unit)'length));
else
address(UNIT_PM) <= std_logic_vector(to_unsigned(1, address(UNIT_PM)'length));
read_enable(UNIT_PM) <= '1';
data_in(dest_unit) <= data_out(UNIT_PM);
end if;
else
address(src_unit) <= src_sub_system;
read_enable(src_unit) <= '1';
data_in(dest_unit) <= data_out(src_unit);
end if;
write_enable(dest_unit) <= '1';
end if;
when HALT =>
halt_flag <= '1';
when others =>
state <= HALT;
end case;
end if;
end process;
end block;
end arch;
|
----------------------------------------------------------------------------------
-- Company: @Home
-- Engineer: Zoltan Pekic ([email protected])
--
-- Create Date: 01:57:47 02/27/2016
-- Design Name:
-- Module Name: pwm10bit - Behavioral
-- Project Name: Alarm Clock
-- Target Devices: Mercury FPGA + Baseboard (http://www.micro-nova.com/mercury/)
-- Tool versions: Xilinx ISE 14.7 (nt64)
--
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity pwm10bit is
Port ( clk : in STD_LOGIC;
adc_samplingrate: in STD_LOGIC;
adc_channel : in STD_LOGIC_VECTOR (2 downto 0);
adc_miso : in std_logic; -- ADC SPI MISO
adc_mosi : out std_logic; -- ADC SPI MOSI
adc_cs : out std_logic; -- ADC SPI CHIP SELECT
adc_clk : out std_logic; -- ADC SPI CLOCK
adc_value: out std_logic_vector(15 downto 0);
adc_valid: out std_logic;
pwm_out : out STD_LOGIC);
end pwm10bit;
-- From http://www.micro-nova.com/resources/
use work.MercuryADC;
architecture Behavioral of pwm10bit is
component MercuryADC is
port
(
-- command input
clock : in std_logic; -- 50MHz onboard oscillator
trigger : in std_logic; -- assert to sample ADC
diffn : in std_logic; -- single/differential inputs
channel : in std_logic_vector(2 downto 0); -- channel to sample
-- data output
Dout : out std_logic_vector(9 downto 0); -- data from ADC
OutVal : out std_logic; -- pulsed when data sampled
-- ADC connection
adc_miso : in std_logic; -- ADC SPI MISO
adc_mosi : out std_logic; -- ADC SPI MOSI
adc_cs : out std_logic; -- ADC SPI CHIP SELECT
adc_clk : out std_logic -- ADC SPI CLOCK
);
end component;
signal threshold: integer range 0 to 1023 := 0;
signal counter: integer range 0 to 1023 := 0;
signal adc_out: std_logic_vector(9 downto 0);
signal adc_pulse: std_logic;
begin
-- map to output and extend to 16 bits
adc_value <= "000000" & adc_out;
adc_valid <= adc_pulse;
adc: MercuryADC port map
(
-- command input
clock => clk, -- from onboard oscillator
trigger => adc_samplingrate, -- assert to sample ADC
diffn => '1', -- single/differential inputs
channel => adc_channel, -- channel to sample (3 == light sensor)
-- data output
Dout => adc_out, -- data from ADC
OutVal => adc_pulse, -- pulsed when data sampled
-- ADC connection
adc_miso => adc_miso, -- ADC SPI MISO
adc_mosi => adc_mosi, -- ADC SPI MOSI
adc_cs => adc_cs, -- ADC SPI CHIP SELECT
adc_clk => adc_clk -- ADC SPI CLOCK
);
get_adc: process(adc_pulse)
begin
if (adc_pulse = '1') then
threshold <= to_integer(unsigned(adc_out));
end if;
end process;
generate_pwm: process(clk)
begin
if (clk'event and clk = '1') then
counter <= counter + 1; -- just let it wrap around
if (counter > threshold) then
pwm_out <= '0';
else
pwm_out <= '1';
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_byte_swap is
end entity tb_byte_swap;
----------------------------------------------------------------
use work.byte_swap_types.all;
architecture test_behavior of tb_byte_swap is
signal input, output : halfword := x"0000";
begin
dut : entity work.byte_swap(behavior)
port map ( input => input, output => output );
stumulus : process is
begin
wait for 10 ns;
input <= x"ff00"; wait for 10 ns;
input <= x"00ff"; wait for 10 ns;
input <= x"aa33"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_byte_swap is
end entity tb_byte_swap;
----------------------------------------------------------------
use work.byte_swap_types.all;
architecture test_behavior of tb_byte_swap is
signal input, output : halfword := x"0000";
begin
dut : entity work.byte_swap(behavior)
port map ( input => input, output => output );
stumulus : process is
begin
wait for 10 ns;
input <= x"ff00"; wait for 10 ns;
input <= x"00ff"; wait for 10 ns;
input <= x"aa33"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity tb_byte_swap is
end entity tb_byte_swap;
----------------------------------------------------------------
use work.byte_swap_types.all;
architecture test_behavior of tb_byte_swap is
signal input, output : halfword := x"0000";
begin
dut : entity work.byte_swap(behavior)
port map ( input => input, output => output );
stumulus : process is
begin
wait for 10 ns;
input <= x"ff00"; wait for 10 ns;
input <= x"00ff"; wait for 10 ns;
input <= x"aa33"; wait for 10 ns;
wait;
end process stumulus;
end architecture test_behavior;
|
-- -------------------------------------------------------------
--
-- Entity Declaration for inst_shadow_7_e
--
-- Generated
-- by: wig
-- on: Fri Jul 15 13:54:30 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -nodelta ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_7_e-e.vhd,v 1.2 2005/07/15 16:20:00 wig Exp $
-- $Date: 2005/07/15 16:20:00 $
-- $Log: inst_shadow_7_e-e.vhd,v $
-- Revision 1.2 2005/07/15 16:20:00 wig
-- Update all testcases; still problems though
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.55 2005/07/13 15:38:34 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/enty
--
--
-- Start of Generated Entity inst_shadow_7_e
--
entity inst_shadow_7_e is
-- Generics:
-- No Generated Generics for Entity inst_shadow_7_e
-- Generated Port Declaration:
-- No Generated Port for Entity inst_shadow_7_e
end inst_shadow_7_e;
--
-- End of Generated Entity inst_shadow_7_e
--
--
--!End of Entity/ies
-- --------------------------------------------------------------
|
-------------------------------------------------------------------------------------------------
-- Company : CNES
-- Author : Mickael Carl (CNES)
-- Copyright : Copyright (c) CNES.
-- Licensing : GNU GPLv3
-------------------------------------------------------------------------------------------------
-- Version : V1
-- Version history :
-- V1 : 2015-04-02 : Mickael Carl (CNES): Creation
-------------------------------------------------------------------------------------------------
-- File name : STD_03100_good.vhd
-- File Creation date : 2015-04-02
-- Project name : VHDL Handbook CNES Edition
-------------------------------------------------------------------------------------------------
-- Softwares : Microsoft Windows (Windows 7) - Editor (Eclipse + VEditor)
-------------------------------------------------------------------------------------------------
-- Description : Handbook example: Dead VHDL code: good example
--
-- Limitations : This file is an example of the VHDL handbook made by CNES. It is a stub aimed at
-- demonstrating good practices in VHDL and as such, its design is minimalistic.
-- It is provided as is, without any warranty.
--
-------------------------------------------------------------------------------------------------
-- Naming conventions:
--
-- i_Port: Input entity port
-- o_Port: Output entity port
-- b_Port: Bidirectional entity port
-- g_My_Generic: Generic entity port
--
-- c_My_Constant: Constant definition
-- t_My_Type: Custom type definition
--
-- My_Signal_n: Active low signal
-- v_My_Variable: Variable
-- sm_My_Signal: FSM signal
-- pkg_Param: Element Param coming from a package
--
-- My_Signal_re: Rising edge detection of My_Signal
-- My_Signal_fe: Falling edge detection of My_Signal
-- My_Signal_rX: X times registered My_Signal signal
--
-- P_Process_Name: Process
--
-------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity STD_03100_good is
port (
i_Clock : in std_logic; -- Clock signal
i_Reset_n : in std_logic; -- Reset signal
i_D : in std_logic; -- D Flip-Flop input signal
o_Q : out std_logic -- D Flip-Flop output signal
);
end STD_03100_good;
--CODE
architecture Behavioral of STD_03100_good is
signal Q : std_logic; -- D Flip-Flop output
begin
-- D FlipFlop process
P_FlipFlop : process(i_Clock, i_Reset_n)
begin
if (i_Reset_n = '0') then
Q <= '0';
elsif (rising_edge(i_Clock)) then
Q <= i_D;
end if;
end process;
o_Q <= Q;
end Behavioral;
--CODE
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package coeff_ram_types is
subtype coeff_ram_address is integer range 0 to 63;
end package coeff_ram_types;
use work.coeff_ram_types.all;
-- end not in book
entity coeff_ram is
port ( rd, wr : in bit; addr : in coeff_ram_address;
d_in : in real; d_out : out real );
end entity coeff_ram;
--------------------------------------------------
architecture abstract of coeff_ram is
begin
memory : process is
type coeff_array is array (coeff_ram_address) of real;
variable coeff : coeff_array;
begin
for index in coeff_ram_address loop
coeff(index) := 0.0;
end loop;
loop
wait on rd, wr, addr, d_in;
if rd = '1' then
d_out <= coeff(addr);
end if;
if wr = '1' then
coeff(addr) := d_in;
end if;
end loop;
end process memory;
end architecture abstract;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package coeff_ram_types is
subtype coeff_ram_address is integer range 0 to 63;
end package coeff_ram_types;
use work.coeff_ram_types.all;
-- end not in book
entity coeff_ram is
port ( rd, wr : in bit; addr : in coeff_ram_address;
d_in : in real; d_out : out real );
end entity coeff_ram;
--------------------------------------------------
architecture abstract of coeff_ram is
begin
memory : process is
type coeff_array is array (coeff_ram_address) of real;
variable coeff : coeff_array;
begin
for index in coeff_ram_address loop
coeff(index) := 0.0;
end loop;
loop
wait on rd, wr, addr, d_in;
if rd = '1' then
d_out <= coeff(addr);
end if;
if wr = '1' then
coeff(addr) := d_in;
end if;
end loop;
end process memory;
end architecture abstract;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- not in book:
package coeff_ram_types is
subtype coeff_ram_address is integer range 0 to 63;
end package coeff_ram_types;
use work.coeff_ram_types.all;
-- end not in book
entity coeff_ram is
port ( rd, wr : in bit; addr : in coeff_ram_address;
d_in : in real; d_out : out real );
end entity coeff_ram;
--------------------------------------------------
architecture abstract of coeff_ram is
begin
memory : process is
type coeff_array is array (coeff_ram_address) of real;
variable coeff : coeff_array;
begin
for index in coeff_ram_address loop
coeff(index) := 0.0;
end loop;
loop
wait on rd, wr, addr, d_in;
if rd = '1' then
d_out <= coeff(addr);
end if;
if wr = '1' then
coeff(addr) := d_in;
end if;
end loop;
end process memory;
end architecture abstract;
|
entity proc is
end entity;
architecture test of proc is
signal x, y : integer;
procedure proc(n : integer) is
begin
end procedure;
begin
-- Test rewrite of process sensitivity list
process (x, y) is
begin
report "awake";
end process;
-- Test rewrite of concurrent assignments
x <= y + 4;
postponed x <= y + 4 when y < 2 else x + 1 when x < 2 else 0;
-- Concurrent procedure call to process
proc(n => 4);
end architecture;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.devices.all;
use grlib.stdlib.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.spacewire.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use work.config.all;
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
sys_rst_in : in std_ulogic;
sys_clk : in std_ulogic; -- 100 MHz main clock
sysace_clk_in : in std_ulogic; -- System ACE clock
plb_error : out std_logic; -- IU error mode
opb_error : out std_logic; -- DSU active
flash_a23 : out std_ulogic;
sram_flash_addr : out std_logic_vector(22 downto 0);
sram_flash_data : inout std_logic_vector(31 downto 0);
sram_cen : out std_logic;
sram_bw : out std_logic_vector (0 to 3);
sram_flash_oe_n : out std_ulogic;
sram_flash_we_n : out std_ulogic;
flash_ce : out std_logic;
sram_clk : out std_ulogic;
sram_clk_fb : in std_ulogic;
sram_mode : out std_ulogic;
sram_adv_ld_n : out std_ulogic;
--pragma translate_off
iosn : out std_ulogic;
--pragma translate_on
ddr_clk : out std_logic;
ddr_clkb : out std_logic;
ddr_clk_fb : in std_logic;
ddr_cke : out std_logic;
ddr_csb : out std_logic;
ddr_web : out std_ulogic; -- ddr write enable
ddr_rasb : out std_ulogic; -- ddr ras
ddr_casb : out std_ulogic; -- ddr cas
ddr_dm : out std_logic_vector (3 downto 0); -- ddr dm
ddr_dqs : inout std_logic_vector (3 downto 0); -- ddr dqs
ddr_ad : out std_logic_vector (12 downto 0); -- ddr address
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
ddr_dq : inout std_logic_vector (31 downto 0); -- ddr data
txd1 : out std_ulogic; -- UART1 tx data
rxd1 : in std_ulogic; -- UART1 rx data
gpio : inout std_logic_vector(26 downto 0); -- I/O port
phy_gtx_clk : out std_logic;
phy_mii_data: inout std_logic; -- ethernet PHY interface
phy_tx_clk : in std_ulogic;
phy_rx_clk : in std_ulogic;
phy_rx_data : in std_logic_vector(7 downto 0);
phy_dv : in std_ulogic;
phy_rx_er : in std_ulogic;
phy_col : in std_ulogic;
phy_crs : in std_ulogic;
phy_int_n : in std_ulogic;
phy_tx_data : out std_logic_vector(7 downto 0);
phy_tx_en : out std_ulogic;
phy_tx_er : out std_ulogic;
phy_mii_clk : out std_ulogic;
phy_rst_n : out std_ulogic;
ps2_keyb_clk : inout std_logic;
ps2_keyb_data : inout std_logic;
ps2_mouse_clk : inout std_logic;
ps2_mouse_data : inout std_logic;
tft_lcd_clk : out std_ulogic;
vid_blankn : out std_ulogic;
vid_syncn : out std_ulogic;
vid_hsync : out std_ulogic;
vid_vsync : out std_ulogic;
vid_r : out std_logic_vector(7 downto 0);
vid_g : out std_logic_vector(7 downto 0);
vid_b : out std_logic_vector(7 downto 0);
usb_csn : out std_logic;
iic_scl : inout std_ulogic;
iic_sda : inout std_ulogic;
sace_usb_a : out std_logic_vector(6 downto 0);
sace_mpce : out std_ulogic;
sace_usb_d : inout std_logic_vector(15 downto 0);
sace_usb_oen : out std_ulogic;
sace_usb_wen : out std_ulogic;
sysace_mpirq : in std_ulogic
);
end;
architecture rtl of leon3mp is
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART
+CFG_GRETH+CFG_AHB_JTAG+CFG_SVGA_ENABLE;
signal vcc, gnd : std_logic_vector(4 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal sdi : sdctrl_in_type;
signal sdo : sdctrl_out_type;
signal apbi : apb_slv_in_type;
signal apbo : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, rstn, rstraw, srclkl : std_ulogic;
signal clkm_90, clkm_180, clkm_270 : std_ulogic;
signal cgi, cgi2 : clkgen_in_type;
signal cgo, cgo2 : clkgen_out_type;
signal u1i, u2i, dui : uart_in_type;
signal u1o, u2o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock, lclk, clkml, rst, ndsuact : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal ddrclk, ddrrst : std_ulogic;
signal ethclk, egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal kbdi : ps2_in_type;
signal kbdo : ps2_out_type;
signal moui : ps2_in_type;
signal mouo : ps2_out_type;
signal vgao : apbvga_out_type;
signal clk_sel : std_logic_vector(1 downto 0);
signal clkval : std_logic_vector(1 downto 0);
signal clkvga, clk1x, video_clk, dac_clk : std_ulogic;
signal i2ci : i2c_in_type;
signal i2co : i2c_out_type;
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
constant IOAEN : integer := CFG_DDRSP;
signal stati : ahbstat_in_type;
signal ddrclkfb, ssrclkfb, ddr_clkl, ddr_clk90l, ddr_clknl, ddr_clk270l : std_ulogic;
signal ddr_clkv : std_logic_vector(2 downto 0);
signal ddr_clkbv : std_logic_vector(2 downto 0);
signal ddr_ckev : std_logic_vector(1 downto 0);
signal ddr_csbv : std_logic_vector(1 downto 0);
signal ddr_adl : std_logic_vector (13 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of lock : signal is true;
attribute syn_preserve of lock : signal is true;
attribute syn_keep of clkml : signal is true;
attribute syn_preserve of clkml : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute keep : boolean;
attribute keep of lock : signal is true;
attribute keep of clkml : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_clk_in_pad : label is true;
signal romsn : std_ulogic;
constant SPW_LOOP_BACK : integer := 0;
begin
usb_csn <= '1';
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
vcc <= (others => '1'); gnd <= (others => '0');
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= ssrclkfb;
ssrref_pad : clkpad generic map (tech => padtech)
port map (sram_clk_fb, ssrclkfb);
clk_pad : clkpad generic map (tech => padtech, arch => 2)
port map (sys_clk, lclk);
srclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (sram_clk, srclkl);
sysace_clk_in_pad : clkpad generic map (tech => padtech)
port map (sysace_clk_in, clkace);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), clkm, open, open, srclkl, open, cgi, cgo, open, clk1x);
clkgen1 : clkgen -- Ethernet 1G PHY clock generator
generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
egtx_clk_pad : outpad generic map (tech => padtech)
port map (phy_gtx_clk, egtx_clk);
resetn_pad : inpad generic map (tech => padtech) port map (sys_rst_in, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock and cgo2.clklock;
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML401,
ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
errorn_pad : odpad generic map (tech => padtech) port map (plb_error, dbgo(0).error);
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
-- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
dsui.enable <= '1';
-- dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
dsui.break <= gpioo.val(11); -- South Button
-- dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, ndsuact);
dsuact_pad : outpad generic map (tech => padtech) port map (opb_error, ndsuact);
ndsuact <= not dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0';
end generate;
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd1, dui.rxd);
-- dsutx_pad : outpad generic map (tech => padtech) port map (txd1, duo.txd);
dui.rxd <= rxd1 when gpioo.val(21) = '1' else '1';
end generate;
txd1 <= duo.txd when gpioo.val(21) = '1' else u1o.txd;
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
memi.brdyn <= '1'; memi.bexcn <= '1';
ssr0 : if CFG_SSCTRL = 1 generate
ssrctrl0 : ssrctrl generic map (hindex => 3, pindex => 0, ramaddr => 16#600#)
port map (rstn, clkm, ahbsi, ahbso(3), apbi, apbo(0), memi, memo);
end generate;
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 16#C00#, rammask => 16#FF0#,
paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
invclk => CFG_MCTRL_INVCLK, sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo, open);
end generate;
romsn <= not memo.romsn(0);
sram_adv_ld_n_pad : outpad generic map (tech => padtech)
port map (sram_adv_ld_n, gnd(0));
sram_mode_pad : outpad generic map (tech => padtech)
port map (sram_mode, gnd(0));
addr_pad : outpadv generic map (width => 23, tech => padtech)
port map (sram_flash_addr, memo.address(24 downto 2));
addr23_pad : outpad generic map (tech => padtech)
port map (flash_a23, gnd(0));
rams_pad : outpad generic map ( tech => padtech)
port map (sram_cen, memo.ramsn(0));
roms_pad : outpad generic map (tech => padtech)
port map (flash_ce, romsn);
oen_pad : outpad generic map (tech => padtech)
port map (sram_flash_oe_n, memo.oen);
--pragma translate_off
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
rwen_pad : outpadv generic map (width => 4, tech => padtech)
port map (sram_bw, memo.wrn);
wri_pad : outpad generic map (tech => padtech)
port map (sram_flash_we_n, memo.writen);
data_pads : iopadvv generic map (tech => padtech, width => 32)
port map (sram_flash_data, memo.data, memo.vbdrive, memi.data);
ddrsp0 : if (CFG_DDRSP /= 0) generate
-- phyiconf => 1 = no diff pads for DDR clock pairs
ddrc0 : ddrspa generic map ( fabtech => CFG_FABTECH, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#F00#, ioaddr => 1,
pwron => CFG_DDRSP_INIT, MHz => BOARD_FREQ/1000,
clkmul => CFG_DDRSP_FREQ/10, clkdiv => 10, ahbfreq => CPU_FREQ/1000,
col => CFG_DDRSP_COL, Mbyte => CFG_DDRSP_SIZE, ddrbits => 32,
phyiconf => 1)
port map (
rst, rstn, lclk, clkm, lock, clkml, clkml, ahbsi, ahbso(0),
ddr_clkv, ddr_clkbv, open, ddr_clk_fb,
ddr_ckev, ddr_csbv, ddr_web, ddr_rasb, ddr_casb,
ddr_dm, ddr_dqs, ddr_adl, ddr_ba, ddr_dq);
ddr_ad <= ddr_adl(12 downto 0);
ddr_clk <= ddr_clkv(0); ddr_clkb <= ddr_clkbv(0);
ddr_cke <= ddr_ckev(0); ddr_csb <= ddr_csbv(0);
end generate;
noddr : if (CFG_DDRSP = 0) generate lock <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 4, hirq => 10,
haddr => 16#002#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(4), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL /= 1 generate
aceo <= gracectrl_none;
end generate;
sace_usb_a_pads : outpadv generic map (width => 7, tech => padtech)
port map (sace_usb_a, aceo.addr);
sace_mpce_pad : outpad generic map (tech => padtech)
port map (sace_mpce, aceo.cen);
sace_usb_d_pads : iopadv generic map (tech => padtech, width => 16)
port map (sace_usb_d, aceo.do, aceo.doen, acei.di);
sace_usb_oen_pad : outpad generic map (tech => padtech)
port map (sace_usb_oen, aceo.oen);
sace_usb_wen_pad : outpad generic map (tech => padtech)
port map (sace_usb_wen, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map ( rstn, clkm, ahbsi, ahbso(6));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0'; u1i.ctsn <= '0';
u1i.rxd <= rxd1 when gpioo.val(21) = '0' else '1';
end generate;
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
kbd : if CFG_KBD_ENABLE /= 0 generate
ps21 : apbps2 generic map(pindex => 4, paddr => 4, pirq => 4)
port map(rstn, clkm, apbi, apbo(4), moui, mouo);
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
end generate;
nokbd : if CFG_KBD_ENABLE = 0 generate apbo(5) <= apb_none; kbdo <= ps2o_none; end generate;
kbdclk_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
kbdata_pad : iopad generic map (tech => padtech)
port map (ps2_keyb_data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
mouclk_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_clk, mouo.ps2_clk_o, mouo.ps2_clk_oe, moui.ps2_clk_i);
mouata_pad : iopad generic map (tech => padtech)
port map (ps2_mouse_data, mouo.ps2_data_o, mouo.ps2_data_oe, moui.ps2_data_i);
vga : if CFG_VGA_ENABLE /= 0 generate
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
port map(rstn, clkm, ethclk, apbi, apbo(6), vgao);
clk_sel <= "00";
end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 4*(1000000000/BOARD_FREQ), clk1 => 2*(1000000000/BOARD_FREQ),
clk2 => 1000000000/CPU_FREQ, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(6), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
end generate;
vgadiv : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) /= 0 generate
clkdiv : process(clk1x, rstn)
begin
if rstn = '0' then clkval <= "00";
elsif rising_edge(clk1x) then
clkval <= clkval + 1;
end if;
end process;
video_clk <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
b1 : techbuf generic map (2, CFG_FABTECH) port map (video_clk, clkvga);
dac_clk <= not clkvga;
end generate;
novga : if (CFG_VGA_ENABLE + CFG_SVGA_ENABLE) = 0 generate
apbo(6) <= apb_none; vgao <= vgao_none;
end generate;
blank_pad : outpad generic map (tech => padtech)
port map (vid_blankn, vgao.blank);
comp_sync_pad : outpad generic map (tech => padtech)
port map (vid_syncn, vgao.comp_sync);
vert_sync_pad : outpad generic map (tech => padtech)
port map (vid_vsync, vgao.vsync);
horiz_sync_pad : outpad generic map (tech => padtech)
port map (vid_hsync, vgao.hsync);
video_out_r_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_r, vgao.video_out_r);
video_out_g_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_g, vgao.video_out_g);
video_out_b_pad : outpadv generic map (width => 8, tech => padtech)
port map (vid_b, vgao.video_out_b);
video_clock_pad : outpad generic map ( tech => padtech)
port map (tft_lcd_clk, dac_clk);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => 16#00F0#, nbits => 27)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
gpio_pads : iopadvv generic map (tech => padtech, width => 27)
port map (gpio, gpioo.dout(26 downto 0), gpioo.oen(26 downto 0),
gpioi.din(26 downto 0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 12, paddr => 12, pmask => 16#FFF#,
pirq => 11, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(12), i2ci, i2co);
i2c_scl_pad : iopad generic map (tech => padtech)
port map (iic_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (iic_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
end generate i2cm;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 12, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, enable_mdint => 1,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy_mii_data, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_tx_clk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2)
port map (phy_rx_clk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 8)
port map (phy_rx_data, ethi.rxd(7 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy_dv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy_rx_er, ethi.rx_er);
erxco_pad : inpad generic map (tech => padtech)
port map (phy_col, ethi.rx_col);
erxcr_pad : inpad generic map (tech => padtech)
port map (phy_crs, ethi.rx_crs);
emdint_pad : inpad generic map (tech => padtech)
port map (phy_int_n, ethi.mdint);
etxd_pad : outpadv generic map (tech => padtech, width => 8)
port map (phy_tx_data, etho.txd(7 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map ( phy_tx_en, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy_tx_er, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy_mii_clk, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy_rst_n, rstn);
ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(7));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => "LEON3 Avnet ML401 (Virtex4 LX25) Demonstration design",
fabtech => tech_table(fabtech), memtech => tech_table(memtech), mdel => 1
);
-- pragma translate_on
end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: skew_outpad
-- File: skew_outpad.vhd
-- Author: Nils-Johan Wessman - Gaisler Research
-- Description: output pad with technology wrapper
------------------------------------------------------------------------------
library techmap;
library ieee;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
use techmap.allpads.all;
entity skew_outpad is
generic (tech : integer := 0; level : integer := 0; slew : integer := 0;
voltage : integer := x33v; strength : integer := 12; skew : integer := 0);
port (pad : out std_ulogic; i : in std_ulogic; rst : in std_ulogic;
o : out std_ulogic);
end;
architecture rtl of skew_outpad is
signal padx, gnd, vcc : std_ulogic;
begin
gnd <= '0'; vcc <= '1';
gen0 : if has_pads(tech) = 0 generate
pad <= i
-- pragma translate_off
after 2 ns
-- pragma translate_on
when slew = 0 else i;
end generate;
xcv : if (is_unisim(tech) = 1) generate
x0 : unisim_skew_outpad generic map (level, slew, voltage, strength, skew) port map (pad, i, rst, o);
end generate;
end;
|
-- $Id: pdp11_aunit.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_aunit - syn
-- Description: pdp11: arithmetic unit for data (aunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
-- arithmetic unit for data, usage:
-- ADD: SRC + DST + 0 (dst+src)
-- SUB: ~SRC + DST + 1 (dst-src)
-- ADC: 0 + DST + CI (dst+ci)
-- SBC: ~0 + DST + ~CI (dst-ci)
-- CMP: SRC + ~DST + 1 (src-dst)
-- COM: 0 + ~DST + 0 (~dst)
-- NEG: 0 + ~DST + 1 (-dst)
-- INC: 0 + DST + 1 (dst+1)
-- DEC: ~0 + DST + 0 (dst-1)
-- CLR: 0 + 0 + 0 (0)
-- SOB: SRC + ~0 + 0 (src-1)
entity pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_aunit;
architecture syn of pdp11_aunit is
-- --------------------------------------
begin
process (DSRC, DDST, CI, CIMOD, CC1OP, CCMODE, SRCMOD, DSTMOD, BYTOP)
variable msrc : slv16 := (others=>'0'); -- effective src data
variable mdst : slv16 := (others=>'0'); -- effective dst data
variable mci : slbit := '0'; -- effective ci
variable sum : slv16 := (others=>'0'); -- sum
variable co8 : slbit := '0'; -- co 8 bit
variable co16 : slbit := '0'; -- co 16 bit
variable nno : slbit := '0'; -- local no
variable nzo : slbit := '0'; -- local zo
variable nvo : slbit := '0'; -- local vo
variable nco : slbit := '0'; -- local co
variable src_msb : slbit := '0'; -- msb from src (bit 15 or 7)
variable dst_msb : slbit := '0'; -- msb from dst (bit 15 or 7)
variable sum_msb : slbit := '0'; -- msb from sum (bit 15 or 7)
alias NO : slbit is CCOUT(3);
alias ZO : slbit is CCOUT(2);
alias VO : slbit is CCOUT(1);
alias CO : slbit is CCOUT(0);
-- procedure do_add8_ci_co: 8 bit adder with carry in and carry out
-- implemented following the recommended pattern for XST ISE V8.1
procedure do_add8_ci_co (
variable a : in slv8; -- input a
variable b : in slv8; -- input b
variable ci : in slbit; -- carry in
variable sum : out slv8; -- sum out
variable co : out slbit -- carry out
) is
variable tmp: slv9;
begin
tmp := conv_std_logic_vector((conv_integer(a) + conv_integer(b) +
conv_integer(ci)),9);
sum := tmp(7 downto 0);
co := tmp(8);
end procedure do_add8_ci_co;
begin
case SRCMOD is
when c_aunit_mod_pass => msrc := DSRC;
when c_aunit_mod_inv => msrc := not DSRC;
when c_aunit_mod_zero => msrc := (others=>'0');
when c_aunit_mod_one => msrc := (others=>'1');
when others => null;
end case;
case DSTMOD is
when c_aunit_mod_pass => mdst := DDST;
when c_aunit_mod_inv => mdst := not DDST;
when c_aunit_mod_zero => mdst := (others=>'0');
when c_aunit_mod_one => mdst := (others=>'1');
when others => null;
end case;
case CIMOD is
when c_aunit_mod_pass => mci := CI;
when c_aunit_mod_inv => mci := not CI;
when c_aunit_mod_zero => mci := '0';
when c_aunit_mod_one => mci := '1';
when others => null;
end case;
do_add8_ci_co(msrc(7 downto 0), mdst(7 downto 0), mci,
sum(7 downto 0), co8);
do_add8_ci_co(msrc(15 downto 8), mdst(15 downto 8), co8,
sum(15 downto 8), co16);
DOUT <= sum;
-- V ('overflow) bit set if
-- ADD : both operants of same sign but has result opposite sign
-- SUB : both operants of opposide sign and sign source equals sign result
-- CMP : both operants of opposide sign and sign dest. equals sign result
nno := '0';
nzo := '0';
nvo := '0';
nco := '0';
if BYTOP = '1' then
nno := sum(7);
if unsigned(sum(7 downto 0)) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co8;
src_msb := DSRC(7);
dst_msb := DDST(7);
sum_msb := sum(7);
else
nno := sum(15);
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co16;
src_msb := DSRC(15);
dst_msb := DDST(15);
sum_msb := sum(15);
end if;
-- the logic for 2 operand V+C is ugly. It is reverse engineered from
-- the MOD's the operation type.
if CC1OP = '0' then -- 2 operand cases
if unsigned(CIMOD) = unsigned(c_aunit_mod_zero) then -- case ADD
nvo := not(src_msb xor dst_msb) and (src_msb xor sum_msb);
else
if unsigned(SRCMOD) = unsigned(c_aunit_mod_inv) then -- case SUB
nvo := (src_msb xor dst_msb) and not (src_msb xor sum_msb);
else -- case CMP
nvo := (src_msb xor dst_msb) and not (dst_msb xor sum_msb);
end if;
nco := not nco; -- invert C for SUB and CMP
end if;
else -- 1 operand cases
case CCMODE is
when c_aunit_ccmode_clr|c_aunit_ccmode_tst =>
nvo := '0'; -- force v=0 for tst and clr
nco := '0'; -- force c=0 for tst and clr
when c_aunit_ccmode_com =>
nvo := '0'; -- force v=0 for com
nco := '1'; -- force c=1 for com
when c_aunit_ccmode_inc =>
nvo := sum_msb and not dst_msb;
nco := CI; -- C not affected for INC
when c_aunit_ccmode_dec =>
nvo := not sum_msb and dst_msb;
nco := CI; -- C not affected for DEC
when c_aunit_ccmode_neg =>
nvo := sum_msb and dst_msb;
nco := not nzo;
when c_aunit_ccmode_adc =>
nvo := sum_msb and not dst_msb;
when c_aunit_ccmode_sbc =>
nvo := not sum_msb and dst_msb;
nco := not nco;
when others => null;
end case;
end if;
NO <= nno;
ZO <= nzo;
VO <= nvo;
CO <= nco;
end process;
end syn;
|
-- $Id: pdp11_aunit.vhd 330 2010-09-19 17:43:53Z mueller $
--
-- Copyright 2006-2007 by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: pdp11_aunit - syn
-- Description: pdp11: arithmetic unit for data (aunit)
--
-- Dependencies: -
-- Test bench: tb/tb_pdp11_core (implicit)
-- Target Devices: generic
-- Tool versions: xst 8.1, 8.2, 9.1, 9.2, 12.1; ghdl 0.18-0.26
-- Revision History:
-- Date Rev Version Comment
-- 2010-09-18 300 1.1 renamed from abox
-- 2007-06-14 56 1.0.1 Use slvtypes.all
-- 2007-05-12 26 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.slvtypes.all;
use work.pdp11.all;
-- ----------------------------------------------------------------------------
-- arithmetic unit for data, usage:
-- ADD: SRC + DST + 0 (dst+src)
-- SUB: ~SRC + DST + 1 (dst-src)
-- ADC: 0 + DST + CI (dst+ci)
-- SBC: ~0 + DST + ~CI (dst-ci)
-- CMP: SRC + ~DST + 1 (src-dst)
-- COM: 0 + ~DST + 0 (~dst)
-- NEG: 0 + ~DST + 1 (-dst)
-- INC: 0 + DST + 1 (dst+1)
-- DEC: ~0 + DST + 0 (dst-1)
-- CLR: 0 + 0 + 0 (0)
-- SOB: SRC + ~0 + 0 (src-1)
entity pdp11_aunit is -- arithmetic unit for data (aunit)
port (
DSRC : in slv16; -- 'src' data in
DDST : in slv16; -- 'dst' data in
CI : in slbit; -- carry flag in
SRCMOD : in slv2; -- src modifier mode
DSTMOD : in slv2; -- dst modifier mode
CIMOD : in slv2; -- ci modifier mode
CC1OP : in slbit; -- use cc modes (1 op instruction)
CCMODE : in slv3; -- cc mode
BYTOP : in slbit; -- byte operation
DOUT : out slv16; -- data output
CCOUT : out slv4 -- condition codes out
);
end pdp11_aunit;
architecture syn of pdp11_aunit is
-- --------------------------------------
begin
process (DSRC, DDST, CI, CIMOD, CC1OP, CCMODE, SRCMOD, DSTMOD, BYTOP)
variable msrc : slv16 := (others=>'0'); -- effective src data
variable mdst : slv16 := (others=>'0'); -- effective dst data
variable mci : slbit := '0'; -- effective ci
variable sum : slv16 := (others=>'0'); -- sum
variable co8 : slbit := '0'; -- co 8 bit
variable co16 : slbit := '0'; -- co 16 bit
variable nno : slbit := '0'; -- local no
variable nzo : slbit := '0'; -- local zo
variable nvo : slbit := '0'; -- local vo
variable nco : slbit := '0'; -- local co
variable src_msb : slbit := '0'; -- msb from src (bit 15 or 7)
variable dst_msb : slbit := '0'; -- msb from dst (bit 15 or 7)
variable sum_msb : slbit := '0'; -- msb from sum (bit 15 or 7)
alias NO : slbit is CCOUT(3);
alias ZO : slbit is CCOUT(2);
alias VO : slbit is CCOUT(1);
alias CO : slbit is CCOUT(0);
-- procedure do_add8_ci_co: 8 bit adder with carry in and carry out
-- implemented following the recommended pattern for XST ISE V8.1
procedure do_add8_ci_co (
variable a : in slv8; -- input a
variable b : in slv8; -- input b
variable ci : in slbit; -- carry in
variable sum : out slv8; -- sum out
variable co : out slbit -- carry out
) is
variable tmp: slv9;
begin
tmp := conv_std_logic_vector((conv_integer(a) + conv_integer(b) +
conv_integer(ci)),9);
sum := tmp(7 downto 0);
co := tmp(8);
end procedure do_add8_ci_co;
begin
case SRCMOD is
when c_aunit_mod_pass => msrc := DSRC;
when c_aunit_mod_inv => msrc := not DSRC;
when c_aunit_mod_zero => msrc := (others=>'0');
when c_aunit_mod_one => msrc := (others=>'1');
when others => null;
end case;
case DSTMOD is
when c_aunit_mod_pass => mdst := DDST;
when c_aunit_mod_inv => mdst := not DDST;
when c_aunit_mod_zero => mdst := (others=>'0');
when c_aunit_mod_one => mdst := (others=>'1');
when others => null;
end case;
case CIMOD is
when c_aunit_mod_pass => mci := CI;
when c_aunit_mod_inv => mci := not CI;
when c_aunit_mod_zero => mci := '0';
when c_aunit_mod_one => mci := '1';
when others => null;
end case;
do_add8_ci_co(msrc(7 downto 0), mdst(7 downto 0), mci,
sum(7 downto 0), co8);
do_add8_ci_co(msrc(15 downto 8), mdst(15 downto 8), co8,
sum(15 downto 8), co16);
DOUT <= sum;
-- V ('overflow) bit set if
-- ADD : both operants of same sign but has result opposite sign
-- SUB : both operants of opposide sign and sign source equals sign result
-- CMP : both operants of opposide sign and sign dest. equals sign result
nno := '0';
nzo := '0';
nvo := '0';
nco := '0';
if BYTOP = '1' then
nno := sum(7);
if unsigned(sum(7 downto 0)) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co8;
src_msb := DSRC(7);
dst_msb := DDST(7);
sum_msb := sum(7);
else
nno := sum(15);
if unsigned(sum) = 0 then
nzo := '1';
else
nzo := '0';
end if;
nco := co16;
src_msb := DSRC(15);
dst_msb := DDST(15);
sum_msb := sum(15);
end if;
-- the logic for 2 operand V+C is ugly. It is reverse engineered from
-- the MOD's the operation type.
if CC1OP = '0' then -- 2 operand cases
if unsigned(CIMOD) = unsigned(c_aunit_mod_zero) then -- case ADD
nvo := not(src_msb xor dst_msb) and (src_msb xor sum_msb);
else
if unsigned(SRCMOD) = unsigned(c_aunit_mod_inv) then -- case SUB
nvo := (src_msb xor dst_msb) and not (src_msb xor sum_msb);
else -- case CMP
nvo := (src_msb xor dst_msb) and not (dst_msb xor sum_msb);
end if;
nco := not nco; -- invert C for SUB and CMP
end if;
else -- 1 operand cases
case CCMODE is
when c_aunit_ccmode_clr|c_aunit_ccmode_tst =>
nvo := '0'; -- force v=0 for tst and clr
nco := '0'; -- force c=0 for tst and clr
when c_aunit_ccmode_com =>
nvo := '0'; -- force v=0 for com
nco := '1'; -- force c=1 for com
when c_aunit_ccmode_inc =>
nvo := sum_msb and not dst_msb;
nco := CI; -- C not affected for INC
when c_aunit_ccmode_dec =>
nvo := not sum_msb and dst_msb;
nco := CI; -- C not affected for DEC
when c_aunit_ccmode_neg =>
nvo := sum_msb and dst_msb;
nco := not nzo;
when c_aunit_ccmode_adc =>
nvo := sum_msb and not dst_msb;
when c_aunit_ccmode_sbc =>
nvo := not sum_msb and dst_msb;
nco := not nco;
when others => null;
end case;
end if;
NO <= nno;
ZO <= nzo;
VO <= nvo;
CO <= nco;
end process;
end syn;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package my_pkg is
type t_frame_x record is
a : std_logic_vector(1 downto 0);
b : std_logic_vector(17 downto 0);
end record t_frame_x;
end package my_pkg;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: fifo_rx_synth.vhd
--
-- Description:
-- This is the demo testbench for fifo_generator core.
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;
USE ieee.STD_LOGIC_unsigned.ALL;
USE IEEE.STD_LOGIC_arith.ALL;
USE ieee.numeric_std.ALL;
USE ieee.STD_LOGIC_misc.ALL;
LIBRARY std;
USE std.textio.ALL;
LIBRARY work;
USE work.fifo_rx_pkg.ALL;
--------------------------------------------------------------------------------
-- Entity Declaration
--------------------------------------------------------------------------------
ENTITY fifo_rx_synth IS
GENERIC(
FREEZEON_ERROR : INTEGER := 0;
TB_STOP_CNT : INTEGER := 0;
TB_SEED : INTEGER := 1
);
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC;
SIM_DONE : OUT STD_LOGIC;
STATUS : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
);
END ENTITY;
ARCHITECTURE simulation_arch OF fifo_rx_synth IS
-- FIFO interface signal declarations
SIGNAL clk_i : STD_LOGIC;
SIGNAL srst : STD_LOGIC;
SIGNAL wr_en : STD_LOGIC;
SIGNAL rd_en : STD_LOGIC;
SIGNAL din : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL full : STD_LOGIC;
SIGNAL empty : STD_LOGIC;
-- TB Signals
SIGNAL wr_data : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL dout_i : STD_LOGIC_VECTOR(9-1 DOWNTO 0);
SIGNAL wr_en_i : STD_LOGIC := '0';
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL full_i : STD_LOGIC := '0';
SIGNAL empty_i : STD_LOGIC := '0';
SIGNAL almost_full_i : STD_LOGIC := '0';
SIGNAL almost_empty_i : STD_LOGIC := '0';
SIGNAL prc_we_i : STD_LOGIC := '0';
SIGNAL prc_re_i : STD_LOGIC := '0';
SIGNAL dout_chk_i : STD_LOGIC := '0';
SIGNAL rst_int_rd : STD_LOGIC := '0';
SIGNAL rst_int_wr : STD_LOGIC := '0';
SIGNAL rst_gen_rd : STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => '0');
SIGNAL rst_s_wr3 : STD_LOGIC := '0';
SIGNAL rst_s_rd : STD_LOGIC := '0';
SIGNAL reset_en : STD_LOGIC := '0';
SIGNAL rst_async_rd1 : STD_LOGIC := '0';
SIGNAL rst_async_rd2 : STD_LOGIC := '0';
SIGNAL rst_async_rd3 : STD_LOGIC := '0';
SIGNAL rst_sync_rd1 : STD_LOGIC := '0';
SIGNAL rst_sync_rd2 : STD_LOGIC := '0';
SIGNAL rst_sync_rd3 : STD_LOGIC := '0';
BEGIN
---- Reset generation logic -----
rst_int_wr <= rst_async_rd3 OR rst_s_rd;
rst_int_rd <= rst_async_rd3 OR rst_s_rd;
--Testbench reset synchronization
PROCESS(clk_i,RESET)
BEGIN
IF(RESET = '1') THEN
rst_async_rd1 <= '1';
rst_async_rd2 <= '1';
rst_async_rd3 <= '1';
ELSIF(clk_i'event AND clk_i='1') THEN
rst_async_rd1 <= RESET;
rst_async_rd2 <= rst_async_rd1;
rst_async_rd3 <= rst_async_rd2;
END IF;
END PROCESS;
--Synchronous reset generation for FIFO core
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_sync_rd1 <= RESET;
rst_sync_rd2 <= rst_sync_rd1;
rst_sync_rd3 <= rst_sync_rd2;
END IF;
END PROCESS;
--Soft reset for core and testbench
PROCESS(clk_i)
BEGIN
IF(clk_i'event AND clk_i='1') THEN
rst_gen_rd <= rst_gen_rd + "1";
IF(reset_en = '1' AND AND_REDUCE(rst_gen_rd) = '1') THEN
rst_s_rd <= '1';
assert false
report "Reset applied..Memory Collision checks are not valid"
severity note;
ELSE
IF(AND_REDUCE(rst_gen_rd) = '1' AND rst_s_rd = '1') THEN
rst_s_rd <= '0';
assert false
report "Reset removed..Memory Collision checks are valid"
severity note;
END IF;
END IF;
END IF;
END PROCESS;
------------------
---- Clock buffers for testbench ----
clk_i <= CLK;
------------------
srst <= rst_sync_rd3 OR rst_s_rd AFTER 50 ns;
din <= wr_data;
dout_i <= dout;
wr_en <= wr_en_i;
rd_en <= rd_en_i;
full_i <= full;
empty_i <= empty;
fg_dg_nv: fifo_rx_dgen
GENERIC MAP (
C_DIN_WIDTH => 9,
C_DOUT_WIDTH => 9,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP ( -- Write Port
RESET => rst_int_wr,
WR_CLK => clk_i,
PRC_WR_EN => prc_we_i,
FULL => full_i,
WR_EN => wr_en_i,
WR_DATA => wr_data
);
fg_dv_nv: fifo_rx_dverif
GENERIC MAP (
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_USE_EMBEDDED_REG => 0,
TB_SEED => TB_SEED,
C_CH_TYPE => 0
)
PORT MAP(
RESET => rst_int_rd,
RD_CLK => clk_i,
PRC_RD_EN => prc_re_i,
RD_EN => rd_en_i,
EMPTY => empty_i,
DATA_OUT => dout_i,
DOUT_CHK => dout_chk_i
);
fg_pc_nv: fifo_rx_pctrl
GENERIC MAP (
AXI_CHANNEL => "Native",
C_APPLICATION_TYPE => 0,
C_DOUT_WIDTH => 9,
C_DIN_WIDTH => 9,
C_WR_PNTR_WIDTH => 4,
C_RD_PNTR_WIDTH => 4,
C_CH_TYPE => 0,
FREEZEON_ERROR => FREEZEON_ERROR,
TB_SEED => TB_SEED,
TB_STOP_CNT => TB_STOP_CNT
)
PORT MAP(
RESET_WR => rst_int_wr,
RESET_RD => rst_int_rd,
RESET_EN => reset_en,
WR_CLK => clk_i,
RD_CLK => clk_i,
PRC_WR_EN => prc_we_i,
PRC_RD_EN => prc_re_i,
FULL => full_i,
ALMOST_FULL => almost_full_i,
ALMOST_EMPTY => almost_empty_i,
DOUT_CHK => dout_chk_i,
EMPTY => empty_i,
DATA_IN => wr_data,
DATA_OUT => dout,
SIM_DONE => SIM_DONE,
STATUS => STATUS
);
fifo_rx_inst : fifo_rx_exdes
PORT MAP (
CLK => clk_i,
SRST => srst,
WR_EN => wr_en,
RD_EN => rd_en,
DIN => din,
DOUT => dout,
FULL => full,
EMPTY => empty);
END ARCHITECTURE;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - INTC - INTC implementation
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple interrupt controller with variable number of
-- inputs to connect the RECONOS_AXI_FIFO-interrupts to
-- the processor.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic (
-- INTC parameters
C_NUM_INTERRUPTS : integer := 1;
-- Bus protocol parameters
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
);
port (
OSIF_INTC_Rst : in std_logic;
OSIF_INTC_in : in std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
OSIF_INTC_out : out std_logic;
-- Bus protocol ports
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "Clk";
attribute SIGIS of Bus2IP_Resetn : signal is "Rst";
attribute SIGIS of OSIF_INTC_Rst : signal is "Rst";
attribute SIGIS of OSIF_INTC_in : signal is "Intr_Level_High";
attribute SIGIS of OSIF_INTC_out : signal is "Intr_Level_High";
end entity user_logic;
architecture implementation of user_logic is
-- padding to fill unused interrupts in interrupt_reg
signal pad : std_logic_vector(C_SLV_DWIDTH * C_NUM_REG - C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_masked : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_enable : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_reg : std_logic_vector(C_NUM_REG * 32 - 1 downto 0);
signal interrupt_enable_reg : std_logic_vector(C_NUM_REG * 32 - 1 downto 0);
-- Signals for user logic slave model s/w accessible register example
signal slv_reg_write_sel : std_logic_vector(C_NUM_REG - 1 downto 0);
signal slv_reg_read_sel : std_logic_vector(C_NUM_REG - 1 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= Bus2IP_Clk;
rst <= OSIF_INTC_Rst or not Bus2IP_Resetn;
pad <= (others => '0');
interrupt_enable <= interrupt_enable_reg(C_NUM_INTERRUPTS - 1 downto 0);
interrupt_masked <= OSIF_INTC_in and interrupt_enable;
-- interrupt register only contains enabled interrupts
interrupt_reg <= pad & interrupt_masked;
OSIF_INTC_Out <= or_reduce(interrupt_masked);
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
-- Example code to drive IP to Bus signals
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
slv_reg_write_sel <= Bus2IP_WrCE;
slv_reg_read_sel <= Bus2IP_RdCE;
slv_write_ack <= or_reduce(Bus2IP_WrCE);
slv_read_ack <= or_reduce(Bus2IP_RdCE);
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
int_enable_reg_proc : process(clk,rst) is
begin
if rst = '1' then
interrupt_enable_reg <= (others => '0');
elsif rising_edge(clk) then
for i in 0 to C_NUM_REG - 1 loop
if slv_reg_write_sel(C_NUM_REG - 1 - i) = '1' then
interrupt_enable_reg(32 * i + 31 downto 32 * i) <= Bus2IP_Data;
end if;
end loop;
end if;
end process int_enable_reg_proc;
bus_read_reg_proc : process(slv_reg_read_sel) is
begin
for i in 0 to C_NUM_REG - 1 loop
if slv_reg_read_sel(C_NUM_REG - 1 - i) = '1' then
slv_ip2bus_data <= interrupt_reg(32 * i + 31 downto 32 * i);
end if;
end loop;
end process bus_read_reg_proc;
end implementation;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - INTC - INTC implementation
--
-- project: ReconOS
-- author: Christoph Rüthing, University of Paderborn
-- description: A simple interrupt controller with variable number of
-- inputs to connect the RECONOS_AXI_FIFO-interrupts to
-- the processor.
--
-- ======================================================================
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_misc.all;
library proc_common_v3_00_a;
use proc_common_v3_00_a.proc_common_pkg.all;
entity user_logic is
generic (
-- INTC parameters
C_NUM_INTERRUPTS : integer := 1;
-- Bus protocol parameters
C_NUM_REG : integer := 1;
C_SLV_DWIDTH : integer := 32
);
port (
OSIF_INTC_Rst : in std_logic;
OSIF_INTC_in : in std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
OSIF_INTC_out : out std_logic;
-- Bus protocol ports
Bus2IP_Clk : in std_logic;
Bus2IP_Resetn : in std_logic;
Bus2IP_Data : in std_logic_vector(C_SLV_DWIDTH-1 downto 0);
Bus2IP_BE : in std_logic_vector(C_SLV_DWIDTH/8-1 downto 0);
Bus2IP_RdCE : in std_logic_vector(C_NUM_REG-1 downto 0);
Bus2IP_WrCE : in std_logic_vector(C_NUM_REG-1 downto 0);
IP2Bus_Data : out std_logic_vector(C_SLV_DWIDTH-1 downto 0);
IP2Bus_RdAck : out std_logic;
IP2Bus_WrAck : out std_logic;
IP2Bus_Error : out std_logic
);
attribute MAX_FANOUT : string;
attribute SIGIS : string;
attribute SIGIS of Bus2IP_Clk : signal is "Clk";
attribute SIGIS of Bus2IP_Resetn : signal is "Rst";
attribute SIGIS of OSIF_INTC_Rst : signal is "Rst";
attribute SIGIS of OSIF_INTC_in : signal is "Intr_Level_High";
attribute SIGIS of OSIF_INTC_out : signal is "Intr_Level_High";
end entity user_logic;
architecture implementation of user_logic is
-- padding to fill unused interrupts in interrupt_reg
signal pad : std_logic_vector(C_SLV_DWIDTH * C_NUM_REG - C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_masked : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_enable : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
signal interrupt_reg : std_logic_vector(C_NUM_REG * 32 - 1 downto 0);
signal interrupt_enable_reg : std_logic_vector(C_NUM_REG * 32 - 1 downto 0);
-- Signals for user logic slave model s/w accessible register example
signal slv_reg_write_sel : std_logic_vector(C_NUM_REG - 1 downto 0);
signal slv_reg_read_sel : std_logic_vector(C_NUM_REG - 1 downto 0);
signal slv_ip2bus_data : std_logic_vector(C_SLV_DWIDTH - 1 downto 0);
signal slv_read_ack : std_logic;
signal slv_write_ack : std_logic;
signal clk : std_logic;
signal rst : std_logic;
begin
clk <= Bus2IP_Clk;
rst <= OSIF_INTC_Rst or not Bus2IP_Resetn;
pad <= (others => '0');
interrupt_enable <= interrupt_enable_reg(C_NUM_INTERRUPTS - 1 downto 0);
interrupt_masked <= OSIF_INTC_in and interrupt_enable;
-- interrupt register only contains enabled interrupts
interrupt_reg <= pad & interrupt_masked;
OSIF_INTC_Out <= or_reduce(interrupt_masked);
-- Bus2IP_WrCE/Bus2IP_RdCE Memory Mapped Register
-- "1000" C_BASEADDR + 0x0
-- "0100" C_BASEADDR + 0x4
-- "0010" C_BASEADDR + 0x8
-- "0001" C_BASEADDR + 0xC
-- Example code to drive IP to Bus signals
IP2Bus_Data <= slv_ip2bus_data when slv_read_ack = '1' else (others => '0');
slv_reg_write_sel <= Bus2IP_WrCE;
slv_reg_read_sel <= Bus2IP_RdCE;
slv_write_ack <= or_reduce(Bus2IP_WrCE);
slv_read_ack <= or_reduce(Bus2IP_RdCE);
IP2Bus_WrAck <= slv_write_ack;
IP2Bus_RdAck <= slv_read_ack;
IP2Bus_Error <= '0';
int_enable_reg_proc : process(clk,rst) is
begin
if rst = '1' then
interrupt_enable_reg <= (others => '0');
elsif rising_edge(clk) then
for i in 0 to C_NUM_REG - 1 loop
if slv_reg_write_sel(C_NUM_REG - 1 - i) = '1' then
interrupt_enable_reg(32 * i + 31 downto 32 * i) <= Bus2IP_Data;
end if;
end loop;
end if;
end process int_enable_reg_proc;
bus_read_reg_proc : process(slv_reg_read_sel) is
begin
for i in 0 to C_NUM_REG - 1 loop
if slv_reg_read_sel(C_NUM_REG - 1 - i) = '1' then
slv_ip2bus_data <= interrupt_reg(32 * i + 31 downto 32 * i);
end if;
end loop;
end process bus_read_reg_proc;
end implementation;
|
architecture RTL of FIFO is
begin
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
-- Violations below
process
variable var1 : integer;
begin
end process;
process (a, b)
variable var1 : integer;
begin
end process;
process is
variable var1 : integer;
begin
end process;
process
begin
end process;
end architecture RTL;
|
----------------------------------------------------------------------------------
-- Company: LARC - Escola Politecnica - University of Sao Paulo
-- Engineer: Pedro Maat C. Massolino
--
-- Create Date: 05/12/2012
-- Design Name: Counter_decrement_load_rst_n_bits
-- Module Name: Counter_decrement_load_rst_n_bits
-- Project Name: Essentials
-- Target Devices: Any
-- Tool versions: Xilinx ISE 13.3 WebPack
--
-- Description:
--
-- Counter of size bits with reset signal, that only decrements when ce equals to 1.
-- The reset is synchronous and the value loaded during reset is defined by reset_value.
-- The counter has a synchronous load signal, which will register the value on input d,
-- when load is 1 and reset is 0.
--
-- The circuits parameters
--
-- size :
--
-- The size of the counter in bits.
--
-- decrement_value :
--
-- The amount will be decremented each cycle.
--
-- Dependencies:
-- VHDL-93
--
--
-- Revision:
-- Revision 1.0
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity counter_decrement_load_rst_nbits is
Generic (
size : integer;
decrement_value : integer
);
Port (
d : in STD_LOGIC_VECTOR((size - 1) downto 0);
clk : in STD_LOGIC;
load : in STD_LOGIC;
ce : in STD_LOGIC;
rst : in STD_LOGIC;
rst_value : in STD_LOGIC_VECTOR((size - 1) downto 0);
q : out STD_LOGIC_VECTOR((size - 1) downto 0)
);
end counter_decrement_load_rst_nbits;
architecture Behavioral of counter_decrement_load_rst_nbits is
signal internal_value : UNSIGNED((size - 1) downto 0);
begin
process(clk, ce, rst)
begin
if(clk'event and clk = '1')then
if(rst = '1') then
internal_value <= unsigned(rst_value);
elsif(ce = '1') then
if(load = '1') then
internal_value <= unsigned(d);
else
internal_value <= internal_value - to_unsigned(decrement_value, internal_value'Length);
end if;
else
null;
end if;
end if;
end process;
q <= std_logic_vector(internal_value);
end Behavioral; |
--------------------------------------------------------------------------------
--Copyright (c) 2014, Benjamin Bässler <[email protected]>
--All rights reserved.
--
--Redistribution and use in source and binary forms, with or without
--modification, are permitted provided that the following conditions are met:
--
--* Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
--
--* Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
--
--THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
--AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
--IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
--FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
--DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
--SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
--CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
--OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
--OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--------------------------------------------------------------------------------
--! @file tb_labeling_p1.vhd
--! @brief testbench for the 1. pass of component labeling
--! @author Benjamin Bässler
--! @email [email protected]
--! @date 2013-06-04
--------------------------------------------------------------------------------
--! Use standard library
library ieee;
use ieee.std_logic_1164.all;
--! Use numeric std
use IEEE.numeric_std.all;
use work.pbm_package.all;
use work.types.all;
use work.utils.all;
--! Reads in a PPM file an use it as input for connected component labeling
entity tb_labeling_p1 is
end tb_labeling_p1;
architecture Behavioral of tb_labeling_p1 is
constant infile : String := "../../img/sim_in.pbm";
constant half_period : Time := 10 ns; -- generate 50MHz clock
Signal clk_in_s : STD_LOGIC := '0';
Signal rst_in_s : STD_LOGIC := '1';
Signal px_in_s : STD_LOGIC;
Signal stall_out_s : STD_LOGIC;
Signal stall_in_s : STD_LOGIC;
Signal img_width_in_s : UNSIGNED(log2_ceil(C_MAX_IMAGE_WIDTH) downto 0);
Signal img_height_in_s : UNSIGNED(log2_ceil(C_MAX_IMAGE_HEIGHT) downto 0);
Signal next_lable_in_s : T_LABEL;
Signal gen_lable_out_s : STD_LOGIC;
Signal equi_out_s : T_EQUI;
Signal equi_valid_out_s : STD_LOGIC;
Signal label_out_s : T_LABEL;
Signal px_valid_in_s : STD_LOGIC;
Signal last_lookup_in_s : STD_LOGIC;
Signal equi_ready_out_s : STD_LOGIC;
-- used to turn the clock off after simulation
Signal clk_en_s : STD_LOGIC := '1';
begin
dut_labeling_p1 : entity work.labeling_p1 PORT MAP(
clk_in => clk_in_s,
rst_in => rst_in_s,
stall_out => stall_out_s,
stall_in => stall_in_s,
px_in => px_in_s,
px_valid_in => px_valid_in_s,
img_width_in => img_width_in_s,
img_height_in => img_height_in_s,
next_lable_in => next_lable_in_s,
gen_lable_out => gen_lable_out_s,
equi_out => equi_out_s,
equi_valid_out => equi_valid_out_s,
label_out => label_out_s,
last_lbl_out => open
);
dut_lookup_table : entity work.lookup_table PORT MAP(
clk_in => clk_in_s,
rst_in => rst_in_s,
stall_out => stall_in_s,
next_lable_out => next_lable_in_s,
gen_lable_in => gen_lable_out_s,
equi_in => equi_out_s,
equi_valid_in => equi_valid_out_s,
lookup_ready_out => equi_ready_out_s,
last_look_up_in => last_lookup_in_s,
lookup_in => to_unsigned(1, T_LABEL'length),
lookup_out => open
);
rst_in_s <= '1' after 50 ns, '0' after 100 ns; -- generate initial reset
clk_p : process
begin
while clk_en_s = '1' loop
clk_in_s <= not clk_in_s;
wait for half_period;
end loop;
wait;
end process clk_p;
test_p : process
variable img_width : natural;
variable img_height : natural;
variable image : image_type;
variable first : boolean := true;
begin
read_pbm(infile, image, img_width, img_height);
stall_in_s <= '0';
px_valid_in_s <= '0';
last_lookup_in_s <= '0';
img_width_in_s <= to_unsigned(img_width, img_width_in_s'length);
img_height_in_s <= to_unsigned(img_height, img_height_in_s'length);
wait until rst_in_s = '0';
wait until clk_in_s = '1';
wait for half_period;
for y in 1 to img_height loop
for x in 1 to img_width loop
px_in_s <= image(y)(x);
px_valid_in_s <= '1';
if y = img_height and x = img_width then
last_lookup_in_s <= '1';
end if;
wait for half_period*2;
report "Label: " & INTEGER'IMAGE(TO_INTEGER(label_out_s));
end loop;
end loop;
px_valid_in_s <= '0';
if equi_ready_out_s = '0' then
wait until equi_ready_out_s = '1';
wait for half_period*2;
end if;
clk_en_s <= '0';
wait;
end process test_p;
end architecture Behavioral;
|
library IEEE;
use IEEE.std_logic_1164.all;
use ieee.numeric_std.all;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
--This component receives the real value of the tip of the vector. Then, for every bit value, it checks if it should be painted or not according to the real value.
entity memory_writer is
generic(ROWS : integer := 350; COLUMNS : integer := 350; BITS : integer := 32);
port(
clk : in std_logic := '0';
enable : in std_logic := '0';
rst : in std_logic := '0';
pixel_x : out std_logic_vector(9 downto 0) := (others => '0');
pixel_y : out std_logic_vector(9 downto 0) := (others => '0');
pixel_on : out std_logic_vector(0 downto 0) := (others => '0')
);
end entity;
architecture memory_writer_arq of memory_writer is
constant AXIS_X_BIT : std_logic_vector(9 downto 0) := std_logic_vector(shift_right(to_unsigned(COLUMNS,10),1));
constant AXIS_Y_BIT : std_logic_vector(9 downto 0) := std_logic_vector(shift_right(to_unsigned(ROWS,10),1));
constant ONE : unsigned(BITS - 1 downto 0) := "00000000000000010000000000000000"; --1.0
constant PIXEL_COEF : std_logic_vector(BITS - 1 downto 0) := "00000000101011110000000000000000"; --350/2 to account for the displacement by 1
constant MAX_POSITION : integer := 177;
constant ROTATION_ANGLE : signed(31 downto 0) := "00000000000000001011010000000000"; --0.703125 degrees
--constant ROTATION_ANGLE : signed(31 downto 0) := "00000000000000000000000000000000";
signal clk_signal : std_logic := '0';
--Signals to memory
signal x_read_address_to_memory : std_logic_vector(9 downto 0) := (others => '0');
--Signals from memory
signal memory_read_x : std_logic_vector(15 downto 0) := (others => '0');
--Signals to preprocessor
signal preprocessor_x_input : std_logic_vector(BITS-1 downto 0) := (others => '0');
signal preprocessor_y_input : std_logic_vector(BITS-1 downto 0) := (others => '0');
signal preprocessor_angle_input : std_logic_vector(BITS-1 downto 0) := (others => '0');
--Signals to cordic
signal preprocessor_x_output_to_cordic : std_logic_vector(BITS - 1 downto 0) := (others => '0');
signal preprocessor_y_output_to_cordic : std_logic_vector(BITS - 1 downto 0) := (others => '0');
signal preprocessor_angle_output_to_cordic : std_logic_vector(BITS - 1 downto 0) := (others => '0');
--Output signals
signal output_x_from_cordic : std_logic_vector(BITS - 1 downto 0 ) := (others => '0');
signal output_y_from_cordic : std_logic_vector(BITS - 1 downto 0 ) := (others => '0');
--Mapped values
signal decimal_x : std_logic_vector(31 downto 0) := (others => '0');
signal decimal_y : std_logic_vector(31 downto 0) := (others => '0');
signal mapped_x : std_logic_vector(63 downto 0) := (others => '0');
signal mapped_y : std_logic_vector(63 downto 0) := (others => '0');
component cordic is
generic(TOTAL_BITS: integer := 32; STEPS: integer := 16);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
component preprocessor is
generic(TOTAL_BITS: integer := 32);
port(
x_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_in: in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_in : in std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
x_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
y_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0');
angle_out: out std_logic_vector(TOTAL_BITS - 1 downto 0) := (others => '0')
);
end component;
component multiplier is
port(
op_1_in: in std_logic_vector(31 downto 0) := (others => '0');
op_2_in: in std_logic_vector(31 downto 0) := (others => '0');
result_out: out std_logic_vector(63 downto 0) := (others => '0')
);
end component;
begin
clk_signal <= clk;
preprocessor_0 : preprocessor
port map(
x_in => preprocessor_x_input,
y_in => preprocessor_y_input,
angle_in => preprocessor_angle_input,
x_out => preprocessor_x_output_to_cordic,
y_out => preprocessor_y_output_to_cordic,
angle_out => preprocessor_angle_output_to_cordic
);
cordic_0 : cordic
port map(
x_in => preprocessor_x_output_to_cordic,
y_in => preprocessor_y_output_to_cordic,
angle => preprocessor_angle_output_to_cordic,
x_out => output_x_from_cordic,
y_out => output_y_from_cordic
);
multiplier_0 : multiplier
port map(
op_1_in => decimal_x,
op_2_in => PIXEL_COEF,
result_out => mapped_x
);
multiplier_1 : multiplier
port map(
op_1_in => decimal_y,
op_2_in => PIXEL_COEF,
result_out => mapped_y
);
x_values_ram: RAMB16_S18_S18
generic map(WRITE_MODE_B => "READ_FIRST",
INIT_00 => X"176715F1147A1304118D10170EA00D2A0BB30A3D08C6075005D9046302EC0176",
INIT_01 => X"2ECF2D592BE22A6C28F5277F26082492231B21A5202E1EB81D411BCB1A5418DE",
INIT_02 => X"463744C1434A41D4405D3EE73D703BFA3A83390D3796362034A9333331BC3046",
INIT_03 => X"5D9F5C285AB2593B57C5564E54D8536251EB50754EFE4D884C114A9B492447AE",
INIT_04 => X"75077390721A70A36F2D6DB66C406AC9695367DC666664EF63796202608C5F15",
INIT_05 => X"8C6F8AF88982880B8695851E83A8823180BB7F447DCE7C577AE1796A77F4767D",
INIT_06 => X"A3D7A260A0EA9F739DFD9C869B109999982396AC953693BF924990D28F5C8DE5",
INIT_07 => X"BB3EB9C8B851B6DBB564B3EEB277B101AF8AAE14AC9DAB27A9B1A83AA6C4A54D",
INIT_08 => X"D2A6D130CFB9CE43CCCCCB56C9DFC869C6F2C57CC405C28FC118BFA2BE2BBCB5",
INIT_09 => X"EA0EE898E721E5ABE434E2BEE147DFD1DE5ADCE4DB6DD9F7D880D70AD593D41D",
INIT_0a => X"FFFFFFFFFE89FD13FB9CFA26F8AFF739F5C2F44CF2D5F15FEFE8EE72ECFBEB85"
)
port map (
DOA => open,
DOB => memory_read_x,
ADDRA => (others => '0'),
ADDRB => x_read_address_to_memory,
DIPA => (others => '0'),
DIPB => (others => '0'),
CLKA => '0',
CLKB => clk_signal,
DIA => (others => '0'),
DIB => (others => '0'),
ENA => '0',
ENB => enable,
SSRA => '0',
SSRB => '0',
WEA => '0',
WEB => '0'
);
--y_values_ram: RAMB16_S18_S18
-- generic map(WRITE_MODE_B => "READ_FIRST")
-- port map (
-- DOA => open,
-- DOB => memory_read_y,
-- ADDRA => open,
-- ADDRB => y_read_address_to_memory,
-- DIPA => (others => '0'),
-- DIPB => (others => '0'),
-- CLKA => clk_signal,
-- CLKB => clk_signal,
-- DIA => y_input_to_memory,
-- DIB => (others => '0'),
-- ENA => enable,
-- ENB => enable,
-- SSRA => '0',
-- SSRB => '0',
-- WEA => enable,
-- WEB => '0'
-- );
preprocessor_x_input <= ("0000000000000000" & memory_read_x);
preprocessor_y_input <= (others => '0');
process(clk, rst)
variable moved_x : unsigned(BITS - 1 downto 0) := (others => '0');
variable moved_y : unsigned(BITS - 1 downto 0) := (others => '0');
variable extended_moved_x_bit : std_logic_vector(BITS * 2 - 1 downto 0) := (others => '0');
variable extended_moved_y_bit_unsigned : unsigned(BITS * 2 - 1 downto 0) := (others => '0');
variable truncated_extended_moved_y_bit_unsigned : unsigned(9 downto 0) := (others => '0');
variable inverted_y_bit : unsigned(9 downto 0) := (others => '0');
variable extended_moved_y_bit : std_logic_vector(BITS * 2 - 1 downto 0) := (others => '0');
variable moved_x_bit : std_logic_vector(9 downto 0) := (others => '0');
variable moved_y_bit : std_logic_vector(9 downto 0) := (others => '0');
variable point_position : integer := 0;
variable erasing_x : integer := 0;
variable erasing_y : integer := 0;
variable should_erase : std_logic := '0';
variable done_writing : std_logic := '0';
variable accumulated_angle : signed(BITS - 1 downto 0) := (others => '0');
begin
if(rising_edge(clk)) then
--If rst is 1 we should either erase previous values or start writing the new ones
if(rst = '1') then
if(should_erase = '1') then
erasing_x := erasing_x + 1;
if(erasing_x = COLUMNS) then
erasing_x := 0;
erasing_y := erasing_y + 1;
end if;
if(erasing_y = ROWS) then
should_erase := '0';
end if;
report "ERASING: " & integer'image(erasing_x) & ":" & integer'image(erasing_y);
pixel_x <= std_logic_vector(to_unsigned(erasing_x, 10));
pixel_y <= std_logic_vector(to_unsigned(erasing_y, 10));
pixel_on <= (others => '0');
point_position := 0;
x_read_address_to_memory <= std_logic_vector(to_unsigned(point_position,10));
else --We should start writing the next values
if(point_position >= 0 and point_position < MAX_POSITION) then
point_position := point_position + 1;
--Compute address to set to memory
x_read_address_to_memory <= std_logic_vector(to_unsigned(point_position,10));
--To give time to the cordic to process the data, we shall draw the previous point and in the end set the next point to be processed
moved_x := unsigned(output_x_from_cordic) + ONE; --Move the x value to the right so that all it's posible locations are a positive number
moved_y := unsigned(output_y_from_cordic) + ONE; --Move the y value up so that all it's possible locations are a positive number
decimal_x <= std_logic_vector(moved_x);
extended_moved_x_bit := mapped_x; --Compute the pixel location
moved_x_bit := extended_moved_x_bit(32 + 9 downto 32); --Truncate to integer value
decimal_y <= std_logic_vector(moved_y);
extended_moved_y_bit_unsigned := unsigned(mapped_y); --Compute the pixel location
truncated_extended_moved_y_bit_unsigned := extended_moved_y_bit_unsigned(32 + 9 downto 32); --Truncate to integer value
inverted_y_bit := ROWS - truncated_extended_moved_y_bit_unsigned;
moved_y_bit := std_logic_vector(inverted_y_bit);
report "WRITTING: " & integer'image(point_position);
pixel_x <= moved_x_bit;
pixel_y <= moved_y_bit;
pixel_on <= "1";
else
report "DONE WRITTING -> WAITING_TO_ERASE";
pixel_on <= "0";
erasing_x := 0;
erasing_y := 0;
end if;
end if;
else
report "VIDEO ON, DONT MODIFY MEMORY";
if(should_erase = '0') then
accumulated_angle := accumulated_angle + ROTATION_ANGLE;
preprocessor_angle_input <= std_logic_vector(accumulated_angle);
end if;
should_erase := '1';
erasing_x := 0;
erasing_y := 0;
end if;
end if;
end process;
end memory_writer_arq; |
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_194 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(29 downto 0)
);
end add_194;
architecture augh of add_194 is
signal carry_inA : std_logic_vector(31 downto 0);
signal carry_inB : std_logic_vector(31 downto 0);
signal carry_res : std_logic_vector(31 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(30 downto 1);
end architecture;
|
library ieee;
use ieee.std_logic_1164.all;
library ieee;
use ieee.numeric_std.all;
entity add_194 is
port (
result : out std_logic_vector(29 downto 0);
in_a : in std_logic_vector(29 downto 0);
in_b : in std_logic_vector(29 downto 0)
);
end add_194;
architecture augh of add_194 is
signal carry_inA : std_logic_vector(31 downto 0);
signal carry_inB : std_logic_vector(31 downto 0);
signal carry_res : std_logic_vector(31 downto 0);
begin
-- To handle the CI input, the operation is '1' + CI
-- If CI is not present, the operation is '1' + '0'
carry_inA <= '0' & in_a & '1';
carry_inB <= '0' & in_b & '0';
-- Compute the result
carry_res <= std_logic_vector(unsigned(carry_inA) + unsigned(carry_inB));
-- Set the outputs
result <= carry_res(30 downto 1);
end architecture;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenFILTER
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv and RxDat have to be synchron to Clk
-- The following Conditions are checked:
-- RxDV >163.64µsec HIGH -> invalid
-- RxDV <0.64µsec LOW -> invalid
-- RxDV 4x <5.12µsec HIGH -> invalid
-- RxDV >5.12µsec HIGH -> valid
-- RxErr HIGH -> invalid
-- if invalid deactivation of port, until RxDv and RxErr > 10.24µsec low
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V1.1 to first official version.
-- 2011-07-23 V0.10 zelenkaj Consideration of RX Error signal and jitter (converted from V2.3)
-- 2011-08-03 V0.11 zelenkaj translated comments
-- 2011-11-18 V0.12 zelenkaj bypass filter by generic
-- 2011-11-28 V0.13 zelenkaj Changed reset level to high-active
-- 2012-04-19 V0.20 zelenkaj Redesign with fsm, Preamble-check improvement
-- 2012-05-21 V0.21 muelhausens changed timeout of fs_FRMnopre to 660ns
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY openFILTER is
Generic (
bypassFilter : boolean := false
);
Port ( Rst : in std_logic;
Clk : in std_logic;
nCheckShortFrames : in std_logic := '0'; -- Rx Port von Hub;
RxDvIn : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
RxDatOut : out std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
TxDatIn : in std_logic_vector(1 downto 0);
TxEnOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
RxErr : in std_logic := '0'
);
END ENTITY openFILTER;
ARCHITECTURE rtl OF openFILTER IS
type aRxSet is record
RxDv : std_logic;
RxDat: std_logic_vector(1 downto 0);
end record;
type aRxSetArr is array (3 downto 0) of aRxSet;
type aFiltState is (fs_init, fs_GAP2short, fs_GAPext, fs_GAPok, fs_FRMnopre,
fs_FRMpre2short, fs_FRMpreOk, fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll);
signal FiltState : aFiltState;
signal RxDel : aRxSetArr;
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
BEGIN
disFilter : if bypassFilter generate
begin
RxDvOut <= RxDvIn;
RxDatOut <= RxDatIn;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
end generate;
enFilter : if not bypassFilter generate
begin
-- IN --
RxDel(0).RxDv <= RxDvIn;
RxDel(0).RxDat <= RxDatIn;
BlockRxPort <= '1' when FiltState = fs_FRMnopre or FiltState = fs_BlockAll or LastFrameNOK = '1' else '0';
-- OUTPUT MUX --
RxDvOut <= '0' when BlockRxPort = '1' else
RxDel(3).RxDv when FrameShift = '1' else
RxDel(1).RxDv;
RxDatOut <= "00" when BlockRxPort = '1' else
RxDel(3).RxDat when FrameShift = '1' else
RxDel(1).RxDat;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
fsm: PROCESS(Rst, Clk)
VARIABLE RstStCnt : std_logic;
begin
if Rst = '1' then
StCnt <= (others => '0');
FiltState <= fs_init;
FrameShift <= '0';
RxDel(3 downto 1) <= (others => ('0',"00"));
LastFrameNOK <= '0';
elsif rising_edge(Clk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := '0';
case FiltState is
-------------------------------- INIT ---------------------------------------
when fs_init =>
FiltState <= fs_GAP2short; RstStCnt := '1';
-------------------------------- GAP 2 SHORT --------------------------------
when fs_GAP2short =>
FrameShift <= '0';
IF StCnt(4) = '1' then FiltState <= fs_GAPext; END IF; -- 360ns
IF RxDel(0).RxDv = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- Gap < 360 ns -> too short -> Block Filter
-------------------------------- GAP EXTEND ---------------------------------
when fs_GAPext =>
IF StCnt(5 downto 0) = "101110" then FiltState <= fs_GAPok; END IF;
IF RxDel(0).RxDv = '1' then -- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := '1';
FrameShift <= '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- GAP OK -------------------------------------
when fs_GAPok =>
IF RxDel(0).RxDv = '1' then
RstStCnt := '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- FRAME, BUT STILL NO PREAMBLE ---------------
when fs_FRMnopre =>
IF StCnt(5) = '1' or -- no preamble for >=660 ns -> Block Filter
RxDel(0).RxDat = "11" or RxDel(0).RxDat = "10" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
elsif RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; RstStCnt := '1'; -- preamble starts -> Check Preamble
END IF;
-------------------------------- FRAME CHECK PREAMBLE TOO SHORT --------------
when fs_FRMpre2short =>
IF RxDel(0).RxDat /= "01" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
ELSIF StCnt(3) = '1' then FiltState <= fs_FRMpreOk; END IF; -- preamble ok for 180 ns -> Preamble OK
-------------------------------- FRAME CHECK PREAMBLE OK ---------------
when fs_FRMpreOk =>
IF RxDel(0).RxDat /= "01" then FiltState <= fs_FRMok; END IF; -- preamble done -> Start Frame
IF (StCnt(5) = '1' and StCnt(2) = '1') or -- preamble to long for 740 ns -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF;
LastFrameNOK <= '0'; -- preamble is OK
-------------------------------- FRAME OK -----------------------------------
when fs_FRMok =>
IF StCnt(13) = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- FRAME > 163,842 us -> too long -> Block Filter
IF RxDel(0).RxDv = '0' and
RxDel(1).RxDv = '0' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- FRAME [163,842 us] -> OK -> Start GAP
-------------------------------- Block Filter -------------------------------
when fs_BlockAll =>
IF StCnt(2) = '1' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- Block for 100 nsec
IF RxDel(0).RxDv = '1' then RstStCnt := '1'; END IF; -- RxDv != '0' -> Reset Wait Period
LastFrameNOK <= '1'; -- block next rx frame (until receive a valid preamble)
when others =>
FiltState <= fs_init;
end case;
IF RxErr = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- RxErr -> Block Filter
-- State Counter --
StCnt <= StCnt + 1;
if RstStCnt = '1' then StCnt <= (others => '0'); end if;
end if;
end process;
end generate;
END rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenFILTER
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv and RxDat have to be synchron to Clk
-- The following Conditions are checked:
-- RxDV >163.64µsec HIGH -> invalid
-- RxDV <0.64µsec LOW -> invalid
-- RxDV 4x <5.12µsec HIGH -> invalid
-- RxDV >5.12µsec HIGH -> valid
-- RxErr HIGH -> invalid
-- if invalid deactivation of port, until RxDv and RxErr > 10.24µsec low
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V1.1 to first official version.
-- 2011-07-23 V0.10 zelenkaj Consideration of RX Error signal and jitter (converted from V2.3)
-- 2011-08-03 V0.11 zelenkaj translated comments
-- 2011-11-18 V0.12 zelenkaj bypass filter by generic
-- 2011-11-28 V0.13 zelenkaj Changed reset level to high-active
-- 2012-04-19 V0.20 zelenkaj Redesign with fsm, Preamble-check improvement
-- 2012-05-21 V0.21 muelhausens changed timeout of fs_FRMnopre to 660ns
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY openFILTER is
Generic (
bypassFilter : boolean := false
);
Port ( Rst : in std_logic;
Clk : in std_logic;
nCheckShortFrames : in std_logic := '0'; -- Rx Port von Hub;
RxDvIn : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
RxDatOut : out std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
TxDatIn : in std_logic_vector(1 downto 0);
TxEnOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
RxErr : in std_logic := '0'
);
END ENTITY openFILTER;
ARCHITECTURE rtl OF openFILTER IS
type aRxSet is record
RxDv : std_logic;
RxDat: std_logic_vector(1 downto 0);
end record;
type aRxSetArr is array (3 downto 0) of aRxSet;
type aFiltState is (fs_init, fs_GAP2short, fs_GAPext, fs_GAPok, fs_FRMnopre,
fs_FRMpre2short, fs_FRMpreOk, fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll);
signal FiltState : aFiltState;
signal RxDel : aRxSetArr;
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
BEGIN
disFilter : if bypassFilter generate
begin
RxDvOut <= RxDvIn;
RxDatOut <= RxDatIn;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
end generate;
enFilter : if not bypassFilter generate
begin
-- IN --
RxDel(0).RxDv <= RxDvIn;
RxDel(0).RxDat <= RxDatIn;
BlockRxPort <= '1' when FiltState = fs_FRMnopre or FiltState = fs_BlockAll or LastFrameNOK = '1' else '0';
-- OUTPUT MUX --
RxDvOut <= '0' when BlockRxPort = '1' else
RxDel(3).RxDv when FrameShift = '1' else
RxDel(1).RxDv;
RxDatOut <= "00" when BlockRxPort = '1' else
RxDel(3).RxDat when FrameShift = '1' else
RxDel(1).RxDat;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
fsm: PROCESS(Rst, Clk)
VARIABLE RstStCnt : std_logic;
begin
if Rst = '1' then
StCnt <= (others => '0');
FiltState <= fs_init;
FrameShift <= '0';
RxDel(3 downto 1) <= (others => ('0',"00"));
LastFrameNOK <= '0';
elsif rising_edge(Clk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := '0';
case FiltState is
-------------------------------- INIT ---------------------------------------
when fs_init =>
FiltState <= fs_GAP2short; RstStCnt := '1';
-------------------------------- GAP 2 SHORT --------------------------------
when fs_GAP2short =>
FrameShift <= '0';
IF StCnt(4) = '1' then FiltState <= fs_GAPext; END IF; -- 360ns
IF RxDel(0).RxDv = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- Gap < 360 ns -> too short -> Block Filter
-------------------------------- GAP EXTEND ---------------------------------
when fs_GAPext =>
IF StCnt(5 downto 0) = "101110" then FiltState <= fs_GAPok; END IF;
IF RxDel(0).RxDv = '1' then -- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := '1';
FrameShift <= '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- GAP OK -------------------------------------
when fs_GAPok =>
IF RxDel(0).RxDv = '1' then
RstStCnt := '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- FRAME, BUT STILL NO PREAMBLE ---------------
when fs_FRMnopre =>
IF StCnt(5) = '1' or -- no preamble for >=660 ns -> Block Filter
RxDel(0).RxDat = "11" or RxDel(0).RxDat = "10" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
elsif RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; RstStCnt := '1'; -- preamble starts -> Check Preamble
END IF;
-------------------------------- FRAME CHECK PREAMBLE TOO SHORT --------------
when fs_FRMpre2short =>
IF RxDel(0).RxDat /= "01" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
ELSIF StCnt(3) = '1' then FiltState <= fs_FRMpreOk; END IF; -- preamble ok for 180 ns -> Preamble OK
-------------------------------- FRAME CHECK PREAMBLE OK ---------------
when fs_FRMpreOk =>
IF RxDel(0).RxDat /= "01" then FiltState <= fs_FRMok; END IF; -- preamble done -> Start Frame
IF (StCnt(5) = '1' and StCnt(2) = '1') or -- preamble to long for 740 ns -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF;
LastFrameNOK <= '0'; -- preamble is OK
-------------------------------- FRAME OK -----------------------------------
when fs_FRMok =>
IF StCnt(13) = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- FRAME > 163,842 us -> too long -> Block Filter
IF RxDel(0).RxDv = '0' and
RxDel(1).RxDv = '0' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- FRAME [163,842 us] -> OK -> Start GAP
-------------------------------- Block Filter -------------------------------
when fs_BlockAll =>
IF StCnt(2) = '1' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- Block for 100 nsec
IF RxDel(0).RxDv = '1' then RstStCnt := '1'; END IF; -- RxDv != '0' -> Reset Wait Period
LastFrameNOK <= '1'; -- block next rx frame (until receive a valid preamble)
when others =>
FiltState <= fs_init;
end case;
IF RxErr = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- RxErr -> Block Filter
-- State Counter --
StCnt <= StCnt + 1;
if RstStCnt = '1' then StCnt <= (others => '0'); end if;
end if;
end process;
end generate;
END rtl;
|
------------------------------------------------------------------------------------------------------------------------
-- OpenFILTER
--
-- Copyright (C) 2009 B&R
--
-- Redistribution and use in source and binary forms, with or without
-- modification, are permitted provided that the following conditions
-- are met:
--
-- 1. Redistributions of source code must retain the above copyright
-- notice, this list of conditions and the following disclaimer.
--
-- 2. Redistributions in binary form must reproduce the above copyright
-- notice, this list of conditions and the following disclaimer in the
-- documentation and/or other materials provided with the distribution.
--
-- 3. Neither the name of B&R nor the names of its
-- contributors may be used to endorse or promote products derived
-- from this software without prior written permission. For written
-- permission, please contact [email protected]
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-- "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-- LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-- FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-- COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-- BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-- LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
-- LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
-- ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-- POSSIBILITY OF SUCH DAMAGE.
--
-- Note: RxDv and RxDat have to be synchron to Clk
-- The following Conditions are checked:
-- RxDV >163.64µsec HIGH -> invalid
-- RxDV <0.64µsec LOW -> invalid
-- RxDV 4x <5.12µsec HIGH -> invalid
-- RxDV >5.12µsec HIGH -> valid
-- RxErr HIGH -> invalid
-- if invalid deactivation of port, until RxDv and RxErr > 10.24µsec low
--
------------------------------------------------------------------------------------------------------------------------
-- Version History
------------------------------------------------------------------------------------------------------------------------
-- 2009-08-07 V0.01 Converted from V1.1 to first official version.
-- 2011-07-23 V0.10 zelenkaj Consideration of RX Error signal and jitter (converted from V2.3)
-- 2011-08-03 V0.11 zelenkaj translated comments
-- 2011-11-18 V0.12 zelenkaj bypass filter by generic
-- 2011-11-28 V0.13 zelenkaj Changed reset level to high-active
-- 2012-04-19 V0.20 zelenkaj Redesign with fsm, Preamble-check improvement
-- 2012-05-21 V0.21 muelhausens changed timeout of fs_FRMnopre to 660ns
------------------------------------------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
ENTITY openFILTER is
Generic (
bypassFilter : boolean := false
);
Port ( Rst : in std_logic;
Clk : in std_logic;
nCheckShortFrames : in std_logic := '0'; -- Rx Port von Hub;
RxDvIn : in std_logic;
RxDatIn : in std_logic_vector(1 downto 0);
RxDvOut : out std_logic;
RxDatOut : out std_logic_vector(1 downto 0);
TxEnIn : in std_logic;
TxDatIn : in std_logic_vector(1 downto 0);
TxEnOut : out std_logic;
TxDatOut : out std_logic_vector(1 downto 0);
RxErr : in std_logic := '0'
);
END ENTITY openFILTER;
ARCHITECTURE rtl OF openFILTER IS
type aRxSet is record
RxDv : std_logic;
RxDat: std_logic_vector(1 downto 0);
end record;
type aRxSetArr is array (3 downto 0) of aRxSet;
type aFiltState is (fs_init, fs_GAP2short, fs_GAPext, fs_GAPok, fs_FRMnopre,
fs_FRMpre2short, fs_FRMpreOk, fs_FRM2short, fs_FRMok, fs_FRM2long, fs_BlockAll);
signal FiltState : aFiltState;
signal RxDel : aRxSetArr;
signal FrameShift : std_logic;
signal LastFrameNOK : std_logic;
signal StCnt : std_logic_vector(13 downto 0);
signal BlockRxPort : std_logic;
BEGIN
disFilter : if bypassFilter generate
begin
RxDvOut <= RxDvIn;
RxDatOut <= RxDatIn;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
end generate;
enFilter : if not bypassFilter generate
begin
-- IN --
RxDel(0).RxDv <= RxDvIn;
RxDel(0).RxDat <= RxDatIn;
BlockRxPort <= '1' when FiltState = fs_FRMnopre or FiltState = fs_BlockAll or LastFrameNOK = '1' else '0';
-- OUTPUT MUX --
RxDvOut <= '0' when BlockRxPort = '1' else
RxDel(3).RxDv when FrameShift = '1' else
RxDel(1).RxDv;
RxDatOut <= "00" when BlockRxPort = '1' else
RxDel(3).RxDat when FrameShift = '1' else
RxDel(1).RxDat;
TxEnOut <= TxEnIn;
TxDatOut <= TxDatIn;
fsm: PROCESS(Rst, Clk)
VARIABLE RstStCnt : std_logic;
begin
if Rst = '1' then
StCnt <= (others => '0');
FiltState <= fs_init;
FrameShift <= '0';
RxDel(3 downto 1) <= (others => ('0',"00"));
LastFrameNOK <= '0';
elsif rising_edge(Clk) then
RxDel(3 downto 1) <= RxDel(2 downto 0);
-- DEFAULT --
RstStCnt := '0';
case FiltState is
-------------------------------- INIT ---------------------------------------
when fs_init =>
FiltState <= fs_GAP2short; RstStCnt := '1';
-------------------------------- GAP 2 SHORT --------------------------------
when fs_GAP2short =>
FrameShift <= '0';
IF StCnt(4) = '1' then FiltState <= fs_GAPext; END IF; -- 360ns
IF RxDel(0).RxDv = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- Gap < 360 ns -> too short -> Block Filter
-------------------------------- GAP EXTEND ---------------------------------
when fs_GAPext =>
IF StCnt(5 downto 0) = "101110" then FiltState <= fs_GAPok; END IF;
IF RxDel(0).RxDv = '1' then -- GAP [360ns .. 960ns] -> short, but ok -> Start Frame
RstStCnt := '1';
FrameShift <= '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- GAP OK -------------------------------------
when fs_GAPok =>
IF RxDel(0).RxDv = '1' then
RstStCnt := '1';
IF RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; -- GAP > 960ns -> OK -> Start Frame (preamble already beginning)
ELSE FiltState <= fs_FRMnopre; -- GAP > 960ns -> OK -> Start Frame and wait of preamble
END IF;
END IF;
-------------------------------- FRAME, BUT STILL NO PREAMBLE ---------------
when fs_FRMnopre =>
IF StCnt(5) = '1' or -- no preamble for >=660 ns -> Block Filter
RxDel(0).RxDat = "11" or RxDel(0).RxDat = "10" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
elsif RxDel(0).RxDat = "01" then FiltState <= fs_FRMpre2short; RstStCnt := '1'; -- preamble starts -> Check Preamble
END IF;
-------------------------------- FRAME CHECK PREAMBLE TOO SHORT --------------
when fs_FRMpre2short =>
IF RxDel(0).RxDat /= "01" or -- preamble wrong -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1';
ELSIF StCnt(3) = '1' then FiltState <= fs_FRMpreOk; END IF; -- preamble ok for 180 ns -> Preamble OK
-------------------------------- FRAME CHECK PREAMBLE OK ---------------
when fs_FRMpreOk =>
IF RxDel(0).RxDat /= "01" then FiltState <= fs_FRMok; END IF; -- preamble done -> Start Frame
IF (StCnt(5) = '1' and StCnt(2) = '1') or -- preamble to long for 740 ns -> Block Filter
(RxDel(0).RxDv = '0' and RxDel(1).RxDv = '0')
then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF;
LastFrameNOK <= '0'; -- preamble is OK
-------------------------------- FRAME OK -----------------------------------
when fs_FRMok =>
IF StCnt(13) = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- FRAME > 163,842 us -> too long -> Block Filter
IF RxDel(0).RxDv = '0' and
RxDel(1).RxDv = '0' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- FRAME [163,842 us] -> OK -> Start GAP
-------------------------------- Block Filter -------------------------------
when fs_BlockAll =>
IF StCnt(2) = '1' then FiltState <= fs_GAP2short; RstStCnt := '1'; END IF; -- Block for 100 nsec
IF RxDel(0).RxDv = '1' then RstStCnt := '1'; END IF; -- RxDv != '0' -> Reset Wait Period
LastFrameNOK <= '1'; -- block next rx frame (until receive a valid preamble)
when others =>
FiltState <= fs_init;
end case;
IF RxErr = '1' then FiltState <= fs_BlockAll; RstStCnt := '1'; END IF; -- RxErr -> Block Filter
-- State Counter --
StCnt <= StCnt + 1;
if RstStCnt = '1' then StCnt <= (others => '0'); end if;
end if;
end process;
end generate;
END rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2569.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p16n02i02569ent IS
END c07s05b00x00p16n02i02569ent;
ARCHITECTURE c07s05b00x00p16n02i02569arch OF c07s05b00x00p16n02i02569ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2E6 = (2E3*1E3))
report "***PASSED TEST: c07s05b00x00p16n02i02569"
severity NOTE;
assert ( 2E6 = (2E3*1E3) )
report "***FAILED TEST: c07s05b00x00p16n02i02569 - The values of the operands and the result lie within the range of the integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p16n02i02569arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2569.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p16n02i02569ent IS
END c07s05b00x00p16n02i02569ent;
ARCHITECTURE c07s05b00x00p16n02i02569arch OF c07s05b00x00p16n02i02569ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2E6 = (2E3*1E3))
report "***PASSED TEST: c07s05b00x00p16n02i02569"
severity NOTE;
assert ( 2E6 = (2E3*1E3) )
report "***FAILED TEST: c07s05b00x00p16n02i02569 - The values of the operands and the result lie within the range of the integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p16n02i02569arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2569.vhd,v 1.2 2001-10-26 16:29:48 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c07s05b00x00p16n02i02569ent IS
END c07s05b00x00p16n02i02569ent;
ARCHITECTURE c07s05b00x00p16n02i02569arch OF c07s05b00x00p16n02i02569ent IS
BEGIN
TESTING: PROCESS
BEGIN
assert NOT(2E6 = (2E3*1E3))
report "***PASSED TEST: c07s05b00x00p16n02i02569"
severity NOTE;
assert ( 2E6 = (2E3*1E3) )
report "***FAILED TEST: c07s05b00x00p16n02i02569 - The values of the operands and the result lie within the range of the integer type."
severity ERROR;
wait;
END PROCESS TESTING;
END c07s05b00x00p16n02i02569arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc465.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00465ent IS
END c03s02b01x01p19n01i00465ent;
ARCHITECTURE c03s02b01x01p19n01i00465arch OF c03s02b01x01p19n01i00465ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
constant C66: severity_level_vector_range := (others => note);
function complex_scalar(s : severity_level_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return severity_level_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : severity_level_vector_range;
signal S2 : severity_level_vector_range;
signal S3 : severity_level_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00465"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00465 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00465arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc465.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00465ent IS
END c03s02b01x01p19n01i00465ent;
ARCHITECTURE c03s02b01x01p19n01i00465arch OF c03s02b01x01p19n01i00465ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
constant C66: severity_level_vector_range := (others => note);
function complex_scalar(s : severity_level_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return severity_level_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : severity_level_vector_range;
signal S2 : severity_level_vector_range;
signal S3 : severity_level_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00465"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00465 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00465arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc465.vhd,v 1.2 2001-10-26 16:29:54 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY model IS
PORT
(
F1: OUT integer := 3;
F2: INOUT integer := 3;
F3: IN integer
);
END model;
architecture model of model is
begin
process
begin
wait for 1 ns;
assert F3= 3
report"wrong initialization of F3 through type conversion" severity failure;
assert F2 = 3
report"wrong initialization of F2 through type conversion" severity failure;
wait;
end process;
end;
ENTITY c03s02b01x01p19n01i00465ent IS
END c03s02b01x01p19n01i00465ent;
ARCHITECTURE c03s02b01x01p19n01i00465arch OF c03s02b01x01p19n01i00465ent IS
constant low_number : integer := 0;
constant hi_number : integer := 7;
subtype hi_to_low_range is integer range low_number to hi_number;
type severity_level_vector is array (natural range <>) of severity_level;
subtype severity_level_vector_range is severity_level_vector(hi_to_low_range);
constant C66: severity_level_vector_range := (others => note);
function complex_scalar(s : severity_level_vector_range) return integer is
begin
return 3;
end complex_scalar;
function scalar_complex(s : integer) return severity_level_vector_range is
begin
return C66;
end scalar_complex;
component model1
PORT
(
F1: OUT integer;
F2: INOUT integer;
F3: IN integer
);
end component;
for T1 : model1 use entity work.model(model);
signal S1 : severity_level_vector_range;
signal S2 : severity_level_vector_range;
signal S3 : severity_level_vector_range:= C66;
BEGIN
T1: model1
port map (
scalar_complex(F1) => S1,
scalar_complex(F2) => complex_scalar(S2),
F3 => complex_scalar(S3)
);
TESTING: PROCESS
BEGIN
wait for 1 ns;
assert NOT((S1 = C66) and (S2 = C66))
report "***PASSED TEST: c03s02b01x01p19n01i00465"
severity NOTE;
assert ((S1 = C66) and (S2 = C66))
report "***FAILED TEST: c03s02b01x01p19n01i00465 - For an interface object of mode out, buffer, inout, or linkage, if the formal part includes a type conversion function, then the parameter subtype of that function must be a constrained array subtype."
severity ERROR;
wait;
END PROCESS TESTING;
END c03s02b01x01p19n01i00465arch;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d4_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d4_A_shiftReg;
architecture rtl of fifo_w16_d4_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d4_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d4_A is
component fifo_w16_d4_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d4_A_shiftReg : fifo_w16_d4_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2017.4
-- Copyright (C) 1986-2017 Xilinx, Inc. All Rights Reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
entity fifo_w16_d4_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end fifo_w16_d4_A_shiftReg;
architecture rtl of fifo_w16_d4_A_shiftReg is
--constant DEPTH_WIDTH: integer := 16;
type SRL_ARRAY is array (0 to DEPTH-1) of std_logic_vector(DATA_WIDTH-1 downto 0);
signal SRL_SIG : SRL_ARRAY;
begin
p_shift: process (clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
SRL_SIG <= data & SRL_SIG(0 to DEPTH-2);
end if;
end if;
end process;
q <= SRL_SIG(conv_integer(a));
end rtl;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity fifo_w16_d4_A is
generic (
MEM_STYLE : string := "shiftreg";
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
if_empty_n : OUT STD_LOGIC;
if_read_ce : IN STD_LOGIC;
if_read : IN STD_LOGIC;
if_dout : OUT STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
if_full_n : OUT STD_LOGIC;
if_write_ce : IN STD_LOGIC;
if_write : IN STD_LOGIC;
if_din : IN STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0));
end entity;
architecture rtl of fifo_w16_d4_A is
component fifo_w16_d4_A_shiftReg is
generic (
DATA_WIDTH : integer := 16;
ADDR_WIDTH : integer := 3;
DEPTH : integer := 5);
port (
clk : in std_logic;
data : in std_logic_vector(DATA_WIDTH-1 downto 0);
ce : in std_logic;
a : in std_logic_vector(ADDR_WIDTH-1 downto 0);
q : out std_logic_vector(DATA_WIDTH-1 downto 0));
end component;
signal shiftReg_addr : STD_LOGIC_VECTOR(ADDR_WIDTH - 1 downto 0);
signal shiftReg_data, shiftReg_q : STD_LOGIC_VECTOR(DATA_WIDTH - 1 downto 0);
signal shiftReg_ce : STD_LOGIC;
signal mOutPtr : STD_LOGIC_VECTOR(ADDR_WIDTH downto 0) := (others => '1');
signal internal_empty_n : STD_LOGIC := '0';
signal internal_full_n : STD_LOGIC := '1';
begin
if_empty_n <= internal_empty_n;
if_full_n <= internal_full_n;
shiftReg_data <= if_din;
if_dout <= shiftReg_q;
process (clk)
begin
if clk'event and clk = '1' then
if reset = '1' then
mOutPtr <= (others => '1');
internal_empty_n <= '0';
internal_full_n <= '1';
else
if ((if_read and if_read_ce) = '1' and internal_empty_n = '1') and
((if_write and if_write_ce) = '0' or internal_full_n = '0') then
mOutPtr <= mOutPtr - 1;
if (mOutPtr = 0) then
internal_empty_n <= '0';
end if;
internal_full_n <= '1';
elsif ((if_read and if_read_ce) = '0' or internal_empty_n = '0') and
((if_write and if_write_ce) = '1' and internal_full_n = '1') then
mOutPtr <= mOutPtr + 1;
internal_empty_n <= '1';
if (mOutPtr = DEPTH - 2) then
internal_full_n <= '0';
end if;
end if;
end if;
end if;
end process;
shiftReg_addr <= (others => '0') when mOutPtr(ADDR_WIDTH) = '1' else mOutPtr(ADDR_WIDTH-1 downto 0);
shiftReg_ce <= (if_write and if_write_ce) and internal_full_n;
U_fifo_w16_d4_A_shiftReg : fifo_w16_d4_A_shiftReg
generic map (
DATA_WIDTH => DATA_WIDTH,
ADDR_WIDTH => ADDR_WIDTH,
DEPTH => DEPTH)
port map (
clk => clk,
data => shiftReg_data,
ce => shiftReg_ce,
a => shiftReg_addr,
q => shiftReg_q);
end rtl;
|
-- THIS FILE CONTAINS A FIX MADE ON 9/19/2005.
-- Idecode module (implements the register file for
LIBRARY IEEE; -- the MIPS computer)
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY Idecode IS
PORT( read_data_1 : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2_ex : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data_2_mem : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Instruction : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_data : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_result : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
RegWrite : IN STD_LOGIC;
MemtoReg : IN STD_LOGIC;
RegDst : IN STD_LOGIC;
RegWrite_mem : IN STD_LOGIC;
RegWrite_ex : IN STD_LOGIC;
Sign_extend : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result_mem : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result_wb : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
ALU_Result_ex : IN STD_LOGIC_VECTOR( 31 DOWNTO 0 );
read_register_1_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
read_register_2_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
D_read_register_1_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
D_read_register_2_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
D_write_register_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
DD_write_register_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_register_address_out : OUT STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_register_address_ex : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_register_address_mem : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_register_address_wb : IN STD_LOGIC_VECTOR( 4 DOWNTO 0 );
write_data_out : OUT STD_LOGIC_VECTOR( 31 DOWNTO 0 );
Zero : OUT STD_LOGIC;
Add_Result : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
PC_plus_4 : IN STD_LOGIC_VECTOR( 9 DOWNTO 0 );
clock,reset : IN STD_LOGIC );
END Idecode;
ARCHITECTURE behavior OF Idecode IS
TYPE register_file IS ARRAY ( 0 TO 31 ) OF STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL clkbar : STD_LOGIC;
SIGNAL register_array : register_file;
SIGNAL write_register_address : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_data : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL read_register_1_address : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL read_register_2_address : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_register_address_1 : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL write_register_address_0 : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL Instruction_immediate_value : STD_LOGIC_VECTOR( 15 DOWNTO 0 );
SIGNAL D_read_data_1 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL D_read_data_2, DD_read_data_2 : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL Forward_A, Forward_B : STD_LOGIC_VECTOR( 1 DOWNTO 0 );
SIGNAL ALUResult, D_ALU_Result, DD_ALU_Result, DDD_ALU_Result : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL D_Sign_extend : STD_LOGIC_VECTOR( 31 DOWNTO 0 );
SIGNAL D_write_register_address, DD_write_register_address,
DDD_write_register_address : STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL D_read_register_1_address, D_read_register_2_address :
STD_LOGIC_VECTOR( 4 DOWNTO 0 );
SIGNAL D_Add_Result : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL Branch_Add : STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL D_Zero : STD_LOGIC;
BEGIN
clkbar <= NOT clock;
read_register_1_address_out <= read_register_1_address;
read_register_2_address_out <= read_register_2_address;
D_read_register_1_address_out <= D_read_register_1_address;
D_read_register_2_address_out <= D_read_register_2_address;
D_write_register_address_out <= D_write_register_address;
DD_write_register_address_out <= DD_write_register_address;
write_register_address_out <= write_register_address;
write_data_out <= write_data;
D_read_register_1_address <= Instruction( 25 DOWNTO 21 );
D_read_register_2_address <= Instruction( 20 DOWNTO 16 );
write_register_address_1 <= Instruction( 15 DOWNTO 11 );
write_register_address_0 <= Instruction( 20 DOWNTO 16 );
Instruction_immediate_value <= Instruction( 15 DOWNTO 0 );
PROCESS (RegWrite, RegWrite_mem, write_register_address_mem, write_register_address_wb,
read_register_1_address, read_register_2_address)
BEGIN
IF RegWrite_ex = '1' AND write_register_address_ex /= "00000"
AND write_register_address_ex = D_read_register_1_address THEN
Forward_A <= "11";
ELSIF RegWrite_mem = '1' AND write_register_address_mem /= "00000"
AND write_register_address_mem = D_read_register_1_address THEN
Forward_A <= "10";
ELSIF RegWrite = '1' AND write_register_address_wb /= "00000"
AND write_register_address_wb = D_read_register_1_address THEN
Forward_A <= "01";
ELSE Forward_A <= "00";
END IF;
IF RegWrite_ex = '1' AND write_register_address_ex /= "00000"
AND write_register_address_ex = D_read_register_2_address THEN
Forward_B <= "11";
ELSIF RegWrite_mem = '1' AND write_register_address_mem /= "00000"
AND write_register_address_mem = D_read_register_2_address THEN
Forward_B <= "10";
ELSIF RegWrite = '1' AND write_register_address_wb /= "00000"
AND write_register_address_wb = D_read_register_2_address THEN
Forward_B <= "01";
ELSE Forward_B <= "00";
END IF;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL clock = '0';
DDD_ALU_Result <= ALU_Result_ex;
DD_ALU_Result <= ALU_Result_mem;
D_ALU_Result <= ALU_Result_wb;
END PROCESS;
-- Read Register 1 Operation
D_read_data_1 <= register_array( CONV_INTEGER( D_read_register_1_address ) ) WHEN Forward_A = "00" ELSE
DD_ALU_Result WHEN Forward_A = "10" ELSE
D_ALU_Result WHEN Forward_A = "01" ELSE
ALU_Result_ex;
-- Read Register 2 Operation
DD_read_data_2 <= register_array( CONV_INTEGER( D_read_register_2_address ) ) WHEN Forward_B = "00" ELSE
DD_ALU_Result WHEN Forward_B = "10" ELSE
D_ALU_Result WHEN Forward_B = "01" ELSE
ALU_Result_ex;
-- Mux for Register Write Address
-- ALU input mux
DDD_write_register_address <= write_register_address_1
WHEN RegDst = '1' ELSE write_register_address_0;
-- Mux to bypass data memory for Rformat instructions
write_data <= ALU_result_wb( 31 DOWNTO 0 )
WHEN ( MemtoReg = '0' ) ELSE read_data;
-- Sign Extend 16-bits to 32-bits
D_Sign_extend <= X"0000" & Instruction_immediate_value
WHEN Instruction_immediate_value(15) = '0'
ELSE X"FFFF" & Instruction_immediate_value;
Zero <= '1'
WHEN ( D_read_data_1 = DD_read_data_2 )
ELSE '0';
Branch_Add <= PC_plus_4( 9 DOWNTO 2 ) + Instruction_immediate_value(7 DOWNTO 0) ;
Add_result <= Branch_Add( 7 DOWNTO 0 );
PROCESS
BEGIN
WAIT UNTIL clock'EVENT AND clock = '1';
read_data_1 <= D_read_data_1;
read_data_2_ex <= DD_read_data_2;
D_read_data_2 <= DD_read_data_2;
read_data_2_mem <= D_read_data_2;
Sign_extend <= D_sign_extend;
write_register_address <= D_write_register_address;
D_write_register_address <= DD_write_register_address;
DD_write_register_address <= DDD_write_register_address;
read_register_1_address <= D_read_register_1_address;
read_register_2_address <= D_read_register_2_address;
--DD_ALU_Result <= ALU_Result_mem;
--D_ALU_Result <= ALU_Result_wb;
END PROCESS;
PROCESS
BEGIN
WAIT UNTIL clkbar'EVENT AND clkbar = '1';
IF reset = '1' THEN
-- Initial register values on reset are register = reg#
-- use loop to automatically generate reset logic
-- for all registers
FOR i IN 0 TO 31 LOOP
register_array(i) <= CONV_STD_LOGIC_VECTOR( i, 32 );
END LOOP;
-- Write back to register - don't write to register 0
ELSIF RegWrite = '1' AND write_register_address /= 0 THEN
register_array( CONV_INTEGER( write_register_address)) <= write_data;
END IF;
END PROCESS;
END behavior;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity SR_flipflop is
port ( s_n, r_n : in bit; q, q_n : inout bit );
begin
postponed process (q, q_n) is
begin
assert now = 0 fs or q = not q_n
report "implementation error: q /= not q_n";
end postponed process;
end entity SR_flipflop;
--------------------------------------------------
architecture dataflow of SR_flipflop is
begin
gate_1 : q <= s_n nand q_n;
gate_2 : q_n <= r_n nand q;
end architecture dataflow;
|
-------------------------------------------------------------------------------
--
-- File: dvi2rgb.vhd
-- Author: Elod Gyorgy
-- Original Project: HDMI input on 7-series Xilinx FPGA
-- Date: 24 July 2015
--
-------------------------------------------------------------------------------
-- (c) 2015 Copyright Digilent Incorporated
-- All Rights Reserved
--
-- This program is free software; distributed under the terms of BSD 3-clause
-- license ("Revised BSD License", "New BSD License", or "Modified BSD License")
--
-- Redistribution and use in source and binary forms, with or without modification,
-- are permitted provided that the following conditions are met:
--
-- 1. Redistributions of source code must retain the above copyright notice, this
-- list of conditions and the following disclaimer.
-- 2. Redistributions in binary form must reproduce the above copyright notice,
-- this list of conditions and the following disclaimer in the documentation
-- and/or other materials provided with the distribution.
-- 3. Neither the name(s) of the above-listed copyright holder(s) nor the names
-- of its contributors may be used to endorse or promote products derived
-- from this software without specific prior written permission.
--
-- THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-- AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-- IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-- ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
-- FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-- DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-- SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-- CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-- OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-- OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
--
-------------------------------------------------------------------------------
--
-- Purpose:
-- This module connects to a top level DVI 1.0 sink interface comprised of three
-- TMDS data channels and one TMDS clock channel. It includes the necessary
-- clock infrastructure, deserialization, phase alignment, channel deskew and
-- decode logic. It outputs 24-bit RGB video data along with pixel clock and
-- synchronization signals.
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use work.DVI_Constants.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity dvi2rgb is
Generic (
kEmulateDDC : boolean := true; --will emulate a DDC EEPROM with basic EDID, if set to yes
kRstActiveHigh : boolean := true; --true, if active-high; false, if active-low
kAddBUFG : boolean := true; --true, if PixelClk should be re-buffered with BUFG
kClkRange : natural := 1; -- MULT_F = kClkRange*5 (choose >=120MHz=1, >=60MHz=2, >=40MHz=3)
-- 7-series specific
kIDLY_TapValuePs : natural := 78; --delay in ps per tap
kIDLY_TapWidth : natural := 5); --number of bits for IDELAYE2 tap counter
Port (
-- DVI 1.0 TMDS video interface
TMDS_Clk_p : in std_logic;
TMDS_Clk_n : in std_logic;
TMDS_Data_p : in std_logic_vector(2 downto 0);
TMDS_Data_n : in std_logic_vector(2 downto 0);
-- Auxiliary signals
RefClk : in std_logic; --200 MHz reference clock for IDELAYCTRL, reset, lock monitoring etc.
aRst : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
aRst_n : in std_logic; --asynchronous reset; must be reset when RefClk is not within spec
-- Video out
vid_pData : out std_logic_vector(23 downto 0);
vid_pVDE : out std_logic;
vid_pHSync : out std_logic;
vid_pVSync : out std_logic;
PixelClk : out std_logic; --pixel-clock recovered from the DVI interface
SerialClk : out std_logic; -- advanced use only; 5x PixelClk
aPixelClkLckd : out std_logic; -- advanced use only; PixelClk and SerialClk stable
-- Optional DDC port
DDC_SDA_I : in std_logic;
DDC_SDA_O : out std_logic;
DDC_SDA_T : out std_logic;
DDC_SCL_I : in std_logic;
DDC_SCL_O : out std_logic;
DDC_SCL_T : out std_logic;
pRst : in std_logic; -- synchronous reset; will restart locking procedure
pRst_n : in std_logic -- synchronous reset; will restart locking procedure
);
end dvi2rgb;
architecture Behavioral of dvi2rgb is
type dataIn_t is array (2 downto 0) of std_logic_vector(7 downto 0);
type eyeSize_t is array (2 downto 0) of std_logic_vector(kIDLY_TapWidth-1 downto 0);
signal aLocked, SerialClk_int, PixelClk_int, pLockLostRst: std_logic;
signal pRdy, pVld, pDE, pAlignErr, pC0, pC1 : std_logic_vector(2 downto 0);
signal pDataIn : dataIn_t;
signal pEyeSize : eyeSize_t;
signal aRst_int, pRst_int : std_logic;
signal pData : std_logic_vector(23 downto 0);
signal pVDE, pHSync, pVSync : std_logic;
begin
ResetActiveLow: if not kRstActiveHigh generate
aRst_int <= not aRst_n;
pRst_int <= not pRst_n;
end generate ResetActiveLow;
ResetActiveHigh: if kRstActiveHigh generate
aRst_int <= aRst;
pRst_int <= pRst;
end generate ResetActiveHigh;
-- Clocking infrastructure to obtain a usable fast serial clock and a slow parallel clock
TMDS_ClockingX: entity work.TMDS_Clocking
generic map (
kClkRange => kClkRange)
port map (
aRst => aRst_int,
RefClk => RefClk,
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
aLocked => aLocked,
PixelClk => PixelClk_int, -- slow parallel clock
SerialClk => SerialClk_int -- fast serial clock
);
-- We need a reset bridge to use the asynchronous aLocked signal to reset our circuitry
-- and decrease the chance of metastability. The signal pLockLostRst can be used as
-- asynchronous reset for any flip-flop in the PixelClk domain, since it will be de-asserted
-- synchronously.
LockLostReset: entity work.ResetBridge
generic map (
kPolarity => '1')
port map (
aRst => not aLocked,
OutClk => PixelClk_int,
oRst => pLockLostRst);
-- Three data channel decoders
DataDecoders: for iCh in 2 downto 0 generate
DecoderX: entity work.TMDS_Decoder
generic map (
kCtlTknCount => kMinTknCntForBlank, --how many subsequent control tokens make a valid blank detection (DVI spec)
kTimeoutMs => kBlankTimeoutMs, --what is the maximum time interval for a blank to be detected (DVI spec)
kRefClkFrqMHz => 200, --what is the RefClk frequency
kIDLY_TapValuePs => kIDLY_TapValuePs, --delay in ps per tap
kIDLY_TapWidth => kIDLY_TapWidth) --number of bits for IDELAYE2 tap counter
port map (
aRst => pLockLostRst,
PixelClk => PixelClk_int,
SerialClk => SerialClk_int,
RefClk => RefClk,
pRst => pRst_int,
sDataIn_p => TMDS_Data_p(iCh),
sDataIn_n => TMDS_Data_n(iCh),
pOtherChRdy(1 downto 0) => pRdy((iCh+1) mod 3) & pRdy((iCh+2) mod 3), -- tie channels together for channel de-skew
pOtherChVld(1 downto 0) => pVld((iCh+1) mod 3) & pVld((iCh+2) mod 3), -- tie channels together for channel de-skew
pAlignErr => pAlignErr(iCh),
pC0 => pC0(iCh),
pC1 => pC1(iCh),
pMeRdy => pRdy(iCh),
pMeVld => pVld(iCh),
pVde => pDE(iCh),
pDataIn(7 downto 0) => pDataIn(iCh),
pEyeSize => pEyeSize(iCh)
);
end generate DataDecoders;
-- RGB Output conform DVI 1.0
-- except that it sends blank pixel during blanking
-- for some reason video_data uses RBG packing
pData(23 downto 16) <= pDataIn(2); -- red is channel 2
pData(7 downto 0) <= pDataIn(1); -- green is channel 1
pData(15 downto 8) <= pDataIn(0); -- blue is channel 0
pHSync <= pC0(0); -- channel 0 carries control signals too
pVSync <= pC1(0); -- channel 0 carries control signals too
pVDE <= pDE(0); -- since channels are aligned, all of them are either active or blanking at once
-- Clock outputs
SerialClk <= SerialClk_int; -- fast 5x pixel clock for advanced use only
aPixelClkLckd <= aLocked;
----------------------------------------------------------------------------------
-- Re-buffer PixelClk with a BUFG so that it can reach the whole device, unlike
-- through a BUFR. Since BUFG introduces a delay on the clock path, pixel data is
-- re-registered here.
----------------------------------------------------------------------------------
GenerateBUFG: if kAddBUFG generate
ResyncToBUFG_X: entity work.ResyncToBUFG
port map (
-- Video in
piData => pData,
piVDE => pVDE,
piHSync => pHSync,
piVSync => pVSync,
PixelClkIn => PixelClk_int,
-- Video out
poData => vid_pData,
poVDE => vid_pVDE,
poHSync => vid_pHSync,
poVSync => vid_pVSync,
PixelClkOut => PixelClk
);
end generate GenerateBUFG;
DontGenerateBUFG: if not kAddBUFG generate
vid_pData <= pData;
vid_pVDE <= pVDE;
vid_pHSync <= pHSync;
vid_pVSync <= pVSync;
PixelClk <= PixelClk_int;
end generate DontGenerateBUFG;
----------------------------------------------------------------------------------
-- Optional DDC EEPROM Display Data Channel - Bi-directional (DDC2B)
-- The EDID will be loaded from the file specified below in kInitFileName.
----------------------------------------------------------------------------------
GenerateDDC: if kEmulateDDC generate
DDC_EEPROM: entity work.EEPROM_8b
generic map (
kSampleClkFreqInMHz => 200,
kSlaveAddress => "1010000",
kAddrBits => 7, -- 128 byte EDID 1.x data
kWritable => false,
kInitFileName => "dgl_dvi_edid.txt") -- name of file containing init values
port map(
SampleClk => RefClk,
sRst => '0',
aSDA_I => DDC_SDA_I,
aSDA_O => DDC_SDA_O,
aSDA_T => DDC_SDA_T,
aSCL_I => DDC_SCL_I,
aSCL_O => DDC_SCL_O,
aSCL_T => DDC_SCL_T);
end generate GenerateDDC;
end Behavioral;
|
-- Copyright 1986-2016 Xilinx, Inc. All Rights Reserved.
-- --------------------------------------------------------------------------------
-- Tool Version: Vivado v.2016.4 (win64) Build 1756540 Mon Jan 23 19:11:23 MST 2017
-- Date : Fri Apr 14 18:39:27 2017
-- Host : LAPTOP-IQ9G3D1I running 64-bit major release (build 9200)
-- Command : write_vhdl -force -mode funcsim -rename_top bd_auto_cc_0 -prefix
-- bd_auto_cc_0_ bd_auto_cc_0_sim_netlist.vhdl
-- Design : bd_auto_cc_0
-- Purpose : This VHDL netlist is a functional simulation representation of the design and should not be modified or
-- synthesized. This netlist cannot be used for SDF annotated simulation.
-- Device : xc7a100tcsg324-1
-- --------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_dmem is
port (
dout_i : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
end bd_auto_cc_0_dmem;
architecture STRUCTURE of bd_auto_cc_0_dmem is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_64 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(1 downto 0),
DIB(1 downto 0) => DI(3 downto 2),
DIC(1 downto 0) => DI(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(13 downto 12),
DIB(1 downto 0) => DI(15 downto 14),
DIC(1 downto 0) => DI(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(19 downto 18),
DIB(1 downto 0) => DI(21 downto 20),
DIC(1 downto 0) => DI(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(25 downto 24),
DIB(1 downto 0) => DI(27 downto 26),
DIC(1 downto 0) => DI(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(31 downto 30),
DIB(1 downto 0) => DI(33 downto 32),
DIC(1 downto 0) => DI(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(37 downto 36),
DIB(1 downto 0) => DI(39 downto 38),
DIC(1 downto 0) => DI(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(43 downto 42),
DIB(1 downto 0) => DI(45 downto 44),
DIC(1 downto 0) => DI(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(49 downto 48),
DIB(1 downto 0) => DI(51 downto 50),
DIC(1 downto 0) => DI(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(55 downto 54),
DIB(1 downto 0) => DI(57 downto 56),
DIC(1 downto 0) => DI(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_60_64: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(61 downto 60),
DIB(1 downto 0) => DI(63 downto 62),
DIC(1) => '0',
DIC(0) => DI(64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_64_n_0,
DOA(0) => RAM_reg_0_15_60_64_n_1,
DOB(1) => RAM_reg_0_15_60_64_n_2,
DOB(0) => RAM_reg_0_15_60_64_n_3,
DOC(1) => NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED(1),
DOC(0) => RAM_reg_0_15_60_64_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => DI(7 downto 6),
DIB(1 downto 0) => DI(9 downto 8),
DIC(1 downto 0) => DI(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => ram_full_fb_i_reg(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => dout_i(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => dout_i(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => dout_i(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => dout_i(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => dout_i(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => dout_i(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => dout_i(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => dout_i(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => dout_i(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => dout_i(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => dout_i(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => dout_i(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => dout_i(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => dout_i(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => dout_i(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => dout_i(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => dout_i(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => dout_i(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => dout_i(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => dout_i(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => dout_i(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => dout_i(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => dout_i(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => dout_i(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => dout_i(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => dout_i(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => dout_i(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => dout_i(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => dout_i(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => dout_i(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => dout_i(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => dout_i(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => dout_i(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => dout_i(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => dout_i(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => dout_i(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => dout_i(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => dout_i(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => dout_i(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => dout_i(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => dout_i(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => dout_i(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => dout_i(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => dout_i(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => dout_i(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => dout_i(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => dout_i(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => dout_i(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => dout_i(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => dout_i(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => dout_i(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => dout_i(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => dout_i(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => dout_i(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => dout_i(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => dout_i(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_1,
Q => dout_i(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_0,
Q => dout_i(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_3,
Q => dout_i(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_2,
Q => dout_i(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_5,
Q => dout_i(64),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => dout_i(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => dout_i(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => dout_i(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => dout_i(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_dmem_81 is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_dmem_81 : entity is "dmem";
end bd_auto_cc_0_dmem_81;
architecture STRUCTURE of bd_auto_cc_0_dmem_81 is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_2 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_3 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_4 : STD_LOGIC;
signal RAM_reg_0_15_36_41_n_5 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_0 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_1 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_2 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_3 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_4 : STD_LOGIC;
signal RAM_reg_0_15_42_47_n_5 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_0 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_1 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_2 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_3 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_4 : STD_LOGIC;
signal RAM_reg_0_15_48_53_n_5 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_0 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_1 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_2 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_3 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_4 : STD_LOGIC;
signal RAM_reg_0_15_54_59_n_5 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_0 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_1 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_2 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_3 : STD_LOGIC;
signal RAM_reg_0_15_60_64_n_5 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_41 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_42_47 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_48_53 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_54_59 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_60_64 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(1 downto 0),
DIB(1 downto 0) => I123(3 downto 2),
DIC(1 downto 0) => I123(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(13 downto 12),
DIB(1 downto 0) => I123(15 downto 14),
DIC(1 downto 0) => I123(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(19 downto 18),
DIB(1 downto 0) => I123(21 downto 20),
DIC(1 downto 0) => I123(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(25 downto 24),
DIB(1 downto 0) => I123(27 downto 26),
DIC(1 downto 0) => I123(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(31 downto 30),
DIB(1 downto 0) => I123(33 downto 32),
DIC(1 downto 0) => I123(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_41: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(37 downto 36),
DIB(1 downto 0) => I123(39 downto 38),
DIC(1 downto 0) => I123(41 downto 40),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_41_n_0,
DOA(0) => RAM_reg_0_15_36_41_n_1,
DOB(1) => RAM_reg_0_15_36_41_n_2,
DOB(0) => RAM_reg_0_15_36_41_n_3,
DOC(1) => RAM_reg_0_15_36_41_n_4,
DOC(0) => RAM_reg_0_15_36_41_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_41_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_42_47: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(43 downto 42),
DIB(1 downto 0) => I123(45 downto 44),
DIC(1 downto 0) => I123(47 downto 46),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_42_47_n_0,
DOA(0) => RAM_reg_0_15_42_47_n_1,
DOB(1) => RAM_reg_0_15_42_47_n_2,
DOB(0) => RAM_reg_0_15_42_47_n_3,
DOC(1) => RAM_reg_0_15_42_47_n_4,
DOC(0) => RAM_reg_0_15_42_47_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_42_47_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_48_53: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(49 downto 48),
DIB(1 downto 0) => I123(51 downto 50),
DIC(1 downto 0) => I123(53 downto 52),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_48_53_n_0,
DOA(0) => RAM_reg_0_15_48_53_n_1,
DOB(1) => RAM_reg_0_15_48_53_n_2,
DOB(0) => RAM_reg_0_15_48_53_n_3,
DOC(1) => RAM_reg_0_15_48_53_n_4,
DOC(0) => RAM_reg_0_15_48_53_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_48_53_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_54_59: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(55 downto 54),
DIB(1 downto 0) => I123(57 downto 56),
DIC(1 downto 0) => I123(59 downto 58),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_54_59_n_0,
DOA(0) => RAM_reg_0_15_54_59_n_1,
DOB(1) => RAM_reg_0_15_54_59_n_2,
DOB(0) => RAM_reg_0_15_54_59_n_3,
DOC(1) => RAM_reg_0_15_54_59_n_4,
DOC(0) => RAM_reg_0_15_54_59_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_54_59_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_60_64: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(61 downto 60),
DIB(1 downto 0) => I123(63 downto 62),
DIC(1) => '0',
DIC(0) => I123(64),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_60_64_n_0,
DOA(0) => RAM_reg_0_15_60_64_n_1,
DOB(1) => RAM_reg_0_15_60_64_n_2,
DOB(0) => RAM_reg_0_15_60_64_n_3,
DOC(1) => NLW_RAM_reg_0_15_60_64_DOC_UNCONNECTED(1),
DOC(0) => RAM_reg_0_15_60_64_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_60_64_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I123(7 downto 6),
DIB(1 downto 0) => I123(9 downto 8),
DIC(1 downto 0) => I123(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_2,
Q => Q(39),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_5,
Q => Q(40),
R => '0'
);
\gpr1.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_41_n_4,
Q => Q(41),
R => '0'
);
\gpr1.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_1,
Q => Q(42),
R => '0'
);
\gpr1.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_0,
Q => Q(43),
R => '0'
);
\gpr1.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_3,
Q => Q(44),
R => '0'
);
\gpr1.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_2,
Q => Q(45),
R => '0'
);
\gpr1.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_5,
Q => Q(46),
R => '0'
);
\gpr1.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_42_47_n_4,
Q => Q(47),
R => '0'
);
\gpr1.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_1,
Q => Q(48),
R => '0'
);
\gpr1.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_0,
Q => Q(49),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_3,
Q => Q(50),
R => '0'
);
\gpr1.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_2,
Q => Q(51),
R => '0'
);
\gpr1.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_5,
Q => Q(52),
R => '0'
);
\gpr1.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_48_53_n_4,
Q => Q(53),
R => '0'
);
\gpr1.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_1,
Q => Q(54),
R => '0'
);
\gpr1.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_0,
Q => Q(55),
R => '0'
);
\gpr1.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_3,
Q => Q(56),
R => '0'
);
\gpr1.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_2,
Q => Q(57),
R => '0'
);
\gpr1.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_5,
Q => Q(58),
R => '0'
);
\gpr1.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_54_59_n_4,
Q => Q(59),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_1,
Q => Q(60),
R => '0'
);
\gpr1.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_0,
Q => Q(61),
R => '0'
);
\gpr1.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_3,
Q => Q(62),
R => '0'
);
\gpr1.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_2,
Q => Q(63),
R => '0'
);
\gpr1.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_60_64_n_5,
Q => Q(64),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_dmem__parameterized0\ is
port (
Q : out STD_LOGIC_VECTOR ( 36 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_dmem__parameterized0\ : entity is "dmem";
end \bd_auto_cc_0_dmem__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_dmem__parameterized0\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_36_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOA_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_36_36_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_36_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_36 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(1 downto 0),
DIB(1 downto 0) => I115(3 downto 2),
DIC(1 downto 0) => I115(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(13 downto 12),
DIB(1 downto 0) => I115(15 downto 14),
DIC(1 downto 0) => I115(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(19 downto 18),
DIB(1 downto 0) => I115(21 downto 20),
DIC(1 downto 0) => I115(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(25 downto 24),
DIB(1 downto 0) => I115(27 downto 26),
DIC(1 downto 0) => I115(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(31 downto 30),
DIB(1 downto 0) => I115(33 downto 32),
DIC(1 downto 0) => I115(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_36_36: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1) => '0',
DIA(0) => I115(36),
DIB(1 downto 0) => B"00",
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => NLW_RAM_reg_0_15_36_36_DOA_UNCONNECTED(1),
DOA(0) => RAM_reg_0_15_36_36_n_1,
DOB(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOB_UNCONNECTED(1 downto 0),
DOC(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_36_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I115(7 downto 6),
DIB(1 downto 0) => I115(9 downto 8),
DIC(1 downto 0) => I115(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => s_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_36_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_dmem__parameterized1\ is
port (
Q : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_dmem__parameterized1\ : entity is "dmem";
end \bd_auto_cc_0_dmem__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_dmem__parameterized1\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => m_axi_bresp(1 downto 0),
DIB(1 downto 0) => m_axi_bid(1 downto 0),
DIC(1 downto 0) => m_axi_bid(3 downto 2),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_dmem__parameterized2\ is
port (
Q : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_dmem__parameterized2\ : entity is "dmem";
end \bd_auto_cc_0_dmem__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_dmem__parameterized2\ is
signal RAM_reg_0_15_0_5_n_0 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_1 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_2 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_3 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_4 : STD_LOGIC;
signal RAM_reg_0_15_0_5_n_5 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_0 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_1 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_2 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_3 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_4 : STD_LOGIC;
signal RAM_reg_0_15_12_17_n_5 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_0 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_1 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_2 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_3 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_4 : STD_LOGIC;
signal RAM_reg_0_15_18_23_n_5 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_0 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_1 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_2 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_3 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_4 : STD_LOGIC;
signal RAM_reg_0_15_24_29_n_5 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_0 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_1 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_2 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_3 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_4 : STD_LOGIC;
signal RAM_reg_0_15_30_35_n_5 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_0 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_1 : STD_LOGIC;
signal RAM_reg_0_15_36_38_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_0 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_1 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_2 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_3 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_4 : STD_LOGIC;
signal RAM_reg_0_15_6_11_n_5 : STD_LOGIC;
signal NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_38_DOB_UNCONNECTED : STD_LOGIC_VECTOR ( 1 to 1 );
signal NLW_RAM_reg_0_15_36_38_DOC_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_36_38_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
signal NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute METHODOLOGY_DRC_VIOS : string;
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_0_5 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_12_17 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_18_23 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_24_29 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_30_35 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_36_38 : label is "";
attribute METHODOLOGY_DRC_VIOS of RAM_reg_0_15_6_11 : label is "";
begin
RAM_reg_0_15_0_5: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(1 downto 0),
DIB(1 downto 0) => I127(3 downto 2),
DIC(1 downto 0) => I127(5 downto 4),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_0_5_n_0,
DOA(0) => RAM_reg_0_15_0_5_n_1,
DOB(1) => RAM_reg_0_15_0_5_n_2,
DOB(0) => RAM_reg_0_15_0_5_n_3,
DOC(1) => RAM_reg_0_15_0_5_n_4,
DOC(0) => RAM_reg_0_15_0_5_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_0_5_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_12_17: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(13 downto 12),
DIB(1 downto 0) => I127(15 downto 14),
DIC(1 downto 0) => I127(17 downto 16),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_12_17_n_0,
DOA(0) => RAM_reg_0_15_12_17_n_1,
DOB(1) => RAM_reg_0_15_12_17_n_2,
DOB(0) => RAM_reg_0_15_12_17_n_3,
DOC(1) => RAM_reg_0_15_12_17_n_4,
DOC(0) => RAM_reg_0_15_12_17_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_12_17_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_18_23: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(19 downto 18),
DIB(1 downto 0) => I127(21 downto 20),
DIC(1 downto 0) => I127(23 downto 22),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_18_23_n_0,
DOA(0) => RAM_reg_0_15_18_23_n_1,
DOB(1) => RAM_reg_0_15_18_23_n_2,
DOB(0) => RAM_reg_0_15_18_23_n_3,
DOC(1) => RAM_reg_0_15_18_23_n_4,
DOC(0) => RAM_reg_0_15_18_23_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_18_23_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_24_29: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(25 downto 24),
DIB(1 downto 0) => I127(27 downto 26),
DIC(1 downto 0) => I127(29 downto 28),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_24_29_n_0,
DOA(0) => RAM_reg_0_15_24_29_n_1,
DOB(1) => RAM_reg_0_15_24_29_n_2,
DOB(0) => RAM_reg_0_15_24_29_n_3,
DOC(1) => RAM_reg_0_15_24_29_n_4,
DOC(0) => RAM_reg_0_15_24_29_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_24_29_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_30_35: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(31 downto 30),
DIB(1 downto 0) => I127(33 downto 32),
DIC(1 downto 0) => I127(35 downto 34),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_30_35_n_0,
DOA(0) => RAM_reg_0_15_30_35_n_1,
DOB(1) => RAM_reg_0_15_30_35_n_2,
DOB(0) => RAM_reg_0_15_30_35_n_3,
DOC(1) => RAM_reg_0_15_30_35_n_4,
DOC(0) => RAM_reg_0_15_30_35_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_30_35_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_36_38: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(37 downto 36),
DIB(1) => '0',
DIB(0) => I127(38),
DIC(1 downto 0) => B"00",
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_36_38_n_0,
DOA(0) => RAM_reg_0_15_36_38_n_1,
DOB(1) => NLW_RAM_reg_0_15_36_38_DOB_UNCONNECTED(1),
DOB(0) => RAM_reg_0_15_36_38_n_3,
DOC(1 downto 0) => NLW_RAM_reg_0_15_36_38_DOC_UNCONNECTED(1 downto 0),
DOD(1 downto 0) => NLW_RAM_reg_0_15_36_38_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
RAM_reg_0_15_6_11: unisim.vcomponents.RAM32M
port map (
ADDRA(4) => '0',
ADDRA(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRB(4) => '0',
ADDRB(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRC(4) => '0',
ADDRC(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
ADDRD(4) => '0',
ADDRD(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
DIA(1 downto 0) => I127(7 downto 6),
DIB(1 downto 0) => I127(9 downto 8),
DIC(1 downto 0) => I127(11 downto 10),
DID(1 downto 0) => B"00",
DOA(1) => RAM_reg_0_15_6_11_n_0,
DOA(0) => RAM_reg_0_15_6_11_n_1,
DOB(1) => RAM_reg_0_15_6_11_n_2,
DOB(0) => RAM_reg_0_15_6_11_n_3,
DOC(1) => RAM_reg_0_15_6_11_n_4,
DOC(0) => RAM_reg_0_15_6_11_n_5,
DOD(1 downto 0) => NLW_RAM_reg_0_15_6_11_DOD_UNCONNECTED(1 downto 0),
WCLK => m_aclk,
WE => E(0)
);
\gpr1.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_1,
Q => Q(0),
R => '0'
);
\gpr1.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_5,
Q => Q(10),
R => '0'
);
\gpr1.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_4,
Q => Q(11),
R => '0'
);
\gpr1.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_1,
Q => Q(12),
R => '0'
);
\gpr1.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_0,
Q => Q(13),
R => '0'
);
\gpr1.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_3,
Q => Q(14),
R => '0'
);
\gpr1.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_2,
Q => Q(15),
R => '0'
);
\gpr1.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_5,
Q => Q(16),
R => '0'
);
\gpr1.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_12_17_n_4,
Q => Q(17),
R => '0'
);
\gpr1.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_1,
Q => Q(18),
R => '0'
);
\gpr1.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_0,
Q => Q(19),
R => '0'
);
\gpr1.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_0,
Q => Q(1),
R => '0'
);
\gpr1.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_3,
Q => Q(20),
R => '0'
);
\gpr1.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_2,
Q => Q(21),
R => '0'
);
\gpr1.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_5,
Q => Q(22),
R => '0'
);
\gpr1.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_18_23_n_4,
Q => Q(23),
R => '0'
);
\gpr1.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_1,
Q => Q(24),
R => '0'
);
\gpr1.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_0,
Q => Q(25),
R => '0'
);
\gpr1.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_3,
Q => Q(26),
R => '0'
);
\gpr1.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_2,
Q => Q(27),
R => '0'
);
\gpr1.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_5,
Q => Q(28),
R => '0'
);
\gpr1.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_24_29_n_4,
Q => Q(29),
R => '0'
);
\gpr1.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_3,
Q => Q(2),
R => '0'
);
\gpr1.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_1,
Q => Q(30),
R => '0'
);
\gpr1.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_0,
Q => Q(31),
R => '0'
);
\gpr1.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_3,
Q => Q(32),
R => '0'
);
\gpr1.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_2,
Q => Q(33),
R => '0'
);
\gpr1.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_5,
Q => Q(34),
R => '0'
);
\gpr1.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_30_35_n_4,
Q => Q(35),
R => '0'
);
\gpr1.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_1,
Q => Q(36),
R => '0'
);
\gpr1.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_0,
Q => Q(37),
R => '0'
);
\gpr1.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_36_38_n_3,
Q => Q(38),
R => '0'
);
\gpr1.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_2,
Q => Q(3),
R => '0'
);
\gpr1.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_5,
Q => Q(4),
R => '0'
);
\gpr1.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_0_5_n_4,
Q => Q(5),
R => '0'
);
\gpr1.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_1,
Q => Q(6),
R => '0'
);
\gpr1.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_0,
Q => Q(7),
R => '0'
);
\gpr1.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_3,
Q => Q(8),
R => '0'
);
\gpr1.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \gpregsm1.curr_fwft_state_reg[1]\(0),
D => RAM_reg_0_15_6_11_n_2,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_rd_bin_cntr;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__6\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__2\ : label is "soft_lutpair28";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__2\ : label is "soft_lutpair27";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__2\ : label is "soft_lutpair26";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__2\ : label is "soft_lutpair27";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__6\(0)
);
\gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__6\(1)
);
\gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__6\(2)
);
\gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__6\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__6\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__6\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__2_n_0\,
I1 => \ram_empty_i_i_3__2_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__2_n_0\
);
\ram_empty_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr_20 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_bin_cntr_20 : entity is "rd_bin_cntr";
end bd_auto_cc_0_rd_bin_cntr_20;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr_20 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__0\ : label is "soft_lutpair22";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__0\ : label is "soft_lutpair21";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__0\ : label is "soft_lutpair20";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__0\ : label is "soft_lutpair21";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__0\(0)
);
\gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__0\(1)
);
\gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__0\(2)
);
\gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__0\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__0\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__0\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__0_n_0\,
I1 => \ram_empty_i_i_3__0_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__0_n_0\
);
\ram_empty_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr_41 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_bin_cntr_41 : entity is "rd_bin_cntr";
end bd_auto_cc_0_rd_bin_cntr_41;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr_41 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal plusOp : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_empty_i_i_2_n_0 : STD_LOGIC;
signal ram_empty_i_i_3_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1\ : label is "soft_lutpair16";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1\ : label is "soft_lutpair15";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1\ : label is "soft_lutpair14";
attribute SOFT_HLUTNM of ram_empty_i_i_2 : label is "soft_lutpair14";
attribute SOFT_HLUTNM of ram_empty_i_i_3 : label is "soft_lutpair15";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => plusOp(0)
);
\gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => plusOp(1)
);
\gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => plusOp(2)
);
\gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => plusOp(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => plusOp(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => plusOp(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2)
);
ram_empty_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => ram_empty_i_i_2_n_0,
I1 => ram_empty_i_i_3_n_0,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
ram_empty_i_i_2: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => ram_empty_i_i_2_n_0
);
ram_empty_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => ram_empty_i_i_3_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr_62 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_bin_cntr_62 : entity is "rd_bin_cntr";
end bd_auto_cc_0_rd_bin_cntr_62;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr_62 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__8\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__3\ : label is "soft_lutpair10";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__3\ : label is "soft_lutpair9";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__3\ : label is "soft_lutpair8";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__3\ : label is "soft_lutpair9";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__8\(0)
);
\gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__8\(1)
);
\gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__8\(2)
);
\gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__8\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__8\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__8\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__3_n_0\,
I1 => \ram_empty_i_i_3__3_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__3_n_0\
);
\ram_empty_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_bin_cntr_86 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_bin_cntr_86 : entity is "rd_bin_cntr";
end bd_auto_cc_0_rd_bin_cntr_86;
architecture STRUCTURE of bd_auto_cc_0_rd_bin_cntr_86 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gnxpm_cdc.rd_pntr_gc_reg[3]\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__2\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \ram_empty_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_empty_i_i_3__1_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gc0.count[2]_i_1__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gc0.count[3]_i_1__1\ : label is "soft_lutpair4";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[0]_i_1__1\ : label is "soft_lutpair3";
attribute SOFT_HLUTNM of \gnxpm_cdc.rd_pntr_gc[2]_i_1__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ram_empty_i_i_2__1\ : label is "soft_lutpair2";
attribute SOFT_HLUTNM of \ram_empty_i_i_3__1\ : label is "soft_lutpair3";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) <= \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0);
\gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__2\(0)
);
\gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__2\(1)
);
\gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__2\(2)
);
\gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__2\(3)
);
\gc0.count_d1_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(0),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0)
);
\gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(1),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1)
);
\gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(2),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2)
);
\gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \^q\(3),
Q => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3)
);
\gc0.count_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__2\(0),
PRE => \out\(0),
Q => \^q\(0)
);
\gc0.count_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(1),
Q => \^q\(1)
);
\gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(2),
Q => \^q\(2)
);
\gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => \out\(0),
D => \plusOp__2\(3),
Q => \^q\(3)
);
\gnxpm_cdc.rd_pntr_gc[0]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
O => D(0)
);
\gnxpm_cdc.rd_pntr_gc[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
O => D(1)
);
\gnxpm_cdc.rd_pntr_gc[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
O => D(2)
);
\ram_empty_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"F888"
)
port map (
I0 => \ram_empty_i_i_2__1_n_0\,
I1 => \ram_empty_i_i_3__1_n_0\,
I2 => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
I3 => \gpregsm1.curr_fwft_state_reg[1]\,
O => ram_empty_i_reg
);
\ram_empty_i_i_2__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(2),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(2),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(3),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
O => \ram_empty_i_i_2__1_n_0\
);
\ram_empty_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"9009"
)
port map (
I0 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(0),
I1 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I2 => \^gnxpm_cdc.rd_pntr_gc_reg[3]\(1),
I3 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(1),
O => \ram_empty_i_i_3__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_rd_fwft;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[5]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_bready,
O => \goreg_dm.dout_i_reg[5]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_bready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_bready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_bvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft_18 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[36]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_fwft_18 : entity is "rd_fwft";
end bd_auto_cc_0_rd_fwft_18;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft_18 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[36]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_wready,
O => \goreg_dm.dout_i_reg[36]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_wready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_wvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_wvalid
);
\ram_empty_i_i_5__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_wready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft_39 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_fwft_39 : entity is "rd_fwft";
end bd_auto_cc_0_rd_fwft_39;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft_39 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
aempty_fwft_fb_i_i_1: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
empty_fwft_fb_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
empty_fwft_fb_o_i_i_1: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[64]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_awready,
O => \goreg_dm.dout_i_reg[64]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_awready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_awvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_awvalid
);
ram_empty_i_i_5: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_awready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft_60 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[38]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_fwft_60 : entity is "rd_fwft";
end bd_auto_cc_0_rd_fwft_60;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft_60 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[38]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => s_axi_rready,
O => \goreg_dm.dout_i_reg[38]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => s_axi_rready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
\ram_empty_i_i_5__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => s_axi_rready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
s_axi_rvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_fwft_84 is
port (
ram_empty_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
ram_empty_fb_i_reg : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
Q : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_fwft_84 : entity is "rd_fwft";
end bd_auto_cc_0_rd_fwft_84;
architecture STRUCTURE of bd_auto_cc_0_rd_fwft_84 is
signal aempty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of aempty_fwft_fb_i : signal is std.standard.true;
signal aempty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of aempty_fwft_i : signal is std.standard.true;
signal aempty_fwft_i0 : STD_LOGIC;
signal curr_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
attribute DONT_TOUCH of curr_fwft_state : signal is std.standard.true;
signal empty_fwft_fb_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_i : signal is std.standard.true;
signal empty_fwft_fb_o_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_fb_o_i : signal is std.standard.true;
signal empty_fwft_fb_o_i0 : STD_LOGIC;
signal empty_fwft_i : STD_LOGIC;
attribute DONT_TOUCH of empty_fwft_i : signal is std.standard.true;
signal empty_fwft_i0 : STD_LOGIC;
signal next_fwft_state : STD_LOGIC_VECTOR ( 1 downto 0 );
signal user_valid : STD_LOGIC;
attribute DONT_TOUCH of user_valid : signal is std.standard.true;
attribute DONT_TOUCH of aempty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of aempty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of aempty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of aempty_fwft_i_reg : label is std.standard.true;
attribute KEEP of aempty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of aempty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_fb_o_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_fb_o_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_fb_o_i_reg : label is "no";
attribute DONT_TOUCH of empty_fwft_i_reg : label is std.standard.true;
attribute KEEP of empty_fwft_i_reg : label is "yes";
attribute equivalent_register_removal of empty_fwft_i_reg : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[0]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[0]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.curr_fwft_state_reg[1]\ : label is std.standard.true;
attribute KEEP of \gpregsm1.curr_fwft_state_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.curr_fwft_state_reg[1]\ : label is "no";
attribute DONT_TOUCH of \gpregsm1.user_valid_reg\ : label is std.standard.true;
attribute KEEP of \gpregsm1.user_valid_reg\ : label is "yes";
attribute equivalent_register_removal of \gpregsm1.user_valid_reg\ : label is "no";
begin
\aempty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT5
generic map(
INIT => X"FAEF8000"
)
port map (
I0 => ram_empty_fb_i_reg,
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => curr_fwft_state(1),
I4 => aempty_fwft_fb_i,
O => aempty_fwft_i0
);
aempty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_fb_i
);
aempty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => aempty_fwft_i0,
PRE => \out\(1),
Q => aempty_fwft_i
);
\empty_fwft_fb_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_i0
);
empty_fwft_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_fb_i
);
\empty_fwft_fb_o_i_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"B2A2"
)
port map (
I0 => empty_fwft_fb_o_i,
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => empty_fwft_fb_o_i0
);
empty_fwft_fb_o_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_fb_o_i0,
PRE => \out\(1),
Q => empty_fwft_fb_o_i
);
empty_fwft_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => empty_fwft_i0,
PRE => \out\(1),
Q => empty_fwft_i
);
\gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"00DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => E(0)
);
\goreg_dm.dout_i[64]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4404"
)
port map (
I0 => \out\(0),
I1 => curr_fwft_state(1),
I2 => curr_fwft_state(0),
I3 => m_axi_arready,
O => \goreg_dm.dout_i_reg[64]\(0)
);
\gpregsm1.curr_fwft_state[0]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"AE"
)
port map (
I0 => curr_fwft_state(1),
I1 => curr_fwft_state(0),
I2 => m_axi_arready,
O => next_fwft_state(0)
);
\gpregsm1.curr_fwft_state[1]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"20FF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
O => next_fwft_state(1)
);
\gpregsm1.curr_fwft_state_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => curr_fwft_state(0)
);
\gpregsm1.curr_fwft_state_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(1),
Q => curr_fwft_state(1)
);
\gpregsm1.user_valid_reg\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \out\(1),
D => next_fwft_state(0),
Q => user_valid
);
m_axi_arvalid_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => empty_fwft_i,
O => m_axi_arvalid
);
\ram_empty_i_i_5__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"00DF0000000000DF"
)
port map (
I0 => curr_fwft_state(1),
I1 => m_axi_arready,
I2 => curr_fwft_state(0),
I3 => ram_empty_fb_i_reg,
I4 => \gnxpm_cdc.wr_pntr_bin_reg[3]\(0),
I5 => Q(0),
O => ram_empty_i_reg
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_rd_status_flags_as;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as_19 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_status_flags_as_19 : entity is "rd_status_flags_as";
end bd_auto_cc_0_rd_status_flags_as_19;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as_19 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as_40 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_status_flags_as_40 : entity is "rd_status_flags_as";
end bd_auto_cc_0_rd_status_flags_as_40;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as_40 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as_61 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_status_flags_as_61 : entity is "rd_status_flags_as";
end bd_auto_cc_0_rd_status_flags_as_61;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as_61 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_status_flags_as_85 is
port (
\out\ : out STD_LOGIC;
\gc0.count_d1_reg[2]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_status_flags_as_85 : entity is "rd_status_flags_as";
end bd_auto_cc_0_rd_status_flags_as_85;
architecture STRUCTURE of bd_auto_cc_0_rd_status_flags_as_85 is
signal ram_empty_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_empty_fb_i : signal is std.standard.true;
signal ram_empty_i : STD_LOGIC;
attribute DONT_TOUCH of ram_empty_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_empty_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_empty_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_empty_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_empty_i_reg : label is std.standard.true;
attribute KEEP of ram_empty_i_reg : label is "yes";
attribute equivalent_register_removal of ram_empty_i_reg : label is "no";
begin
\out\ <= ram_empty_fb_i;
ram_empty_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_fb_i
);
ram_empty_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gc0.count_d1_reg[2]\,
PRE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0),
Q => ram_empty_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
end bd_auto_cc_0_synchronizer_ff;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_1 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_1 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_1;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_1 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_10 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_10 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_10;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_10 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_11 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_11 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_11;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_11 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_12 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_12 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_12;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_12 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_13 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_13 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_13;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_13 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_14 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_14 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_14;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_14 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_15 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_15 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_15;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_15 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_2 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_2 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_2;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_2 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_3 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_3 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_3;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_3 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_31 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_31 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_31;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_31 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_32 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_32 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_32;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_32 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_33 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_33 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_33;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_33 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_34 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_34 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_34;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_34 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_35 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_35 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_35;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_35 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_36 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_36 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_36;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_36 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_4 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_4 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_4;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_4 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_5 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_5 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_5;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_5 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_52 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_52 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_52;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_52 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_53 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_53 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_53;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_53 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_54 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_54 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_54;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_54 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_55 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_55 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_55;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_55 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_56 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_56 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_56;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_56 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_57 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_57 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_57;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_57 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_75 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_75 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_75;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_75 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_76 is
port (
\out\ : out STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_76 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_76;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_76 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\out\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => in0(0),
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_77 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_77 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_77;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_77 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.rd_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_78 is
port (
\Q_reg_reg[0]_0\ : out STD_LOGIC;
AS : out STD_LOGIC_VECTOR ( 0 to 0 );
\out\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
in0 : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_78 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_78;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_78 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]_0\ <= Q_reg;
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \out\,
Q => Q_reg,
R => '0'
);
\ngwrdrst.grst.g7serrst.wr_rst_reg[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => in0(0),
I1 => Q_reg,
O => AS(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_79 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
m_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_79 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_79;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_79 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_synchronizer_ff_80 is
port (
\Q_reg_reg[0]_0\ : in STD_LOGIC;
s_aclk : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_synchronizer_ff_80 : entity is "synchronizer_ff";
end bd_auto_cc_0_synchronizer_ff_80;
architecture STRUCTURE of bd_auto_cc_0_synchronizer_ff_80 is
signal Q_reg : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
begin
\Q_reg_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => \Q_reg_reg[0]_0\,
Q => Q_reg,
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0_21\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0_21\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0_21\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0_21\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0_42\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0_42\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0_42\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0_42\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0_63\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0_63\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0_63\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0_63\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized0_87\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized0_87\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized0_87\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized0_87\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1_22\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1_22\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1_22\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1_22\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1_43\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1_43\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1_43\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1_43\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1_64\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1_64\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1_64\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1_64\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized1_88\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized1_88\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized1_88\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized1_88\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => Q(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2_23\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2_23\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2_23\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2_23\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2_44\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2_44\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2_44\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2_44\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2_65\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2_65\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2_65\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2_65\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized2_89\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized2_89\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized2_89\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized2_89\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3_24\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3_24\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3_24\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3_24\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3_45\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3_45\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3_45\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3_45\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3_66\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3_66\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3_66\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3_66\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized3_90\ is
port (
D : out STD_LOGIC_VECTOR ( 3 downto 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized3_90\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized3_90\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized3_90\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
D(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4_25\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4_25\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4_25\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4_25\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4_46\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4_46\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4_46\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4_46\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4_67\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4_67\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4_67\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4_67\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized4_91\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized4_91\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized4_91\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized4_91\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.wr_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5_26\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5_26\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5_26\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5_26\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5_47\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5_47\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5_47\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5_47\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5_68\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5_68\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5_68\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5_68\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_synchronizer_ff__parameterized5_92\ is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
D : out STD_LOGIC_VECTOR ( 0 to 0 );
\Q_reg_reg[3]_0\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_synchronizer_ff__parameterized5_92\ : entity is "synchronizer_ff";
end \bd_auto_cc_0_synchronizer_ff__parameterized5_92\;
architecture STRUCTURE of \bd_auto_cc_0_synchronizer_ff__parameterized5_92\ is
signal Q_reg : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute async_reg : string;
attribute async_reg of Q_reg : signal is "true";
attribute msgon : string;
attribute msgon of Q_reg : signal is "true";
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \Q_reg_reg[0]\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \Q_reg_reg[0]\ : label is "yes";
attribute msgon of \Q_reg_reg[0]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[1]\ : label is "yes";
attribute msgon of \Q_reg_reg[1]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[2]\ : label is "yes";
attribute msgon of \Q_reg_reg[2]\ : label is "true";
attribute ASYNC_REG_boolean of \Q_reg_reg[3]\ : label is std.standard.true;
attribute KEEP of \Q_reg_reg[3]\ : label is "yes";
attribute msgon of \Q_reg_reg[3]\ : label is "true";
begin
\out\(3 downto 0) <= Q_reg(3 downto 0);
\Q_reg_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(0),
Q => Q_reg(0)
);
\Q_reg_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(1),
Q => Q_reg(1)
);
\Q_reg_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(2),
Q => Q_reg(2)
);
\Q_reg_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \Q_reg_reg[3]_0\(3),
Q => Q_reg(3)
);
\gnxpm_cdc.rd_pntr_bin[2]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => Q_reg(2),
I1 => Q_reg(3),
O => D(0)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_wr_bin_cntr;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__1\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1\ : label is "soft_lutpair29";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1\ : label is "soft_lutpair29";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__1\(0)
);
\gic0.gc0.count[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__1\(1)
);
\gic0.gc0.count[2]_i_1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__1\(2)
);
\gic0.gc0.count[3]_i_1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__1\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__1\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__1\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr_17 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_bin_cntr_17 : entity is "wr_bin_cntr";
end bd_auto_cc_0_wr_bin_cntr_17;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr_17 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__5\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__2\ : label is "soft_lutpair23";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__2\ : label is "soft_lutpair23";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__2\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__5\(0)
);
\gic0.gc0.count[1]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__5\(1)
);
\gic0.gc0.count[2]_i_1__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__5\(2)
);
\gic0.gc0.count[3]_i_1__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__5\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__5\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__5\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr_38 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_bin_cntr_38 : entity is "wr_bin_cntr";
end bd_auto_cc_0_wr_bin_cntr_38;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr_38 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__4\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__1\ : label is "soft_lutpair17";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__1\ : label is "soft_lutpair17";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__4\(0)
);
\gic0.gc0.count[1]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__4\(1)
);
\gic0.gc0.count[2]_i_1__1\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__4\(2)
);
\gic0.gc0.count[3]_i_1__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__4\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__4\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__4\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr_59 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_bin_cntr_59 : entity is "wr_bin_cntr";
end bd_auto_cc_0_wr_bin_cntr_59;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr_59 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__3\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__0\ : label is "soft_lutpair11";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__0\ : label is "soft_lutpair11";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__0\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__3\(0)
);
\gic0.gc0.count[1]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__3\(1)
);
\gic0.gc0.count[2]_i_1__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__3\(2)
);
\gic0.gc0.count[3]_i_1__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__3\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => E(0),
D => \plusOp__3\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__3\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_bin_cntr_83 is
port (
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]_0\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_bin_cntr_83 : entity is "wr_bin_cntr";
end bd_auto_cc_0_wr_bin_cntr_83;
architecture STRUCTURE of bd_auto_cc_0_wr_bin_cntr_83 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^gic0.gc0.count_d2_reg[3]_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \plusOp__7\ : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \gic0.gc0.count[2]_i_1__3\ : label is "soft_lutpair5";
attribute SOFT_HLUTNM of \gic0.gc0.count[3]_i_1__3\ : label is "soft_lutpair5";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) <= \^gic0.gc0.count_d2_reg[3]_0\(3 downto 0);
\gic0.gc0.count[0]_i_1__3\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => \^q\(0),
O => \plusOp__7\(0)
);
\gic0.gc0.count[1]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \^q\(0),
I1 => \^q\(1),
O => \plusOp__7\(1)
);
\gic0.gc0.count[2]_i_1__3\: unisim.vcomponents.LUT3
generic map(
INIT => X"78"
)
port map (
I0 => \^q\(1),
I1 => \^q\(0),
I2 => \^q\(2),
O => \plusOp__7\(2)
);
\gic0.gc0.count[3]_i_1__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"7F80"
)
port map (
I0 => \^q\(2),
I1 => \^q\(0),
I2 => \^q\(1),
I3 => \^q\(3),
O => \plusOp__7\(3)
);
\gic0.gc0.count_d1_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \^q\(0),
PRE => AR(0),
Q => \^gic0.gc0.count_d2_reg[3]_0\(0)
);
\gic0.gc0.count_d1_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(1),
Q => \^gic0.gc0.count_d2_reg[3]_0\(1)
);
\gic0.gc0.count_d1_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(2),
Q => \^gic0.gc0.count_d2_reg[3]_0\(2)
);
\gic0.gc0.count_d1_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^q\(3),
Q => \^gic0.gc0.count_d2_reg[3]_0\(3)
);
\gic0.gc0.count_d2_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(0)
);
\gic0.gc0.count_d2_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(1)
);
\gic0.gc0.count_d2_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(2)
);
\gic0.gc0.count_d2_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \^gic0.gc0.count_d2_reg[3]_0\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3)
);
\gic0.gc0.count_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(0),
Q => \^q\(0)
);
\gic0.gc0.count_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => E(0),
D => \plusOp__7\(1),
PRE => AR(0),
Q => \^q\(1)
);
\gic0.gc0.count_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(2),
Q => \^q\(2)
);
\gic0.gc0.count_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => E(0),
CLR => AR(0),
D => \plusOp__7\(3),
Q => \^q\(3)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_wr_status_flags_as;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_bvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_bready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_bready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
ram_full_i_i_3: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_bvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as_16 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_status_flags_as_16 : entity is "wr_status_flags_as";
end bd_auto_cc_0_wr_status_flags_as_16;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as_16 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__2\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_wvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__2\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_wvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_wready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_wready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as_37 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_status_flags_as_37 : entity is "wr_status_flags_as";
end bd_auto_cc_0_wr_status_flags_as_37;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as_37 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__1\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_awvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_awvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_awready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_awready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as_58 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_status_flags_as_58 : entity is "wr_status_flags_as";
end bd_auto_cc_0_wr_status_flags_as_58;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as_58 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__0\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => m_axi_rvalid,
I1 => ram_full_fb_i,
O => E(0)
);
m_axi_rready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => m_axi_rready
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__0\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => m_axi_rvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_status_flags_as_82 is
port (
ram_full_fb_i_reg_0 : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_status_flags_as_82 : entity is "wr_status_flags_as";
end bd_auto_cc_0_wr_status_flags_as_82;
architecture STRUCTURE of bd_auto_cc_0_wr_status_flags_as_82 is
signal ram_full_fb_i : STD_LOGIC;
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of ram_full_fb_i : signal is std.standard.true;
signal ram_full_i : STD_LOGIC;
attribute DONT_TOUCH of ram_full_i : signal is std.standard.true;
attribute DONT_TOUCH of ram_full_fb_i_reg : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of ram_full_fb_i_reg : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of ram_full_fb_i_reg : label is "no";
attribute DONT_TOUCH of ram_full_i_reg : label is std.standard.true;
attribute KEEP of ram_full_i_reg : label is "yes";
attribute equivalent_register_removal of ram_full_i_reg : label is "no";
begin
\gic0.gc0.count_d1[3]_i_1__3\: unisim.vcomponents.LUT2
generic map(
INIT => X"2"
)
port map (
I0 => s_axi_arvalid,
I1 => ram_full_fb_i,
O => E(0)
);
ram_full_fb_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_fb_i
);
\ram_full_i_i_3__3\: unisim.vcomponents.LUT4
generic map(
INIT => X"4004"
)
port map (
I0 => ram_full_fb_i,
I1 => s_axi_arvalid,
I2 => Q(0),
I3 => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
O => ram_full_fb_i_reg_0
);
ram_full_i_reg: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \gic0.gc0.count_d1_reg[3]\,
PRE => \out\,
Q => ram_full_i
);
s_axi_arready_INST_0: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => ram_full_i,
O => s_axi_arready
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_clk_x_pntrs;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal ram_full_i_i_2_n_0 : STD_LOGIC;
signal ram_full_i_i_4_n_0 : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair24";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair25";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair25";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
ram_full_i_i_1: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => ram_full_i_i_2_n_0,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => ram_full_i_i_4_n_0,
O => ram_full_fb_i_reg
);
ram_full_i_i_2: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => ram_full_i_i_2_n_0
);
ram_full_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => ram_full_i_i_4_n_0
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs_27 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_clk_x_pntrs_27 : entity is "clk_x_pntrs";
end bd_auto_cc_0_clk_x_pntrs_27;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs_27 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 1 to 1 );
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_0_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__1_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__1_n_0\ : STD_LOGIC;
signal rd_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
signal wr_pntr_gc : STD_LOGIC_VECTOR ( 3 downto 0 );
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair12";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair13";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair13";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => gray2bin(1)
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0_42\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3 downto 0) => wr_pntr_gc(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1_43\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3 downto 0) => rd_pntr_gc(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2_44\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3_45\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4_46\
port map (
D(0) => p_0_out,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5_47\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out_1(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out_1(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out_1(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(0),
Q => rd_pntr_gc(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(1),
Q => rd_pntr_gc(1)
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[2]\(2),
Q => rd_pntr_gc(2)
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => rd_pntr_gc(3)
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => gray2bin(1),
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => p_0_out,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => wr_pntr_gc(0)
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => wr_pntr_gc(1)
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => wr_pntr_gc(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => wr_pntr_gc(3)
);
ram_empty_i_i_4: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__1_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__1_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_2__1_n_0\
);
\ram_full_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out_1(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out_1(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out_1(0),
O => \ram_full_i_i_4__1_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs_48 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
ram_empty_i_reg : out STD_LOGIC;
ram_empty_i_reg_0 : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
Q : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_clk_x_pntrs_48 : entity is "clk_x_pntrs";
end bd_auto_cc_0_clk_x_pntrs_48;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs_48 is
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_empty_i_reg_0\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__0_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__0_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair6";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[0]_i_1\ : label is "soft_lutpair7";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair7";
begin
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_empty_i_reg_0(3 downto 0) <= \^ram_empty_i_reg_0\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0_63\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1_64\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2_65\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3_66\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
m_aclk => m_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4_67\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5_68\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
m_aclk => m_aclk,
\out\(3 downto 0) => p_8_out(3 downto 0)
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^ram_empty_i_reg_0\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^ram_empty_i_reg_0\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^ram_empty_i_reg_0\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^ram_empty_i_reg_0\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^ram_empty_i_reg_0\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^ram_empty_i_reg_0\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^ram_empty_i_reg_0\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__0_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => Q(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__0_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__0_n_0\
);
\ram_full_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => Q(2),
I2 => p_23_out(1),
I3 => Q(1),
I4 => Q(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__0_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs_6 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_clk_x_pntrs_6 : entity is "clk_x_pntrs";
end bd_auto_cc_0_clk_x_pntrs_6;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs_6 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__2_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__2_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair18";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair19";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair19";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0_21\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1_22\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2_23\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3_24\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4_25\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5_26\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__0\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__2_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__2_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__2_n_0\
);
\ram_full_i_i_4__2\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__2_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_clk_x_pntrs_70 is
port (
\out\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_empty_i_reg : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 3 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
ram_full_fb_i_reg_0 : out STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg_1 : in STD_LOGIC;
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg\ : in STD_LOGIC;
\gic0.gc0.count_reg[2]\ : in STD_LOGIC_VECTOR ( 2 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_aclk : in STD_LOGIC;
AR : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
D : in STD_LOGIC_VECTOR ( 2 downto 0 );
\Q_reg_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_clk_x_pntrs_70 : entity is "clk_x_pntrs";
end bd_auto_cc_0_clk_x_pntrs_70;
architecture STRUCTURE of bd_auto_cc_0_clk_x_pntrs_70 is
signal \^q\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \__0_n_0\ : STD_LOGIC;
signal \__1_n_0\ : STD_LOGIC;
signal \__2_n_0\ : STD_LOGIC;
signal bin2gray : STD_LOGIC_VECTOR ( 2 downto 0 );
signal \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\ : STD_LOGIC;
signal \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\ : STD_LOGIC;
signal \^out\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 2 downto 0 );
signal p_3_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_4_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_5_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_6_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_8_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \^ram_full_fb_i_reg_0\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \ram_full_i_i_2__3_n_0\ : STD_LOGIC;
signal \ram_full_i_i_4__3_n_0\ : STD_LOGIC;
attribute SOFT_HLUTNM : string;
attribute SOFT_HLUTNM of \__1\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \__2\ : label is "soft_lutpair0";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[1]_i_1\ : label is "soft_lutpair1";
attribute SOFT_HLUTNM of \gnxpm_cdc.wr_pntr_gc[2]_i_1\ : label is "soft_lutpair1";
begin
Q(3 downto 0) <= \^q\(3 downto 0);
\out\(3 downto 0) <= \^out\(3 downto 0);
ram_full_fb_i_reg_0(0) <= \^ram_full_fb_i_reg_0\(0);
\__0\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => \^out\(2),
I1 => \^out\(1),
I2 => \^out\(3),
O => \__0_n_0\
);
\__1\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_8_out(1),
I1 => p_8_out(0),
I2 => p_8_out(3),
I3 => p_8_out(2),
O => \__1_n_0\
);
\__2\: unisim.vcomponents.LUT3
generic map(
INIT => X"96"
)
port map (
I0 => p_8_out(2),
I1 => p_8_out(1),
I2 => p_8_out(3),
O => \__2_n_0\
);
\gnxpm_cdc.gsync_stage[1].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized0_87\
port map (
D(3 downto 0) => p_3_out(3 downto 0),
Q(3) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[1].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized1_88\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_4_out(3 downto 0),
Q(3) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\,
Q(2) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\,
Q(1) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\,
Q(0) => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\,
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[2].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized2_89\
port map (
D(3 downto 0) => p_5_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_3_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0)
);
\gnxpm_cdc.gsync_stage[2].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized3_90\
port map (
AR(0) => AR(0),
D(3 downto 0) => p_6_out(3 downto 0),
\Q_reg_reg[3]_0\(3 downto 0) => p_4_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.gsync_stage[3].rd_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized4_91\
port map (
D(0) => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_5_out(3 downto 0),
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
\out\(3 downto 0) => \^out\(3 downto 0)
);
\gnxpm_cdc.gsync_stage[3].wr_stg_inst\: entity work.\bd_auto_cc_0_synchronizer_ff__parameterized5_92\
port map (
AR(0) => AR(0),
D(0) => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
\Q_reg_reg[3]_0\(3 downto 0) => p_6_out(3 downto 0),
\out\(3 downto 0) => p_8_out(3 downto 0),
s_aclk => s_aclk
);
\gnxpm_cdc.rd_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__1_n_0\,
Q => p_23_out(0)
);
\gnxpm_cdc.rd_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \__2_n_0\,
Q => p_23_out(1)
);
\gnxpm_cdc.rd_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gnxpm_cdc.gsync_stage[3].wr_stg_inst_n_4\,
Q => p_23_out(2)
);
\gnxpm_cdc.rd_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => p_8_out(3),
Q => \^ram_full_fb_i_reg_0\(0)
);
\gnxpm_cdc.rd_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.rd_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(1),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.rd_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => D(2),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.rd_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gc0.count_d1_reg[3]\(0),
Q => \gnxpm_cdc.rd_pntr_gc_reg_n_0_[3]\
);
\gnxpm_cdc.wr_pntr_bin_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \Q_reg_reg[1]\(0),
Q => \^q\(0)
);
\gnxpm_cdc.wr_pntr_bin_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \__0_n_0\,
Q => \^q\(1)
);
\gnxpm_cdc.wr_pntr_bin_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \gnxpm_cdc.gsync_stage[3].rd_stg_inst_n_4\,
Q => \^q\(2)
);
\gnxpm_cdc.wr_pntr_bin_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
CLR => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0),
D => \^out\(3),
Q => \^q\(3)
);
\gnxpm_cdc.wr_pntr_gc[0]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(0),
I1 => \gic0.gc0.count_d2_reg[3]\(1),
O => bin2gray(0)
);
\gnxpm_cdc.wr_pntr_gc[1]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(1),
I1 => \gic0.gc0.count_d2_reg[3]\(2),
O => bin2gray(1)
);
\gnxpm_cdc.wr_pntr_gc[2]_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"6"
)
port map (
I0 => \gic0.gc0.count_d2_reg[3]\(2),
I1 => \gic0.gc0.count_d2_reg[3]\(3),
O => bin2gray(2)
);
\gnxpm_cdc.wr_pntr_gc_reg[0]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(0),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[0]\
);
\gnxpm_cdc.wr_pntr_gc_reg[1]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(1),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[1]\
);
\gnxpm_cdc.wr_pntr_gc_reg[2]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => bin2gray(2),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[2]\
);
\gnxpm_cdc.wr_pntr_gc_reg[3]\: unisim.vcomponents.FDCE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
CLR => AR(0),
D => \gic0.gc0.count_d2_reg[3]\(3),
Q => \gnxpm_cdc.wr_pntr_gc_reg_n_0_[3]\
);
\ram_empty_i_i_4__1\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => \^q\(2),
I1 => \gc0.count_reg[2]\(2),
I2 => \^q\(1),
I3 => \gc0.count_reg[2]\(1),
I4 => \gc0.count_reg[2]\(0),
I5 => \^q\(0),
O => ram_empty_i_reg
);
\ram_full_i_i_1__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"0000F88F00008888"
)
port map (
I0 => \ram_full_i_i_2__3_n_0\,
I1 => ram_full_fb_i_reg_1,
I2 => \gic0.gc0.count_d1_reg[3]\(3),
I3 => \^ram_full_fb_i_reg_0\(0),
I4 => \grstd1.grst_full.grst_f.rst_d3_reg\,
I5 => \ram_full_i_i_4__3_n_0\,
O => ram_full_fb_i_reg
);
\ram_full_i_i_2__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_reg[2]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_reg[2]\(1),
I4 => \gic0.gc0.count_reg[2]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_2__3_n_0\
);
\ram_full_i_i_4__3\: unisim.vcomponents.LUT6
generic map(
INIT => X"9009000000009009"
)
port map (
I0 => p_23_out(2),
I1 => \gic0.gc0.count_d1_reg[3]\(2),
I2 => p_23_out(1),
I3 => \gic0.gc0.count_d1_reg[3]\(1),
I4 => \gic0.gc0.count_d1_reg[3]\(0),
I5 => p_23_out(0),
O => \ram_full_i_i_4__3_n_0\
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_memory is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
ram_full_fb_i_reg : in STD_LOGIC_VECTOR ( 0 to 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_memory;
architecture STRUCTURE of bd_auto_cc_0_memory is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.bd_auto_cc_0_dmem
port map (
DI(64 downto 0) => DI(64 downto 0),
dout_i(64) => \gdm.dm_gen.dm_n_0\,
dout_i(63) => \gdm.dm_gen.dm_n_1\,
dout_i(62) => \gdm.dm_gen.dm_n_2\,
dout_i(61) => \gdm.dm_gen.dm_n_3\,
dout_i(60) => \gdm.dm_gen.dm_n_4\,
dout_i(59) => \gdm.dm_gen.dm_n_5\,
dout_i(58) => \gdm.dm_gen.dm_n_6\,
dout_i(57) => \gdm.dm_gen.dm_n_7\,
dout_i(56) => \gdm.dm_gen.dm_n_8\,
dout_i(55) => \gdm.dm_gen.dm_n_9\,
dout_i(54) => \gdm.dm_gen.dm_n_10\,
dout_i(53) => \gdm.dm_gen.dm_n_11\,
dout_i(52) => \gdm.dm_gen.dm_n_12\,
dout_i(51) => \gdm.dm_gen.dm_n_13\,
dout_i(50) => \gdm.dm_gen.dm_n_14\,
dout_i(49) => \gdm.dm_gen.dm_n_15\,
dout_i(48) => \gdm.dm_gen.dm_n_16\,
dout_i(47) => \gdm.dm_gen.dm_n_17\,
dout_i(46) => \gdm.dm_gen.dm_n_18\,
dout_i(45) => \gdm.dm_gen.dm_n_19\,
dout_i(44) => \gdm.dm_gen.dm_n_20\,
dout_i(43) => \gdm.dm_gen.dm_n_21\,
dout_i(42) => \gdm.dm_gen.dm_n_22\,
dout_i(41) => \gdm.dm_gen.dm_n_23\,
dout_i(40) => \gdm.dm_gen.dm_n_24\,
dout_i(39) => \gdm.dm_gen.dm_n_25\,
dout_i(38) => \gdm.dm_gen.dm_n_26\,
dout_i(37) => \gdm.dm_gen.dm_n_27\,
dout_i(36) => \gdm.dm_gen.dm_n_28\,
dout_i(35) => \gdm.dm_gen.dm_n_29\,
dout_i(34) => \gdm.dm_gen.dm_n_30\,
dout_i(33) => \gdm.dm_gen.dm_n_31\,
dout_i(32) => \gdm.dm_gen.dm_n_32\,
dout_i(31) => \gdm.dm_gen.dm_n_33\,
dout_i(30) => \gdm.dm_gen.dm_n_34\,
dout_i(29) => \gdm.dm_gen.dm_n_35\,
dout_i(28) => \gdm.dm_gen.dm_n_36\,
dout_i(27) => \gdm.dm_gen.dm_n_37\,
dout_i(26) => \gdm.dm_gen.dm_n_38\,
dout_i(25) => \gdm.dm_gen.dm_n_39\,
dout_i(24) => \gdm.dm_gen.dm_n_40\,
dout_i(23) => \gdm.dm_gen.dm_n_41\,
dout_i(22) => \gdm.dm_gen.dm_n_42\,
dout_i(21) => \gdm.dm_gen.dm_n_43\,
dout_i(20) => \gdm.dm_gen.dm_n_44\,
dout_i(19) => \gdm.dm_gen.dm_n_45\,
dout_i(18) => \gdm.dm_gen.dm_n_46\,
dout_i(17) => \gdm.dm_gen.dm_n_47\,
dout_i(16) => \gdm.dm_gen.dm_n_48\,
dout_i(15) => \gdm.dm_gen.dm_n_49\,
dout_i(14) => \gdm.dm_gen.dm_n_50\,
dout_i(13) => \gdm.dm_gen.dm_n_51\,
dout_i(12) => \gdm.dm_gen.dm_n_52\,
dout_i(11) => \gdm.dm_gen.dm_n_53\,
dout_i(10) => \gdm.dm_gen.dm_n_54\,
dout_i(9) => \gdm.dm_gen.dm_n_55\,
dout_i(8) => \gdm.dm_gen.dm_n_56\,
dout_i(7) => \gdm.dm_gen.dm_n_57\,
dout_i(6) => \gdm.dm_gen.dm_n_58\,
dout_i(5) => \gdm.dm_gen.dm_n_59\,
dout_i(4) => \gdm.dm_gen.dm_n_60\,
dout_i(3) => \gdm.dm_gen.dm_n_61\,
dout_i(2) => \gdm.dm_gen.dm_n_62\,
dout_i(1) => \gdm.dm_gen.dm_n_63\,
dout_i(0) => \gdm.dm_gen.dm_n_64\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => ram_full_fb_i_reg(0),
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_64\,
Q => Q(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_54\,
Q => Q(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_53\,
Q => Q(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_52\,
Q => Q(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_51\,
Q => Q(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_50\,
Q => Q(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_49\,
Q => Q(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_48\,
Q => Q(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_47\,
Q => Q(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_46\,
Q => Q(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_45\,
Q => Q(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_63\,
Q => Q(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_44\,
Q => Q(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_43\,
Q => Q(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_42\,
Q => Q(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_41\,
Q => Q(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_40\,
Q => Q(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_39\,
Q => Q(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_38\,
Q => Q(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_37\,
Q => Q(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_36\,
Q => Q(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_35\,
Q => Q(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_62\,
Q => Q(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_34\,
Q => Q(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_33\,
Q => Q(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_32\,
Q => Q(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_31\,
Q => Q(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_30\,
Q => Q(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_29\,
Q => Q(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_28\,
Q => Q(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_27\,
Q => Q(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_26\,
Q => Q(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_25\,
Q => Q(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_61\,
Q => Q(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_24\,
Q => Q(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_23\,
Q => Q(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_22\,
Q => Q(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_21\,
Q => Q(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_20\,
Q => Q(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_19\,
Q => Q(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_18\,
Q => Q(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_17\,
Q => Q(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_16\,
Q => Q(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_15\,
Q => Q(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_60\,
Q => Q(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_14\,
Q => Q(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_13\,
Q => Q(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_12\,
Q => Q(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_11\,
Q => Q(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_10\,
Q => Q(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_9\,
Q => Q(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_8\,
Q => Q(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_7\,
Q => Q(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_6\,
Q => Q(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_5\,
Q => Q(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_59\,
Q => Q(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_4\,
Q => Q(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_3\,
Q => Q(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_2\,
Q => Q(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_1\,
Q => Q(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_0\,
Q => Q(64),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_58\,
Q => Q(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_57\,
Q => Q(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_56\,
Q => Q(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => E(0),
D => \gdm.dm_gen.dm_n_55\,
Q => Q(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_memory_73 is
port (
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_memory_73 : entity is "memory";
end bd_auto_cc_0_memory_73;
architecture STRUCTURE of bd_auto_cc_0_memory_73 is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_39\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_40\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_41\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_42\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_43\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_44\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_45\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_46\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_47\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_48\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_49\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_50\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_51\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_52\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_53\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_54\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_55\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_56\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_57\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_58\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_59\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_60\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_61\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_62\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_63\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_64\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.bd_auto_cc_0_dmem_81
port map (
E(0) => E(0),
I123(64 downto 0) => I123(64 downto 0),
Q(64) => \gdm.dm_gen.dm_n_0\,
Q(63) => \gdm.dm_gen.dm_n_1\,
Q(62) => \gdm.dm_gen.dm_n_2\,
Q(61) => \gdm.dm_gen.dm_n_3\,
Q(60) => \gdm.dm_gen.dm_n_4\,
Q(59) => \gdm.dm_gen.dm_n_5\,
Q(58) => \gdm.dm_gen.dm_n_6\,
Q(57) => \gdm.dm_gen.dm_n_7\,
Q(56) => \gdm.dm_gen.dm_n_8\,
Q(55) => \gdm.dm_gen.dm_n_9\,
Q(54) => \gdm.dm_gen.dm_n_10\,
Q(53) => \gdm.dm_gen.dm_n_11\,
Q(52) => \gdm.dm_gen.dm_n_12\,
Q(51) => \gdm.dm_gen.dm_n_13\,
Q(50) => \gdm.dm_gen.dm_n_14\,
Q(49) => \gdm.dm_gen.dm_n_15\,
Q(48) => \gdm.dm_gen.dm_n_16\,
Q(47) => \gdm.dm_gen.dm_n_17\,
Q(46) => \gdm.dm_gen.dm_n_18\,
Q(45) => \gdm.dm_gen.dm_n_19\,
Q(44) => \gdm.dm_gen.dm_n_20\,
Q(43) => \gdm.dm_gen.dm_n_21\,
Q(42) => \gdm.dm_gen.dm_n_22\,
Q(41) => \gdm.dm_gen.dm_n_23\,
Q(40) => \gdm.dm_gen.dm_n_24\,
Q(39) => \gdm.dm_gen.dm_n_25\,
Q(38) => \gdm.dm_gen.dm_n_26\,
Q(37) => \gdm.dm_gen.dm_n_27\,
Q(36) => \gdm.dm_gen.dm_n_28\,
Q(35) => \gdm.dm_gen.dm_n_29\,
Q(34) => \gdm.dm_gen.dm_n_30\,
Q(33) => \gdm.dm_gen.dm_n_31\,
Q(32) => \gdm.dm_gen.dm_n_32\,
Q(31) => \gdm.dm_gen.dm_n_33\,
Q(30) => \gdm.dm_gen.dm_n_34\,
Q(29) => \gdm.dm_gen.dm_n_35\,
Q(28) => \gdm.dm_gen.dm_n_36\,
Q(27) => \gdm.dm_gen.dm_n_37\,
Q(26) => \gdm.dm_gen.dm_n_38\,
Q(25) => \gdm.dm_gen.dm_n_39\,
Q(24) => \gdm.dm_gen.dm_n_40\,
Q(23) => \gdm.dm_gen.dm_n_41\,
Q(22) => \gdm.dm_gen.dm_n_42\,
Q(21) => \gdm.dm_gen.dm_n_43\,
Q(20) => \gdm.dm_gen.dm_n_44\,
Q(19) => \gdm.dm_gen.dm_n_45\,
Q(18) => \gdm.dm_gen.dm_n_46\,
Q(17) => \gdm.dm_gen.dm_n_47\,
Q(16) => \gdm.dm_gen.dm_n_48\,
Q(15) => \gdm.dm_gen.dm_n_49\,
Q(14) => \gdm.dm_gen.dm_n_50\,
Q(13) => \gdm.dm_gen.dm_n_51\,
Q(12) => \gdm.dm_gen.dm_n_52\,
Q(11) => \gdm.dm_gen.dm_n_53\,
Q(10) => \gdm.dm_gen.dm_n_54\,
Q(9) => \gdm.dm_gen.dm_n_55\,
Q(8) => \gdm.dm_gen.dm_n_56\,
Q(7) => \gdm.dm_gen.dm_n_57\,
Q(6) => \gdm.dm_gen.dm_n_58\,
Q(5) => \gdm.dm_gen.dm_n_59\,
Q(4) => \gdm.dm_gen.dm_n_60\,
Q(3) => \gdm.dm_gen.dm_n_61\,
Q(2) => \gdm.dm_gen.dm_n_62\,
Q(1) => \gdm.dm_gen.dm_n_63\,
Q(0) => \gdm.dm_gen.dm_n_64\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_64\,
Q => \m_axi_arid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_54\,
Q => \m_axi_arid[3]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_53\,
Q => \m_axi_arid[3]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_52\,
Q => \m_axi_arid[3]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_51\,
Q => \m_axi_arid[3]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_50\,
Q => \m_axi_arid[3]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_49\,
Q => \m_axi_arid[3]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_48\,
Q => \m_axi_arid[3]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_47\,
Q => \m_axi_arid[3]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_46\,
Q => \m_axi_arid[3]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_45\,
Q => \m_axi_arid[3]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_63\,
Q => \m_axi_arid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_44\,
Q => \m_axi_arid[3]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_43\,
Q => \m_axi_arid[3]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_42\,
Q => \m_axi_arid[3]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_41\,
Q => \m_axi_arid[3]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_40\,
Q => \m_axi_arid[3]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_39\,
Q => \m_axi_arid[3]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \m_axi_arid[3]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \m_axi_arid[3]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_arid[3]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_arid[3]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_62\,
Q => \m_axi_arid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_arid[3]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_arid[3]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_arid[3]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_arid[3]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_arid[3]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_arid[3]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_arid[3]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_arid[3]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_arid[3]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[39]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_arid[3]\(39),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_61\,
Q => \m_axi_arid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[40]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_arid[3]\(40),
R => '0'
);
\goreg_dm.dout_i_reg[41]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_arid[3]\(41),
R => '0'
);
\goreg_dm.dout_i_reg[42]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_arid[3]\(42),
R => '0'
);
\goreg_dm.dout_i_reg[43]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_arid[3]\(43),
R => '0'
);
\goreg_dm.dout_i_reg[44]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_arid[3]\(44),
R => '0'
);
\goreg_dm.dout_i_reg[45]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_arid[3]\(45),
R => '0'
);
\goreg_dm.dout_i_reg[46]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_arid[3]\(46),
R => '0'
);
\goreg_dm.dout_i_reg[47]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_arid[3]\(47),
R => '0'
);
\goreg_dm.dout_i_reg[48]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_arid[3]\(48),
R => '0'
);
\goreg_dm.dout_i_reg[49]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_arid[3]\(49),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_60\,
Q => \m_axi_arid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[50]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_arid[3]\(50),
R => '0'
);
\goreg_dm.dout_i_reg[51]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_arid[3]\(51),
R => '0'
);
\goreg_dm.dout_i_reg[52]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_arid[3]\(52),
R => '0'
);
\goreg_dm.dout_i_reg[53]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_arid[3]\(53),
R => '0'
);
\goreg_dm.dout_i_reg[54]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_arid[3]\(54),
R => '0'
);
\goreg_dm.dout_i_reg[55]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_arid[3]\(55),
R => '0'
);
\goreg_dm.dout_i_reg[56]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_arid[3]\(56),
R => '0'
);
\goreg_dm.dout_i_reg[57]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_arid[3]\(57),
R => '0'
);
\goreg_dm.dout_i_reg[58]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_arid[3]\(58),
R => '0'
);
\goreg_dm.dout_i_reg[59]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_arid[3]\(59),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_59\,
Q => \m_axi_arid[3]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[60]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_arid[3]\(60),
R => '0'
);
\goreg_dm.dout_i_reg[61]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_arid[3]\(61),
R => '0'
);
\goreg_dm.dout_i_reg[62]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_arid[3]\(62),
R => '0'
);
\goreg_dm.dout_i_reg[63]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_arid[3]\(63),
R => '0'
);
\goreg_dm.dout_i_reg[64]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_arid[3]\(64),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_58\,
Q => \m_axi_arid[3]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_57\,
Q => \m_axi_arid[3]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_56\,
Q => \m_axi_arid[3]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_55\,
Q => \m_axi_arid[3]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_memory__parameterized0\ is
port (
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
s_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
m_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_memory__parameterized0\ : entity is "memory";
end \bd_auto_cc_0_memory__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_memory__parameterized0\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\bd_auto_cc_0_dmem__parameterized0\
port map (
E(0) => E(0),
I115(36 downto 0) => I115(36 downto 0),
Q(36) => \gdm.dm_gen.dm_n_0\,
Q(35) => \gdm.dm_gen.dm_n_1\,
Q(34) => \gdm.dm_gen.dm_n_2\,
Q(33) => \gdm.dm_gen.dm_n_3\,
Q(32) => \gdm.dm_gen.dm_n_4\,
Q(31) => \gdm.dm_gen.dm_n_5\,
Q(30) => \gdm.dm_gen.dm_n_6\,
Q(29) => \gdm.dm_gen.dm_n_7\,
Q(28) => \gdm.dm_gen.dm_n_8\,
Q(27) => \gdm.dm_gen.dm_n_9\,
Q(26) => \gdm.dm_gen.dm_n_10\,
Q(25) => \gdm.dm_gen.dm_n_11\,
Q(24) => \gdm.dm_gen.dm_n_12\,
Q(23) => \gdm.dm_gen.dm_n_13\,
Q(22) => \gdm.dm_gen.dm_n_14\,
Q(21) => \gdm.dm_gen.dm_n_15\,
Q(20) => \gdm.dm_gen.dm_n_16\,
Q(19) => \gdm.dm_gen.dm_n_17\,
Q(18) => \gdm.dm_gen.dm_n_18\,
Q(17) => \gdm.dm_gen.dm_n_19\,
Q(16) => \gdm.dm_gen.dm_n_20\,
Q(15) => \gdm.dm_gen.dm_n_21\,
Q(14) => \gdm.dm_gen.dm_n_22\,
Q(13) => \gdm.dm_gen.dm_n_23\,
Q(12) => \gdm.dm_gen.dm_n_24\,
Q(11) => \gdm.dm_gen.dm_n_25\,
Q(10) => \gdm.dm_gen.dm_n_26\,
Q(9) => \gdm.dm_gen.dm_n_27\,
Q(8) => \gdm.dm_gen.dm_n_28\,
Q(7) => \gdm.dm_gen.dm_n_29\,
Q(6) => \gdm.dm_gen.dm_n_30\,
Q(5) => \gdm.dm_gen.dm_n_31\,
Q(4) => \gdm.dm_gen.dm_n_32\,
Q(3) => \gdm.dm_gen.dm_n_33\,
Q(2) => \gdm.dm_gen.dm_n_34\,
Q(1) => \gdm.dm_gen.dm_n_35\,
Q(0) => \gdm.dm_gen.dm_n_36\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \m_axi_wdata[31]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \m_axi_wdata[31]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \m_axi_wdata[31]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \m_axi_wdata[31]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \m_axi_wdata[31]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \m_axi_wdata[31]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \m_axi_wdata[31]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \m_axi_wdata[31]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \m_axi_wdata[31]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \m_axi_wdata[31]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \m_axi_wdata[31]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \m_axi_wdata[31]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \m_axi_wdata[31]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \m_axi_wdata[31]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \m_axi_wdata[31]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \m_axi_wdata[31]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \m_axi_wdata[31]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \m_axi_wdata[31]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \m_axi_wdata[31]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \m_axi_wdata[31]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \m_axi_wdata[31]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \m_axi_wdata[31]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \m_axi_wdata[31]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \m_axi_wdata[31]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \m_axi_wdata[31]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \m_axi_wdata[31]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \m_axi_wdata[31]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \m_axi_wdata[31]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \m_axi_wdata[31]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \m_axi_wdata[31]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \m_axi_wdata[31]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \m_axi_wdata[31]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \m_axi_wdata[31]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \m_axi_wdata[31]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \m_axi_wdata[31]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \m_axi_wdata[31]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \m_axi_wdata[31]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_memory__parameterized1\ is
port (
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_memory__parameterized1\ : entity is "memory";
end \bd_auto_cc_0_memory__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_memory__parameterized1\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\bd_auto_cc_0_dmem__parameterized1\
port map (
E(0) => E(0),
Q(5) => \gdm.dm_gen.dm_n_0\,
Q(4) => \gdm.dm_gen.dm_n_1\,
Q(3) => \gdm.dm_gen.dm_n_2\,
Q(2) => \gdm.dm_gen.dm_n_3\,
Q(1) => \gdm.dm_gen.dm_n_4\,
Q(0) => \gdm.dm_gen.dm_n_5\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \s_axi_bid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \s_axi_bid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \s_axi_bid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \s_axi_bid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \s_axi_bid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \s_axi_bid[3]\(5),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_memory__parameterized2\ is
port (
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
m_aclk : in STD_LOGIC;
E : in STD_LOGIC_VECTOR ( 0 to 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
\gc0.count_d1_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d2_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 );
\gpregsm1.curr_fwft_state_reg[1]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
s_aclk : in STD_LOGIC;
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_memory__parameterized2\ : entity is "memory";
end \bd_auto_cc_0_memory__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_memory__parameterized2\ is
signal \gdm.dm_gen.dm_n_0\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_1\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_10\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_11\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_12\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_13\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_14\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_15\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_16\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_17\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_18\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_19\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_2\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_20\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_21\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_22\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_23\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_24\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_25\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_26\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_27\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_28\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_29\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_3\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_30\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_31\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_32\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_33\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_34\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_35\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_36\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_37\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_38\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_4\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_5\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_6\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_7\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_8\ : STD_LOGIC;
signal \gdm.dm_gen.dm_n_9\ : STD_LOGIC;
begin
\gdm.dm_gen.dm\: entity work.\bd_auto_cc_0_dmem__parameterized2\
port map (
E(0) => E(0),
I127(38 downto 0) => I127(38 downto 0),
Q(38) => \gdm.dm_gen.dm_n_0\,
Q(37) => \gdm.dm_gen.dm_n_1\,
Q(36) => \gdm.dm_gen.dm_n_2\,
Q(35) => \gdm.dm_gen.dm_n_3\,
Q(34) => \gdm.dm_gen.dm_n_4\,
Q(33) => \gdm.dm_gen.dm_n_5\,
Q(32) => \gdm.dm_gen.dm_n_6\,
Q(31) => \gdm.dm_gen.dm_n_7\,
Q(30) => \gdm.dm_gen.dm_n_8\,
Q(29) => \gdm.dm_gen.dm_n_9\,
Q(28) => \gdm.dm_gen.dm_n_10\,
Q(27) => \gdm.dm_gen.dm_n_11\,
Q(26) => \gdm.dm_gen.dm_n_12\,
Q(25) => \gdm.dm_gen.dm_n_13\,
Q(24) => \gdm.dm_gen.dm_n_14\,
Q(23) => \gdm.dm_gen.dm_n_15\,
Q(22) => \gdm.dm_gen.dm_n_16\,
Q(21) => \gdm.dm_gen.dm_n_17\,
Q(20) => \gdm.dm_gen.dm_n_18\,
Q(19) => \gdm.dm_gen.dm_n_19\,
Q(18) => \gdm.dm_gen.dm_n_20\,
Q(17) => \gdm.dm_gen.dm_n_21\,
Q(16) => \gdm.dm_gen.dm_n_22\,
Q(15) => \gdm.dm_gen.dm_n_23\,
Q(14) => \gdm.dm_gen.dm_n_24\,
Q(13) => \gdm.dm_gen.dm_n_25\,
Q(12) => \gdm.dm_gen.dm_n_26\,
Q(11) => \gdm.dm_gen.dm_n_27\,
Q(10) => \gdm.dm_gen.dm_n_28\,
Q(9) => \gdm.dm_gen.dm_n_29\,
Q(8) => \gdm.dm_gen.dm_n_30\,
Q(7) => \gdm.dm_gen.dm_n_31\,
Q(6) => \gdm.dm_gen.dm_n_32\,
Q(5) => \gdm.dm_gen.dm_n_33\,
Q(4) => \gdm.dm_gen.dm_n_34\,
Q(3) => \gdm.dm_gen.dm_n_35\,
Q(2) => \gdm.dm_gen.dm_n_36\,
Q(1) => \gdm.dm_gen.dm_n_37\,
Q(0) => \gdm.dm_gen.dm_n_38\,
\gc0.count_d1_reg[3]\(3 downto 0) => \gc0.count_d1_reg[3]\(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => \gpregsm1.curr_fwft_state_reg[1]\(0),
m_aclk => m_aclk,
s_aclk => s_aclk
);
\goreg_dm.dout_i_reg[0]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_38\,
Q => \s_axi_rid[3]\(0),
R => '0'
);
\goreg_dm.dout_i_reg[10]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_28\,
Q => \s_axi_rid[3]\(10),
R => '0'
);
\goreg_dm.dout_i_reg[11]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_27\,
Q => \s_axi_rid[3]\(11),
R => '0'
);
\goreg_dm.dout_i_reg[12]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_26\,
Q => \s_axi_rid[3]\(12),
R => '0'
);
\goreg_dm.dout_i_reg[13]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_25\,
Q => \s_axi_rid[3]\(13),
R => '0'
);
\goreg_dm.dout_i_reg[14]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_24\,
Q => \s_axi_rid[3]\(14),
R => '0'
);
\goreg_dm.dout_i_reg[15]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_23\,
Q => \s_axi_rid[3]\(15),
R => '0'
);
\goreg_dm.dout_i_reg[16]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_22\,
Q => \s_axi_rid[3]\(16),
R => '0'
);
\goreg_dm.dout_i_reg[17]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_21\,
Q => \s_axi_rid[3]\(17),
R => '0'
);
\goreg_dm.dout_i_reg[18]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_20\,
Q => \s_axi_rid[3]\(18),
R => '0'
);
\goreg_dm.dout_i_reg[19]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_19\,
Q => \s_axi_rid[3]\(19),
R => '0'
);
\goreg_dm.dout_i_reg[1]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_37\,
Q => \s_axi_rid[3]\(1),
R => '0'
);
\goreg_dm.dout_i_reg[20]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_18\,
Q => \s_axi_rid[3]\(20),
R => '0'
);
\goreg_dm.dout_i_reg[21]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_17\,
Q => \s_axi_rid[3]\(21),
R => '0'
);
\goreg_dm.dout_i_reg[22]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_16\,
Q => \s_axi_rid[3]\(22),
R => '0'
);
\goreg_dm.dout_i_reg[23]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_15\,
Q => \s_axi_rid[3]\(23),
R => '0'
);
\goreg_dm.dout_i_reg[24]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_14\,
Q => \s_axi_rid[3]\(24),
R => '0'
);
\goreg_dm.dout_i_reg[25]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_13\,
Q => \s_axi_rid[3]\(25),
R => '0'
);
\goreg_dm.dout_i_reg[26]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_12\,
Q => \s_axi_rid[3]\(26),
R => '0'
);
\goreg_dm.dout_i_reg[27]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_11\,
Q => \s_axi_rid[3]\(27),
R => '0'
);
\goreg_dm.dout_i_reg[28]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_10\,
Q => \s_axi_rid[3]\(28),
R => '0'
);
\goreg_dm.dout_i_reg[29]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_9\,
Q => \s_axi_rid[3]\(29),
R => '0'
);
\goreg_dm.dout_i_reg[2]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_36\,
Q => \s_axi_rid[3]\(2),
R => '0'
);
\goreg_dm.dout_i_reg[30]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_8\,
Q => \s_axi_rid[3]\(30),
R => '0'
);
\goreg_dm.dout_i_reg[31]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_7\,
Q => \s_axi_rid[3]\(31),
R => '0'
);
\goreg_dm.dout_i_reg[32]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_6\,
Q => \s_axi_rid[3]\(32),
R => '0'
);
\goreg_dm.dout_i_reg[33]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_5\,
Q => \s_axi_rid[3]\(33),
R => '0'
);
\goreg_dm.dout_i_reg[34]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_4\,
Q => \s_axi_rid[3]\(34),
R => '0'
);
\goreg_dm.dout_i_reg[35]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_3\,
Q => \s_axi_rid[3]\(35),
R => '0'
);
\goreg_dm.dout_i_reg[36]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_2\,
Q => \s_axi_rid[3]\(36),
R => '0'
);
\goreg_dm.dout_i_reg[37]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_1\,
Q => \s_axi_rid[3]\(37),
R => '0'
);
\goreg_dm.dout_i_reg[38]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_0\,
Q => \s_axi_rid[3]\(38),
R => '0'
);
\goreg_dm.dout_i_reg[3]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_35\,
Q => \s_axi_rid[3]\(3),
R => '0'
);
\goreg_dm.dout_i_reg[4]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_34\,
Q => \s_axi_rid[3]\(4),
R => '0'
);
\goreg_dm.dout_i_reg[5]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_33\,
Q => \s_axi_rid[3]\(5),
R => '0'
);
\goreg_dm.dout_i_reg[6]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_32\,
Q => \s_axi_rid[3]\(6),
R => '0'
);
\goreg_dm.dout_i_reg[7]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_31\,
Q => \s_axi_rid[3]\(7),
R => '0'
);
\goreg_dm.dout_i_reg[8]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_30\,
Q => \s_axi_rid[3]\(8),
R => '0'
);
\goreg_dm.dout_i_reg[9]\: unisim.vcomponents.FDRE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0),
D => \gdm.dm_gen.dm_n_29\,
Q => \s_axi_rid[3]\(9),
R => '0'
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[5]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
end bd_auto_cc_0_rd_logic;
architecture STRUCTURE of bd_auto_cc_0_rd_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[5]\(0) => \goreg_dm.dout_i_reg[5]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\,
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic_28 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
\gnxpm_cdc.rd_pntr_gc_reg[2]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_logic_28 : entity is "rd_logic";
end bd_auto_cc_0_rd_logic_28;
architecture STRUCTURE of bd_auto_cc_0_rd_logic_28 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft_39
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[64]\(0) => \goreg_dm.dout_i_reg[64]\(0),
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as_40
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr_41
port map (
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[2]\(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic_49 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[38]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rvalid : out STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_logic_49 : entity is "rd_logic";
end bd_auto_cc_0_rd_logic_49;
architecture STRUCTURE of bd_auto_cc_0_rd_logic_49 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft_60
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[38]\(0) => \goreg_dm.dout_i_reg[38]\(0),
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\,
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as_61
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out,
s_aclk => s_aclk
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr_62
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic_7 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[36]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_wready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_logic_7 : entity is "rd_logic";
end bd_auto_cc_0_rd_logic_7;
architecture STRUCTURE of bd_auto_cc_0_rd_logic_7 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft_18
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[36]\(0) => \goreg_dm.dout_i_reg[36]\(0),
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as_19
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr_20
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_rd_logic_71 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
E : out STD_LOGIC_VECTOR ( 0 to 0 );
\goreg_dm.dout_i_reg[64]\ : out STD_LOGIC_VECTOR ( 0 to 0 );
D : out STD_LOGIC_VECTOR ( 2 downto 0 );
\gnxpm_cdc.rd_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arready : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[2]\ : in STD_LOGIC;
\gnxpm_cdc.wr_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 3 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_rd_logic_71 : entity is "rd_logic";
end bd_auto_cc_0_rd_logic_71;
architecture STRUCTURE of bd_auto_cc_0_rd_logic_71 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \gr1.gr1_int.rfwft_n_0\ : STD_LOGIC;
signal p_2_out : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal rpntr_n_4 : STD_LOGIC;
begin
E(0) <= \^e\(0);
\gr1.gr1_int.rfwft\: entity work.bd_auto_cc_0_rd_fwft_84
port map (
E(0) => \^e\(0),
Q(0) => rd_pntr_plus1(3),
\gnxpm_cdc.wr_pntr_bin_reg[3]\(0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3),
\goreg_dm.dout_i_reg[64]\(0) => \goreg_dm.dout_i_reg[64]\(0),
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1 downto 0) => \out\(1 downto 0),
ram_empty_fb_i_reg => p_2_out,
ram_empty_i_reg => \gr1.gr1_int.rfwft_n_0\
);
\gras.rsts\: entity work.bd_auto_cc_0_rd_status_flags_as_85
port map (
\gc0.count_d1_reg[2]\ => rpntr_n_4,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\(0) => \out\(1),
\out\ => p_2_out
);
rpntr: entity work.bd_auto_cc_0_rd_bin_cntr_86
port map (
D(2 downto 0) => D(2 downto 0),
E(0) => \^e\(0),
Q(3) => rd_pntr_plus1(3),
Q(2 downto 0) => Q(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gnxpm_cdc.wr_pntr_bin_reg[2]\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\ => \gr1.gr1_int.rfwft_n_0\,
m_aclk => m_aclk,
\out\(0) => \out\(1),
ram_empty_i_reg => rpntr_n_4
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
end bd_auto_cc_0_reset_blk_ramfifo;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_1
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_2
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_3
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_4
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_5
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo_30 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_reset_blk_ramfifo_30 : entity is "reset_blk_ramfifo";
end bd_auto_cc_0_reset_blk_ramfifo_30;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo_30 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_31
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_32
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_33
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_34
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_35
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_36
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo_51 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : out STD_LOGIC;
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_reset_blk_ramfifo_51 : entity is "reset_blk_ramfifo";
end bd_auto_cc_0_reset_blk_ramfifo_51;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo_51 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ <= \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_52
port map (
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_53
port map (
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_54
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
\out\ => p_5_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_55
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
m_aclk => m_aclk,
\out\ => p_6_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_56
port map (
\Q_reg_reg[0]_0\ => p_7_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_57
port map (
\Q_reg_reg[0]_0\ => p_8_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_i_1\: unisim.vcomponents.LUT1
generic map(
INIT => X"1"
)
port map (
I0 => s_aresetn,
O => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => \^ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo_74 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_reset_blk_ramfifo_74 : entity is "reset_blk_ramfifo";
end bd_auto_cc_0_reset_blk_ramfifo_74;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo_74 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_75
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_76
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_77
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_78
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_79
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_80
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_reset_blk_ramfifo_9 is
port (
\out\ : out STD_LOGIC_VECTOR ( 1 downto 0 );
\gc0.count_reg[1]\ : out STD_LOGIC_VECTOR ( 2 downto 0 );
\grstd1.grst_full.grst_f.rst_d3_reg_0\ : out STD_LOGIC;
ram_full_fb_i_reg : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_reset_blk_ramfifo_9 : entity is "reset_blk_ramfifo";
end bd_auto_cc_0_reset_blk_ramfifo_9;
architecture STRUCTURE of bd_auto_cc_0_reset_blk_ramfifo_9 is
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\ : STD_LOGIC;
signal \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\ : STD_LOGIC;
signal p_5_out : STD_LOGIC;
signal p_6_out : STD_LOGIC;
signal p_7_out : STD_LOGIC;
signal p_8_out : STD_LOGIC;
signal rd_rst_asreg : STD_LOGIC;
signal rd_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH : boolean;
attribute DONT_TOUCH of rd_rst_reg : signal is std.standard.true;
signal rst_d1 : STD_LOGIC;
attribute async_reg : string;
attribute async_reg of rst_d1 : signal is "true";
attribute msgon : string;
attribute msgon of rst_d1 : signal is "true";
signal rst_d2 : STD_LOGIC;
attribute async_reg of rst_d2 : signal is "true";
attribute msgon of rst_d2 : signal is "true";
signal rst_d3 : STD_LOGIC;
attribute async_reg of rst_d3 : signal is "true";
attribute msgon of rst_d3 : signal is "true";
signal rst_rd_reg1 : STD_LOGIC;
attribute async_reg of rst_rd_reg1 : signal is "true";
attribute msgon of rst_rd_reg1 : signal is "true";
signal rst_rd_reg2 : STD_LOGIC;
attribute async_reg of rst_rd_reg2 : signal is "true";
attribute msgon of rst_rd_reg2 : signal is "true";
signal rst_wr_reg1 : STD_LOGIC;
attribute async_reg of rst_wr_reg1 : signal is "true";
attribute msgon of rst_wr_reg1 : signal is "true";
signal rst_wr_reg2 : STD_LOGIC;
attribute async_reg of rst_wr_reg2 : signal is "true";
attribute msgon of rst_wr_reg2 : signal is "true";
signal wr_rst_asreg : STD_LOGIC;
signal wr_rst_reg : STD_LOGIC_VECTOR ( 2 downto 0 );
attribute DONT_TOUCH of wr_rst_reg : signal is std.standard.true;
attribute ASYNC_REG_boolean : boolean;
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is std.standard.true;
attribute KEEP : string;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is std.standard.true;
attribute KEEP of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "yes";
attribute msgon of \grstd1.grst_full.grst_f.rst_d3_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal : string;
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\ : label is "no";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : label is "true";
attribute ASYNC_REG_boolean of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "yes";
attribute msgon of \ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\ : label is "true";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\ : label is "no";
attribute DONT_TOUCH of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is std.standard.true;
attribute KEEP of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "yes";
attribute equivalent_register_removal of \ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\ : label is "no";
begin
\gc0.count_reg[1]\(2 downto 0) <= rd_rst_reg(2 downto 0);
\grstd1.grst_full.grst_f.rst_d3_reg_0\ <= rst_d2;
\out\(1 downto 0) <= wr_rst_reg(1 downto 0);
ram_full_fb_i_reg <= rst_d3;
\grstd1.grst_full.grst_f.rst_d1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => rst_wr_reg2,
Q => rst_d1
);
\grstd1.grst_full.grst_f.rst_d2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d1,
PRE => rst_wr_reg2,
Q => rst_d2
);
\grstd1.grst_full.grst_f.rst_d3_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => rst_d2,
PRE => rst_wr_reg2,
Q => rst_d3
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_10
port map (
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[1].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_11
port map (
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_12
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_7_out,
in0(0) => rd_rst_asreg,
m_aclk => m_aclk,
\out\ => p_5_out
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_13
port map (
AS(0) => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
\Q_reg_reg[0]_0\ => p_8_out,
in0(0) => wr_rst_asreg,
\out\ => p_6_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].rrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_14
port map (
\Q_reg_reg[0]_0\ => p_7_out,
m_aclk => m_aclk
);
\ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[3].wrst_inst\: entity work.bd_auto_cc_0_synchronizer_ff_15
port map (
\Q_reg_reg[0]_0\ => p_8_out,
s_aclk => s_aclk
);
\ngwrdrst.grst.g7serrst.rd_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
PRE => rst_rd_reg2,
Q => rd_rst_asreg
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].rrst_inst_n_1\,
Q => rd_rst_reg(2)
);
\ngwrdrst.grst.g7serrst.rst_rd_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_rd_reg1
);
\ngwrdrst.grst.g7serrst.rst_rd_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => m_aclk,
CE => '1',
D => rst_rd_reg1,
PRE => inverted_reset,
Q => rst_rd_reg2
);
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => inverted_reset,
Q => rst_wr_reg1
);
\ngwrdrst.grst.g7serrst.rst_wr_reg2_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '0'
)
port map (
C => s_aclk,
CE => '1',
D => rst_wr_reg1,
PRE => inverted_reset,
Q => rst_wr_reg2
);
\ngwrdrst.grst.g7serrst.wr_rst_asreg_reg\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
PRE => rst_wr_reg2,
Q => wr_rst_asreg
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[0]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(0)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[1]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(1)
);
\ngwrdrst.grst.g7serrst.wr_rst_reg_reg[2]\: unisim.vcomponents.FDPE
generic map(
INIT => '1'
)
port map (
C => s_aclk,
CE => '1',
D => '0',
PRE => \ngwrdrst.grst.g7serrst.gwrrd_rst_sync_stage[2].wrst_inst_n_1\,
Q => wr_rst_reg(2)
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
end bd_auto_cc_0_wr_logic;
architecture STRUCTURE of bd_auto_cc_0_wr_logic is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic_29 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_logic_29 : entity is "wr_logic";
end bd_auto_cc_0_wr_logic_29;
architecture STRUCTURE of bd_auto_cc_0_wr_logic_29 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as_37
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr_38
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic_50 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
m_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_logic_50 : entity is "wr_logic";
end bd_auto_cc_0_wr_logic_50;
architecture STRUCTURE of bd_auto_cc_0_wr_logic_50 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as_58
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr_59
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
m_aclk => m_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic_72 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_logic_72 : entity is "wr_logic";
end bd_auto_cc_0_wr_logic_72;
architecture STRUCTURE of bd_auto_cc_0_wr_logic_72 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as_82
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr_83
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_wr_logic_8 is
port (
Q : out STD_LOGIC_VECTOR ( 2 downto 0 );
ram_full_fb_i_reg : out STD_LOGIC;
E : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wready : out STD_LOGIC;
\gic0.gc0.count_d2_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gnxpm_cdc.wr_pntr_gc_reg[3]\ : out STD_LOGIC_VECTOR ( 3 downto 0 );
\gic0.gc0.count_d1_reg[3]\ : in STD_LOGIC;
s_aclk : in STD_LOGIC;
\out\ : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
\gnxpm_cdc.rd_pntr_bin_reg[3]\ : in STD_LOGIC_VECTOR ( 0 to 0 );
AR : in STD_LOGIC_VECTOR ( 0 to 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_wr_logic_8 : entity is "wr_logic";
end bd_auto_cc_0_wr_logic_8;
architecture STRUCTURE of bd_auto_cc_0_wr_logic_8 is
signal \^e\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 3 to 3 );
begin
E(0) <= \^e\(0);
\gwas.wsts\: entity work.bd_auto_cc_0_wr_status_flags_as_16
port map (
E(0) => \^e\(0),
Q(0) => wr_pntr_plus2(3),
\gic0.gc0.count_d1_reg[3]\ => \gic0.gc0.count_d1_reg[3]\,
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => \gnxpm_cdc.rd_pntr_bin_reg[3]\(0),
\out\ => \out\,
ram_full_fb_i_reg_0 => ram_full_fb_i_reg,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
wpntr: entity work.bd_auto_cc_0_wr_bin_cntr_17
port map (
AR(0) => AR(0),
E(0) => \^e\(0),
Q(3) => wr_pntr_plus2(3),
Q(2 downto 0) => Q(2 downto 0),
\gic0.gc0.count_d2_reg[3]_0\(3 downto 0) => \gic0.gc0.count_d2_reg[3]\(3 downto 0),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => \gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0),
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_ramfifo is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end bd_auto_cc_0_fifo_generator_ramfifo;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_ramfifo is
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal gray2bin : STD_LOGIC_VECTOR ( 0 to 0 );
signal p_0_out_0 : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC;
signal p_23_out_1 : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs_27
port map (
AR(0) => wr_rst_i(0),
D(0) => gray2bin(0),
Q(3 downto 0) => p_22_out(3 downto 0),
\gc0.count_d1_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gc0.count_d1_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gc0.count_d1_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gc0.count_d1_reg[3]\(0) => p_0_out_0(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_23_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out_1(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => gray2bin(0)
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic_28
port map (
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[2]\(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
\gnxpm_cdc.rd_pntr_gc_reg[2]\(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[64]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic_29
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out_1(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gntv_or_sync_fifo.mem\: entity work.bd_auto_cc_0_memory
port map (
DI(64 downto 0) => DI(64 downto 0),
E(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
Q(64 downto 0) => Q(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out_0(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
ram_full_fb_i_reg(0) => p_18_out,
s_aclk => s_aclk
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo_30
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_23_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_ramfifo_69 is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_fifo_generator_ramfifo_69 : entity is "fifo_generator_ramfifo";
end bd_auto_cc_0_fifo_generator_ramfifo_69;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_ramfifo_69 is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rach : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs_70
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rach,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic_71
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[64]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic_72
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gntv_or_sync_fifo.mem\: entity work.bd_auto_cc_0_memory_73
port map (
E(0) => p_18_out,
I123(64 downto 0) => I123(64 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo_74
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rach,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\ : entity is "fifo_generator_ramfifo";
end \bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_9\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_15_out : STD_LOGIC;
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs_6
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_22_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d1_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => p_15_out,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_9\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic_7
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[36]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
m_aclk => m_aclk,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0)
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic_8
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_9\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gntv_or_sync_fifo.mem\: entity work.\bd_auto_cc_0_memory__parameterized0\
port map (
E(0) => p_18_out,
I115(36 downto 0) => I115(36 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo_9
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => p_15_out,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\ : entity is "fifo_generator_ramfifo";
end \bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_wrch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_wrch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[5]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_bready => m_axi_bready,
m_axi_bvalid => m_axi_bvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\bd_auto_cc_0_memory__parameterized1\
port map (
E(0) => p_18_out,
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0)
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_wrch,
s_aclk => s_aclk
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
port (
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\ : entity is "fifo_generator_ramfifo";
end \bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\ is
signal \gntv_or_sync_fifo.gcx.clkx/_n_0\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gcx.clkx_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_4\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_5\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_6\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.rd_n_7\ : STD_LOGIC;
signal \gntv_or_sync_fifo.gl0.wr_n_3\ : STD_LOGIC;
signal p_0_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_12_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_13_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_18_out : STD_LOGIC;
signal p_22_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal p_23_out : STD_LOGIC_VECTOR ( 3 to 3 );
signal p_7_out : STD_LOGIC_VECTOR ( 3 downto 0 );
signal ram_rd_en_i : STD_LOGIC;
signal rd_pntr_plus1 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rd_rst_i : STD_LOGIC_VECTOR ( 2 downto 0 );
signal rst_full_ff_i : STD_LOGIC;
signal wr_pntr_plus2 : STD_LOGIC_VECTOR ( 2 downto 0 );
signal wr_rst_busy_rdch : STD_LOGIC;
signal wr_rst_i : STD_LOGIC_VECTOR ( 1 downto 0 );
begin
\gntv_or_sync_fifo.gcx.clkx\: entity work.bd_auto_cc_0_clk_x_pntrs_48
port map (
AR(0) => wr_rst_i(0),
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
Q(3 downto 0) => p_13_out(3 downto 0),
\Q_reg_reg[1]\(0) => \gntv_or_sync_fifo.gcx.clkx/_n_0\,
\gc0.count_d1_reg[3]\(0) => p_0_out(3),
\gc0.count_reg[2]\(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gic0.gc0.count_reg[2]\(2 downto 0) => wr_pntr_plus2(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg\ => wr_rst_busy_rdch,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[1]\(0) => rd_rst_i(1),
\out\(3 downto 0) => p_7_out(3 downto 0),
ram_empty_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_6\,
ram_empty_i_reg_0(3 downto 0) => p_22_out(3 downto 0),
ram_full_fb_i_reg => \gntv_or_sync_fifo.gcx.clkx_n_4\,
ram_full_fb_i_reg_0(0) => p_23_out(3),
ram_full_fb_i_reg_1 => \gntv_or_sync_fifo.gl0.wr_n_3\,
s_aclk => s_aclk
);
\gntv_or_sync_fifo.gcx.clkx/\: unisim.vcomponents.LUT4
generic map(
INIT => X"6996"
)
port map (
I0 => p_7_out(1),
I1 => p_7_out(0),
I2 => p_7_out(3),
I3 => p_7_out(2),
O => \gntv_or_sync_fifo.gcx.clkx/_n_0\
);
\gntv_or_sync_fifo.gl0.rd\: entity work.bd_auto_cc_0_rd_logic_49
port map (
D(2) => \gntv_or_sync_fifo.gl0.rd_n_5\,
D(1) => \gntv_or_sync_fifo.gl0.rd_n_6\,
D(0) => \gntv_or_sync_fifo.gl0.rd_n_7\,
E(0) => ram_rd_en_i,
Q(2 downto 0) => rd_pntr_plus1(2 downto 0),
\gnxpm_cdc.rd_pntr_gc_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gnxpm_cdc.wr_pntr_bin_reg[2]\ => \gntv_or_sync_fifo.gcx.clkx_n_6\,
\gnxpm_cdc.wr_pntr_bin_reg[3]\(3 downto 0) => p_22_out(3 downto 0),
\goreg_dm.dout_i_reg[38]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
\out\(1) => rd_rst_i(2),
\out\(0) => rd_rst_i(0),
s_aclk => s_aclk,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gntv_or_sync_fifo.gl0.wr\: entity work.bd_auto_cc_0_wr_logic_50
port map (
AR(0) => wr_rst_i(1),
E(0) => p_18_out,
Q(2 downto 0) => wr_pntr_plus2(2 downto 0),
\gic0.gc0.count_d1_reg[3]\ => \gntv_or_sync_fifo.gcx.clkx_n_4\,
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_13_out(3 downto 0),
\gnxpm_cdc.rd_pntr_bin_reg[3]\(0) => p_23_out(3),
\gnxpm_cdc.wr_pntr_gc_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\out\ => rst_full_ff_i,
ram_full_fb_i_reg => \gntv_or_sync_fifo.gl0.wr_n_3\
);
\gntv_or_sync_fifo.mem\: entity work.\bd_auto_cc_0_memory__parameterized2\
port map (
E(0) => p_18_out,
I127(38 downto 0) => I127(38 downto 0),
\gc0.count_d1_reg[3]\(3 downto 0) => p_0_out(3 downto 0),
\gic0.gc0.count_d2_reg[3]\(3 downto 0) => p_12_out(3 downto 0),
\gpregsm1.curr_fwft_state_reg[1]\(0) => ram_rd_en_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rd_rst_reg_reg[0]\(0) => \gntv_or_sync_fifo.gl0.rd_n_4\,
s_aclk => s_aclk,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0)
);
rstblk: entity work.bd_auto_cc_0_reset_blk_ramfifo_51
port map (
\gc0.count_reg[1]\(2 downto 0) => rd_rst_i(2 downto 0),
\grstd1.grst_full.grst_f.rst_d3_reg_0\ => rst_full_ff_i,
m_aclk => m_aclk,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg_0\ => \ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\,
\out\(1 downto 0) => wr_rst_i(1 downto 0),
ram_full_fb_i_reg => wr_rst_busy_rdch,
s_aclk => s_aclk,
s_aresetn => s_aresetn
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_top is
port (
s_axi_arready : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
end bd_auto_cc_0_fifo_generator_top;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_top is
begin
\grf.rf\: entity work.bd_auto_cc_0_fifo_generator_ramfifo_69
port map (
I123(64 downto 0) => I123(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_top_0 is
port (
s_axi_awready : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_awready : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR ( 64 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of bd_auto_cc_0_fifo_generator_top_0 : entity is "fifo_generator_top";
end bd_auto_cc_0_fifo_generator_top_0;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_top_0 is
begin
\grf.rf\: entity work.bd_auto_cc_0_fifo_generator_ramfifo
port map (
DI(64 downto 0) => DI(64 downto 0),
Q(64 downto 0) => Q(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_top__parameterized0\ is
port (
s_axi_wready : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_top__parameterized0\ : entity is "fifo_generator_top";
end \bd_auto_cc_0_fifo_generator_top__parameterized0\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_top__parameterized0\ is
begin
\grf.rf\: entity work.\bd_auto_cc_0_fifo_generator_ramfifo__parameterized0\
port map (
I115(36 downto 0) => I115(36 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_top__parameterized1\ is
port (
s_axi_bvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
inverted_reset : in STD_LOGIC;
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_top__parameterized1\ : entity is "fifo_generator_top";
end \bd_auto_cc_0_fifo_generator_top__parameterized1\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_top__parameterized1\ is
begin
\grf.rf\: entity work.\bd_auto_cc_0_fifo_generator_ramfifo__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity \bd_auto_cc_0_fifo_generator_top__parameterized2\ is
port (
inverted_reset : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_aclk : in STD_LOGIC;
m_aclk : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 )
);
attribute ORIG_REF_NAME : string;
attribute ORIG_REF_NAME of \bd_auto_cc_0_fifo_generator_top__parameterized2\ : entity is "fifo_generator_top";
end \bd_auto_cc_0_fifo_generator_top__parameterized2\;
architecture STRUCTURE of \bd_auto_cc_0_fifo_generator_top__parameterized2\ is
begin
\grf.rf\: entity work.\bd_auto_cc_0_fifo_generator_ramfifo__parameterized2\
port map (
I127(38 downto 0) => I127(38 downto 0),
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\ngwrdrst.grst.g7serrst.rst_wr_reg1_reg\ => inverted_reset,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_v13_1_3_synth is
port (
Q : out STD_LOGIC_VECTOR ( 64 downto 0 );
\m_axi_wdata[31]\ : out STD_LOGIC_VECTOR ( 36 downto 0 );
\s_axi_bid[3]\ : out STD_LOGIC_VECTOR ( 5 downto 0 );
\m_axi_arid[3]\ : out STD_LOGIC_VECTOR ( 64 downto 0 );
\s_axi_rid[3]\ : out STD_LOGIC_VECTOR ( 38 downto 0 );
s_axi_awready : out STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bvalid : out STD_LOGIC;
m_axi_awvalid : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
m_axi_arvalid : out STD_LOGIC;
m_axi_rready : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
I115 : in STD_LOGIC_VECTOR ( 36 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
I123 : in STD_LOGIC_VECTOR ( 64 downto 0 );
I127 : in STD_LOGIC_VECTOR ( 38 downto 0 );
DI : in STD_LOGIC_VECTOR ( 64 downto 0 );
m_axi_awready : in STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bvalid : in STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
s_axi_awvalid : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arvalid : in STD_LOGIC;
s_axi_rready : in STD_LOGIC;
s_aresetn : in STD_LOGIC
);
end bd_auto_cc_0_fifo_generator_v13_1_3_synth;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_v13_1_3_synth is
signal inverted_reset : STD_LOGIC;
begin
\gaxi_full_lite.gread_ch.grach2.axi_rach\: entity work.bd_auto_cc_0_fifo_generator_top
port map (
I123(64 downto 0) => I123(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 0) => \m_axi_arid[3]\(64 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
s_aclk => s_aclk,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid
);
\gaxi_full_lite.gread_ch.grdch2.axi_rdch\: entity work.\bd_auto_cc_0_fifo_generator_top__parameterized2\
port map (
I127(38 downto 0) => I127(38 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
\s_axi_rid[3]\(38 downto 0) => \s_axi_rid[3]\(38 downto 0),
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid
);
\gaxi_full_lite.gwrite_ch.gwach2.axi_wach\: entity work.bd_auto_cc_0_fifo_generator_top_0
port map (
DI(64 downto 0) => DI(64 downto 0),
Q(64 downto 0) => Q(64 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
s_aclk => s_aclk,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid
);
\gaxi_full_lite.gwrite_ch.gwdch2.axi_wdch\: entity work.\bd_auto_cc_0_fifo_generator_top__parameterized0\
port map (
I115(36 downto 0) => I115(36 downto 0),
inverted_reset => inverted_reset,
m_aclk => m_aclk,
\m_axi_wdata[31]\(36 downto 0) => \m_axi_wdata[31]\(36 downto 0),
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
\gaxi_full_lite.gwrite_ch.gwrch2.axi_wrch\: entity work.\bd_auto_cc_0_fifo_generator_top__parameterized1\
port map (
inverted_reset => inverted_reset,
m_aclk => m_aclk,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
s_aclk => s_aclk,
\s_axi_bid[3]\(5 downto 0) => \s_axi_bid[3]\(5 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_fifo_generator_v13_1_3 is
port (
backup : in STD_LOGIC;
backup_marker : in STD_LOGIC;
clk : in STD_LOGIC;
rst : in STD_LOGIC;
srst : in STD_LOGIC;
wr_clk : in STD_LOGIC;
wr_rst : in STD_LOGIC;
rd_clk : in STD_LOGIC;
rd_rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR ( 17 downto 0 );
wr_en : in STD_LOGIC;
rd_en : in STD_LOGIC;
prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_empty_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_assert : in STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full_thresh_negate : in STD_LOGIC_VECTOR ( 9 downto 0 );
int_clk : in STD_LOGIC;
injectdbiterr : in STD_LOGIC;
injectsbiterr : in STD_LOGIC;
sleep : in STD_LOGIC;
dout : out STD_LOGIC_VECTOR ( 17 downto 0 );
full : out STD_LOGIC;
almost_full : out STD_LOGIC;
wr_ack : out STD_LOGIC;
overflow : out STD_LOGIC;
empty : out STD_LOGIC;
almost_empty : out STD_LOGIC;
valid : out STD_LOGIC;
underflow : out STD_LOGIC;
data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
rd_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
wr_data_count : out STD_LOGIC_VECTOR ( 9 downto 0 );
prog_full : out STD_LOGIC;
prog_empty : out STD_LOGIC;
sbiterr : out STD_LOGIC;
dbiterr : out STD_LOGIC;
wr_rst_busy : out STD_LOGIC;
rd_rst_busy : out STD_LOGIC;
m_aclk : in STD_LOGIC;
s_aclk : in STD_LOGIC;
s_aresetn : in STD_LOGIC;
m_aclk_en : in STD_LOGIC;
s_aclk_en : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC;
s_axis_tvalid : in STD_LOGIC;
s_axis_tready : out STD_LOGIC;
s_axis_tdata : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axis_tstrb : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tkeep : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tlast : in STD_LOGIC;
s_axis_tid : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tdest : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axis_tuser : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axis_tvalid : out STD_LOGIC;
m_axis_tready : in STD_LOGIC;
m_axis_tdata : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axis_tstrb : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tkeep : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tlast : out STD_LOGIC;
m_axis_tid : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tdest : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axis_tuser : out STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_injectsbiterr : in STD_LOGIC;
axi_aw_injectdbiterr : in STD_LOGIC;
axi_aw_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_aw_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_aw_sbiterr : out STD_LOGIC;
axi_aw_dbiterr : out STD_LOGIC;
axi_aw_overflow : out STD_LOGIC;
axi_aw_underflow : out STD_LOGIC;
axi_aw_prog_full : out STD_LOGIC;
axi_aw_prog_empty : out STD_LOGIC;
axi_w_injectsbiterr : in STD_LOGIC;
axi_w_injectdbiterr : in STD_LOGIC;
axi_w_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_w_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_w_sbiterr : out STD_LOGIC;
axi_w_dbiterr : out STD_LOGIC;
axi_w_overflow : out STD_LOGIC;
axi_w_underflow : out STD_LOGIC;
axi_w_prog_full : out STD_LOGIC;
axi_w_prog_empty : out STD_LOGIC;
axi_b_injectsbiterr : in STD_LOGIC;
axi_b_injectdbiterr : in STD_LOGIC;
axi_b_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_b_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_b_sbiterr : out STD_LOGIC;
axi_b_dbiterr : out STD_LOGIC;
axi_b_overflow : out STD_LOGIC;
axi_b_underflow : out STD_LOGIC;
axi_b_prog_full : out STD_LOGIC;
axi_b_prog_empty : out STD_LOGIC;
axi_ar_injectsbiterr : in STD_LOGIC;
axi_ar_injectdbiterr : in STD_LOGIC;
axi_ar_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_ar_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_ar_sbiterr : out STD_LOGIC;
axi_ar_dbiterr : out STD_LOGIC;
axi_ar_overflow : out STD_LOGIC;
axi_ar_underflow : out STD_LOGIC;
axi_ar_prog_full : out STD_LOGIC;
axi_ar_prog_empty : out STD_LOGIC;
axi_r_injectsbiterr : in STD_LOGIC;
axi_r_injectdbiterr : in STD_LOGIC;
axi_r_prog_full_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_prog_empty_thresh : in STD_LOGIC_VECTOR ( 3 downto 0 );
axi_r_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_wr_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_rd_data_count : out STD_LOGIC_VECTOR ( 4 downto 0 );
axi_r_sbiterr : out STD_LOGIC;
axi_r_dbiterr : out STD_LOGIC;
axi_r_overflow : out STD_LOGIC;
axi_r_underflow : out STD_LOGIC;
axi_r_prog_full : out STD_LOGIC;
axi_r_prog_empty : out STD_LOGIC;
axis_injectsbiterr : in STD_LOGIC;
axis_injectdbiterr : in STD_LOGIC;
axis_prog_full_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_prog_empty_thresh : in STD_LOGIC_VECTOR ( 9 downto 0 );
axis_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_wr_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_rd_data_count : out STD_LOGIC_VECTOR ( 10 downto 0 );
axis_sbiterr : out STD_LOGIC;
axis_dbiterr : out STD_LOGIC;
axis_overflow : out STD_LOGIC;
axis_underflow : out STD_LOGIC;
axis_prog_full : out STD_LOGIC;
axis_prog_empty : out STD_LOGIC
);
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 65;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 39;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 65;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 37;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 6;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_FAMILY : string;
attribute C_FAMILY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of bd_auto_cc_0_fifo_generator_v13_1_3 : entity is 1;
end bd_auto_cc_0_fifo_generator_v13_1_3;
architecture STRUCTURE of bd_auto_cc_0_fifo_generator_v13_1_3 is
signal \<const0>\ : STD_LOGIC;
begin
almost_empty <= \<const0>\;
almost_full <= \<const0>\;
axi_ar_data_count(4) <= \<const0>\;
axi_ar_data_count(3) <= \<const0>\;
axi_ar_data_count(2) <= \<const0>\;
axi_ar_data_count(1) <= \<const0>\;
axi_ar_data_count(0) <= \<const0>\;
axi_ar_dbiterr <= \<const0>\;
axi_ar_overflow <= \<const0>\;
axi_ar_prog_empty <= \<const0>\;
axi_ar_prog_full <= \<const0>\;
axi_ar_rd_data_count(4) <= \<const0>\;
axi_ar_rd_data_count(3) <= \<const0>\;
axi_ar_rd_data_count(2) <= \<const0>\;
axi_ar_rd_data_count(1) <= \<const0>\;
axi_ar_rd_data_count(0) <= \<const0>\;
axi_ar_sbiterr <= \<const0>\;
axi_ar_underflow <= \<const0>\;
axi_ar_wr_data_count(4) <= \<const0>\;
axi_ar_wr_data_count(3) <= \<const0>\;
axi_ar_wr_data_count(2) <= \<const0>\;
axi_ar_wr_data_count(1) <= \<const0>\;
axi_ar_wr_data_count(0) <= \<const0>\;
axi_aw_data_count(4) <= \<const0>\;
axi_aw_data_count(3) <= \<const0>\;
axi_aw_data_count(2) <= \<const0>\;
axi_aw_data_count(1) <= \<const0>\;
axi_aw_data_count(0) <= \<const0>\;
axi_aw_dbiterr <= \<const0>\;
axi_aw_overflow <= \<const0>\;
axi_aw_prog_empty <= \<const0>\;
axi_aw_prog_full <= \<const0>\;
axi_aw_rd_data_count(4) <= \<const0>\;
axi_aw_rd_data_count(3) <= \<const0>\;
axi_aw_rd_data_count(2) <= \<const0>\;
axi_aw_rd_data_count(1) <= \<const0>\;
axi_aw_rd_data_count(0) <= \<const0>\;
axi_aw_sbiterr <= \<const0>\;
axi_aw_underflow <= \<const0>\;
axi_aw_wr_data_count(4) <= \<const0>\;
axi_aw_wr_data_count(3) <= \<const0>\;
axi_aw_wr_data_count(2) <= \<const0>\;
axi_aw_wr_data_count(1) <= \<const0>\;
axi_aw_wr_data_count(0) <= \<const0>\;
axi_b_data_count(4) <= \<const0>\;
axi_b_data_count(3) <= \<const0>\;
axi_b_data_count(2) <= \<const0>\;
axi_b_data_count(1) <= \<const0>\;
axi_b_data_count(0) <= \<const0>\;
axi_b_dbiterr <= \<const0>\;
axi_b_overflow <= \<const0>\;
axi_b_prog_empty <= \<const0>\;
axi_b_prog_full <= \<const0>\;
axi_b_rd_data_count(4) <= \<const0>\;
axi_b_rd_data_count(3) <= \<const0>\;
axi_b_rd_data_count(2) <= \<const0>\;
axi_b_rd_data_count(1) <= \<const0>\;
axi_b_rd_data_count(0) <= \<const0>\;
axi_b_sbiterr <= \<const0>\;
axi_b_underflow <= \<const0>\;
axi_b_wr_data_count(4) <= \<const0>\;
axi_b_wr_data_count(3) <= \<const0>\;
axi_b_wr_data_count(2) <= \<const0>\;
axi_b_wr_data_count(1) <= \<const0>\;
axi_b_wr_data_count(0) <= \<const0>\;
axi_r_data_count(4) <= \<const0>\;
axi_r_data_count(3) <= \<const0>\;
axi_r_data_count(2) <= \<const0>\;
axi_r_data_count(1) <= \<const0>\;
axi_r_data_count(0) <= \<const0>\;
axi_r_dbiterr <= \<const0>\;
axi_r_overflow <= \<const0>\;
axi_r_prog_empty <= \<const0>\;
axi_r_prog_full <= \<const0>\;
axi_r_rd_data_count(4) <= \<const0>\;
axi_r_rd_data_count(3) <= \<const0>\;
axi_r_rd_data_count(2) <= \<const0>\;
axi_r_rd_data_count(1) <= \<const0>\;
axi_r_rd_data_count(0) <= \<const0>\;
axi_r_sbiterr <= \<const0>\;
axi_r_underflow <= \<const0>\;
axi_r_wr_data_count(4) <= \<const0>\;
axi_r_wr_data_count(3) <= \<const0>\;
axi_r_wr_data_count(2) <= \<const0>\;
axi_r_wr_data_count(1) <= \<const0>\;
axi_r_wr_data_count(0) <= \<const0>\;
axi_w_data_count(4) <= \<const0>\;
axi_w_data_count(3) <= \<const0>\;
axi_w_data_count(2) <= \<const0>\;
axi_w_data_count(1) <= \<const0>\;
axi_w_data_count(0) <= \<const0>\;
axi_w_dbiterr <= \<const0>\;
axi_w_overflow <= \<const0>\;
axi_w_prog_empty <= \<const0>\;
axi_w_prog_full <= \<const0>\;
axi_w_rd_data_count(4) <= \<const0>\;
axi_w_rd_data_count(3) <= \<const0>\;
axi_w_rd_data_count(2) <= \<const0>\;
axi_w_rd_data_count(1) <= \<const0>\;
axi_w_rd_data_count(0) <= \<const0>\;
axi_w_sbiterr <= \<const0>\;
axi_w_underflow <= \<const0>\;
axi_w_wr_data_count(4) <= \<const0>\;
axi_w_wr_data_count(3) <= \<const0>\;
axi_w_wr_data_count(2) <= \<const0>\;
axi_w_wr_data_count(1) <= \<const0>\;
axi_w_wr_data_count(0) <= \<const0>\;
axis_data_count(10) <= \<const0>\;
axis_data_count(9) <= \<const0>\;
axis_data_count(8) <= \<const0>\;
axis_data_count(7) <= \<const0>\;
axis_data_count(6) <= \<const0>\;
axis_data_count(5) <= \<const0>\;
axis_data_count(4) <= \<const0>\;
axis_data_count(3) <= \<const0>\;
axis_data_count(2) <= \<const0>\;
axis_data_count(1) <= \<const0>\;
axis_data_count(0) <= \<const0>\;
axis_dbiterr <= \<const0>\;
axis_overflow <= \<const0>\;
axis_prog_empty <= \<const0>\;
axis_prog_full <= \<const0>\;
axis_rd_data_count(10) <= \<const0>\;
axis_rd_data_count(9) <= \<const0>\;
axis_rd_data_count(8) <= \<const0>\;
axis_rd_data_count(7) <= \<const0>\;
axis_rd_data_count(6) <= \<const0>\;
axis_rd_data_count(5) <= \<const0>\;
axis_rd_data_count(4) <= \<const0>\;
axis_rd_data_count(3) <= \<const0>\;
axis_rd_data_count(2) <= \<const0>\;
axis_rd_data_count(1) <= \<const0>\;
axis_rd_data_count(0) <= \<const0>\;
axis_sbiterr <= \<const0>\;
axis_underflow <= \<const0>\;
axis_wr_data_count(10) <= \<const0>\;
axis_wr_data_count(9) <= \<const0>\;
axis_wr_data_count(8) <= \<const0>\;
axis_wr_data_count(7) <= \<const0>\;
axis_wr_data_count(6) <= \<const0>\;
axis_wr_data_count(5) <= \<const0>\;
axis_wr_data_count(4) <= \<const0>\;
axis_wr_data_count(3) <= \<const0>\;
axis_wr_data_count(2) <= \<const0>\;
axis_wr_data_count(1) <= \<const0>\;
axis_wr_data_count(0) <= \<const0>\;
data_count(9) <= \<const0>\;
data_count(8) <= \<const0>\;
data_count(7) <= \<const0>\;
data_count(6) <= \<const0>\;
data_count(5) <= \<const0>\;
data_count(4) <= \<const0>\;
data_count(3) <= \<const0>\;
data_count(2) <= \<const0>\;
data_count(1) <= \<const0>\;
data_count(0) <= \<const0>\;
dbiterr <= \<const0>\;
dout(17) <= \<const0>\;
dout(16) <= \<const0>\;
dout(15) <= \<const0>\;
dout(14) <= \<const0>\;
dout(13) <= \<const0>\;
dout(12) <= \<const0>\;
dout(11) <= \<const0>\;
dout(10) <= \<const0>\;
dout(9) <= \<const0>\;
dout(8) <= \<const0>\;
dout(7) <= \<const0>\;
dout(6) <= \<const0>\;
dout(5) <= \<const0>\;
dout(4) <= \<const0>\;
dout(3) <= \<const0>\;
dout(2) <= \<const0>\;
dout(1) <= \<const0>\;
dout(0) <= \<const0>\;
empty <= \<const0>\;
full <= \<const0>\;
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
m_axis_tdata(7) <= \<const0>\;
m_axis_tdata(6) <= \<const0>\;
m_axis_tdata(5) <= \<const0>\;
m_axis_tdata(4) <= \<const0>\;
m_axis_tdata(3) <= \<const0>\;
m_axis_tdata(2) <= \<const0>\;
m_axis_tdata(1) <= \<const0>\;
m_axis_tdata(0) <= \<const0>\;
m_axis_tdest(0) <= \<const0>\;
m_axis_tid(0) <= \<const0>\;
m_axis_tkeep(0) <= \<const0>\;
m_axis_tlast <= \<const0>\;
m_axis_tstrb(0) <= \<const0>\;
m_axis_tuser(3) <= \<const0>\;
m_axis_tuser(2) <= \<const0>\;
m_axis_tuser(1) <= \<const0>\;
m_axis_tuser(0) <= \<const0>\;
m_axis_tvalid <= \<const0>\;
overflow <= \<const0>\;
prog_empty <= \<const0>\;
prog_full <= \<const0>\;
rd_data_count(9) <= \<const0>\;
rd_data_count(8) <= \<const0>\;
rd_data_count(7) <= \<const0>\;
rd_data_count(6) <= \<const0>\;
rd_data_count(5) <= \<const0>\;
rd_data_count(4) <= \<const0>\;
rd_data_count(3) <= \<const0>\;
rd_data_count(2) <= \<const0>\;
rd_data_count(1) <= \<const0>\;
rd_data_count(0) <= \<const0>\;
rd_rst_busy <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
s_axis_tready <= \<const0>\;
sbiterr <= \<const0>\;
underflow <= \<const0>\;
valid <= \<const0>\;
wr_ack <= \<const0>\;
wr_data_count(9) <= \<const0>\;
wr_data_count(8) <= \<const0>\;
wr_data_count(7) <= \<const0>\;
wr_data_count(6) <= \<const0>\;
wr_data_count(5) <= \<const0>\;
wr_data_count(4) <= \<const0>\;
wr_data_count(3) <= \<const0>\;
wr_data_count(2) <= \<const0>\;
wr_data_count(1) <= \<const0>\;
wr_data_count(0) <= \<const0>\;
wr_rst_busy <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
inst_fifo_gen: entity work.bd_auto_cc_0_fifo_generator_v13_1_3_synth
port map (
DI(64 downto 61) => s_axi_awid(3 downto 0),
DI(60 downto 29) => s_axi_awaddr(31 downto 0),
DI(28 downto 21) => s_axi_awlen(7 downto 0),
DI(20 downto 18) => s_axi_awsize(2 downto 0),
DI(17 downto 16) => s_axi_awburst(1 downto 0),
DI(15) => s_axi_awlock(0),
DI(14 downto 11) => s_axi_awcache(3 downto 0),
DI(10 downto 8) => s_axi_awprot(2 downto 0),
DI(7 downto 4) => s_axi_awqos(3 downto 0),
DI(3 downto 0) => s_axi_awregion(3 downto 0),
I115(36 downto 5) => s_axi_wdata(31 downto 0),
I115(4 downto 1) => s_axi_wstrb(3 downto 0),
I115(0) => s_axi_wlast,
I123(64 downto 61) => s_axi_arid(3 downto 0),
I123(60 downto 29) => s_axi_araddr(31 downto 0),
I123(28 downto 21) => s_axi_arlen(7 downto 0),
I123(20 downto 18) => s_axi_arsize(2 downto 0),
I123(17 downto 16) => s_axi_arburst(1 downto 0),
I123(15) => s_axi_arlock(0),
I123(14 downto 11) => s_axi_arcache(3 downto 0),
I123(10 downto 8) => s_axi_arprot(2 downto 0),
I123(7 downto 4) => s_axi_arqos(3 downto 0),
I123(3 downto 0) => s_axi_arregion(3 downto 0),
I127(38 downto 35) => m_axi_rid(3 downto 0),
I127(34 downto 3) => m_axi_rdata(31 downto 0),
I127(2 downto 1) => m_axi_rresp(1 downto 0),
I127(0) => m_axi_rlast,
Q(64 downto 61) => m_axi_awid(3 downto 0),
Q(60 downto 29) => m_axi_awaddr(31 downto 0),
Q(28 downto 21) => m_axi_awlen(7 downto 0),
Q(20 downto 18) => m_axi_awsize(2 downto 0),
Q(17 downto 16) => m_axi_awburst(1 downto 0),
Q(15) => m_axi_awlock(0),
Q(14 downto 11) => m_axi_awcache(3 downto 0),
Q(10 downto 8) => m_axi_awprot(2 downto 0),
Q(7 downto 4) => m_axi_awqos(3 downto 0),
Q(3 downto 0) => m_axi_awregion(3 downto 0),
m_aclk => m_aclk,
\m_axi_arid[3]\(64 downto 61) => m_axi_arid(3 downto 0),
\m_axi_arid[3]\(60 downto 29) => m_axi_araddr(31 downto 0),
\m_axi_arid[3]\(28 downto 21) => m_axi_arlen(7 downto 0),
\m_axi_arid[3]\(20 downto 18) => m_axi_arsize(2 downto 0),
\m_axi_arid[3]\(17 downto 16) => m_axi_arburst(1 downto 0),
\m_axi_arid[3]\(15) => m_axi_arlock(0),
\m_axi_arid[3]\(14 downto 11) => m_axi_arcache(3 downto 0),
\m_axi_arid[3]\(10 downto 8) => m_axi_arprot(2 downto 0),
\m_axi_arid[3]\(7 downto 4) => m_axi_arqos(3 downto 0),
\m_axi_arid[3]\(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arvalid => m_axi_arvalid,
m_axi_awready => m_axi_awready,
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_bvalid => m_axi_bvalid,
m_axi_rready => m_axi_rready,
m_axi_rvalid => m_axi_rvalid,
\m_axi_wdata[31]\(36 downto 5) => m_axi_wdata(31 downto 0),
\m_axi_wdata[31]\(4 downto 1) => m_axi_wstrb(3 downto 0),
\m_axi_wdata[31]\(0) => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wvalid => m_axi_wvalid,
s_aclk => s_aclk,
s_aresetn => s_aresetn,
s_axi_arready => s_axi_arready,
s_axi_arvalid => s_axi_arvalid,
s_axi_awready => s_axi_awready,
s_axi_awvalid => s_axi_awvalid,
\s_axi_bid[3]\(5 downto 2) => s_axi_bid(3 downto 0),
\s_axi_bid[3]\(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bvalid => s_axi_bvalid,
\s_axi_rid[3]\(38 downto 35) => s_axi_rid(3 downto 0),
\s_axi_rid[3]\(34 downto 3) => s_axi_rdata(31 downto 0),
\s_axi_rid[3]\(2 downto 1) => s_axi_rresp(1 downto 0),
\s_axi_rid[3]\(0) => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rvalid => s_axi_rvalid,
s_axi_wready => s_axi_wready,
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wuser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_buser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_aruser : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_ruser : out STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wuser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_buser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_aruser : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_ruser : in STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 61;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 61;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 6;
attribute C_FAMILY : string;
attribute C_FAMILY of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 65;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 6;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 39;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 35;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 39;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 5;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 32;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 4;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 37;
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "yes";
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter : entity is "1'b1";
end bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter;
architecture STRUCTURE of bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter is
signal \<const0>\ : STD_LOGIC;
signal async_conv_reset_n : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\ : STD_LOGIC;
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 4 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 10 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\ : STD_LOGIC_VECTOR ( 17 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\ : STD_LOGIC_VECTOR ( 7 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 3 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\ : STD_LOGIC_VECTOR ( 0 to 0 );
signal \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\ : STD_LOGIC_VECTOR ( 9 downto 0 );
attribute C_ADD_NGC_CONSTRAINT : integer;
attribute C_ADD_NGC_CONSTRAINT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_AXIS : integer;
attribute C_APPLICATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RACH : integer;
attribute C_APPLICATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_RDCH : integer;
attribute C_APPLICATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WACH : integer;
attribute C_APPLICATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WDCH : integer;
attribute C_APPLICATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_APPLICATION_TYPE_WRCH : integer;
attribute C_APPLICATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXIS_TDATA_WIDTH : integer;
attribute C_AXIS_TDATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXIS_TDEST_WIDTH : integer;
attribute C_AXIS_TDEST_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TID_WIDTH : integer;
attribute C_AXIS_TID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TKEEP_WIDTH : integer;
attribute C_AXIS_TKEEP_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TSTRB_WIDTH : integer;
attribute C_AXIS_TSTRB_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXIS_TUSER_WIDTH : integer;
attribute C_AXIS_TUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_AXIS_TYPE : integer;
attribute C_AXIS_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_AXI_ADDR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 32;
attribute C_AXI_ARUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_AWUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_BUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_DATA_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 32;
attribute C_AXI_ID_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_AXI_LEN_WIDTH : integer;
attribute C_AXI_LEN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 8;
attribute C_AXI_LOCK_WIDTH : integer;
attribute C_AXI_LOCK_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_RUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_TYPE : integer;
attribute C_AXI_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_AXI_WUSER_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_COMMON_CLOCK : integer;
attribute C_COMMON_CLOCK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_COUNT_TYPE : integer;
attribute C_COUNT_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_DATA_COUNT_WIDTH : integer;
attribute C_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_DEFAULT_VALUE : string;
attribute C_DEFAULT_VALUE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_DIN_WIDTH : integer;
attribute C_DIN_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_DIN_WIDTH_AXIS : integer;
attribute C_DIN_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_DIN_WIDTH_RACH : integer;
attribute C_DIN_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 65;
attribute C_DIN_WIDTH_RDCH : integer;
attribute C_DIN_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 39;
attribute C_DIN_WIDTH_WACH : integer;
attribute C_DIN_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 65;
attribute C_DIN_WIDTH_WDCH : integer;
attribute C_DIN_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 37;
attribute C_DIN_WIDTH_WRCH : integer;
attribute C_DIN_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 6;
attribute C_DOUT_RST_VAL : string;
attribute C_DOUT_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "0";
attribute C_DOUT_WIDTH : integer;
attribute C_DOUT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 18;
attribute C_ENABLE_RLOCS : integer;
attribute C_ENABLE_RLOCS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ENABLE_RST_SYNC : integer;
attribute C_ENABLE_RST_SYNC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_EN_SAFETY_CKT : integer;
attribute C_EN_SAFETY_CKT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE : integer;
attribute C_ERROR_INJECTION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_AXIS : integer;
attribute C_ERROR_INJECTION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RACH : integer;
attribute C_ERROR_INJECTION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_RDCH : integer;
attribute C_ERROR_INJECTION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WACH : integer;
attribute C_ERROR_INJECTION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WDCH : integer;
attribute C_ERROR_INJECTION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_ERROR_INJECTION_TYPE_WRCH : integer;
attribute C_ERROR_INJECTION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_FAMILY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "artix7";
attribute C_FULL_FLAGS_RST_VAL : integer;
attribute C_FULL_FLAGS_RST_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_ALMOST_EMPTY : integer;
attribute C_HAS_ALMOST_EMPTY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_ALMOST_FULL : integer;
attribute C_HAS_ALMOST_FULL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TDATA : integer;
attribute C_HAS_AXIS_TDATA of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TDEST : integer;
attribute C_HAS_AXIS_TDEST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TID : integer;
attribute C_HAS_AXIS_TID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TKEEP : integer;
attribute C_HAS_AXIS_TKEEP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TLAST : integer;
attribute C_HAS_AXIS_TLAST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TREADY : integer;
attribute C_HAS_AXIS_TREADY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXIS_TSTRB : integer;
attribute C_HAS_AXIS_TSTRB of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXIS_TUSER : integer;
attribute C_HAS_AXIS_TUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_ARUSER : integer;
attribute C_HAS_AXI_ARUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_AWUSER : integer;
attribute C_HAS_AXI_AWUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_BUSER : integer;
attribute C_HAS_AXI_BUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_ID : integer;
attribute C_HAS_AXI_ID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RD_CHANNEL : integer;
attribute C_HAS_AXI_RD_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_RUSER : integer;
attribute C_HAS_AXI_RUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_AXI_WR_CHANNEL : integer;
attribute C_HAS_AXI_WR_CHANNEL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_AXI_WUSER : integer;
attribute C_HAS_AXI_WUSER of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_BACKUP : integer;
attribute C_HAS_BACKUP of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNT : integer;
attribute C_HAS_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_AXIS : integer;
attribute C_HAS_DATA_COUNTS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RACH : integer;
attribute C_HAS_DATA_COUNTS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_RDCH : integer;
attribute C_HAS_DATA_COUNTS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WACH : integer;
attribute C_HAS_DATA_COUNTS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WDCH : integer;
attribute C_HAS_DATA_COUNTS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_DATA_COUNTS_WRCH : integer;
attribute C_HAS_DATA_COUNTS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_INT_CLK : integer;
attribute C_HAS_INT_CLK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MASTER_CE : integer;
attribute C_HAS_MASTER_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_MEMINIT_FILE : integer;
attribute C_HAS_MEMINIT_FILE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_OVERFLOW : integer;
attribute C_HAS_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_AXIS : integer;
attribute C_HAS_PROG_FLAGS_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RACH : integer;
attribute C_HAS_PROG_FLAGS_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_RDCH : integer;
attribute C_HAS_PROG_FLAGS_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WACH : integer;
attribute C_HAS_PROG_FLAGS_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WDCH : integer;
attribute C_HAS_PROG_FLAGS_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_PROG_FLAGS_WRCH : integer;
attribute C_HAS_PROG_FLAGS_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_DATA_COUNT : integer;
attribute C_HAS_RD_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RD_RST : integer;
attribute C_HAS_RD_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_RST : integer;
attribute C_HAS_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_HAS_SLAVE_CE : integer;
attribute C_HAS_SLAVE_CE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_SRST : integer;
attribute C_HAS_SRST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_UNDERFLOW : integer;
attribute C_HAS_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_VALID : integer;
attribute C_HAS_VALID of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_ACK : integer;
attribute C_HAS_WR_ACK of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_DATA_COUNT : integer;
attribute C_HAS_WR_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_HAS_WR_RST : integer;
attribute C_HAS_WR_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE : integer;
attribute C_IMPLEMENTATION_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_IMPLEMENTATION_TYPE_AXIS : integer;
attribute C_IMPLEMENTATION_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 11;
attribute C_IMPLEMENTATION_TYPE_RACH : integer;
attribute C_IMPLEMENTATION_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_RDCH : integer;
attribute C_IMPLEMENTATION_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WACH : integer;
attribute C_IMPLEMENTATION_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WDCH : integer;
attribute C_IMPLEMENTATION_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_IMPLEMENTATION_TYPE_WRCH : integer;
attribute C_IMPLEMENTATION_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 12;
attribute C_INIT_WR_PNTR_VAL : integer;
attribute C_INIT_WR_PNTR_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_INTERFACE_TYPE : integer;
attribute C_INTERFACE_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_MEMORY_TYPE : integer;
attribute C_MEMORY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_MIF_FILE_NAME : string;
attribute C_MIF_FILE_NAME of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "BlankString";
attribute C_MSGON_VAL : integer;
attribute C_MSGON_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_OPTIMIZATION_MODE : integer;
attribute C_OPTIMIZATION_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_OVERFLOW_LOW : integer;
attribute C_OVERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_POWER_SAVING_MODE : integer;
attribute C_POWER_SAVING_MODE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRELOAD_LATENCY : integer;
attribute C_PRELOAD_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_PRELOAD_REGS : integer;
attribute C_PRELOAD_REGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PRIM_FIFO_TYPE : string;
attribute C_PRIM_FIFO_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "4kx4";
attribute C_PRIM_FIFO_TYPE_AXIS : string;
attribute C_PRIM_FIFO_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RACH : string;
attribute C_PRIM_FIFO_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_RDCH : string;
attribute C_PRIM_FIFO_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WACH : string;
attribute C_PRIM_FIFO_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WDCH : string;
attribute C_PRIM_FIFO_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PRIM_FIFO_TYPE_WRCH : string;
attribute C_PRIM_FIFO_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is "512x36";
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 2;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_EMPTY_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 13;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL : integer;
attribute C_PROG_EMPTY_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_PROG_EMPTY_TYPE : integer;
attribute C_PROG_EMPTY_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_AXIS : integer;
attribute C_PROG_EMPTY_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RACH : integer;
attribute C_PROG_EMPTY_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_RDCH : integer;
attribute C_PROG_EMPTY_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WACH : integer;
attribute C_PROG_EMPTY_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WDCH : integer;
attribute C_PROG_EMPTY_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_EMPTY_TYPE_WRCH : integer;
attribute C_PROG_EMPTY_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_THRESH_ASSERT_VAL : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1022;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1023;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH : integer;
attribute C_PROG_FULL_THRESH_ASSERT_VAL_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 15;
attribute C_PROG_FULL_THRESH_NEGATE_VAL : integer;
attribute C_PROG_FULL_THRESH_NEGATE_VAL of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1021;
attribute C_PROG_FULL_TYPE : integer;
attribute C_PROG_FULL_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_AXIS : integer;
attribute C_PROG_FULL_TYPE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RACH : integer;
attribute C_PROG_FULL_TYPE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_RDCH : integer;
attribute C_PROG_FULL_TYPE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WACH : integer;
attribute C_PROG_FULL_TYPE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WDCH : integer;
attribute C_PROG_FULL_TYPE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_PROG_FULL_TYPE_WRCH : integer;
attribute C_PROG_FULL_TYPE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RACH_TYPE : integer;
attribute C_RACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RDCH_TYPE : integer;
attribute C_RDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_RD_DATA_COUNT_WIDTH : integer;
attribute C_RD_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_RD_DEPTH : integer;
attribute C_RD_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_RD_FREQ : integer;
attribute C_RD_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_RD_PNTR_WIDTH : integer;
attribute C_RD_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_REG_SLICE_MODE_AXIS : integer;
attribute C_REG_SLICE_MODE_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RACH : integer;
attribute C_REG_SLICE_MODE_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_RDCH : integer;
attribute C_REG_SLICE_MODE_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WACH : integer;
attribute C_REG_SLICE_MODE_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WDCH : integer;
attribute C_REG_SLICE_MODE_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_REG_SLICE_MODE_WRCH : integer;
attribute C_REG_SLICE_MODE_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SELECT_XPM : integer;
attribute C_SELECT_XPM of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_SYNCHRONIZER_STAGE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 3;
attribute C_UNDERFLOW_LOW : integer;
attribute C_UNDERFLOW_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_OVERFLOW : integer;
attribute C_USE_COMMON_OVERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_COMMON_UNDERFLOW : integer;
attribute C_USE_COMMON_UNDERFLOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DEFAULT_SETTINGS : integer;
attribute C_USE_DEFAULT_SETTINGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_DOUT_RST : integer;
attribute C_USE_DOUT_RST of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_USE_ECC : integer;
attribute C_USE_ECC of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_AXIS : integer;
attribute C_USE_ECC_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RACH : integer;
attribute C_USE_ECC_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_RDCH : integer;
attribute C_USE_ECC_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WACH : integer;
attribute C_USE_ECC_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WDCH : integer;
attribute C_USE_ECC_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_ECC_WRCH : integer;
attribute C_USE_ECC_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_EMBEDDED_REG : integer;
attribute C_USE_EMBEDDED_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FIFO16_FLAGS : integer;
attribute C_USE_FIFO16_FLAGS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_FWFT_DATA_COUNT : integer;
attribute C_USE_FWFT_DATA_COUNT of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_USE_PIPELINE_REG : integer;
attribute C_USE_PIPELINE_REG of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_VALID_LOW : integer;
attribute C_VALID_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WACH_TYPE : integer;
attribute C_WACH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WDCH_TYPE : integer;
attribute C_WDCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WRCH_TYPE : integer;
attribute C_WRCH_TYPE of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_ACK_LOW : integer;
attribute C_WR_ACK_LOW of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 0;
attribute C_WR_DATA_COUNT_WIDTH : integer;
attribute C_WR_DATA_COUNT_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_DEPTH : integer;
attribute C_WR_DEPTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_AXIS : integer;
attribute C_WR_DEPTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1024;
attribute C_WR_DEPTH_RACH : integer;
attribute C_WR_DEPTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_RDCH : integer;
attribute C_WR_DEPTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WACH : integer;
attribute C_WR_DEPTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WDCH : integer;
attribute C_WR_DEPTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_DEPTH_WRCH : integer;
attribute C_WR_DEPTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 16;
attribute C_WR_FREQ : integer;
attribute C_WR_FREQ of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
attribute C_WR_PNTR_WIDTH : integer;
attribute C_WR_PNTR_WIDTH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_AXIS : integer;
attribute C_WR_PNTR_WIDTH_AXIS of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 10;
attribute C_WR_PNTR_WIDTH_RACH : integer;
attribute C_WR_PNTR_WIDTH_RACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_RDCH : integer;
attribute C_WR_PNTR_WIDTH_RDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WACH : integer;
attribute C_WR_PNTR_WIDTH_WACH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WDCH : integer;
attribute C_WR_PNTR_WIDTH_WDCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_PNTR_WIDTH_WRCH : integer;
attribute C_WR_PNTR_WIDTH_WRCH of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 4;
attribute C_WR_RESPONSE_LATENCY : integer;
attribute C_WR_RESPONSE_LATENCY of \gen_clock_conv.gen_async_conv.asyncfifo_axi\ : label is 1;
begin
m_axi_aruser(0) <= \<const0>\;
m_axi_awuser(0) <= \<const0>\;
m_axi_wid(3) <= \<const0>\;
m_axi_wid(2) <= \<const0>\;
m_axi_wid(1) <= \<const0>\;
m_axi_wid(0) <= \<const0>\;
m_axi_wuser(0) <= \<const0>\;
s_axi_buser(0) <= \<const0>\;
s_axi_ruser(0) <= \<const0>\;
GND: unisim.vcomponents.GND
port map (
G => \<const0>\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi\: entity work.bd_auto_cc_0_fifo_generator_v13_1_3
port map (
almost_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_empty_UNCONNECTED\,
almost_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_almost_full_UNCONNECTED\,
axi_ar_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_data_count_UNCONNECTED\(4 downto 0),
axi_ar_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_dbiterr_UNCONNECTED\,
axi_ar_injectdbiterr => '0',
axi_ar_injectsbiterr => '0',
axi_ar_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_overflow_UNCONNECTED\,
axi_ar_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_empty_UNCONNECTED\,
axi_ar_prog_empty_thresh(3 downto 0) => B"0000",
axi_ar_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_prog_full_UNCONNECTED\,
axi_ar_prog_full_thresh(3 downto 0) => B"0000",
axi_ar_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_rd_data_count_UNCONNECTED\(4 downto 0),
axi_ar_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_sbiterr_UNCONNECTED\,
axi_ar_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_underflow_UNCONNECTED\,
axi_ar_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_ar_wr_data_count_UNCONNECTED\(4 downto 0),
axi_aw_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_data_count_UNCONNECTED\(4 downto 0),
axi_aw_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_dbiterr_UNCONNECTED\,
axi_aw_injectdbiterr => '0',
axi_aw_injectsbiterr => '0',
axi_aw_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_overflow_UNCONNECTED\,
axi_aw_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_empty_UNCONNECTED\,
axi_aw_prog_empty_thresh(3 downto 0) => B"0000",
axi_aw_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_prog_full_UNCONNECTED\,
axi_aw_prog_full_thresh(3 downto 0) => B"0000",
axi_aw_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_rd_data_count_UNCONNECTED\(4 downto 0),
axi_aw_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_sbiterr_UNCONNECTED\,
axi_aw_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_underflow_UNCONNECTED\,
axi_aw_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_aw_wr_data_count_UNCONNECTED\(4 downto 0),
axi_b_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_data_count_UNCONNECTED\(4 downto 0),
axi_b_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_dbiterr_UNCONNECTED\,
axi_b_injectdbiterr => '0',
axi_b_injectsbiterr => '0',
axi_b_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_overflow_UNCONNECTED\,
axi_b_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_empty_UNCONNECTED\,
axi_b_prog_empty_thresh(3 downto 0) => B"0000",
axi_b_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_prog_full_UNCONNECTED\,
axi_b_prog_full_thresh(3 downto 0) => B"0000",
axi_b_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_rd_data_count_UNCONNECTED\(4 downto 0),
axi_b_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_sbiterr_UNCONNECTED\,
axi_b_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_underflow_UNCONNECTED\,
axi_b_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_b_wr_data_count_UNCONNECTED\(4 downto 0),
axi_r_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_data_count_UNCONNECTED\(4 downto 0),
axi_r_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_dbiterr_UNCONNECTED\,
axi_r_injectdbiterr => '0',
axi_r_injectsbiterr => '0',
axi_r_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_overflow_UNCONNECTED\,
axi_r_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_empty_UNCONNECTED\,
axi_r_prog_empty_thresh(3 downto 0) => B"0000",
axi_r_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_prog_full_UNCONNECTED\,
axi_r_prog_full_thresh(3 downto 0) => B"0000",
axi_r_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_rd_data_count_UNCONNECTED\(4 downto 0),
axi_r_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_sbiterr_UNCONNECTED\,
axi_r_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_underflow_UNCONNECTED\,
axi_r_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_r_wr_data_count_UNCONNECTED\(4 downto 0),
axi_w_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_data_count_UNCONNECTED\(4 downto 0),
axi_w_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_dbiterr_UNCONNECTED\,
axi_w_injectdbiterr => '0',
axi_w_injectsbiterr => '0',
axi_w_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_overflow_UNCONNECTED\,
axi_w_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_empty_UNCONNECTED\,
axi_w_prog_empty_thresh(3 downto 0) => B"0000",
axi_w_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_prog_full_UNCONNECTED\,
axi_w_prog_full_thresh(3 downto 0) => B"0000",
axi_w_rd_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_rd_data_count_UNCONNECTED\(4 downto 0),
axi_w_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_sbiterr_UNCONNECTED\,
axi_w_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_underflow_UNCONNECTED\,
axi_w_wr_data_count(4 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axi_w_wr_data_count_UNCONNECTED\(4 downto 0),
axis_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_data_count_UNCONNECTED\(10 downto 0),
axis_dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_dbiterr_UNCONNECTED\,
axis_injectdbiterr => '0',
axis_injectsbiterr => '0',
axis_overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_overflow_UNCONNECTED\,
axis_prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_empty_UNCONNECTED\,
axis_prog_empty_thresh(9 downto 0) => B"0000000000",
axis_prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_prog_full_UNCONNECTED\,
axis_prog_full_thresh(9 downto 0) => B"0000000000",
axis_rd_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_rd_data_count_UNCONNECTED\(10 downto 0),
axis_sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_sbiterr_UNCONNECTED\,
axis_underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_underflow_UNCONNECTED\,
axis_wr_data_count(10 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_axis_wr_data_count_UNCONNECTED\(10 downto 0),
backup => '0',
backup_marker => '0',
clk => '0',
data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_data_count_UNCONNECTED\(9 downto 0),
dbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dbiterr_UNCONNECTED\,
din(17 downto 0) => B"000000000000000000",
dout(17 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_dout_UNCONNECTED\(17 downto 0),
empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_empty_UNCONNECTED\,
full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_full_UNCONNECTED\,
injectdbiterr => '0',
injectsbiterr => '0',
int_clk => '0',
m_aclk => m_axi_aclk,
m_aclk_en => '1',
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_arid(3 downto 0) => m_axi_arid(3 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_aruser_UNCONNECTED\(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(3 downto 0) => m_axi_awid(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_awuser_UNCONNECTED\(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(3 downto 0) => m_axi_rid(3 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(3 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wid_UNCONNECTED\(3 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axi_wuser_UNCONNECTED\(0),
m_axi_wvalid => m_axi_wvalid,
m_axis_tdata(7 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdata_UNCONNECTED\(7 downto 0),
m_axis_tdest(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tdest_UNCONNECTED\(0),
m_axis_tid(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tid_UNCONNECTED\(0),
m_axis_tkeep(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tkeep_UNCONNECTED\(0),
m_axis_tlast => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tlast_UNCONNECTED\,
m_axis_tready => '0',
m_axis_tstrb(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tstrb_UNCONNECTED\(0),
m_axis_tuser(3 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tuser_UNCONNECTED\(3 downto 0),
m_axis_tvalid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_m_axis_tvalid_UNCONNECTED\,
overflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_overflow_UNCONNECTED\,
prog_empty => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_empty_UNCONNECTED\,
prog_empty_thresh(9 downto 0) => B"0000000000",
prog_empty_thresh_assert(9 downto 0) => B"0000000000",
prog_empty_thresh_negate(9 downto 0) => B"0000000000",
prog_full => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_prog_full_UNCONNECTED\,
prog_full_thresh(9 downto 0) => B"0000000000",
prog_full_thresh_assert(9 downto 0) => B"0000000000",
prog_full_thresh_negate(9 downto 0) => B"0000000000",
rd_clk => '0',
rd_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_data_count_UNCONNECTED\(9 downto 0),
rd_en => '0',
rd_rst => '0',
rd_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_rd_rst_busy_UNCONNECTED\,
rst => '0',
s_aclk => s_axi_aclk,
s_aclk_en => '1',
s_aresetn => async_conv_reset_n,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_arid(3 downto 0) => s_axi_arid(3 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(3 downto 0) => s_axi_awid(3 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(3 downto 0) => s_axi_bid(3 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_buser_UNCONNECTED\(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(3 downto 0) => s_axi_rid(3 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axi_ruser_UNCONNECTED\(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid,
s_axis_tdata(7 downto 0) => B"00000000",
s_axis_tdest(0) => '0',
s_axis_tid(0) => '0',
s_axis_tkeep(0) => '0',
s_axis_tlast => '0',
s_axis_tready => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_s_axis_tready_UNCONNECTED\,
s_axis_tstrb(0) => '0',
s_axis_tuser(3 downto 0) => B"0000",
s_axis_tvalid => '0',
sbiterr => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_sbiterr_UNCONNECTED\,
sleep => '0',
srst => '0',
underflow => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_underflow_UNCONNECTED\,
valid => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_valid_UNCONNECTED\,
wr_ack => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_ack_UNCONNECTED\,
wr_clk => '0',
wr_data_count(9 downto 0) => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_data_count_UNCONNECTED\(9 downto 0),
wr_en => '0',
wr_rst => '0',
wr_rst_busy => \NLW_gen_clock_conv.gen_async_conv.asyncfifo_axi_wr_rst_busy_UNCONNECTED\
);
\gen_clock_conv.gen_async_conv.asyncfifo_axi_i_1\: unisim.vcomponents.LUT2
generic map(
INIT => X"8"
)
port map (
I0 => s_axi_aresetn,
I1 => m_axi_aresetn,
O => async_conv_reset_n
);
end STRUCTURE;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
entity bd_auto_cc_0 is
port (
s_axi_aclk : in STD_LOGIC;
s_axi_aresetn : in STD_LOGIC;
s_axi_awid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awaddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_awlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_awsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_awlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_awcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_awregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_awvalid : in STD_LOGIC;
s_axi_awready : out STD_LOGIC;
s_axi_wdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_wstrb : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_wlast : in STD_LOGIC;
s_axi_wvalid : in STD_LOGIC;
s_axi_wready : out STD_LOGIC;
s_axi_bid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_bresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_bvalid : out STD_LOGIC;
s_axi_bready : in STD_LOGIC;
s_axi_arid : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_araddr : in STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_arlen : in STD_LOGIC_VECTOR ( 7 downto 0 );
s_axi_arsize : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arburst : in STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_arlock : in STD_LOGIC_VECTOR ( 0 to 0 );
s_axi_arcache : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arprot : in STD_LOGIC_VECTOR ( 2 downto 0 );
s_axi_arregion : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arqos : in STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_arvalid : in STD_LOGIC;
s_axi_arready : out STD_LOGIC;
s_axi_rid : out STD_LOGIC_VECTOR ( 3 downto 0 );
s_axi_rdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
s_axi_rresp : out STD_LOGIC_VECTOR ( 1 downto 0 );
s_axi_rlast : out STD_LOGIC;
s_axi_rvalid : out STD_LOGIC;
s_axi_rready : in STD_LOGIC;
m_axi_aclk : in STD_LOGIC;
m_axi_aresetn : in STD_LOGIC;
m_axi_awid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awaddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_awlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_awsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_awlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_awcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_awregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_awvalid : out STD_LOGIC;
m_axi_awready : in STD_LOGIC;
m_axi_wdata : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_wstrb : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_wlast : out STD_LOGIC;
m_axi_wvalid : out STD_LOGIC;
m_axi_wready : in STD_LOGIC;
m_axi_bid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_bresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_bvalid : in STD_LOGIC;
m_axi_bready : out STD_LOGIC;
m_axi_arid : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_araddr : out STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_arlen : out STD_LOGIC_VECTOR ( 7 downto 0 );
m_axi_arsize : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arburst : out STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_arlock : out STD_LOGIC_VECTOR ( 0 to 0 );
m_axi_arcache : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arprot : out STD_LOGIC_VECTOR ( 2 downto 0 );
m_axi_arregion : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arqos : out STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_arvalid : out STD_LOGIC;
m_axi_arready : in STD_LOGIC;
m_axi_rid : in STD_LOGIC_VECTOR ( 3 downto 0 );
m_axi_rdata : in STD_LOGIC_VECTOR ( 31 downto 0 );
m_axi_rresp : in STD_LOGIC_VECTOR ( 1 downto 0 );
m_axi_rlast : in STD_LOGIC;
m_axi_rvalid : in STD_LOGIC;
m_axi_rready : out STD_LOGIC
);
attribute NotValidForBitStream : boolean;
attribute NotValidForBitStream of bd_auto_cc_0 : entity is true;
attribute CHECK_LICENSE_TYPE : string;
attribute CHECK_LICENSE_TYPE of bd_auto_cc_0 : entity is "bd_auto_cc_0,axi_clock_converter_v2_1_10_axi_clock_converter,{}";
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of bd_auto_cc_0 : entity is "yes";
attribute X_CORE_INFO : string;
attribute X_CORE_INFO of bd_auto_cc_0 : entity is "axi_clock_converter_v2_1_10_axi_clock_converter,Vivado 2016.4";
end bd_auto_cc_0;
architecture STRUCTURE of bd_auto_cc_0 is
signal NLW_inst_m_axi_aruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_awuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_m_axi_wid_UNCONNECTED : STD_LOGIC_VECTOR ( 3 downto 0 );
signal NLW_inst_m_axi_wuser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_buser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
signal NLW_inst_s_axi_ruser_UNCONNECTED : STD_LOGIC_VECTOR ( 0 to 0 );
attribute C_ARADDR_RIGHT : integer;
attribute C_ARADDR_RIGHT of inst : label is 29;
attribute C_ARADDR_WIDTH : integer;
attribute C_ARADDR_WIDTH of inst : label is 32;
attribute C_ARBURST_RIGHT : integer;
attribute C_ARBURST_RIGHT of inst : label is 16;
attribute C_ARBURST_WIDTH : integer;
attribute C_ARBURST_WIDTH of inst : label is 2;
attribute C_ARCACHE_RIGHT : integer;
attribute C_ARCACHE_RIGHT of inst : label is 11;
attribute C_ARCACHE_WIDTH : integer;
attribute C_ARCACHE_WIDTH of inst : label is 4;
attribute C_ARID_RIGHT : integer;
attribute C_ARID_RIGHT of inst : label is 61;
attribute C_ARID_WIDTH : integer;
attribute C_ARID_WIDTH of inst : label is 4;
attribute C_ARLEN_RIGHT : integer;
attribute C_ARLEN_RIGHT of inst : label is 21;
attribute C_ARLEN_WIDTH : integer;
attribute C_ARLEN_WIDTH of inst : label is 8;
attribute C_ARLOCK_RIGHT : integer;
attribute C_ARLOCK_RIGHT of inst : label is 15;
attribute C_ARLOCK_WIDTH : integer;
attribute C_ARLOCK_WIDTH of inst : label is 1;
attribute C_ARPROT_RIGHT : integer;
attribute C_ARPROT_RIGHT of inst : label is 8;
attribute C_ARPROT_WIDTH : integer;
attribute C_ARPROT_WIDTH of inst : label is 3;
attribute C_ARQOS_RIGHT : integer;
attribute C_ARQOS_RIGHT of inst : label is 0;
attribute C_ARQOS_WIDTH : integer;
attribute C_ARQOS_WIDTH of inst : label is 4;
attribute C_ARREGION_RIGHT : integer;
attribute C_ARREGION_RIGHT of inst : label is 4;
attribute C_ARREGION_WIDTH : integer;
attribute C_ARREGION_WIDTH of inst : label is 4;
attribute C_ARSIZE_RIGHT : integer;
attribute C_ARSIZE_RIGHT of inst : label is 18;
attribute C_ARSIZE_WIDTH : integer;
attribute C_ARSIZE_WIDTH of inst : label is 3;
attribute C_ARUSER_RIGHT : integer;
attribute C_ARUSER_RIGHT of inst : label is 0;
attribute C_ARUSER_WIDTH : integer;
attribute C_ARUSER_WIDTH of inst : label is 0;
attribute C_AR_WIDTH : integer;
attribute C_AR_WIDTH of inst : label is 65;
attribute C_AWADDR_RIGHT : integer;
attribute C_AWADDR_RIGHT of inst : label is 29;
attribute C_AWADDR_WIDTH : integer;
attribute C_AWADDR_WIDTH of inst : label is 32;
attribute C_AWBURST_RIGHT : integer;
attribute C_AWBURST_RIGHT of inst : label is 16;
attribute C_AWBURST_WIDTH : integer;
attribute C_AWBURST_WIDTH of inst : label is 2;
attribute C_AWCACHE_RIGHT : integer;
attribute C_AWCACHE_RIGHT of inst : label is 11;
attribute C_AWCACHE_WIDTH : integer;
attribute C_AWCACHE_WIDTH of inst : label is 4;
attribute C_AWID_RIGHT : integer;
attribute C_AWID_RIGHT of inst : label is 61;
attribute C_AWID_WIDTH : integer;
attribute C_AWID_WIDTH of inst : label is 4;
attribute C_AWLEN_RIGHT : integer;
attribute C_AWLEN_RIGHT of inst : label is 21;
attribute C_AWLEN_WIDTH : integer;
attribute C_AWLEN_WIDTH of inst : label is 8;
attribute C_AWLOCK_RIGHT : integer;
attribute C_AWLOCK_RIGHT of inst : label is 15;
attribute C_AWLOCK_WIDTH : integer;
attribute C_AWLOCK_WIDTH of inst : label is 1;
attribute C_AWPROT_RIGHT : integer;
attribute C_AWPROT_RIGHT of inst : label is 8;
attribute C_AWPROT_WIDTH : integer;
attribute C_AWPROT_WIDTH of inst : label is 3;
attribute C_AWQOS_RIGHT : integer;
attribute C_AWQOS_RIGHT of inst : label is 0;
attribute C_AWQOS_WIDTH : integer;
attribute C_AWQOS_WIDTH of inst : label is 4;
attribute C_AWREGION_RIGHT : integer;
attribute C_AWREGION_RIGHT of inst : label is 4;
attribute C_AWREGION_WIDTH : integer;
attribute C_AWREGION_WIDTH of inst : label is 4;
attribute C_AWSIZE_RIGHT : integer;
attribute C_AWSIZE_RIGHT of inst : label is 18;
attribute C_AWSIZE_WIDTH : integer;
attribute C_AWSIZE_WIDTH of inst : label is 3;
attribute C_AWUSER_RIGHT : integer;
attribute C_AWUSER_RIGHT of inst : label is 0;
attribute C_AWUSER_WIDTH : integer;
attribute C_AWUSER_WIDTH of inst : label is 0;
attribute C_AW_WIDTH : integer;
attribute C_AW_WIDTH of inst : label is 65;
attribute C_AXI_ADDR_WIDTH : integer;
attribute C_AXI_ADDR_WIDTH of inst : label is 32;
attribute C_AXI_ARUSER_WIDTH : integer;
attribute C_AXI_ARUSER_WIDTH of inst : label is 1;
attribute C_AXI_AWUSER_WIDTH : integer;
attribute C_AXI_AWUSER_WIDTH of inst : label is 1;
attribute C_AXI_BUSER_WIDTH : integer;
attribute C_AXI_BUSER_WIDTH of inst : label is 1;
attribute C_AXI_DATA_WIDTH : integer;
attribute C_AXI_DATA_WIDTH of inst : label is 32;
attribute C_AXI_ID_WIDTH : integer;
attribute C_AXI_ID_WIDTH of inst : label is 4;
attribute C_AXI_IS_ACLK_ASYNC : integer;
attribute C_AXI_IS_ACLK_ASYNC of inst : label is 1;
attribute C_AXI_PROTOCOL : integer;
attribute C_AXI_PROTOCOL of inst : label is 0;
attribute C_AXI_RUSER_WIDTH : integer;
attribute C_AXI_RUSER_WIDTH of inst : label is 1;
attribute C_AXI_SUPPORTS_READ : integer;
attribute C_AXI_SUPPORTS_READ of inst : label is 1;
attribute C_AXI_SUPPORTS_USER_SIGNALS : integer;
attribute C_AXI_SUPPORTS_USER_SIGNALS of inst : label is 0;
attribute C_AXI_SUPPORTS_WRITE : integer;
attribute C_AXI_SUPPORTS_WRITE of inst : label is 1;
attribute C_AXI_WUSER_WIDTH : integer;
attribute C_AXI_WUSER_WIDTH of inst : label is 1;
attribute C_BID_RIGHT : integer;
attribute C_BID_RIGHT of inst : label is 2;
attribute C_BID_WIDTH : integer;
attribute C_BID_WIDTH of inst : label is 4;
attribute C_BRESP_RIGHT : integer;
attribute C_BRESP_RIGHT of inst : label is 0;
attribute C_BRESP_WIDTH : integer;
attribute C_BRESP_WIDTH of inst : label is 2;
attribute C_BUSER_RIGHT : integer;
attribute C_BUSER_RIGHT of inst : label is 0;
attribute C_BUSER_WIDTH : integer;
attribute C_BUSER_WIDTH of inst : label is 0;
attribute C_B_WIDTH : integer;
attribute C_B_WIDTH of inst : label is 6;
attribute C_FAMILY : string;
attribute C_FAMILY of inst : label is "artix7";
attribute C_FIFO_AR_WIDTH : integer;
attribute C_FIFO_AR_WIDTH of inst : label is 65;
attribute C_FIFO_AW_WIDTH : integer;
attribute C_FIFO_AW_WIDTH of inst : label is 65;
attribute C_FIFO_B_WIDTH : integer;
attribute C_FIFO_B_WIDTH of inst : label is 6;
attribute C_FIFO_R_WIDTH : integer;
attribute C_FIFO_R_WIDTH of inst : label is 39;
attribute C_FIFO_W_WIDTH : integer;
attribute C_FIFO_W_WIDTH of inst : label is 37;
attribute C_M_AXI_ACLK_RATIO : integer;
attribute C_M_AXI_ACLK_RATIO of inst : label is 2;
attribute C_RDATA_RIGHT : integer;
attribute C_RDATA_RIGHT of inst : label is 3;
attribute C_RDATA_WIDTH : integer;
attribute C_RDATA_WIDTH of inst : label is 32;
attribute C_RID_RIGHT : integer;
attribute C_RID_RIGHT of inst : label is 35;
attribute C_RID_WIDTH : integer;
attribute C_RID_WIDTH of inst : label is 4;
attribute C_RLAST_RIGHT : integer;
attribute C_RLAST_RIGHT of inst : label is 0;
attribute C_RLAST_WIDTH : integer;
attribute C_RLAST_WIDTH of inst : label is 1;
attribute C_RRESP_RIGHT : integer;
attribute C_RRESP_RIGHT of inst : label is 1;
attribute C_RRESP_WIDTH : integer;
attribute C_RRESP_WIDTH of inst : label is 2;
attribute C_RUSER_RIGHT : integer;
attribute C_RUSER_RIGHT of inst : label is 0;
attribute C_RUSER_WIDTH : integer;
attribute C_RUSER_WIDTH of inst : label is 0;
attribute C_R_WIDTH : integer;
attribute C_R_WIDTH of inst : label is 39;
attribute C_SYNCHRONIZER_STAGE : integer;
attribute C_SYNCHRONIZER_STAGE of inst : label is 3;
attribute C_S_AXI_ACLK_RATIO : integer;
attribute C_S_AXI_ACLK_RATIO of inst : label is 1;
attribute C_WDATA_RIGHT : integer;
attribute C_WDATA_RIGHT of inst : label is 5;
attribute C_WDATA_WIDTH : integer;
attribute C_WDATA_WIDTH of inst : label is 32;
attribute C_WID_RIGHT : integer;
attribute C_WID_RIGHT of inst : label is 37;
attribute C_WID_WIDTH : integer;
attribute C_WID_WIDTH of inst : label is 0;
attribute C_WLAST_RIGHT : integer;
attribute C_WLAST_RIGHT of inst : label is 0;
attribute C_WLAST_WIDTH : integer;
attribute C_WLAST_WIDTH of inst : label is 1;
attribute C_WSTRB_RIGHT : integer;
attribute C_WSTRB_RIGHT of inst : label is 1;
attribute C_WSTRB_WIDTH : integer;
attribute C_WSTRB_WIDTH of inst : label is 4;
attribute C_WUSER_RIGHT : integer;
attribute C_WUSER_RIGHT of inst : label is 0;
attribute C_WUSER_WIDTH : integer;
attribute C_WUSER_WIDTH of inst : label is 0;
attribute C_W_WIDTH : integer;
attribute C_W_WIDTH of inst : label is 37;
attribute P_ACLK_RATIO : integer;
attribute P_ACLK_RATIO of inst : label is 2;
attribute P_AXI3 : integer;
attribute P_AXI3 of inst : label is 1;
attribute P_AXI4 : integer;
attribute P_AXI4 of inst : label is 0;
attribute P_AXILITE : integer;
attribute P_AXILITE of inst : label is 2;
attribute P_FULLY_REG : integer;
attribute P_FULLY_REG of inst : label is 1;
attribute P_LIGHT_WT : integer;
attribute P_LIGHT_WT of inst : label is 0;
attribute P_LUTRAM_ASYNC : integer;
attribute P_LUTRAM_ASYNC of inst : label is 12;
attribute P_ROUNDING_OFFSET : integer;
attribute P_ROUNDING_OFFSET of inst : label is 0;
attribute P_SI_LT_MI : string;
attribute P_SI_LT_MI of inst : label is "1'b1";
attribute downgradeipidentifiedwarnings of inst : label is "yes";
begin
inst: entity work.bd_auto_cc_0_axi_clock_converter_v2_1_10_axi_clock_converter
port map (
m_axi_aclk => m_axi_aclk,
m_axi_araddr(31 downto 0) => m_axi_araddr(31 downto 0),
m_axi_arburst(1 downto 0) => m_axi_arburst(1 downto 0),
m_axi_arcache(3 downto 0) => m_axi_arcache(3 downto 0),
m_axi_aresetn => m_axi_aresetn,
m_axi_arid(3 downto 0) => m_axi_arid(3 downto 0),
m_axi_arlen(7 downto 0) => m_axi_arlen(7 downto 0),
m_axi_arlock(0) => m_axi_arlock(0),
m_axi_arprot(2 downto 0) => m_axi_arprot(2 downto 0),
m_axi_arqos(3 downto 0) => m_axi_arqos(3 downto 0),
m_axi_arready => m_axi_arready,
m_axi_arregion(3 downto 0) => m_axi_arregion(3 downto 0),
m_axi_arsize(2 downto 0) => m_axi_arsize(2 downto 0),
m_axi_aruser(0) => NLW_inst_m_axi_aruser_UNCONNECTED(0),
m_axi_arvalid => m_axi_arvalid,
m_axi_awaddr(31 downto 0) => m_axi_awaddr(31 downto 0),
m_axi_awburst(1 downto 0) => m_axi_awburst(1 downto 0),
m_axi_awcache(3 downto 0) => m_axi_awcache(3 downto 0),
m_axi_awid(3 downto 0) => m_axi_awid(3 downto 0),
m_axi_awlen(7 downto 0) => m_axi_awlen(7 downto 0),
m_axi_awlock(0) => m_axi_awlock(0),
m_axi_awprot(2 downto 0) => m_axi_awprot(2 downto 0),
m_axi_awqos(3 downto 0) => m_axi_awqos(3 downto 0),
m_axi_awready => m_axi_awready,
m_axi_awregion(3 downto 0) => m_axi_awregion(3 downto 0),
m_axi_awsize(2 downto 0) => m_axi_awsize(2 downto 0),
m_axi_awuser(0) => NLW_inst_m_axi_awuser_UNCONNECTED(0),
m_axi_awvalid => m_axi_awvalid,
m_axi_bid(3 downto 0) => m_axi_bid(3 downto 0),
m_axi_bready => m_axi_bready,
m_axi_bresp(1 downto 0) => m_axi_bresp(1 downto 0),
m_axi_buser(0) => '0',
m_axi_bvalid => m_axi_bvalid,
m_axi_rdata(31 downto 0) => m_axi_rdata(31 downto 0),
m_axi_rid(3 downto 0) => m_axi_rid(3 downto 0),
m_axi_rlast => m_axi_rlast,
m_axi_rready => m_axi_rready,
m_axi_rresp(1 downto 0) => m_axi_rresp(1 downto 0),
m_axi_ruser(0) => '0',
m_axi_rvalid => m_axi_rvalid,
m_axi_wdata(31 downto 0) => m_axi_wdata(31 downto 0),
m_axi_wid(3 downto 0) => NLW_inst_m_axi_wid_UNCONNECTED(3 downto 0),
m_axi_wlast => m_axi_wlast,
m_axi_wready => m_axi_wready,
m_axi_wstrb(3 downto 0) => m_axi_wstrb(3 downto 0),
m_axi_wuser(0) => NLW_inst_m_axi_wuser_UNCONNECTED(0),
m_axi_wvalid => m_axi_wvalid,
s_axi_aclk => s_axi_aclk,
s_axi_araddr(31 downto 0) => s_axi_araddr(31 downto 0),
s_axi_arburst(1 downto 0) => s_axi_arburst(1 downto 0),
s_axi_arcache(3 downto 0) => s_axi_arcache(3 downto 0),
s_axi_aresetn => s_axi_aresetn,
s_axi_arid(3 downto 0) => s_axi_arid(3 downto 0),
s_axi_arlen(7 downto 0) => s_axi_arlen(7 downto 0),
s_axi_arlock(0) => s_axi_arlock(0),
s_axi_arprot(2 downto 0) => s_axi_arprot(2 downto 0),
s_axi_arqos(3 downto 0) => s_axi_arqos(3 downto 0),
s_axi_arready => s_axi_arready,
s_axi_arregion(3 downto 0) => s_axi_arregion(3 downto 0),
s_axi_arsize(2 downto 0) => s_axi_arsize(2 downto 0),
s_axi_aruser(0) => '0',
s_axi_arvalid => s_axi_arvalid,
s_axi_awaddr(31 downto 0) => s_axi_awaddr(31 downto 0),
s_axi_awburst(1 downto 0) => s_axi_awburst(1 downto 0),
s_axi_awcache(3 downto 0) => s_axi_awcache(3 downto 0),
s_axi_awid(3 downto 0) => s_axi_awid(3 downto 0),
s_axi_awlen(7 downto 0) => s_axi_awlen(7 downto 0),
s_axi_awlock(0) => s_axi_awlock(0),
s_axi_awprot(2 downto 0) => s_axi_awprot(2 downto 0),
s_axi_awqos(3 downto 0) => s_axi_awqos(3 downto 0),
s_axi_awready => s_axi_awready,
s_axi_awregion(3 downto 0) => s_axi_awregion(3 downto 0),
s_axi_awsize(2 downto 0) => s_axi_awsize(2 downto 0),
s_axi_awuser(0) => '0',
s_axi_awvalid => s_axi_awvalid,
s_axi_bid(3 downto 0) => s_axi_bid(3 downto 0),
s_axi_bready => s_axi_bready,
s_axi_bresp(1 downto 0) => s_axi_bresp(1 downto 0),
s_axi_buser(0) => NLW_inst_s_axi_buser_UNCONNECTED(0),
s_axi_bvalid => s_axi_bvalid,
s_axi_rdata(31 downto 0) => s_axi_rdata(31 downto 0),
s_axi_rid(3 downto 0) => s_axi_rid(3 downto 0),
s_axi_rlast => s_axi_rlast,
s_axi_rready => s_axi_rready,
s_axi_rresp(1 downto 0) => s_axi_rresp(1 downto 0),
s_axi_ruser(0) => NLW_inst_s_axi_ruser_UNCONNECTED(0),
s_axi_rvalid => s_axi_rvalid,
s_axi_wdata(31 downto 0) => s_axi_wdata(31 downto 0),
s_axi_wid(3 downto 0) => B"0000",
s_axi_wlast => s_axi_wlast,
s_axi_wready => s_axi_wready,
s_axi_wstrb(3 downto 0) => s_axi_wstrb(3 downto 0),
s_axi_wuser(0) => '0',
s_axi_wvalid => s_axi_wvalid
);
end STRUCTURE;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
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-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_updt_noqueue.vhd
-- Description: This entity provides the descriptor update for the No Queue mode
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library proc_common_v4_0;
use proc_common_v4_0.sync_fifo_fg;
use proc_common_v4_0.proc_common_pkg.all;
-------------------------------------------------------------------------------
entity axi_sg_updt_noqueue is
generic (
C_M_AXI_SG_ADDR_WIDTH : integer range 32 to 64 := 32;
-- Master AXI Memory Map Address Width for Scatter Gather R/W Port
C_M_AXIS_UPDT_DATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Memory Map Data Width for Scatter Gather R/W Port
C_S_AXIS_UPDPTR_TDATA_WIDTH : integer range 32 to 32 := 32;
-- 32 Update Status Bits
C_S_AXIS_UPDSTS_TDATA_WIDTH : integer range 33 to 33 := 33
-- 1 IOC bit + 32 Update Status Bits
);
port (
-----------------------------------------------------------------------
-- AXI Scatter Gather Interface
-----------------------------------------------------------------------
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Channel 1 Control --
updt_curdesc_wren : out std_logic ; --
updt_curdesc : out std_logic_vector --
(C_M_AXI_SG_ADDR_WIDTH-1 downto 0) ; --
updt_active : in std_logic ; --
updt_queue_empty : out std_logic ; --
updt_ioc : out std_logic ; --
updt_ioc_irq_set : in std_logic ; --
--
dma_interr : out std_logic ; --
dma_slverr : out std_logic ; --
dma_decerr : out std_logic ; --
dma_interr_set : in std_logic ; --
dma_slverr_set : in std_logic ; --
dma_decerr_set : in std_logic ; --
updt2_active : in std_logic ; --
updt2_queue_empty : out std_logic ; --
updt2_ioc : out std_logic ; --
updt2_ioc_irq_set : in std_logic ; --
--
dma2_interr : out std_logic ; --
dma2_slverr : out std_logic ; --
dma2_decerr : out std_logic ; --
dma2_interr_set : in std_logic ; --
dma2_slverr_set : in std_logic ; --
dma2_decerr_set : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface In **-- --
--*********************************-- --
-- Update Pointer Stream --
s_axis_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis_updtptr_tvalid : in std_logic ; --
s_axis_updtptr_tready : out std_logic ; --
s_axis_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis_updtsts_tvalid : in std_logic ; --
s_axis_updtsts_tready : out std_logic ; --
s_axis_updtsts_tlast : in std_logic ; --
-- Update Pointer Stream --
s_axis2_updtptr_tdata : in std_logic_vector --
(C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) ; --
s_axis2_updtptr_tvalid : in std_logic ; --
s_axis2_updtptr_tready : out std_logic ; --
s_axis2_updtptr_tlast : in std_logic ; --
--
-- Update Status Stream --
s_axis2_updtsts_tdata : in std_logic_vector --
(C_S_AXIS_UPDSTS_TDATA_WIDTH-1 downto 0); --
s_axis2_updtsts_tvalid : in std_logic ; --
s_axis2_updtsts_tready : out std_logic ; --
s_axis2_updtsts_tlast : in std_logic ; --
--
--*********************************-- --
--** Channel Update Interface Out**-- --
--*********************************-- --
-- S2MM Stream Out To DataMover --
m_axis_updt_tdata : out std_logic_vector --
(C_M_AXIS_UPDT_DATA_WIDTH-1 downto 0); --
m_axis_updt_tlast : out std_logic ; --
m_axis_updt_tvalid : out std_logic ; --
m_axis_updt_tready : in std_logic --
);
end axi_sg_updt_noqueue;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_updt_noqueue is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- No Contstants Declared
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- Channel signals
signal writing_curdesc : std_logic := '0';
signal write_curdesc_lsb : std_logic := '0';
signal write_curdesc_msb : std_logic := '0';
signal updt_active_d1 : std_logic := '0';
signal updt_active_re : std_logic := '0';
type PNTR_STATE_TYPE is (IDLE,
READ_CURDESC_LSB,
READ_CURDESC_MSB,
WRITE_STATUS
);
signal pntr_cs : PNTR_STATE_TYPE;
signal pntr_ns : PNTR_STATE_TYPE;
signal writing_status : std_logic := '0';
signal curdesc_tready : std_logic := '0';
signal writing_status_d1 : std_logic := '0';
signal writing_status_re : std_logic := '0';
signal writing_status_re_ch1 : std_logic := '0';
signal writing_status_re_ch2 : std_logic := '0';
signal updt_active_int : std_logic := '0';
signal s_axis_updtptr_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tvalid_int : std_logic := '0';
signal s_axis_updtsts_tlast_int : std_logic := '0';
signal s_axis_updtptr_tdata_int : std_logic_vector (C_S_AXIS_UPDPTR_TDATA_WIDTH-1 downto 0) := (others => '0');
signal s_axis_qual : std_logic := '0';
signal s_axis2_qual : std_logic := '0';
signal m_axis_updt_tdata_mm2s : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_mm2s : std_logic ; --
signal m_axis_updt_tvalid_mm2s : std_logic ;
signal m_axis_updt_tdata_s2mm : std_logic_vector (31 downto 0); --
signal m_axis_updt_tlast_s2mm : std_logic ; --
signal m_axis_updt_tvalid_s2mm : std_logic ;
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
m_axis_updt_tdata <= m_axis_updt_tdata_mm2s when updt_active = '1' else
m_axis_updt_tdata_s2mm;
m_axis_updt_tvalid <= m_axis_updt_tvalid_mm2s when updt_active = '1' else
m_axis_updt_tvalid_s2mm;
m_axis_updt_tlast <= m_axis_updt_tlast_mm2s when updt_active = '1' else
m_axis_updt_tlast_s2mm;
updt_active_int <= updt_active or updt2_active;
s_axis_updtptr_tvalid_int <= s_axis_updtptr_tvalid or s_axis2_updtptr_tvalid;
s_axis_updtsts_tvalid_int <= s_axis_updtsts_tvalid or s_axis2_updtsts_tvalid;
s_axis_updtsts_tlast_int <= s_axis_updtsts_tlast or s_axis2_updtsts_tlast;
s_axis_qual <= s_axis_updtsts_tvalid and s_axis_updtsts_tlast and updt_active;
s_axis2_qual <= s_axis2_updtsts_tvalid and s_axis2_updtsts_tlast and updt2_active;
-- Asset active strobe on rising edge of update active
-- asertion. This kicks off the update process for
-- the channel
REG_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
updt_active_d1 <= '0';
else
updt_active_d1 <= updt_active or updt2_active;
end if;
end if;
end process REG_ACTIVE;
updt_active_re <= (updt_active or updt2_active) and not updt_active_d1;
-- Current Descriptor Pointer Fetch. This state machine controls
-- reading out the current pointer from the Queue or channel port
-- and writing it to the update manager for use in command
-- generation to the DataMover for Descriptor update.
CURDESC_PNTR_STATE : process(pntr_cs,
updt_active_int,
s_axis_updtptr_tvalid_int,
updt_active, updt2_active,
s_axis_qual, s_axis2_qual,
s_axis_updtptr_tvalid,
s_axis2_updtptr_tvalid,
s_axis_updtsts_tvalid_int,
m_axis_updt_tready)
begin
write_curdesc_lsb <= '0';
write_curdesc_msb <= '0';
writing_status <= '0';
writing_curdesc <= '0';
curdesc_tready <= '0';
pntr_ns <= pntr_cs;
case pntr_cs is
when IDLE =>
if((s_axis_updtptr_tvalid = '1' and updt_active = '1') or
(s_axis2_updtptr_tvalid = '1' and updt2_active = '1')) then
writing_curdesc <= '1';
pntr_ns <= READ_CURDESC_LSB;
else
pntr_ns <= IDLE;
end if;
---------------------------------------------------------------
-- Get lower current descriptor
when READ_CURDESC_LSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- on tvalid from Queue or channel port then register
-- lsb curdesc and setup to register msb curdesc
if(s_axis_updtptr_tvalid_int = '1' and updt_active_int = '1')then
write_curdesc_lsb <= '1';
-- pntr_ns <= READ_CURDESC_MSB;
pntr_ns <= WRITE_STATUS;
else
-- coverage off
pntr_ns <= READ_CURDESC_LSB;
-- coverage on
end if;
-- coverage off
---------------------------------------------------------------
-- Get upper current descriptor
when READ_CURDESC_MSB =>
curdesc_tready <= '1';
writing_curdesc <= '1';
-- On tvalid from Queue or channel port then register
-- msb. This will also write curdesc out to update
-- manager.
if(s_axis_updtptr_tvalid_int = '1')then
write_curdesc_msb <= '1';
pntr_ns <= WRITE_STATUS;
else
pntr_ns <= READ_CURDESC_MSB;
end if;
-- coverage on
---------------------------------------------------------------
-- Hold in this state until remainder of descriptor is
-- written out.
when WRITE_STATUS =>
writing_status <= '1'; --s_axis_updtsts_tvalid_int;
if((s_axis_qual = '1' and m_axis_updt_tready = '1') or
(s_axis2_qual = '1' and m_axis_updt_tready = '1')) then
pntr_ns <= IDLE;
else
pntr_ns <= WRITE_STATUS;
end if;
-- coverage off
when others =>
pntr_ns <= IDLE;
-- coverage on
end case;
end process CURDESC_PNTR_STATE;
---------------------------------------------------------------------------
-- Register for CURDESC Pointer state machine
---------------------------------------------------------------------------
REG_PNTR_STATES : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
pntr_cs <= IDLE;
else
pntr_cs <= pntr_ns;
end if;
end if;
end process REG_PNTR_STATES;
-- Status stream signals
m_axis_updt_tdata_mm2s <= s_axis_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_mm2s <= s_axis_updtsts_tvalid and writing_status;
m_axis_updt_tlast_mm2s <= s_axis_updtsts_tlast and writing_status;
s_axis_updtsts_tready <= m_axis_updt_tready and writing_status and updt_active;
-- Pointer stream signals
s_axis_updtptr_tready <= curdesc_tready and updt_active;
-- Indicate need for channel service for update state machine
updt_queue_empty <= not (s_axis_updtsts_tvalid); -- and writing_status);
m_axis_updt_tdata_s2mm <= s_axis2_updtsts_tdata(C_S_AXIS_UPDSTS_TDATA_WIDTH-2 downto 0);
m_axis_updt_tvalid_s2mm <= s_axis2_updtsts_tvalid and writing_status;
m_axis_updt_tlast_s2mm <= s_axis2_updtsts_tlast and writing_status;
s_axis2_updtsts_tready <= m_axis_updt_tready and writing_status and updt2_active;
-- Pointer stream signals
s_axis2_updtptr_tready <= curdesc_tready and updt2_active;
-- Indicate need for channel service for update state machine
updt2_queue_empty <= not (s_axis2_updtsts_tvalid); -- and writing_status);
--*********************************************************************
--** POINTER CAPTURE LOGIC
--*********************************************************************
s_axis_updtptr_tdata_int <= s_axis_updtptr_tdata when (updt_active = '1') else
s_axis2_updtptr_tdata;
---------------------------------------------------------------------------
-- Write lower order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_LSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(31 downto 0) <= (others => '0');
-- Capture lower pointer from FIFO or channel port
elsif(write_curdesc_lsb = '1')then
updt_curdesc(31 downto 0) <= s_axis_updtptr_tdata_int(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
end if;
end if;
end process REG_LSB_CURPNTR;
---------------------------------------------------------------------------
-- 64 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_UPPER_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 64 generate
begin
---------------------------------------------------------------------------
-- Write upper order Next Descriptor Pointer out to pntr_mngr
---------------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc(63 downto 32) <= (others => '0');
updt_curdesc_wren <= '0';
-- Capture upper pointer from FIFO or channel port
-- and also write curdesc out
elsif(write_curdesc_msb = '1')then
updt_curdesc(63 downto 32) <= s_axis_updtptr_tdata(C_S_AXIS_UPDPTR_TDATA_WIDTH - 1 downto 0);
updt_curdesc_wren <= '1';
-- Assert tready/wren for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_UPPER_MSB_CURDESC;
---------------------------------------------------------------------------
-- 32 Bit Scatter Gather addresses enabled
---------------------------------------------------------------------------
GEN_NO_UPR_MSB_CURDESC : if C_M_AXI_SG_ADDR_WIDTH = 32 generate
begin
-----------------------------------------------------------------------
-- No upper order therefore dump fetched word and write pntr lower next
-- pointer to pntr mngr
-----------------------------------------------------------------------
REG_MSB_CURPNTR : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' )then
updt_curdesc_wren <= '0';
-- Throw away second word, only write curdesc out with msb
-- set to zero
elsif(write_curdesc_lsb = '1')then
-- elsif(write_curdesc_msb = '1')then
updt_curdesc_wren <= '1';
-- Assert for only 1 clock
else
updt_curdesc_wren <= '0';
end if;
end if;
end process REG_MSB_CURPNTR;
end generate GEN_NO_UPR_MSB_CURDESC;
--*********************************************************************
--** ERROR CAPTURE LOGIC
--*********************************************************************
-----------------------------------------------------------------------
-- Generate rising edge pulse on writing status signal. This will
-- assert at the beginning of the status write. Coupled with status
-- fifo set to first word fall through status will be on dout
-- regardless of target ready.
-----------------------------------------------------------------------
REG_WRITE_STATUS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
writing_status_d1 <= '0';
else
writing_status_d1 <= writing_status;
end if;
end if;
end process REG_WRITE_STATUS;
writing_status_re <= writing_status and not writing_status_d1;
writing_status_re_ch1 <= writing_status_re and updt_active;
writing_status_re_ch2 <= writing_status_re and updt2_active;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt_ioc_irq_set = '1')then
updt_ioc <= '0';
elsif(writing_status_re_ch1 = '1')then
updt_ioc <= s_axis_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_interr_set = '1')then
dma_interr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_interr <= s_axis_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_slverr_set = '1')then
dma_slverr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_slverr <= s_axis_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma_decerr_set = '1')then
dma_decerr <= '0';
elsif(writing_status_re_ch1 = '1')then
dma_decerr <= s_axis_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE_DMADEC_ERROR;
---------------------------------------------------------------------------
-- Caputure IOC begin set
---------------------------------------------------------------------------
REG2_IOC_PROCESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or updt2_ioc_irq_set = '1')then
updt2_ioc <= '0';
elsif(writing_status_re_ch2 = '1')then
updt2_ioc <= s_axis2_updtsts_tdata(DESC_IOC_TAG_BIT);
end if;
end if;
end process REG2_IOC_PROCESS;
-----------------------------------------------------------------------
-- Capture DMA Internal Errors
-----------------------------------------------------------------------
CAPTURE2_DMAINT_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_interr_set = '1')then
dma2_interr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_interr <= s_axis2_updtsts_tdata(DESC_STS_INTERR_BIT);
end if;
end if;
end process CAPTURE2_DMAINT_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Slave Errors
-----------------------------------------------------------------------
CAPTURE2_DMASLV_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_slverr_set = '1')then
dma2_slverr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_slverr <= s_axis2_updtsts_tdata(DESC_STS_SLVERR_BIT);
end if;
end if;
end process CAPTURE2_DMASLV_ERROR;
-----------------------------------------------------------------------
-- Capture DMA Decode Errors
-----------------------------------------------------------------------
CAPTURE2_DMADEC_ERROR: process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or dma2_decerr_set = '1')then
dma2_decerr <= '0';
elsif(writing_status_re_ch2 = '1')then
dma2_decerr <= s_axis2_updtsts_tdata(DESC_STS_DECERR_BIT);
end if;
end if;
end process CAPTURE2_DMADEC_ERROR;
end implementation;
|
--
-- WISHBONE revB2 compiant I2C master core
--
-- author: Richard Herveille
-- rev. 0.1 based on simple_i2c
-- rev. 0.2 april 27th 2001, fixed incomplete sensitivity list on assign_dato process (thanks to Matt Oseman)
-- rev. 0.3 may 4th 2001, fixed typo rev.0.2 txt -> txr
-- rev. 0.4 may 8th, added some remarks, fixed some sensitivity list issues
--
--
-- Changes compared to simple_i2c
-- 1) WISHBONE interface
-- 2) added start/stop detection
-- 3) added busy bit
-- 4) removed automatic tri-state buffer insertion (for ASIC support)
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity wishbone_i2c_master is
port (
-- wishbone signals
CLK_I : in std_logic; -- master clock input
RST_I : in std_logic := '0'; -- synchronous active high reset
nRESET: in std_logic := '1'; -- asynchronous active low reset
ADR_I : in std_logic_vector(1 downto 0); -- lower address bits
DAT_I : in std_logic_vector(15 downto 0); -- Databus input
DAT_O : out std_logic_vector(15 downto 0); -- Databus output
SEL_I : in std_logic_vector(1 downto 0); -- Byte select signals
WE_I : in std_logic; -- Write enable input
STB_I : in std_logic; -- Strobe signals / core select signal
CYC_I : in std_logic; -- Valid bus cycle input
ACK_O : out std_logic; -- Bus cycle acknowledge output
INTA_O : out std_logic; -- interrupt request output signal
-- I2C signals
SCLi : in std_logic; -- I2C clock line
SCLo : out std_logic;
SDAi : in std_logic; -- I2C data line
SDAo : out std_logic
);
end entity wishbone_i2c_master;
architecture structural of wishbone_i2c_master is
component byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
ena,
start,
stop,
read,
write,
ack_in : std_logic;
Din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
Dout : out std_logic_vector(7 downto 0);
i2c_busy : out std_logic;
-- i2c signals
SCLi : in std_logic; -- I2C clock line
SCLo : out std_logic;
SDAi : in std_logic; -- I2C data line
SDAo : out std_logic
);
end component byte_ctrl;
-- registers
signal prer : unsigned(15 downto 0); -- clock prescale register
signal ctr : std_logic_vector(7 downto 0); -- control register
signal txr : std_logic_vector(7 downto 0); -- transmit register
signal rxr : std_logic_vector(7 downto 0); -- receive register
signal cr : std_logic_vector(7 downto 0); -- command register
signal sr : std_logic_vector(7 downto 0); -- status register
-- done signal: command completed, clear command register
signal done : std_logic;
-- command register signals
signal sta, sto, rd, wr, ack, iack : std_logic;
-- core enable signal
signal core_en : std_logic;
-- status register signals
signal irxack, rxack : std_logic; -- received aknowledge from slave
signal tip : std_logic; -- transfer in progress
signal irq_flag : std_logic; -- interrupt pending flag
signal i2c_busy : std_logic; -- bus busy (start signal detected)
begin
-- generate acknowledge output signal
ACK_O <= STB_I; -- since timing is always honored
-- assign DAT_O
assign_dato : process(ADR_I, prer, ctr, txr, cr, rxr, sr)
begin
case ADR_I is
when "00" =>
DAT_O <= std_logic_vector(prer);
when "01" =>
DAT_O <= (x"00" & ctr);
when "10" =>
DAT_O <= (txr & cr);
when "11" =>
DAT_O <= (rxr & sr);
when others =>
DAT_O <= (others => 'X'); -- for simulation only
end case;
end process assign_dato;
-- registers block
regs_block: block
-- address decode signals
signal we_a0, we_a1, we_a2, we_a3 : std_logic;
begin
-- decode address lines
we_a0 <= CYC_I and STB_I and WE_I and not ADR_I(1) and not ADR_I(0); -- 00
we_a1 <= CYC_I and STB_I and WE_I and not ADR_I(1) and ADR_I(0); -- 01
we_a2 <= CYC_I and STB_I and WE_I and ADR_I(1) and not ADR_I(0); -- 10
we_a3 <= CYC_I and STB_I and WE_I and ADR_I(1) and ADR_I(0); -- 11
-- store data in writeable registers
-- prescale register
write_prer: process(nRESET, CLK_I)
begin
if (nRESET = '0') then
prer <= (others => '1');
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
prer <= (others => '1');
else
if ( (we_a0 and SEL_I(1)) = '1') then
prer(15 downto 8) <= unsigned(DAT_I(15 downto 8));
end if;
if ( (we_a0 and SEL_I(0)) = '1') then
prer(7 downto 0) <= unsigned(DAT_I(7 downto 0));
end if;
end if;
end if;
end process write_prer;
-- control register
write_ctr: process(nRESET, CLK_I)
begin
if (nRESET = '0') then
ctr <= (others => '0');
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
ctr <= (others => '0');
else
if ( (we_a1 and SEL_I(0)) = '1') then
ctr <= DAT_I(7 downto 0);
end if;
end if;
end if;
end process write_ctr;
-- transmit register
write_txr: process(nRESET, CLK_I)
begin
if (nRESET = '0') then
txr <= (others => '0');
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
txr <= (others => '0');
else
if ( (we_a2 and SEL_I(1)) = '1') then
txr <= DAT_I(15 downto 8);
end if;
end if;
end if;
end process write_txr;
-- command register
write_cr: process(nRESET, CLK_I)
begin
if (nRESET = '0') then
cr <= (others => '0'); -- asynchronous clear
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
cr <= (others => '0'); -- synchronous clear
else
if ( (we_a2 and SEL_I(0)) = '1') then
if (core_en = '1') then
cr <= DAT_I(7 downto 0); -- only take new commands when I2C core is enabled, pending commands are finished
end if;
else
if (done = '0') then
cr(7 downto 4) <= cr(7 downto 4);
else
cr(7 downto 0) <= (others => '0'); -- clear command_bits when command completed
end if;
cr(2 downto 1) <= cr(2 downto 1);
cr(0) <= cr(0) and irq_flag; -- automatically clear when irq_flag is cleared
end if;
end if;
end if;
end process write_cr;
end block regs_block;
-- decode command register
sta <= cr(7);
sto <= cr(6);
rd <= cr(5);
wr <= cr(4);
ack <= cr(3);
iack <= cr(0);
-- decode control register
core_en <= ctr(7);
-- hookup byte controller block
u1: byte_ctrl port map (clk => CLK_I,
rst => RST_I,
nReset => nRESET,
clk_cnt => prer,
ena => core_en,
start => sta,
stop => sto,
read => rd,
write => wr,
ack_in => ack,
i2c_busy => i2c_busy,
Din => txr,
cmd_ack => done,
ack_out => irxack,
Dout => rxr, -- note: maybe store rxr in registers ??
SCLi => SCLi,
SCLo => SCLo,
SDAi => SDAi,
SDAo => SDAo);
-- status register block + interrupt request signal
st_block : block
begin
-- generate status register bits
gen_sr_bits: process (CLK_I, nRESET)
begin
if (nRESET = '0') then
rxack <= '0';
tip <= '0';
irq_flag <= '0';
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
rxack <= '0';
tip <= '0';
irq_flag <= '0';
else
rxack <= irxack;
tip <= ( rd or wr );
irq_flag <= (done or irq_flag) and not iack; -- interrupt request flag is always generated
end if;
end if;
end process gen_sr_bits;
-- generate interrupt request signals
gen_irq: process (CLK_I, nRESET)
begin
if (nRESET = '0') then
INTA_O <= '0';
elsif (CLK_I'event and CLK_I = '1') then
if (RST_I = '1') then
INTA_O <= '0';
else
INTA_O <= irq_flag and ctr(6); -- interrupt signal is only generated when IEN (interrupt enable bit) is set
end if;
end if;
end process gen_irq;
-- assign status register bits
sr(7) <= rxack;
sr(6) <= i2c_busy;
sr(5 downto 2) <= (others => '0'); -- reserved
sr(1) <= tip;
sr(0) <= irq_flag;
end block;
end architecture structural;
--
------------------------------------------
-- Byte controller section
------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity byte_ctrl is
port (
clk : in std_logic;
rst : in std_logic; -- synchronous active high reset (WISHBONE compatible)
nReset : in std_logic; -- asynchornous active low reset (FPGA compatible)
clk_cnt : in unsigned(15 downto 0); -- 4x SCL
-- input signals
ena,
start,
stop,
read,
write,
ack_in : std_logic;
Din : in std_logic_vector(7 downto 0);
-- output signals
cmd_ack : out std_logic;
ack_out : out std_logic;
Dout : out std_logic_vector(7 downto 0);
i2c_busy : out std_logic;
-- i2c signals
SCLi : in std_logic; -- I2C clock line
SCLo : out std_logic;
SDAi : in std_logic; -- I2C data line
SDAo : out std_logic
);
end entity byte_ctrl;
architecture structural of byte_ctrl is
component bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
ena : in std_logic; -- core enable signal
cmd : in std_logic_vector(2 downto 0);
cmd_ack : out std_logic;
busy : out std_logic;
Din : in std_logic;
Dout : out std_logic;
SCLin : in std_logic; -- I2C clock line
SCLout : out std_logic;
SDAin : in std_logic; -- I2C data line
SDAout : out std_logic
);
end component bit_ctrl;
-- commands for i2c_core
constant CMD_NOP : std_logic_vector(2 downto 0) := "000";
constant CMD_START : std_logic_vector(2 downto 0) := "010";
constant CMD_STOP : std_logic_vector(2 downto 0) := "011";
constant CMD_READ : std_logic_vector(2 downto 0) := "100";
constant CMD_WRITE : std_logic_vector(2 downto 0) := "101";
-- signals for bit_controller
signal core_cmd : std_logic_vector(2 downto 0);
signal core_ack, core_txd, core_rxd : std_logic;
-- signals for shift register
signal sr : std_logic_vector(7 downto 0); -- 8bit shift register
signal shift, ld : std_logic;
-- signals for state machine
signal go, host_ack : std_logic;
begin
-- hookup bit_controller
u1: bit_ctrl port map (clk, rst, nReset, clk_cnt, ena, core_cmd, core_ack, i2c_busy, core_txd, core_rxd, SCLi, SCLo, SDAi, SDAo);
-- generate host-command-acknowledge
cmd_ack <= host_ack;
-- generate go-signal
go <= (read or write) and not host_ack;
-- assign Dout output to shift-register
Dout <= sr;
-- assign ack_out output to core_rxd (contains last received bit)
ack_out <= core_rxd;
-- generate shift register
shift_register: process(clk)
begin
if (clk'event and clk = '1') then
if (ld = '1') then
sr <= din;
elsif (shift = '1') then
sr <= (sr(6 downto 0) & core_rxd);
end if;
end if;
end process shift_register;
--
-- state machine
--
statemachine : block
type states is (st_idle, st_start, st_read, st_write, st_ack, st_stop);
signal state : states;
signal dcnt : unsigned(2 downto 0);
begin
--
-- command interpreter, translate complex commands into simpler I2C commands
--
nxt_state_decoder: process(clk, nReset, state)
variable nxt_state : states;
variable idcnt : unsigned(2 downto 0);
variable ihost_ack : std_logic;
variable icore_cmd : std_logic_vector(2 downto 0);
variable icore_txd : std_logic;
variable ishift, iload : std_logic;
begin
-- 8 databits (1byte) of data to shift-in/out
idcnt := dcnt;
-- no acknowledge (until command complete)
ihost_ack := '0';
icore_txd := core_txd;
-- keep current command to bit_controller
icore_cmd := core_cmd;
-- no shifting or loading of shift-register
ishift := '0';
iload := '0';
-- keep current state;
nxt_state := state;
case state is
when st_idle =>
if (go = '1') then
if (start = '1') then
nxt_state := st_start;
icore_cmd := CMD_START;
elsif (read = '1') then
nxt_state := st_read;
icore_cmd := CMD_READ;
idcnt := "111";
else
nxt_state := st_write;
icore_cmd := CMD_WRITE;
idcnt := "111";
iload := '1';
end if;
end if;
when st_start =>
if (core_ack = '1') then
if (read = '1') then
nxt_state := st_read;
icore_cmd := CMD_READ;
idcnt := "111";
else
nxt_state := st_write;
icore_cmd := CMD_WRITE;
idcnt := "111";
iload := '1';
end if;
end if;
when st_write =>
if (core_ack = '1') then
idcnt := dcnt -1; -- count down Data_counter
icore_txd := sr(7);
if (dcnt = 0) then
nxt_state := st_ack;
icore_cmd := CMD_READ;
else
ishift := '1';
-- icore_txd := sr(7);
end if;
end if;
when st_read =>
if (core_ack = '1') then
idcnt := dcnt -1; -- count down Data_counter
ishift := '1';
if (dcnt = 0) then
nxt_state := st_ack;
icore_cmd := CMD_WRITE;
icore_txd := ack_in;
end if;
end if;
when st_ack =>
if (core_ack = '1') then
-- generate command acknowledge signal
ihost_ack := '1';
-- Perform an additional shift, needed for 'read' (store last received bit in shift register)
ishift := '1';
-- check for stop; Should a STOP command be generated ?
if (stop = '1') then
nxt_state := st_stop;
icore_cmd := CMD_STOP;
else
nxt_state := st_idle;
icore_cmd := CMD_NOP;
end if;
end if;
when st_stop =>
if (core_ack = '1') then
nxt_state := st_idle;
icore_cmd := CMD_NOP;
end if;
when others => -- illegal states
nxt_state := st_idle;
icore_cmd := CMD_NOP;
end case;
-- generate registers
if (nReset = '0') then
core_cmd <= CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
dcnt <= "111";
host_ack <= '0';
state <= st_idle;
elsif (clk'event and clk = '1') then
if (rst = '1') then
core_cmd <= CMD_NOP;
core_txd <= '0';
shift <= '0';
ld <= '0';
dcnt <= "111";
host_ack <= '0';
state <= st_idle;
else
state <= nxt_state;
dcnt <= idcnt;
shift <= ishift;
ld <= iload;
core_cmd <= icore_cmd;
core_txd <= icore_txd;
host_ack <= ihost_ack;
end if;
end if;
end process nxt_state_decoder;
end block statemachine;
end architecture structural;
--
-------------------------------------
-- Bit controller section
------------------------------------
--
-- Translate simple commands into SCL/SDA transitions
-- Each command has 5 states, A/B/C/D/idle
--
-- start: SCL ~~~~~~~~~~\____
-- SDA ~~~~~~~~\______
-- x | A | B | C | D | i
--
-- repstart SCL ____/~~~~\___
-- SDA __/~~~\______
-- x | A | B | C | D | i
--
-- stop SCL ____/~~~~~~~~
-- SDA ==\____/~~~~~
-- x | A | B | C | D | i
--
--- write SCL ____/~~~~\____
-- SDA ==X=========X=
-- x | A | B | C | D | i
--
--- read SCL ____/~~~~\____
-- SDA XXXX=====XXXX
-- x | A | B | C | D | i
--
-- Timing: Normal mode Fast mode
-----------------------------------------------------------------
-- Fscl 100KHz 400KHz
-- Th_scl 4.0us 0.6us High period of SCL
-- Tl_scl 4.7us 1.3us Low period of SCL
-- Tsu:sta 4.7us 0.6us setup time for a repeated start condition
-- Tsu:sto 4.0us 0.6us setup time for a stop conditon
-- Tbuf 4.7us 1.3us Bus free time between a stop and start condition
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity bit_ctrl is
port (
clk : in std_logic;
rst : in std_logic;
nReset : in std_logic;
clk_cnt : in unsigned(15 downto 0); -- clock prescale value
ena : in std_logic; -- core enable signal
cmd : in std_logic_vector(2 downto 0);
cmd_ack : out std_logic;
busy : out std_logic;
Din : in std_logic;
Dout : out std_logic;
-- i2c lines
SCLin : in std_logic; -- I2C clock line
SCLout : out std_logic;
SDAin : in std_logic; -- I2C data line
SDAout : out std_logic
);
end entity bit_ctrl;
architecture structural of bit_ctrl is
constant CMD_NOP : std_logic_vector(2 downto 0) := "000";
constant CMD_START : std_logic_vector(2 downto 0) := "010";
constant CMD_STOP : std_logic_vector(2 downto 0) := "011";
constant CMD_READ : std_logic_vector(2 downto 0) := "100";
constant CMD_WRITE : std_logic_vector(2 downto 0) := "101";
type cmds is (idle, start_a, start_b, start_c, start_d, stop_a, stop_b, stop_c, rd_a, rd_b, rd_c, rd_d, wr_a, wr_b, wr_c, wr_d);
signal state : cmds;
signal SCLo, SDAo : std_logic; -- internal I2C lines
signal sSCL, sSDA : std_logic; -- synchronized SCL and SDA inputs
signal txd : std_logic; -- transmit bit
signal clk_en, slave_wait :std_logic; -- clock generation signals
-- signal cnt : unsigned(15 downto 0) := clk_cnt; -- clock divider counter (simulation)
signal cnt : unsigned(15 downto 0); -- clock divider counter (synthesis)
begin
-- synchronize SCL and SDA inputs
synch_SCL_SDA: process(clk)
begin
if (clk'event and clk = '1') then
sSCL <= SCLin;
sSDA <= SDAin;
end if;
end process synch_SCL_SDA;
-- whenever the slave is not ready it can delay the cycle by pulling SCL low
slave_wait <= '1' when ( (SCLo = '1') and (sSCL = '0') ) else '0';
-- generate clk enable signal
gen_clken: process(clk, nReset)
begin
if (nReset = '0') then
cnt <= (others => '0');
clk_en <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
cnt <= (others => '0');
clk_en <= '1';
else
if ( (cnt = 0) or (ena = '0') ) then
clk_en <= '1';
cnt <= clk_cnt;
else
if (slave_wait = '0') then
cnt <= cnt -1;
end if;
clk_en <= '0';
end if;
end if;
end if;
end process gen_clken;
-- generate bus status controller
bus_status_ctrl: block
signal dSDA : std_logic;
signal sta_condition : std_logic;
signal sto_condition : std_logic;
signal ibusy : std_logic;
begin
-- detect start condition => detect falling edge on SDA while SCL is high
-- detect stop condition => detect rising edge on SDA while SCL is high
det_sta_sto: process(clk)
begin
if (clk'event and clk = '1') then
dSDA <= sSDA; -- generate a delayed version of sSDA
sta_condition <= (not sSDA and dSDA) and sSCL;
sto_condition <= (sSDA and not dSDA) and sSCL;
end if;
end process det_sta_sto;
-- generate bus busy signal
gen_busy: process(clk, nReset)
begin
if (nReset = '0') then
ibusy <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
ibusy <= '0';
else
ibusy <= (sta_condition or ibusy) and not sto_condition;
end if;
end if;
end process gen_busy;
-- assign output
busy <= ibusy;
end block bus_status_ctrl;
-- generate statemachine
nxt_state_decoder : process (clk, nReset, state, cmd)
variable nxt_state : cmds;
variable icmd_ack, store_sda : std_logic;
variable itxd : std_logic;
begin
nxt_state := state;
icmd_ack := '0'; -- default no acknowledge
store_sda := '0';
itxd := txd;
case (state) is
-- idle
when idle =>
case cmd is
when CMD_START =>
nxt_state := start_a;
icmd_ack := '1'; -- command completed
when CMD_STOP =>
nxt_state := stop_a;
icmd_ack := '1'; -- command completed
when CMD_WRITE =>
nxt_state := wr_a;
icmd_ack := '1'; -- command completed
itxd := Din;
when CMD_READ =>
nxt_state := rd_a;
icmd_ack := '1'; -- command completed
when others =>
nxt_state := idle;
-- don't acknowledge NOP command icmd_ack := '1'; -- command completed
end case;
-- start
when start_a =>
nxt_state := start_b;
when start_b =>
nxt_state := start_c;
when start_c =>
nxt_state := start_d;
when start_d =>
nxt_state := idle;
-- stop
when stop_a =>
nxt_state := stop_b;
when stop_b =>
nxt_state := stop_c;
when stop_c =>
nxt_state := idle;
-- read
when rd_a =>
nxt_state := rd_b;
when rd_b =>
nxt_state := rd_c;
when rd_c =>
nxt_state := rd_d;
store_sda := '1';
when rd_d =>
nxt_state := idle;
-- write
when wr_a =>
nxt_state := wr_b;
when wr_b =>
nxt_state := wr_c;
when wr_c =>
nxt_state := wr_d;
when wr_d =>
nxt_state := idle;
end case;
-- generate regs
if (nReset = '0') then
state <= idle;
cmd_ack <= '0';
txd <= '0';
Dout <= '0';
elsif (clk'event and clk = '1') then
if (rst = '1') then
state <= idle;
cmd_ack <= '0';
txd <= '0';
Dout <= '0';
else
if (clk_en = '1') then
state <= nxt_state;
txd <= itxd;
if (store_sda = '1') then
Dout <= sSDA;
end if;
end if;
cmd_ack <= icmd_ack and clk_en;
end if;
end if;
end process nxt_state_decoder;
--
-- convert states to SCL and SDA signals
--
output_decoder: process (clk, nReset, state)
variable iscl, isda : std_logic;
begin
case (state) is
when idle =>
iscl := SCLo; -- keep SCL in same state
isda := sSDA; -- keep SDA in same state
-- start
when start_a =>
iscl := SCLo; -- keep SCL in same state (for repeated start)
isda := '1'; -- set SDA high
when start_b =>
iscl := '1'; -- set SCL high
isda := '1'; -- keep SDA high
when start_c =>
iscl := '1'; -- keep SCL high
isda := '0'; -- sel SDA low
when start_d =>
iscl := '0'; -- set SCL low
isda := '0'; -- keep SDA low
-- stop
when stop_a =>
iscl := '0'; -- keep SCL disabled
isda := '0'; -- set SDA low
when stop_b =>
iscl := '1'; -- set SCL high
isda := '0'; -- keep SDA low
when stop_c =>
iscl := '1'; -- keep SCL high
isda := '1'; -- set SDA high
-- write
when wr_a =>
iscl := '0'; -- keep SCL low
isda := Din;
when wr_b =>
iscl := '1'; -- set SCL high
isda := Din;
when wr_c =>
iscl := '1'; -- keep SCL high
isda := Din;
when wr_d =>
iscl := '0'; -- set SCL low
isda := Din;
-- read
when rd_a =>
iscl := '0'; -- keep SCL low
isda := '1'; -- tri-state SDA
when rd_b =>
iscl := '1'; -- set SCL high
isda := '1'; -- tri-state SDA
when rd_c =>
iscl := '1'; -- keep SCL high
isda := '1'; -- tri-state SDA
when rd_d =>
iscl := '0'; -- set SCL low
isda := '1'; -- tri-state SDA
end case;
-- generate registers
if (nReset = '0') then
SCLo <= '1';
SDAo <= '1';
elsif (clk'event and clk = '1') then
if (rst = '1') then
SCLo <= '1';
SDAo <= '1';
else
if (clk_en = '1') then
SCLo <= iscl;
SDAo <= isda;
end if;
end if;
end if;
end process output_decoder;
-- assign outputs
SCLout <= SCLo;
SDAout <= SDAo;
end architecture structural;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
C : in std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
process(A) is
begin
case A is
when '0' => case B is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
when '1' => case C is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
end case;
end process;
end behv;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity adder is
port(A : in std_logic;
B : in std_logic;
C : in std_logic;
sum : out std_logic);
end adder;
architecture behv of adder is
begin
process(A) is
begin
case A is
when '0' => case B is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
when '1' => case C is
when '0' => sum <= '0';
when '1' => sum <= '1';
end case;
end case;
end process;
end behv;
|
-----------------------------------------------------------------------------------------
-- Project : Invent a Chip
-- Module : Toplevel
-- Author : Jan D�rre
-- Last update : 12.01.2015
-- Description : -
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
use work.iac_pkg.all;
entity iac_toplevel is
generic (
SIMULATION : boolean := false
);
port (
-- global signals
clock_ext_50 : in std_ulogic;
clock_ext2_50 : in std_ulogic;
clock_ext3_50 : in std_ulogic;
reset_n : in std_ulogic; -- (key3)
-- 7_seg
hex0_n : out std_ulogic_vector(6 downto 0);
hex1_n : out std_ulogic_vector(6 downto 0);
hex2_n : out std_ulogic_vector(6 downto 0);
hex3_n : out std_ulogic_vector(6 downto 0);
hex4_n : out std_ulogic_vector(6 downto 0);
hex5_n : out std_ulogic_vector(6 downto 0);
hex6_n : out std_ulogic_vector(6 downto 0);
hex7_n : out std_ulogic_vector(6 downto 0);
-- gpio
gpio : inout std_logic_vector(15 downto 0);
-- lcd
lcd_en : out std_ulogic;
lcd_rs : out std_ulogic;
lcd_rw : out std_ulogic;
lcd_on : out std_ulogic;
lcd_blon : out std_ulogic;
lcd_dat : out std_ulogic_vector(7 downto 0);
-- led/switches/keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key_n : in std_ulogic_vector(2 downto 0);
-- adc_dac
exb_adc_switch : out std_ulogic_vector(2 downto 0);
exb_adc_en_n : out std_ulogic;
exb_dac_ldac_n : out std_ulogic;
exb_spi_clk : out std_ulogic;
exb_spi_mosi : out std_ulogic;
exb_spi_miso : in std_logic;
exb_spi_cs_adc_n : out std_ulogic;
exb_spi_cs_dac_n : out std_ulogic;
-- sram
sram_ce_n : out std_ulogic;
sram_oe_n : out std_ulogic;
sram_we_n : out std_ulogic;
sram_ub_n : out std_ulogic;
sram_lb_n : out std_ulogic;
sram_addr : out std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0);
-- uart
uart_rts : in std_ulogic;
uart_cts : out std_ulogic;
uart_rxd : in std_ulogic;
uart_txd : out std_ulogic;
-- audio
aud_xclk : out std_ulogic;
aud_bclk : in std_ulogic;
aud_adc_lrck : in std_ulogic;
aud_adc_dat : in std_ulogic;
aud_dac_lrck : in std_ulogic;
aud_dac_dat : out std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : inout std_logic;
-- infrared
irda_rxd : in std_ulogic
);
end iac_toplevel;
architecture rtl of iac_toplevel is
-- clock
signal clk_50 : std_ulogic; -- 50 MHz
signal clk_audio_12 : std_ulogic; -- 12 MHz
signal pll_locked : std_ulogic;
-- reset
signal reset : std_ulogic;
signal reset_intern : std_ulogic;
signal reset_n_intern : std_ulogic;
-- 7-Seg Bus Signals
signal sevenseg_cs : std_ulogic;
signal sevenseg_wr : std_ulogic;
signal sevenseg_addr : std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
signal sevenseg_din : std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
signal sevenseg_dout : std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC Bus Signals
signal adc_dac_cs : std_ulogic;
signal adc_dac_wr : std_ulogic;
signal adc_dac_addr : std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
signal adc_dac_din : std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
signal adc_dac_dout : std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- Audio Bus Signals
signal audio_cs : std_ulogic;
signal audio_wr : std_ulogic;
signal audio_addr : std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
signal audio_din : std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
signal audio_dout : std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
signal audio_irq_left : std_ulogic;
signal audio_irq_right : std_ulogic;
signal audio_ack_left : std_ulogic;
signal audio_ack_right : std_ulogic;
-- Infra-red Receiver
signal ir_cs : std_ulogic;
signal ir_wr : std_ulogic;
signal ir_addr : std_ulogic_vector(CW_ADDR_IR-1 downto 0);
signal ir_din : std_ulogic_vector(CW_DATA_IR-1 downto 0);
signal ir_dout : std_ulogic_vector(CW_DATA_IR-1 downto 0);
signal ir_irq_rx : std_ulogic;
signal ir_ack_rx : std_ulogic;
-- LCD Bus Signals
signal lcd_cs : std_ulogic;
signal lcd_wr : std_ulogic;
signal lcd_addr : std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
signal lcd_din : std_ulogic_vector(CW_DATA_LCD-1 downto 0);
signal lcd_dout : std_ulogic_vector(CW_DATA_LCD-1 downto 0);
signal lcd_irq_rdy : std_ulogic;
signal lcd_ack_rdy : std_ulogic;
-- SRAM Bus Signals
signal sram_cs : std_ulogic;
signal sram_wr : std_ulogic;
signal sram_adr : std_ulogic_vector(CW_ADDR_SRAM-1 downto 0); -- slightly different name, because of a conflict with the entity
signal sram_din : std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
signal sram_dout : std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART Bus Signals
signal uart_cs : std_ulogic;
signal uart_wr : std_ulogic;
signal uart_addr : std_ulogic_vector(CW_ADDR_UART-1 downto 0);
signal uart_din : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_dout : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal uart_irq_rx : std_ulogic;
signal uart_irq_tx : std_ulogic;
signal uart_ack_rx : std_ulogic;
signal uart_ack_tx : std_ulogic;
-- mux data signals for the case an interface is disabled
signal sevenseg_dout_wire : std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
signal adc_dac_dout_wire : std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
signal ir_dout_wire : std_ulogic_vector(CW_DATA_IR-1 downto 0);
signal lcd_dout_wire : std_ulogic_vector(CW_DATA_LCD-1 downto 0);
signal sram_dout_wire : std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
signal uart_dout_wire : std_ulogic_vector(CW_DATA_UART-1 downto 0);
signal audio_dout_wire : std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
signal audio_irq_left_wire : std_ulogic;
signal audio_irq_right_wire : std_ulogic;
signal ir_irq_rx_wire : std_ulogic;
signal lcd_irq_rdy_wire : std_ulogic;
signal uart_irq_rx_wire : std_ulogic;
signal uart_irq_tx_wire : std_ulogic;
-- key to revert key_n
signal key : std_ulogic_vector(2 downto 0);
-- register to sync async input signals
signal key_reg : std_ulogic_vector(2 downto 0);
signal switch_reg : std_ulogic_vector(17 downto 0);
-- gpio
component gpio_switcher is
port (
gpio : inout std_logic_vector(15 downto 0);
gp_ctrl : in std_ulogic_vector(15 downto 0);
gp_in : out std_ulogic_vector(15 downto 0);
gp_out : in std_ulogic_vector(15 downto 0)
);
end component gpio_switcher;
signal gp_ctrl : std_ulogic_vector(15 downto 0);
signal gp_out : std_ulogic_vector(15 downto 0);
signal gp_in : std_ulogic_vector(15 downto 0);
-- PLL (clk_50, clk_audio_12)
component pll is
port (
areset : in std_ulogic;
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c1 : out std_ulogic;
locked : out std_ulogic
);
end component pll;
-- components
component invent_a_chip is
port (
-- Global Signals
clock : in std_ulogic;
reset : in std_ulogic;
-- Interface Signals
-- 7-Seg
sevenseg_cs : out std_ulogic;
sevenseg_wr : out std_ulogic;
sevenseg_addr : out std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
sevenseg_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
sevenseg_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- ADC/DAC
adc_dac_cs : out std_ulogic;
adc_dac_wr : out std_ulogic;
adc_dac_addr : out std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
adc_dac_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
adc_dac_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- AUDIO
audio_cs : out std_ulogic;
audio_wr : out std_ulogic;
audio_addr : out std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
audio_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
audio_irq_left : in std_ulogic;
audio_irq_right : in std_ulogic;
audio_ack_left : out std_ulogic;
audio_ack_right : out std_ulogic;
-- Infra-red Receiver
ir_cs : out std_ulogic;
ir_wr : out std_ulogic;
ir_addr : out std_ulogic_vector(CW_ADDR_IR-1 downto 0);
ir_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
ir_irq_rx : in std_ulogic;
ir_ack_rx : out std_ulogic;
-- LCD
lcd_cs : out std_ulogic;
lcd_wr : out std_ulogic;
lcd_addr : out std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
lcd_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
lcd_irq_rdy : in std_ulogic;
lcd_ack_rdy : out std_ulogic;
-- SRAM
sram_cs : out std_ulogic;
sram_wr : out std_ulogic;
sram_addr : out std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
sram_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
sram_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- UART
uart_cs : out std_ulogic;
uart_wr : out std_ulogic;
uart_addr : out std_ulogic_vector(CW_ADDR_UART-1 downto 0);
uart_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
uart_irq_rx : in std_ulogic;
uart_irq_tx : in std_ulogic;
uart_ack_rx : out std_ulogic;
uart_ack_tx : out std_ulogic;
-- GPIO
gp_ctrl : out std_ulogic_vector(15 downto 0);
gp_in : in std_ulogic_vector(15 downto 0);
gp_out : out std_ulogic_vector(15 downto 0);
-- LED/Switches/Keys
led_green : out std_ulogic_vector(8 downto 0);
led_red : out std_ulogic_vector(17 downto 0);
switch : in std_ulogic_vector(17 downto 0);
key : in std_ulogic_vector(2 downto 0)
);
end component invent_a_chip;
component seven_seg is
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_SEVENSEG-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_SEVENSEG-1 downto 0);
-- 7-Seg
hex0_n : out std_ulogic_vector(6 downto 0);
hex1_n : out std_ulogic_vector(6 downto 0);
hex2_n : out std_ulogic_vector(6 downto 0);
hex3_n : out std_ulogic_vector(6 downto 0);
hex4_n : out std_ulogic_vector(6 downto 0);
hex5_n : out std_ulogic_vector(6 downto 0);
hex6_n : out std_ulogic_vector(6 downto 0);
hex7_n : out std_ulogic_vector(6 downto 0)
);
end component seven_seg;
component adc_dac is
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_ADC_DAC-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_ADC_DAC-1 downto 0);
-- adc/dac signals
-- spi signals
spi_clk : out std_ulogic;
spi_mosi : out std_ulogic;
spi_miso : in std_ulogic;
spi_cs_dac_n : out std_ulogic;
spi_cs_adc_n : out std_ulogic;
-- Switch Signals
swt_select : out std_ulogic_vector(2 downto 0);
swt_enable_n : out std_ulogic;
-- DAC Signals
dac_ldac_n : out std_ulogic
);
end component adc_dac;
component audio is
port (
-- global
clock : in std_ulogic;
clock_audio : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_AUDIO-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_AUDIO-1 downto 0);
-- IRQ handling
iobus_irq_left : out std_ulogic;
iobus_irq_right : out std_ulogic;
iobus_ack_left : in std_ulogic;
iobus_ack_right : in std_ulogic;
-- connections to audio codec
aud_xclk : out std_ulogic;
aud_bclk : in std_ulogic;
aud_adc_lrck : in std_ulogic;
aud_adc_dat : in std_ulogic;
aud_dac_lrck : in std_ulogic;
aud_dac_dat : out std_ulogic;
i2c_sdat : inout std_logic;
i2c_sclk : inout std_logic
);
end component audio;
component infrared is
generic (
SIMULATION : boolean := false
);
port (
-- global
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_IR-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_IR-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_IR-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
-- connection to ir-receiver
irda_rxd : in std_ulogic
);
end component infrared;
component lcd is
generic (
SIMULATION : boolean := false
);
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus signals
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_LCD-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_LCD-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_LCD-1 downto 0);
iobus_irq_rdy : out std_ulogic;
iobus_ack_rdy : in std_ulogic;
-- display signals
disp_en : out std_ulogic;
disp_rs : out std_ulogic;
disp_rw : out std_ulogic;
disp_dat : out std_ulogic_vector(7 downto 0);
disp_pwr : out std_ulogic;
disp_blon : out std_ulogic
);
end component lcd;
component sram is
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_SRAM-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_SRAM-1 downto 0);
-- sram connections
sram_ce_n : out std_ulogic;
sram_oe_n : out std_ulogic;
sram_we_n : out std_ulogic;
sram_ub_n : out std_ulogic;
sram_lb_n : out std_ulogic;
sram_addr : out std_ulogic_vector(19 downto 0);
sram_dq : inout std_logic_vector(15 downto 0)
);
end component sram;
component uart is
generic (
SIMULATION : boolean := false
);
port (
-- global signals
clock : in std_ulogic;
reset_n : in std_ulogic;
-- bus interface
iobus_cs : in std_ulogic;
iobus_wr : in std_ulogic;
iobus_addr : in std_ulogic_vector(CW_ADDR_UART-1 downto 0);
iobus_din : in std_ulogic_vector(CW_DATA_UART-1 downto 0);
iobus_dout : out std_ulogic_vector(CW_DATA_UART-1 downto 0);
-- IRQ handling
iobus_irq_rx : out std_ulogic;
iobus_irq_tx : out std_ulogic;
iobus_ack_rx : in std_ulogic;
iobus_ack_tx : in std_ulogic;
-- pins to outside
rts : in std_ulogic;
cts : out std_ulogic;
rxd : in std_ulogic;
txd : out std_ulogic
);
end component uart;
begin
-- gpio
gpio_switcher_inst : gpio_switcher
port map (
gpio => gpio,
gp_ctrl => gp_ctrl,
gp_in => gp_in,
gp_out => gp_out
);
-- PLL
pll_inst : pll
port map (
areset => reset,
inclk0 => clock_ext_50,
c0 => clk_50,
c1 => clk_audio_12,
locked => pll_locked
);
-- external reset
reset <= not(reset_n);
-- high active internal reset-signal
reset_n_intern <= pll_locked;
reset_intern <= not reset_n_intern;
-- invert low-active keys
key <= not key_n;
-- register to sync async signals
process(clk_50, reset_n_intern)
begin
if reset_n_intern = '0' then
key_reg <= (others => '0');
switch_reg <= (others => '0');
elsif rising_edge(clk_50) then
key_reg <= key;
switch_reg <= switch;
end if;
end process;
-- mux to prevent undefined signals
sevenseg_dout_wire <= (others => '0') when CV_EN_SEVENSEG = 0 else sevenseg_dout;
adc_dac_dout_wire <= (others => '0') when CV_EN_ADC_DAC = 0 else adc_dac_dout;
audio_dout_wire <= (others => '0') when CV_EN_AUDIO = 0 else audio_dout;
ir_dout_wire <= (others => '0') when CV_EN_IR = 0 else ir_dout;
lcd_dout_wire <= (others => '0') when CV_EN_LCD = 0 else lcd_dout;
sram_dout_wire <= (others => '0') when CV_EN_SRAM = 0 else sram_dout;
uart_dout_wire <= (others => '0') when CV_EN_UART = 0 else uart_dout;
audio_irq_left_wire <= '0' when CV_EN_AUDIO = 0 else audio_irq_left;
audio_irq_right_wire <= '0' when CV_EN_AUDIO = 0 else audio_irq_right;
ir_irq_rx_wire <= '0' when CV_EN_IR = 0 else ir_irq_rx;
lcd_irq_rdy_wire <= '0' when CV_EN_LCD = 0 else lcd_irq_rdy;
uart_irq_rx_wire <= '0' when CV_EN_UART = 0 else uart_irq_rx;
uart_irq_tx_wire <= '0' when CV_EN_UART = 0 else uart_irq_tx;
-- invent_a_chip module
invent_a_chip_inst : invent_a_chip
port map (
-- Global Signals
clock => clk_50,
reset => reset_intern,
-- Interface Signals
-- 7-Seg
sevenseg_cs => sevenseg_cs,
sevenseg_wr => sevenseg_wr,
sevenseg_addr => sevenseg_addr,
sevenseg_din => sevenseg_dout_wire,
sevenseg_dout => sevenseg_din,
-- ADC/DAC
adc_dac_cs => adc_dac_cs,
adc_dac_wr => adc_dac_wr,
adc_dac_addr => adc_dac_addr,
adc_dac_din => adc_dac_dout_wire,
adc_dac_dout => adc_dac_din,
-- AUDIO
audio_cs => audio_cs,
audio_wr => audio_wr,
audio_addr => audio_addr,
audio_din => audio_dout_wire,
audio_dout => audio_din,
audio_irq_left => audio_irq_left_wire,
audio_irq_right => audio_irq_right_wire,
audio_ack_left => audio_ack_left,
audio_ack_right => audio_ack_right,
-- Infra-red Receiver
ir_cs => ir_cs,
ir_wr => ir_wr,
ir_addr => ir_addr,
ir_din => ir_dout_wire,
ir_dout => ir_din,
ir_irq_rx => ir_irq_rx_wire,
ir_ack_rx => ir_ack_rx,
-- LCD
lcd_cs => lcd_cs,
lcd_wr => lcd_wr,
lcd_addr => lcd_addr,
lcd_din => lcd_dout_wire,
lcd_dout => lcd_din,
lcd_irq_rdy => lcd_irq_rdy_wire,
lcd_ack_rdy => lcd_ack_rdy,
-- SRAM
sram_cs => sram_cs,
sram_wr => sram_wr,
sram_addr => sram_adr,
sram_din => sram_dout_wire,
sram_dout => sram_din,
-- UART
uart_cs => uart_cs,
uart_wr => uart_wr,
uart_addr => uart_addr,
uart_din => uart_dout_wire,
uart_dout => uart_din,
uart_irq_rx => uart_irq_rx_wire,
uart_irq_tx => uart_irq_tx_wire,
uart_ack_rx => uart_ack_rx,
uart_ack_tx => uart_ack_tx,
-- GPIO
gp_ctrl => gp_ctrl,
gp_in => gp_in,
gp_out => gp_out,
-- LED/Switches/Keys
led_green => led_green,
led_red => led_red,
switch => switch_reg,
key => key_reg
);
-- generate interface modules
seven_seg_gen : if CV_EN_SEVENSEG = 1 generate
sven_seg_inst : seven_seg
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => sevenseg_cs,
iobus_wr => sevenseg_wr,
iobus_addr => sevenseg_addr,
iobus_din => sevenseg_din,
iobus_dout => sevenseg_dout,
-- 7-Seg
hex0_n => hex0_n,
hex1_n => hex1_n,
hex2_n => hex2_n,
hex3_n => hex3_n,
hex4_n => hex4_n,
hex5_n => hex5_n,
hex6_n => hex6_n,
hex7_n => hex7_n
);
end generate seven_seg_gen;
adc_dac_gen : if CV_EN_ADC_DAC = 1 generate
adc_dac_inst : adc_dac
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => adc_dac_cs,
iobus_wr => adc_dac_wr,
iobus_addr => adc_dac_addr,
iobus_din => adc_dac_din,
iobus_dout => adc_dac_dout,
-- adc/dac signals
-- spi signals
spi_clk => exb_spi_clk,
spi_mosi => exb_spi_mosi,
spi_miso => exb_spi_miso,
spi_cs_dac_n => exb_spi_cs_dac_n,
spi_cs_adc_n => exb_spi_cs_adc_n,
-- switch signals
swt_select => exb_adc_switch,
swt_enable_n => exb_adc_en_n,
-- dac signals
dac_ldac_n => exb_dac_ldac_n
);
end generate adc_dac_gen;
audio_gen : if CV_EN_AUDIO = 1 generate
audio_inst : audio
port map (
-- global
clock => clk_50,
clock_audio => clk_audio_12,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => audio_cs,
iobus_wr => audio_wr,
iobus_addr => audio_addr,
iobus_din => audio_din,
iobus_dout => audio_dout,
-- IRQ handling
iobus_irq_left => audio_irq_left,
iobus_irq_right => audio_irq_right,
iobus_ack_left => audio_ack_left,
iobus_ack_right => audio_ack_right,
-- connections to audio codec
aud_xclk => aud_xclk,
aud_bclk => aud_bclk,
aud_adc_lrck => aud_adc_lrck,
aud_adc_dat => aud_adc_dat,
aud_dac_lrck => aud_dac_lrck,
aud_dac_dat => aud_dac_dat,
i2c_sdat => i2c_sdat,
i2c_sclk => i2c_sclk
);
end generate audio_gen;
ir_gen : if CV_EN_IR = 1 generate
ir_inst : infrared
generic map (
SIMULATION => SIMULATION
)
port map (
-- global
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => ir_cs,
iobus_wr => ir_wr,
iobus_addr => ir_addr,
iobus_din => ir_din,
iobus_dout => ir_dout,
-- IRQ handling
iobus_irq_rx => ir_irq_rx,
iobus_ack_rx => ir_ack_rx,
-- connection to ir-receiver
irda_rxd => irda_rxd
);
end generate ir_gen;
lcd_gen : if CV_EN_LCD = 1 generate
lcd_inst : lcd
generic map (
SIMULATION => SIMULATION
)
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => lcd_cs,
iobus_wr => lcd_wr,
iobus_addr => lcd_addr,
iobus_din => lcd_din,
iobus_dout => lcd_dout,
-- IRQ handling
iobus_irq_rdy => lcd_irq_rdy,
iobus_ack_rdy => lcd_ack_rdy,
-- display signals
disp_en => lcd_en,
disp_rs => lcd_rs,
disp_rw => lcd_rw,
disp_dat => lcd_dat,
disp_pwr => lcd_on,
disp_blon => lcd_blon
);
end generate lcd_gen;
sram_gen : if CV_EN_SRAM = 1 generate
sram_inst : sram
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => sram_cs,
iobus_wr => sram_wr,
iobus_addr => sram_adr,
iobus_din => sram_din,
iobus_dout => sram_dout,
-- sram connections
sram_ce_n => sram_ce_n,
sram_oe_n => sram_oe_n,
sram_we_n => sram_we_n,
sram_ub_n => sram_ub_n,
sram_lb_n => sram_lb_n,
sram_addr => sram_addr,
sram_dq => sram_dq
);
end generate sram_gen;
uart_gen : if CV_EN_UART = 1 generate
uart_inst : uart
generic map (
SIMULATION => SIMULATION
)
port map (
-- global signals
clock => clk_50,
reset_n => reset_n_intern,
-- bus interface
iobus_cs => uart_cs,
iobus_wr => uart_wr,
iobus_addr => uart_addr,
iobus_din => uart_din,
iobus_dout => uart_dout,
-- IRQ handling
iobus_irq_rx => uart_irq_rx,
iobus_irq_tx => uart_irq_tx,
iobus_ack_rx => uart_ack_rx,
iobus_ack_tx => uart_ack_tx,
-- pins to outside
rts => uart_rts,
cts => uart_cts,
rxd => uart_rxd,
txd => uart_txd
);
end generate uart_gen;
end rtl; |
-- Copyright (c) 2012 Brian Nezvadovitz <http://nezzen.net>
-- This software is distributed under the terms of the MIT License shown below.
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to
-- deal in the Software without restriction, including without limitation the
-- rights to use, copy, modify, merge, publish, distribute, sublicense, and/or
-- sell copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
-- FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
-- IN THE SOFTWARE.
-- Multiplexer 4:1
-- Implements a 4-to-1 multiplexer of a given width.
library ieee;
use ieee.std_logic_1164.all;
entity mux_4x1 is
generic (
WIDTH : positive := 1
);
port (
output : out std_logic_vector(WIDTH-1 downto 0);
sel : in std_logic_vector(1 downto 0);
in0 : in std_logic_vector(WIDTH-1 downto 0);
in1 : in std_logic_vector(WIDTH-1 downto 0);
in2 : in std_logic_vector(WIDTH-1 downto 0);
in3 : in std_logic_vector(WIDTH-1 downto 0)
);
end mux_4x1;
architecture BHV of mux_4x1 is
begin
output <=
in0 when sel = "00" else
in1 when sel = "01" else
in2 when sel = "10" else
in3 when sel = "11" else
(others => '0');
end BHV;
|
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
entity cse_rnd is
port(
clock: in std_logic;
input: in std_logic_vector(6 downto 0);
output: out std_logic_vector(6 downto 0)
);
end cse_rnd;
architecture behaviour of cse_rnd is
constant st0: std_logic_vector(3 downto 0) := "1101";
constant st1: std_logic_vector(3 downto 0) := "0010";
constant st9: std_logic_vector(3 downto 0) := "1011";
constant st6: std_logic_vector(3 downto 0) := "1110";
constant st8: std_logic_vector(3 downto 0) := "1111";
constant st2: std_logic_vector(3 downto 0) := "0001";
constant st5: std_logic_vector(3 downto 0) := "0110";
constant st3: std_logic_vector(3 downto 0) := "0000";
constant st4: std_logic_vector(3 downto 0) := "1010";
constant st7: std_logic_vector(3 downto 0) := "1000";
constant st10: std_logic_vector(3 downto 0) := "0100";
constant st11: std_logic_vector(3 downto 0) := "1001";
constant st12: std_logic_vector(3 downto 0) := "1100";
constant st13: std_logic_vector(3 downto 0) := "0011";
constant st14: std_logic_vector(3 downto 0) := "0111";
constant st15: std_logic_vector(3 downto 0) := "0101";
signal current_state, next_state: std_logic_vector(3 downto 0);
begin
process(clock) begin
if rising_edge(clock) then current_state <= next_state;
end if;
end process;
process(input, current_state) begin
next_state <= "----"; output <= "-------";
case current_state is
when st0 =>
if std_match(input, "1-000--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-11---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "1-1-1--") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-10";
elsif std_match(input, "10011--") then next_state <= st9; output <= "0010001";
elsif std_match(input, "10001--") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10100--") then next_state <= st8; output <= "0000--0";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st1 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "0100-00";
elsif std_match(input, "1000---") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st2 =>
if std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "10000--") then next_state <= st2; output <= "0000-00";
elsif std_match(input, "10001--") then next_state <= st3; output <= "1000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0-----1") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1----0") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1----1") then next_state <= st0; output <= "0000-10";
end if;
when st3 =>
if std_match(input, "10001--") then next_state <= st3; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-10";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-10";
end if;
when st4 =>
if std_match(input, "101----") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st1; output <= "1100-00";
elsif std_match(input, "1000---") then next_state <= st4; output <= "0000-00";
elsif std_match(input, "10011--") then next_state <= st5; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st5 =>
if std_match(input, "10-1---") then next_state <= st5; output <= "0000-00";
elsif std_match(input, "10-0---") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st6 =>
if std_match(input, "10--1--") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "101----") then next_state <= st6; output <= "0000-00";
elsif std_match(input, "100-0--") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st7 =>
if std_match(input, "100--0-") then next_state <= st7; output <= "0000-00";
elsif std_match(input, "101--0-") then next_state <= st6; output <= "0000-01";
elsif std_match(input, "10---1-") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000-00";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000-00";
end if;
when st8 =>
if std_match(input, "10-00--") then next_state <= st8; output <= "0000-00";
elsif std_match(input, "10010--") then next_state <= st9; output <= "0010101";
elsif std_match(input, "10-01--") then next_state <= st10; output <= "0000-10";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st9 =>
if std_match(input, "10-1---") then next_state <= st9; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st7; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st10 =>
if std_match(input, "10-0---") then next_state <= st10; output <= "0000-00";
elsif std_match(input, "10-10--") then next_state <= st11; output <= "0000100";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st11 =>
if std_match(input, "10-10--") then next_state <= st11; output <= "0000000";
elsif std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st12 =>
if std_match(input, "10-0---") then next_state <= st12; output <= "0000000";
elsif std_match(input, "10-10--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "10-11--") then next_state <= st0; output <= "0000--0";
end if;
when st13 =>
if std_match(input, "10-10--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10-01--") then next_state <= st13; output <= "0000000";
elsif std_match(input, "10100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0000--0";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0000--0";
end if;
when st14 =>
if std_match(input, "--111--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--100--") then next_state <= st14; output <= "0000000";
elsif std_match(input, "--110--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--101--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "--0----") then next_state <= st0; output <= "0001000";
end if;
when st15 =>
if std_match(input, "10000--") then next_state <= st15; output <= "0000000";
elsif std_match(input, "10010--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "10001--") then next_state <= st13; output <= "1000000";
elsif std_match(input, "101----") then next_state <= st8; output <= "0001000";
elsif std_match(input, "0------") then next_state <= st0; output <= "0001000";
elsif std_match(input, "-1-----") then next_state <= st0; output <= "0001000";
elsif std_match(input, "10011--") then next_state <= st0; output <= "0001000";
end if;
when others => next_state <= "----"; output <= "-------";
end case;
end process;
end behaviour;
|
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- Generic asynchronous FIFO wrapper
-- http://www.ohwr.org/projects/fmc-adc-100m14b4cha
--------------------------------------------------------------------------------
--
-- unit name: generic_async_fifo (generic_async_fifo_wrapper.vhd)
--
-- author: Matthieu Cattin ([email protected])
--
-- date: 05-12-2011
--
-- version: 1.0
--
-- description: Wrapper to use Xilinx Coregen FIFOs instead of generic FIFOs
-- from Generics RAMs and FIFOs collection.
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- last changes: see svn log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
--library work;
use work.gn4124_core_pkg.all;
entity generic_async_fifo is
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
-- Read-side flag selection
g_with_rd_empty : boolean := true; -- with empty flag
g_with_rd_full : boolean := false; -- with full flag
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false; -- with words counter
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer; -- threshold for almost empty flag
g_almost_full_threshold : integer -- threshold for almost full flag
);
port (
rst_n_i : in std_logic := '1';
-- write port
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0);
-- read port
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(log2_ceil(g_size)-1 downto 0)
);
end generic_async_fifo;
architecture syn of generic_async_fifo is
component fifo_32x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(31 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(9 downto 0);
prog_full_thresh_negate : in std_logic_vector(9 downto 0);
dout : out std_logic_vector(31 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_32x512;
component fifo_64x512
port (
rst : in std_logic;
wr_clk : in std_logic;
rd_clk : in std_logic;
din : in std_logic_vector(63 downto 0);
wr_en : in std_logic;
rd_en : in std_logic;
prog_full_thresh_assert : in std_logic_vector(8 downto 0);
prog_full_thresh_negate : in std_logic_vector(8 downto 0);
dout : out std_logic_vector(63 downto 0);
full : out std_logic;
empty : out std_logic;
valid : out std_logic;
prog_full : out std_logic);
end component fifo_64x512;
signal rst : std_logic;
begin
-- Active high reset for FIFOs
rst <= not(rst_n_i);
-- Assign unused outputs
wr_empty_o <= '0';
wr_almost_empty_o <= '0';
wr_count_o <= (others => '0');
rd_full_o <= '0';
rd_almost_full_o <= '0';
rd_almost_empty_o <= '0';
rd_count_o <= (others => '0');
gen_fifo_32bit : if g_data_width = 32 generate
cmp_fifo_32x512 : fifo_32x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 10)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 10)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_32bit;
gen_fifo_64bit : if g_data_width = 64 generate
cmp_fifo_64x512 : fifo_64x512
port map (
rst => rst,
wr_clk => clk_wr_i,
rd_clk => clk_rd_i,
din => d_i,
wr_en => we_i,
rd_en => rd_i,
prog_full_thresh_assert => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
prog_full_thresh_negate => std_logic_vector(to_unsigned(g_almost_full_threshold, 9)),
dout => q_o,
full => wr_full_o,
empty => rd_empty_o,
valid => open,
prog_full => wr_almost_full_o);
end generate gen_fifo_64bit;
end syn;
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff2.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff2 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END lpm_dff2;
ARCHITECTURE SYN OF lpm_dff2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (20 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(20 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 21
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "21"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 21 0 INPUT NODEFVAL data[20..0]
-- Retrieval info: USED_PORT: q 0 0 21 0 OUTPUT NODEFVAL q[20..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 21 0 @q 0 0 21 0
-- Retrieval info: CONNECT: @data 0 0 21 0 data 0 0 21 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff2.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff2 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END lpm_dff2;
ARCHITECTURE SYN OF lpm_dff2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (20 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(20 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 21
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "21"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 21 0 INPUT NODEFVAL data[20..0]
-- Retrieval info: USED_PORT: q 0 0 21 0 OUTPUT NODEFVAL q[20..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 21 0 @q 0 0 21 0
-- Retrieval info: CONNECT: @data 0 0 21 0 data 0 0 21 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
-- megafunction wizard: %LPM_FF%
-- GENERATION: STANDARD
-- VERSION: WM1.0
-- MODULE: lpm_ff
-- ============================================================
-- File Name: lpm_dff2.vhd
-- Megafunction Name(s):
-- lpm_ff
--
-- Simulation Library Files(s):
-- lpm
-- ============================================================
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 222 10/21/2009 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2009 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
--(including device programming or simulation files), and any
--associated documentation or information are expressly subject
--to the terms and conditions of the Altera Program License
--Subscription Agreement, Altera MegaCore Function License
--Agreement, or other applicable license agreement, including,
--without limitation, that your use is for the sole purpose of
--programming logic devices manufactured by Altera and sold by
--Altera or its authorized distributors. Please refer to the
--applicable agreement for further details.
LIBRARY ieee;
USE ieee.std_logic_1164.all;
LIBRARY lpm;
USE lpm.all;
ENTITY lpm_dff2 IS
PORT
(
clock : IN STD_LOGIC ;
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0);
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END lpm_dff2;
ARCHITECTURE SYN OF lpm_dff2 IS
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (20 DOWNTO 0);
COMPONENT lpm_ff
GENERIC (
lpm_fftype : STRING;
lpm_type : STRING;
lpm_width : NATURAL
);
PORT (
clock : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (20 DOWNTO 0);
data : IN STD_LOGIC_VECTOR (20 DOWNTO 0)
);
END COMPONENT;
BEGIN
q <= sub_wire0(20 DOWNTO 0);
lpm_ff_component : lpm_ff
GENERIC MAP (
lpm_fftype => "DFF",
lpm_type => "LPM_FF",
lpm_width => 21
)
PORT MAP (
clock => clock,
data => data,
q => sub_wire0
);
END SYN;
-- ============================================================
-- CNX file retrieval info
-- ============================================================
-- Retrieval info: PRIVATE: ACLR NUMERIC "0"
-- Retrieval info: PRIVATE: ALOAD NUMERIC "0"
-- Retrieval info: PRIVATE: ASET NUMERIC "0"
-- Retrieval info: PRIVATE: ASET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: CLK_EN NUMERIC "0"
-- Retrieval info: PRIVATE: DFF NUMERIC "1"
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone II"
-- Retrieval info: PRIVATE: SCLR NUMERIC "0"
-- Retrieval info: PRIVATE: SLOAD NUMERIC "0"
-- Retrieval info: PRIVATE: SSET NUMERIC "0"
-- Retrieval info: PRIVATE: SSET_ALL1 NUMERIC "1"
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
-- Retrieval info: PRIVATE: UseTFFdataPort NUMERIC "0"
-- Retrieval info: PRIVATE: nBit NUMERIC "21"
-- Retrieval info: CONSTANT: LPM_FFTYPE STRING "DFF"
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_FF"
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "21"
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
-- Retrieval info: USED_PORT: data 0 0 21 0 INPUT NODEFVAL data[20..0]
-- Retrieval info: USED_PORT: q 0 0 21 0 OUTPUT NODEFVAL q[20..0]
-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
-- Retrieval info: CONNECT: q 0 0 21 0 @q 0 0 21 0
-- Retrieval info: CONNECT: @data 0 0 21 0 data 0 0 21 0
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.inc FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_dff2_inst.vhd FALSE
-- Retrieval info: LIB_FILE: lpm
|
entity FIFO is
port (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
entity FIFO is
PORT (
I_WR_EN : in std_logic;
I_DATA : out std_logic_vector(31 downto 0);
I_RD_EN : in std_logic;
O_DATA : out std_logic_vector(31 downto 0)
);
end entity FIFO;
|
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