content
stringlengths 1
1.04M
⌀ |
|---|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: xilinx.com:ip:microblaze:9.5
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
LIBRARY microblaze_v9_5;
USE microblaze_v9_5.MicroBlaze;
ENTITY design_1_microblaze_0_0 IS
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC
);
END design_1_microblaze_0_0;
ARCHITECTURE design_1_microblaze_0_0_arch OF design_1_microblaze_0_0 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "yes";
COMPONENT MicroBlaze IS
GENERIC (
C_SCO : INTEGER;
C_FREQ : INTEGER;
C_USE_CONFIG_RESET : INTEGER;
C_NUM_SYNC_FF_CLK : INTEGER;
C_NUM_SYNC_FF_CLK_IRQ : INTEGER;
C_NUM_SYNC_FF_CLK_DEBUG : INTEGER;
C_NUM_SYNC_FF_DBG_CLK : INTEGER;
C_FAULT_TOLERANT : INTEGER;
C_ECC_USE_CE_EXCEPTION : INTEGER;
C_LOCKSTEP_SLAVE : INTEGER;
C_ENDIANNESS : INTEGER;
C_FAMILY : STRING;
C_DATA_SIZE : INTEGER;
C_INSTANCE : STRING;
C_AVOID_PRIMITIVES : INTEGER;
C_AREA_OPTIMIZED : INTEGER;
C_OPTIMIZATION : INTEGER;
C_INTERCONNECT : INTEGER;
C_BASE_VECTORS : STD_LOGIC_VECTOR;
C_M_AXI_DP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DP_DATA_WIDTH : INTEGER;
C_M_AXI_DP_ADDR_WIDTH : INTEGER;
C_M_AXI_DP_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_D_BUS_EXCEPTION : INTEGER;
C_M_AXI_IP_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IP_DATA_WIDTH : INTEGER;
C_M_AXI_IP_ADDR_WIDTH : INTEGER;
C_M_AXI_I_BUS_EXCEPTION : INTEGER;
C_D_LMB : INTEGER;
C_D_AXI : INTEGER;
C_I_LMB : INTEGER;
C_I_AXI : INTEGER;
C_USE_MSR_INSTR : INTEGER;
C_USE_PCMP_INSTR : INTEGER;
C_USE_BARREL : INTEGER;
C_USE_DIV : INTEGER;
C_USE_HW_MUL : INTEGER;
C_USE_FPU : INTEGER;
C_USE_REORDER_INSTR : INTEGER;
C_UNALIGNED_EXCEPTIONS : INTEGER;
C_ILL_OPCODE_EXCEPTION : INTEGER;
C_DIV_ZERO_EXCEPTION : INTEGER;
C_FPU_EXCEPTION : INTEGER;
C_FSL_LINKS : INTEGER;
C_USE_EXTENDED_FSL_INSTR : INTEGER;
C_FSL_EXCEPTION : INTEGER;
C_USE_STACK_PROTECTION : INTEGER;
C_IMPRECISE_EXCEPTIONS : INTEGER;
C_USE_INTERRUPT : INTEGER;
C_USE_EXT_BRK : INTEGER;
C_USE_EXT_NM_BRK : INTEGER;
C_USE_MMU : INTEGER;
C_MMU_DTLB_SIZE : INTEGER;
C_MMU_ITLB_SIZE : INTEGER;
C_MMU_TLB_ACCESS : INTEGER;
C_MMU_ZONES : INTEGER;
C_MMU_PRIVILEGED_INSTR : INTEGER;
C_USE_BRANCH_TARGET_CACHE : INTEGER;
C_BRANCH_TARGET_CACHE_SIZE : INTEGER;
C_PC_WIDTH : INTEGER;
C_PVR : INTEGER;
C_PVR_USER1 : STD_LOGIC_VECTOR(0 TO 7);
C_PVR_USER2 : STD_LOGIC_VECTOR(0 TO 31);
C_DYNAMIC_BUS_SIZING : INTEGER;
C_RESET_MSR : STD_LOGIC_VECTOR(0 TO 31);
C_OPCODE_0x0_ILLEGAL : INTEGER;
C_DEBUG_ENABLED : INTEGER;
C_NUMBER_OF_PC_BRK : INTEGER;
C_NUMBER_OF_RD_ADDR_BRK : INTEGER;
C_NUMBER_OF_WR_ADDR_BRK : INTEGER;
C_DEBUG_EVENT_COUNTERS : INTEGER;
C_DEBUG_LATENCY_COUNTERS : INTEGER;
C_DEBUG_COUNTER_WIDTH : INTEGER;
C_DEBUG_TRACE_SIZE : INTEGER;
C_DEBUG_EXTERNAL_TRACE : INTEGER;
C_DEBUG_PROFILE_SIZE : INTEGER;
C_INTERRUPT_IS_EDGE : INTEGER;
C_EDGE_IS_POSITIVE : INTEGER;
C_ASYNC_INTERRUPT : INTEGER;
C_M0_AXIS_DATA_WIDTH : INTEGER;
C_S0_AXIS_DATA_WIDTH : INTEGER;
C_M1_AXIS_DATA_WIDTH : INTEGER;
C_S1_AXIS_DATA_WIDTH : INTEGER;
C_M2_AXIS_DATA_WIDTH : INTEGER;
C_S2_AXIS_DATA_WIDTH : INTEGER;
C_M3_AXIS_DATA_WIDTH : INTEGER;
C_S3_AXIS_DATA_WIDTH : INTEGER;
C_M4_AXIS_DATA_WIDTH : INTEGER;
C_S4_AXIS_DATA_WIDTH : INTEGER;
C_M5_AXIS_DATA_WIDTH : INTEGER;
C_S5_AXIS_DATA_WIDTH : INTEGER;
C_M6_AXIS_DATA_WIDTH : INTEGER;
C_S6_AXIS_DATA_WIDTH : INTEGER;
C_M7_AXIS_DATA_WIDTH : INTEGER;
C_S7_AXIS_DATA_WIDTH : INTEGER;
C_M8_AXIS_DATA_WIDTH : INTEGER;
C_S8_AXIS_DATA_WIDTH : INTEGER;
C_M9_AXIS_DATA_WIDTH : INTEGER;
C_S9_AXIS_DATA_WIDTH : INTEGER;
C_M10_AXIS_DATA_WIDTH : INTEGER;
C_S10_AXIS_DATA_WIDTH : INTEGER;
C_M11_AXIS_DATA_WIDTH : INTEGER;
C_S11_AXIS_DATA_WIDTH : INTEGER;
C_M12_AXIS_DATA_WIDTH : INTEGER;
C_S12_AXIS_DATA_WIDTH : INTEGER;
C_M13_AXIS_DATA_WIDTH : INTEGER;
C_S13_AXIS_DATA_WIDTH : INTEGER;
C_M14_AXIS_DATA_WIDTH : INTEGER;
C_S14_AXIS_DATA_WIDTH : INTEGER;
C_M15_AXIS_DATA_WIDTH : INTEGER;
C_S15_AXIS_DATA_WIDTH : INTEGER;
C_ICACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_ICACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_ICACHE : INTEGER;
C_ALLOW_ICACHE_WR : INTEGER;
C_ADDR_TAG_BITS : INTEGER;
C_CACHE_BYTE_SIZE : INTEGER;
C_ICACHE_LINE_LEN : INTEGER;
C_ICACHE_ALWAYS_USED : INTEGER;
C_ICACHE_STREAMS : INTEGER;
C_ICACHE_VICTIMS : INTEGER;
C_ICACHE_FORCE_TAG_LUTRAM : INTEGER;
C_ICACHE_DATA_WIDTH : INTEGER;
C_M_AXI_IC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_IC_DATA_WIDTH : INTEGER;
C_M_AXI_IC_ADDR_WIDTH : INTEGER;
C_M_AXI_IC_USER_VALUE : INTEGER;
C_M_AXI_IC_AWUSER_WIDTH : INTEGER;
C_M_AXI_IC_ARUSER_WIDTH : INTEGER;
C_M_AXI_IC_WUSER_WIDTH : INTEGER;
C_M_AXI_IC_RUSER_WIDTH : INTEGER;
C_M_AXI_IC_BUSER_WIDTH : INTEGER;
C_DCACHE_BASEADDR : STD_LOGIC_VECTOR(0 TO 31);
C_DCACHE_HIGHADDR : STD_LOGIC_VECTOR(0 TO 31);
C_USE_DCACHE : INTEGER;
C_ALLOW_DCACHE_WR : INTEGER;
C_DCACHE_ADDR_TAG : INTEGER;
C_DCACHE_BYTE_SIZE : INTEGER;
C_DCACHE_LINE_LEN : INTEGER;
C_DCACHE_ALWAYS_USED : INTEGER;
C_DCACHE_USE_WRITEBACK : INTEGER;
C_DCACHE_VICTIMS : INTEGER;
C_DCACHE_FORCE_TAG_LUTRAM : INTEGER;
C_DCACHE_DATA_WIDTH : INTEGER;
C_M_AXI_DC_THREAD_ID_WIDTH : INTEGER;
C_M_AXI_DC_DATA_WIDTH : INTEGER;
C_M_AXI_DC_ADDR_WIDTH : INTEGER;
C_M_AXI_DC_EXCLUSIVE_ACCESS : INTEGER;
C_M_AXI_DC_USER_VALUE : INTEGER;
C_M_AXI_DC_AWUSER_WIDTH : INTEGER;
C_M_AXI_DC_ARUSER_WIDTH : INTEGER;
C_M_AXI_DC_WUSER_WIDTH : INTEGER;
C_M_AXI_DC_RUSER_WIDTH : INTEGER;
C_M_AXI_DC_BUSER_WIDTH : INTEGER
);
PORT (
Clk : IN STD_LOGIC;
Reset : IN STD_LOGIC;
Mb_Reset : IN STD_LOGIC;
Config_Reset : IN STD_LOGIC;
Scan_Reset : IN STD_LOGIC;
Scan_Reset_Sel : IN STD_LOGIC;
Dbg_Disable : IN STD_LOGIC;
Interrupt : IN STD_LOGIC;
Interrupt_Address : IN STD_LOGIC_VECTOR(0 TO 31);
Interrupt_Ack : OUT STD_LOGIC_VECTOR(0 TO 1);
Ext_BRK : IN STD_LOGIC;
Ext_NM_BRK : IN STD_LOGIC;
Dbg_Stop : IN STD_LOGIC;
Dbg_Intr : OUT STD_LOGIC;
MB_Halted : OUT STD_LOGIC;
MB_Error : OUT STD_LOGIC;
Wakeup : IN STD_LOGIC_VECTOR(0 TO 1);
Sleep : OUT STD_LOGIC;
Dbg_Wakeup : OUT STD_LOGIC;
Reset_Mode : IN STD_LOGIC_VECTOR(0 TO 1);
LOCKSTEP_Slave_In : IN STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Master_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
LOCKSTEP_Out : OUT STD_LOGIC_VECTOR(0 TO 4095);
Instr_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Instr : IN STD_LOGIC_VECTOR(0 TO 31);
IFetch : OUT STD_LOGIC;
I_AS : OUT STD_LOGIC;
IReady : IN STD_LOGIC;
IWAIT : IN STD_LOGIC;
ICE : IN STD_LOGIC;
IUE : IN STD_LOGIC;
M_AXI_IP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_AWLOCK : OUT STD_LOGIC;
M_AXI_IP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_AWVALID : OUT STD_LOGIC;
M_AXI_IP_AWREADY : IN STD_LOGIC;
M_AXI_IP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_WLAST : OUT STD_LOGIC;
M_AXI_IP_WVALID : OUT STD_LOGIC;
M_AXI_IP_WREADY : IN STD_LOGIC;
M_AXI_IP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_BVALID : IN STD_LOGIC;
M_AXI_IP_BREADY : OUT STD_LOGIC;
M_AXI_IP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_ARLOCK : OUT STD_LOGIC;
M_AXI_IP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IP_ARVALID : OUT STD_LOGIC;
M_AXI_IP_ARREADY : IN STD_LOGIC;
M_AXI_IP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IP_RLAST : IN STD_LOGIC;
M_AXI_IP_RVALID : IN STD_LOGIC;
M_AXI_IP_RREADY : OUT STD_LOGIC;
Data_Addr : OUT STD_LOGIC_VECTOR(0 TO 31);
Data_Read : IN STD_LOGIC_VECTOR(0 TO 31);
Data_Write : OUT STD_LOGIC_VECTOR(0 TO 31);
D_AS : OUT STD_LOGIC;
Read_Strobe : OUT STD_LOGIC;
Write_Strobe : OUT STD_LOGIC;
DReady : IN STD_LOGIC;
DWait : IN STD_LOGIC;
DCE : IN STD_LOGIC;
DUE : IN STD_LOGIC;
Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
M_AXI_DP_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_AWLOCK : OUT STD_LOGIC;
M_AXI_DP_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_AWVALID : OUT STD_LOGIC;
M_AXI_DP_AWREADY : IN STD_LOGIC;
M_AXI_DP_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_WLAST : OUT STD_LOGIC;
M_AXI_DP_WVALID : OUT STD_LOGIC;
M_AXI_DP_WREADY : IN STD_LOGIC;
M_AXI_DP_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_BVALID : IN STD_LOGIC;
M_AXI_DP_BREADY : OUT STD_LOGIC;
M_AXI_DP_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DP_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_ARLOCK : OUT STD_LOGIC;
M_AXI_DP_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DP_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DP_ARVALID : OUT STD_LOGIC;
M_AXI_DP_ARREADY : IN STD_LOGIC;
M_AXI_DP_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DP_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DP_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DP_RLAST : IN STD_LOGIC;
M_AXI_DP_RVALID : IN STD_LOGIC;
M_AXI_DP_RREADY : OUT STD_LOGIC;
Dbg_Clk : IN STD_LOGIC;
Dbg_TDI : IN STD_LOGIC;
Dbg_TDO : OUT STD_LOGIC;
Dbg_Reg_En : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Shift : IN STD_LOGIC;
Dbg_Capture : IN STD_LOGIC;
Dbg_Update : IN STD_LOGIC;
Dbg_Trig_In : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_In : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Out : IN STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trig_Ack_Out : OUT STD_LOGIC_VECTOR(0 TO 7);
Dbg_Trace_Clk : IN STD_LOGIC;
Dbg_Trace_Data : OUT STD_LOGIC_VECTOR(0 TO 35);
Dbg_Trace_Ready : IN STD_LOGIC;
Dbg_Trace_Valid : OUT STD_LOGIC;
Debug_Rst : IN STD_LOGIC;
Trace_Instruction : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Valid_Instr : OUT STD_LOGIC;
Trace_PC : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Reg_Write : OUT STD_LOGIC;
Trace_Reg_Addr : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_MSR_Reg : OUT STD_LOGIC_VECTOR(0 TO 14);
Trace_PID_Reg : OUT STD_LOGIC_VECTOR(0 TO 7);
Trace_New_Reg_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Exception_Taken : OUT STD_LOGIC;
Trace_Exception_Kind : OUT STD_LOGIC_VECTOR(0 TO 4);
Trace_Jump_Taken : OUT STD_LOGIC;
Trace_Delay_Slot : OUT STD_LOGIC;
Trace_Data_Address : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Write_Value : OUT STD_LOGIC_VECTOR(0 TO 31);
Trace_Data_Byte_Enable : OUT STD_LOGIC_VECTOR(0 TO 3);
Trace_Data_Access : OUT STD_LOGIC;
Trace_Data_Read : OUT STD_LOGIC;
Trace_Data_Write : OUT STD_LOGIC;
Trace_DCache_Req : OUT STD_LOGIC;
Trace_DCache_Hit : OUT STD_LOGIC;
Trace_DCache_Rdy : OUT STD_LOGIC;
Trace_DCache_Read : OUT STD_LOGIC;
Trace_ICache_Req : OUT STD_LOGIC;
Trace_ICache_Hit : OUT STD_LOGIC;
Trace_ICache_Rdy : OUT STD_LOGIC;
Trace_OF_PipeRun : OUT STD_LOGIC;
Trace_EX_PipeRun : OUT STD_LOGIC;
Trace_MEM_PipeRun : OUT STD_LOGIC;
Trace_MB_Halted : OUT STD_LOGIC;
Trace_Jump_Hit : OUT STD_LOGIC;
M0_AXIS_TLAST : OUT STD_LOGIC;
M0_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M0_AXIS_TVALID : OUT STD_LOGIC;
M0_AXIS_TREADY : IN STD_LOGIC;
M1_AXIS_TLAST : OUT STD_LOGIC;
M1_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M1_AXIS_TVALID : OUT STD_LOGIC;
M1_AXIS_TREADY : IN STD_LOGIC;
M2_AXIS_TLAST : OUT STD_LOGIC;
M2_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M2_AXIS_TVALID : OUT STD_LOGIC;
M2_AXIS_TREADY : IN STD_LOGIC;
M3_AXIS_TLAST : OUT STD_LOGIC;
M3_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M3_AXIS_TVALID : OUT STD_LOGIC;
M3_AXIS_TREADY : IN STD_LOGIC;
M4_AXIS_TLAST : OUT STD_LOGIC;
M4_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M4_AXIS_TVALID : OUT STD_LOGIC;
M4_AXIS_TREADY : IN STD_LOGIC;
M5_AXIS_TLAST : OUT STD_LOGIC;
M5_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M5_AXIS_TVALID : OUT STD_LOGIC;
M5_AXIS_TREADY : IN STD_LOGIC;
M6_AXIS_TLAST : OUT STD_LOGIC;
M6_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M6_AXIS_TVALID : OUT STD_LOGIC;
M6_AXIS_TREADY : IN STD_LOGIC;
M7_AXIS_TLAST : OUT STD_LOGIC;
M7_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M7_AXIS_TVALID : OUT STD_LOGIC;
M7_AXIS_TREADY : IN STD_LOGIC;
M8_AXIS_TLAST : OUT STD_LOGIC;
M8_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M8_AXIS_TVALID : OUT STD_LOGIC;
M8_AXIS_TREADY : IN STD_LOGIC;
M9_AXIS_TLAST : OUT STD_LOGIC;
M9_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M9_AXIS_TVALID : OUT STD_LOGIC;
M9_AXIS_TREADY : IN STD_LOGIC;
M10_AXIS_TLAST : OUT STD_LOGIC;
M10_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M10_AXIS_TVALID : OUT STD_LOGIC;
M10_AXIS_TREADY : IN STD_LOGIC;
M11_AXIS_TLAST : OUT STD_LOGIC;
M11_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M11_AXIS_TVALID : OUT STD_LOGIC;
M11_AXIS_TREADY : IN STD_LOGIC;
M12_AXIS_TLAST : OUT STD_LOGIC;
M12_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M12_AXIS_TVALID : OUT STD_LOGIC;
M12_AXIS_TREADY : IN STD_LOGIC;
M13_AXIS_TLAST : OUT STD_LOGIC;
M13_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M13_AXIS_TVALID : OUT STD_LOGIC;
M13_AXIS_TREADY : IN STD_LOGIC;
M14_AXIS_TLAST : OUT STD_LOGIC;
M14_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M14_AXIS_TVALID : OUT STD_LOGIC;
M14_AXIS_TREADY : IN STD_LOGIC;
M15_AXIS_TLAST : OUT STD_LOGIC;
M15_AXIS_TDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M15_AXIS_TVALID : OUT STD_LOGIC;
M15_AXIS_TREADY : IN STD_LOGIC;
S0_AXIS_TLAST : IN STD_LOGIC;
S0_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S0_AXIS_TVALID : IN STD_LOGIC;
S0_AXIS_TREADY : OUT STD_LOGIC;
S1_AXIS_TLAST : IN STD_LOGIC;
S1_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S1_AXIS_TVALID : IN STD_LOGIC;
S1_AXIS_TREADY : OUT STD_LOGIC;
S2_AXIS_TLAST : IN STD_LOGIC;
S2_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S2_AXIS_TVALID : IN STD_LOGIC;
S2_AXIS_TREADY : OUT STD_LOGIC;
S3_AXIS_TLAST : IN STD_LOGIC;
S3_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S3_AXIS_TVALID : IN STD_LOGIC;
S3_AXIS_TREADY : OUT STD_LOGIC;
S4_AXIS_TLAST : IN STD_LOGIC;
S4_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S4_AXIS_TVALID : IN STD_LOGIC;
S4_AXIS_TREADY : OUT STD_LOGIC;
S5_AXIS_TLAST : IN STD_LOGIC;
S5_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S5_AXIS_TVALID : IN STD_LOGIC;
S5_AXIS_TREADY : OUT STD_LOGIC;
S6_AXIS_TLAST : IN STD_LOGIC;
S6_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S6_AXIS_TVALID : IN STD_LOGIC;
S6_AXIS_TREADY : OUT STD_LOGIC;
S7_AXIS_TLAST : IN STD_LOGIC;
S7_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S7_AXIS_TVALID : IN STD_LOGIC;
S7_AXIS_TREADY : OUT STD_LOGIC;
S8_AXIS_TLAST : IN STD_LOGIC;
S8_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S8_AXIS_TVALID : IN STD_LOGIC;
S8_AXIS_TREADY : OUT STD_LOGIC;
S9_AXIS_TLAST : IN STD_LOGIC;
S9_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S9_AXIS_TVALID : IN STD_LOGIC;
S9_AXIS_TREADY : OUT STD_LOGIC;
S10_AXIS_TLAST : IN STD_LOGIC;
S10_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S10_AXIS_TVALID : IN STD_LOGIC;
S10_AXIS_TREADY : OUT STD_LOGIC;
S11_AXIS_TLAST : IN STD_LOGIC;
S11_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S11_AXIS_TVALID : IN STD_LOGIC;
S11_AXIS_TREADY : OUT STD_LOGIC;
S12_AXIS_TLAST : IN STD_LOGIC;
S12_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S12_AXIS_TVALID : IN STD_LOGIC;
S12_AXIS_TREADY : OUT STD_LOGIC;
S13_AXIS_TLAST : IN STD_LOGIC;
S13_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S13_AXIS_TVALID : IN STD_LOGIC;
S13_AXIS_TREADY : OUT STD_LOGIC;
S14_AXIS_TLAST : IN STD_LOGIC;
S14_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S14_AXIS_TVALID : IN STD_LOGIC;
S14_AXIS_TREADY : OUT STD_LOGIC;
S15_AXIS_TLAST : IN STD_LOGIC;
S15_AXIS_TDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
S15_AXIS_TVALID : IN STD_LOGIC;
S15_AXIS_TREADY : OUT STD_LOGIC;
M_AXI_IC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWLOCK : OUT STD_LOGIC;
M_AXI_IC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_AWVALID : OUT STD_LOGIC;
M_AXI_IC_AWREADY : IN STD_LOGIC;
M_AXI_IC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_WLAST : OUT STD_LOGIC;
M_AXI_IC_WVALID : OUT STD_LOGIC;
M_AXI_IC_WREADY : IN STD_LOGIC;
M_AXI_IC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_BVALID : IN STD_LOGIC;
M_AXI_IC_BREADY : OUT STD_LOGIC;
M_AXI_IC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_WACK : OUT STD_LOGIC;
M_AXI_IC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_IC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARLOCK : OUT STD_LOGIC;
M_AXI_IC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARVALID : OUT STD_LOGIC;
M_AXI_IC_ARREADY : IN STD_LOGIC;
M_AXI_IC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_IC_RLAST : IN STD_LOGIC;
M_AXI_IC_RVALID : IN STD_LOGIC;
M_AXI_IC_RREADY : OUT STD_LOGIC;
M_AXI_IC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_IC_RACK : OUT STD_LOGIC;
M_AXI_IC_ACVALID : IN STD_LOGIC;
M_AXI_IC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_IC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_IC_ACREADY : OUT STD_LOGIC;
M_AXI_IC_CRVALID : OUT STD_LOGIC;
M_AXI_IC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_IC_CRREADY : IN STD_LOGIC;
M_AXI_IC_CDVALID : OUT STD_LOGIC;
M_AXI_IC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_IC_CDLAST : OUT STD_LOGIC;
M_AXI_IC_CDREADY : IN STD_LOGIC;
M_AXI_DC_AWID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_AWADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_AWLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_AWSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWLOCK : OUT STD_LOGIC;
M_AXI_DC_AWCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_AWVALID : OUT STD_LOGIC;
M_AXI_DC_AWREADY : IN STD_LOGIC;
M_AXI_DC_AWUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_AWDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_AWSNOOP : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_AWBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_WDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_WSTRB : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_WLAST : OUT STD_LOGIC;
M_AXI_DC_WVALID : OUT STD_LOGIC;
M_AXI_DC_WREADY : IN STD_LOGIC;
M_AXI_DC_WUSER : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_BID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_BVALID : IN STD_LOGIC;
M_AXI_DC_BREADY : OUT STD_LOGIC;
M_AXI_DC_BUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_WACK : OUT STD_LOGIC;
M_AXI_DC_ARID : OUT STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_ARADDR : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ARLEN : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
M_AXI_DC_ARSIZE : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARBURST : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARLOCK : OUT STD_LOGIC;
M_AXI_DC_ARCACHE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARPROT : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ARQOS : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARVALID : OUT STD_LOGIC;
M_AXI_DC_ARREADY : IN STD_LOGIC;
M_AXI_DC_ARUSER : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_ARDOMAIN : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_ARSNOOP : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ARBAR : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RID : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RDATA : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_RRESP : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
M_AXI_DC_RLAST : IN STD_LOGIC;
M_AXI_DC_RVALID : IN STD_LOGIC;
M_AXI_DC_RREADY : OUT STD_LOGIC;
M_AXI_DC_RUSER : IN STD_LOGIC_VECTOR(0 DOWNTO 0);
M_AXI_DC_RACK : OUT STD_LOGIC;
M_AXI_DC_ACVALID : IN STD_LOGIC;
M_AXI_DC_ACADDR : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_ACSNOOP : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
M_AXI_DC_ACPROT : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
M_AXI_DC_ACREADY : OUT STD_LOGIC;
M_AXI_DC_CRVALID : OUT STD_LOGIC;
M_AXI_DC_CRRESP : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
M_AXI_DC_CRREADY : IN STD_LOGIC;
M_AXI_DC_CDVALID : OUT STD_LOGIC;
M_AXI_DC_CDDATA : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
M_AXI_DC_CDLAST : OUT STD_LOGIC;
M_AXI_DC_CDREADY : IN STD_LOGIC
);
END COMPONENT MicroBlaze;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "MicroBlaze,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_microblaze_0_0_arch : ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{}";
ATTRIBUTE CORE_GENERATION_INFO : STRING;
ATTRIBUTE CORE_GENERATION_INFO OF design_1_microblaze_0_0_arch: ARCHITECTURE IS "design_1_microblaze_0_0,MicroBlaze,{x_ipProduct=Vivado 2015.2,x_ipVendor=xilinx.com,x_ipLibrary=ip,x_ipName=microblaze,x_ipVersion=9.5,x_ipCoreRevision=1,x_ipLanguage=VERILOG,x_ipSimLanguage=MIXED,C_SCO=0,C_FREQ=100000000,C_USE_CONFIG_RESET=0,C_NUM_SYNC_FF_CLK=2,C_NUM_SYNC_FF_CLK_IRQ=1,C_NUM_SYNC_FF_CLK_DEBUG=2,C_NUM_SYNC_FF_DBG_CLK=1,C_FAULT_TOLERANT=0,C_ECC_USE_CE_EXCEPTION=0,C_LOCKSTEP_SLAVE=0,C_ENDIANNESS=1,C_FAMILY=artix7,C_DATA_SIZE=32,C_INSTANCE=design_1_microblaze_0_0,C_AVOID_PRIMITIVES=0,C_AREA_OPTIMIZED=0,C_OPTIMIZATION=0,C_INTERCONNECT=2,C_BASE_VECTORS=0x00000000,C_M_AXI_DP_THREAD_ID_WIDTH=1,C_M_AXI_DP_DATA_WIDTH=32,C_M_AXI_DP_ADDR_WIDTH=32,C_M_AXI_DP_EXCLUSIVE_ACCESS=0,C_M_AXI_D_BUS_EXCEPTION=0,C_M_AXI_IP_THREAD_ID_WIDTH=1,C_M_AXI_IP_DATA_WIDTH=32,C_M_AXI_IP_ADDR_WIDTH=32,C_M_AXI_I_BUS_EXCEPTION=0,C_D_LMB=1,C_D_AXI=1,C_I_LMB=1,C_I_AXI=0,C_USE_MSR_INSTR=0,C_USE_PCMP_INSTR=0,C_USE_BARREL=0,C_USE_DIV=0,C_USE_HW_MUL=0,C_USE_FPU=0,C_USE_REORDER_INSTR=1,C_UNALIGNED_EXCEPTIONS=0,C_ILL_OPCODE_EXCEPTION=0,C_DIV_ZERO_EXCEPTION=0,C_FPU_EXCEPTION=0,C_FSL_LINKS=0,C_USE_EXTENDED_FSL_INSTR=0,C_FSL_EXCEPTION=0,C_USE_STACK_PROTECTION=0,C_IMPRECISE_EXCEPTIONS=0,C_USE_INTERRUPT=2,C_USE_EXT_BRK=0,C_USE_EXT_NM_BRK=0,C_USE_MMU=0,C_MMU_DTLB_SIZE=4,C_MMU_ITLB_SIZE=2,C_MMU_TLB_ACCESS=3,C_MMU_ZONES=16,C_MMU_PRIVILEGED_INSTR=0,C_USE_BRANCH_TARGET_CACHE=0,C_BRANCH_TARGET_CACHE_SIZE=0,C_PC_WIDTH=32,C_PVR=0,C_PVR_USER1=0x00,C_PVR_USER2=0x00000000,C_DYNAMIC_BUS_SIZING=0,C_RESET_MSR=0x00000000,C_OPCODE_0x0_ILLEGAL=0,C_DEBUG_ENABLED=1,C_NUMBER_OF_PC_BRK=1,C_NUMBER_OF_RD_ADDR_BRK=0,C_NUMBER_OF_WR_ADDR_BRK=0,C_DEBUG_EVENT_COUNTERS=5,C_DEBUG_LATENCY_COUNTERS=1,C_DEBUG_COUNTER_WIDTH=32,C_DEBUG_TRACE_SIZE=8192,C_DEBUG_EXTERNAL_TRACE=0,C_DEBUG_PROFILE_SIZE=0,C_INTERRUPT_IS_EDGE=0,C_EDGE_IS_POSITIVE=1,C_ASYNC_INTERRUPT=1,C_M0_AXIS_DATA_WIDTH=32,C_S0_AXIS_DATA_WIDTH=32,C_M1_AXIS_DATA_WIDTH=32,C_S1_AXIS_DATA_WIDTH=32,C_M2_AXIS_DATA_WIDTH=32,C_S2_AXIS_DATA_WIDTH=32,C_M3_AXIS_DATA_WIDTH=32,C_S3_AXIS_DATA_WIDTH=32,C_M4_AXIS_DATA_WIDTH=32,C_S4_AXIS_DATA_WIDTH=32,C_M5_AXIS_DATA_WIDTH=32,C_S5_AXIS_DATA_WIDTH=32,C_M6_AXIS_DATA_WIDTH=32,C_S6_AXIS_DATA_WIDTH=32,C_M7_AXIS_DATA_WIDTH=32,C_S7_AXIS_DATA_WIDTH=32,C_M8_AXIS_DATA_WIDTH=32,C_S8_AXIS_DATA_WIDTH=32,C_M9_AXIS_DATA_WIDTH=32,C_S9_AXIS_DATA_WIDTH=32,C_M10_AXIS_DATA_WIDTH=32,C_S10_AXIS_DATA_WIDTH=32,C_M11_AXIS_DATA_WIDTH=32,C_S11_AXIS_DATA_WIDTH=32,C_M12_AXIS_DATA_WIDTH=32,C_S12_AXIS_DATA_WIDTH=32,C_M13_AXIS_DATA_WIDTH=32,C_S13_AXIS_DATA_WIDTH=32,C_M14_AXIS_DATA_WIDTH=32,C_S14_AXIS_DATA_WIDTH=32,C_M15_AXIS_DATA_WIDTH=32,C_S15_AXIS_DATA_WIDTH=32,C_ICACHE_BASEADDR=0x60000000,C_ICACHE_HIGHADDR=0x60ffffff,C_USE_ICACHE=1,C_ALLOW_ICACHE_WR=1,C_ADDR_TAG_BITS=10,C_CACHE_BYTE_SIZE=16384,C_ICACHE_LINE_LEN=4,C_ICACHE_ALWAYS_USED=1,C_ICACHE_STREAMS=0,C_ICACHE_VICTIMS=0,C_ICACHE_FORCE_TAG_LUTRAM=0,C_ICACHE_DATA_WIDTH=0,C_M_AXI_IC_THREAD_ID_WIDTH=1,C_M_AXI_IC_DATA_WIDTH=32,C_M_AXI_IC_ADDR_WIDTH=32,C_M_AXI_IC_USER_VALUE=31,C_M_AXI_IC_AWUSER_WIDTH=5,C_M_AXI_IC_ARUSER_WIDTH=5,C_M_AXI_IC_WUSER_WIDTH=1,C_M_AXI_IC_RUSER_WIDTH=1,C_M_AXI_IC_BUSER_WIDTH=1,C_DCACHE_BASEADDR=0x60000000,C_DCACHE_HIGHADDR=0x60ffffff,C_USE_DCACHE=1,C_ALLOW_DCACHE_WR=1,C_DCACHE_ADDR_TAG=10,C_DCACHE_BYTE_SIZE=16384,C_DCACHE_LINE_LEN=4,C_DCACHE_ALWAYS_USED=1,C_DCACHE_USE_WRITEBACK=0,C_DCACHE_VICTIMS=0,C_DCACHE_FORCE_TAG_LUTRAM=0,C_DCACHE_DATA_WIDTH=0,C_M_AXI_DC_THREAD_ID_WIDTH=1,C_M_AXI_DC_DATA_WIDTH=32,C_M_AXI_DC_ADDR_WIDTH=32,C_M_AXI_DC_EXCLUSIVE_ACCESS=0,C_M_AXI_DC_USER_VALUE=31,C_M_AXI_DC_AWUSER_WIDTH=5,C_M_AXI_DC_ARUSER_WIDTH=5,C_M_AXI_DC_WUSER_WIDTH=1,C_M_AXI_DC_RUSER_WIDTH=1,C_M_AXI_DC_BUSER_WIDTH=1}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF Clk: SIGNAL IS "xilinx.com:signal:clock:1.0 CLK.CLK CLK";
ATTRIBUTE X_INTERFACE_INFO OF Reset: SIGNAL IS "xilinx.com:signal:reset:1.0 RST.RESET RST";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT INTERRUPT";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Address: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ADDRESS";
ATTRIBUTE X_INTERFACE_INFO OF Interrupt_Ack: SIGNAL IS "xilinx.com:interface:mbinterrupt:1.0 INTERRUPT ACK";
ATTRIBUTE X_INTERFACE_INFO OF Instr_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Instr: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF IFetch: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF I_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF IReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB READY";
ATTRIBUTE X_INTERFACE_INFO OF IWAIT: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF ICE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB CE";
ATTRIBUTE X_INTERFACE_INFO OF IUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 ILMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Data_Addr: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ABUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Read: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READDBUS";
ATTRIBUTE X_INTERFACE_INFO OF Data_Write: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITEDBUS";
ATTRIBUTE X_INTERFACE_INFO OF D_AS: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB ADDRSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Read_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READSTROBE";
ATTRIBUTE X_INTERFACE_INFO OF Write_Strobe: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WRITESTROBE";
ATTRIBUTE X_INTERFACE_INFO OF DReady: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB READY";
ATTRIBUTE X_INTERFACE_INFO OF DWait: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB WAIT";
ATTRIBUTE X_INTERFACE_INFO OF DCE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB CE";
ATTRIBUTE X_INTERFACE_INFO OF DUE: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB UE";
ATTRIBUTE X_INTERFACE_INFO OF Byte_Enable: SIGNAL IS "xilinx.com:interface:lmb:1.0 DLMB BE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DP_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DP RREADY";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Clk: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CLK";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDI: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDI";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_TDO: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG TDO";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Reg_En: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG REG_EN";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Shift: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG SHIFT";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Capture: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG CAPTURE";
ATTRIBUTE X_INTERFACE_INFO OF Dbg_Update: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG UPDATE";
ATTRIBUTE X_INTERFACE_INFO OF Debug_Rst: SIGNAL IS "xilinx.com:interface:mbdebug:3.0 DEBUG RST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_IC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_IC RREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_AWREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC AWREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WSTRB: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WSTRB";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_WREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC WREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_BREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC BREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARADDR: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARADDR";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLEN: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLEN";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARSIZE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARSIZE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARBURST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARBURST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARLOCK: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARLOCK";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARCACHE: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARCACHE";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARPROT: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARPROT";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARQOS: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARQOS";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_ARREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC ARREADY";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RDATA: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RDATA";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RRESP: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RRESP";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RLAST: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RLAST";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RVALID: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RVALID";
ATTRIBUTE X_INTERFACE_INFO OF M_AXI_DC_RREADY: SIGNAL IS "xilinx.com:interface:aximm:1.0 M_AXI_DC RREADY";
BEGIN
U0 : MicroBlaze
GENERIC MAP (
C_SCO => 0,
C_FREQ => 100000000,
C_USE_CONFIG_RESET => 0,
C_NUM_SYNC_FF_CLK => 2,
C_NUM_SYNC_FF_CLK_IRQ => 1,
C_NUM_SYNC_FF_CLK_DEBUG => 2,
C_NUM_SYNC_FF_DBG_CLK => 1,
C_FAULT_TOLERANT => 0,
C_ECC_USE_CE_EXCEPTION => 0,
C_LOCKSTEP_SLAVE => 0,
C_ENDIANNESS => 1,
C_FAMILY => "artix7",
C_DATA_SIZE => 32,
C_INSTANCE => "design_1_microblaze_0_0",
C_AVOID_PRIMITIVES => 0,
C_AREA_OPTIMIZED => 0,
C_OPTIMIZATION => 0,
C_INTERCONNECT => 2,
C_BASE_VECTORS => X"00000000",
C_M_AXI_DP_THREAD_ID_WIDTH => 1,
C_M_AXI_DP_DATA_WIDTH => 32,
C_M_AXI_DP_ADDR_WIDTH => 32,
C_M_AXI_DP_EXCLUSIVE_ACCESS => 0,
C_M_AXI_D_BUS_EXCEPTION => 0,
C_M_AXI_IP_THREAD_ID_WIDTH => 1,
C_M_AXI_IP_DATA_WIDTH => 32,
C_M_AXI_IP_ADDR_WIDTH => 32,
C_M_AXI_I_BUS_EXCEPTION => 0,
C_D_LMB => 1,
C_D_AXI => 1,
C_I_LMB => 1,
C_I_AXI => 0,
C_USE_MSR_INSTR => 0,
C_USE_PCMP_INSTR => 0,
C_USE_BARREL => 0,
C_USE_DIV => 0,
C_USE_HW_MUL => 0,
C_USE_FPU => 0,
C_USE_REORDER_INSTR => 1,
C_UNALIGNED_EXCEPTIONS => 0,
C_ILL_OPCODE_EXCEPTION => 0,
C_DIV_ZERO_EXCEPTION => 0,
C_FPU_EXCEPTION => 0,
C_FSL_LINKS => 0,
C_USE_EXTENDED_FSL_INSTR => 0,
C_FSL_EXCEPTION => 0,
C_USE_STACK_PROTECTION => 0,
C_IMPRECISE_EXCEPTIONS => 0,
C_USE_INTERRUPT => 2,
C_USE_EXT_BRK => 0,
C_USE_EXT_NM_BRK => 0,
C_USE_MMU => 0,
C_MMU_DTLB_SIZE => 4,
C_MMU_ITLB_SIZE => 2,
C_MMU_TLB_ACCESS => 3,
C_MMU_ZONES => 16,
C_MMU_PRIVILEGED_INSTR => 0,
C_USE_BRANCH_TARGET_CACHE => 0,
C_BRANCH_TARGET_CACHE_SIZE => 0,
C_PC_WIDTH => 32,
C_PVR => 0,
C_PVR_USER1 => X"00",
C_PVR_USER2 => X"00000000",
C_DYNAMIC_BUS_SIZING => 0,
C_RESET_MSR => X"00000000",
C_OPCODE_0x0_ILLEGAL => 0,
C_DEBUG_ENABLED => 1,
C_NUMBER_OF_PC_BRK => 1,
C_NUMBER_OF_RD_ADDR_BRK => 0,
C_NUMBER_OF_WR_ADDR_BRK => 0,
C_DEBUG_EVENT_COUNTERS => 5,
C_DEBUG_LATENCY_COUNTERS => 1,
C_DEBUG_COUNTER_WIDTH => 32,
C_DEBUG_TRACE_SIZE => 8192,
C_DEBUG_EXTERNAL_TRACE => 0,
C_DEBUG_PROFILE_SIZE => 0,
C_INTERRUPT_IS_EDGE => 0,
C_EDGE_IS_POSITIVE => 1,
C_ASYNC_INTERRUPT => 1,
C_M0_AXIS_DATA_WIDTH => 32,
C_S0_AXIS_DATA_WIDTH => 32,
C_M1_AXIS_DATA_WIDTH => 32,
C_S1_AXIS_DATA_WIDTH => 32,
C_M2_AXIS_DATA_WIDTH => 32,
C_S2_AXIS_DATA_WIDTH => 32,
C_M3_AXIS_DATA_WIDTH => 32,
C_S3_AXIS_DATA_WIDTH => 32,
C_M4_AXIS_DATA_WIDTH => 32,
C_S4_AXIS_DATA_WIDTH => 32,
C_M5_AXIS_DATA_WIDTH => 32,
C_S5_AXIS_DATA_WIDTH => 32,
C_M6_AXIS_DATA_WIDTH => 32,
C_S6_AXIS_DATA_WIDTH => 32,
C_M7_AXIS_DATA_WIDTH => 32,
C_S7_AXIS_DATA_WIDTH => 32,
C_M8_AXIS_DATA_WIDTH => 32,
C_S8_AXIS_DATA_WIDTH => 32,
C_M9_AXIS_DATA_WIDTH => 32,
C_S9_AXIS_DATA_WIDTH => 32,
C_M10_AXIS_DATA_WIDTH => 32,
C_S10_AXIS_DATA_WIDTH => 32,
C_M11_AXIS_DATA_WIDTH => 32,
C_S11_AXIS_DATA_WIDTH => 32,
C_M12_AXIS_DATA_WIDTH => 32,
C_S12_AXIS_DATA_WIDTH => 32,
C_M13_AXIS_DATA_WIDTH => 32,
C_S13_AXIS_DATA_WIDTH => 32,
C_M14_AXIS_DATA_WIDTH => 32,
C_S14_AXIS_DATA_WIDTH => 32,
C_M15_AXIS_DATA_WIDTH => 32,
C_S15_AXIS_DATA_WIDTH => 32,
C_ICACHE_BASEADDR => X"60000000",
C_ICACHE_HIGHADDR => X"60ffffff",
C_USE_ICACHE => 1,
C_ALLOW_ICACHE_WR => 1,
C_ADDR_TAG_BITS => 10,
C_CACHE_BYTE_SIZE => 16384,
C_ICACHE_LINE_LEN => 4,
C_ICACHE_ALWAYS_USED => 1,
C_ICACHE_STREAMS => 0,
C_ICACHE_VICTIMS => 0,
C_ICACHE_FORCE_TAG_LUTRAM => 0,
C_ICACHE_DATA_WIDTH => 0,
C_M_AXI_IC_THREAD_ID_WIDTH => 1,
C_M_AXI_IC_DATA_WIDTH => 32,
C_M_AXI_IC_ADDR_WIDTH => 32,
C_M_AXI_IC_USER_VALUE => 31,
C_M_AXI_IC_AWUSER_WIDTH => 5,
C_M_AXI_IC_ARUSER_WIDTH => 5,
C_M_AXI_IC_WUSER_WIDTH => 1,
C_M_AXI_IC_RUSER_WIDTH => 1,
C_M_AXI_IC_BUSER_WIDTH => 1,
C_DCACHE_BASEADDR => X"60000000",
C_DCACHE_HIGHADDR => X"60ffffff",
C_USE_DCACHE => 1,
C_ALLOW_DCACHE_WR => 1,
C_DCACHE_ADDR_TAG => 10,
C_DCACHE_BYTE_SIZE => 16384,
C_DCACHE_LINE_LEN => 4,
C_DCACHE_ALWAYS_USED => 1,
C_DCACHE_USE_WRITEBACK => 0,
C_DCACHE_VICTIMS => 0,
C_DCACHE_FORCE_TAG_LUTRAM => 0,
C_DCACHE_DATA_WIDTH => 0,
C_M_AXI_DC_THREAD_ID_WIDTH => 1,
C_M_AXI_DC_DATA_WIDTH => 32,
C_M_AXI_DC_ADDR_WIDTH => 32,
C_M_AXI_DC_EXCLUSIVE_ACCESS => 0,
C_M_AXI_DC_USER_VALUE => 31,
C_M_AXI_DC_AWUSER_WIDTH => 5,
C_M_AXI_DC_ARUSER_WIDTH => 5,
C_M_AXI_DC_WUSER_WIDTH => 1,
C_M_AXI_DC_RUSER_WIDTH => 1,
C_M_AXI_DC_BUSER_WIDTH => 1
)
PORT MAP (
Clk => Clk,
Reset => Reset,
Mb_Reset => '0',
Config_Reset => '0',
Scan_Reset => '0',
Scan_Reset_Sel => '0',
Dbg_Disable => '0',
Interrupt => Interrupt,
Interrupt_Address => Interrupt_Address,
Interrupt_Ack => Interrupt_Ack,
Ext_BRK => '0',
Ext_NM_BRK => '0',
Dbg_Stop => '0',
Wakeup => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
Reset_Mode => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
LOCKSTEP_Slave_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4096)),
Instr_Addr => Instr_Addr,
Instr => Instr,
IFetch => IFetch,
I_AS => I_AS,
IReady => IReady,
IWAIT => IWAIT,
ICE => ICE,
IUE => IUE,
M_AXI_IP_AWREADY => '0',
M_AXI_IP_WREADY => '0',
M_AXI_IP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_BRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_BVALID => '0',
M_AXI_IP_ARREADY => '0',
M_AXI_IP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IP_RDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IP_RRESP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 2)),
M_AXI_IP_RLAST => '0',
M_AXI_IP_RVALID => '0',
Data_Addr => Data_Addr,
Data_Read => Data_Read,
Data_Write => Data_Write,
D_AS => D_AS,
Read_Strobe => Read_Strobe,
Write_Strobe => Write_Strobe,
DReady => DReady,
DWait => DWait,
DCE => DCE,
DUE => DUE,
Byte_Enable => Byte_Enable,
M_AXI_DP_AWADDR => M_AXI_DP_AWADDR,
M_AXI_DP_AWPROT => M_AXI_DP_AWPROT,
M_AXI_DP_AWVALID => M_AXI_DP_AWVALID,
M_AXI_DP_AWREADY => M_AXI_DP_AWREADY,
M_AXI_DP_WDATA => M_AXI_DP_WDATA,
M_AXI_DP_WSTRB => M_AXI_DP_WSTRB,
M_AXI_DP_WVALID => M_AXI_DP_WVALID,
M_AXI_DP_WREADY => M_AXI_DP_WREADY,
M_AXI_DP_BID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_BRESP => M_AXI_DP_BRESP,
M_AXI_DP_BVALID => M_AXI_DP_BVALID,
M_AXI_DP_BREADY => M_AXI_DP_BREADY,
M_AXI_DP_ARADDR => M_AXI_DP_ARADDR,
M_AXI_DP_ARPROT => M_AXI_DP_ARPROT,
M_AXI_DP_ARVALID => M_AXI_DP_ARVALID,
M_AXI_DP_ARREADY => M_AXI_DP_ARREADY,
M_AXI_DP_RID => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DP_RDATA => M_AXI_DP_RDATA,
M_AXI_DP_RRESP => M_AXI_DP_RRESP,
M_AXI_DP_RLAST => '0',
M_AXI_DP_RVALID => M_AXI_DP_RVALID,
M_AXI_DP_RREADY => M_AXI_DP_RREADY,
Dbg_Clk => Dbg_Clk,
Dbg_TDI => Dbg_TDI,
Dbg_TDO => Dbg_TDO,
Dbg_Reg_En => Dbg_Reg_En,
Dbg_Shift => Dbg_Shift,
Dbg_Capture => Dbg_Capture,
Dbg_Update => Dbg_Update,
Dbg_Trig_Ack_In => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trig_Out => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 8)),
Dbg_Trace_Clk => '0',
Dbg_Trace_Ready => '0',
Debug_Rst => Debug_Rst,
M0_AXIS_TREADY => '0',
M1_AXIS_TREADY => '0',
M2_AXIS_TREADY => '0',
M3_AXIS_TREADY => '0',
M4_AXIS_TREADY => '0',
M5_AXIS_TREADY => '0',
M6_AXIS_TREADY => '0',
M7_AXIS_TREADY => '0',
M8_AXIS_TREADY => '0',
M9_AXIS_TREADY => '0',
M10_AXIS_TREADY => '0',
M11_AXIS_TREADY => '0',
M12_AXIS_TREADY => '0',
M13_AXIS_TREADY => '0',
M14_AXIS_TREADY => '0',
M15_AXIS_TREADY => '0',
S0_AXIS_TLAST => '0',
S0_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S0_AXIS_TVALID => '0',
S1_AXIS_TLAST => '0',
S1_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S1_AXIS_TVALID => '0',
S2_AXIS_TLAST => '0',
S2_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S2_AXIS_TVALID => '0',
S3_AXIS_TLAST => '0',
S3_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S3_AXIS_TVALID => '0',
S4_AXIS_TLAST => '0',
S4_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S4_AXIS_TVALID => '0',
S5_AXIS_TLAST => '0',
S5_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S5_AXIS_TVALID => '0',
S6_AXIS_TLAST => '0',
S6_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S6_AXIS_TVALID => '0',
S7_AXIS_TLAST => '0',
S7_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S7_AXIS_TVALID => '0',
S8_AXIS_TLAST => '0',
S8_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S8_AXIS_TVALID => '0',
S9_AXIS_TLAST => '0',
S9_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S9_AXIS_TVALID => '0',
S10_AXIS_TLAST => '0',
S10_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S10_AXIS_TVALID => '0',
S11_AXIS_TLAST => '0',
S11_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S11_AXIS_TVALID => '0',
S12_AXIS_TLAST => '0',
S12_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S12_AXIS_TVALID => '0',
S13_AXIS_TLAST => '0',
S13_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S13_AXIS_TVALID => '0',
S14_AXIS_TLAST => '0',
S14_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S14_AXIS_TVALID => '0',
S15_AXIS_TLAST => '0',
S15_AXIS_TDATA => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
S15_AXIS_TVALID => '0',
M_AXI_IC_AWID => M_AXI_IC_AWID,
M_AXI_IC_AWADDR => M_AXI_IC_AWADDR,
M_AXI_IC_AWLEN => M_AXI_IC_AWLEN,
M_AXI_IC_AWSIZE => M_AXI_IC_AWSIZE,
M_AXI_IC_AWBURST => M_AXI_IC_AWBURST,
M_AXI_IC_AWLOCK => M_AXI_IC_AWLOCK,
M_AXI_IC_AWCACHE => M_AXI_IC_AWCACHE,
M_AXI_IC_AWPROT => M_AXI_IC_AWPROT,
M_AXI_IC_AWQOS => M_AXI_IC_AWQOS,
M_AXI_IC_AWVALID => M_AXI_IC_AWVALID,
M_AXI_IC_AWREADY => M_AXI_IC_AWREADY,
M_AXI_IC_WDATA => M_AXI_IC_WDATA,
M_AXI_IC_WSTRB => M_AXI_IC_WSTRB,
M_AXI_IC_WLAST => M_AXI_IC_WLAST,
M_AXI_IC_WVALID => M_AXI_IC_WVALID,
M_AXI_IC_WREADY => M_AXI_IC_WREADY,
M_AXI_IC_BID => M_AXI_IC_BID,
M_AXI_IC_BRESP => M_AXI_IC_BRESP,
M_AXI_IC_BVALID => M_AXI_IC_BVALID,
M_AXI_IC_BREADY => M_AXI_IC_BREADY,
M_AXI_IC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ARID => M_AXI_IC_ARID,
M_AXI_IC_ARADDR => M_AXI_IC_ARADDR,
M_AXI_IC_ARLEN => M_AXI_IC_ARLEN,
M_AXI_IC_ARSIZE => M_AXI_IC_ARSIZE,
M_AXI_IC_ARBURST => M_AXI_IC_ARBURST,
M_AXI_IC_ARLOCK => M_AXI_IC_ARLOCK,
M_AXI_IC_ARCACHE => M_AXI_IC_ARCACHE,
M_AXI_IC_ARPROT => M_AXI_IC_ARPROT,
M_AXI_IC_ARQOS => M_AXI_IC_ARQOS,
M_AXI_IC_ARVALID => M_AXI_IC_ARVALID,
M_AXI_IC_ARREADY => M_AXI_IC_ARREADY,
M_AXI_IC_RID => M_AXI_IC_RID,
M_AXI_IC_RDATA => M_AXI_IC_RDATA,
M_AXI_IC_RRESP => M_AXI_IC_RRESP,
M_AXI_IC_RLAST => M_AXI_IC_RLAST,
M_AXI_IC_RVALID => M_AXI_IC_RVALID,
M_AXI_IC_RREADY => M_AXI_IC_RREADY,
M_AXI_IC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_IC_ACVALID => '0',
M_AXI_IC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_IC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_IC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_IC_CRREADY => '0',
M_AXI_IC_CDREADY => '0',
M_AXI_DC_AWID => M_AXI_DC_AWID,
M_AXI_DC_AWADDR => M_AXI_DC_AWADDR,
M_AXI_DC_AWLEN => M_AXI_DC_AWLEN,
M_AXI_DC_AWSIZE => M_AXI_DC_AWSIZE,
M_AXI_DC_AWBURST => M_AXI_DC_AWBURST,
M_AXI_DC_AWLOCK => M_AXI_DC_AWLOCK,
M_AXI_DC_AWCACHE => M_AXI_DC_AWCACHE,
M_AXI_DC_AWPROT => M_AXI_DC_AWPROT,
M_AXI_DC_AWQOS => M_AXI_DC_AWQOS,
M_AXI_DC_AWVALID => M_AXI_DC_AWVALID,
M_AXI_DC_AWREADY => M_AXI_DC_AWREADY,
M_AXI_DC_WDATA => M_AXI_DC_WDATA,
M_AXI_DC_WSTRB => M_AXI_DC_WSTRB,
M_AXI_DC_WLAST => M_AXI_DC_WLAST,
M_AXI_DC_WVALID => M_AXI_DC_WVALID,
M_AXI_DC_WREADY => M_AXI_DC_WREADY,
M_AXI_DC_BRESP => M_AXI_DC_BRESP,
M_AXI_DC_BID => M_AXI_DC_BID,
M_AXI_DC_BVALID => M_AXI_DC_BVALID,
M_AXI_DC_BREADY => M_AXI_DC_BREADY,
M_AXI_DC_BUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ARID => M_AXI_DC_ARID,
M_AXI_DC_ARADDR => M_AXI_DC_ARADDR,
M_AXI_DC_ARLEN => M_AXI_DC_ARLEN,
M_AXI_DC_ARSIZE => M_AXI_DC_ARSIZE,
M_AXI_DC_ARBURST => M_AXI_DC_ARBURST,
M_AXI_DC_ARLOCK => M_AXI_DC_ARLOCK,
M_AXI_DC_ARCACHE => M_AXI_DC_ARCACHE,
M_AXI_DC_ARPROT => M_AXI_DC_ARPROT,
M_AXI_DC_ARQOS => M_AXI_DC_ARQOS,
M_AXI_DC_ARVALID => M_AXI_DC_ARVALID,
M_AXI_DC_ARREADY => M_AXI_DC_ARREADY,
M_AXI_DC_RID => M_AXI_DC_RID,
M_AXI_DC_RDATA => M_AXI_DC_RDATA,
M_AXI_DC_RRESP => M_AXI_DC_RRESP,
M_AXI_DC_RLAST => M_AXI_DC_RLAST,
M_AXI_DC_RVALID => M_AXI_DC_RVALID,
M_AXI_DC_RREADY => M_AXI_DC_RREADY,
M_AXI_DC_RUSER => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 1)),
M_AXI_DC_ACVALID => '0',
M_AXI_DC_ACADDR => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 32)),
M_AXI_DC_ACSNOOP => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 4)),
M_AXI_DC_ACPROT => STD_LOGIC_VECTOR(TO_UNSIGNED(0, 3)),
M_AXI_DC_CRREADY => '0',
M_AXI_DC_CDREADY => '0'
);
END design_1_microblaze_0_0_arch;
|
-- ____ _____
-- ________ _________ ____ / __ \/ ___/
-- / ___/ _ \/ ___/ __ \/ __ \/ / / /\__ \
-- / / / __/ /__/ /_/ / / / / /_/ /___/ /
-- /_/ \___/\___/\____/_/ /_/\____//____/
--
-- ======================================================================
--
-- title: IP-Core - INTC - Top level entity
--
-- project: ReconOS
-- author: Christoph R??thing, University of Paderborn
-- description: A simple interrupt controller with variable number of
-- inputs to connect the RECONOS_AXI_FIFO-interrupts to
-- the processor.
--
-- ======================================================================
<<reconos_preproc>>
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library axi_lite_ipif_v3_0_4;
use axi_lite_ipif_v3_0_4.ipif_pkg.all;
use axi_lite_ipif_v3_0_4.axi_lite_ipif;
entity reconos_osif_intc is
generic (
-- INTC paramters
C_NUM_INTERRUPTS : integer := 1;
-- Bus protocol parameters, do not add to or delete
C_S_AXI_DATA_WIDTH : integer := 32;
C_S_AXI_ADDR_WIDTH : integer := 32;
C_S_AXI_MIN_SIZE : std_logic_vector := X"000001FF";
C_USE_WSTRB : integer := 0;
C_DPHASE_TIMEOUT : integer := 8;
C_BASEADDR : std_logic_vector := X"FFFFFFFF";
C_HIGHADDR : std_logic_vector := X"00000000";
C_FAMILY : string := "virtex6";
C_NUM_REG : integer := 1;
C_NUM_MEM : integer := 1;
C_SLV_AWIDTH : integer := 32;
C_SLV_DWIDTH : integer := 32
);
port (
-- INTC ports
<<generate for SLOTS>>
OSIF_INTC_In_<<Id>> : in std_logic;
<<end generate>>
OSIF_INTC_Out : out std_logic;
-- Bus protocol ports, do not add to or delete
S_AXI_ACLK : in std_logic;
S_AXI_ARESETN : in std_logic;
S_AXI_AWADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_AWVALID : in std_logic;
S_AXI_WDATA : in std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_WSTRB : in std_logic_vector((C_S_AXI_DATA_WIDTH/8)-1 downto 0);
S_AXI_WVALID : in std_logic;
S_AXI_BREADY : in std_logic;
S_AXI_ARADDR : in std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
S_AXI_ARVALID : in std_logic;
S_AXI_RREADY : in std_logic;
S_AXI_ARREADY : out std_logic;
S_AXI_RDATA : out std_logic_vector(C_S_AXI_DATA_WIDTH-1 downto 0);
S_AXI_RRESP : out std_logic_vector(1 downto 0);
S_AXI_RVALID : out std_logic;
S_AXI_WREADY : out std_logic;
S_AXI_BRESP : out std_logic_vector(1 downto 0);
S_AXI_BVALID : out std_logic;
S_AXI_AWREADY : out std_logic
);
end entity reconos_osif_intc;
architecture implementation of reconos_osif_intc is
-- Declare port attributes for the Vivado IP Packager
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_PARAMETER : STRING;
<<generate for SLOTS>>
ATTRIBUTE X_INTERFACE_INFO of OSIF_INTC_In_<<Id>>: SIGNAL is "xilinx.com:signal:interrupt:1.0 OSIF_INTC_In_<<Id>> INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER of OSIF_INTC_In_<<Id>>: SIGNAL is "SENSITIVITY LEVEL_HIGH";
<<end generate>>
ATTRIBUTE X_INTERFACE_INFO of OSIF_INTC_Out: SIGNAL is "xilinx.com:signal:interrupt:1.0 OSIF_INTC_Out INTERRUPT";
ATTRIBUTE X_INTERFACE_PARAMETER of OSIF_INTC_Out: SIGNAL is "SENSITIVITY LEVEL_HIGH";
constant USER_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant IPIF_SLV_DWIDTH : integer := C_S_AXI_DATA_WIDTH;
constant ZERO_ADDR_PAD : std_logic_vector(0 to 31) := (others => '0');
constant USER_SLV_BASEADDR : std_logic_vector := C_BASEADDR;
constant USER_SLV_HIGHADDR : std_logic_vector := C_HIGHADDR;
constant IPIF_ARD_ADDR_RANGE_ARRAY : SLV64_ARRAY_TYPE :=
(
ZERO_ADDR_PAD & USER_SLV_BASEADDR, -- user logic slave space base address
ZERO_ADDR_PAD & USER_SLV_HIGHADDR -- user logic slave space high address
);
constant USER_SLV_NUM_REG : integer := C_NUM_INTERRUPTS / C_SLV_DWIDTH + 1;
constant USER_NUM_REG : integer := USER_SLV_NUM_REG;
constant TOTAL_IPIF_CE : integer := USER_NUM_REG;
constant IPIF_ARD_NUM_CE_ARRAY : INTEGER_ARRAY_TYPE :=
(
0 => (USER_SLV_NUM_REG) -- number of ce for user logic slave space
);
-- Index for CS/CE
constant USER_SLV_CS_INDEX : integer := 0;
constant USER_SLV_CE_INDEX : integer := calc_start_ce_index(IPIF_ARD_NUM_CE_ARRAY, USER_SLV_CS_INDEX);
constant USER_CE_INDEX : integer := USER_SLV_CE_INDEX;
-- IP Interconnect (IPIC) signal declarations
signal ipif_Bus2IP_Clk : std_logic;
signal ipif_Bus2IP_Resetn : std_logic;
signal ipif_Bus2IP_Addr : std_logic_vector(C_S_AXI_ADDR_WIDTH-1 downto 0);
signal ipif_Bus2IP_RNW : std_logic;
signal ipif_Bus2IP_BE : std_logic_vector(IPIF_SLV_DWIDTH/8-1 downto 0);
signal ipif_Bus2IP_CS : std_logic_vector((IPIF_ARD_ADDR_RANGE_ARRAY'LENGTH)/2-1 downto 0);
signal ipif_Bus2IP_RdCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_WrCE : std_logic_vector(calc_num_ce(IPIF_ARD_NUM_CE_ARRAY)-1 downto 0);
signal ipif_Bus2IP_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal ipif_IP2Bus_WrAck : std_logic;
signal ipif_IP2Bus_RdAck : std_logic;
signal ipif_IP2Bus_Error : std_logic;
signal ipif_IP2Bus_Data : std_logic_vector(IPIF_SLV_DWIDTH-1 downto 0);
signal user_Bus2IP_RdCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_Bus2IP_WrCE : std_logic_vector(USER_NUM_REG-1 downto 0);
signal user_IP2Bus_Data : std_logic_vector(USER_SLV_DWIDTH-1 downto 0);
signal user_IP2Bus_RdAck : std_logic;
signal user_IP2Bus_WrAck : std_logic;
signal user_IP2Bus_Error : std_logic;
signal intc_in : std_logic_vector(C_NUM_INTERRUPTS - 1 downto 0);
begin
AXI_LITE_IPIF_I : entity axi_lite_ipif_v3_0_4.axi_lite_ipif
generic map (
C_S_AXI_DATA_WIDTH => IPIF_SLV_DWIDTH,
C_S_AXI_ADDR_WIDTH => C_S_AXI_ADDR_WIDTH,
C_S_AXI_MIN_SIZE => C_S_AXI_MIN_SIZE,
C_USE_WSTRB => C_USE_WSTRB,
C_DPHASE_TIMEOUT => C_DPHASE_TIMEOUT,
C_ARD_ADDR_RANGE_ARRAY => IPIF_ARD_ADDR_RANGE_ARRAY,
C_ARD_NUM_CE_ARRAY => IPIF_ARD_NUM_CE_ARRAY,
C_FAMILY => C_FAMILY
)
port map (
S_AXI_ACLK => S_AXI_ACLK,
S_AXI_ARESETN => S_AXI_ARESETN,
S_AXI_AWADDR => S_AXI_AWADDR,
S_AXI_AWVALID => S_AXI_AWVALID,
S_AXI_WDATA => S_AXI_WDATA,
S_AXI_WSTRB => S_AXI_WSTRB,
S_AXI_WVALID => S_AXI_WVALID,
S_AXI_BREADY => S_AXI_BREADY,
S_AXI_ARADDR => S_AXI_ARADDR,
S_AXI_ARVALID => S_AXI_ARVALID,
S_AXI_RREADY => S_AXI_RREADY,
S_AXI_ARREADY => S_AXI_ARREADY,
S_AXI_RDATA => S_AXI_RDATA,
S_AXI_RRESP => S_AXI_RRESP,
S_AXI_RVALID => S_AXI_RVALID,
S_AXI_WREADY => S_AXI_WREADY,
S_AXI_BRESP => S_AXI_BRESP,
S_AXI_BVALID => S_AXI_BVALID,
S_AXI_AWREADY => S_AXI_AWREADY,
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Addr => ipif_Bus2IP_Addr,
Bus2IP_RNW => ipif_Bus2IP_RNW,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_CS => ipif_Bus2IP_CS,
Bus2IP_RdCE => ipif_Bus2IP_RdCE,
Bus2IP_WrCE => ipif_Bus2IP_WrCE,
Bus2IP_Data => ipif_Bus2IP_Data,
IP2Bus_WrAck => ipif_IP2Bus_WrAck,
IP2Bus_RdAck => ipif_IP2Bus_RdAck,
IP2Bus_Error => ipif_IP2Bus_Error,
IP2Bus_Data => ipif_IP2Bus_Data
);
USER_LOGIC_I : entity work.reconos_osif_intc_user_logic
generic map (
-- INTC ports
C_NUM_INTERRUPTS => C_NUM_INTERRUPTS,
-- Bus protocol parameters
C_NUM_REG => USER_NUM_REG,
C_SLV_DWIDTH => USER_SLV_DWIDTH
)
port map (
-- INTC ports
OSIF_INTC_In => intc_in,
OSIF_INTC_Out => OSIF_INTC_Out,
-- Bus protocol ports
Bus2IP_Clk => ipif_Bus2IP_Clk,
Bus2IP_Resetn => ipif_Bus2IP_Resetn,
Bus2IP_Data => ipif_Bus2IP_Data,
Bus2IP_BE => ipif_Bus2IP_BE,
Bus2IP_RdCE => user_Bus2IP_RdCE,
Bus2IP_WrCE => user_Bus2IP_WrCE,
IP2Bus_Data => user_IP2Bus_Data,
IP2Bus_RdAck => user_IP2Bus_RdAck,
IP2Bus_WrAck => user_IP2Bus_WrAck,
IP2Bus_Error => user_IP2Bus_Error
);
-- connect internal signals
ipif_IP2Bus_Data <= user_IP2Bus_Data;
ipif_IP2Bus_WrAck <= user_IP2Bus_WrAck;
ipif_IP2Bus_RdAck <= user_IP2Bus_RdAck;
ipif_IP2Bus_Error <= user_IP2Bus_Error;
user_Bus2IP_RdCE <= ipif_Bus2IP_RdCE(USER_NUM_REG-1 downto 0);
user_Bus2IP_WrCE <= ipif_Bus2IP_WrCE(USER_NUM_REG-1 downto 0);
<<generate for SLOTS>>
intc_in(<<_i>>) <= OSIF_INTC_In_<<Id>>;
<<end generate>>
end implementation;
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
---------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
PACKAGE mlite_pack IS
-----------------------------------------------------------------------------------
--
--
CONSTANT ZERO : std_logic_vector(31 DOWNTO 0) :=
"00000000000000000000000000000000";
CONSTANT ONES : std_logic_vector(31 DOWNTO 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
CONSTANT HIGH_Z : std_logic_vector(31 DOWNTO 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
-----------------------------------------------------------------------------------
--
--
--subtype alu_function_type is std_logic_vector(3 downto 0);
--constant ALU_NOTHING : alu_function_type := "0000";
--constant ALU_ADD : alu_function_type := "0001";
--constant ALU_SUBTRACT : alu_function_type := "0010";
--constant ALU_LESS_THAN : alu_function_type := "0011";
--constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
--constant ALU_OR : alu_function_type := "0101";
--constant ALU_AND : alu_function_type := "0110";
--constant ALU_XOR : alu_function_type := "0111";
--constant ALU_NOR : alu_function_type := "1000";
TYPE alu_function_type IS (
ALU_NOTHING
, ALU_ADD
, ALU_SUBTRACT
-- BEGIN ENABLE_(SLT,SLTU,SLTI,SLTIU)
, ALU_LESS_THAN
, ALU_LESS_THAN_SIGNED
-- END ENABLE_(SLT,SLTU,SLTI,SLTIU)
, ALU_OR
-- BEGIN ENABLE_(AND,ANDI)
, ALU_AND
-- END ENABLE_(AND,ANDI)
-- BEGIN ENABLE_(XOR,XORI)
, ALU_XOR
-- END ENABLE_(XOR,XORI)
-- BEGIN ENABLE_(NOR)
, ALU_NOR
-- END ENABLE_(NOR)
);
-----------------------------------------------------------------------------------
--
--
--subtype shift_function_type is std_logic_vector(1 downto 0);
--constant SHIFT_NOTHING : shift_function_type := "00";
--constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
--constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
--constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
TYPE shift_function_type IS (
SHIFT_NOTHING
-- IMPOSSIBLE A SUPPRIMER A CAUSE DE L'INSTRUCTION (NOP)
, SHIFT_LEFT_UNSIGNED
-- FIN DE NOP
-- BEGIN ENABLE_(SRA,SRAV)
, SHIFT_RIGHT_SIGNED
-- END ENABLE_(SRA,SRAV)
-- BEGIN ENABLE_(SRL,SRLV)
, SHIFT_RIGHT_UNSIGNED
-- END ENABLE_(SRL,SRLV)
);
-----------------------------------------------------------------------------------
--
--
-- subtype mult_function_type is std_logic_vector(3 downto 0);
-- constant MULT_NOTHING : mult_function_type := "0000";
-- constant MULT_READ_LO : mult_function_type := "0001";
-- constant MULT_READ_HI : mult_function_type := "0010";
-- constant MULT_WRITE_LO : mult_function_type := "0011";
-- constant MULT_WRITE_HI : mult_function_type := "0100";
-- constant MULT_MULT : mult_function_type := "0101";
-- constant MULT_SIGNED_MULT : mult_function_type := "0110";
-- constant MULT_DIVIDE : mult_function_type := "0111";
-- constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
TYPE mult_function_type IS (MULT_NOTHING
-- BEGIN ENABLE_(MFLO)
, MULT_READ_LO
-- END ENABLE_(MFLO)
-- BEGIN ENABLE_(MFHI)
, MULT_READ_HI
-- END ENABLE_(MFHI)
-- BEGIN ENABLE_(MTLO)
, MULT_WRITE_LO
-- END ENABLE_(MTLO)
-- BEGIN ENABLE_(MTHI)
, MULT_WRITE_HI
-- END ENABLE_(MTHI)
-- BEGIN ENABLE_(MULTU)
, MULT_MULT
-- END ENABLE_(MULTU)
-- BEGIN ENABLE_(MULT)
, MULT_SIGNED_MULT
-- END ENABLE_(MULT)
-- BEGIN ENABLE_(DIVU)
, MULT_DIVIDE
-- END ENABLE_(DIVU)
-- BEGIN ENABLE_(DIV)
, MULT_SIGNED_DIVIDE
-- END ENABLE_(DIV)
);
-----------------------------------------------------------------------------------
--
--
SUBTYPE a_source_type IS std_logic_vector(1 DOWNTO 0);
CONSTANT A_FROM_REG_SOURCE : a_source_type := "00";
CONSTANT A_FROM_IMM10_6 : a_source_type := "01";
CONSTANT A_FROM_PC : a_source_type := "10";
-----------------------------------------------------------------------------------
--
--
SUBTYPE b_source_type IS std_logic_vector(1 DOWNTO 0);
CONSTANT B_FROM_REG_TARGET : b_source_type := "00";
CONSTANT B_FROM_IMM : b_source_type := "01";
CONSTANT B_FROM_SIGNED_IMM : b_source_type := "10";
CONSTANT B_FROM_IMMX4 : b_source_type := "11";
-----------------------------------------------------------------------------------
--
--
SUBTYPE c_source_type IS std_logic_vector(2 DOWNTO 0);
CONSTANT C_FROM_NULL : c_source_type := "000";
CONSTANT C_FROM_ALU : c_source_type := "001";
CONSTANT C_FROM_SHIFT : c_source_type := "001"; --same as alu
CONSTANT C_FROM_MULT : c_source_type := "001"; --same as alu
CONSTANT C_FROM_MEMORY : c_source_type := "010";
CONSTANT C_FROM_PC : c_source_type := "011";
CONSTANT C_FROM_PC_PLUS4 : c_source_type := "100";
CONSTANT C_FROM_IMM_SHIFT16 : c_source_type := "101";
CONSTANT C_FROM_REG_SOURCEN : c_source_type := "110";
CONSTANT C_FROM_EXTENSIONS : c_source_type := "111";
-----------------------------------------------------------------------------------
--
--
SUBTYPE pc_source_type IS std_logic_vector(1 DOWNTO 0);
CONSTANT FROM_INC4 : pc_source_type := "00";
CONSTANT FROM_OPCODE25_0 : pc_source_type := "01";
CONSTANT FROM_BRANCH : pc_source_type := "10";
CONSTANT FROM_LBRANCH : pc_source_type := "11";
-----------------------------------------------------------------------------------
--
--
-- subtype branch_function_type is std_logic_vector(2 downto 0);
-- constant BRANCH_LTZ : branch_function_type := "000";
-- constant BRANCH_LEZ : branch_function_type := "001";
-- constant BRANCH_EQ : branch_function_type := "010";
-- constant BRANCH_NE : branch_function_type := "011";
-- constant BRANCH_GEZ : branch_function_type := "100";
-- constant BRANCH_GTZ : branch_function_type := "101";
-- constant BRANCH_YES : branch_function_type := "110";
-- constant BRANCH_NO : branch_function_type := "111";
TYPE branch_function_type IS (
BRANCH_EQ
-- BEGIN ENABLE_(BLTZ,BLTZAL)
, BRANCH_LTZ
-- END ENABLE_(BLTZ,BLTZAL)
-- BEGIN ENABLE_(BLEZ)
, BRANCH_LEZ
-- END ENABLE_(BLEZ)
-- ON DEPLACE ,BRANCH_EQ
-- BEGIN ENABLE_(BNE)
, BRANCH_NE
-- END ENABLE_(BNE)
-- BEGIN ENABLE_(BGEZ,BGEZAL)
, BRANCH_GEZ
-- END ENABLE_(BGEZ,BGEZAL)
-- NE PEUT PAS ETRE ENLEVE FACILEMENT...
, BRANCH_GTZ
, BRANCH_YES
, BRANCH_NO
);
-----------------------------------------------------------------------------------
--
--
-- mode(32=1,16=2,8=3), signed, write
-- subtype mem_source_type is std_logic_vector(3 downto 0);
-- constant MEM_FETCH : mem_source_type := "0000";
-- constant MEM_READ32 : mem_source_type := "0100";
-- constant MEM_WRITE32 : mem_source_type := "0101";
-- constant MEM_READ16 : mem_source_type := "1000";
-- constant MEM_READ16S : mem_source_type := "1010";
-- constant MEM_WRITE16 : mem_source_type := "1001";
-- constant MEM_READ8 : mem_source_type := "1100";
-- constant MEM_READ8S : mem_source_type := "1110";
-- constant MEM_WRITE8 : mem_source_type := "1101";
TYPE mem_source_type IS (
MEM_FETCH
, MEM_READ32
, MEM_WRITE32
-- BEGIN ENABLE_(LHU)
, MEM_READ16
-- END ENABLE_(LHU)
-- BEGIN ENABLE_(LH)
, MEM_READ16S
-- END ENABLE_(LH)
-- BEGIN ENABLE_(SH)
, MEM_WRITE16
-- END ENABLE_(SH)
-- BEGIN ENABLE_(LBU)
, MEM_READ8
-- END ENABLE_(LBU)
-- BEGIN ENABLE_(LB)
, MEM_READ8S
-- END ENABLE_(LB)
-- BEGIN ENABLE_(SB)
, MEM_WRITE8
-- END ENABLE_(SB)
);
-----------------------------------------------------------------------------------
--
--
FUNCTION bv_adder(a : IN std_logic_vector;
b : IN std_logic_vector;
do_add : IN std_logic) RETURN std_logic_vector;
FUNCTION bv_negate(a : IN std_logic_vector) RETURN std_logic_vector;
FUNCTION bv_increment(a : IN std_logic_vector(31 DOWNTO 2)
) RETURN std_logic_vector;
FUNCTION bv_inc(a : IN std_logic_vector
) RETURN std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
GENERIC (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
PORT (
RDCLOCK : IN std_logic := '0';
RDCLKEN : IN std_logic := '1';
RDADDRESS : IN std_logic_vector(LPM_WIDTHAD-1 DOWNTO 0);
RDEN : IN std_logic := '1';
DATA : IN std_logic_vector(LPM_WIDTH-1 DOWNTO 0);
WRADDRESS : IN std_logic_vector(LPM_WIDTHAD-1 DOWNTO 0);
WREN : IN std_logic;
WRCLOCK : IN std_logic := '0';
WRCLKEN : IN std_logic := '1';
Q : OUT std_logic_vector(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;
-- For Altera
COMPONENT LPM_RAM_DQ
GENERIC (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
PORT (
DATA : IN std_logic_vector(LPM_WIDTH-1 DOWNTO 0);
ADDRESS : IN std_logic_vector(LPM_WIDTHAD-1 DOWNTO 0);
INCLOCK : IN std_logic := '0';
OUTCLOCK : IN std_logic := '0';
WE : IN std_logic;
Q : OUT std_logic_vector(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;
-- For Xilinx
COMPONENT RAM16X1D
-- synthesis translate_off
GENERIC (INIT : bit_vector := X"16");
-- synthesis translate_on
PORT (DPO : OUT std_ulogic;
SPO : OUT std_ulogic;
A0 : IN std_ulogic;
A1 : IN std_ulogic;
A2 : IN std_ulogic;
A3 : IN std_ulogic;
D : IN std_ulogic;
DPRA0 : IN std_ulogic;
DPRA1 : IN std_ulogic;
DPRA2 : IN std_ulogic;
DPRA3 : IN std_ulogic;
WCLK : IN std_ulogic;
WE : IN std_ulogic);
END COMPONENT;
-- For Xilinx Virtex-5
COMPONENT RAM32X1D
-- synthesis translate_off
GENERIC (INIT : bit_vector := X"32");
-- synthesis translate_on
PORT (DPO : OUT std_ulogic;
SPO : OUT std_ulogic;
A0 : IN std_ulogic;
A1 : IN std_ulogic;
A2 : IN std_ulogic;
A3 : IN std_ulogic;
A4 : IN std_ulogic;
D : IN std_ulogic;
DPRA0 : IN std_ulogic;
DPRA1 : IN std_ulogic;
DPRA2 : IN std_ulogic;
DPRA3 : IN std_ulogic;
DPRA4 : IN std_ulogic;
WCLK : IN std_ulogic;
WE : IN std_ulogic);
END COMPONENT;
COMPONENT pc_next
PORT(clk : IN std_logic;
reset_in : IN std_logic;
pc_new : IN std_logic_vector(31 DOWNTO 2);
take_branch : IN std_logic;
pause_in : IN std_logic;
opcode25_0 : IN std_logic_vector(25 DOWNTO 0);
pc_source : IN pc_source_type;
pc_future : OUT std_logic_vector(31 DOWNTO 2);
pc_current : OUT std_logic_vector(31 DOWNTO 2);
pc_plus4 : OUT std_logic_vector(31 DOWNTO 2));
END COMPONENT;
COMPONENT mem_ctrl
PORT(clk : IN std_logic;
reset_in : IN std_logic;
pause_in : IN std_logic;
nullify_op : IN std_logic;
address_pc : IN std_logic_vector(31 DOWNTO 2);
opcode_out : OUT std_logic_vector(31 DOWNTO 0);
address_in : IN std_logic_vector(31 DOWNTO 0);
mem_source : IN mem_source_type;
data_write : IN std_logic_vector(31 DOWNTO 0);
data_read : OUT std_logic_vector(31 DOWNTO 0);
pause_out : OUT std_logic;
address_next : OUT std_logic_vector(31 DOWNTO 2);
byte_we_next : OUT std_logic_vector(3 DOWNTO 0);
address : OUT std_logic_vector(31 DOWNTO 2);
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_w : OUT std_logic_vector(31 DOWNTO 0);
data_r : IN std_logic_vector(31 DOWNTO 0));
END COMPONENT;
COMPONENT control
PORT(opcode : IN std_logic_vector(31 DOWNTO 0);
intr_signal : IN std_logic;
rs_index : OUT std_logic_vector(5 DOWNTO 0);
rt_index : OUT std_logic_vector(5 DOWNTO 0);
rd_index : OUT std_logic_vector(5 DOWNTO 0);
imm_out : OUT std_logic_vector(15 DOWNTO 0);
alu_func : OUT alu_function_type;
shift_func : OUT shift_function_type;
mult_func : OUT mult_function_type;
branch_func : OUT branch_function_type;
calu_1_func : OUT std_logic_vector(5 DOWNTO 0);
salu_1_func : OUT std_logic_vector(5 DOWNTO 0);
a_source_out : OUT a_source_type;
b_source_out : OUT b_source_type;
c_source_out : OUT c_source_type;
pc_source_out : OUT pc_source_type;
mem_source_out : OUT mem_source_type;
exception_out : OUT std_logic);
END COMPONENT;
COMPONENT reg_bank
GENERIC(memory_type : string := "XILINX_16X");
PORT(clk : IN std_logic;
reset_in : IN std_logic;
pause : IN std_logic;
rs_index : IN std_logic_vector(5 DOWNTO 0);
rt_index : IN std_logic_vector(5 DOWNTO 0);
rd_index : IN std_logic_vector(5 DOWNTO 0);
reg_source_out : OUT std_logic_vector(31 DOWNTO 0);
reg_target_out : OUT std_logic_vector(31 DOWNTO 0);
reg_dest_new : IN std_logic_vector(31 DOWNTO 0);
intr_enable : OUT std_logic);
END COMPONENT;
COMPONENT bus_mux
PORT(imm_in : IN std_logic_vector(15 DOWNTO 0);
reg_source : IN std_logic_vector(31 DOWNTO 0);
a_mux : IN a_source_type;
a_out : OUT std_logic_vector(31 DOWNTO 0);
reg_target : IN std_logic_vector(31 DOWNTO 0);
b_mux : IN b_source_type;
b_out : OUT std_logic_vector(31 DOWNTO 0);
c_bus : IN std_logic_vector(31 DOWNTO 0);
c_memory : IN std_logic_vector(31 DOWNTO 0);
c_pc : IN std_logic_vector(31 DOWNTO 2);
c_pc_plus4 : IN std_logic_vector(31 DOWNTO 2);
c_mux : IN c_source_type;
reg_dest_out : OUT std_logic_vector(31 DOWNTO 0);
branch_func : IN branch_function_type;
take_branch : OUT std_logic);
END COMPONENT;
---------------------------------------------------------------------------------------
COMPONENT alu
GENERIC(
alu_type : string := "DEFAULT"
);
PORT(
a_in : IN std_logic_vector(31 DOWNTO 0);
b_in : IN std_logic_vector(31 DOWNTO 0);
alu_function : IN alu_function_type;
c_alu : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT shifter
GENERIC(
shifter_type : string := "DEFAULT"
);
PORT(value : IN std_logic_vector(31 DOWNTO 0);
shift_amount : IN std_logic_vector(4 DOWNTO 0);
shift_func : IN shift_function_type;
c_shift : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT mult
GENERIC(
mult_type : string := "DEFAULT"
);
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
a : IN std_logic_vector(31 DOWNTO 0);
b : IN std_logic_vector(31 DOWNTO 0);
mult_func : IN mult_function_type;
c_mult : OUT std_logic_vector(31 DOWNTO 0);
pause_out : OUT std_logic
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT pipeline
PORT(
clk : IN std_logic;
reset : IN std_logic;
a_bus : IN std_logic_vector(31 DOWNTO 0);
a_busD : OUT std_logic_vector(31 DOWNTO 0);
b_bus : IN std_logic_vector(31 DOWNTO 0);
b_busD : OUT std_logic_vector(31 DOWNTO 0);
alu_func : IN alu_function_type;
alu_funcD : OUT alu_function_type;
shift_func : IN shift_function_type;
shift_funcD : OUT shift_function_type;
mult_func : IN mult_function_type;
mult_funcD : OUT mult_function_type;
calu_1_func : IN std_logic_vector(5 DOWNTO 0);
calu_1_funcD : OUT std_logic_vector(5 DOWNTO 0);
salu_1_func : IN std_logic_vector(5 DOWNTO 0);
salu_1_funcD : OUT std_logic_vector(5 DOWNTO 0);
reg_dest : IN std_logic_vector(31 DOWNTO 0);
reg_destD : OUT std_logic_vector(31 DOWNTO 0);
rd_index : IN std_logic_vector(5 DOWNTO 0);
rd_indexD : OUT std_logic_vector(5 DOWNTO 0);
rs_index : IN std_logic_vector(5 DOWNTO 0);
rt_index : IN std_logic_vector(5 DOWNTO 0);
pc_source : IN pc_source_type;
mem_source : IN mem_source_type;
a_source : IN a_source_type;
b_source : IN b_source_type;
c_source : IN c_source_type;
c_bus : IN std_logic_vector(31 DOWNTO 0);
pause_any : IN std_logic;
pause_pipeline : OUT std_logic
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT mlite_cpu
GENERIC(
memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2
); --2 or 3
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
intr_in : IN std_logic;
address_next : OUT std_logic_vector(31 DOWNTO 2); --for synch ram
byte_we_next : OUT std_logic_vector(3 DOWNTO 0);
address : OUT std_logic_vector(31 DOWNTO 2);
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_w : OUT std_logic_vector(31 DOWNTO 0);
data_r : IN std_logic_vector(31 DOWNTO 0);
mem_pause : IN std_logic
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT cache
GENERIC(
memory_type : string := "DEFAULT"
);
PORT(
clk : IN std_logic;
reset : IN std_logic;
address_next : IN std_logic_vector(31 DOWNTO 2);
byte_we_next : IN std_logic_vector(3 DOWNTO 0);
cpu_address : IN std_logic_vector(31 DOWNTO 2);
mem_busy : IN std_logic;
cache_access : OUT std_logic; --access 4KB cache
cache_checking : OUT std_logic; --checking if cache hit
cache_miss : OUT std_logic
); --cache miss
END COMPONENT; --cache
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT ram
GENERIC(
memory_type : string := "DEFAULT";
plasma_code : string
);
PORT(
clk : IN std_logic;
enable : IN std_logic;
write_byte_enable : IN std_logic_vector(3 DOWNTO 0);
address : IN std_logic_vector(31 DOWNTO 2);
data_write : IN std_logic_vector(31 DOWNTO 0);
data_read : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT; --ram
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT uart
GENERIC(log_file : string := "UNUSED");
PORT(clk : IN std_logic;
reset : IN std_logic;
enable_read : IN std_logic;
enable_write : IN std_logic;
data_in : IN std_logic_vector(7 DOWNTO 0);
data_out : OUT std_logic_vector(7 DOWNTO 0);
uart_read : IN std_logic;
uart_write : OUT std_logic;
busy_write : OUT std_logic;
data_avail : OUT std_logic
);
END COMPONENT; --uart
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT eth_dma
PORT(clk : IN std_logic; --25 MHz
reset : IN std_logic;
enable_eth : IN std_logic;
select_eth : IN std_logic;
rec_isr : OUT std_logic;
send_isr : OUT std_logic;
address : OUT std_logic_vector(31 DOWNTO 2); --to DDR
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_write : OUT std_logic_vector(31 DOWNTO 0);
data_read : IN std_logic_vector(31 DOWNTO 0);
pause_in : IN std_logic;
mem_address : IN std_logic_vector(31 DOWNTO 2); --from CPU
mem_byte_we : IN std_logic_vector(3 DOWNTO 0);
data_w : IN std_logic_vector(31 DOWNTO 0);
pause_out : OUT std_logic;
E_RX_CLK : IN std_logic; --2.5 MHz receive
E_RX_DV : IN std_logic; --data valid
E_RXD : IN std_logic_vector(3 DOWNTO 0); --receive nibble
E_TX_CLK : IN std_logic; --2.5 MHz transmit
E_TX_EN : OUT std_logic; --transmit enable
E_TXD : OUT std_logic_vector(3 DOWNTO 0)
); --transmit nibble
END COMPONENT; --eth_dma
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT plasma
GENERIC(
memory_type : string := "XILINX_16X"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
eUart : std_logic := '0';
use_cache : std_logic := '0';
plasma_code : string
);
PORT(
clk : IN std_logic;
reset : IN std_logic;
uart_write : OUT std_logic;
uart_read : IN std_logic;
address : OUT std_logic_vector(31 DOWNTO 2);
byte_we : OUT std_logic_vector(3 DOWNTO 0);
data_write : OUT std_logic_vector(31 DOWNTO 0);
data_read : IN std_logic_vector(31 DOWNTO 0);
mem_pause_in : IN std_logic;
no_ddr_start : OUT std_logic;
no_ddr_stop : OUT std_logic;
fifo_1_out_data : IN std_logic_vector (31 DOWNTO 0);
fifo_1_read_en : OUT std_logic;
fifo_1_empty : IN std_logic;
fifo_2_in_data : OUT std_logic_vector (31 DOWNTO 0);
fifo_1_write_en : OUT std_logic;
fifo_2_full : IN std_logic;
fifo_1_full : IN std_logic;
fifo_1_valid : IN std_logic;
fifo_2_empty : IN std_logic;
fifo_2_valid : IN std_logic;
fifo_1_compteur : IN std_logic_vector (31 DOWNTO 0);
fifo_2_compteur : IN std_logic_vector (31 DOWNTO 0);
data_enable :out std_logic;
ADDR : out std_logic_vector(16 downto 0);
data_out : out std_logic_vector(11 downto 0);
gpio0_out : OUT std_logic_vector(31 DOWNTO 0);
gpioA_in : IN std_logic_vector(31 DOWNTO 0)
);
END COMPONENT; --plasma
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT ddr_ctrl
PORT(clk : IN std_logic;
clk_2x : IN std_logic;
reset_in : IN std_logic;
address : IN std_logic_vector(25 DOWNTO 2);
byte_we : IN std_logic_vector(3 DOWNTO 0);
data_w : IN std_logic_vector(31 DOWNTO 0);
data_r : OUT std_logic_vector(31 DOWNTO 0);
active : IN std_logic;
no_start : IN std_logic;
no_stop : IN std_logic;
pause : OUT std_logic;
SD_CK_P : OUT std_logic; --clock_positive
SD_CK_N : OUT std_logic; --clock_negative
SD_CKE : OUT std_logic; --clock_enable
SD_BA : OUT std_logic_vector(1 DOWNTO 0); --bank_address
SD_A : OUT std_logic_vector(12 DOWNTO 0); --address(row or col)
SD_CS : OUT std_logic; --chip_select
SD_RAS : OUT std_logic; --row_address_strobe
SD_CAS : OUT std_logic; --column_address_strobe
SD_WE : OUT std_logic; --write_enable
SD_DQ : INOUT std_logic_vector(15 DOWNTO 0); --data
SD_UDM : OUT std_logic; --upper_byte_enable
SD_UDQS : INOUT std_logic; --upper_data_strobe
SD_LDM : OUT std_logic; --low_byte_enable
SD_LDQS : INOUT std_logic
); --low_data_strobe
END COMPONENT; --ddr
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT disassembler
PORT(
clk : IN std_logic;
reset : IN std_logic;
pause : IN std_logic;
opcode : IN std_logic_vector(31 DOWNTO 0);
pc_addr : IN std_logic_vector(31 DOWNTO 2)
);
END COMPONENT;
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT comb_alu_1
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
a_in : IN std_logic_vector(31 DOWNTO 0);
b_in : IN std_logic_vector(31 DOWNTO 0);
alu_function : IN std_logic_vector(5 DOWNTO 0);
c_alu : OUT std_logic_vector(31 DOWNTO 0)
);
END COMPONENT; --comb_alu_1
---------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------
COMPONENT sequ_alu_1
PORT(
clk : IN std_logic;
reset_in : IN std_logic;
a_in : IN std_logic_vector(31 DOWNTO 0);
b_in : IN std_logic_vector(31 DOWNTO 0);
alu_function : IN std_logic_vector(5 DOWNTO 0);
c_alu : OUT std_logic_vector(31 DOWNTO 0);
pause_out : OUT std_logic
);
END COMPONENT; --sequ_alu_1
---------------------------------------------------------------------------------------
END; --package mlite_pack
PACKAGE BODY mlite_pack IS
FUNCTION bv_adder(a : IN std_logic_vector;
b : IN std_logic_vector;
do_add : IN std_logic) RETURN std_logic_vector IS
VARIABLE carry_in : std_logic;
VARIABLE bb : std_logic_vector(a'length-1 DOWNTO 0);
VARIABLE result : std_logic_vector(a'length DOWNTO 0);
BEGIN
IF do_add = '1' THEN
bb := b;
carry_in := '0';
ELSE
bb := NOT b;
carry_in := '1';
END IF;
FOR index IN 0 TO a'length-1 LOOP
result(index) := a(index) XOR bb(index) XOR carry_in;
carry_in := (carry_in AND (a(index) OR bb(index))) OR
(a(index) AND bb(index));
END LOOP;
result(a'length) := carry_in XNOR do_add;
RETURN result;
END; --function
FUNCTION bv_negate(a : IN std_logic_vector) RETURN std_logic_vector IS
VARIABLE carry_in : std_logic;
VARIABLE not_a : std_logic_vector(a'length-1 DOWNTO 0);
VARIABLE result : std_logic_vector(a'length-1 DOWNTO 0);
BEGIN
not_a := NOT a;
carry_in := '1';
FOR index IN a'reverse_range LOOP
result(index) := not_a(index) XOR carry_in;
carry_in := carry_in AND not_a(index);
END LOOP;
RETURN result;
END; --function
FUNCTION bv_increment(a : IN std_logic_vector(31 DOWNTO 2)
) RETURN std_logic_vector IS
VARIABLE carry_in : std_logic;
VARIABLE result : std_logic_vector(31 DOWNTO 2);
BEGIN
carry_in := '1';
FOR index IN 2 TO 31 LOOP
result(index) := a(index) XOR carry_in;
carry_in := a(index) AND carry_in;
END LOOP;
RETURN result;
END; --function
FUNCTION bv_inc(a : IN std_logic_vector
) RETURN std_logic_vector IS
VARIABLE carry_in : std_logic;
VARIABLE result : std_logic_vector(a'length-1 DOWNTO 0);
BEGIN
carry_in := '1';
FOR index IN 0 TO a'length-1 LOOP
result(index) := a(index) XOR carry_in;
carry_in := a(index) AND carry_in;
END LOOP;
RETURN result;
END; --function
END; --package body
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_counter is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "0";
USE_SSET : string := "false";
USE_SLOAD : string := "false";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 256;
USE_CNT_ENA : string := "false";
WIDTH : natural := 8;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
user_aclr : in std_logic;
clock : in std_logic;
q : out std_logic_vector(width-1 downto 0);
direction : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aset : in std_logic;
cout : out std_logic;
sset : in std_logic;
aclr : in std_logic;
cnt_ena : in std_logic;
cin : in std_logic;
ena : in std_logic;
aload : in std_logic;
sload : in std_logic
);
end entity alt_dspbuilder_counter;
architecture rtl of alt_dspbuilder_counter is
component alt_dspbuilder_counter_GNW5IG44CT is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SSET : string := "false";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := -1;
USE_CNT_ENA : string := "true";
WIDTH : natural := 3;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
q : out std_logic_vector(3-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_counter_GNW5IG44CT;
begin
alt_dspbuilder_counter_GNW5IG44CT_0: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SSET = "false") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNW5IG44CT_0: alt_dspbuilder_counter_GNW5IG44CT
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", NDIRECTION => 1, SVALUE => "1", USE_SSET => "false", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => -1, USE_CNT_ENA => "true", WIDTH => 3, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
assert not (((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SSET = "false") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")))
report "Please run generate again" severity error;
end architecture rtl;
|
-- This file is not intended for synthesis, is is present so that simulators
-- see a complete view of the system.
-- You may use the entity declaration from this file as the basis for a
-- component declaration in a VHDL file instantiating this entity.
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;
entity alt_dspbuilder_counter is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "0";
USE_SSET : string := "false";
USE_SLOAD : string := "false";
USE_SCLR : string := "false";
USE_COUT : string := "false";
MODULUS : integer := 256;
USE_CNT_ENA : string := "false";
WIDTH : natural := 8;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
user_aclr : in std_logic;
clock : in std_logic;
q : out std_logic_vector(width-1 downto 0);
direction : in std_logic;
sclr : in std_logic;
data : in std_logic_vector(width-1 downto 0);
aset : in std_logic;
cout : out std_logic;
sset : in std_logic;
aclr : in std_logic;
cnt_ena : in std_logic;
cin : in std_logic;
ena : in std_logic;
aload : in std_logic;
sload : in std_logic
);
end entity alt_dspbuilder_counter;
architecture rtl of alt_dspbuilder_counter is
component alt_dspbuilder_counter_GNW5IG44CT is
generic (
USE_USR_ACLR : string := "false";
USE_ENA : string := "false";
USE_CIN : string := "false";
NDIRECTION : natural := 1;
SVALUE : string := "1";
USE_SSET : string := "false";
USE_SLOAD : string := "false";
USE_SCLR : string := "true";
USE_COUT : string := "false";
MODULUS : integer := -1;
USE_CNT_ENA : string := "true";
WIDTH : natural := 3;
USE_ASET : string := "false";
USE_ALOAD : string := "false";
AVALUE : string := "0"
);
port (
aclr : in std_logic;
clock : in std_logic;
cnt_ena : in std_logic;
cout : out std_logic;
q : out std_logic_vector(3-1 downto 0);
sclr : in std_logic
);
end component alt_dspbuilder_counter_GNW5IG44CT;
begin
alt_dspbuilder_counter_GNW5IG44CT_0: if ((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SSET = "false") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")) generate
inst_alt_dspbuilder_counter_GNW5IG44CT_0: alt_dspbuilder_counter_GNW5IG44CT
generic map(USE_USR_ACLR => "false", USE_ENA => "false", USE_CIN => "false", NDIRECTION => 1, SVALUE => "1", USE_SSET => "false", USE_SLOAD => "false", USE_SCLR => "true", USE_COUT => "false", MODULUS => -1, USE_CNT_ENA => "true", WIDTH => 3, USE_ASET => "false", USE_ALOAD => "false", AVALUE => "0")
port map(aclr => aclr, clock => clock, cnt_ena => cnt_ena, cout => cout, q => q, sclr => sclr);
end generate;
assert not (((USE_USR_ACLR = "false") and (USE_ENA = "false") and (USE_CIN = "false") and (NDIRECTION = 1) and (SVALUE = "1") and (USE_SSET = "false") and (USE_SLOAD = "false") and (USE_SCLR = "true") and (USE_COUT = "false") and (MODULUS = -1) and (USE_CNT_ENA = "true") and (WIDTH = 3) and (USE_ASET = "false") and (USE_ALOAD = "false") and (AVALUE = "0")))
report "Please run generate again" severity error;
end architecture rtl;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.RxTstFIFO2K_pkg.ALL;
ENTITY RxTstFIFO2K_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF RxTstFIFO2K_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:RxTstFIFO2K_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
--------------------------------------------------------------------------------
--
-- FIFO Generator Core Demo Testbench
--
--------------------------------------------------------------------------------
--
-- (c) Copyright 2009 - 2010 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--------------------------------------------------------------------------------
--
-- Filename: RxTstFIFO2K_dverif.vhd
--
-- Description:
-- Used for FIFO read interface stimulus generation and data checking
--
--------------------------------------------------------------------------------
-- Library Declarations
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE IEEE.std_logic_arith.all;
USE IEEE.std_logic_misc.all;
LIBRARY work;
USE work.RxTstFIFO2K_pkg.ALL;
ENTITY RxTstFIFO2K_dverif IS
GENERIC(
C_DIN_WIDTH : INTEGER := 0;
C_DOUT_WIDTH : INTEGER := 0;
C_USE_EMBEDDED_REG : INTEGER := 0;
C_CH_TYPE : INTEGER := 0;
TB_SEED : INTEGER := 2
);
PORT(
RESET : IN STD_LOGIC;
RD_CLK : IN STD_LOGIC;
PRC_RD_EN : IN STD_LOGIC;
EMPTY : IN STD_LOGIC;
DATA_OUT : IN STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0);
RD_EN : OUT STD_LOGIC;
DOUT_CHK : OUT STD_LOGIC
);
END ENTITY;
ARCHITECTURE fg_dv_arch OF RxTstFIFO2K_dverif IS
CONSTANT C_DATA_WIDTH : INTEGER := if_then_else(C_DIN_WIDTH > C_DOUT_WIDTH,C_DIN_WIDTH,C_DOUT_WIDTH);
CONSTANT EXTRA_WIDTH : INTEGER := if_then_else(C_CH_TYPE = 2,1,0);
CONSTANT LOOP_COUNT : INTEGER := divroundup(C_DATA_WIDTH+EXTRA_WIDTH,8);
SIGNAL expected_dout : STD_LOGIC_VECTOR(C_DOUT_WIDTH-1 DOWNTO 0) := (OTHERS => '0');
SIGNAL data_chk : STD_LOGIC := '1';
SIGNAL rand_num : STD_LOGIC_VECTOR(8*LOOP_COUNT-1 downto 0);
SIGNAL rd_en_i : STD_LOGIC := '0';
SIGNAL pr_r_en : STD_LOGIC := '0';
SIGNAL rd_en_d1 : STD_LOGIC := '1';
BEGIN
DOUT_CHK <= data_chk;
RD_EN <= rd_en_i;
rd_en_i <= PRC_RD_EN;
rd_en_d1 <= '1';
data_fifo_chk:IF(C_CH_TYPE /=2) GENERATE
-------------------------------------------------------
-- Expected data generation and checking for data_fifo
-------------------------------------------------------
pr_r_en <= rd_en_i AND NOT EMPTY AND rd_en_d1;
expected_dout <= rand_num(C_DOUT_WIDTH-1 DOWNTO 0);
gen_num:FOR N IN LOOP_COUNT-1 DOWNTO 0 GENERATE
rd_gen_inst2:RxTstFIFO2K_rng
GENERIC MAP(
WIDTH => 8,
SEED => TB_SEED+N
)
PORT MAP(
CLK => RD_CLK,
RESET => RESET,
RANDOM_NUM => rand_num(8*(N+1)-1 downto 8*N),
ENABLE => pr_r_en
);
END GENERATE;
PROCESS (RD_CLK,RESET)
BEGIN
IF(RESET = '1') THEN
data_chk <= '0';
ELSIF (RD_CLK'event AND RD_CLK='1') THEN
IF(EMPTY = '0') THEN
IF(DATA_OUT = expected_dout) THEN
data_chk <= '0';
ELSE
data_chk <= '1';
END IF;
END IF;
END IF;
END PROCESS;
END GENERATE data_fifo_chk;
END ARCHITECTURE;
|
-- ipif_reg_logic.vhd
-- Jan Viktorin <[email protected]>
-- Copyright (C) 2011, 2012 Jan Viktorin
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use work.utils_pkg.all;
entity ipif_reg_logic is
generic (
REG_DWIDTH : integer := 32;
IPIF_DWIDTH : integer := 32;
IPIF_MODE : integer := IPIF_RO
);
port (
CLK : in std_logic;
RST : in std_logic;
---
-- IPIF access to the register
---
IP2Bus_Data : out std_logic_vector(IPIF_DWIDTH - 1 downto 0);
IP2Bus_WrAck : out std_logic;
IP2Bus_RdAck : out std_logic;
IP2Bus_Error : out std_logic;
Bus2IP_Data : in std_logic_vector(IPIF_DWIDTH - 1 downto 0);
Bus2IP_BE : in std_logic_vector(IPIF_DWIDTH / 8 - 1 downto 0);
Bus2IP_RNW : in std_logic;
Bus2IP_CS : in std_logic;
---
-- IP access to the register
---
REG_DO : in std_logic_vector(REG_DWIDTH - 1 downto 0);
REG_BE : out std_logic_vector(width_of_be(REG_DWIDTH) - 1 downto 0);
REG_WE : out std_logic;
REG_DI : out std_logic_vector(REG_DWIDTH - 1 downto 0)
);
end entity;
architecture full of ipif_reg_logic is
constant IPIF_WRITABLE : boolean := IPIF_MODE = IPIF_WO or IPIF_MODE = IPIF_RW;
constant IPIF_READABLE : boolean := IPIF_MODE = IPIF_RO or IPIF_MODE = IPIF_RW;
signal ipif_we : std_logic;
signal ipif_re : std_logic;
signal ipif_sel : std_logic;
signal ipif_error : std_logic;
signal ipif_di : std_logic_vector(REG_DWIDTH - 1 downto 0);
signal ipif_do : std_logic_vector(IPIF_DWIDTH - 1 downto 0);
begin
assert REG_DWIDTH > 0 and REG_DWIDTH <= IPIF_DWIDTH
report "Invalid register width: " & integer'image(REG_DWIDTH)
severity failure;
-----------------------
gen_writable: if IPIF_WRITABLE
generate
REG_WE <= ipif_we;
REG_DI <= ipif_di;
REG_BE <= Bus2IP_BE(REG_BE'range);
end generate;
gen_not_writable: if not IPIF_WRITABLE
generate
REG_WE <= '0';
REG_DI <= (others => 'X');
REG_BE <= (others => 'X');
end generate;
-----------------------
ipif_sel <= Bus2IP_CS and not RST;
ipif_we <= ipif_sel and not Bus2IP_RNW;
ipif_re <= ipif_sel and Bus2IP_RNW;
ipif_di <= Bus2IP_Data(REG_DWIDTH - 1 downto 0);
-----------------------
gen_assign_direct: if REG_DO'length = ipif_do'length
generate
ipif_do <= REG_DO;
end generate;
gen_assign_padding: if REG_DO'length < ipif_do'length
generate
ipif_do(ipif_do'length - 1 downto REG_DO'length) <= (others => '0');
ipif_do(REG_DO'range) <= REG_DO;
end generate;
IP2Bus_Data <= ipif_do when IPIF_READABLE else (others => '1');
ipif_error <= '1' when not IPIF_WRITABLE and ipif_we = '1' else
'1' when not IPIF_READABLE and ipif_re = '1' else
'0';
IP2Bus_WrAck <= ipif_we;
IP2Bus_RdAck <= ipif_re;
IP2Bus_Error <= ipif_error;
end architecture;
|
-- NetUP Universal Dual DVB-CI FPGA firmware
-- http://www.netup.tv
--
-- Copyright (c) 2014 NetUP Inc, AVB Labs
-- License: GPLv3
-- altera vhdl_input_version vhdl_2008
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity dvb_ts_sync is
port (
-- transport stream input port
ts_clk : in std_logic;
ts_strt : in std_logic;
ts_dval : in std_logic;
ts_data : in std_logic_vector(7 downto 0);
-- data output port (system clock domain)
rst : in std_logic;
clk : in std_logic;
--
strt : out std_logic;
data : out std_logic_vector(7 downto 0);
dval : out std_logic
);
end entity;
architecture rtl of dvb_ts_sync is
signal ts_rst_meta : std_logic;
signal ts_rst_n : std_logic;
signal src_latch : std_logic_vector(ts_data'left + 2 downto 0);
signal src_hold_0 : std_logic_vector(ts_data'left + 1 downto 0);
signal src_hold_1 : std_logic_vector(ts_data'left + 1 downto 0);
signal src_hold_2 : std_logic_vector(ts_data'left + 1 downto 0);
signal src_hold_3 : std_logic_vector(ts_data'left + 1 downto 0);
signal src_ptr : std_logic_vector(1 downto 0);
signal src_ptr_meta : std_logic_vector(1 downto 0);
signal src_ptr_sync : std_logic_vector(1 downto 0);
signal dst_ptr : std_logic_vector(1 downto 0);
begin
process (rst, ts_rst_n, ts_clk)
begin
if rising_edge(ts_clk) then
ts_rst_meta <= '1';
ts_rst_n <= ts_rst_meta;
--
src_latch <= ts_dval & ts_strt & ts_data;
if src_latch(src_latch'left) then
src_ptr(0) <= not src_ptr(1);
src_ptr(1) <= src_ptr(0);
if src_ptr = "00" then
src_hold_0 <= src_latch(src_latch'left - 1 downto 0);
end if;
if src_ptr = "01" then
src_hold_1 <= src_latch(src_latch'left - 1 downto 0);
end if;
if src_ptr = "11" then
src_hold_2 <= src_latch(src_latch'left - 1 downto 0);
end if;
if src_ptr = "10" then
src_hold_3 <= src_latch(src_latch'left - 1 downto 0);
end if;
end if;
end if;
if rst then
ts_rst_meta <= '0';
ts_rst_n <= '0';
end if;
if not ts_rst_n then
src_latch <= (others => '0');
src_ptr <= (others => '0');
src_hold_0 <= (others => '0');
src_hold_1 <= (others => '0');
src_hold_2 <= (others => '0');
src_hold_3 <= (others => '0');
end if;
end process;
process (rst, clk)
variable fifo_not_empty : std_logic;
begin
if rising_edge(clk) then
src_ptr_meta <= src_ptr;
src_ptr_sync <= src_ptr_meta;
--
fifo_not_empty := (src_ptr_sync(1) xor dst_ptr(1)) or (src_ptr_sync(0) xor dst_ptr(0));
if fifo_not_empty then
dst_ptr(0) <= not dst_ptr(1);
dst_ptr(1) <= dst_ptr(0);
case dst_ptr is
when "00" =>
strt <= src_hold_0(src_hold_0'left);
data <= src_hold_0(src_hold_0'left - 1 downto 0);
when "01" =>
strt <= src_hold_1(src_hold_1'left);
data <= src_hold_1(src_hold_1'left - 1 downto 0);
when "11" =>
strt <= src_hold_2(src_hold_2'left);
data <= src_hold_2(src_hold_2'left - 1 downto 0);
when others =>
strt <= src_hold_3(src_hold_3'left);
data <= src_hold_3(src_hold_3'left - 1 downto 0);
end case;
end if;
dval <= fifo_not_empty;
end if;
if rst then
src_ptr_meta <= (others => '0');
src_ptr_sync <= (others => '0');
dst_ptr <= (others => '0');
strt <= '0';
data <= (others => '0');
dval <= '0';
end if;
end process;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY flopr IS
PORT (d: IN std_logic_vector(31 DOWNTO 0);
clk, reset: IN std_logic;
q: OUT std_logic_vector(31 DOWNTO 0));
END flopr;
ARCHITECTURE flopr_est OF flopr IS
BEGIN
PROCESS (clk, reset)
BEGIN
IF (reset='1') THEN
q <= x"00000000";
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END flopr_est;
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY flopr IS
PORT (d: IN std_logic_vector(31 DOWNTO 0);
clk, reset: IN std_logic;
q: OUT std_logic_vector(31 DOWNTO 0));
END flopr;
ARCHITECTURE flopr_est OF flopr IS
BEGIN
PROCESS (clk, reset)
BEGIN
IF (reset='1') THEN
q <= x"00000000";
ELSIF (clk'EVENT AND clk='1') THEN
q <= d;
END IF;
END PROCESS;
END flopr_est;
|
-----------------------------------------------------------------------------
-- LEON3 Demonstration design
-- Copyright (C) 2008 Jiri Gaisler, Jan Andersson, Aeroflex Gaisler
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.pci.all;
use gaisler.ddrpkg.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
fpga_cpu_reset_b : in std_ulogic;
user_clksys : in std_ulogic; -- 100 MHz main clock
sysace_fpga_clk : in std_ulogic; -- 33 MHz
-- Flash
flash_we_b : out std_ulogic;
flash_wait : in std_ulogic;
flash_reset_b : out std_ulogic;
flash_oe_b : out std_ulogic;
flash_d : inout std_logic_vector(15 downto 0);
flash_clk : out std_ulogic;
flash_ce_b : out std_ulogic;
flash_adv_b : out std_logic;
flash_a : out std_logic_vector(21 downto 0);
--pragma translate_off
-- For debug output module
sram_bw : out std_ulogic;
sim_d : inout std_logic_vector(31 downto 16);
iosn : out std_ulogic;
--pragma translate_on
-- DDR2 slot 1
dimm1_ddr2_we_b : out std_ulogic;
dimm1_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm1_ddr2_ras_b : out std_ulogic;
dimm1_ddr2_pll_clkin_p : out std_ulogic;
dimm1_ddr2_pll_clkin_n : out std_ulogic;
dimm1_ddr2_odt : out std_logic_vector(1 downto 0);
dimm1_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm1_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm1_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm1_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm1_ddr2_cas_b : out std_ulogic;
dimm1_ddr2_ba : out std_logic_vector(2 downto 0);
dimm1_ddr2_a : out std_logic_vector(13 downto 0);
-- DDR2 slot 0
dimm0_ddr2_we_b : out std_ulogic;
dimm0_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm0_ddr2_ras_b : out std_ulogic;
dimm0_ddr2_pll_clkin_p : out std_ulogic;
dimm0_ddr2_pll_clkin_n : out std_ulogic;
dimm0_ddr2_odt : out std_logic_vector(1 downto 0);
dimm0_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm0_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm0_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm0_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm0_ddr2_cas_b : out std_ulogic;
dimm0_ddr2_ba : out std_logic_vector(2 downto 0);
dimm0_ddr2_a : out std_logic_vector(13 downto 0);
dimm0_ddr2_reset_n : out std_ulogic;
-- Ethernet PHY
phy0_txer : out std_ulogic;
phy0_txd : out std_logic_vector(3 downto 0);
phy0_txctl_txen : out std_ulogic;
phy0_txclk : in std_ulogic;
phy0_rxer : in std_ulogic;
phy0_rxd : in std_logic_vector(3 downto 0);
phy0_rxctl_rxdv : in std_ulogic;
phy0_rxclk : in std_ulogic;
phy0_reset : out std_ulogic;
phy0_mdio : inout std_logic;
phy0_mdc : out std_ulogic;
-- phy0_int : in std_ulogic;
-- System ACE MPU
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_mpd : inout std_logic_vector(15 downto 0);
-- GPIO/Green LEDs
dbg_led : inout std_logic_vector(3 downto 0);
-- Red/Green LEDs
opb_bus_error : out std_ulogic;
plb_bus_error : out std_ulogic;
-- LCD
-- fpga_lcd_rw : out std_ulogic;
-- fpga_lcd_rs : out std_ulogic;
-- fpga_lcd_e : out std_ulogic;
-- fpga_lcd_db : out std_logic_vector(7 downto 0);
-- DVI
dvi_xclk_p : out std_ulogic;
dvi_xclk_n : out std_ulogic;
dvi_v : out std_ulogic;
dvi_reset_b : out std_ulogic;
dvi_h : out std_ulogic;
dvi_gpio1 : inout std_logic;
dvi_de : out std_ulogic;
dvi_d : out std_logic_vector(11 downto 0);
-- PCI
pci_p_trdy_b : inout std_logic;
pci_p_stop_b : inout std_logic;
pci_p_serr_b : inout std_logic;
pci_p_rst_b : inout std_logic;
pci_p_req_b : in std_logic_vector(0 to 4);
pci_p_perr_b : inout std_logic;
pci_p_par : inout std_logic;
pci_p_lock_b : inout std_logic;
pci_p_irdy_b : inout std_logic;
pci_p_intd_b : in std_logic;
pci_p_intc_b : in std_logic;
pci_p_intb_b : in std_logic;
pci_p_inta_b : in std_logic;
pci_p_gnt_b : out std_logic_vector(0 to 4);
pci_p_frame_b : inout std_logic;
pci_p_devsel_b : inout std_logic;
pci_p_clk5_r : out std_ulogic;
pci_p_clk5 : in std_ulogic;
pci_p_clk4_r : out std_ulogic;
pci_p_clk3_r : out std_ulogic;
pci_p_clk1_r : out std_ulogic;
pci_p_clk0_r : out std_ulogic;
pci_p_cbe_b : inout std_logic_vector(3 downto 0);
pci_p_ad : inout std_logic_vector(31 downto 0);
-- pci_fpga_idsel : in std_ulogic;
sbr_pwg_rsm_rstj : inout std_logic;
sbr_nmi_r : in std_ulogic;
sbr_intr_r : in std_ulogic;
sbr_ide_rst_b : inout std_logic;
-- IIC/SMBus and sideband signals
iic_sda_dvi : inout std_logic;
iic_scl_dvi : inout std_logic;
fpga_sda : inout std_logic;
fpga_scl : inout std_logic;
iic_therm_b : in std_ulogic;
iic_reset_b : out std_ulogic;
iic_irq_b : in std_ulogic;
iic_alert_b : in std_ulogic;
-- SPI
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic;
-- UARTs
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts_b : out std_ulogic;
uart1_cts_b : in std_ulogic;
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;
uart0_rts_b : out std_ulogic
-- uart0_cts_b : in std_ulogic
-- System monitor
-- test_mon_vrefp : in std_ulogic;
-- test_mon_vp0_p : in std_ulogic;
-- test_mon_vn0_n : in std_ulogic
-- test_mon_avdd : in std_ulogic
);
end;
architecture rtl of leon3mp is
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_PCI;
-- Set this constant to 1 to include an APB bridge with the Logan logic
-- analyzer attached to the PCI signals
constant CFG_LOGAN : integer := 0;
signal ddr0_clk_fb, ddr1_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal apbi, apbi1 : apb_slv_in_type;
signal apbo, apbo1 : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal clkm, clkm2x, rstn, rstraw, flashclkl : std_ulogic;
signal clkddr, clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal dbgi : l3_debug_in_vector(0 to NCPU-1);
signal dbgo : l3_debug_out_vector(0 to NCPU-1);
signal dsui : dsu_in_type;
signal dsuo : dsu_out_type;
signal opb_bus_errorl, plb_bus_errorl : std_ulogic;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock0, lock1, lclk, clkml0, clkml1 : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
-- DDR clock is 200 MHz clock unless CFG_DDR2SP_NOSYNC is set. If that config
-- option is set the DDR clock is 2x CPU clock.
constant DDR_FREQ : integer :=
BOARD_FREQ_200 - (BOARD_FREQ_200 - 2*CPU_FREQ)*CFG_DDR2SP_NOSYNC;
constant IOAEN : integer := CFG_DDR2SP;
signal stati : ahbstat_in_type;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr1_clkv : std_logic_vector(2 downto 0);
signal ddr1_clkbv : std_logic_vector(2 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal pciclk, pci_clk, pci_clk_fb : std_ulogic;
signal pci_arb_gnt : std_logic_vector(0 to 7);
signal pci_arb_req : std_logic_vector(0 to 7);
signal pci_arb_reql : std_logic_vector(0 to 4);
signal pci_reql : std_ulogic;
signal pci_host, pci_66 : std_ulogic;
signal pci_intv : std_logic_vector(3 downto 0);
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal clkma, clkmb, clkmc : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal phy_init_done : std_ulogic;
-- Logan signals
signal signals : std_logic_vector(63*CFG_LOGAN downto 0);
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml0 : signal is true;
attribute syn_preserve of clkml0 : signal is true;
attribute syn_keep of clkml1 : signal is true;
attribute syn_preserve of clkml1 : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of phy_init_done : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute keep : boolean;
attribute keep of lock0 : signal is true;
attribute keep of lock1 : signal is true;
attribute keep of clkml0 : signal is true;
attribute keep of clkml1 : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_fpga_clk_pad : label is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, flashclkl);
sysace_fpga_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_fpga_clk, clkace);
pci_p_clk5_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (pci_p_clk5, pci_clk_fb);
pci_p_clk5_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk5_r, pci_clk);
pci_p_clk4_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk4_r, pci_clk);
pci_p_clk3_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk3_r, pci_clk);
pci_p_clk1_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk1_r, pci_clk);
pci_p_clk0_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk0_r, pci_clk);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 1,
1, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 1)
port map (lclk, pci_clk_fb, clkmc, open, clkm2x, flashclkl, pciclk, cgi, cgo,
open, open, clk_200);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
-- clkgen1 : clkgen -- Ethernet 1G PHY clock generator
-- generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
-- port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
-- cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
-- egtx_clk_pad : outpad generic map (tech => padtech)
-- port map (phy_gtx_clk, egtx_clk);
clkgen2 : clkgen -- PCI clock generator
generic map (CFG_FABTECH, 2, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), pci_clk, open, open, open, open, cgi3, cgo3);
cgi3.pllctrl <= "00"; cgi3.pllrst <= rstraw; cgi3.pllref <= '0';
iic_reset_b_pad : outpad generic map (tech => padtech)
port map (iic_reset_b, rstn);
resetn_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (fpga_cpu_reset_b, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock0 and lock1 and cgo.clklock and cgo3.clklock;
clk_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (user_clksys, lclk);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML510,
ioen => IOAEN, nahbm => maxahbm, nahbs => 11 + CFG_LOGAN)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON3 processor and DSU -----------------------------------------
----------------------------------------------------------------------
l3 : if CFG_LEON3 = 1 generate
cpu : for i in 0 to NCPU-1 generate
u0 : leon3s -- LEON3 processor
generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
0, CFG_MAC, pclow, CFG_NOTAG, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE,
CFG_TLB_REP, CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, NCPU-1,
CFG_DFIXED, CFG_SCAN, CFG_MMU_PAGE, CFG_BP)
port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
irqi(i), irqo(i), dbgi(i), dbgo(i));
end generate;
opb_bus_errorl <= not dbgo(0).error;
dsugen : if CFG_DSU = 1 generate
dsu0 : dsu3 -- LEON3 Debug Support Unit
generic map (hindex => 2, haddr => 16#D00#, hmask => 16#F00#,
ncpu => NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
dsui.enable <= '1';
dsui.break <= not gpioo.val(0); -- Position on on GPIO DIP switch
plb_bus_errorl <= dsuo.active;
end generate;
end generate;
nodsu : if CFG_DSU = 0 generate
dsuo.tstop <= '0'; dsuo.active <= '0'; plb_bus_errorl <= '0';
end generate;
opb_bus_error_pad : outpad generic map (tech => padtech)
port map (opb_bus_error, opb_bus_errorl);
plb_bus_error_pad : outpad generic map (tech => padtech)
port map (plb_bus_error, plb_bus_errorl);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
end generate;
nodcom : if CFG_AHB_UART = 0 generate
duo.txd <= '0'; duo.rtsn <= '1';
end generate;
dsurx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_txd, duo.txd);
-- dsucts_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
-- port map (uart0_cts_b, dui.ctsn);
dsurts_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rts_b, duo.rtsn);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
nomctrl: if CFG_MCTRL_LEON2 = 0 generate
memo.address <= (others => '0'); memo.romsn <= (others => '1');
memo.oen <= '1'; memo.wrn <= (others => '1');
memo.vbdrive <= (others => '1'); memo.writen <= '1';
end generate;
flash_reset_b_pad : outpad generic map (tech => padtech)
port map (flash_reset_b, rstn);
-- flash_wait_pad : inpad generic map (tech => padtech)
-- port map (flash_wait, );
flash_adv_b_pad : outpad generic map (tech => padtech)
port map (flash_adv_b, gnd(0));
flash_a_pads : outpadv generic map (width => 22, tech => padtech)
port map (flash_a, memo.address(22 downto 1));
flash_ce_b_pad : outpad generic map (tech => padtech)
port map (flash_ce_b, memo.romsn(0));
flash_oe_b_pad : outpad generic map (tech => padtech)
port map (flash_oe_b, memo.oen);
--pragma translate_off
rwen_pad : outpad generic map (tech => padtech)
port map (sram_bw, memo.wrn(3));
sim_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sim_d, memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
flash_we_b_pad : outpad generic map (tech => padtech)
port map (flash_we_b, memo.writen);
flash_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (flash_d, memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
dbg_led0_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dbg_led(3), phy_init_done);
clkm <= clkma; clkma <= clkmb; clkmb <= clkmc;
ddrsp0 : if (CFG_DDR2SP /= 0) generate
phy_init_done <= '1';
-- DDR clock selection
-- If the synchronization registers are removed in the DDR controller, we
-- assume that the user wants to run at 2x the system clock. Otherwise the
-- DDR clock is generated from the 200 MHz clock.
ddrclkselarb: if CFG_DDR2SP_NOSYNC = 0 generate
BUFGDDR : BUFG port map (I => clk_200, O => clkddr);
end generate;
ddrclksel2x: if CFG_DDR2SP_NOSYNC /= 0 generate
clkddr <= clkm2x;
end generate;
dimm0_ddr2_reset_n_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dimm0_ddr2_reset_n, rst);
-- Slot 0
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#e00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock0, clkml0, clkml0, ahbsi, ahbso(0),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
dimm0_ddr2_cke, dimm0_ddr2_s_b, dimm0_ddr2_we_b, dimm0_ddr2_ras_b,
dimm0_ddr2_cas_b, dimm0_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm0_ddr2_a,
dimm0_ddr2_ba(2 downto 0), dimm0_ddr2_dq(63 downto 32*(32/CFG_DDR2SP_DATAWIDTH)),
dimm0_ddr2_odt);
dimm0_ddr2_pll_clkin_p <= ddr0_clkv(0);
dimm0_ddr2_pll_clkin_n <= ddr0_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm0_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm0_ddr2_ba(2), gnd(0));
dimm0_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm0_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm0_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm0_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm0_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm0_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr032bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm0_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm0_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm0_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm0_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
-- Slot 1
ddrc1 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 1, haddr => 16#600#, hmask => 16#E00#, ioaddr => 2,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock1, clkml1, clkml1, ahbsi, ahbso(1),
ddr1_clkv, ddr1_clkbv, ddr1_clk_fb, ddr1_clk_fb,
dimm1_ddr2_cke, dimm1_ddr2_s_b, dimm1_ddr2_we_b, dimm1_ddr2_ras_b,
dimm1_ddr2_cas_b, dimm1_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm1_ddr2_a,
dimm1_ddr2_ba(2 downto 0), dimm1_ddr2_dq(63 downto 32*(32/ CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_odt);
dimm1_ddr2_pll_clkin_p <= ddr1_clkv(0);
dimm1_ddr2_pll_clkin_n <= ddr1_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm1_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm1_ddr2_ba(2), gnd(0));
dimm1_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm1_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm1_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm1_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm1_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm1_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr132bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm1_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm1_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm1_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm1_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
end generate;
-- noddr : if (CFG_DDR2SP = 0) generate lock0 <= '1'; lock1 <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 5,
haddr => 16#000#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo <= gracectrl_none;
end generate nograce;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_mpd_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_mpd, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 10, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(10));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 4, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(4), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua1: if CFG_UART1_ENABLE = 0 generate u1o.txd <= '0'; u1o.rtsn <= '1'; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts_b, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts_b, u1o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 14, paddr => 14,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(14), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 6, paddr => 6, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(6), dvi_i2ci, dvi_i2co);
end generate;
novga : if CFG_SVGA_ENABLE = 0 generate
apbo(14) <= apb_none; apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
dvi_d_pad : outpadv generic map (width => 12, tech => padtech)
port map (dvi_d, lcd_datal);
dvi_xclk_p_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_p, clkvga_p);
dvi_xclk_n_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_n, clkvga_n);
dvi_h_pad : outpad generic map (tech => padtech)
port map (dvi_h, lcd_hsyncl);
dvi_v_pad : outpad generic map (tech => padtech)
port map (dvi_v, lcd_vsyncl);
dvi_de_pad : outpad generic map (tech => padtech)
port map (dvi_de, lcd_del);
dvi_reset_b_pad : outpad generic map (tech => padtech)
port map (dvi_reset_b, rstn);
iic_scl_dvi_pad : iopad generic map (tech => padtech)
port map (iic_scl_dvi, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
iic_sda_dvi_pad : iopad generic map (tech => padtech)
port map (iic_sda_dvi, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate
gpioo.oen <= (others => '1'); gpioo.val <= (others => '0');
gpioo.dout <= (others => '1');
end generate;
dbg_led_pads : iopadvv generic map (tech => padtech, width => 3, level => cmos, voltage => x33v)
port map (dbg_led(2 downto 0), gpioo.dout(2 downto 0), gpioo.oen(2 downto 0),
gpioi.din(2 downto 0));
dvi_gpio_pad : iopad generic map (tech => padtech)
port map (dvi_gpio1, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
iic_therm_b_pad : inpad generic map (tech => padtech)
port map (iic_therm_b, gpioi.din(9));
iic_irq_b_pad : inpad generic map (tech => padtech)
port map (iic_irq_b, gpioi.din(10));
iic_alert_b_pad : inpad generic map (tech => padtech)
port map (iic_alert_b, gpioi.din(11));
sbr_pwg_rsm_rstj_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_pwg_rsm_rstj, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
sbr_nmi_r_pad : inpad generic map (tech => padtech)
port map (sbr_nmi_r, gpioi.din(6));
sbr_intr_r_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_intr_r, gpioi.din(5));
sbr_ide_rst_b_pad : iopad generic map (tech => padtech)
port map (sbr_ide_rst_b, gpioo.dout(8), gpioo.oen(8), gpioi.din(8));
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 3, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (fpga_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (fpga_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 4, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_txclk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_rxclk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy0_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy0_rxctl_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy0_rxer, ethi.rx_er);
-- Collision detect and carrier sense are not connected on the
-- board.
ethi.rx_col <= '0';
ethi.rx_crs <= ethi.rx_dv;
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy0_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (phy0_txctl_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy0_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy0_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy0_reset, rstn);
-- ethi.gtx_clk <= egtx_clk;
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
----------------------------------------------------------------------
pp : if CFG_PCI /= 0 generate
pci_mtf0 : if CFG_PCI = 2 generate -- master/target with fifo
pci0 : pci_mtf generic map (memtech => memtech,
hmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
fifodepth => log2(CFG_PCIDEPTH), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
hslvndx => 7, pindex => 4, paddr => 4, haddr => 16#800#, hmask => 16#c00#,
ioaddr => 16#400#, irq => 5, irqmask => 16#F#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbi, apbo(4),
ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH), ahbsi, ahbso(7));
end generate;
pci_mtf1 : if CFG_PCI = 3 generate -- master/target with fifo and DMA
dma : pcidma generic map (memtech => memtech,
dmstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+1,
dapbndx => 5, dapbaddr => 5, blength => blength,
mstndx => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
fifodepth => log2(fifodepth), device_id => CFG_PCIDID, vendor_id => CFG_PCIVID,
slvndx => 7, apbndx => 4, apbaddr => 4, haddr => 16#800#, hmask => 16#c00#,
ioaddr => 16#400#, irq => 5, irqmask => 16#F#, nsync => 2, hostrst => 1)
port map (rstn, clkm, pciclk, pcii, pcio, apbo(5),
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+1),
apbi, apbo(4), ahbmi, ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH),
ahbsi, ahbso(7));
end generate;
pci_trc0 : if CFG_PCITBUFEN /= 0 generate -- PCI trace buffer
pt0 : pcitrace generic map (depth => (6 + log2(CFG_PCITBUF/256)),
memtech => memtech, pindex => 12, paddr => 16#100#, pmask => 16#f00#)
port map (rstn, clkm, pciclk, pcii, apbi, apbo(12));
end generate;
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 13, paddr => 13, nb_agents => CFG_PCI_ARB_NGNT,
apb_en => CFG_PCI_ARBAPB)
port map (clk => pciclk, rst_n => pcii.rst, req_n => pci_arb_req, frame_n => pcii.frame,
gnt_n => pci_arb_gnt, pclk => clkm, prst_n => rstn, apbi => apbi, apbo => apbo(13));
-- Internal connection of req(2)
pci_arb_req(0 to 4) <= pci_arb_reql(0 to 1) & pci_reql & pci_arb_reql(3 to 4);
pci_arb_req(5 to 7) <= (others => '1');
end generate;
end generate;
nopcia0: if CFG_PCI = 0 or CFG_PCI_ARB = 0 generate
pci_arb_gnt <= (others => '1');
end generate;
nopci_mtf: if CFG_PCI /= 2 and CFG_PCI /= 3 generate
pcio <= pci_out_none;
end generate;
pgnt_pad : outpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_gnt_b, pci_arb_gnt(0 to 4));
preq_pad : inpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_req_b, pci_arb_reql);
pcipads0 : pcipads -- PCI pads
generic map (padtech => padtech, host => 2, int => 14, no66 => 1, onchipreqgnt => 1,
drivereset => 1, constidsel => 1)
port map (pci_rst => pci_p_rst_b, pci_gnt => pci_arb_gnt(2), pci_idsel => '0', --pci_fpga_idsel,
pci_lock => pci_p_lock_b, pci_ad => pci_p_ad, pci_cbe => pci_p_cbe_b,
pci_frame => pci_p_frame_b, pci_irdy => pci_p_irdy_b, pci_trdy => pci_p_trdy_b,
pci_devsel => pci_p_devsel_b, pci_stop => pci_p_stop_b, pci_perr => pci_p_perr_b,
pci_par => pci_p_par, pci_req => pci_reql, pci_serr => pci_p_serr_b,
pci_host => pci_host, pci_66 => pci_66, pcii => pcii, pcio => pcio, pci_int => pci_intv);
pci_intv <= pci_p_intd_b & pci_p_intc_b & pci_p_intb_b & pci_p_inta_b;
pci_host <= '0'; -- Always host
pci_66 <= '0';
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 8,
hirq => 1, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(8), sysmoni, sysmono);
sysmoni.convst <= '0';
sysmoni.convstclk <= '0';
sysmoni.vauxn <= (others => '0');
sysmoni.vauxp <= (others => '0');
-- sysmoni.vn <= test_mon_vn0_n;
-- sysmoni.vp <= test_mon_vp0_p;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 9, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(9));
end generate;
-----------------------------------------------------------------------
--- APB bridge with LOGAN --------------------------------------------
-----------------------------------------------------------------------
-- log: if CFG_LOGAN = 1 generate -- Logan is enabled by constant
-- -- declared above
-- apb0 : apbctrl -- AHB/APB bridge
-- generic map (hindex => 11, haddr => 16#F00#, nslaves => 1)
-- port map (rstn, clkm, ahbsi, ahbso(11), apbi1, apbo1);
-- logan0 : logan -- Logic analyzer
-- generic map (dbits => 64, depth => 4096, trigl => 2, usereg => 1,
-- usequal => 0, pindex => 0, paddr => 0, pmask => 16#F00#,
-- memtech => memtech)
-- port map (rstn, clkm, pciclk, apbi1, apbo1(0), signals);
-- signals(0) <= pcii.rst;
-- signals(1) <= pcii.gnt;
-- signals(2) <= pcii.idsel;
-- signals(34 downto 3) <= pcii.ad;
-- signals(38 downto 35) <= pcii.cbe;
-- signals(39) <= pcii.frame;
-- signals(40) <= pcii.irdy;
-- signals(41) <= pcii.trdy;
-- signals(42) <= pcii.devsel;
-- signals(43) <= pcii.stop;
-- signals(44) <= pcii.lock;
-- signals(45) <= pcii.perr;
-- signals(46) <= pcii.serr;
-- signals(47) <= pcii.par;
-- signals(48) <= pcii.host;
-- signals(49) <= pcii.pci66;
-- signals(53 downto 50) <= pcii.int;
-- signals(58 downto 54) <= pci_arb_gnt(0 to 4);
-- signals(63 downto 59) <= pci_arb_req(0 to 4);
-- end generate log;
nolog: if CFG_LOGAN /= 1 generate
signals <= (others => '0');
end generate nolog;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML510),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-- (c) Copyright 1995-2015 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- DO NOT MODIFY THIS FILE.
-- IP VLNV: digilentinc.com:ip:dvi2rgb:1.5
-- IP Revision: 1
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY design_1_dvi2rgb_0_1 IS
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst_n : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst_n : IN STD_LOGIC
);
END design_1_dvi2rgb_0_1;
ARCHITECTURE design_1_dvi2rgb_0_1_arch OF design_1_dvi2rgb_0_1 IS
ATTRIBUTE DowngradeIPIdentifiedWarnings : string;
ATTRIBUTE DowngradeIPIdentifiedWarnings OF design_1_dvi2rgb_0_1_arch: ARCHITECTURE IS "yes";
COMPONENT dvi2rgb IS
GENERIC (
kEmulateDDC : BOOLEAN;
kRstActiveHigh : BOOLEAN;
kClkRange : INTEGER;
kIDLY_TapValuePs : INTEGER;
kIDLY_TapWidth : INTEGER;
kAddBUFG : BOOLEAN
);
PORT (
TMDS_Clk_p : IN STD_LOGIC;
TMDS_Clk_n : IN STD_LOGIC;
TMDS_Data_p : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
TMDS_Data_n : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
RefClk : IN STD_LOGIC;
aRst : IN STD_LOGIC;
aRst_n : IN STD_LOGIC;
vid_pData : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
vid_pVDE : OUT STD_LOGIC;
vid_pHSync : OUT STD_LOGIC;
vid_pVSync : OUT STD_LOGIC;
PixelClk : OUT STD_LOGIC;
SerialClk : OUT STD_LOGIC;
aPixelClkLckd : OUT STD_LOGIC;
DDC_SDA_I : IN STD_LOGIC;
DDC_SDA_O : OUT STD_LOGIC;
DDC_SDA_T : OUT STD_LOGIC;
DDC_SCL_I : IN STD_LOGIC;
DDC_SCL_O : OUT STD_LOGIC;
DDC_SCL_T : OUT STD_LOGIC;
pRst : IN STD_LOGIC;
pRst_n : IN STD_LOGIC
);
END COMPONENT dvi2rgb;
ATTRIBUTE X_CORE_INFO : STRING;
ATTRIBUTE X_CORE_INFO OF design_1_dvi2rgb_0_1_arch: ARCHITECTURE IS "dvi2rgb,Vivado 2015.2";
ATTRIBUTE CHECK_LICENSE_TYPE : STRING;
ATTRIBUTE CHECK_LICENSE_TYPE OF design_1_dvi2rgb_0_1_arch : ARCHITECTURE IS "design_1_dvi2rgb_0_1,dvi2rgb,{}";
ATTRIBUTE X_INTERFACE_INFO : STRING;
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Clk_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS CLK_N";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_p: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_P";
ATTRIBUTE X_INTERFACE_INFO OF TMDS_Data_n: SIGNAL IS "digilentinc.com:interface:tmds:1.0 TMDS DATA_N";
ATTRIBUTE X_INTERFACE_INFO OF RefClk: SIGNAL IS "xilinx.com:signal:clock:1.0 RefClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF aRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 AsyncRst_n RST";
ATTRIBUTE X_INTERFACE_INFO OF vid_pData: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB DATA";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVDE: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB ACTIVE_VIDEO";
ATTRIBUTE X_INTERFACE_INFO OF vid_pHSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB HSYNC";
ATTRIBUTE X_INTERFACE_INFO OF vid_pVSync: SIGNAL IS "xilinx.com:interface:vid_io:1.0 RGB VSYNC";
ATTRIBUTE X_INTERFACE_INFO OF PixelClk: SIGNAL IS "xilinx.com:signal:clock:1.0 PixelClk CLK";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SDA_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SDA_T";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_I: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_I";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_O: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_O";
ATTRIBUTE X_INTERFACE_INFO OF DDC_SCL_T: SIGNAL IS "xilinx.com:interface:iic:1.0 DDC SCL_T";
ATTRIBUTE X_INTERFACE_INFO OF pRst_n: SIGNAL IS "xilinx.com:signal:reset:1.0 SyncRst_n RST";
BEGIN
U0 : dvi2rgb
GENERIC MAP (
kEmulateDDC => true,
kRstActiveHigh => false,
kClkRange => 2,
kIDLY_TapValuePs => 78,
kIDLY_TapWidth => 5,
kAddBUFG => true
)
PORT MAP (
TMDS_Clk_p => TMDS_Clk_p,
TMDS_Clk_n => TMDS_Clk_n,
TMDS_Data_p => TMDS_Data_p,
TMDS_Data_n => TMDS_Data_n,
RefClk => RefClk,
aRst => '0',
aRst_n => aRst_n,
vid_pData => vid_pData,
vid_pVDE => vid_pVDE,
vid_pHSync => vid_pHSync,
vid_pVSync => vid_pVSync,
PixelClk => PixelClk,
aPixelClkLckd => aPixelClkLckd,
DDC_SDA_I => DDC_SDA_I,
DDC_SDA_O => DDC_SDA_O,
DDC_SDA_T => DDC_SDA_T,
DDC_SCL_I => DDC_SCL_I,
DDC_SCL_O => DDC_SCL_O,
DDC_SCL_T => DDC_SCL_T,
pRst => '0',
pRst_n => pRst_n
);
END design_1_dvi2rgb_0_1_arch;
|
library verilog;
use verilog.vl_types.all;
entity ImaDRAM is
port(
data : in vl_logic_vector(7 downto 0);
inclock : in vl_logic;
outclock : in vl_logic;
rdaddress : in vl_logic_vector(13 downto 0);
wraddress : in vl_logic_vector(13 downto 0);
wren : in vl_logic;
q : out vl_logic_vector(7 downto 0)
);
end ImaDRAM;
|
--------------------------------------------------------------------------------
--
-- Title : cl_square.vhd
-- Design : VGA
-- Author : Kapitanov
-- Company : InSys
--
-- Version : 1.0
--------------------------------------------------------------------------------
--
-- Description : Game block for square 8x8
--
--
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
use work.ctrl_types_pkg.array8x8;
entity cl_square is
generic(
constant yend : std_logic_vector(4 downto 0):="11000";
constant ystart : std_logic_vector(4 downto 0):="10000";
constant xend : std_logic_vector(6 downto 0):="0011000";
constant xstart : std_logic_vector(6 downto 0):="0010000"
);
port(
-- system signals:
clk : in std_logic;
reset : in std_logic;
-- vga XoY coordinates:
show_disp : in array8x8;
--data_hide : in std_logic;
display : in std_logic;
x_char : in std_logic_vector(9 downto 0); -- X line: 0:79
y_char : in std_logic_vector(8 downto 0); -- Y line: 0:29
-- out color scheme:
rgb : out std_logic_vector(2 downto 0)
);
end cl_square;
architecture cl_square of cl_square is
signal data_rom : std_logic_vector(7 downto 0);
signal x_in : std_logic_vector(6 downto 0);
signal y_in : std_logic_vector(4 downto 0);
signal data : std_logic;
signal dataxy : std_logic;
signal x_rev : std_logic_vector(2 downto 0);
signal x_del : std_logic_vector(2 downto 0);
signal x_z : std_logic_vector(2 downto 0);
signal y_charz : std_logic_vector(3 downto 0);
constant color : std_logic_vector(2 downto 0):="001";
begin
y_charz <= y_char(3 downto 0) when rising_edge(clk);
x_in <= x_char(9 downto 3);
y_in <= y_char(8 downto 4);
pr_select3: process(clk, reset) is
begin
if reset = '0' then
dataxy <= '0';
elsif rising_edge(clk) then
if display = '0' then
dataxy <= '0';
else
if ((xstart <= x_in) and (x_in < xend)) then
if ((ystart <= y_in) and (y_in < yend)) then
dataxy <= not show_disp(conv_integer(x_in(2 downto 0)))(conv_integer(y_in(2 downto 0)));
else
dataxy <= '0';
end if;
else
dataxy <= '0';
end if;
end if;
end if;
end process;
pr_new_box: process(clk, reset)
begin
if reset = '0' then
data_rom <= x"00";
elsif rising_edge(clk) then
if (dataxy = '1') then
case y_charz(3 downto 0) is
when x"0" => data_rom <= x"FE";
when x"1" => data_rom <= x"FE";
when x"2" => data_rom <= x"FE";
when x"3" => data_rom <= x"FE";
when x"4" => data_rom <= x"FE";
when x"5" => data_rom <= x"FE";
when x"6" => data_rom <= x"FE";
when x"7" => data_rom <= x"FE";
when x"8" => data_rom <= x"FE";
when x"9" => data_rom <= x"FE";
when x"A" => data_rom <= x"FE";
when x"B" => data_rom <= x"FE";
when x"C" => data_rom <= x"FE";
when x"D" => data_rom <= x"FE";
when x"E" => data_rom <= x"FE";
when others => data_rom <= x"00";
end case;
else
data_rom <= x"00";
end if;
end if;
end process;
g_rev: for ii in 0 to 2 generate
begin
x_rev(ii) <= not x_char(ii) when rising_edge(clk);
end generate;
x_del <= x_rev when rising_edge(clk);
x_z <= x_del when rising_edge(clk);
pr_sw_sel: process(clk, reset) is
begin
if reset = '0' then
data <= '0';
elsif rising_edge(clk) then
data <= data_rom(to_integer(unsigned(x_z)));
end if;
end process;
g_rgb: for ii in 0 to 2 generate
begin
rgb(ii) <= data and color(ii);
end generate;
end cl_square; |
-- -------------------------------------------------------------
--
-- Generated Configuration for inst_shadow_ok_3_e
--
-- Generated
-- by: wig
-- on: Tue Nov 21 12:18:38 2006
-- cmd: /cygdrive/h/work/eclipse/MIX/mix_0.pl ../macro.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: inst_shadow_ok_3_e-c.vhd,v 1.1 2006/11/22 10:40:10 wig Exp $
-- $Date: 2006/11/22 10:40:10 $
-- $Log: inst_shadow_ok_3_e-c.vhd,v $
-- Revision 1.1 2006/11/22 10:40:10 wig
-- Detect missing directories and flag that as error.
--
--
-- Based on Mix Entity Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.99 2006/11/02 15:37:48 wig Exp
--
-- Generator: mix_0.pl Version: Revision: 1.47 , [email protected]
-- (C) 2003,2005 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/conf
--
-- Start of Generated Configuration inst_shadow_ok_3_rtl_conf / inst_shadow_ok_3_e
--
configuration inst_shadow_ok_3_rtl_conf of inst_shadow_ok_3_e is
for rtl
-- Generated Configuration
end for;
end inst_shadow_ok_3_rtl_conf;
--
-- End of Generated Configuration inst_shadow_ok_3_rtl_conf
--
--
--!End of Configuration/ies
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package packetprocessor_types is
type tup2_1 is record
tup2_1_sel0 : boolean;
tup2_1_sel1 : unsigned(7 downto 0);
end record;
type tup3 is record
tup3_sel0 : std_logic_vector(8 downto 0);
tup3_sel1 : boolean;
tup3_sel2 : boolean;
end record;
type array_of_unsigned_8 is array (integer range <>) of unsigned(7 downto 0);
type tup4 is record
tup4_sel0 : unsigned(10 downto 0);
tup4_sel1 : boolean;
tup4_sel2 : boolean;
tup4_sel3 : std_logic_vector(19 downto 0);
end record;
type tup2 is record
tup2_sel0 : std_logic_vector(11 downto 0);
tup2_sel1 : boolean;
end record;
type tup2_0 is record
tup2_0_sel0 : unsigned(10 downto 0);
tup2_0_sel1 : unsigned(7 downto 0);
end record;
function toSLV (slv : in std_logic_vector) return std_logic_vector;
function toSLV (s : in signed) return std_logic_vector;
function toSLV (u : in unsigned) return std_logic_vector;
function toSLV (b : in boolean) return std_logic_vector;
function fromSLV (sl : in std_logic_vector) return boolean;
function tagToEnum (s : in signed) return boolean;
function dataToTag (b : in boolean) return signed;
function toSLV (p : packetprocessor_types.tup2_1) return std_logic_vector;
function toSLV (p : packetprocessor_types.tup3) return std_logic_vector;
function toSLV (value : packetprocessor_types.array_of_unsigned_8) return std_logic_vector;
function toSLV (p : packetprocessor_types.tup4) return std_logic_vector;
function toSLV (p : packetprocessor_types.tup2) return std_logic_vector;
function toSLV (p : packetprocessor_types.tup2_0) return std_logic_vector;
end;
package body packetprocessor_types is
function toSLV (slv : in std_logic_vector) return std_logic_vector is
begin
return slv;
end;
function toSLV (s : in signed) return std_logic_vector is
begin
return std_logic_vector(s);
end;
function toSLV (u : in unsigned) return std_logic_vector is
begin
return std_logic_vector(u);
end;
function toSLV (b : in boolean) return std_logic_vector is
begin
if b then
return "1";
else
return "0";
end if;
end;
function fromSLV (sl : in std_logic_vector) return boolean is
begin
if sl = "1" then
return true;
else
return false;
end if;
end;
function tagToEnum (s : in signed) return boolean is
begin
if s = to_signed(0,64) then
return false;
else
return true;
end if;
end;
function dataToTag (b : in boolean) return signed is
begin
if b then
return to_signed(1,64);
else
return to_signed(0,64);
end if;
end;
function toSLV (p : packetprocessor_types.tup2_1) return std_logic_vector is
begin
return (toSLV(p.tup2_1_sel0) & toSLV(p.tup2_1_sel1));
end;
function toSLV (p : packetprocessor_types.tup3) return std_logic_vector is
begin
return (toSLV(p.tup3_sel0) & toSLV(p.tup3_sel1) & toSLV(p.tup3_sel2));
end;
function toSLV (value : packetprocessor_types.array_of_unsigned_8) return std_logic_vector is
alias ivalue : packetprocessor_types.array_of_unsigned_8(1 to value'length) is value;
variable result : std_logic_vector(1 to value'length * 8);
begin
for i in ivalue'range loop
result(((i - 1) * 8) + 1 to i*8) := toSLV(ivalue(i));
end loop;
return result;
end;
function toSLV (p : packetprocessor_types.tup4) return std_logic_vector is
begin
return (toSLV(p.tup4_sel0) & toSLV(p.tup4_sel1) & toSLV(p.tup4_sel2) & toSLV(p.tup4_sel3));
end;
function toSLV (p : packetprocessor_types.tup2) return std_logic_vector is
begin
return (toSLV(p.tup2_sel0) & toSLV(p.tup2_sel1));
end;
function toSLV (p : packetprocessor_types.tup2_0) return std_logic_vector is
begin
return (toSLV(p.tup2_0_sel0) & toSLV(p.tup2_0_sel1));
end;
end;
|
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package packetprocessor_types is
type tup2_1 is record
tup2_1_sel0 : boolean;
tup2_1_sel1 : unsigned(7 downto 0);
end record;
type tup3 is record
tup3_sel0 : std_logic_vector(8 downto 0);
tup3_sel1 : boolean;
tup3_sel2 : boolean;
end record;
type array_of_unsigned_8 is array (integer range <>) of unsigned(7 downto 0);
type tup4 is record
tup4_sel0 : unsigned(10 downto 0);
tup4_sel1 : boolean;
tup4_sel2 : boolean;
tup4_sel3 : std_logic_vector(19 downto 0);
end record;
type tup2 is record
tup2_sel0 : std_logic_vector(11 downto 0);
tup2_sel1 : boolean;
end record;
type tup2_0 is record
tup2_0_sel0 : unsigned(10 downto 0);
tup2_0_sel1 : unsigned(7 downto 0);
end record;
function toSLV (slv : in std_logic_vector) return std_logic_vector;
function toSLV (s : in signed) return std_logic_vector;
function toSLV (u : in unsigned) return std_logic_vector;
function toSLV (b : in boolean) return std_logic_vector;
function fromSLV (sl : in std_logic_vector) return boolean;
function tagToEnum (s : in signed) return boolean;
function dataToTag (b : in boolean) return signed;
function toSLV (p : packetprocessor_types.tup2_1) return std_logic_vector;
function toSLV (p : packetprocessor_types.tup3) return std_logic_vector;
function toSLV (value : packetprocessor_types.array_of_unsigned_8) return std_logic_vector;
function toSLV (p : packetprocessor_types.tup4) return std_logic_vector;
function toSLV (p : packetprocessor_types.tup2) return std_logic_vector;
function toSLV (p : packetprocessor_types.tup2_0) return std_logic_vector;
end;
package body packetprocessor_types is
function toSLV (slv : in std_logic_vector) return std_logic_vector is
begin
return slv;
end;
function toSLV (s : in signed) return std_logic_vector is
begin
return std_logic_vector(s);
end;
function toSLV (u : in unsigned) return std_logic_vector is
begin
return std_logic_vector(u);
end;
function toSLV (b : in boolean) return std_logic_vector is
begin
if b then
return "1";
else
return "0";
end if;
end;
function fromSLV (sl : in std_logic_vector) return boolean is
begin
if sl = "1" then
return true;
else
return false;
end if;
end;
function tagToEnum (s : in signed) return boolean is
begin
if s = to_signed(0,64) then
return false;
else
return true;
end if;
end;
function dataToTag (b : in boolean) return signed is
begin
if b then
return to_signed(1,64);
else
return to_signed(0,64);
end if;
end;
function toSLV (p : packetprocessor_types.tup2_1) return std_logic_vector is
begin
return (toSLV(p.tup2_1_sel0) & toSLV(p.tup2_1_sel1));
end;
function toSLV (p : packetprocessor_types.tup3) return std_logic_vector is
begin
return (toSLV(p.tup3_sel0) & toSLV(p.tup3_sel1) & toSLV(p.tup3_sel2));
end;
function toSLV (value : packetprocessor_types.array_of_unsigned_8) return std_logic_vector is
alias ivalue : packetprocessor_types.array_of_unsigned_8(1 to value'length) is value;
variable result : std_logic_vector(1 to value'length * 8);
begin
for i in ivalue'range loop
result(((i - 1) * 8) + 1 to i*8) := toSLV(ivalue(i));
end loop;
return result;
end;
function toSLV (p : packetprocessor_types.tup4) return std_logic_vector is
begin
return (toSLV(p.tup4_sel0) & toSLV(p.tup4_sel1) & toSLV(p.tup4_sel2) & toSLV(p.tup4_sel3));
end;
function toSLV (p : packetprocessor_types.tup2) return std_logic_vector is
begin
return (toSLV(p.tup2_sel0) & toSLV(p.tup2_sel1));
end;
function toSLV (p : packetprocessor_types.tup2_0) return std_logic_vector is
begin
return (toSLV(p.tup2_0_sel0) & toSLV(p.tup2_0_sel1));
end;
end;
|
{{define "_entityFB"}}
{{$block := index .Blocks .BlockIndex}}{{$blocks := .Blocks}}{{$specialIO := getSpecialIO $block .Blocks}}
entity {{$block.Name}} is
port(
--for clock and reset signal
clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
sync : in std_logic;
{{if $block.EventInputs}}
--input events
{{range $index, $event := $block.EventInputs.Events}}{{$event.Name}}_eI : in std_logic := '0';
{{end}}{{end}}
{{if $block.EventOutputs}}
--output events
{{range $index, $event := $block.EventOutputs.Events}}{{$event.Name}}_eO : out std_logic;
{{end}}{{end}}
{{if $block.InputVars}}
--input variables
{{range $index, $var := $block.InputVars.Variables}}{{$var.Name}}_I : in {{getVhdlType $var.Type}} := {{if eq (getVhdlType $var.Type) "std_logic"}}'0'{{else}}(others => '0'){{end}}; --type was {{$var.Type}}
{{end}}{{end}}
{{if $block.OutputVars}}
--output variables
{{range $index, $var := $block.OutputVars.Variables}}{{$var.Name}}_O : out {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}
{{if $block.BasicFB}}{{if $specialIO.InternalVars}}
--special emitted internal vars for I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} : {{if variableIsTOPIO_IN $var}}in{{else}}out{{end}} {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}{{else if $block.CompositeFB}}{{if $specialIO.InternalVars}}
--special emitted internal variables for child I/O
{{range $index, $var := $specialIO.InternalVars}}{{$var.Name}} : {{if variableIsTOPIO_IN $var}}in{{else}}out{{end}} {{getVhdlType $var.Type}}; --type was {{$var.Type}}
{{end}}{{end}}{{end}}
--for done signal
done : out std_logic
);
end entity;
{{end}} |
context foo;
entity test is end;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2013, Aeroflex Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-----------------------------------------------------------------------------
-- Entity: syncram128bw
-- File: syncram128bw.vhd
-- Author: Nils-Johan Wessman - Aeroflex Gaisler AB
-- Description: 128-bit data + 28-bit edac syncronous 1-port ram with 16-bit write strobes
-- and tech selection
--
------------------------------------------------------------------------------
library ieee;
library techmap;
use ieee.std_logic_1164.all;
use techmap.gencomp.all;
library grlib;
use grlib.config.all;
use grlib.config_types.all;
use grlib.stdlib.all;
entity syncram156bw is
generic (tech : integer := 0; abits : integer := 6; testen : integer := 0; custombits: integer := 1);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (TESTIN_WIDTH-1 downto 0) := testin_none;
customclk: in std_ulogic := '0';
customin : in std_logic_vector(20*custombits-1 downto 0) := (others => '0');
customout:out std_logic_vector(20*custombits-1 downto 0));
end;
architecture rtl of syncram156bw is
-- component unisim_syncram128bw
-- generic ( abits : integer := 9);
-- port (
-- clk : in std_ulogic;
-- address : in std_logic_vector (abits -1 downto 0);
-- datain : in std_logic_vector (127 downto 0);
-- dataout : out std_logic_vector (127 downto 0);
-- enable : in std_logic_vector (15 downto 0);
-- write : in std_logic_vector (15 downto 0)
-- );
-- end component;
--
-- component altera_syncram128bw
-- generic ( abits : integer := 9);
-- port (
-- clk : in std_ulogic;
-- address : in std_logic_vector (abits -1 downto 0);
-- datain : in std_logic_vector (127 downto 0);
-- dataout : out std_logic_vector (127 downto 0);
-- enable : in std_logic_vector (15 downto 0);
-- write : in std_logic_vector (15 downto 0)
-- );
-- end component;
--
component cust1_syncram156bw
generic ( abits : integer := 14; testen : integer := 0);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
testin : in std_logic_vector (3 downto 0) := "0000"
);
end component;
component ut90nhbd_syncram156bw
generic (abits : integer := 14);
port (
clk : in std_ulogic;
address : in std_logic_vector (abits -1 downto 0);
datain : in std_logic_vector (155 downto 0);
dataout : out std_logic_vector (155 downto 0);
enable : in std_logic_vector (15 downto 0);
write : in std_logic_vector (15 downto 0);
tdbn : in std_ulogic);
end component;
signal xenable, xwrite : std_logic_vector(15 downto 0);
signal custominx,customoutx: std_logic_vector(syncram_customif_maxwidth downto 0);
begin
xenable <= enable when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
xwrite <= write when testen=0 or testin(TESTIN_WIDTH-2)='0' else (others => '0');
custominx(custominx'high downto custombits) <= (others => '0');
custominx(custombits-1 downto 0) <= customin(custombits-1 downto 0);
nocust: if syncram_has_customif(tech)=0 or has_sram156bw(tech)=0 generate
customoutx <= (others => '0');
end generate;
s156 : if has_sram156bw(tech) = 1 generate
-- xc2v : if (is_unisim(tech) = 1) generate
-- x0 : unisim_syncram128bw generic map (abits)
-- port map (clk, address, datain, dataout, enable, write);
-- end generate;
-- alt : if (tech = stratix2) or (tech = stratix3) or
-- (tech = cyclone3) or (tech = altera) generate
-- x0 : altera_syncram128bw generic map (abits)
-- port map (clk, address, datain, dataout, enable, write);
-- end generate;
cust1u : if tech = custom1 generate
x0 : cust1_syncram156bw generic map (abits, testen)
port map (clk, address, datain, dataout, xenable, xwrite, testin);
end generate;
ut90u : if tech = ut90 generate
x0 : ut90nhbd_syncram156bw generic map (abits)
port map (clk, address, datain, dataout, xenable, xwrite, testin(TESTIN_WIDTH-3));
end generate;
customout(20*custombits-1 downto custombits) <= (others => '0');
customout(custombits-1 downto 0) <= customoutx(custombits-1 downto 0);
-- pragma translate_off
dmsg : if GRLIB_CONFIG_ARRAY(grlib_debug_level) >= 2 generate
x : process
begin
assert false report "syncram156bw: " & tost(2**abits) & "x156" &
" (" & tech_table(tech) & ")"
severity note;
wait;
end process;
end generate;
-- pragma translate_on
end generate;
nos156 : if has_sram156bw(tech) = 0 generate
rx : for i in 0 to 15 generate
x0 : syncram generic map (tech, abits, 8, testen, custombits)
port map (clk, address, datain(i*8+7 downto i*8),
dataout(i*8+7 downto i*8), enable(i), write(i), testin,
customclk, customin((i+1)*custombits-1 downto i*custombits),
customout((i+1)*custombits-1 downto i*custombits));
c0 : if i mod 4 = 0 generate
x0 : syncram generic map (tech, abits, 7, testen, custombits)
port map (clk, address, datain(i/4*7+128+6 downto i/4*7+128),
dataout(i/4*7+128+6 downto i/4*7+128), enable(i), write(i), testin,
customclk, customin((i/4+17)*custombits-1 downto (i/4+16)*custombits),
customout((i/4+17)*custombits-1 downto (i/4+16)*custombits));
end generate;
end generate;
end generate;
end;
|
architecture RTL of ENTITY_NAME is
begin
process
begin
SEL_LABEL : some target <= force in some expression when some condition else
some expression when some condition else
some expression;
SEL_LABEL : some target <= force some expression when some condition else
some expression when some condition else
some expression;
SEL_LABEL : some target <= force some expression when some condition else
some expression when some condition;
SEL_LABEL : some target <= force some expression when some condition;
-- Remove the labels
some target <= force in some expression when some condition else
some expression when some condition else
some expression;
some target <= force some expression when some condition else
some expression when some condition else
some expression;
some target <= force some expression when some condition else
some expression when some condition;
some target <= force some expression when some condition;
end process;
end architecture RTL;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.cmos_sensor_output_generator_constants.all;
entity cmos_sensor_output_generator is
generic(
PIX_DEPTH : positive;
MAX_WIDTH : positive;
MAX_HEIGHT : positive
);
port(
clk : in std_logic;
reset : in std_logic;
-- Avalon-MM slave
addr : in std_logic_vector(2 downto 0);
read : in std_logic;
write : in std_logic;
rddata : out std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
wrdata : in std_logic_vector(CMOS_SENSOR_OUTPUT_GENERATOR_MM_S_DATA_WIDTH - 1 downto 0);
frame_valid : out std_logic;
line_valid : out std_logic;
data : out std_logic_vector(PIX_DEPTH - 1 downto 0)
);
end entity cmos_sensor_output_generator;
architecture rtl of cmos_sensor_output_generator is
constant CONFIG_REG_WIDTH : positive := bit_width(max(MAX_WIDTH, MAX_HEIGHT));
-- MM_WRITE
signal reg_frame_width_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_frame_height_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_frame_frame_blank_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_frame_line_blank_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_line_line_blank_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_line_frame_blank_config : unsigned(CONFIG_REG_WIDTH - 1 downto 0);
signal reg_start : std_logic;
signal reg_stop : std_logic;
-- STATE_LOGIC & NEXT_STATE_LOGIC
type state_type is (STATE_IDLE, STATE_FRAME_FRAME_BLANK, STATE_FRAME_LINE_BLANK, STATE_VALID, STATE_LINE_LINE_BLANK, STATE_LINE_FRAME_BLANK);
signal reg_state, next_reg_state : state_type;
signal reg_frame_width_counter, next_reg_frame_width_counter : unsigned(reg_frame_width_config'range);
signal reg_frame_height_counter, next_reg_frame_height_counter : unsigned(reg_frame_height_config'range);
signal reg_frame_frame_blank_counter, next_reg_frame_frame_blank_counter : unsigned(reg_frame_frame_blank_config'range);
signal reg_frame_line_blank_counter, next_reg_frame_line_blank_counter : unsigned(reg_frame_line_blank_config'range);
signal reg_line_line_blank_counter, next_reg_line_line_blank_counter : unsigned(reg_line_line_blank_config'range);
signal reg_line_frame_blank_counter, next_reg_line_frame_blank_counter : unsigned(reg_line_frame_blank_config'range);
begin
MM_WRITE : process(clk, reset)
begin
if reset = '1' then
reg_frame_width_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_MIN, reg_frame_width_config'length);
reg_frame_height_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_MIN, reg_frame_height_config'length);
reg_frame_frame_blank_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_MIN, reg_frame_frame_blank_config'length);
reg_frame_line_blank_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_MIN, reg_frame_line_blank_config'length);
reg_line_line_blank_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_MIN, reg_line_line_blank_config'length);
reg_line_frame_blank_config <= to_unsigned(CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_MIN, reg_line_frame_blank_config'length);
reg_start <= '0';
reg_stop <= '0';
elsif rising_edge(clk) then
reg_start <= '0';
reg_stop <= '0';
if write = '1' then
case addr is
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST =>
if reg_state = STATE_IDLE then
reg_frame_width_config <= unsigned(wrdata(reg_frame_width_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST =>
if reg_state = STATE_IDLE then
reg_frame_height_config <= unsigned(wrdata(reg_frame_height_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST =>
if reg_state = STATE_IDLE then
reg_frame_frame_blank_config <= unsigned(wrdata(reg_frame_frame_blank_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST =>
if reg_state = STATE_IDLE then
reg_frame_line_blank_config <= unsigned(wrdata(reg_frame_line_blank_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST =>
if reg_state = STATE_IDLE then
reg_line_line_blank_config <= unsigned(wrdata(reg_line_line_blank_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST =>
if reg_state = STATE_IDLE then
reg_line_frame_blank_config <= unsigned(wrdata(reg_line_frame_blank_config'range));
end if;
when CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_OFST =>
if wrdata(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_WIDTH - 1 downto 0) = CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_START then
if reg_state = STATE_IDLE then
reg_start <= '1';
end if;
elsif wrdata(CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_WIDTH - 1 downto 0) = CMOS_SENSOR_OUTPUT_GENERATOR_COMMAND_STOP then
if reg_state /= STATE_IDLE then
reg_stop <= '1';
end if;
end if;
when others =>
end case;
end if;
end if;
end process;
MM_READ : process(clk, reset)
begin
if reset = '1' then
rddata <= (others => '0');
elsif rising_edge(clk) then
rddata <= (others => '0');
if read = '1' then
case addr is
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_WIDTH_OFST =>
rddata <= std_logic_vector(resize(reg_frame_width_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_HEIGHT_OFST =>
rddata <= std_logic_vector(resize(reg_frame_height_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_FRAME_BLANK_OFST =>
rddata <= std_logic_vector(resize(reg_frame_frame_blank_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_FRAME_LINE_BLANK_OFST =>
rddata <= std_logic_vector(resize(reg_frame_line_blank_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_LINE_BLANK_OFST =>
rddata <= std_logic_vector(resize(reg_line_line_blank_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_CONFIG_LINE_FRAME_BLANK_OFST =>
rddata <= std_logic_vector(resize(reg_line_frame_blank_config, rddata'length));
when CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_OFST =>
if reg_state = STATE_IDLE then
rddata <= CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_IDLE;
else
rddata <= CMOS_SENSOR_OUTPUT_GENERATOR_STATUS_BUSY;
end if;
when others =>
null;
end case;
end if;
end if;
end process;
STATE_LOGIC : process(clk, reset)
begin
if reset = '1' then
reg_state <= STATE_IDLE;
reg_frame_width_counter <= (others => '0');
reg_frame_height_counter <= (others => '0');
reg_frame_frame_blank_counter <= (others => '0');
reg_frame_line_blank_counter <= (others => '0');
reg_line_line_blank_counter <= (others => '0');
reg_line_frame_blank_counter <= (others => '0');
elsif rising_edge(clk) then
reg_state <= next_reg_state;
reg_frame_width_counter <= next_reg_frame_width_counter;
reg_frame_height_counter <= next_reg_frame_height_counter;
reg_frame_frame_blank_counter <= next_reg_frame_frame_blank_counter;
reg_frame_line_blank_counter <= next_reg_frame_line_blank_counter;
reg_line_line_blank_counter <= next_reg_line_line_blank_counter;
reg_line_frame_blank_counter <= next_reg_line_frame_blank_counter;
end if;
end process;
NEXT_STATE_LOGIC : process(reg_frame_frame_blank_config, reg_frame_frame_blank_counter, reg_frame_height_config, reg_frame_height_counter, reg_frame_line_blank_config, reg_frame_line_blank_counter, reg_frame_width_config, reg_frame_width_counter, reg_line_frame_blank_config, reg_line_frame_blank_counter, reg_line_line_blank_config, reg_line_line_blank_counter, reg_start, reg_state, reg_stop)
begin
next_reg_state <= reg_state;
next_reg_frame_width_counter <= reg_frame_width_counter;
next_reg_frame_height_counter <= reg_frame_height_counter;
next_reg_frame_frame_blank_counter <= reg_frame_frame_blank_counter;
next_reg_frame_line_blank_counter <= reg_frame_line_blank_counter;
next_reg_line_line_blank_counter <= reg_line_line_blank_counter;
next_reg_line_frame_blank_counter <= reg_line_frame_blank_counter;
frame_valid <= '0';
line_valid <= '0';
data <= (others => '0');
case reg_state is
when STATE_IDLE =>
if reg_start = '1' then
if reg_frame_line_blank_config > 0 then
next_reg_state <= STATE_FRAME_LINE_BLANK;
next_reg_frame_line_blank_counter <= to_unsigned(1, next_reg_frame_line_blank_counter'length);
elsif reg_frame_line_blank_config = 0 then
next_reg_state <= STATE_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
end if;
when STATE_FRAME_FRAME_BLANK =>
next_reg_frame_frame_blank_counter <= reg_frame_frame_blank_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_frame_frame_blank_counter = reg_frame_frame_blank_config then
if reg_frame_line_blank_config > 0 then
next_reg_state <= STATE_FRAME_LINE_BLANK;
next_reg_frame_line_blank_counter <= to_unsigned(1, next_reg_frame_line_blank_counter'length);
elsif reg_frame_line_blank_config = 0 then
next_reg_state <= STATE_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
end if;
end if;
when STATE_FRAME_LINE_BLANK =>
frame_valid <= '1';
next_reg_frame_line_blank_counter <= reg_frame_line_blank_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_frame_line_blank_counter = reg_frame_line_blank_config then
next_reg_state <= STATE_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= to_unsigned(1, next_reg_frame_height_counter'length);
end if;
end if;
when STATE_VALID =>
frame_valid <= '1';
line_valid <= '1';
data <= std_logic_vector(resize((reg_frame_height_counter - 1) * reg_frame_width_config + (reg_frame_width_counter - 1), data'length));
-- if reg_frame_height_counter(0) = '0' and reg_frame_width_counter(0) = '0' then -- upper right
-- data <= std_logic_vector(to_unsigned(1, data'length));
-- end if;
--
-- if reg_frame_height_counter(0) = '0' and reg_frame_width_counter(0) = '1' then -- upper left
-- data <= std_logic_vector(to_unsigned(2, data'length));
-- end if;
--
-- if reg_frame_height_counter(0) = '1' and reg_frame_width_counter(0) = '0' then -- lower right
-- data <= std_logic_vector(to_unsigned(2, data'length));
-- end if;
--
-- if reg_frame_height_counter(0) = '1' and reg_frame_width_counter(0) = '1' then -- lower left
-- data <= std_logic_vector(to_unsigned(3, data'length));
-- end if;
next_reg_frame_width_counter <= reg_frame_width_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_frame_width_counter = reg_frame_width_config then
if reg_frame_height_counter < reg_frame_height_config then
next_reg_state <= STATE_LINE_LINE_BLANK;
next_reg_line_line_blank_counter <= to_unsigned(1, next_reg_line_line_blank_counter'length);
elsif reg_frame_height_counter = reg_frame_height_config then
if reg_line_frame_blank_config > 0 then
next_reg_state <= STATE_LINE_FRAME_BLANK;
next_reg_line_frame_blank_counter <= to_unsigned(1, next_reg_line_frame_blank_counter'length);
elsif reg_line_frame_blank_config = 0 then
next_reg_state <= STATE_FRAME_FRAME_BLANK;
next_reg_frame_frame_blank_counter <= to_unsigned(1, next_reg_frame_frame_blank_counter'length);
end if;
end if;
end if;
end if;
when STATE_LINE_LINE_BLANK =>
frame_valid <= '1';
next_reg_line_line_blank_counter <= reg_line_line_blank_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_line_line_blank_counter = reg_line_line_blank_config then
next_reg_state <= STATE_VALID;
next_reg_frame_width_counter <= to_unsigned(1, next_reg_frame_width_counter'length);
next_reg_frame_height_counter <= reg_frame_height_counter + 1;
end if;
end if;
when STATE_LINE_FRAME_BLANK =>
frame_valid <= '1';
next_reg_line_frame_blank_counter <= reg_line_frame_blank_counter + 1;
if reg_stop = '1' then
next_reg_state <= STATE_IDLE;
else
if reg_line_frame_blank_counter = reg_line_frame_blank_config then
next_reg_state <= STATE_FRAME_FRAME_BLANK;
next_reg_frame_frame_blank_counter <= to_unsigned(1, next_reg_frame_frame_blank_counter'length);
end if;
end if;
end case;
end process;
end architecture rtl;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(48 - 1 downto 0));
end entity;
architecture behav of my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
signal tmp_product : std_logic_vector(48 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(48 - 1 downto 0);
signal a_reg0 : std_logic_vector(16 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(48 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 48));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity my_video_filter_mul_16ns_32ns_48_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of my_video_filter_mul_16ns_32ns_48_3 is
component my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
my_video_filter_mul_16ns_32ns_48_3_Mul3S_0_U : component my_video_filter_mul_16ns_32ns_48_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
-- ==============================================================
-- File generated by Vivado(TM) HLS - High-Level Synthesis from C, C++ and SystemC
-- Version: 2015.3
-- Copyright (C) 2015 Xilinx Inc. All rights reserved.
--
-- ==============================================================
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
entity my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
port (
clk: in std_logic;
ce: in std_logic;
a: in std_logic_vector(16 - 1 downto 0);
b: in std_logic_vector(32 - 1 downto 0);
p: out std_logic_vector(48 - 1 downto 0));
end entity;
architecture behav of my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
signal tmp_product : std_logic_vector(48 - 1 downto 0);
signal a_i : std_logic_vector(16 - 1 downto 0);
signal b_i : std_logic_vector(32 - 1 downto 0);
signal p_tmp : std_logic_vector(48 - 1 downto 0);
signal a_reg0 : std_logic_vector(16 - 1 downto 0);
signal b_reg0 : std_logic_vector(32 - 1 downto 0);
attribute keep : string;
attribute keep of a_i : signal is "true";
attribute keep of b_i : signal is "true";
signal buff0 : std_logic_vector(48 - 1 downto 0);
begin
a_i <= a;
b_i <= b;
p <= p_tmp;
p_tmp <= buff0;
tmp_product <= std_logic_vector(resize(unsigned(a_reg0) * unsigned(b_reg0), 48));
process(clk)
begin
if (clk'event and clk = '1') then
if (ce = '1') then
a_reg0 <= a_i;
b_reg0 <= b_i;
buff0 <= tmp_product;
end if;
end if;
end process;
end architecture;
Library IEEE;
use IEEE.std_logic_1164.all;
entity my_video_filter_mul_16ns_32ns_48_3 is
generic (
ID : INTEGER;
NUM_STAGE : INTEGER;
din0_WIDTH : INTEGER;
din1_WIDTH : INTEGER;
dout_WIDTH : INTEGER);
port (
clk : IN STD_LOGIC;
reset : IN STD_LOGIC;
ce : IN STD_LOGIC;
din0 : IN STD_LOGIC_VECTOR(din0_WIDTH - 1 DOWNTO 0);
din1 : IN STD_LOGIC_VECTOR(din1_WIDTH - 1 DOWNTO 0);
dout : OUT STD_LOGIC_VECTOR(dout_WIDTH - 1 DOWNTO 0));
end entity;
architecture arch of my_video_filter_mul_16ns_32ns_48_3 is
component my_video_filter_mul_16ns_32ns_48_3_Mul3S_0 is
port (
clk : IN STD_LOGIC;
ce : IN STD_LOGIC;
a : IN STD_LOGIC_VECTOR;
b : IN STD_LOGIC_VECTOR;
p : OUT STD_LOGIC_VECTOR);
end component;
begin
my_video_filter_mul_16ns_32ns_48_3_Mul3S_0_U : component my_video_filter_mul_16ns_32ns_48_3_Mul3S_0
port map (
clk => clk,
ce => ce,
a => din0,
b => din1,
p => dout);
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
hNU1Fw8N5flzF7Dghvh6XU+XL4livwFhgUKirojOUYwyKIKeUh7nyLwO0FOegpo/MFH7aElslmiH
WCSdhyjBDw==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
CXbqVSsRUpRk0hgCZEc+6DFcI860KQJ9aXS/R/aWZ44LeB7n/KNhjI0UvOcvG4qKgedNZ18erSkv
4NcXxTL51ZANLRW4vV5G63kqA33/oTvqZ29mRbUlE01gRDQzOR00+nqjWzfeKHex/3Cd0Kje2bas
bOdiv+p4vxl6MQaFL6E=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
ICxJUWvywkTB2IX+xrIyFqh8q5LbfBkmhGNlHsAFyOjP8AutiwPkvKMJPcbsaEIMkoxqclzys7Dh
VksOjN+EZIcGgVAo96+B0dj/e4nBqTDSXWKnrRlZ+BdwlfBvpIiohPy6hN9lxsVVfHBGAWd1uYBq
muudxpLZJ20aVw0jmgVJPWtYzOCt4b4bD5XF21wn5V/98y48G9iJ6nsnADHiz6HVCRbqD8A8AXjJ
engogkxMp+5sqFmnE6DPcE69qg/lum5Hu8+Br/xleC+NZo58DezDChri/UJrviiXT1lZisxtTQ0k
3yxPD76y72VYT1jciKyc0UD4GlLzZ3RpE41GQg==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
1okb0g9l27Ks0+k2riB5pSTUvnU2Cmc7tZSLR0VauQIiKfZYRt569YCYIpKCZMOI6dcOmrhZ/2mA
k4Hin6HCBoTVr+rdfv0hH1txb2ata4EMDg/cqSAj72EyNYbkuVaTHDyFUlXDq8vHoES3VnPTbo+0
SuOpbgXutkKZOPemao8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RS+gKMWH/ErKVYRpmPl5v/MXxJm4H8IkrCOWuAET1H/zTcAOZoEFCLKY/SRSHPv9xRMOIOCzlWlk
+Nkd22GRGnDjJyDpbjBi2A1o3lGHsesDzKSMedwMs7h/wy752JwVKXzamhtVYwElE8b7IQ8tqkAq
136dFy9NCwW4iqecOxR4xI3u2ECR6BTJFLXYi/scLdXXAhUQb8KkOwBtohMzOTmXRDAAQl7TWKbw
rmADAtlFXG4uWvoJYEU8C48xsE8i+WItDtK/Myk09JrAld5mIhGqacTd6jjmdBN7b+cs2aZ7szaw
t/pi4HPhfg0RSAklB9kxNy0t1EV56cQb7tAubA==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 9248)
`protect data_block
8Lff6nfhbdeB/jQQjslYvQMcIi/OoiaCgZGTr3lLta6wK48AwIAxrUUCHkaZjO+3mPLRc+aco8O8
X2pdZ+YbwiBuWYDtAIMsp9EbtZO2vXCNxMnDs998gQaoEvO8hT1FzwLdQlmdRXq/W1r6s3wvgm7A
MljRzrYTFukTeDWNetmQPvvEckwOKZhfjm6eJZxZQ3vBT7rTMRJrJNYnUqP6Boc5R90uBlDiuOaG
JYLc1LNCrxS6Cio92dZhBJwgIImzAHQY6PMY9Pk+m4xH1+w+tBtpsN/m0NeomEwUB2UQHKBh4sKr
xBjGnOyPW5ATNrrRuz6xPEAFWsV1eQy2JNRZ/eaiC/oxI4bvdZfiKO63qCv+WVVwLV1TOZ7oK8Ru
EZ3y2CKNaWJQhapbfP8Y3XK6pW3ipAbOvIXylkMk4zLQzCC5EwQfhBVmaKdRiWyWL6kKc5eGOuE6
GEuzrVjBG7QLxhlCYxHlKJDpM06OsGi9VF68889frlHn9pMdcNTwJrzsrOkz61jeh3DdwaCIJz8p
I3C3HsRb27AdlKgk+ZGodRHpp3Rp4zH4QvnSL68t+H7dcFK2RK+6KTOgdvIP4GTIx3DY10zRfx4j
qDJDn0OI8PxHCowE/R6rTCbesllxA2rLHTltwSvogXGaY91Hg5Y83bsDCLHHHTt1ngNbUhgDcDRc
uJLr5JO1FvqdO7lR08uptHO6r75rSRZOHuwloa3ezjrGcXeRhJ4iXG/gVpWynl19hHpwgDT7o36G
PXTEBQTBkBkB5DtfgNx15AOrTFLT/pNdLZth3qBH8Ox4XcLWGNOcdhPlACbbBgsGzqLFWmhVEkQi
9rjqlw1zQqBiioqtMfAPyIlLnhDTsJmE26Z+BmHufxJROqcz9BLzPa6G9sRyFSa5BontJkgtFPeJ
3ZSJ6fjqYRhjQjoNin3b5raNew9EKfWFGMR29ZHJUrURZDJnzOhnMFB8k8axC3S13nRx9Ea1gnHv
zshBKZRyyjl+otZQhfzMG0NZxW8eHIC83S17ItLxgdyynZnicabnt9oXlWZaYMXGYn4e3/IjRXor
SimFaS/yc0aq9QbCrLXuNHZ/5pU0qc0F+Ei5uzVXxFySUXbARnbKyv5hTbrArvFapZOaMmwjbtrz
8RLSCVL9Qnfou5izTdOa4hKav7NesICNainTWqdpodCKWtkxT8bQ53OxeduLCJKuNIoSrMIGReBa
GhPg9c7EbBT6JyRt+f6xq+wUpRfglM1MWhjSjQxbp9Dv+CURSXVmwjkbHx5+EZEzvU6UQM49uI6V
pORDj0YtG0x/kRqnL4EIImoiq3DeF9BbksMqnvUZmCTqkB5NXQJeQfPU32pclSNO8F8fuMImIG3k
tWtpyZP4mSdexDHj2bJ4oDYWk6Z0FpWn0eyFTU89ximBQ2c9DtRghrhkUZ0KxqauLaVenY6UBIJ4
dW/JAgkFxrlnihbKWOaGiH1nfIC4+dgN6MyBJaVaqxH5FQlPGcNR0cee21Uv793VWPL0oHbZuokH
4fYpVUaReDeqP8j5KBQBEhDYIT4EUMTVVbj7CopUEYhgj50ZIUUJXMXE0D49cPmobnJ3HoCf/0Al
Y1yhTnV0Jhjro4ieC9FfHXMIegyxTWpa5nSGMJP3rpkFCzBGOBq8IiIBYS8sj0ji5/5JkZP9tVzu
ZMJDGviMe+30FaFyHh8oB11s8c/lPW1HrupMRpdzR/4d+NjuN+pVkEonTc6N99QWGdmbok+NOfTv
Ks9uYumKyMnE11XUSX/pMSvnFwboJ8caH9uQPnaWu2XXrwQiXyvU7KaaJE2KSmXQ2Yt28J3zmoLV
EIJhYP0urrQACRbgVYaRz62zyDqE+gkh+v1g+hYM7d9vAHRUDIp81K/TvjCpeaofgoq3dSrS3g0q
1Ue06C5dWE5c8roP9eRCbJpDuSyrJrhbSVhXoSRWI5FYKLwFJRY8bfldTPpefcq/kmbQ56otvAot
9HDyb0mdRHvDCzZppzFbNDDsYN6pQCIp3+KP/qEEo3EHAEt6LcUQDy5UbfQJKrAs2o6Pg54lwIoL
AvPXyq66Y2y/g/zaor7Kms+1LyRDIKaI31YISs2ZTh1TBMiHRCVBMjVMFL4fkB7PRzrFfGNahAJS
Vpi5/h7owA67h/MoGEWQP5m6lFg1gzbLF7Um+CzaMAU4OU60kL48my3YxPtP90voe5NqKtyh4aBD
g1HkZLlp9cjRM7qOPQzrXgphzNGd+5I8aa83WjUjrHAauxOdnpCRfevLTyYwjnsHtEcZX3vnu+zz
Qlzn+HFwsqBgwBGoCnYOwMtecvTXR9ml+DJ6gYinZVOPHABxhAnt6NslCiVfeq5qcdLa8w+IXKU1
kK9N9ivr7UzerjQobYswj2ZsSf4M9oPHqw/pm0Fj2rAleqUheXVVNv7nIDuRQGApN3QT4WijpUaW
FNXoY0AnclfXw09a2XVk6ICgURcXgkzfc+WNY4rYvkllM4A7tIy0KDVrxvL1lsjoybQkjx9+hH3U
Uk+9MO5GOwduvMshY0wVuQMln+7ZETTnNbcykmiGZrzuaevXc+7azfWbxV2utDv8LesCoY3BZOj5
BKcEmOuYNLS6iiNrs+YRVZO/q8RkVeS3MCkQuvFFGAkASYECM+NpV0MceH08YtGnbsX1s3L50lvp
7VQBRr7T3R1HnnBmvyw2VU9QZ+eGaUJ8gEU3nPH24Nxl+rwQl63Rc+9QH7LSRN5s2SSpwtj7KUPx
1bqxVrsQYJvsgUpPDY3VPWCz6lsMwDUw6kK/PFrPYpfI4pGZwRSG6HFFYSTPxmIY/igBA+JH6nOv
2ZMuPpouutNWNfoU+CnccuJ15mWsSAD4BTbrRVhgUxW8IT6jNAKUzE2MGGbqs2PwoSPcsx8lmy03
OGNhii3zws+GtTdPrMl1KgPW2mMCqsQl5G2mrYEVB8G7IwnDEjXg2clLYsxQYHAMsnbkhPv6ybFb
9x63mNgrTEIfrn+78dz7FPuofc9KhkkF06rrH96B1bs5SoK59WYMdkh8t+FrLVRGLNmwCAMBkxQP
iRGb8RTIENpfNNUZpuqX3yRM843xDhOGf9oMU6BO/VUS80xDpt3HxJlTIoLiVHKTCbd/o493jPvZ
AbcsC4dQ6JrEVbZu1dqgPFEApanejqt7Ic4sbIlDmeOVtFO7kwdB3JnY+htkNDvfslNiKxvYZZuD
ggPltzJpqlG4gKt1AhQXHXDnwrO9tZ4+IBJi+a1i2GpmCWjE4EeZLsU7UCWb8cfBvo70kfGPhKsn
iTNrOU7BUCQpwGqfqE2TgYrgZc1+FurOoaErY7mrWy0iGLaOZYCLQ1wsxTdqgreTQYWTB2eceI5g
qbN0AQuyF6XU10PLIhpTg0AElVT6pKl+vodzVH953IdQOo7c1TNwMjhNhOg9ECnsXvxgaTw1+MlC
qXqbaA9F5aqgPiTowjU9tiCtKfaWNliw0LdXGiKlnROXSBzX7j5LW0LjJzWfDOR3HSY3jzwxDZBb
wfmNA80DaN8qCZ9iWOm1hzyXdhlIkxmyZF0fHpBpgvKcCN/1OrUGLDUazzWvm/9nXk8JElMzsvIL
oZ0JJpWMNqLeBRwHAeMblfIhx701OeWTNmXKUM6RlMDYxcjrE7lfHZ3ZH5PrNgDw9UqEqYhc1THU
KHfCOEkLzo9DmlYfVoPgsRIfylNeC+BMbyR4yb/ZlKv3pLx2q5EFB99ZqCboGdstL5irlQgnW+5/
z8KUtPWFn1X9igOpLvJuBI8khYtDzm4GLBQEH+tL/D8Yzqm6R8cPtZXNTJqr5Qox2gVA6s+O5J5I
xGB5c6rVwIUI1EIg9M3x3jMQ94W7pJN1/kXM6gSOOMTlQTrt6ADez6yyL33QaKauQC0CGrS1iv0t
+clzq8TcgmnEnWbQVRbpAfEebcNrJPWJnLUUbsdRk03p79Yo2+dqCHqUG/mt331Nr+gWBbNcSflh
yfflTiDFrNpIPNg7GEdK/IN5v8k1HMj/Atssmi2fMexc/mQc5gWRxNWVLshC8xoaaCIBXX1NL/hj
be+l2MH/sAUc4hUqPLgHr8lf+B6SrjH0hIH/VPXv1IqNsxILP+IJm5otFrXBTyJ6Eul8Gr9vbHEH
hPBTgPpZAja/3gWEkFw9ypMGaC3g6q58p0/f/fFR2uaVqa+m/XRfVybd/Hf9uc4E6Qe9WADERUNe
Zm5d+IhuduRjlnPySjPzExzMJTfDoTDqw1daOhs00d0dy8TvIR/l4Y61wOwheKA9AKNyoc4CFs3y
eZOH5P2Fr9fzC34B+L14czRD4RR+5kOx+Vs/NrhY5UR0Ha0Li73EHeFPa8xQuN7OPdWPuUd+k78M
15swYouKz6VI4FqEeRzhSE6nu4KIOPDUheZ/AIp3E7mZvLCvYfRoavWIKTCKaStQXESe6XUqibt6
6GszHom93Bhs+zeAwUK1ZP+ScV77DzLYIJ0PT1+wIhD5c6M4WUwZR7ulLNuUywEX8PcWYwNARl6J
gGVkWAxx45W/dMkxbT8nrbIeTVi0tEggPmPcTD+j7pnyfqMb7Iqd/2dXey6a6uqLX+Edl0h4FdP1
jCVSmJxk81uUWYPeFVzh9iN6UKWn4ISuNx0f0mEqKDoxIkT0JkiJXwsGGFuYACWTkKY6sPgxiHjK
Sl84O3Atfipfcp5gCPG9PjxPuuPrl5aTbLLA9oLIwTZg47CzqqjJTzhWyiLPgpKFXjw44ItK5d6C
6FNyjDlRi2/EYpikPhjdg2u/1BBBWJ4KvpRmLZ3xLyNtRtJ1P4/+nqyy46/P63fzPDYQOAavTbvV
0FPoEaRhxvuRTwHB/rQRc7wv1+UUjx/0SWVyHZxhRjpd/23W7zqcYnttPE7Y6T3t0T3MflUjivTv
HeS38N9um7P2TIoVMxROuNFtzW3xKT82JmQog5lmEo+eDA9y7B6atZg0vt35JAED+e2N0hw/FmW5
7kr6n+STX+Oi5uWb3Tf65+UPtmyBxFCmK48E0XhbA2HGUQZLvnsORMcZD3k4i0odJVaU/QCF2XVd
SRpIJv3G3AFX4uin5KStXUErb8tOe1SQ6CySDgJD9Fp/B/E4Cdo9JWC20tgYRdDptnyON9pAcDje
GJ6KWWl77h6+y1wVcjAfy94EpANY8boZNPrNPZXOf7QS7ZPwdY3yA3xP1/tPaZ7zwpKRPPUzKGHl
LV/GlfWilUJPdYFhziSKQEbr2c37a8EQqk52ofCUmuXDQK1nCUUrMSYr/Khm0ctsA5V3JEMIQDDv
SILWpbSxdWWEmD9PiWoqAsnkMg9bIkpeEa73B7XUD04+kSZmVJ4V5wC5Xmr4CYcivdOaijmGBBK9
pgFaXm7yziinqIXlF7KPy07NpIsui193rTc9QOWwIWXD6lpFJs8GmuObD59AXvRV9Q+ve+BtlNj5
D3p5CWhrhLtYhWb0FPC8ETaX9WGAdP/VBXhLRxXSh8wpODiwRxID5xCT+69JJErHt6H6UnunyuQr
QMMg3Xmb5YzlSZFaqqjWfxl+h8xL/wriCaLqSt7/EWPDBjpGq5y0dX3bdq3+m7Bt9JLbqp+APbdk
JXVUMFoQIbJjg7aHggffgN8a+sXVkBBmAe24Kg2Aei6tOpq8kILhAqxQlgFD1+wxXTO5cUIR2rz+
sK6PPuz68gJPvNneDzIoueSmVriY3Wf4VFilvu7eF4vVAW/c+xHGexXGoOAKUD96dXKQ3u32Vg2D
0RE3HESdUy8bU9yKF9k+hSL31046kBWmFzPLZoBud9BX5xJJMcdvi7EyQSueYcclRVNqsQ9x5pKk
c/LD3D1hjobG+aifrVz/VRLQ2/WZ78wmWHiV86N04892BgIHqhUzVJJQGGVQVMcjX1fFCoEAdFZT
fA2jeNdQ33p/b3py4/XI/mct5axOq8wc5LUWPnMrUwhbfOzZDFi249F2tzzRgqUK8kXVzjoaeGmP
fth/Di6ZY2PHmUqZBhLSX3EV/GxuAVBI3+uBmnwHElTZhZ5SQdKXozDFP6UgQtnaK0yw0e5BBipz
UZ5s4bTDmmaAEezBMRFnosWFp8F08y60MfbmnqNxJgR8SnIbgkYe7BXCnGcbVd/pTxuhzYxSL2Yi
5loM66obFecjMZchRYaDdELyfVXqk8IPbiFKXINQnXfCxg9en76yAJ0SNplG+eO24dMCUVu6/aj0
b+ukCtHPwtOk4BXmBNzXRk12BXXOBbszslXRGJzq4NZTjcksdeZo70ltpkWu35Q5ze5AvI3QKyaa
EAmYYf9Igknu4G8qJn6wzYkQ3ZGsMjJp0gsLGwJbANEPt5zHrg0rPKGy8NLNJJrQLEo9hoxZUUKv
VKD5WNjdwlgVi4zFGZ30xj46qxxOMPnKyIb73K/PCCnyFr3lBdMNvCL58G6kGG7pg5qiqSO3hw+j
qpyO66S7NHu+usw4b/89seUDmdyzz7k19abep4CwwcO5aF5KTCaWFluWFK6+VGXGxoMA0W7HXfDa
6xIGRp8yj+nKTYtQuOX5ZSta9ct54vwOwFKX0kOCP4h2I3HSeb/jPx4r2pAwzqWm/BTfIw0CtUPX
DTqi9mlZ0gvblQKm/ARwcAx+6UCwubn2BihvuLLZ9B+i+Y1sz9l0Gud2aInu5/ipWh1MxtQLDprR
CucDNEVNqz4Ph8HKD49u/Q+t4kNMSCj4nCGdBzzQzKLMRsTaEc9TlmnNWu6cJkUTGjCb3HofPsd6
wRpLI5tO22Mt2lgl7+d2jcyAMctiyjCsyjvsIOEMGfrVfRsoBcE3BadfHrA2edkosRLGlEXLgX2z
YHHsZXHpBXEQpWJQr/G3EDJTEqqSO1vwllp28hbWmRiLCGosYFeYx7USobrGQvTc7zu6M0P0sOP2
3J/5FlD8SRIgBtK6qxRzJj/+/Hea0nrAJXWTteo13wv29/bEbrlhcA6Xjr2rWBKRvDDGFhRPWaNe
2fAAK25iPdKkLPc9oe2a66kEyBGiuyEig1/DgpkfLHVDkQRkr8Ooerzi60TBWHhCwoLTU2TV7O2Q
M2ZUoEawkMzjTe/tK7Wh96zlcHoqsb8gjaNeV7wTGqPSJD0wVYnLqJ7+uu1sXFt0PsVNhmrn4yaL
XOnw3H1LnHVC8WVo5rkYOHzaJSLhVWyP2SQao4sLp8pqG3+qG4QhsAu/aqQIMNSjtdGpecZFLkqX
VknhvffKoz+DIksPWf4Tq9n9TwQjRP3ddq8mDvAfRCiwsTRCy1eFglQw4xQmN6I9i4FlUYfKdzeK
/dzrKTJq0AjtvKDTQqdw03ksYQp2HEURYVPzQn21B9lxLQyUR+7mefZqZewG68WgFdXRUdjhZ+5b
g972czfPc9KKTCdTJrOSlQmp0fCUUsvCOCuOJrNEI0er0eVSkC9GfgMs9OO1ra/hl0WVlHZfFTLt
kXhmejlMjPEx5m7n4m1/Wcf5gRPficCT2X3fdBBWGBBtz9z4qmUMsCdK0KCypCpGA0Ej3C8+zCNr
tdHoTwOAwWHQrsr8xjaOv/uySuyaB5A9YDQwvP9OV8cSNQgUCitAwlnCb15VwujqWdz6jujo9Vus
SlStCVNXN/q6v3tL9eQFAnP5IAHLDaAzImhKynbiRTr9IOoGBJKYaxTMCC+dZdz+K/UykysxIb+/
UelCBz57pxMUvR1NEVPeo5HNGVgsWRZRhqx76xPef8RApICE0dpn/Hlh0oBKLim2Pr0uW0AwX8lq
r3Bv9wtI0scj90454cpxcwAA4+t8GjPTb4AiLi/9xaFzlGr2cOMr9GIkU460JTDidn55Mv+rm//F
/Rt6Z3Eaj/TuMMjCNQmNGkfA9GwbsWVZe/LI+ijzIPac7/EIHXrP9VsASmfsBjF44I8GTmIYgeV0
jdpjWn04yrJJvpCi1dpgYJm8gKCaAJg3opUJKTUmDmW7zcszqBIgTIx81y6hcQQNKBQvod5sEP70
04KK7jJZdOP6zprBpQNfpFwpdtv9vFAywb2sl0mI+HLvVCDc5SG47wjpjgG4nn/NG4Eesyyp964V
7GiFbawLzMEMlQyCvO35kQjRWGsU6stO5bLTPBnBhv3cW4z1hHHx0XPBQvduHjhkyLrpErvPpXuz
eZXhK+DBsGgMJkas9OaBBgIQ8/fvjYtbV+BWoALk5TmDTmA2uFJuZjdvgrPfaU20GUzRGKmrKGbG
6OTCx0JbuYzQKrmc7/HIsmbMIbz725EcwypP5cX/avjT8pexnBXjNHYgWO3S6/wp8UZY0mCi8SsZ
rXWFaktd17YYG/LXCu9+Cz23m3IR94IRU37js/xhWKOaJLOsb5Pbz7hOwbChLvCtJGMNC6pUO0g/
6zQmk2ygt3gw3D1o7xMNIVXW6n0uMpBC1bzwYnUYw83ESSp8CeuiJaml3LwrYKefR2JBxbM076KG
ZEHWtDogw2fTB6BjkEjUFcJgSrtq7v1M1ZRorrAcTEFfs1oBNCUBmxtrKf4kh0Xb5jXtic8hyBxy
KCai2mzYRDR6lxtRNw904t16NaaMi0yHFJKZO274ELViQRGjTnjmOLtwaR2Mv9ERb+eQ5tjEfumi
JiMnpSXhEkjlrBGqN7Vtsg3zLEyBUt5/kZ2reFWtEw6iSJaWbPMqUl2IHLmb7lyHXIko3skU2iwk
mAl70zgkJNv/a4RcZoUvq2OY9qAZtevVzlq6YLtRbGr4deH4gtYhSlCgIutX0F0gcwvD0aKUaZn1
cQZJch+Eyr/WYV5wUUTlR8YuclYd8p5obqhVgPPzPvIncvzMNpYsKoZRlwNqrkO3s/HsoztMmBzH
IdR2MipYEPOclOk/eMDfnGL2/xapw67/bWWDOu4hv++frJuAnLKjJhc0Hznx2IL3WUOvl1YjHLG1
fc9HWLnwLjN7FEFmriKTePDyO9qVTavZqvQyCKDQEXyhUojsQzGJ8REGiJVjtBbsYMhyW09A4qLC
lwHCguzOp8YrAcuJlmJmBmujXhBqICXoz8Rr0ukiysjhWINR5Suekthna4/fKRujSrmLwQ6QkBAi
wCcmNJondvSGtdDhOoYvYXd2w4DYl+vQiwqX9x5b9HkK1XnRf25EAnzg1sJvcWBC3RG+PEQk8B83
fOGLJOSFzTVXNP0nz3eSxUg7QDhWMPMvOZ1qnScZf204vh2kSnwXb5NOFT+G28UkfBPW7j1JA7pA
O2F/nOUIgLMHvQX2A2j2UPQrWDhEFQPcHOItCNPpBxhQ/cqKrvLorY2iYpEci7VH2GqGu2x/2B12
H/FJ1Xq6F8nksIzrKyHgbAAPCfLGjOtxF6mJCT2MM85DyIL8mAIbRqhQsPM0zxeJ9cW3yCCoAAld
dGmAK7uZEPDGcav38eW9G4+8oWTL29AAdnyXnL05OMMqSo3I7QbKtttf/G7i6RgGMPAsTaDuYWyq
C1ARLc2wJw55+PsQ28Hqur6kdqvhypIKPXFFy1Cu3tp1VpeXRxO7zq/LNsa2KAN20f20JdqtYPzW
c7KNo8V8SXQWZEvsFv90VrNshGOGxzeYXQcXA5ZLIVa9L0i58LiGaUFrYBDMEduevl4Q8AqBXHlB
iUiUxPWoCfGSGeE7XYmKjDOC2h0y9wvJqV1w1qQU6VA/JiHTEhvK47dmRYcGFC0ZiMDIbiWczixU
v+iLS18FD8vrLK89GzkAoY1baFRg7hzdF6oi0NzQLw3JHgP+BKxhmfjPmxggKGotN452Ev+TiLGk
2elkKOhfdCSZqGmw7slLGJW0x87Y2RnDXEbtvzDE+d8sPa62Nah8OMCfOkYYz3d85p1yAQKPGenj
AN9/ZZUd5aMBl8DL+SKe7p/XoGMrbnF2SlgX0BvpDSWknx3OlZJDRJQehbc8WKPMBuHpER9nzU2v
ZSewtmZPl8NjJhnLwm+DQXdHNQtoF3+WJQKfWSSJTxDrBgbvd1hDma2LeSwlUf5B8qr623MKvFWX
gbDy598O3R5RXIjktth8LRv4Z/osFsjYhXKrFDJfdkhFMEgZ5l1V5BwHBDSokIgOAdGN8N/5Qlkv
MCNUO2SdZ+z/WIevW3aalSgXKiqns8ZiKOE0gQfTXj+HdoB/ZFTjssgrKXwOcoA/y/p9DHLWjc1z
JQyy/pOQL6x9YoZfQaf7lynHhztdQlQAui7uNu/Bdw1qSQSJZUnC1GVCZvZRXrmXU0D0cVGk9P5E
ToPKjwEfvOFOIMzlCNYY9/tOImas7g2lRXafAPa3AZSFO+VZmObtQpP7GvuoVkSyAutTbWCWKLTH
8szDT/3kumiM5SErDKiUBhEO0Yg+ahw94qHWMuniLgErhAXuMP3rMd9yz62rAEBBKU70aSD94YY9
DgDw23wAaL//HMjJuffm7RrIIW4tF+dT+WllxQLJU/HMb9STgIEirxeZO9QFr5KKcnrRYKl1yze9
csLa/H3gSY58yM2k9rC13ZjTTy9r1BEF/MEP6aTBxgSMkl7fjDcTmeP58sMad8/a4eLEg6QjY3Wi
3TSgF/ernqh2p/pMzIivCWuC90YoWINon4IH+VR2vp+wiXJ4E2zKOkwUyh2pnERF4bgTLwAORxPc
LebgqXSKSiUJGHjIoD3tJRobve2Yjn9CHV3KA+bR2NKZHC/TZ4BnzW50H4PvHOjDHC83LgZWkOD8
95ELh9sqMP+ejfaXox2kbMptD1oj4SjlwLiwafe6U5cQoqeXOQgKsbthmoPDxmGx+O9qsdw3OjCM
CLtw4HW26bOHPfbd7J1Oe3BBXriYyFUM+yIoiQuhZ4FEPHbEXb5a+uxe4dAXHEAwTzzse43izXsa
WB3BraDFhu0MAIpHsCIt7tFQo01UumVuJ7iAYHxe8WFEUrBtzVhAipP23R/ih4Zt7FMAZ2enrH6o
V2LRbXftDP6khEFzOxxxEBfpEz62XjvLqv8tFaP3xZTrOo8S4kZkVPhMfl+H1MVtEEh8uRjaXWRd
BeTGZC8yO5DmnNJY7cQdnJpHm9r+fc/WDzerLrRoIdvoaFtr2+ePAfV6vw4gsxzx7Rq0NTeVtYP+
0sMvMwzI/CBe7bOF1WKSW84RxbgP9w+ykNAlJ+C4knnICPUaZVAqEoPxPCodrRG4GaTqLMovdIxw
H1xIOQBtc0noLF4fzG0Q+JQ1S38YS0nJxJnv6x9BdqfEu/FZvDATRHAZZ5yEidtr3WQQemNAlcrM
W5YXJ3T+BoUVfV3VUVfx6GamPjClp73VADQjKXqBw4r43l5BsK6hidUcqsXs8w86BxHla2ejLY2F
jEwhc7B5xyd9bdOLUNUCLAcxkW4CXCf8Z1q0ULtphsk+4ku/PGMRv5zgvQsPlN5PzqsRG0mw7xyV
5PeOKIIKYI61qlbj25PuTc3eef9jhMYndd80r3X3ZYxBlyYXeE5wZje0owUk5ibKdX+xVfNSaGLR
mMNZK2OTRFUjYKK2p2PUEURwzq1sMGe/dBY2YJxEJVmDmReiFujrzyG2AKziGIQvblouXVCIKaqU
a8I5xPosV0B5KxyPn7nO3U4m8a4Bnrsd1KJEuCgP6MmIyL3ayMo73r2+2HXHQIMeLqKxeaxhfx5d
NaHIsPRhebDE2fG96XkU/82Ftn+zQs0saA/3I/rwzvgnOn3v33VhSJ6x71EIQX3B2ZGvKQoE47Dw
+JR+sMpIqoGXoR/qAXUXGofFxvM4um2foOt996es4+/hGDBflawGUHS3oJpTnBn9RjdQnUvhjxUi
hgSa17/HAY05mSeTxp2s/gAeqHuH6Yj1osTw6ZHPjpB4uVheiptnZeN+m3p84qhBBFGogvC9JM0s
WKN0oG6UpcVXbaykxebvSuKO9QSyFNLKw1drA6qK1E2zGVP1u491FDnf9x48kBmBzyrpV9b4z+ol
44C8QtqxNDS/7EoKyFG70LS/Umxyh+U4U38WxJWcyiZMahTQ0OAnyLba8mfw1v5T0PEI2AQZG8RA
Uren/IVS66rETSjj6ykVtcfCCTD0oAiIjL3Mrw+ehi2kiW+hWqw8OVuzuUxymOuGlhIkR/n+KGJY
2SLjzWKmq9+LQsATR47KQWoB4M1oXW4Br+jXmjZEvds5z66hWUHyunW09bahf7INEmhSQffgQpYt
bo9VFr2v0i4Y7KZ7B8q48EXtcmoLpY6rrgHUDQAhYDG7dVBfxorAz00kV5icTa9UcAoEw/qyatwH
5Jal83kwczDPXrq0rRteFwh2UJNwQ6u0Fkhn0aIDcwpCo1efPUAH2BOYOwpY+I87aCxUUA7wxpwu
2Y/19NQ1kwY9hv/MamTDoyZWJuBSpspqjqfakEl+SzzKcrJ+6yUPD99nVogmvO2r0MFF0drWmbhh
M7l6C28wta9j0HY3EoBFw8Mkwsp1mX1CpTlhOos5ye90J9SNjRYpOrzQK+1C5DwimRob8/K9A4hi
8wdEA6aRGHuSH3vlDpc=
`protect end_protected
|
-- file: clk_108MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_108MHz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_108MHz;
architecture xilinx of clk_108MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_108MHz,clk_wiz_v5_1,{component_name=clk_108MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_108MHz_clk_wiz
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_108MHz_clk_wiz
port map (
-- Clock in ports
clk_100MHz => clk_100MHz,
-- Clock out ports
clk_108MHz => clk_108MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
-- file: clk_108MHz.vhd
--
-- (c) Copyright 2008 - 2013 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
------------------------------------------------------------------------------
-- User entered comments
------------------------------------------------------------------------------
-- None
--
------------------------------------------------------------------------------
-- Output Output Phase Duty Cycle Pk-to-Pk Phase
-- Clock Freq (MHz) (degrees) (%) Jitter (ps) Error (ps)
------------------------------------------------------------------------------
-- CLK_OUT1___108.000______0.000______50.0______127.691_____97.646
--
------------------------------------------------------------------------------
-- Input Clock Freq (MHz) Input Jitter (UI)
------------------------------------------------------------------------------
-- __primary_________100.000____________0.010
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;
library unisim;
use unisim.vcomponents.all;
entity clk_108MHz is
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end clk_108MHz;
architecture xilinx of clk_108MHz is
attribute CORE_GENERATION_INFO : string;
attribute CORE_GENERATION_INFO of xilinx : architecture is "clk_108MHz,clk_wiz_v5_1,{component_name=clk_108MHz,use_phase_alignment=true,use_min_o_jitter=false,use_max_i_jitter=false,use_dyn_phase_shift=false,use_inclk_switchover=false,use_dyn_reconfig=false,enable_axi=0,feedback_source=FDBK_AUTO,PRIMITIVE=MMCM,num_out_clk=1,clkin1_period=10.0,clkin2_period=10.0,use_power_down=false,use_reset=false,use_locked=true,use_inclk_stopped=false,feedback_type=SINGLE,CLOCK_MGR_TYPE=NA,manual_override=false}";
component clk_108MHz_clk_wiz
port
(-- Clock in ports
clk_100MHz : in std_logic;
-- Clock out ports
clk_108MHz : out std_logic;
-- Status and control signals
locked : out std_logic
);
end component;
begin
U0: clk_108MHz_clk_wiz
port map (
-- Clock in ports
clk_100MHz => clk_100MHz,
-- Clock out ports
clk_108MHz => clk_108MHz,
-- Status and control signals
locked => locked
);
end xilinx;
|
entity condvar is
end entity;
architecture test of condvar is
begin
process is
variable x, y : integer;
begin
x := 1 when y > 2 else 5; -- OK
end process;
end architecture;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YZt9CVgibtz1DQhIVW75t8+TB5qXvdexZipIOzyeYIgjhSC9SRzqg6fjPwWu35j8chcIzAAacfEy
N/Vp17OxkA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D7G+voNCt8FsDi3lN0+coq3b3FkjH/LNdyhooKGcm3s/eZ0sVak/m4rW+ojrElXDbYRXuatPl+SX
Lc1hLK2VdyLMqWXRcyLZyKsDq3V3C2FXvr5eig5UHiNy5w2di7di+f5wfWbkObli4928VyEp9aR7
YQv27whektGwcfV9U18=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GF3K08+YYqBd2ub6UE9jZ/5bHRPiZ2QgQMvQCsD8RURUNmL83Jq90ui2eflqe4TOcGuC6wPXCjM3
H8PpXsD/hHmC+6FkQQ7UoicI06j9/DKap9niHRPf65xpNEe9bPUMBhd/IQntjOiGUmc89fIsGQSZ
RkcPZ5XwMdP4hs056yQKej/T9on3Z/8f3kEJmRfcdfSnVxwWJyZbDV2lM4M6NJquGBXcyf/QpU3W
2KhISzSeqCI3pEwmkoen5IfqD5ZemYxse2FuP6MVQoZVvrbH9ProAaWZ3DuOxu414Z3D0UjrdFt8
823S8MLZyivBlbVu/5XEgvwyRYrwX+KdshR1Sw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MIlcOxbbFuYAuGOjTR5T+J3srLvuO8OEWUb5EN2s3ucxWo80Gn2QZggebQKC5pYj6sLppCwudLDV
cdqfX9KBvQtHkkSgj8aqVuJJN7rYBzmGDlibrUPJVkDVvRZ85CN2EH+9gbp1V8eLR4g3vPvJSJS3
71afQJfeRO0iX2gt4IE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Fp6Uhu2a02nqflyhMvH8oj0IYd9pTqoMCSRb1p+GUwtPkmJbfMsXRVcCKC40mgD/Wkj8Z5V8eLXS
HCU/6hqqfM/0xokNMCxQGOW8yvROxuVkt8YUml7fm0Cs0UHaAQLheW2rikLn43XQjQc/Zn/9jSac
Rc5GmhxKQ66ADM4gjqTYtNH4aN5KxZ6Xq7+GQfYPT1G3YQCyCmQOO4ggoGumW8/QFLhxe/X6+Plo
TVdOJIyx5Xa2TC0jH7A1zAo0rDUsgkkcEQZnrQ4p32W+8wuvWYrTPUnbZiQkBftFhpavuPyBQ0Pc
TxJXY/KHBe8uimmGBRd++t1lAlrftMYRi/FAGQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
ZHyqMQFkFijxELUyV+w5NMv1U3wBwAEo80aTrxTML36naBC6m1PL3qLB9GLPcG9fE3ECx5V5TigZ
QMKAlt4Dz/OntpGG5NmTg8JpH29YXw7zvZxhHRvgOCcO9iHMb0LWIueuQ+ZnJbcotwdrmjafFI0M
C2cIJ4sbH6kIEuoh3vw662LW2ZyT721nr5S2IneEi73A0X2WKiKtgkpNJghUMfK4farz4OW0Io/a
V+c/6t7GtTqCuA/B/a1hMBXgk9yKCCB2WA8YOCYdA3Kt1coAv3PpESDYr5oTkTtdK7zlTMh+E/TP
NwXDlSlN1FLfsUre0H9oltsSLu37ecFHNocLJi2XrvQcogDWj+NOaH5wM4UKZtKqz/dTh8e/upkq
W7uJGqbgiHxtXkr87xMS462OY3WHsv8pR/ozLyF9k0wEABRazQN9DVOKEcpp1BUU7KF5yg8niPy+
1gyN81eyNgG5wKtdyxChTS1PxS9+ADaitWaL4XWlXt2D8CczYgHna6lIjbFOkHoAJDnsPMdxAliK
BhLhzln4sEwgk3l201XaOyWOQgGGMS7wteQtditvOxu4fC3VQLLpl05ozhHdJc8Jor1fQ5b7k4BW
lqm2QDlq9/BdlDZ94NDvgFxJ9N+c1SWSb3jFkMF7TT0wII4KbRF1vIwb9u1Oj6708VaFnF9gMv7B
T+499nYqBC1sW4dHr1iajEm4Ls0P7Zw5yBHj9peGVojXeJrx+dVWgijbfk8y4ekm9kQusGdFtd+x
2vzKcVqHFEN5C94obFoN3RWy+jU1K51XKat4fLOmaYGmivlkMrCYlfj9yZAnLCEgOsjfQqctA339
W9ZNY4sdYQaDvN1yFF+SjpO3+PqdbfpnQUw/YPepcpo/oBHNwyGsVL+8/cKGGJ0YApDSntCg4EoH
og79SR2bJOCGl+ot8k9oKYQ7a2rlOrJqKoJ0KZq95HNmx1fElnXfHYa3zvgzvyyCAg6ljLzXqbl2
YArKErDUYFWRlKjAMIFIVKXVIxslpGjqTID70SbVEXoY1XienLHnEIB7gQVFPKjSAfcat7B0T0E/
ZA61NlODZPnVZ2WcT6HfnCVkyV9JVVmBZwz92n+EkZ1svbyi3XCK6SbjIwvcrgm6+Pn1328K4oOV
+rIi0S7bDuJ4tLjirzCb1TfpDSAnJr4QGDrXg+YY3luo2yFhDcFxbInSSVg+vQTdpgwiE1sRB7Ye
sEPn9RHOjg1JfwWe+4es8Xzj1MXXEk9IFeWu/2PIYR1vU4HXvIOHS1/nOXJSX/dHdISJSkzGW5Qs
1REDXn/fN9r7C9psxSSiY+TPs7GKfqWxGdPQlatKbEq6KZwKdm9fbYYY1yKmboSOgMmGVlEovAk1
0BEDhiJWmJ2EzAlEioEcHowdlmUZqJbW7vuDcnwLjx3JIh798QNjAtVGVzfglEeKXJnIVWwMbh/l
d4wjnWoCa2YuMsvmELSWxEvuyDI5w+ZVqp5gblpBom09XFgXHceZOB3wKV+mPe3VGu13/q59/uBn
y9btXrCpmKCGGrcutmJhlgdOtJXnwxia+EXbuvzrwakSgnSd9c7FSlnvq66GwkjLx2fWr01OytLs
Iom6sFMbHiNyCTTCqBcyi0kD5rUs/nTR+gRR9nhmvi62mOr7ZJQ0PEMWCD0av/AmBL/kLNXPdMqk
J2CuiicMXW6Ri+vzmAxtF22LZyouX2dkVB1KEvKIntkH39PC5eAtfqF1mWomao00XzC5DX9D1OCB
27qmqQQ4lku9CxpFLkpVx99hTxOSyRCTd0Yp0Mbi7QAM0GGw+3alQ3y8OhZnE8iDyrunM8q5IdM7
TVIR27sW+9dV/qDBaflG5uWp3CY+DNOVXXwxymADWptnFsGkLg13MiF3ei7MBbRsWzn/jjxTqddS
L5ufM42yhTUgaoC13cidiY9HdRRd+aRUSrfGz9Plgz7vjVauIxt6mbQnOiyUx+H3GtA0Inhift1c
N6BHTVXgaWNhG0LtiQfdo3nrcjV3NdDeqg/lgdEcMSLDt6gKjspIdpSMbssBV+YJiDSkawbPEAXZ
oxc9tMkVAkuDbWromf4BCI8YbeBgLEc1nwOsj/fvksk4YB3OtlZCiVSxqgi4w/YVN1wr0Vslw6IF
7xk6wtnYpOYRqIO/TsGecyydMCb9MMzNzuOwOPh7S5D2ceb5sujv5pt3Avjlk8eaTX4TNEWdbqso
4iTr6gbACRwlWd/UN7Kv02O5TN2p3E/f9ztLnkgGYrHLismGrwoQEUAtd9I8RS1S6KcdoC97Qu8b
vPr5Zdub5dhfLPZKtPx4Syh2vlb+fmLPIor0xZezBu9HAFPrfr+0bkFaDJ2i4iNfl34mtnotslkY
hyjf8FX6s97rT4IMUMNZBYFwGg1uA2iRNyxBtS71Lzl/c18sYP6kP1nWSAP2P52k8cyx4+e9NTJb
W4BKDt+nSdiZAFCJzrJDHzDvGO++MgST7LvARdVTdarb3cc6u0UALrO8Po4UZFSqgDxTA1p4JCWp
FPlgFSaZ447T/0CiDvWZd/OEtDMXMa1oYb6lcGFmUKemVphjqHsgzM6Kix2ZEJrKqIuwhSFCXL+s
pjURajGfF8j42bPMTD4cjJaSxKlajTAiuPPV8p6GpeWrPM2VrZiTSDigxbQri1L7YQ3bes0luTrW
9lbHFSH220rETEKNq69fbfWPXpjrNqxMrhjx3d8Ye/QsxCbiZnv0kAANnz8ghFIEr5nJ/rPdtaM6
f26h4k8s2u+9k+hbwBMAhirpkrNARQBaXZmcSf+6D1c4cu2LfABjpndXVpCj1jGbdQ0R/+Z54OfY
88Al6JXNnfOrS6IRTAzw0K8OzJISKLNAP2TAA8aU7o9a+0LScWqua/c1ATlt7RR4trk6dlp8Rwd0
cgOpx6exzK4S90Lj2GTjTfPS+l+aZA2ZSS4t5vH02MHpWyX/A3PcQ3witevcdhKVKCzvdZhqSEKV
aC0HTvLm0NE5HryulbcDKqAhNnTTmD2Y8R1XUvevx7ncBCQqkYvorxLZy4Kz1Fp6mTRU4akiBM+i
sVEc6eMwAyQp4w+3d0B6/gJaDERUVxFpO5JMPF2rEPuSwGrZMZfiIFsYA+h7x7X2/+QiIoY4FcTM
uXjSBcjHGzLW4nXbFXl88ISnhccbIWLHarGErT4DuZWs0sdMuTJWclNrZURZ1MqOFV5iHsek37a1
VCIBhBTHPdoz4BwcFlA4fFnlFvSzhoESghcvIQg/4D0DVmSog+Ws8SF7yLhTfbZ9ZEVRsvXhaXFo
OmyaWD23vgQUsTzISAZZrs0y1bH0Htoiyj6u+T2y0zcPkvzmEReDyEy0kr8YGSRxdNlbTkrzdyZ6
lddZQ4zGXTXbTd4NHrkmA7I2Lz43EUe0++neTDStW790/HeKFGUsEF+93itxHw1lErKGKoSzlGfp
e5oNOrdJDyNt19naE66ORINaFMfp5QoDzdONPBAjlQBPITNdJkUgmnnntjaORK+B0XrEA30jF8XX
ru+EJXq59ULhUMHcVsmRB5YofnuzsY4XIcna0PdkRTMiUJiV6ndstvQ6YL50XqctnpSpBevWqMHt
KAkN7xN+L8Txpk+DGkCYcoohyYgDIGQxkG912jdrwafMLMjyViqXzyK5093I3dsuUyItr4wNekGW
63va03ioJHX33jptDWmYHK5iL7l7xzFb/ljQCdhVyhw+BZm93+FhVkHd/Xgtokwy+6/sQgS7ynBm
6tDpLJC2qLug5/WgOH/G1hV+2+KTW7EuFbSqwuMs4AySDkE43RS8xtypMaKb972Dmsq8QUanlqQZ
Q+Ngx8ZCTMQPI0xoSxfruSidVavLJIQcSQdnUgsqXAUBKDUvjHuXQKDDrJBckLXOS7zEV29emuY/
W5LobOf56VLImsj7M66eAlWtHRlv9eBPgTKtwmFSt4NePTSGs8AbPsmiTOxI1PUc/3xwYgfcepAu
W8rKjorBIN9mDKwQRxCbFXkmY1OclejTRvv47hih30UrKsGtOn7whbmppVWU0tDLCqdxEjuwuXgJ
hii4PfEJUZNpiUjRwOvGF2IFsx4b16lQKfM74Prux6GMMIh48aFa2HYFIhXLbvL1Khc0NNucj4+E
s/p/6IdCgLzdSPngX7ze0gNWIoQcAZv9HaJx6R3UCIs+IAchinZoA3iECJShH+LrygLPQSjzBV+D
A8qgFRRbASFHVouqtTO5YvCYVSpQP+NqYOfJ7vIZe4DV8R5ZDGwqwJPAYoW5uV70fd9D4N09AyCS
f3PM4ZJVknTltLb+IHr62QKlnSWby8dZoMt3FGoQuXt2+6M+V19AhF7gi+KwbSCs37bqvhJOR6me
5PMDkVuNmxhfAInMHtsdY/tQ0xOOmqGhdJ2jIsSJjIP11lroWGd5I7AYFVH/cjHOYNn0mCT4VFH0
q/3efEVlaJWNRUF/TbcQHDpvbeZwlBgLZHip4+5532lA/eLNx5rXXYG7SCDElLWUxUy2Q8qI/yy0
49+dEEa5Nkabim7slOxs56zOPvaIf5XGT3DhWucwHZJE4S3K6fu8rdzcSAc72x9T2HT9nHQysiGX
n6gjfUgKpfNB9OgYQqRAwiQo+KzhXc748iHdCB/+HRwovBgDN1plEPFSallSJ334Edpnt68c4x/W
AAeKcfqoBg6MvTHHHYTZJEYBND1mQmwRIW4bnxVSIFvhAN+AT9D1vTP8gKQDxLkncJJ0+p3416lF
pbPG+I3fbj/kpVWWR13h38pdDnX5K0D4ybzrmHMB1RBdeENF+n3rvUvVP7cdxtzjacjDGOsq0EW8
b9Uu6TJXSNnVgQWM6CT8tpAM7zYLSWRs+fQdKa/+CA/vVIJk8v4qH8+Bfkb7OvFUi2XBM46dQY3Z
px3y9qt686XLD8xK+tTVNvcD6D2WKhga+pbfJiOd+sbCr9wlYYAX3a+561tqA5fIcPRWN3p7OcIx
9ua7qIx3s21HCJpx8YmEb59c+JyPPHOx1b70AZ337lAohuNvKvbH1V7kFtgQLPZBfGB5w8FdtiGu
PlbxYR89Oc0TCsE5SlE7LlWCYXlq3IWRbGLIIJWiU36aqYxyAjTFG8usPNmCA/hSlFfctaWhmnqh
3/LfEQHg6wyvj7LT2+JGc4iPBiL3ttBy6k1ubs/wvpcoHnCH88TK+1zBNQS4btoExYH9GT1FMhkt
2VcL2uGksQ/4epIY5rxMQSdNkoh8bBuQWXIeLXFZaLsNb+vlZJLgc7NRLsNGB4SwyYA7C9XlgOf6
Vk+0w1wB3ArQVEW9DU055auEXZceQ5NdWHMXqx073wmgm2u4eSMdWRT0X6fZ5p2fQh1iXDLMWAO8
4PjWBfITloHISmXpVmi+MOPRcjTrc6GoETyxd01Q3wh+J3l98Lx8Ii+m
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YZt9CVgibtz1DQhIVW75t8+TB5qXvdexZipIOzyeYIgjhSC9SRzqg6fjPwWu35j8chcIzAAacfEy
N/Vp17OxkA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D7G+voNCt8FsDi3lN0+coq3b3FkjH/LNdyhooKGcm3s/eZ0sVak/m4rW+ojrElXDbYRXuatPl+SX
Lc1hLK2VdyLMqWXRcyLZyKsDq3V3C2FXvr5eig5UHiNy5w2di7di+f5wfWbkObli4928VyEp9aR7
YQv27whektGwcfV9U18=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GF3K08+YYqBd2ub6UE9jZ/5bHRPiZ2QgQMvQCsD8RURUNmL83Jq90ui2eflqe4TOcGuC6wPXCjM3
H8PpXsD/hHmC+6FkQQ7UoicI06j9/DKap9niHRPf65xpNEe9bPUMBhd/IQntjOiGUmc89fIsGQSZ
RkcPZ5XwMdP4hs056yQKej/T9on3Z/8f3kEJmRfcdfSnVxwWJyZbDV2lM4M6NJquGBXcyf/QpU3W
2KhISzSeqCI3pEwmkoen5IfqD5ZemYxse2FuP6MVQoZVvrbH9ProAaWZ3DuOxu414Z3D0UjrdFt8
823S8MLZyivBlbVu/5XEgvwyRYrwX+KdshR1Sw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MIlcOxbbFuYAuGOjTR5T+J3srLvuO8OEWUb5EN2s3ucxWo80Gn2QZggebQKC5pYj6sLppCwudLDV
cdqfX9KBvQtHkkSgj8aqVuJJN7rYBzmGDlibrUPJVkDVvRZ85CN2EH+9gbp1V8eLR4g3vPvJSJS3
71afQJfeRO0iX2gt4IE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Fp6Uhu2a02nqflyhMvH8oj0IYd9pTqoMCSRb1p+GUwtPkmJbfMsXRVcCKC40mgD/Wkj8Z5V8eLXS
HCU/6hqqfM/0xokNMCxQGOW8yvROxuVkt8YUml7fm0Cs0UHaAQLheW2rikLn43XQjQc/Zn/9jSac
Rc5GmhxKQ66ADM4gjqTYtNH4aN5KxZ6Xq7+GQfYPT1G3YQCyCmQOO4ggoGumW8/QFLhxe/X6+Plo
TVdOJIyx5Xa2TC0jH7A1zAo0rDUsgkkcEQZnrQ4p32W+8wuvWYrTPUnbZiQkBftFhpavuPyBQ0Pc
TxJXY/KHBe8uimmGBRd++t1lAlrftMYRi/FAGQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
ZHyqMQFkFijxELUyV+w5NMv1U3wBwAEo80aTrxTML36naBC6m1PL3qLB9GLPcG9fE3ECx5V5TigZ
QMKAlt4Dz/OntpGG5NmTg8JpH29YXw7zvZxhHRvgOCcO9iHMb0LWIueuQ+ZnJbcotwdrmjafFI0M
C2cIJ4sbH6kIEuoh3vw662LW2ZyT721nr5S2IneEi73A0X2WKiKtgkpNJghUMfK4farz4OW0Io/a
V+c/6t7GtTqCuA/B/a1hMBXgk9yKCCB2WA8YOCYdA3Kt1coAv3PpESDYr5oTkTtdK7zlTMh+E/TP
NwXDlSlN1FLfsUre0H9oltsSLu37ecFHNocLJi2XrvQcogDWj+NOaH5wM4UKZtKqz/dTh8e/upkq
W7uJGqbgiHxtXkr87xMS462OY3WHsv8pR/ozLyF9k0wEABRazQN9DVOKEcpp1BUU7KF5yg8niPy+
1gyN81eyNgG5wKtdyxChTS1PxS9+ADaitWaL4XWlXt2D8CczYgHna6lIjbFOkHoAJDnsPMdxAliK
BhLhzln4sEwgk3l201XaOyWOQgGGMS7wteQtditvOxu4fC3VQLLpl05ozhHdJc8Jor1fQ5b7k4BW
lqm2QDlq9/BdlDZ94NDvgFxJ9N+c1SWSb3jFkMF7TT0wII4KbRF1vIwb9u1Oj6708VaFnF9gMv7B
T+499nYqBC1sW4dHr1iajEm4Ls0P7Zw5yBHj9peGVojXeJrx+dVWgijbfk8y4ekm9kQusGdFtd+x
2vzKcVqHFEN5C94obFoN3RWy+jU1K51XKat4fLOmaYGmivlkMrCYlfj9yZAnLCEgOsjfQqctA339
W9ZNY4sdYQaDvN1yFF+SjpO3+PqdbfpnQUw/YPepcpo/oBHNwyGsVL+8/cKGGJ0YApDSntCg4EoH
og79SR2bJOCGl+ot8k9oKYQ7a2rlOrJqKoJ0KZq95HNmx1fElnXfHYa3zvgzvyyCAg6ljLzXqbl2
YArKErDUYFWRlKjAMIFIVKXVIxslpGjqTID70SbVEXoY1XienLHnEIB7gQVFPKjSAfcat7B0T0E/
ZA61NlODZPnVZ2WcT6HfnCVkyV9JVVmBZwz92n+EkZ1svbyi3XCK6SbjIwvcrgm6+Pn1328K4oOV
+rIi0S7bDuJ4tLjirzCb1TfpDSAnJr4QGDrXg+YY3luo2yFhDcFxbInSSVg+vQTdpgwiE1sRB7Ye
sEPn9RHOjg1JfwWe+4es8Xzj1MXXEk9IFeWu/2PIYR1vU4HXvIOHS1/nOXJSX/dHdISJSkzGW5Qs
1REDXn/fN9r7C9psxSSiY+TPs7GKfqWxGdPQlatKbEq6KZwKdm9fbYYY1yKmboSOgMmGVlEovAk1
0BEDhiJWmJ2EzAlEioEcHowdlmUZqJbW7vuDcnwLjx3JIh798QNjAtVGVzfglEeKXJnIVWwMbh/l
d4wjnWoCa2YuMsvmELSWxEvuyDI5w+ZVqp5gblpBom09XFgXHceZOB3wKV+mPe3VGu13/q59/uBn
y9btXrCpmKCGGrcutmJhlgdOtJXnwxia+EXbuvzrwakSgnSd9c7FSlnvq66GwkjLx2fWr01OytLs
Iom6sFMbHiNyCTTCqBcyi0kD5rUs/nTR+gRR9nhmvi62mOr7ZJQ0PEMWCD0av/AmBL/kLNXPdMqk
J2CuiicMXW6Ri+vzmAxtF22LZyouX2dkVB1KEvKIntkH39PC5eAtfqF1mWomao00XzC5DX9D1OCB
27qmqQQ4lku9CxpFLkpVx99hTxOSyRCTd0Yp0Mbi7QAM0GGw+3alQ3y8OhZnE8iDyrunM8q5IdM7
TVIR27sW+9dV/qDBaflG5uWp3CY+DNOVXXwxymADWptnFsGkLg13MiF3ei7MBbRsWzn/jjxTqddS
L5ufM42yhTUgaoC13cidiY9HdRRd+aRUSrfGz9Plgz7vjVauIxt6mbQnOiyUx+H3GtA0Inhift1c
N6BHTVXgaWNhG0LtiQfdo3nrcjV3NdDeqg/lgdEcMSLDt6gKjspIdpSMbssBV+YJiDSkawbPEAXZ
oxc9tMkVAkuDbWromf4BCI8YbeBgLEc1nwOsj/fvksk4YB3OtlZCiVSxqgi4w/YVN1wr0Vslw6IF
7xk6wtnYpOYRqIO/TsGecyydMCb9MMzNzuOwOPh7S5D2ceb5sujv5pt3Avjlk8eaTX4TNEWdbqso
4iTr6gbACRwlWd/UN7Kv02O5TN2p3E/f9ztLnkgGYrHLismGrwoQEUAtd9I8RS1S6KcdoC97Qu8b
vPr5Zdub5dhfLPZKtPx4Syh2vlb+fmLPIor0xZezBu9HAFPrfr+0bkFaDJ2i4iNfl34mtnotslkY
hyjf8FX6s97rT4IMUMNZBYFwGg1uA2iRNyxBtS71Lzl/c18sYP6kP1nWSAP2P52k8cyx4+e9NTJb
W4BKDt+nSdiZAFCJzrJDHzDvGO++MgST7LvARdVTdarb3cc6u0UALrO8Po4UZFSqgDxTA1p4JCWp
FPlgFSaZ447T/0CiDvWZd/OEtDMXMa1oYb6lcGFmUKemVphjqHsgzM6Kix2ZEJrKqIuwhSFCXL+s
pjURajGfF8j42bPMTD4cjJaSxKlajTAiuPPV8p6GpeWrPM2VrZiTSDigxbQri1L7YQ3bes0luTrW
9lbHFSH220rETEKNq69fbfWPXpjrNqxMrhjx3d8Ye/QsxCbiZnv0kAANnz8ghFIEr5nJ/rPdtaM6
f26h4k8s2u+9k+hbwBMAhirpkrNARQBaXZmcSf+6D1c4cu2LfABjpndXVpCj1jGbdQ0R/+Z54OfY
88Al6JXNnfOrS6IRTAzw0K8OzJISKLNAP2TAA8aU7o9a+0LScWqua/c1ATlt7RR4trk6dlp8Rwd0
cgOpx6exzK4S90Lj2GTjTfPS+l+aZA2ZSS4t5vH02MHpWyX/A3PcQ3witevcdhKVKCzvdZhqSEKV
aC0HTvLm0NE5HryulbcDKqAhNnTTmD2Y8R1XUvevx7ncBCQqkYvorxLZy4Kz1Fp6mTRU4akiBM+i
sVEc6eMwAyQp4w+3d0B6/gJaDERUVxFpO5JMPF2rEPuSwGrZMZfiIFsYA+h7x7X2/+QiIoY4FcTM
uXjSBcjHGzLW4nXbFXl88ISnhccbIWLHarGErT4DuZWs0sdMuTJWclNrZURZ1MqOFV5iHsek37a1
VCIBhBTHPdoz4BwcFlA4fFnlFvSzhoESghcvIQg/4D0DVmSog+Ws8SF7yLhTfbZ9ZEVRsvXhaXFo
OmyaWD23vgQUsTzISAZZrs0y1bH0Htoiyj6u+T2y0zcPkvzmEReDyEy0kr8YGSRxdNlbTkrzdyZ6
lddZQ4zGXTXbTd4NHrkmA7I2Lz43EUe0++neTDStW790/HeKFGUsEF+93itxHw1lErKGKoSzlGfp
e5oNOrdJDyNt19naE66ORINaFMfp5QoDzdONPBAjlQBPITNdJkUgmnnntjaORK+B0XrEA30jF8XX
ru+EJXq59ULhUMHcVsmRB5YofnuzsY4XIcna0PdkRTMiUJiV6ndstvQ6YL50XqctnpSpBevWqMHt
KAkN7xN+L8Txpk+DGkCYcoohyYgDIGQxkG912jdrwafMLMjyViqXzyK5093I3dsuUyItr4wNekGW
63va03ioJHX33jptDWmYHK5iL7l7xzFb/ljQCdhVyhw+BZm93+FhVkHd/Xgtokwy+6/sQgS7ynBm
6tDpLJC2qLug5/WgOH/G1hV+2+KTW7EuFbSqwuMs4AySDkE43RS8xtypMaKb972Dmsq8QUanlqQZ
Q+Ngx8ZCTMQPI0xoSxfruSidVavLJIQcSQdnUgsqXAUBKDUvjHuXQKDDrJBckLXOS7zEV29emuY/
W5LobOf56VLImsj7M66eAlWtHRlv9eBPgTKtwmFSt4NePTSGs8AbPsmiTOxI1PUc/3xwYgfcepAu
W8rKjorBIN9mDKwQRxCbFXkmY1OclejTRvv47hih30UrKsGtOn7whbmppVWU0tDLCqdxEjuwuXgJ
hii4PfEJUZNpiUjRwOvGF2IFsx4b16lQKfM74Prux6GMMIh48aFa2HYFIhXLbvL1Khc0NNucj4+E
s/p/6IdCgLzdSPngX7ze0gNWIoQcAZv9HaJx6R3UCIs+IAchinZoA3iECJShH+LrygLPQSjzBV+D
A8qgFRRbASFHVouqtTO5YvCYVSpQP+NqYOfJ7vIZe4DV8R5ZDGwqwJPAYoW5uV70fd9D4N09AyCS
f3PM4ZJVknTltLb+IHr62QKlnSWby8dZoMt3FGoQuXt2+6M+V19AhF7gi+KwbSCs37bqvhJOR6me
5PMDkVuNmxhfAInMHtsdY/tQ0xOOmqGhdJ2jIsSJjIP11lroWGd5I7AYFVH/cjHOYNn0mCT4VFH0
q/3efEVlaJWNRUF/TbcQHDpvbeZwlBgLZHip4+5532lA/eLNx5rXXYG7SCDElLWUxUy2Q8qI/yy0
49+dEEa5Nkabim7slOxs56zOPvaIf5XGT3DhWucwHZJE4S3K6fu8rdzcSAc72x9T2HT9nHQysiGX
n6gjfUgKpfNB9OgYQqRAwiQo+KzhXc748iHdCB/+HRwovBgDN1plEPFSallSJ334Edpnt68c4x/W
AAeKcfqoBg6MvTHHHYTZJEYBND1mQmwRIW4bnxVSIFvhAN+AT9D1vTP8gKQDxLkncJJ0+p3416lF
pbPG+I3fbj/kpVWWR13h38pdDnX5K0D4ybzrmHMB1RBdeENF+n3rvUvVP7cdxtzjacjDGOsq0EW8
b9Uu6TJXSNnVgQWM6CT8tpAM7zYLSWRs+fQdKa/+CA/vVIJk8v4qH8+Bfkb7OvFUi2XBM46dQY3Z
px3y9qt686XLD8xK+tTVNvcD6D2WKhga+pbfJiOd+sbCr9wlYYAX3a+561tqA5fIcPRWN3p7OcIx
9ua7qIx3s21HCJpx8YmEb59c+JyPPHOx1b70AZ337lAohuNvKvbH1V7kFtgQLPZBfGB5w8FdtiGu
PlbxYR89Oc0TCsE5SlE7LlWCYXlq3IWRbGLIIJWiU36aqYxyAjTFG8usPNmCA/hSlFfctaWhmnqh
3/LfEQHg6wyvj7LT2+JGc4iPBiL3ttBy6k1ubs/wvpcoHnCH88TK+1zBNQS4btoExYH9GT1FMhkt
2VcL2uGksQ/4epIY5rxMQSdNkoh8bBuQWXIeLXFZaLsNb+vlZJLgc7NRLsNGB4SwyYA7C9XlgOf6
Vk+0w1wB3ArQVEW9DU055auEXZceQ5NdWHMXqx073wmgm2u4eSMdWRT0X6fZ5p2fQh1iXDLMWAO8
4PjWBfITloHISmXpVmi+MOPRcjTrc6GoETyxd01Q3wh+J3l98Lx8Ii+m
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2014"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
YZt9CVgibtz1DQhIVW75t8+TB5qXvdexZipIOzyeYIgjhSC9SRzqg6fjPwWu35j8chcIzAAacfEy
N/Vp17OxkA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
D7G+voNCt8FsDi3lN0+coq3b3FkjH/LNdyhooKGcm3s/eZ0sVak/m4rW+ojrElXDbYRXuatPl+SX
Lc1hLK2VdyLMqWXRcyLZyKsDq3V3C2FXvr5eig5UHiNy5w2di7di+f5wfWbkObli4928VyEp9aR7
YQv27whektGwcfV9U18=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2014_03", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
GF3K08+YYqBd2ub6UE9jZ/5bHRPiZ2QgQMvQCsD8RURUNmL83Jq90ui2eflqe4TOcGuC6wPXCjM3
H8PpXsD/hHmC+6FkQQ7UoicI06j9/DKap9niHRPf65xpNEe9bPUMBhd/IQntjOiGUmc89fIsGQSZ
RkcPZ5XwMdP4hs056yQKej/T9on3Z/8f3kEJmRfcdfSnVxwWJyZbDV2lM4M6NJquGBXcyf/QpU3W
2KhISzSeqCI3pEwmkoen5IfqD5ZemYxse2FuP6MVQoZVvrbH9ProAaWZ3DuOxu414Z3D0UjrdFt8
823S8MLZyivBlbVu/5XEgvwyRYrwX+KdshR1Sw==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
MIlcOxbbFuYAuGOjTR5T+J3srLvuO8OEWUb5EN2s3ucxWo80Gn2QZggebQKC5pYj6sLppCwudLDV
cdqfX9KBvQtHkkSgj8aqVuJJN7rYBzmGDlibrUPJVkDVvRZ85CN2EH+9gbp1V8eLR4g3vPvJSJS3
71afQJfeRO0iX2gt4IE=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
Fp6Uhu2a02nqflyhMvH8oj0IYd9pTqoMCSRb1p+GUwtPkmJbfMsXRVcCKC40mgD/Wkj8Z5V8eLXS
HCU/6hqqfM/0xokNMCxQGOW8yvROxuVkt8YUml7fm0Cs0UHaAQLheW2rikLn43XQjQc/Zn/9jSac
Rc5GmhxKQ66ADM4gjqTYtNH4aN5KxZ6Xq7+GQfYPT1G3YQCyCmQOO4ggoGumW8/QFLhxe/X6+Plo
TVdOJIyx5Xa2TC0jH7A1zAo0rDUsgkkcEQZnrQ4p32W+8wuvWYrTPUnbZiQkBftFhpavuPyBQ0Pc
TxJXY/KHBe8uimmGBRd++t1lAlrftMYRi/FAGQ==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 4032)
`protect data_block
ZHyqMQFkFijxELUyV+w5NMv1U3wBwAEo80aTrxTML36naBC6m1PL3qLB9GLPcG9fE3ECx5V5TigZ
QMKAlt4Dz/OntpGG5NmTg8JpH29YXw7zvZxhHRvgOCcO9iHMb0LWIueuQ+ZnJbcotwdrmjafFI0M
C2cIJ4sbH6kIEuoh3vw662LW2ZyT721nr5S2IneEi73A0X2WKiKtgkpNJghUMfK4farz4OW0Io/a
V+c/6t7GtTqCuA/B/a1hMBXgk9yKCCB2WA8YOCYdA3Kt1coAv3PpESDYr5oTkTtdK7zlTMh+E/TP
NwXDlSlN1FLfsUre0H9oltsSLu37ecFHNocLJi2XrvQcogDWj+NOaH5wM4UKZtKqz/dTh8e/upkq
W7uJGqbgiHxtXkr87xMS462OY3WHsv8pR/ozLyF9k0wEABRazQN9DVOKEcpp1BUU7KF5yg8niPy+
1gyN81eyNgG5wKtdyxChTS1PxS9+ADaitWaL4XWlXt2D8CczYgHna6lIjbFOkHoAJDnsPMdxAliK
BhLhzln4sEwgk3l201XaOyWOQgGGMS7wteQtditvOxu4fC3VQLLpl05ozhHdJc8Jor1fQ5b7k4BW
lqm2QDlq9/BdlDZ94NDvgFxJ9N+c1SWSb3jFkMF7TT0wII4KbRF1vIwb9u1Oj6708VaFnF9gMv7B
T+499nYqBC1sW4dHr1iajEm4Ls0P7Zw5yBHj9peGVojXeJrx+dVWgijbfk8y4ekm9kQusGdFtd+x
2vzKcVqHFEN5C94obFoN3RWy+jU1K51XKat4fLOmaYGmivlkMrCYlfj9yZAnLCEgOsjfQqctA339
W9ZNY4sdYQaDvN1yFF+SjpO3+PqdbfpnQUw/YPepcpo/oBHNwyGsVL+8/cKGGJ0YApDSntCg4EoH
og79SR2bJOCGl+ot8k9oKYQ7a2rlOrJqKoJ0KZq95HNmx1fElnXfHYa3zvgzvyyCAg6ljLzXqbl2
YArKErDUYFWRlKjAMIFIVKXVIxslpGjqTID70SbVEXoY1XienLHnEIB7gQVFPKjSAfcat7B0T0E/
ZA61NlODZPnVZ2WcT6HfnCVkyV9JVVmBZwz92n+EkZ1svbyi3XCK6SbjIwvcrgm6+Pn1328K4oOV
+rIi0S7bDuJ4tLjirzCb1TfpDSAnJr4QGDrXg+YY3luo2yFhDcFxbInSSVg+vQTdpgwiE1sRB7Ye
sEPn9RHOjg1JfwWe+4es8Xzj1MXXEk9IFeWu/2PIYR1vU4HXvIOHS1/nOXJSX/dHdISJSkzGW5Qs
1REDXn/fN9r7C9psxSSiY+TPs7GKfqWxGdPQlatKbEq6KZwKdm9fbYYY1yKmboSOgMmGVlEovAk1
0BEDhiJWmJ2EzAlEioEcHowdlmUZqJbW7vuDcnwLjx3JIh798QNjAtVGVzfglEeKXJnIVWwMbh/l
d4wjnWoCa2YuMsvmELSWxEvuyDI5w+ZVqp5gblpBom09XFgXHceZOB3wKV+mPe3VGu13/q59/uBn
y9btXrCpmKCGGrcutmJhlgdOtJXnwxia+EXbuvzrwakSgnSd9c7FSlnvq66GwkjLx2fWr01OytLs
Iom6sFMbHiNyCTTCqBcyi0kD5rUs/nTR+gRR9nhmvi62mOr7ZJQ0PEMWCD0av/AmBL/kLNXPdMqk
J2CuiicMXW6Ri+vzmAxtF22LZyouX2dkVB1KEvKIntkH39PC5eAtfqF1mWomao00XzC5DX9D1OCB
27qmqQQ4lku9CxpFLkpVx99hTxOSyRCTd0Yp0Mbi7QAM0GGw+3alQ3y8OhZnE8iDyrunM8q5IdM7
TVIR27sW+9dV/qDBaflG5uWp3CY+DNOVXXwxymADWptnFsGkLg13MiF3ei7MBbRsWzn/jjxTqddS
L5ufM42yhTUgaoC13cidiY9HdRRd+aRUSrfGz9Plgz7vjVauIxt6mbQnOiyUx+H3GtA0Inhift1c
N6BHTVXgaWNhG0LtiQfdo3nrcjV3NdDeqg/lgdEcMSLDt6gKjspIdpSMbssBV+YJiDSkawbPEAXZ
oxc9tMkVAkuDbWromf4BCI8YbeBgLEc1nwOsj/fvksk4YB3OtlZCiVSxqgi4w/YVN1wr0Vslw6IF
7xk6wtnYpOYRqIO/TsGecyydMCb9MMzNzuOwOPh7S5D2ceb5sujv5pt3Avjlk8eaTX4TNEWdbqso
4iTr6gbACRwlWd/UN7Kv02O5TN2p3E/f9ztLnkgGYrHLismGrwoQEUAtd9I8RS1S6KcdoC97Qu8b
vPr5Zdub5dhfLPZKtPx4Syh2vlb+fmLPIor0xZezBu9HAFPrfr+0bkFaDJ2i4iNfl34mtnotslkY
hyjf8FX6s97rT4IMUMNZBYFwGg1uA2iRNyxBtS71Lzl/c18sYP6kP1nWSAP2P52k8cyx4+e9NTJb
W4BKDt+nSdiZAFCJzrJDHzDvGO++MgST7LvARdVTdarb3cc6u0UALrO8Po4UZFSqgDxTA1p4JCWp
FPlgFSaZ447T/0CiDvWZd/OEtDMXMa1oYb6lcGFmUKemVphjqHsgzM6Kix2ZEJrKqIuwhSFCXL+s
pjURajGfF8j42bPMTD4cjJaSxKlajTAiuPPV8p6GpeWrPM2VrZiTSDigxbQri1L7YQ3bes0luTrW
9lbHFSH220rETEKNq69fbfWPXpjrNqxMrhjx3d8Ye/QsxCbiZnv0kAANnz8ghFIEr5nJ/rPdtaM6
f26h4k8s2u+9k+hbwBMAhirpkrNARQBaXZmcSf+6D1c4cu2LfABjpndXVpCj1jGbdQ0R/+Z54OfY
88Al6JXNnfOrS6IRTAzw0K8OzJISKLNAP2TAA8aU7o9a+0LScWqua/c1ATlt7RR4trk6dlp8Rwd0
cgOpx6exzK4S90Lj2GTjTfPS+l+aZA2ZSS4t5vH02MHpWyX/A3PcQ3witevcdhKVKCzvdZhqSEKV
aC0HTvLm0NE5HryulbcDKqAhNnTTmD2Y8R1XUvevx7ncBCQqkYvorxLZy4Kz1Fp6mTRU4akiBM+i
sVEc6eMwAyQp4w+3d0B6/gJaDERUVxFpO5JMPF2rEPuSwGrZMZfiIFsYA+h7x7X2/+QiIoY4FcTM
uXjSBcjHGzLW4nXbFXl88ISnhccbIWLHarGErT4DuZWs0sdMuTJWclNrZURZ1MqOFV5iHsek37a1
VCIBhBTHPdoz4BwcFlA4fFnlFvSzhoESghcvIQg/4D0DVmSog+Ws8SF7yLhTfbZ9ZEVRsvXhaXFo
OmyaWD23vgQUsTzISAZZrs0y1bH0Htoiyj6u+T2y0zcPkvzmEReDyEy0kr8YGSRxdNlbTkrzdyZ6
lddZQ4zGXTXbTd4NHrkmA7I2Lz43EUe0++neTDStW790/HeKFGUsEF+93itxHw1lErKGKoSzlGfp
e5oNOrdJDyNt19naE66ORINaFMfp5QoDzdONPBAjlQBPITNdJkUgmnnntjaORK+B0XrEA30jF8XX
ru+EJXq59ULhUMHcVsmRB5YofnuzsY4XIcna0PdkRTMiUJiV6ndstvQ6YL50XqctnpSpBevWqMHt
KAkN7xN+L8Txpk+DGkCYcoohyYgDIGQxkG912jdrwafMLMjyViqXzyK5093I3dsuUyItr4wNekGW
63va03ioJHX33jptDWmYHK5iL7l7xzFb/ljQCdhVyhw+BZm93+FhVkHd/Xgtokwy+6/sQgS7ynBm
6tDpLJC2qLug5/WgOH/G1hV+2+KTW7EuFbSqwuMs4AySDkE43RS8xtypMaKb972Dmsq8QUanlqQZ
Q+Ngx8ZCTMQPI0xoSxfruSidVavLJIQcSQdnUgsqXAUBKDUvjHuXQKDDrJBckLXOS7zEV29emuY/
W5LobOf56VLImsj7M66eAlWtHRlv9eBPgTKtwmFSt4NePTSGs8AbPsmiTOxI1PUc/3xwYgfcepAu
W8rKjorBIN9mDKwQRxCbFXkmY1OclejTRvv47hih30UrKsGtOn7whbmppVWU0tDLCqdxEjuwuXgJ
hii4PfEJUZNpiUjRwOvGF2IFsx4b16lQKfM74Prux6GMMIh48aFa2HYFIhXLbvL1Khc0NNucj4+E
s/p/6IdCgLzdSPngX7ze0gNWIoQcAZv9HaJx6R3UCIs+IAchinZoA3iECJShH+LrygLPQSjzBV+D
A8qgFRRbASFHVouqtTO5YvCYVSpQP+NqYOfJ7vIZe4DV8R5ZDGwqwJPAYoW5uV70fd9D4N09AyCS
f3PM4ZJVknTltLb+IHr62QKlnSWby8dZoMt3FGoQuXt2+6M+V19AhF7gi+KwbSCs37bqvhJOR6me
5PMDkVuNmxhfAInMHtsdY/tQ0xOOmqGhdJ2jIsSJjIP11lroWGd5I7AYFVH/cjHOYNn0mCT4VFH0
q/3efEVlaJWNRUF/TbcQHDpvbeZwlBgLZHip4+5532lA/eLNx5rXXYG7SCDElLWUxUy2Q8qI/yy0
49+dEEa5Nkabim7slOxs56zOPvaIf5XGT3DhWucwHZJE4S3K6fu8rdzcSAc72x9T2HT9nHQysiGX
n6gjfUgKpfNB9OgYQqRAwiQo+KzhXc748iHdCB/+HRwovBgDN1plEPFSallSJ334Edpnt68c4x/W
AAeKcfqoBg6MvTHHHYTZJEYBND1mQmwRIW4bnxVSIFvhAN+AT9D1vTP8gKQDxLkncJJ0+p3416lF
pbPG+I3fbj/kpVWWR13h38pdDnX5K0D4ybzrmHMB1RBdeENF+n3rvUvVP7cdxtzjacjDGOsq0EW8
b9Uu6TJXSNnVgQWM6CT8tpAM7zYLSWRs+fQdKa/+CA/vVIJk8v4qH8+Bfkb7OvFUi2XBM46dQY3Z
px3y9qt686XLD8xK+tTVNvcD6D2WKhga+pbfJiOd+sbCr9wlYYAX3a+561tqA5fIcPRWN3p7OcIx
9ua7qIx3s21HCJpx8YmEb59c+JyPPHOx1b70AZ337lAohuNvKvbH1V7kFtgQLPZBfGB5w8FdtiGu
PlbxYR89Oc0TCsE5SlE7LlWCYXlq3IWRbGLIIJWiU36aqYxyAjTFG8usPNmCA/hSlFfctaWhmnqh
3/LfEQHg6wyvj7LT2+JGc4iPBiL3ttBy6k1ubs/wvpcoHnCH88TK+1zBNQS4btoExYH9GT1FMhkt
2VcL2uGksQ/4epIY5rxMQSdNkoh8bBuQWXIeLXFZaLsNb+vlZJLgc7NRLsNGB4SwyYA7C9XlgOf6
Vk+0w1wB3ArQVEW9DU055auEXZceQ5NdWHMXqx073wmgm2u4eSMdWRT0X6fZ5p2fQh1iXDLMWAO8
4PjWBfITloHISmXpVmi+MOPRcjTrc6GoETyxd01Q3wh+J3l98Lx8Ii+m
`protect end_protected
|
----------------------------------------------------------------------------------
-- Engineer: Mike Field <[email protected]>
--
-- Module Name: edid_decode - Behavioral
--
-- Description: Extract the default video timing and
-- modes from a stream of EDID data.
--
-- The Stream must end with EDID_addr of 0xFF so that the
-- checksum can be verified and valid asserted
----------------------------------------------------------------------------------
-- FPGA_DisplayPort from https://github.com/hamsternz/FPGA_DisplayPort
------------------------------------------------------------------------------------
-- The MIT License (MIT)
--
-- Copyright (c) 2015 Michael Alan Field <[email protected]>
--
-- Permission is hereby granted, free of charge, to any person obtaining a copy
-- of this software and associated documentation files (the "Software"), to deal
-- in the Software without restriction, including without limitation the rights
-- to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
-- copies of the Software, and to permit persons to whom the Software is
-- furnished to do so, subject to the following conditions:
--
-- The above copyright notice and this permission notice shall be included in
-- all copies or substantial portions of the Software.
--
-- THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
-- IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
-- FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
-- AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
-- LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
-- OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
-- THE SOFTWARE.
------------------------------------------------------------------------------------
----- Want to say thanks? ----------------------------------------------------------
------------------------------------------------------------------------------------
--
-- This design has taken many hours - 3 months of work. I'm more than happy
-- to share it if you can make use of it. It is released under the MIT license,
-- so you are not under any onus to say thanks, but....
--
-- If you what to say thanks for this design either drop me an email, or how about
-- trying PayPal to my email ([email protected])?
--
-- Educational use - Enough for a beer
-- Hobbyist use - Enough for a pizza
-- Research use - Enough to take the family out to dinner
-- Commercial use - A weeks pay for an engineer (I wish!)
--------------------------------------------------------------------------------------
-- Ver | Date | Change
--------+------------+---------------------------------------------------------------
-- 0.1 | 2015-09-17 | Initial Version
------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity edid_decode is
port ( clk : in std_logic;
edid_de : in std_logic;
edid_data : in std_logic_vector(7 downto 0);
edid_addr : in std_logic_vector(7 downto 0);
invalidate : in std_logic;
valid : out std_logic := '0';
support_RGB444 : out std_logic := '0';
support_YCC444 : out std_logic := '0';
support_YCC422 : out std_logic := '0';
pixel_clock_x10k : out std_logic_vector(15 downto 0) := (others => '0');
h_visible_len : out std_logic_vector(11 downto 0) := (others => '0');
h_blank_len : out std_logic_vector(11 downto 0) := (others => '0');
h_front_len : out std_logic_vector(11 downto 0) := (others => '0');
h_sync_len : out std_logic_vector(11 downto 0) := (others => '0');
v_visible_len : out std_logic_vector(11 downto 0) := (others => '0');
v_blank_len : out std_logic_vector(11 downto 0) := (others => '0');
v_front_len : out std_logic_vector(11 downto 0) := (others => '0');
v_sync_len : out std_logic_vector(11 downto 0) := (others => '0');
interlaced : out std_logic := '0');
end edid_decode;
architecture arch of edid_decode is
signal checksum : unsigned(7 downto 0);
signal checksum_next : unsigned(7 downto 0);
begin
checksum_next <= checksum + unsigned(edid_data);
clk_proc: process(clk)
begin
if rising_edge(clk) then
if edid_de = '1' then
checksum <= checksum_next;
valid <= '0';
case edid_addr is
when x"00" => -- reset the checksum
checksum <= unsigned(edid_data);
when x"18" => -- Colour modes supported
support_rgb444 <= '1';
support_ycc444 <= edid_data(3);
support_ycc422 <= edid_data(4);
-- Timing 0 - 1
when x"36" => pixel_clock_x10k( 7 downto 0) <= edid_data;
when x"37" => pixel_clock_x10k(15 downto 8) <= edid_data;
-- Timing 2 - 4
when x"38" => h_visible_len( 7 downto 0) <= edid_data;
when x"39" => h_blank_len(7 downto 0) <= edid_data;
when x"3A" => h_visible_len(11 downto 8) <= edid_data(7 downto 4);
h_blank_len(11 downto 8) <= edid_data(3 downto 0);
-- Timing 5 - 7
when x"3B" => v_visible_len( 7 downto 0) <= edid_data;
when x"3C" => v_blank_len(7 downto 0) <= edid_data;
when x"3D" => v_visible_len(11 downto 8) <= edid_data(7 downto 4);
v_blank_len(11 downto 8) <= edid_data(3 downto 0);
-- Timing 8 - 11
when x"3E" => h_front_len( 7 downto 0) <= edid_data;
when x"3F" => h_sync_len( 7 downto 0) <= edid_data;
when x"40" => v_front_len( 3 downto 0) <= edid_data(7 downto 4);
v_sync_len( 3 downto 0) <= edid_data(3 downto 0);
when x"41" => h_front_len( 9 downto 8) <= edid_data(7 downto 6);
h_sync_len( 9 downto 8) <= edid_data(5 downto 4);
v_front_len( 5 downto 4) <= edid_data(3 downto 2);
v_sync_len( 5 downto 4) <= edid_data(1 downto 0);
-- Timing 11-16 not used - that is the physical
-- size and boarder.
when x"7F" => if checksum_next = x"00" then
valid <= '1';
end if;
when others => NULL;
end case;
------------------------------------------------
-- Allow for an external event to invalidate the
-- outputs (e.g. hot plug)
------------------------------------------------
if invalidate = '1' then
valid <= '0';
end if;
end if;
end if;
end process;
end architecture;
|
-- -------------------------------------------------------------
--
-- Generated Architecture Declaration for rtl of a_clk
--
-- Generated
-- by: wig
-- on: Mon Jul 18 15:56:34 2005
-- cmd: h:/work/eclipse/mix/mix_0.pl -strip -nodelta ../../padio.xls
--
-- !!! Do not edit this file! Autogenerated by MIX !!!
-- $Author: wig $
-- $Id: a_clk-rtl-a.vhd,v 1.3 2005/07/19 07:13:11 wig Exp $
-- $Date: 2005/07/19 07:13:11 $
-- $Log: a_clk-rtl-a.vhd,v $
-- Revision 1.3 2005/07/19 07:13:11 wig
-- Update testcases. Added highlow/nolowbus
--
--
-- Based on Mix Architecture Template built into RCSfile: MixWriter.pm,v
-- Id: MixWriter.pm,v 1.57 2005/07/18 08:58:22 wig Exp
--
-- Generator: mix_0.pl Revision: 1.36 , [email protected]
-- (C) 2003 Micronas GmbH
--
-- --------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
-- No project specific VHDL libraries/arch
--
--
-- Start of Generated Architecture rtl of a_clk
--
architecture rtl of a_clk is
-- Generated Constant Declarations
--
-- Components
--
-- Generated Components
component a_fsm --
-- No Generated Generics
port (
-- Generated Port for Entity a_fsm
alarm_button : in std_ulogic;
clk : in std_ulogic;
d9_core_di : in std_ulogic_vector(1 downto 0);
d9_core_en : in std_ulogic_vector(1 downto 0);
d9_core_pu : in std_ulogic_vector(1 downto 0);
data_core_do : out std_ulogic_vector(1 downto 0);
data_core_i33 : in std_ulogic_vector(7 downto 0);
data_core_i34 : in std_ulogic_vector(7 downto 0);
data_core_o35 : out std_ulogic_vector(7 downto 0);
data_core_o36 : out std_ulogic_vector(7 downto 0);
data_i1 : in std_ulogic_vector(7 downto 0);
data_o1 : out std_ulogic_vector(7 downto 0);
di : in std_ulogic_vector(7 downto 0);
di2 : in std_ulogic_vector(8 downto 0);
disp2_en : in std_ulogic_vector(7 downto 0);
disp_ls_port : out std_ulogic;
disp_ms_port : out std_ulogic;
iosel_bus : out std_ulogic_vector(7 downto 0);
iosel_bus_disp : out std_ulogic;
iosel_bus_ls_hr : out std_ulogic;
iosel_bus_ls_min : out std_ulogic;
iosel_bus_ms_hr : out std_ulogic;
iosel_bus_ms_min : out std_ulogic;
iosel_bus_nosel : out std_ulogic;
iosel_bus_port : out std_ulogic_vector(7 downto 0);
key : in std_ulogic_vector(3 downto 0);
load_new_a : out std_ulogic;
load_new_c : out std_ulogic;
one_second : in std_ulogic;
reset : in std_ulogic;
shift : out std_ulogic;
show_a : out std_ulogic;
show_new_time : out std_ulogic;
time_button : in std_ulogic
-- End of Generated Port for Entity a_fsm
);
end component;
-- ---------
component ios_e --
-- No Generated Generics
port (
-- Generated Port for Entity ios_e
p_mix_d9_di_go : out std_ulogic_vector(1 downto 0);
p_mix_d9_do_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_en_gi : in std_ulogic_vector(1 downto 0);
p_mix_d9_pu_gi : in std_ulogic_vector(1 downto 0);
p_mix_data_i1_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i33_go : out std_ulogic_vector(7 downto 0);
p_mix_data_i34_go : out std_ulogic_vector(7 downto 0);
p_mix_data_o1_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o35_gi : in std_ulogic_vector(7 downto 0);
p_mix_data_o36_gi : in std_ulogic_vector(7 downto 0);
p_mix_di2_1_0_go : out std_ulogic_vector(1 downto 0);
p_mix_di2_7_3_go : out std_ulogic_vector(4 downto 0);
p_mix_disp2_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_disp2_en_1_0_gi : in std_ulogic_vector(1 downto 0);
p_mix_disp2_en_7_3_gi : in std_ulogic_vector(4 downto 0);
p_mix_display_ls_en_gi : in std_ulogic;
p_mix_display_ls_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_en_gi : in std_ulogic;
p_mix_display_ms_hr_gi : in std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_gi : in std_ulogic_vector(6 downto 0);
p_mix_iosel_0_gi : in std_ulogic;
p_mix_iosel_1_gi : in std_ulogic;
p_mix_iosel_2_gi : in std_ulogic;
p_mix_iosel_3_gi : in std_ulogic;
p_mix_iosel_4_gi : in std_ulogic;
p_mix_iosel_5_gi : in std_ulogic;
p_mix_iosel_6_gi : in std_ulogic;
p_mix_iosel_7_gi : in std_ulogic;
p_mix_iosel_bus_gi : in std_ulogic_vector(7 downto 0);
p_mix_iosel_disp_gi : in std_ulogic;
p_mix_iosel_ls_hr_gi : in std_ulogic;
p_mix_iosel_ls_min_gi : in std_ulogic;
p_mix_iosel_ms_hr_gi : in std_ulogic;
p_mix_iosel_ms_min_gi : in std_ulogic;
p_mix_pad_di_12_gi : in std_ulogic;
p_mix_pad_di_13_gi : in std_ulogic;
p_mix_pad_di_14_gi : in std_ulogic;
p_mix_pad_di_15_gi : in std_ulogic;
p_mix_pad_di_16_gi : in std_ulogic;
p_mix_pad_di_17_gi : in std_ulogic;
p_mix_pad_di_18_gi : in std_ulogic;
p_mix_pad_di_1_gi : in std_ulogic;
p_mix_pad_di_31_gi : in std_ulogic;
p_mix_pad_di_32_gi : in std_ulogic;
p_mix_pad_di_33_gi : in std_ulogic;
p_mix_pad_di_34_gi : in std_ulogic;
p_mix_pad_di_39_gi : in std_ulogic;
p_mix_pad_di_40_gi : in std_ulogic;
p_mix_pad_do_12_go : out std_ulogic;
p_mix_pad_do_13_go : out std_ulogic;
p_mix_pad_do_14_go : out std_ulogic;
p_mix_pad_do_15_go : out std_ulogic;
p_mix_pad_do_16_go : out std_ulogic;
p_mix_pad_do_17_go : out std_ulogic;
p_mix_pad_do_18_go : out std_ulogic;
p_mix_pad_do_2_go : out std_ulogic;
p_mix_pad_do_31_go : out std_ulogic;
p_mix_pad_do_32_go : out std_ulogic;
p_mix_pad_do_35_go : out std_ulogic;
p_mix_pad_do_36_go : out std_ulogic;
p_mix_pad_do_39_go : out std_ulogic;
p_mix_pad_do_40_go : out std_ulogic;
p_mix_pad_en_12_go : out std_ulogic;
p_mix_pad_en_13_go : out std_ulogic;
p_mix_pad_en_14_go : out std_ulogic;
p_mix_pad_en_15_go : out std_ulogic;
p_mix_pad_en_16_go : out std_ulogic;
p_mix_pad_en_17_go : out std_ulogic;
p_mix_pad_en_18_go : out std_ulogic;
p_mix_pad_en_2_go : out std_ulogic;
p_mix_pad_en_31_go : out std_ulogic;
p_mix_pad_en_32_go : out std_ulogic;
p_mix_pad_en_35_go : out std_ulogic;
p_mix_pad_en_36_go : out std_ulogic;
p_mix_pad_en_39_go : out std_ulogic;
p_mix_pad_en_40_go : out std_ulogic;
p_mix_pad_pu_31_go : out std_ulogic;
p_mix_pad_pu_32_go : out std_ulogic
-- End of Generated Port for Entity ios_e
);
end component;
-- ---------
component pad_pads_e --
-- No Generated Generics
port (
-- Generated Port for Entity pad_pads_e
p_mix_pad_di_12_go : out std_ulogic;
p_mix_pad_di_13_go : out std_ulogic;
p_mix_pad_di_14_go : out std_ulogic;
p_mix_pad_di_15_go : out std_ulogic;
p_mix_pad_di_16_go : out std_ulogic;
p_mix_pad_di_17_go : out std_ulogic;
p_mix_pad_di_18_go : out std_ulogic;
p_mix_pad_di_1_go : out std_ulogic;
p_mix_pad_di_31_go : out std_ulogic;
p_mix_pad_di_32_go : out std_ulogic;
p_mix_pad_di_33_go : out std_ulogic;
p_mix_pad_di_34_go : out std_ulogic;
p_mix_pad_di_39_go : out std_ulogic;
p_mix_pad_di_40_go : out std_ulogic;
p_mix_pad_do_12_gi : in std_ulogic;
p_mix_pad_do_13_gi : in std_ulogic;
p_mix_pad_do_14_gi : in std_ulogic;
p_mix_pad_do_15_gi : in std_ulogic;
p_mix_pad_do_16_gi : in std_ulogic;
p_mix_pad_do_17_gi : in std_ulogic;
p_mix_pad_do_18_gi : in std_ulogic;
p_mix_pad_do_2_gi : in std_ulogic;
p_mix_pad_do_31_gi : in std_ulogic;
p_mix_pad_do_32_gi : in std_ulogic;
p_mix_pad_do_35_gi : in std_ulogic;
p_mix_pad_do_36_gi : in std_ulogic;
p_mix_pad_do_39_gi : in std_ulogic;
p_mix_pad_do_40_gi : in std_ulogic;
p_mix_pad_en_12_gi : in std_ulogic;
p_mix_pad_en_13_gi : in std_ulogic;
p_mix_pad_en_14_gi : in std_ulogic;
p_mix_pad_en_15_gi : in std_ulogic;
p_mix_pad_en_16_gi : in std_ulogic;
p_mix_pad_en_17_gi : in std_ulogic;
p_mix_pad_en_18_gi : in std_ulogic;
p_mix_pad_en_2_gi : in std_ulogic;
p_mix_pad_en_31_gi : in std_ulogic;
p_mix_pad_en_32_gi : in std_ulogic;
p_mix_pad_en_35_gi : in std_ulogic;
p_mix_pad_en_36_gi : in std_ulogic;
p_mix_pad_en_39_gi : in std_ulogic;
p_mix_pad_en_40_gi : in std_ulogic;
p_mix_pad_pu_31_gi : in std_ulogic;
p_mix_pad_pu_32_gi : in std_ulogic
-- End of Generated Port for Entity pad_pads_e
);
end component;
-- ---------
component testctrl_e --
-- No Generated Generics
-- No Generated Port
end component;
-- ---------
component alreg --
-- No Generated Generics
port (
-- Generated Port for Entity alreg
alarm_time : out std_ulogic_vector(3 downto 0);
load_new_a : in std_ulogic;
new_alarm_time : in std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity alreg
);
end component;
-- ---------
component count4 --
-- No Generated Generics
port (
-- Generated Port for Entity count4
current_time_ls_hr : out std_ulogic_vector(3 downto 0);
current_time_ls_min : out std_ulogic_vector(3 downto 0);
current_time_ms_hr : out std_ulogic_vector(3 downto 0);
current_time_ms_min : out std_ulogic_vector(3 downto 0);
load_new_c : in std_ulogic;
new_current_time_ls_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ls_min : in std_ulogic_vector(3 downto 0);
new_current_time_ms_hr : in std_ulogic_vector(3 downto 0);
new_current_time_ms_min : in std_ulogic_vector(3 downto 0);
one_minute : in std_ulogic
-- End of Generated Port for Entity count4
);
end component;
-- ---------
component ddrv4 --
-- No Generated Generics
port (
-- Generated Port for Entity ddrv4
alarm_time_ls_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ls_min : in std_ulogic_vector(3 downto 0);
alarm_time_ms_hr : in std_ulogic_vector(3 downto 0);
alarm_time_ms_min : in std_ulogic_vector(3 downto 0);
current_time_ls_hr : in std_ulogic_vector(3 downto 0);
current_time_ls_min : in std_ulogic_vector(3 downto 0);
current_time_ms_hr : in std_ulogic_vector(3 downto 0);
current_time_ms_min : in std_ulogic_vector(3 downto 0);
key_buffer_0 : in std_ulogic_vector(3 downto 0);
key_buffer_1 : in std_ulogic_vector(3 downto 0);
key_buffer_2 : in std_ulogic_vector(3 downto 0);
key_buffer_3 : in std_ulogic_vector(3 downto 0);
p_mix_display_ls_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ls_min_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_hr_go : out std_ulogic_vector(6 downto 0);
p_mix_display_ms_min_go : out std_ulogic_vector(6 downto 0);
p_mix_sound_alarm_go : out std_ulogic;
show_a : in std_ulogic;
show_new_time : in std_ulogic
-- End of Generated Port for Entity ddrv4
);
end component;
-- ---------
component keypad --
-- No Generated Generics
port (
-- Generated Port for Entity keypad
columns : in std_ulogic_vector(2 downto 0);
rows : out std_ulogic_vector(3 downto 0)
-- End of Generated Port for Entity keypad
);
end component;
-- ---------
component keyscan --
-- No Generated Generics
port (
-- Generated Port for Entity keyscan
alarm_button : out std_ulogic;
columns : out std_ulogic_vector(2 downto 0);
key : out std_ulogic_vector(3 downto 0);
key_buffer_0 : out std_ulogic_vector(3 downto 0);
key_buffer_1 : out std_ulogic_vector(3 downto 0);
key_buffer_2 : out std_ulogic_vector(3 downto 0);
key_buffer_3 : out std_ulogic_vector(3 downto 0);
rows : in std_ulogic_vector(3 downto 0);
shift : in std_ulogic;
time_button : out std_ulogic
-- End of Generated Port for Entity keyscan
);
end component;
-- ---------
component timegen --
-- No Generated Generics
port (
-- Generated Port for Entity timegen
one_minute : out std_ulogic;
one_second : out std_ulogic;
stopwatch : in std_ulogic
-- End of Generated Port for Entity timegen
);
end component;
-- ---------
--
-- Nets
--
--
-- Generated Signal List
--
signal alarm_button : std_ulogic;
signal s_int_alarm_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_alarm_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal columns : std_ulogic_vector(2 downto 0);
signal s_int_current_time_ls_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ls_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_hr : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_current_time_ms_min : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal d9_di : std_ulogic_vector(1 downto 0);
signal d9_do : std_ulogic_vector(1 downto 0);
signal d9_en : std_ulogic_vector(1 downto 0);
signal d9_pu : std_ulogic_vector(1 downto 0);
signal data_i1 : std_ulogic_vector(7 downto 0);
signal data_i33 : std_ulogic_vector(7 downto 0);
signal data_i34 : std_ulogic_vector(7 downto 0);
signal data_o1 : std_ulogic_vector(7 downto 0);
signal data_o35 : std_ulogic_vector(7 downto 0);
signal data_o36 : std_ulogic_vector(7 downto 0);
signal di2 : std_ulogic_vector(8 downto 0);
signal disp2 : std_ulogic_vector(7 downto 0);
signal disp2_en : std_ulogic_vector(7 downto 0);
signal display_ls_en : std_ulogic;
signal s_int_display_ls_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ls_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal display_ms_en : std_ulogic;
signal s_int_display_ms_hr : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_display_ms_min : std_ulogic_vector(6 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal iosel_0 : std_ulogic;
signal iosel_1 : std_ulogic;
signal iosel_2 : std_ulogic;
signal iosel_3 : std_ulogic;
signal iosel_4 : std_ulogic;
signal iosel_5 : std_ulogic;
signal iosel_6 : std_ulogic;
signal iosel_7 : std_ulogic;
signal iosel_bus : std_ulogic_vector(7 downto 0);
signal iosel_disp : std_ulogic;
signal iosel_ls_hr : std_ulogic;
signal iosel_ls_min : std_ulogic;
signal iosel_ms_hr : std_ulogic;
signal iosel_ms_min : std_ulogic;
-- __I_OUT_OPEN signal iosel_nosel : std_ulogic;
signal key : std_ulogic_vector(3 downto 0);
signal s_int_key_buffer_0 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_1 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_2 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_key_buffer_3 : std_ulogic_vector(3 downto 0); -- __W_PORT_SIGNAL_MAP_REQ
signal load_new_a : std_ulogic;
signal load_new_c : std_ulogic;
signal one_minute : std_ulogic;
signal one_sec_pulse : std_ulogic;
signal pad_di_1 : std_ulogic;
signal pad_di_12 : std_ulogic;
signal pad_di_13 : std_ulogic;
signal pad_di_14 : std_ulogic;
signal pad_di_15 : std_ulogic;
signal pad_di_16 : std_ulogic;
signal pad_di_17 : std_ulogic;
signal pad_di_18 : std_ulogic;
signal pad_di_31 : std_ulogic;
signal pad_di_32 : std_ulogic;
signal pad_di_33 : std_ulogic;
signal pad_di_34 : std_ulogic;
signal pad_di_39 : std_ulogic;
signal pad_di_40 : std_ulogic;
signal pad_do_12 : std_ulogic;
signal pad_do_13 : std_ulogic;
signal pad_do_14 : std_ulogic;
signal pad_do_15 : std_ulogic;
signal pad_do_16 : std_ulogic;
signal pad_do_17 : std_ulogic;
signal pad_do_18 : std_ulogic;
signal pad_do_2 : std_ulogic;
signal pad_do_31 : std_ulogic;
signal pad_do_32 : std_ulogic;
signal pad_do_35 : std_ulogic;
signal pad_do_36 : std_ulogic;
signal pad_do_39 : std_ulogic;
signal pad_do_40 : std_ulogic;
signal pad_en_12 : std_ulogic;
signal pad_en_13 : std_ulogic;
signal pad_en_14 : std_ulogic;
signal pad_en_15 : std_ulogic;
signal pad_en_16 : std_ulogic;
signal pad_en_17 : std_ulogic;
signal pad_en_18 : std_ulogic;
signal pad_en_2 : std_ulogic;
signal pad_en_31 : std_ulogic;
signal pad_en_32 : std_ulogic;
signal pad_en_35 : std_ulogic;
signal pad_en_36 : std_ulogic;
signal pad_en_39 : std_ulogic;
signal pad_en_40 : std_ulogic;
signal pad_pu_31 : std_ulogic;
signal pad_pu_32 : std_ulogic;
signal rows : std_ulogic_vector(3 downto 0);
signal shift : std_ulogic;
signal s_int_show_a : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal s_int_show_new_time : std_ulogic; -- __W_PORT_SIGNAL_MAP_REQ
signal time_button : std_ulogic;
--
-- End of Generated Signal List
--
begin
--
-- Generated Concurrent Statements
--
-- Generated Signal Assignments
s_int_alarm_time_ls_hr <= alarm_time_ls_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ls_min <= alarm_time_ls_min; -- __I_I_BUS_PORT
s_int_alarm_time_ms_hr <= alarm_time_ms_hr; -- __I_I_BUS_PORT
s_int_alarm_time_ms_min <= alarm_time_ms_min; -- __I_I_BUS_PORT
s_int_current_time_ls_hr <= current_time_ls_hr; -- __I_I_BUS_PORT
s_int_current_time_ls_min <= current_time_ls_min; -- __I_I_BUS_PORT
s_int_current_time_ms_hr <= current_time_ms_hr; -- __I_I_BUS_PORT
s_int_current_time_ms_min <= current_time_ms_min; -- __I_I_BUS_PORT
display_ls_hr <= s_int_display_ls_hr; -- __I_O_BUS_PORT
display_ls_min <= s_int_display_ls_min; -- __I_O_BUS_PORT
display_ms_hr <= s_int_display_ms_hr; -- __I_O_BUS_PORT
display_ms_min <= s_int_display_ms_min; -- __I_O_BUS_PORT
s_int_key_buffer_0 <= key_buffer_0; -- __I_I_BUS_PORT
s_int_key_buffer_1 <= key_buffer_1; -- __I_I_BUS_PORT
s_int_key_buffer_2 <= key_buffer_2; -- __I_I_BUS_PORT
s_int_key_buffer_3 <= key_buffer_3; -- __I_I_BUS_PORT
s_int_show_a <= show_a; -- __I_I_BIT_PORT
s_int_show_new_time <= show_new_time; -- __I_I_BIT_PORT
--
-- Generated Instances
--
-- Generated Instances and Port Mappings
-- Generated Instance Port Map for control
control: a_fsm
port map (
alarm_button => alarm_button,
clk => clk,
d9_core_di => d9_di, -- d9io
d9_core_en => d9_en, -- d9io
d9_core_pu => d9_pu, -- d9io
data_core_do => d9_do, -- d9io
data_core_i33 => data_i33, -- io data
data_core_i34 => data_i34, -- io data
data_core_o35 => data_o35, -- io data
data_core_o36 => data_o36, -- io data
data_i1 => data_i1, -- io data
data_o1 => data_o1, -- io data
di => disp2, -- io data
di2 => di2, -- io data
disp2_en => disp2_en, -- io data
disp_ls_port => display_ls_en, -- io_enable
disp_ms_port => display_ms_en, -- io_enable
iosel_bus(0) => iosel_0, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(1) => iosel_1, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(2) => iosel_2, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(3) => iosel_3, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(4) => iosel_4, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(5) => iosel_5, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(6) => iosel_6, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus(7) => iosel_7, -- __I_BIT_TO_BUSPORT -- IO_Select
iosel_bus_disp => iosel_disp, -- IO_Select
iosel_bus_ls_hr => iosel_ls_hr, -- IO_Select
iosel_bus_ls_min => iosel_ls_min, -- IO_Select
iosel_bus_ms_hr => iosel_ms_hr, -- IO_Select
iosel_bus_ms_min => iosel_ms_min, -- IO_Select
iosel_bus_nosel => open, -- IO_Select -- __I_OUT_OPEN
iosel_bus_port => iosel_bus, -- io data
key => key,
load_new_a => load_new_a,
load_new_c => load_new_c,
one_second => one_sec_pulse,
reset => reset,
shift => shift,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time,
time_button => time_button
);
-- End of Generated Instance Port Map for control
-- Generated Instance Port Map for ios
ios: ios_e
port map (
p_mix_d9_di_go => d9_di, -- d9io
p_mix_d9_do_gi => d9_do, -- d9io
p_mix_d9_en_gi => d9_en, -- d9io
p_mix_d9_pu_gi => d9_pu, -- d9io
p_mix_data_i1_go => data_i1, -- io data
p_mix_data_i33_go => data_i33, -- io data
p_mix_data_i34_go => data_i34, -- io data
p_mix_data_o1_gi => data_o1, -- io data
p_mix_data_o35_gi => data_o35, -- io data
p_mix_data_o36_gi => data_o36, -- io data
p_mix_di2_1_0_go => di2(1 downto 0), -- io data
p_mix_di2_7_3_go => di2(7 downto 3), -- io data
p_mix_disp2_1_0_gi => disp2(1 downto 0), -- io data
p_mix_disp2_7_3_gi => disp2(7 downto 3), -- io data
p_mix_disp2_en_1_0_gi => disp2_en(1 downto 0), -- io data
p_mix_disp2_en_7_3_gi => disp2_en(7 downto 3), -- io data
p_mix_display_ls_en_gi => display_ls_en, -- io_enable
p_mix_display_ls_hr_gi => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_gi => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_en_gi => display_ms_en, -- io_enable
p_mix_display_ms_hr_gi => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_gi => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_iosel_0_gi => iosel_0, -- IO_Select
p_mix_iosel_1_gi => iosel_1, -- IO_Select
p_mix_iosel_2_gi => iosel_2, -- IO_Select
p_mix_iosel_3_gi => iosel_3, -- IO_Select
p_mix_iosel_4_gi => iosel_4, -- IO_Select
p_mix_iosel_5_gi => iosel_5, -- IO_Select
p_mix_iosel_6_gi => iosel_6, -- IO_Select
p_mix_iosel_7_gi => iosel_7, -- IO_Select
p_mix_iosel_bus_gi => iosel_bus, -- io data
p_mix_iosel_disp_gi => iosel_disp, -- IO_Select
p_mix_iosel_ls_hr_gi => iosel_ls_hr, -- IO_Select
p_mix_iosel_ls_min_gi => iosel_ls_min, -- IO_Select
p_mix_iosel_ms_hr_gi => iosel_ms_hr, -- IO_Select
p_mix_iosel_ms_min_gi => iosel_ms_min, -- IO_Select
p_mix_pad_di_12_gi => pad_di_12, -- data in from pad
p_mix_pad_di_13_gi => pad_di_13, -- data in from pad
p_mix_pad_di_14_gi => pad_di_14, -- data in from pad
p_mix_pad_di_15_gi => pad_di_15, -- data in from pad
p_mix_pad_di_16_gi => pad_di_16, -- data in from pad
p_mix_pad_di_17_gi => pad_di_17, -- data in from pad
p_mix_pad_di_18_gi => pad_di_18, -- data in from pad
p_mix_pad_di_1_gi => pad_di_1, -- data in from pad
p_mix_pad_di_31_gi => pad_di_31, -- data in from pad
p_mix_pad_di_32_gi => pad_di_32, -- data in from pad
p_mix_pad_di_33_gi => pad_di_33, -- data in from pad
p_mix_pad_di_34_gi => pad_di_34, -- data in from pad
p_mix_pad_di_39_gi => pad_di_39, -- data in from pad
p_mix_pad_di_40_gi => pad_di_40, -- data in from pad
p_mix_pad_do_12_go => pad_do_12, -- data out to pad
p_mix_pad_do_13_go => pad_do_13, -- data out to pad
p_mix_pad_do_14_go => pad_do_14, -- data out to pad
p_mix_pad_do_15_go => pad_do_15, -- data out to pad
p_mix_pad_do_16_go => pad_do_16, -- data out to pad
p_mix_pad_do_17_go => pad_do_17, -- data out to pad
p_mix_pad_do_18_go => pad_do_18, -- data out to pad
p_mix_pad_do_2_go => pad_do_2, -- data out to pad
p_mix_pad_do_31_go => pad_do_31, -- data out to pad
p_mix_pad_do_32_go => pad_do_32, -- data out to pad
p_mix_pad_do_35_go => pad_do_35, -- data out to pad
p_mix_pad_do_36_go => pad_do_36, -- data out to pad
p_mix_pad_do_39_go => pad_do_39, -- data out to pad
p_mix_pad_do_40_go => pad_do_40, -- data out to pad
p_mix_pad_en_12_go => pad_en_12, -- pad output enable
p_mix_pad_en_13_go => pad_en_13, -- pad output enable
p_mix_pad_en_14_go => pad_en_14, -- pad output enable
p_mix_pad_en_15_go => pad_en_15, -- pad output enable
p_mix_pad_en_16_go => pad_en_16, -- pad output enable
p_mix_pad_en_17_go => pad_en_17, -- pad output enable
p_mix_pad_en_18_go => pad_en_18, -- pad output enable
p_mix_pad_en_2_go => pad_en_2, -- pad output enable
p_mix_pad_en_31_go => pad_en_31, -- pad output enable
p_mix_pad_en_32_go => pad_en_32, -- pad output enable
p_mix_pad_en_35_go => pad_en_35, -- pad output enable
p_mix_pad_en_36_go => pad_en_36, -- pad output enable
p_mix_pad_en_39_go => pad_en_39, -- pad output enable
p_mix_pad_en_40_go => pad_en_40, -- pad output enable
p_mix_pad_pu_31_go => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_go => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for ios
-- Generated Instance Port Map for pad_pads
pad_pads: pad_pads_e
port map (
p_mix_pad_di_12_go => pad_di_12, -- data in from pad
p_mix_pad_di_13_go => pad_di_13, -- data in from pad
p_mix_pad_di_14_go => pad_di_14, -- data in from pad
p_mix_pad_di_15_go => pad_di_15, -- data in from pad
p_mix_pad_di_16_go => pad_di_16, -- data in from pad
p_mix_pad_di_17_go => pad_di_17, -- data in from pad
p_mix_pad_di_18_go => pad_di_18, -- data in from pad
p_mix_pad_di_1_go => pad_di_1, -- data in from pad
p_mix_pad_di_31_go => pad_di_31, -- data in from pad
p_mix_pad_di_32_go => pad_di_32, -- data in from pad
p_mix_pad_di_33_go => pad_di_33, -- data in from pad
p_mix_pad_di_34_go => pad_di_34, -- data in from pad
p_mix_pad_di_39_go => pad_di_39, -- data in from pad
p_mix_pad_di_40_go => pad_di_40, -- data in from pad
p_mix_pad_do_12_gi => pad_do_12, -- data out to pad
p_mix_pad_do_13_gi => pad_do_13, -- data out to pad
p_mix_pad_do_14_gi => pad_do_14, -- data out to pad
p_mix_pad_do_15_gi => pad_do_15, -- data out to pad
p_mix_pad_do_16_gi => pad_do_16, -- data out to pad
p_mix_pad_do_17_gi => pad_do_17, -- data out to pad
p_mix_pad_do_18_gi => pad_do_18, -- data out to pad
p_mix_pad_do_2_gi => pad_do_2, -- data out to pad
p_mix_pad_do_31_gi => pad_do_31, -- data out to pad
p_mix_pad_do_32_gi => pad_do_32, -- data out to pad
p_mix_pad_do_35_gi => pad_do_35, -- data out to pad
p_mix_pad_do_36_gi => pad_do_36, -- data out to pad
p_mix_pad_do_39_gi => pad_do_39, -- data out to pad
p_mix_pad_do_40_gi => pad_do_40, -- data out to pad
p_mix_pad_en_12_gi => pad_en_12, -- pad output enable
p_mix_pad_en_13_gi => pad_en_13, -- pad output enable
p_mix_pad_en_14_gi => pad_en_14, -- pad output enable
p_mix_pad_en_15_gi => pad_en_15, -- pad output enable
p_mix_pad_en_16_gi => pad_en_16, -- pad output enable
p_mix_pad_en_17_gi => pad_en_17, -- pad output enable
p_mix_pad_en_18_gi => pad_en_18, -- pad output enable
p_mix_pad_en_2_gi => pad_en_2, -- pad output enable
p_mix_pad_en_31_gi => pad_en_31, -- pad output enable
p_mix_pad_en_32_gi => pad_en_32, -- pad output enable
p_mix_pad_en_35_gi => pad_en_35, -- pad output enable
p_mix_pad_en_36_gi => pad_en_36, -- pad output enable
p_mix_pad_en_39_gi => pad_en_39, -- pad output enable
p_mix_pad_en_40_gi => pad_en_40, -- pad output enable
p_mix_pad_pu_31_gi => pad_pu_31, -- pull-up control
p_mix_pad_pu_32_gi => pad_pu_32 -- pull-up control
);
-- End of Generated Instance Port Map for pad_pads
-- Generated Instance Port Map for test_ctrl
test_ctrl: testctrl_e
;
-- End of Generated Instance Port Map for test_ctrl
-- Generated Instance Port Map for u0_alreg
u0_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_0 -- Display storage buffer 0 ls_min
);
-- End of Generated Instance Port Map for u0_alreg
-- Generated Instance Port Map for u1_alreg
u1_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_1 -- Display storage buffer 1 ms_min
);
-- End of Generated Instance Port Map for u1_alreg
-- Generated Instance Port Map for u2_alreg
u2_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_2 -- Display storage buffer 2 ls_hr
);
-- End of Generated Instance Port Map for u2_alreg
-- Generated Instance Port Map for u3_alreg
u3_alreg: alreg
port map (
alarm_time => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
load_new_a => load_new_a,
new_alarm_time => s_int_key_buffer_3 -- Display storage buffer 3 ms_hr
);
-- End of Generated Instance Port Map for u3_alreg
-- Generated Instance Port Map for u_counter
u_counter: count4
port map (
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
load_new_c => load_new_c,
new_current_time_ls_hr => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
new_current_time_ls_min => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
new_current_time_ms_hr => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
new_current_time_ms_min => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
one_minute => one_minute
);
-- End of Generated Instance Port Map for u_counter
-- Generated Instance Port Map for u_ddrv4
u_ddrv4: ddrv4
port map (
alarm_time_ls_hr => s_int_alarm_time_ls_hr, -- Display storage buffer 2 ls_hr
alarm_time_ls_min => s_int_alarm_time_ls_min, -- Display storage buffer 0 ls_min
alarm_time_ms_hr => s_int_alarm_time_ms_hr, -- Display storage buffer 3 ms_hr
alarm_time_ms_min => s_int_alarm_time_ms_min, -- Display storage buffer 1 ms_min
current_time_ls_hr => s_int_current_time_ls_hr, -- Display storage buffer 2 ls_hr
current_time_ls_min => s_int_current_time_ls_min, -- Display storage buffer 0 ls_min
current_time_ms_hr => s_int_current_time_ms_hr, -- Display storage buffer 3 ms_hr
current_time_ms_min => s_int_current_time_ms_min, -- Display storage buffer 1 ms_min
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
p_mix_display_ls_hr_go => s_int_display_ls_hr, -- Display storage buffer 2 ls_hr
p_mix_display_ls_min_go => s_int_display_ls_min, -- Display storage buffer 0 ls_min
p_mix_display_ms_hr_go => s_int_display_ms_hr, -- Display storage buffer 3 ms_hr
p_mix_display_ms_min_go => s_int_display_ms_min, -- Display storage buffer 1 ms_min
p_mix_sound_alarm_go => sound_alarm,
show_a => s_int_show_a,
show_new_time => s_int_show_new_time
);
-- End of Generated Instance Port Map for u_ddrv4
-- Generated Instance Port Map for u_keypad
u_keypad: keypad
port map (
columns => columns,
rows => rows -- Keypad Output
);
-- End of Generated Instance Port Map for u_keypad
-- Generated Instance Port Map for u_keyscan
u_keyscan: keyscan
port map (
alarm_button => alarm_button,
columns => columns,
key => key,
key_buffer_0 => s_int_key_buffer_0, -- Display storage buffer 0 ls_min
key_buffer_1 => s_int_key_buffer_1, -- Display storage buffer 1 ms_min
key_buffer_2 => s_int_key_buffer_2, -- Display storage buffer 2 ls_hr
key_buffer_3 => s_int_key_buffer_3, -- Display storage buffer 3 ms_hr
rows => rows, -- Keypad Output
shift => shift,
time_button => time_button
);
-- End of Generated Instance Port Map for u_keyscan
-- Generated Instance Port Map for u_timegen
u_timegen: timegen
port map (
one_minute => one_minute,
one_second => one_sec_pulse,
stopwatch => stopwatch -- Driven by reset
);
-- End of Generated Instance Port Map for u_timegen
end rtl;
--
--!End of Architecture/s
-- --------------------------------------------------------------
|
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity nt_nt is
port(
clk : in std_logic;
SI : in BIT;
SO : out BIT
);
end nt_nt;
architecture nt_nt of nt_nt is
signal tmp: bit_vector(7 downto 0);
begin
process (clk)
begin
if (clk'event and clk='1') then
tmp <= tmp(6 downto 0)& SI;
end if;
end process;
SO <= tmp(7);
end nt_nt;
--clk=20Mhz; SI= random 10ns; |
----------------------------------------------------------------------------
-- ps7_stub.vhd
-- ZedBoard simple VHDL example
-- Version 1.0
--
-- Copyright (C) 2013 H.Poetzl
--
-- This program is free software: you can redistribute it and/or
-- modify it under the terms of the GNU General Public License
-- as published by the Free Software Foundation, either version
-- 2 of the License, or (at your option) any later version.
--
----------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
library unisim;
use unisim.VCOMPONENTS.all;
entity ps7_stub is
port (
i2c_sda_i : in std_ulogic;
i2c_sda_o : out std_ulogic;
i2c_sda_tn : out std_ulogic;
--
i2c_scl_i : in std_ulogic;
i2c_scl_o : out std_ulogic;
i2c_scl_tn : out std_ulogic
);
end entity ps7_stub;
architecture RTL of ps7_stub is
begin
PS7_inst : PS7
port map (
DMA0DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA0DAVALID => open, -- out std_ulogic;
DMA0DRREADY => open, -- out std_ulogic;
DMA0RSTN => open, -- out std_ulogic;
DMA1DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA1DAVALID => open, -- out std_ulogic;
DMA1DRREADY => open, -- out std_ulogic;
DMA1RSTN => open, -- out std_ulogic;
DMA2DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA2DAVALID => open, -- out std_ulogic;
DMA2DRREADY => open, -- out std_ulogic;
DMA2RSTN => open, -- out std_ulogic;
DMA3DATYPE => open, -- out std_logic_vector(1 downto 0);
DMA3DAVALID => open, -- out std_ulogic;
DMA3DRREADY => open, -- out std_ulogic;
DMA3RSTN => open, -- out std_ulogic;
EMIOCAN0PHYTX => open, -- out std_ulogic;
EMIOCAN1PHYTX => open, -- out std_ulogic;
EMIOENET0GMIITXD => open, -- out std_logic_vector(7 downto 0);
EMIOENET0GMIITXEN => open, -- out std_ulogic;
EMIOENET0GMIITXER => open, -- out std_ulogic;
EMIOENET0MDIOMDC => open, -- out std_ulogic;
EMIOENET0MDIOO => open, -- out std_ulogic;
EMIOENET0MDIOTN => open, -- out std_ulogic;
EMIOENET0PTPDELAYREQRX => open, -- out std_ulogic;
EMIOENET0PTPDELAYREQTX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYREQRX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYREQTX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYRESPRX => open, -- out std_ulogic;
EMIOENET0PTPPDELAYRESPTX => open, -- out std_ulogic;
EMIOENET0PTPSYNCFRAMERX => open, -- out std_ulogic;
EMIOENET0PTPSYNCFRAMETX => open, -- out std_ulogic;
EMIOENET0SOFRX => open, -- out std_ulogic;
EMIOENET0SOFTX => open, -- out std_ulogic;
EMIOENET1GMIITXD => open, -- out std_logic_vector(7 downto 0);
EMIOENET1GMIITXEN => open, -- out std_ulogic;
EMIOENET1GMIITXER => open, -- out std_ulogic;
EMIOENET1MDIOMDC => open, -- out std_ulogic;
EMIOENET1MDIOO => open, -- out std_ulogic;
EMIOENET1MDIOTN => open, -- out std_ulogic;
EMIOENET1PTPDELAYREQRX => open, -- out std_ulogic;
EMIOENET1PTPDELAYREQTX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYREQRX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYREQTX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYRESPRX => open, -- out std_ulogic;
EMIOENET1PTPPDELAYRESPTX => open, -- out std_ulogic;
EMIOENET1PTPSYNCFRAMERX => open, -- out std_ulogic;
EMIOENET1PTPSYNCFRAMETX => open, -- out std_ulogic;
EMIOENET1SOFRX => open, -- out std_ulogic;
EMIOENET1SOFTX => open, -- out std_ulogic;
EMIOGPIOO => open, -- out std_logic_vector(63 downto 0);
EMIOGPIOTN => open, -- out std_logic_vector(63 downto 0);
EMIOI2C0SCLO => i2c_scl_o, -- out std_ulogic;
EMIOI2C0SCLTN => i2c_scl_tn, -- out std_ulogic;
EMIOI2C0SDAO => i2c_sda_o, -- out std_ulogic;
EMIOI2C0SDATN => i2c_sda_tn, -- out std_ulogic;
EMIOI2C1SCLO => open, -- out std_ulogic;
EMIOI2C1SCLTN => open, -- out std_ulogic;
EMIOI2C1SDAO => open, -- out std_ulogic;
EMIOI2C1SDATN => open, -- out std_ulogic;
EMIOPJTAGTDO => open, -- out std_ulogic;
EMIOPJTAGTDTN => open, -- out std_ulogic;
EMIOSDIO0BUSPOW => open, -- out std_ulogic;
EMIOSDIO0BUSVOLT => open, -- out std_logic_vector(2 downto 0);
EMIOSDIO0CLK => open, -- out std_ulogic;
EMIOSDIO0CMDO => open, -- out std_ulogic;
EMIOSDIO0CMDTN => open, -- out std_ulogic;
EMIOSDIO0DATAO => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO0DATATN => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO0LED => open, -- out std_ulogic;
EMIOSDIO1BUSPOW => open, -- out std_ulogic;
EMIOSDIO1BUSVOLT => open, -- out std_logic_vector(2 downto 0);
EMIOSDIO1CLK => open, -- out std_ulogic;
EMIOSDIO1CMDO => open, -- out std_ulogic;
EMIOSDIO1CMDTN => open, -- out std_ulogic;
EMIOSDIO1DATAO => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO1DATATN => open, -- out std_logic_vector(3 downto 0);
EMIOSDIO1LED => open, -- out std_ulogic;
EMIOSPI0MO => open, -- out std_ulogic;
EMIOSPI0MOTN => open, -- out std_ulogic;
EMIOSPI0SCLKO => open, -- out std_ulogic;
EMIOSPI0SCLKTN => open, -- out std_ulogic;
EMIOSPI0SO => open, -- out std_ulogic;
EMIOSPI0SSNTN => open, -- out std_ulogic;
EMIOSPI0SSON => open, -- out std_logic_vector(2 downto 0);
EMIOSPI0STN => open, -- out std_ulogic;
EMIOSPI1MO => open, -- out std_ulogic;
EMIOSPI1MOTN => open, -- out std_ulogic;
EMIOSPI1SCLKO => open, -- out std_ulogic;
EMIOSPI1SCLKTN => open, -- out std_ulogic;
EMIOSPI1SO => open, -- out std_ulogic;
EMIOSPI1SSNTN => open, -- out std_ulogic;
EMIOSPI1SSON => open, -- out std_logic_vector(2 downto 0);
EMIOSPI1STN => open, -- out std_ulogic;
EMIOTRACECTL => open, -- out std_ulogic;
EMIOTRACEDATA => open, -- out std_logic_vector(31 downto 0);
EMIOTTC0WAVEO => open, -- out std_logic_vector(2 downto 0);
EMIOTTC1WAVEO => open, -- out std_logic_vector(2 downto 0);
EMIOUART0DTRN => open, -- out std_ulogic;
EMIOUART0RTSN => open, -- out std_ulogic;
EMIOUART0TX => open, -- out std_ulogic;
EMIOUART1DTRN => open, -- out std_ulogic;
EMIOUART1RTSN => open, -- out std_ulogic;
EMIOUART1TX => open, -- out std_ulogic;
EMIOUSB0PORTINDCTL => open, -- out std_logic_vector(1 downto 0);
EMIOUSB0VBUSPWRSELECT => open, -- out std_ulogic;
EMIOUSB1PORTINDCTL => open, -- out std_logic_vector(1 downto 0);
EMIOUSB1VBUSPWRSELECT => open, -- out std_ulogic;
EMIOWDTRSTO => open, -- out std_ulogic;
EVENTEVENTO => open, -- out std_ulogic;
EVENTSTANDBYWFE => open, -- out std_logic_vector(1 downto 0);
EVENTSTANDBYWFI => open, -- out std_logic_vector(1 downto 0);
FCLKCLK => open, -- out std_logic_vector(3 downto 0);
FCLKRESETN => open, -- out std_logic_vector(3 downto 0);
FTMTF2PTRIGACK => open, -- out std_logic_vector(3 downto 0);
FTMTP2FDEBUG => open, -- out std_logic_vector(31 downto 0);
FTMTP2FTRIG => open, -- out std_logic_vector(3 downto 0);
IRQP2F => open, -- out std_logic_vector(28 downto 0);
MAXIGP0ARADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP0ARBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARESETN => open, -- out std_ulogic;
MAXIGP0ARID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0ARLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP0ARQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP0ARSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP0ARVALID => open, -- out std_ulogic;
MAXIGP0AWADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP0AWBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0AWLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP0AWQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP0AWSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP0AWVALID => open, -- out std_ulogic;
MAXIGP0BREADY => open, -- out std_ulogic;
MAXIGP0RREADY => open, -- out std_ulogic;
MAXIGP0WDATA => open, -- out std_logic_vector(31 downto 0);
MAXIGP0WID => open, -- out std_logic_vector(11 downto 0);
MAXIGP0WLAST => open, -- out std_ulogic;
MAXIGP0WSTRB => open, -- out std_logic_vector(3 downto 0);
MAXIGP0WVALID => open, -- out std_ulogic;
MAXIGP1ARADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP1ARBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARESETN => open, -- out std_ulogic;
MAXIGP1ARID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1ARLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP1ARQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP1ARSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP1ARVALID => open, -- out std_ulogic;
MAXIGP1AWADDR => open, -- out std_logic_vector(31 downto 0);
MAXIGP1AWBURST => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWCACHE => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1AWLEN => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWLOCK => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWPROT => open, -- out std_logic_vector(2 downto 0);
MAXIGP1AWQOS => open, -- out std_logic_vector(3 downto 0);
MAXIGP1AWSIZE => open, -- out std_logic_vector(1 downto 0);
MAXIGP1AWVALID => open, -- out std_ulogic;
MAXIGP1BREADY => open, -- out std_ulogic;
MAXIGP1RREADY => open, -- out std_ulogic;
MAXIGP1WDATA => open, -- out std_logic_vector(31 downto 0);
MAXIGP1WID => open, -- out std_logic_vector(11 downto 0);
MAXIGP1WLAST => open, -- out std_ulogic;
MAXIGP1WSTRB => open, -- out std_logic_vector(3 downto 0);
MAXIGP1WVALID => open, -- out std_ulogic;
SAXIACPARESETN => open, -- out std_ulogic;
SAXIACPARREADY => open, -- out std_ulogic;
SAXIACPAWREADY => open, -- out std_ulogic;
SAXIACPBID => open, -- out std_logic_vector(2 downto 0);
SAXIACPBRESP => open, -- out std_logic_vector(1 downto 0);
SAXIACPBVALID => open, -- out std_ulogic;
SAXIACPRDATA => open, -- out std_logic_vector(63 downto 0);
SAXIACPRID => open, -- out std_logic_vector(2 downto 0);
SAXIACPRLAST => open, -- out std_ulogic;
SAXIACPRRESP => open, -- out std_logic_vector(1 downto 0);
SAXIACPRVALID => open, -- out std_ulogic;
SAXIACPWREADY => open, -- out std_ulogic;
SAXIGP0ARESETN => open, -- out std_ulogic;
SAXIGP0ARREADY => open, -- out std_ulogic;
SAXIGP0AWREADY => open, -- out std_ulogic;
SAXIGP0BID => open, -- out std_logic_vector(5 downto 0);
SAXIGP0BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP0BVALID => open, -- out std_ulogic;
SAXIGP0RDATA => open, -- out std_logic_vector(31 downto 0);
SAXIGP0RID => open, -- out std_logic_vector(5 downto 0);
SAXIGP0RLAST => open, -- out std_ulogic;
SAXIGP0RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP0RVALID => open, -- out std_ulogic;
SAXIGP0WREADY => open, -- out std_ulogic;
SAXIGP1ARESETN => open, -- out std_ulogic;
SAXIGP1ARREADY => open, -- out std_ulogic;
SAXIGP1AWREADY => open, -- out std_ulogic;
SAXIGP1BID => open, -- out std_logic_vector(5 downto 0);
SAXIGP1BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP1BVALID => open, -- out std_ulogic;
SAXIGP1RDATA => open, -- out std_logic_vector(31 downto 0);
SAXIGP1RID => open, -- out std_logic_vector(5 downto 0);
SAXIGP1RLAST => open, -- out std_ulogic;
SAXIGP1RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIGP1RVALID => open, -- out std_ulogic;
SAXIGP1WREADY => open, -- out std_ulogic;
SAXIHP0ARESETN => open, -- out std_ulogic;
SAXIHP0ARREADY => open, -- out std_ulogic;
SAXIHP0AWREADY => open, -- out std_ulogic;
SAXIHP0BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP0BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP0BVALID => open, -- out std_ulogic;
SAXIHP0RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP0RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP0RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP0RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP0RLAST => open, -- out std_ulogic;
SAXIHP0RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP0RVALID => open, -- out std_ulogic;
SAXIHP0WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP0WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP0WREADY => open, -- out std_ulogic;
SAXIHP1ARESETN => open, -- out std_ulogic;
SAXIHP1ARREADY => open, -- out std_ulogic;
SAXIHP1AWREADY => open, -- out std_ulogic;
SAXIHP1BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP1BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP1BVALID => open, -- out std_ulogic;
SAXIHP1RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP1RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP1RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP1RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP1RLAST => open, -- out std_ulogic;
SAXIHP1RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP1RVALID => open, -- out std_ulogic;
SAXIHP1WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP1WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP1WREADY => open, -- out std_ulogic;
SAXIHP2ARESETN => open, -- out std_ulogic;
SAXIHP2ARREADY => open, -- out std_ulogic;
SAXIHP2AWREADY => open, -- out std_ulogic;
SAXIHP2BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP2BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP2BVALID => open, -- out std_ulogic;
SAXIHP2RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP2RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP2RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP2RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP2RLAST => open, -- out std_ulogic;
SAXIHP2RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP2RVALID => open, -- out std_ulogic;
SAXIHP2WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP2WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP2WREADY => open, -- out std_ulogic;
SAXIHP3ARESETN => open, -- out std_ulogic;
SAXIHP3ARREADY => open, -- out std_ulogic;
SAXIHP3AWREADY => open, -- out std_ulogic;
SAXIHP3BID => open, -- out std_logic_vector(5 downto 0);
SAXIHP3BRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP3BVALID => open, -- out std_ulogic;
SAXIHP3RACOUNT => open, -- out std_logic_vector(2 downto 0);
SAXIHP3RCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP3RDATA => open, -- out std_logic_vector(63 downto 0);
SAXIHP3RID => open, -- out std_logic_vector(5 downto 0);
SAXIHP3RLAST => open, -- out std_ulogic;
SAXIHP3RRESP => open, -- out std_logic_vector(1 downto 0);
SAXIHP3RVALID => open, -- out std_ulogic;
SAXIHP3WACOUNT => open, -- out std_logic_vector(5 downto 0);
SAXIHP3WCOUNT => open, -- out std_logic_vector(7 downto 0);
SAXIHP3WREADY => open, -- out std_ulogic;
DDRA => open, -- inout std_logic_vector(14 downto 0);
DDRBA => open, -- inout std_logic_vector(2 downto 0);
DDRCASB => open, -- inout std_ulogic;
DDRCKE => open, -- inout std_ulogic;
DDRCKN => open, -- inout std_ulogic;
DDRCKP => open, -- inout std_ulogic;
DDRCSB => open, -- inout std_ulogic;
DDRDM => open, -- inout std_logic_vector(3 downto 0);
DDRDQ => open, -- inout std_logic_vector(31 downto 0);
DDRDQSN => open, -- inout std_logic_vector(3 downto 0);
DDRDQSP => open, -- inout std_logic_vector(3 downto 0);
DDRDRSTB => open, -- inout std_ulogic;
DDRODT => open, -- inout std_ulogic;
DDRRASB => open, -- inout std_ulogic;
DDRVRN => open, -- inout std_ulogic;
DDRVRP => open, -- inout std_ulogic;
DDRWEB => open, -- inout std_ulogic;
MIO => open, -- inout std_logic_vector(53 downto 0);
PSCLK => open, -- inout std_ulogic;
PSPORB => open, -- inout std_ulogic;
PSSRSTB => open, -- inout std_ulogic;
DDRARB => (others => '0'), -- in std_logic_vector(3 downto 0);
DMA0ACLK => '0', -- in std_ulogic;
DMA0DAREADY => '0', -- in std_ulogic;
DMA0DRLAST => '0', -- in std_ulogic;
DMA0DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA0DRVALID => '0', -- in std_ulogic;
DMA1ACLK => '0', -- in std_ulogic;
DMA1DAREADY => '0', -- in std_ulogic;
DMA1DRLAST => '0', -- in std_ulogic;
DMA1DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA1DRVALID => '0', -- in std_ulogic;
DMA2ACLK => '0', -- in std_ulogic;
DMA2DAREADY => '0', -- in std_ulogic;
DMA2DRLAST => '0', -- in std_ulogic;
DMA2DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA2DRVALID => '0', -- in std_ulogic;
DMA3ACLK => '0', -- in std_ulogic;
DMA3DAREADY => '0', -- in std_ulogic;
DMA3DRLAST => '0', -- in std_ulogic;
DMA3DRTYPE => (others => '0'), -- in std_logic_vector(1 downto 0);
DMA3DRVALID => '0', -- in std_ulogic;
EMIOCAN0PHYRX => '0', -- in std_ulogic;
EMIOCAN1PHYRX => '0', -- in std_ulogic;
EMIOENET0EXTINTIN => '0', -- in std_ulogic;
EMIOENET0GMIICOL => '0', -- in std_ulogic;
EMIOENET0GMIICRS => '0', -- in std_ulogic;
EMIOENET0GMIIRXCLK => '0', -- in std_ulogic;
EMIOENET0GMIIRXD => (others => '0'), -- in std_logic_vector(7 downto 0);
EMIOENET0GMIIRXDV => '0', -- in std_ulogic;
EMIOENET0GMIIRXER => '0', -- in std_ulogic;
EMIOENET0GMIITXCLK => '0', -- in std_ulogic;
EMIOENET0MDIOI => '0', -- in std_ulogic;
EMIOENET1EXTINTIN => '0', -- in std_ulogic;
EMIOENET1GMIICOL => '0', -- in std_ulogic;
EMIOENET1GMIICRS => '0', -- in std_ulogic;
EMIOENET1GMIIRXCLK => '0', -- in std_ulogic;
EMIOENET1GMIIRXD => (others => '0'), -- in std_logic_vector(7 downto 0);
EMIOENET1GMIIRXDV => '0', -- in std_ulogic;
EMIOENET1GMIIRXER => '0', -- in std_ulogic;
EMIOENET1GMIITXCLK => '0', -- in std_ulogic;
EMIOENET1MDIOI => '0', -- in std_ulogic;
EMIOGPIOI => (others => '0'), -- in std_logic_vector(63 downto 0);
EMIOI2C0SCLI => i2c_scl_i, -- in std_ulogic;
EMIOI2C0SDAI => i2c_sda_i, -- in std_ulogic;
EMIOI2C1SCLI => '0', -- in std_ulogic;
EMIOI2C1SDAI => '0', -- in std_ulogic;
EMIOPJTAGTCK => '0', -- in std_ulogic;
EMIOPJTAGTDI => '0', -- in std_ulogic;
EMIOPJTAGTMS => '0', -- in std_ulogic;
EMIOSDIO0CDN => '0', -- in std_ulogic;
EMIOSDIO0CLKFB => '0', -- in std_ulogic;
EMIOSDIO0CMDI => '0', -- in std_ulogic;
EMIOSDIO0DATAI => (others => '0'), -- in std_logic_vector(3 downto 0);
EMIOSDIO0WP => '0', -- in std_ulogic;
EMIOSDIO1CDN => '0', -- in std_ulogic;
EMIOSDIO1CLKFB => '0', -- in std_ulogic;
EMIOSDIO1CMDI => '0', -- in std_ulogic;
EMIOSDIO1DATAI => (others => '0'), -- in std_logic_vector(3 downto 0);
EMIOSDIO1WP => '0', -- in std_ulogic;
EMIOSPI0MI => '0', -- in std_ulogic;
EMIOSPI0SCLKI => '0', -- in std_ulogic;
EMIOSPI0SI => '0', -- in std_ulogic;
EMIOSPI0SSIN => '0', -- in std_ulogic;
EMIOSPI1MI => '0', -- in std_ulogic;
EMIOSPI1SCLKI => '0', -- in std_ulogic;
EMIOSPI1SI => '0', -- in std_ulogic;
EMIOSPI1SSIN => '0', -- in std_ulogic;
EMIOSRAMINTIN => '0', -- in std_ulogic;
EMIOTRACECLK => '0', -- in std_ulogic;
EMIOTTC0CLKI => (others => '0'), -- in std_logic_vector(2 downto 0);
EMIOTTC1CLKI => (others => '0'), -- in std_logic_vector(2 downto 0);
EMIOUART0CTSN => '0', -- in std_ulogic;
EMIOUART0DCDN => '0', -- in std_ulogic;
EMIOUART0DSRN => '0', -- in std_ulogic;
EMIOUART0RIN => '0', -- in std_ulogic;
EMIOUART0RX => '0', -- in std_ulogic;
EMIOUART1CTSN => '0', -- in std_ulogic;
EMIOUART1DCDN => '0', -- in std_ulogic;
EMIOUART1DSRN => '0', -- in std_ulogic;
EMIOUART1RIN => '0', -- in std_ulogic;
EMIOUART1RX => '0', -- in std_ulogic;
EMIOUSB0VBUSPWRFAULT => '0', -- in std_ulogic;
EMIOUSB1VBUSPWRFAULT => '0', -- in std_ulogic;
EMIOWDTCLKI => '0', -- in std_ulogic;
EVENTEVENTI => '0', -- in std_ulogic;
FCLKCLKTRIGN => (others => '0'), -- in std_logic_vector(3 downto 0);
FPGAIDLEN => '0', -- in std_ulogic;
FTMDTRACEINATID => (others => '0'), -- in std_logic_vector(3 downto 0);
FTMDTRACEINCLOCK => '0', -- in std_ulogic;
FTMDTRACEINDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
FTMDTRACEINVALID => '0', -- in std_ulogic;
FTMTF2PDEBUG => (others => '0'), -- in std_logic_vector(31 downto 0);
FTMTF2PTRIG => (others => '0'), -- in std_logic_vector(3 downto 0);
FTMTP2FTRIGACK => (others => '0'), -- in std_logic_vector(3 downto 0);
IRQF2P => (others => '0'), -- in std_logic_vector(19 downto 0);
MAXIGP0ACLK => '0', -- in std_ulogic;
MAXIGP0ARREADY => '0', -- in std_ulogic;
MAXIGP0AWREADY => '0', -- in std_ulogic;
MAXIGP0BID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP0BRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP0BVALID => '0', -- in std_ulogic;
MAXIGP0RDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
MAXIGP0RID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP0RLAST => '0', -- in std_ulogic;
MAXIGP0RRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP0RVALID => '0', -- in std_ulogic;
MAXIGP0WREADY => '0', -- in std_ulogic;
MAXIGP1ACLK => '0', -- in std_ulogic;
MAXIGP1ARREADY => '0', -- in std_ulogic;
MAXIGP1AWREADY => '0', -- in std_ulogic;
MAXIGP1BID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP1BRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP1BVALID => '0', -- in std_ulogic;
MAXIGP1RDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
MAXIGP1RID => (others => '0'), -- in std_logic_vector(11 downto 0);
MAXIGP1RLAST => '0', -- in std_ulogic;
MAXIGP1RRESP => (others => '0'), -- in std_logic_vector(1 downto 0);
MAXIGP1RVALID => '0', -- in std_ulogic;
MAXIGP1WREADY => '0', -- in std_ulogic;
SAXIACPACLK => '0', -- in std_ulogic;
SAXIACPARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIACPARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPARUSER => (others => '0'), -- in std_logic_vector(4 downto 0);
SAXIACPARVALID => '0', -- in std_ulogic;
SAXIACPAWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIACPAWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPAWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPAWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIACPAWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIACPAWUSER => (others => '0'), -- in std_logic_vector(4 downto 0);
SAXIACPAWVALID => '0', -- in std_ulogic;
SAXIACPBREADY => '0', -- in std_ulogic;
SAXIACPRREADY => '0', -- in std_ulogic;
SAXIACPWDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIACPWID => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIACPWLAST => '0', -- in std_ulogic;
SAXIACPWSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIACPWVALID => '0', -- in std_ulogic;
SAXIGP0ACLK => '0', -- in std_ulogic;
SAXIGP0ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP0ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0ARVALID => '0', -- in std_ulogic;
SAXIGP0AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP0AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP0AWVALID => '0', -- in std_ulogic;
SAXIGP0BREADY => '0', -- in std_ulogic;
SAXIGP0RREADY => '0', -- in std_ulogic;
SAXIGP0WDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP0WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP0WLAST => '0', -- in std_ulogic;
SAXIGP0WSTRB => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP0WVALID => '0', -- in std_ulogic;
SAXIGP1ACLK => '0', -- in std_ulogic;
SAXIGP1ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP1ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1ARVALID => '0', -- in std_ulogic;
SAXIGP1AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIGP1AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIGP1AWVALID => '0', -- in std_ulogic;
SAXIGP1BREADY => '0', -- in std_ulogic;
SAXIGP1RREADY => '0', -- in std_ulogic;
SAXIGP1WDATA => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIGP1WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIGP1WLAST => '0', -- in std_ulogic;
SAXIGP1WSTRB => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIGP1WVALID => '0', -- in std_ulogic;
SAXIHP0ACLK => '0', -- in std_ulogic;
SAXIHP0ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP0ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP0ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0ARVALID => '0', -- in std_ulogic;
SAXIHP0AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP0AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP0AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP0AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP0AWVALID => '0', -- in std_ulogic;
SAXIHP0BREADY => '0', -- in std_ulogic;
SAXIHP0RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP0RREADY => '0', -- in std_ulogic;
SAXIHP0WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP0WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP0WLAST => '0', -- in std_ulogic;
SAXIHP0WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP0WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP0WVALID => '0', -- in std_ulogic;
SAXIHP1ACLK => '0', -- in std_ulogic;
SAXIHP1ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP1ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP1ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1ARVALID => '0', -- in std_ulogic;
SAXIHP1AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP1AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP1AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP1AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP1AWVALID => '0', -- in std_ulogic;
SAXIHP1BREADY => '0', -- in std_ulogic;
SAXIHP1RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP1RREADY => '0', -- in std_ulogic;
SAXIHP1WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP1WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP1WLAST => '0', -- in std_ulogic;
SAXIHP1WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP1WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP1WVALID => '0', -- in std_ulogic;
SAXIHP2ACLK => '0', -- in std_ulogic;
SAXIHP2ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP2ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP2ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2ARVALID => '0', -- in std_ulogic;
SAXIHP2AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP2AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP2AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP2AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP2AWVALID => '0', -- in std_ulogic;
SAXIHP2BREADY => '0', -- in std_ulogic;
SAXIHP2RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP2RREADY => '0', -- in std_ulogic;
SAXIHP2WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP2WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP2WLAST => '0', -- in std_ulogic;
SAXIHP2WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP2WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP2WVALID => '0', -- in std_ulogic;
SAXIHP3ACLK => '0', -- in std_ulogic;
SAXIHP3ARADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP3ARBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3ARLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP3ARQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3ARSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3ARVALID => '0', -- in std_ulogic;
SAXIHP3AWADDR => (others => '0'), -- in std_logic_vector(31 downto 0);
SAXIHP3AWBURST => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWCACHE => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3AWLEN => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWLOCK => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWPROT => (others => '0'), -- in std_logic_vector(2 downto 0);
SAXIHP3AWQOS => (others => '0'), -- in std_logic_vector(3 downto 0);
SAXIHP3AWSIZE => (others => '0'), -- in std_logic_vector(1 downto 0);
SAXIHP3AWVALID => '0', -- in std_ulogic;
SAXIHP3BREADY => '0', -- in std_ulogic;
SAXIHP3RDISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP3RREADY => '0', -- in std_ulogic;
SAXIHP3WDATA => (others => '0'), -- in std_logic_vector(63 downto 0);
SAXIHP3WID => (others => '0'), -- in std_logic_vector(5 downto 0);
SAXIHP3WLAST => '0', -- in std_ulogic;
SAXIHP3WRISSUECAP1EN => '0', -- in std_ulogic;
SAXIHP3WSTRB => (others => '0'), -- in std_logic_vector(7 downto 0);
SAXIHP3WVALID => '0' -- in std_ulogic
);
end RTL; |
-- ================================================================================
-- Legal Notice: Copyright (C) 1991-2006 Altera Corporation
-- Any megafunction design, and related net list (encrypted or decrypted),
-- support information, device programming or simulation file, and any other
-- associated documentation or information provided by Altera or a partner
-- under Altera's Megafunction Partnership Program may be used only to
-- program PLD devices (but not masked PLD devices) from Altera. Any other
-- use of such megafunction design, net list, support information, device
-- programming or simulation file, or any other related documentation or
-- information is prohibited for any other purpose, including, but not
-- limited to modification, reverse engineering, de-compiling, or use with
-- any other silicon devices, unless such use is explicitly licensed under
-- a separate agreement with Altera or a megafunction partner. Title to
-- the intellectual property, including patents, copyrights, trademarks,
-- trade secrets, or maskworks, embodied in any such megafunction design,
-- net list, support information, device programming or simulation file, or
-- any other related documentation or information provided by Altera or a
-- megafunction partner, remains with Altera, the megafunction partner, or
-- their respective licensors. No other licenses, including any licenses
-- needed under any third party's intellectual property, are provided herein.
-- ================================================================================
--
-- Generated by: FIR Compiler 9.0
-- Generated on: 2015-11-11 15:52:10
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library auk_dspip_lib;
use auk_dspip_lib.auk_dspip_lib_pkg_fir_90.all;
entity matchfilter_ast is
port(
clk : in std_logic;
reset_n : in std_logic;
ast_sink_ready : out std_logic;
ast_source_data : out std_logic_vector (30 -1 downto 0);
ast_sink_data : in std_logic_vector (15 -1 downto 0);
ast_sink_valid : in std_logic;
ast_source_valid : out std_logic;
ast_source_ready : in std_logic;
ast_sink_error : in std_logic_vector (1 downto 0);
ast_source_error : out std_logic_vector (1 downto 0)
);
attribute altera_attribute : string;
attribute altera_attribute of matchfilter_ast:entity is "-name MESSAGE_DISABLE 15400; -name MESSAGE_DISABLE 14130; -name MESSAGE_DISABLE 12020; -name MESSAGE_DISABLE 12030; -name MESSAGE_DISABLE 12010; -name MESSAGE_DISABLE 12110; -name MESSAGE_DISABLE 14320; -name MESSAGE_DISABLE 13410; -name MESSAGE_DISABLE 10036";
end matchfilter_ast;
-- Warnings Suppression On
-- altera message_off 10036
architecture struct of matchfilter_ast is
signal sink_packet_error : std_logic_vector(1 downto 0);
signal data_in : std_logic_vector(15 -1 downto 0);
signal data_out : std_logic_vector(30 -1 downto 0);
signal core_out : std_logic_vector(30 -1 downto 0);
signal ready : std_logic;
signal reset_fir : std_logic;
signal sink_ready_ctrl : std_logic;
signal sink_stall : std_logic;
signal source_packet_error : std_logic_vector(1 downto 0);
signal source_stall : std_logic;
signal source_valid_ctrl : std_logic;
signal stall : std_logic;
signal valid : std_logic;
signal core_valid : std_logic;
signal enable_in : std_logic;
signal stall_delayed : std_logic;
constant ENABLE_PIPELINE_DEPTH_c : natural := 0;
component matchfilter_st is
port (
rst : in std_logic;
clk : in std_logic;
clk_en : in std_logic;
rdy_to_ld : out std_logic;
done : out std_logic;
data_in : in std_logic_vector(15 - 1 downto 0);
fir_result : out std_logic_vector(30 - 1 downto 0));
end component matchfilter_st;
begin
sink : auk_dspip_avalon_streaming_sink_fir_90
generic map (
WIDTH_g => 15,
PACKET_SIZE_g => 1,
FIFO_DEPTH_g => 7,
FAMILY_g => "Cyclone III",
MEM_TYPE_g => "Auto")
port map (
clk => clk,
reset_n => reset_n,
data => data_in,
sink_ready_ctrl => sink_ready_ctrl,
sink_stall => sink_stall,
packet_error => sink_packet_error,
at_sink_ready => ast_sink_ready,
at_sink_valid => ast_sink_valid,
at_sink_data => ast_sink_data,
at_sink_error => ast_sink_error);
source : auk_dspip_avalon_streaming_source_fir_90
generic map (
WIDTH_g => 30,
packet_size_g => 1)
port map (
clk => clk,
reset_n => reset_n,
data => data_out,
source_valid_ctrl => source_valid_ctrl,
design_stall => stall_delayed,
source_stall => source_stall,
packet_error => source_packet_error,
at_source_ready => ast_source_ready,
at_source_valid => ast_source_valid,
at_source_data => ast_source_data,
at_source_error => ast_source_error);
intf_ctrl : auk_dspip_avalon_streaming_controller_fir_90
port map (
clk => clk,
ready => ready,
reset_n => reset_n,
sink_packet_error => sink_packet_error,
sink_stall => sink_stall,
source_stall => source_stall,
valid => valid,
reset_design => reset_fir,
sink_ready_ctrl => sink_ready_ctrl,
source_packet_error => source_packet_error,
source_valid_ctrl => source_valid_ctrl,
stall => stall);
fircore: matchfilter_st
port map (
rst => reset_fir,
clk => clk,
clk_en => enable_in,
rdy_to_ld => ready,
done => core_valid,
data_in => data_in,
fir_result => core_out);
data_out <= core_out;
valid <= core_valid;
enable_in <= not stall;
no_enable_pipeline: if ENABLE_PIPELINE_DEPTH_c = 0 generate
stall_delayed <= stall;
end generate no_enable_pipeline;
enable_pipeline: if ENABLE_PIPELINE_DEPTH_c > 0 generate
delay_core_enable : process (clk, reset_n)
variable stall_delay : std_logic_vector(ENABLE_PIPELINE_DEPTH_c downto 0);
begin -- process delay_core_enable
if reset_n = '0' then
stall_delay := (others => '0');
elsif rising_edge(clk) then
stall_delay := stall_delay(stall_delay'high-1 downto 0) & stall;
end if;
stall_delayed <= stall_delay(stall_delay'high);
end process delay_core_enable;
end generate enable_pipeline;
end struct;
|
--Copyright 2014 by Emmanuel D. Bello <[email protected]>
--Laboratorio de Computacion Reconfigurable (LCR)
--Universidad Tecnologica Nacional
--Facultad Regional Mendoza
--Argentina
--This file is part of FREAK-on-FPGA.
--FREAK-on-FPGA is free software: you can redistribute it and/or modify
--it under the terms of the GNU General Public License as published by
--the Free Software Foundation, either version 3 of the License, or
--(at your option) any later version.
--FREAK-on-FPGA is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
--GNU General Public License for more details.
--You should have received a copy of the GNU General Public License
--along with FREAK-on-FPGA. If not, see <http://www.gnu.org/licenses/>.
--------------------------------------------------------------------------------
-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
--------------------------------------------------------------------------------
-- ____ ____
-- / /\/ /
-- /___/ \ / Vendor: Xilinx
-- \ \ \/ Version : 14.6
-- \ \ Application :
-- / / Filename : xil_S42m9M
-- /___/ /\ Timestamp : 05/09/2014 00:41:30
-- \ \ / \
-- \___\/\___\
--
--Command:
--Design Name:
--
library ieee;
use ieee.std_logic_1164.ALL;
use ieee.numeric_std.ALL;
--library UNISIM;
--use UNISIM.Vcomponents.ALL;
use work.RetinaParameters.ALL;
entity RetinaDescriptorGenerator is
port ( CLK : in std_logic;
ENABLE : in std_logic;
IMG_BASE_ADDR : in std_logic_vector (31 downto 0);
KPTS_ADDR : in std_logic_vector (31 downto 0);
KPT_DATA : in std_logic_vector (31 downto 0);
PIXEL_DATA : in std_logic_vector (PIXEL_BW-1 downto 0);
RST : in std_logic;
KPT_ADDR_MEM : out std_logic_vector (31 downto 0);
PIXEL_ADDR_MEM: out std_logic_vector (31 downto 0);
DESCRIPTOR : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
ENABLEOUT : out std_logic;
KPT_READ_MEM : out std_logic;
PIXEL_READ_MEM : out std_logic
);
end RetinaDescriptorGenerator;
architecture BEHAVIORAL of RetinaDescriptorGenerator is
component KeypointReader is
port ( addr : in std_logic_vector (31 downto 0);
enableIn : in std_logic;
clk : in std_logic;
memData : in std_logic_vector (31 downto 0);
request : in std_logic;
rst : in std_logic;
busy : out std_logic;
kptCoordX : out std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's column possition
kptCoordY : out std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's row possition
kptScale : out std_logic_vector(KPT_SCALE_BW-1 downto 0);
kptOctave : out std_logic_vector(KPT_OCTAVE_BW-1 downto 0);
memAddr : out std_logic_vector (31 downto 0);
read_mem : out std_logic
);
end component;
--signals between KeypointReader and AddressGenerator:
---Control
signal sCtrlBusyKptAddr: std_logic;
signal sCtrlRequestKptAddr: std_logic;
---Data
signal skptCoordX: std_logic_vector (KPT_COORD_BW-1 downto 0);
signal skptCoordY: std_logic_vector (KPT_COORD_BW-1 downto 0);
signal skptScale : std_logic_vector(KPT_SCALE_BW-1 downto 0);
signal skptOctave : std_logic_vector(KPT_OCTAVE_BW-1 downto 0);
component AddressGenerator is
port ( busy_in : in std_logic;
clk : in std_logic;
imgBaseAddr : in std_logic_vector (31 downto 0);
kptCoordX : in std_logic_vector (KPT_COORD_BW-1 downto 0);--keypoint's column possition
kptCoordY : in std_logic_vector (KPT_COORD_BW-1 downto 0); --keypoint's row possition
kptScale : in std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
kptOctave : in std_logic_vector(KPT_OCTAVE_BW-1 downto 0);--keypoint's octave
request_in : in std_logic;
rst : in std_logic;
kptScaleOut : out std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
addr : out std_logic_vector (31 downto 0);
busy_out : out std_logic;
request_out : out std_logic
);
end component;
--signals between AddressGenerator and ImagePatchReader:
---Control
signal sCtrlBusyAddrImgRd: std_logic;
signal sCtrlRequestAddrImgRd: std_logic;
---Data
signal skptScaleOut : std_logic_vector(KPT_SCALE_BW-1 downto 0);
signal sGeneratedAddr: std_logic_vector (31 downto 0);
component ImagePatchReader is
port ( addr : in std_logic_vector (31 downto 0);
kptScale : in std_logic_vector(KPT_SCALE_BW-1 downto 0);--keypoint's scale
busy_in : in std_logic;
clk : in std_logic;
memData : in std_logic_vector (PIXEL_BW-1 downto 0);
rst : in std_logic;
addrKernel : out std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
en_out : out std_logic;
memAddr : out std_logic_vector (31 downto 0);
patchColumn : out T_INPUT_VERTICAL_CONVOLUTION;
readMem : out std_logic;
request_out : out std_logic
);
end component;
--signals between ImagePatchReader and GaussianFilter:
---Control
signal sEnableImgRdGauss: std_logic;
---Data
signal sAddrKernel: std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
signal sPatchColumn: T_INPUT_VERTICAL_CONVOLUTION;
component GaussianFilter is
port ( ADDR : in std_logic_vector (N_GAUSS_KERNEL_BW-1 downto 0);
CLK : in std_logic;
ENABLEIN : in std_logic;
INPUTARRAY : in T_INPUT_VERTICAL_CONVOLUTION;
RST : in std_logic;
ENABLEOUT : out std_logic;
OUTPUTDATA : out std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0)
);
end component;
--signals between GaussianFilter and PointBuffer:
---Control
signal sEnableGaussOut: std_logic;
---Data
signal sPointValue: std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
component TopDescriptorMaker is
port ( clk : in std_logic;
rst : in std_logic;
enableIn : in std_logic;
inputValue : in std_logic_vector (OUT_HORIZ_CONV_BW-1 downto 0);
descriptor : out std_logic_vector (DESCRIPTOR_SIZE-1 downto 0);
enableOut : out std_logic
);
end component;
begin
--mapping
keypoint_Reader: KeypointReader
port map( addr => KPTS_ADDR,
enableIn => ENABLE,
clk => CLK,
memData => KPT_DATA,
request => sCtrlRequestKptAddr,
rst => RST,
busy => sCtrlBusyKptAddr,
kptCoordX => skptCoordX,
kptCoordY => skptCoordY,
kptScale => skptScale,
kptOctave => skptOctave,
memAddr => KPT_ADDR_MEM,
read_mem => KPT_READ_MEM
);
address_Generator: AddressGenerator
port map( busy_in => sCtrlBusyKptAddr,
clk => CLK,
imgBaseAddr => IMG_BASE_ADDR,
kptCoordX => skptCoordX,
kptCoordY => skptCoordY,
kptScale => skptScale,
kptOctave => skptOctave,
request_in => sCtrlRequestAddrImgRd,
rst => RST,
kptScaleOut => skptScaleOut,
addr => sGeneratedAddr,
busy_out => sCtrlBusyAddrImgRd,
request_out => sCtrlRequestKptAddr
);
imagePatch_Reader: ImagePatchReader
port map( addr => sGeneratedAddr,
busy_in => sCtrlBusyAddrImgRd,
kptScale => skptScaleOut,
clk => CLK,
memData => PIXEL_DATA,
rst => RST,
addrKernel => sAddrKernel,
en_out => sEnableImgRdGauss,
memAddr => PIXEL_ADDR_MEM,
patchColumn => sPatchColumn,
readMem => PIXEL_READ_MEM,
request_out => sCtrlRequestAddrImgRd
);
gaussian_Filter: GaussianFilter
port map( ADDR => sAddrKernel,
CLK => CLK,
ENABLEIN => sEnableImgRdGauss,
INPUTARRAY => sPatchColumn,
RST => RST,
ENABLEOUT => sEnableGaussOut,
OUTPUTDATA => sPointValue
);
TopDescriptor_Maker: TopDescriptorMaker
port map(
clk => CLK,
rst => RST,
enableIn => sEnableGaussOut,
inputValue => sPointValue,
descriptor => DESCRIPTOR,
enableOut => ENABLEOUT
);
end BEHAVIORAL;
|
--!
--! Copyright 2018 Sergey Khabarov, [email protected]
--!
--! Licensed under the Apache License, Version 2.0 (the "License");
--! you may not use this file except in compliance with the License.
--! You may obtain a copy of the License at
--!
--! http://www.apache.org/licenses/LICENSE-2.0
--!
--! Unless required by applicable law or agreed to in writing, software
--! distributed under the License is distributed on an "AS IS" BASIS,
--! WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
--! See the License for the specific language governing permissions and
--! limitations under the License.
--!
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library techmap;
use techmap.gencomp.all;
package config_target is
-- Technology and synthesis options
constant CFG_FABTECH : integer := kintex7;
constant CFG_MEMTECH : integer := kintex7;
constant CFG_PADTECH : integer := kintex7;
constant CFG_JTAGTECH : integer := kintex7;
constant CFG_ASYNC_RESET : boolean := false;
constant CFG_TOPDIR : string := "../../../";
--! @brief Number of processors in a system
--! @details This value may be in a range 1 to CFG_TOTAL_CPU_MAX-1
constant CFG_CPU_NUM : integer := 1;
--! @brief HEX-image for the initialization of the Boot ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_BOOTROM_HEX : string :=
CFG_TOPDIR & "examples/boot/linuxbuild/bin/bootimage.hex";
-- CFG_TOPDIR & "examples/bootrom_tests/linuxbuild/bin/bootrom_tests.hex";
--! @brief HEX-image for the initialization of the FwImage ROM.
--! @details This file is used by \e inferred ROM implementation.
constant CFG_SIM_FWIMAGE_HEX : string :=
-- CFG_TOPDIR & "examples/zephyr/gcc711/zephyr.hex";
CFG_TOPDIR & "examples/gnss_fw/makefiles/bin/gnssfw.hex";
--! @brief Hardware SoC Identificator.
--!
--! @details Read Only unique platform identificator that could be
--! read by firmware from the Plug'n'Play support module.
constant CFG_HW_ID : std_logic_vector(31 downto 0) := X"20191125";
--! @brief Enabling Ethernet MAC interface.
--! @details By default MAC module enables support of the debug feature EDCL.
constant CFG_ETHERNET_ENABLE : boolean := true;
--! @brief Enable/Disable Debug Unit
constant CFG_DSU_ENABLE : boolean := true;
--! External Flash IC connected via SPI
constant CFG_EXT_FLASH_ENA : boolean := false;
--! GNSS sub-system
constant CFG_GNSS_SS_ENA : boolean := true;
--! OTP 8 KB memory bank
constant CFG_OTP8KB_ENA : boolean := false;
--! Coherent bridge with L2-cache
constant CFG_L2CACHE_ENA : boolean := false;
end;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb1_ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of usb1_ulpi_bus : entity is "yes";
end usb1_ulpi_bus;
architecture gideon of usb1_ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity usb1_ulpi_bus is
port (
clock : in std_logic;
reset : in std_logic;
ULPI_DATA : inout std_logic_vector(7 downto 0);
ULPI_DIR : in std_logic;
ULPI_NXT : in std_logic;
ULPI_STP : out std_logic;
-- status
status : out std_logic_vector(7 downto 0);
-- register interface
reg_read : in std_logic;
reg_write : in std_logic;
reg_address : in std_logic_vector(5 downto 0);
reg_wdata : in std_logic_vector(7 downto 0);
reg_ack : out std_logic;
-- stream interface
tx_data : in std_logic_vector(7 downto 0);
tx_last : in std_logic;
tx_valid : in std_logic;
tx_start : in std_logic;
tx_next : out std_logic;
rx_data : out std_logic_vector(7 downto 0);
rx_register : out std_logic;
rx_last : out std_logic;
rx_valid : out std_logic;
rx_store : out std_logic );
attribute keep_hierarchy : string;
attribute keep_hierarchy of usb1_ulpi_bus : entity is "yes";
end usb1_ulpi_bus;
architecture gideon of usb1_ulpi_bus is
signal ulpi_data_out : std_logic_vector(7 downto 0);
signal ulpi_data_in : std_logic_vector(7 downto 0);
signal ulpi_dir_d1 : std_logic;
signal ulpi_dir_d2 : std_logic;
signal ulpi_dir_d3 : std_logic;
signal ulpi_nxt_d1 : std_logic;
signal ulpi_nxt_d2 : std_logic;
signal ulpi_nxt_d3 : std_logic;
signal reg_cmd_d2 : std_logic;
signal reg_cmd_d3 : std_logic;
signal reg_cmd_d4 : std_logic;
signal reg_cmd_d5 : std_logic;
signal rx_reg_i : std_logic;
signal tx_reg_i : std_logic;
signal rx_status_i : std_logic;
signal ulpi_stop : std_logic := '1';
signal ulpi_last : std_logic;
type t_state is ( idle, reading, writing, writing_data, transmit );
signal state : t_state;
attribute iob : string;
attribute iob of ulpi_data_in : signal is "true";
attribute iob of ulpi_dir_d1 : signal is "true";
attribute iob of ulpi_nxt_d1 : signal is "true";
attribute iob of ulpi_data_out : signal is "true";
attribute iob of ULPI_STP : signal is "true";
begin
-- Marking incoming data based on next/dir pattern
rx_data <= ulpi_data_in;
rx_store <= ulpi_dir_d1 and ulpi_dir_d2 and ulpi_nxt_d1;
rx_valid <= ulpi_dir_d1 and ulpi_dir_d2;
rx_last <= not ulpi_dir_d1 and ulpi_dir_d2;
rx_status_i <= ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_nxt_d1 and not rx_reg_i;
rx_reg_i <= (ulpi_dir_d1 and ulpi_dir_d2 and not ulpi_dir_d3) and
(not ulpi_nxt_d1 and not ulpi_nxt_d2 and ulpi_nxt_d3) and
reg_cmd_d5;
rx_register <= rx_reg_i;
reg_ack <= rx_reg_i or tx_reg_i;
p_sample: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_data_in <= ULPI_DATA;
reg_cmd_d2 <= ulpi_data_in(7) and ulpi_data_in(6);
reg_cmd_d3 <= reg_cmd_d2;
reg_cmd_d4 <= reg_cmd_d3;
reg_cmd_d5 <= reg_cmd_d4;
ulpi_dir_d1 <= ULPI_DIR;
ulpi_dir_d2 <= ulpi_dir_d1;
ulpi_dir_d3 <= ulpi_dir_d2;
ulpi_nxt_d1 <= ULPI_NXT;
ulpi_nxt_d2 <= ulpi_nxt_d1;
ulpi_nxt_d3 <= ulpi_nxt_d2;
if rx_status_i='1' then
status <= ulpi_data_in;
end if;
if reset='1' then
status <= (others => '0');
end if;
end if;
end process;
p_tx_state: process(clock, reset)
begin
if rising_edge(clock) then
ulpi_stop <= '0';
tx_reg_i <= '0';
case state is
when idle =>
ulpi_data_out <= X"00";
if reg_read='1' and rx_reg_i='0' then
ulpi_data_out <= "11" & reg_address;
state <= reading;
elsif reg_write='1' and tx_reg_i='0' then
ulpi_data_out <= "10" & reg_address;
state <= writing;
elsif tx_valid = '1' and tx_start = '1' and ULPI_DIR='0' then
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
state <= transmit;
end if;
when reading =>
if rx_reg_i='1' then
ulpi_data_out <= X"00";
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing =>
if ULPI_NXT='1' then
ulpi_data_out <= reg_wdata;
state <= writing_data;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when writing_data =>
if ULPI_NXT='1' and ULPI_DIR='0' then
tx_reg_i <= '1';
ulpi_stop <= '1';
state <= idle;
end if;
if ulpi_dir_d1='1' then
state <= idle; -- terminate current tx
ulpi_data_out <= X"00";
end if;
when transmit =>
if ULPI_NXT = '1' then
if ulpi_last='1' or tx_valid = '0' then
ulpi_data_out <= X"00";
ulpi_stop <= '1';
state <= idle;
else
ulpi_data_out <= tx_data;
ulpi_last <= tx_last;
end if;
end if;
when others =>
null;
end case;
if reset='1' then
state <= idle;
ulpi_stop <= '0';
ulpi_last <= '0';
end if;
end if;
end process;
p_next: process(state, tx_valid, tx_start, rx_reg_i, tx_reg_i, ULPI_DIR, ULPI_NXT, ulpi_last, reg_read, reg_write)
begin
case state is
when idle =>
tx_next <= not ULPI_DIR and tx_valid and tx_start;
if reg_read='1' and rx_reg_i='0' then
tx_next <= '0';
end if;
if reg_write='1' and tx_reg_i='0' then
tx_next <= '0';
end if;
when transmit =>
tx_next <= ULPI_NXT and tx_valid and not ulpi_last;
when others =>
tx_next <= '0';
end case;
end process;
ULPI_STP <= ulpi_stop;
ULPI_DATA <= ulpi_data_out when ULPI_DIR='0' and ulpi_dir_d1='0' else (others => 'Z');
end gideon;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--******************************************************************************
--*** ***
--*** ALTERA FLOATING POINT DATAPATH COMPILER ***
--*** ***
--*** HCC_CASTYTOD.VHD ***
--*** ***
--*** Function: Cast Internal Double to IEEE754 ***
--*** Double ***
--*** ***
--*** 14/07/07 ML ***
--*** ***
--*** (c) 2007 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** 27/05/09 - fixed zero/infinity/nan mantissa cases, also output 0 if ***
--*** mantissa is 0 ***
--*** 29/06/09 - look at bits 12&13 of expnode to check zero & max *** ***
--*** ***
--*** ***
--******************************************************************************
--******************************************************************************
--*** Latency: ***
--*** 4 + swNormSpeed + swDoubleSpeed + swRoundConvert*(1 + swDoubleSpeed); ***
--******************************************************************************
ENTITY hcc_castytod IS
GENERIC (
roundconvert : integer := 0; -- global switch - round all ieee<=>y conversion when '1'
normspeed : positive := 3; -- 1,2, or 3 pipes for norm core
doublespeed : integer := 1; -- '0' for unpiped adder, '1' for piped adder
synthesize : integer := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa : IN STD_LOGIC_VECTOR (77 DOWNTO 1);
aasat, aazip : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
END hcc_castytod;
ARCHITECTURE rtl OF hcc_castytod IS
constant signdepth : positive := 3 + (roundconvert*doublespeed) + normspeed + roundconvert*(1 + doublespeed);
constant exptopffdepth : positive := 2 + (roundconvert*doublespeed);
constant expbotffdepth : positive := normspeed;
constant satffdepth : positive := 3 + (roundconvert*doublespeed) + normspeed;
type absfftype IS ARRAY (3 DOWNTO 1) OF STD_LOGIC_VECTOR (64 DOWNTO 1);
type exptopfftype IS ARRAY (exptopffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
type expbotdelfftype IS ARRAY (expbotffdepth DOWNTO 1) OF STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zerovec : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal aaff : STD_LOGIC_VECTOR (77 DOWNTO 1);
signal absinvnode, absnode, absff, absolute : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal countnorm : STD_LOGIC_VECTOR (6 DOWNTO 1);
signal fracout, fracoutff : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal exptopff : exptopfftype;
signal expbotff : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal expbotdelff : expbotdelfftype;
signal exponent : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal satff, zipff : STD_LOGIC_VECTOR (satffdepth DOWNTO 1);
signal signff : STD_LOGIC_VECTOR (signdepth DOWNTO 1);
signal zeronumber : STD_LOGIC_VECTOR (64 DOWNTO 1);
signal zeronumberff : STD_LOGIC_VECTOR (1+normspeed DOWNTO 1);
signal roundoverflow : STD_LOGIC_VECTOR (53 DOWNTO 1);
signal roundoverflowff : STD_LOGIC;
signal expnode : STD_LOGIC_VECTOR (13 DOWNTO 1);
signal zeroexpnode, maxexpnode : STD_LOGIC;
signal zeromantissanode : STD_LOGIC;
signal zeroexponentnode, maxexponentnode : STD_LOGIC;
signal roundbit : STD_LOGIC;
-- common to all output flows
signal mantissaoutff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoutff : STD_LOGIC_VECTOR (11 DOWNTO 1);
-- common to all rounded output flows
signal mantissaroundff : STD_LOGIC_VECTOR (52 DOWNTO 1);
signal exponentoneff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissaff : STD_LOGIC;
signal zeroexponentff, maxexponentff : STD_LOGIC;
-- only for doublespeed rounded output
signal mantissaroundnode : STD_LOGIC_VECTOR (54 DOWNTO 1);
signal exponenttwoff : STD_LOGIC_VECTOR (11 DOWNTO 1);
signal zeromantissadelff : STD_LOGIC;
signal zeroexponentdelff, maxexponentdelff : STD_LOGIC;
-- debug
signal aaexp : STD_LOGIC_VECTOR(13 DOWNTO 1);
signal aaman : STD_LOGIC_VECTOR(64 DOWNTO 1);
signal ccsgn : STD_LOGIC;
signal ccexp : STD_LOGIC_VECTOR(11 DOWNTO 1);
signal ccman : STD_LOGIC_VECTOR(52 DOWNTO 1);
component hcc_addpipeb
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_addpipes
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
carryin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component hcc_normus64 IS
GENERIC (pipes : positive := 1);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
fracin : IN STD_LOGIC_VECTOR (64 DOWNTO 1);
countout : OUT STD_LOGIC_VECTOR (6 DOWNTO 1);
fracout : OUT STD_LOGIC_VECTOR (64 DOWNTO 1)
);
end component;
BEGIN
gza: FOR k IN 1 TO 64 GENERATE
zerovec(k) <= '0';
END GENERATE;
pclk: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 77 LOOP
aaff(k) <= '0';
END LOOP;
FOR k IN 1 TO 64 LOOP
fracoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO exptopffdepth LOOP
FOR j IN 1 TO 13 LOOP
exptopff(k)(j) <= '0';
END LOOP;
END LOOP;
FOR k IN 1 TO satffdepth LOOP
satff(k) <= '0';
zipff(k) <= '0';
END LOOP;
FOR k IN 1 TO signdepth LOOP
signff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
aaff <= aa;
fracoutff <= fracout;
exptopff(1)(13 DOWNTO 1) <= aaff(13 DOWNTO 1) + "0000000000100";
FOR k IN 2 TO exptopffdepth LOOP
exptopff(k)(13 DOWNTO 1) <= exptopff(k-1)(13 DOWNTO 1);
END LOOP;
satff(1) <= aasat;
FOR k IN 2 TO satffdepth LOOP
satff(k) <= satff(k-1);
END LOOP;
zipff(1) <= aazip;
FOR k IN 2 TO satffdepth LOOP
zipff(k) <= zipff(k-1);
END LOOP;
signff(1) <= aaff(77);
FOR k IN 2 TO signdepth LOOP
signff(k) <= signff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
gna: FOR k IN 1 TO 64 GENERATE
absinvnode(k) <= aaff(k+13) XOR aaff(77);
END GENERATE;
--*** APPLY ROUNDING TO ABS VALUE (IF REQUIRED) ***
gnb: IF ((roundconvert = 0) OR
(roundconvert = 1 AND doublespeed = 0)) GENERATE
gnc: IF (roundconvert = 0) GENERATE
absnode <= absinvnode;
END GENERATE;
gnd: IF (roundconvert = 1) GENERATE
absnode <= absinvnode + (zerovec(63 DOWNTO 1) & aaff(77));
END GENERATE;
pnb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 64 LOOP
absff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
absff <= absnode;
END IF;
END IF;
END PROCESS;
absolute <= absff;
END GENERATE;
gnd: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
gsa: IF (synthesize = 0) GENERATE
absone: hcc_addpipeb
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
gsb: IF (synthesize = 1) GENERATE
abstwo: hcc_addpipes
GENERIC MAP (width=>64,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>absinvnode,bb=>zerovec,carryin=>aaff(77),
cc=>absolute);
END GENERATE;
END GENERATE;
zeronumber(1) <= absolute(1);
gzma: FOR k IN 2 TO 64 GENERATE
zeronumber(k) <= zeronumber(k-1) OR absolute(k);
END GENERATE;
pzm: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO normspeed+1 LOOP
zeronumberff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
zeronumberff(1) <= NOT(zeronumber(64));
FOR k IN 2 TO 1+normspeed LOOP
zeronumberff(k) <= zeronumberff(k-1);
END LOOP;
END IF;
END IF;
END PROCESS;
--******************************************************************
--*** NORMALIZE HERE - 1-3 pipes (countnorm output after 1 pipe) ***
--******************************************************************
normcore: hcc_normus64
GENERIC MAP (pipes=>normspeed)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
fracin=>absolute,
countout=>countnorm,fracout=>fracout);
--****************************
--*** exponent bottom half ***
--****************************
gxa: IF (expbotffdepth = 1) GENERATE
pxa: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 13 LOOP
expbotff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotff(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
END IF;
END IF;
END PROCESS;
exponent <= expbotff;
END GENERATE;
gxb: IF (expbotffdepth > 1) GENERATE
pxb: PROCESS (sysclk, reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO expbotffdepth LOOP
FOR j IN 1 TO 13 LOOP
expbotdelff(k)(j) <= '0';
END LOOP;
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
expbotdelff(1)(13 DOWNTO 1) <= exptopff(exptopffdepth)(13 DOWNTO 1) - ("0000000" & countnorm);
FOR k IN 2 TO expbotffdepth LOOP
expbotdelff(k)(13 DOWNTO 1) <= expbotdelff(k-1)(13 DOWNTO 1);
END LOOP;
END IF;
END IF;
END PROCESS;
exponent <= expbotdelff(expbotffdepth)(13 DOWNTO 1);
END GENERATE;
--**************************************
--*** CALCULATE OVERFLOW & UNDERFLOW ***
--**************************************
groa: IF (roundconvert = 1) GENERATE
roundoverflow(1) <= fracout(10);
grob: FOR k IN 2 TO 53 GENERATE
roundoverflow(k) <= roundoverflow(k-1) AND fracout(k+9);
END GENERATE;
prca: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
roundoverflowff <= '0';
ELSIF (rising_edge(sysclk)) THEN
IF (enable = '1') THEN
roundoverflowff <= roundoverflow(53);
END IF;
END IF;
END PROCESS;
END GENERATE;
-- fracff, expnode, roundoverflowff (if used) aligned here, depth of satffdepth
zeroexpnode <= NOT(expnode(13) OR expnode(12) OR
expnode(11) OR expnode(10) OR expnode(9) OR
expnode(8) OR expnode(7) OR expnode(6) OR expnode(5) OR
expnode(4) OR expnode(3) OR expnode(2) OR expnode(1));
maxexpnode <= NOT(expnode(13)) AND NOT(expnode(12)) AND
expnode(11) AND expnode(10) AND expnode(9) AND
expnode(8) AND expnode(7) AND expnode(6) AND expnode(5) AND
expnode(4) AND expnode(3) AND expnode(2) AND expnode(1);
-- '1' when true
-- 27/05/09 make sure all conditions are covered
groc: IF (roundconvert = 0) GENERATE
zeromantissanode <= expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth);
END GENERATE;
grod: IF (roundconvert = 1) GENERATE
zeromantissanode <= roundoverflowff OR expnode(12) OR expnode(13) OR
zeroexpnode OR maxexpnode OR
zipff(satffdepth) OR satff(satffdepth) OR
zeronumberff(1+normspeed);
END GENERATE;
zeroexponentnode <= zeroexpnode OR expnode(13) OR
zipff(satffdepth) OR zeronumberff(1+normspeed);
-- 27/05/09 - make sure than exp = -1 doesn't trigger max nod
maxexponentnode <= (maxexpnode AND NOT(expnode(12)) AND NOT(expnode(13))) OR
(expnode(12) AND NOT(expnode(13))) OR
satff(satffdepth);
--**********************
--*** OUTPUT SECTION ***
--**********************
goa: IF (roundconvert = 0) GENERATE
expnode <= exponent;
roundbit <= '0';
poa: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= '0';
END LOOP;
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= fracoutff(k+10) AND NOT(zeromantissanode);
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (expnode(k) AND NOT(zeroexponentnode)) OR maxexponentnode;
END LOOP;
END IF;
END PROCESS;
END GENERATE;
gob: IF (roundconvert = 1 AND doublespeed = 0) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
pob: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaroundff(k) <= '0';
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
ELSIF (rising_edge(sysclk)) THEN
mantissaroundff <= fracoutff(62 DOWNTO 11) + (zerovec(51 DOWNTO 1) & roundbit);
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundff(k) AND NOT(zeromantissaff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponentoneff(k) AND NOT(zeroexponentff)) OR maxexponentff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
END IF;
END PROCESS;
END GENERATE;
goc: IF (roundconvert = 1 AND doublespeed = 1) GENERATE
expnode <= exponent + (zerovec(12 DOWNTO 1) & roundoverflowff);
-- round to nearest even
roundbit <= (fracoutff(11) AND fracoutff(10)) OR
(NOT(fracoutff(11)) AND fracoutff(10) AND
(fracoutff(9) OR fracoutff(8) OR fracoutff(7)));
poc: PROCESS (sysclk,reset)
BEGIN
IF (reset = '1') THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= '0';
END LOOP;
FOR k IN 1 TO 11 LOOP
exponentoneff(k) <= '0';
exponenttwoff(k) <= '0';
exponentoutff(k) <= '0';
END LOOP;
zeromantissaff <= '0';
zeroexponentff <= '0';
maxexponentff <= '0';
zeromantissadelff <= '0';
zeroexponentdelff <= '0';
maxexponentdelff <= '0';
ELSIF (rising_edge(sysclk)) THEN
FOR k IN 1 TO 52 LOOP
mantissaoutff(k) <= mantissaroundnode(k) AND NOT(zeromantissadelff);
END LOOP;
exponentoneff <= expnode(11 DOWNTO 1);
exponenttwoff <= exponentoneff;
FOR k IN 1 TO 11 LOOP
exponentoutff(k) <= (exponenttwoff(k) AND NOT(zeroexponentdelff)) OR maxexponentdelff;
END LOOP;
-- '1' when true
zeromantissaff <= zeromantissanode;
zeroexponentff <= zeroexponentnode;
maxexponentff <= maxexponentnode;
zeromantissadelff <= zeromantissaff;
zeroexponentdelff <= zeroexponentff;
maxexponentdelff <= maxexponentff;
END IF;
END PROCESS;
aroa: IF (synthesize = 0) GENERATE
roone: hcc_addpipeb
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
arob: IF (synthesize = 1) GENERATE
rotwo: hcc_addpipes
GENERIC MAP (width=>54,pipes=>2)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>fracoutff(64 DOWNTO 11),bb=>zerovec(54 DOWNTO 1),carryin=>roundbit,
cc=>mantissaroundnode);
END GENERATE;
END GENERATE;
--*** OUTPUTS ***
cc(64) <= signff(signdepth);
cc(63 DOWNTO 53) <= exponentoutff;
cc(52 DOWNTO 1) <= mantissaoutff;
--*** DEBUG ***
aaexp <= aa(13 DOWNTO 1);
aaman <= aa(77 DOWNTO 14);
ccsgn <= signff(signdepth);
ccexp <= exponentoutff;
ccman <= mantissaoutff;
END rtl;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity RS232Write is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
DATAWR : in std_logic_vector(7 downto 0);
NBaud : in std_logic_vector(3 downto 0);
EOT : out std_logic;
Tx : out std_logic
);
end RS232Write;
architecture moore of RS232Write is
signal CTRL : std_logic_vector(3 downto 0);
signal FBaud : std_logic;
component BaudRate
port(
RST : in std_logic;
CLK : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end component;
component RightShift
port(
RST : in std_logic;
CLK : in std_logic;
CTRL : in std_logic_vector(3 downto 0);
DATAWR : in std_logic_vector(7 downto 0);
Tx : out std_logic
);
end component;
component FsmWrite
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOT : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end component;
begin
U00 : BaudRate port map(RST,CLK,NBaud,FBaud);
U01 : RightShift port map(RST,CLK,CTRL,DATAWR,Tx);
U02 : FsmWrite port map(RST,CLK,STR,FBaud,EOT,CTRL);
end moore;
|
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity RS232Write is
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
DATAWR : in std_logic_vector(7 downto 0);
NBaud : in std_logic_vector(3 downto 0);
EOT : out std_logic;
Tx : out std_logic
);
end RS232Write;
architecture moore of RS232Write is
signal CTRL : std_logic_vector(3 downto 0);
signal FBaud : std_logic;
component BaudRate
port(
RST : in std_logic;
CLK : in std_logic;
NBaud : in std_logic_vector(3 downto 0); -- Number of Bauds by second
FBaud : out std_logic -- Base frecuency
);
end component;
component RightShift
port(
RST : in std_logic;
CLK : in std_logic;
CTRL : in std_logic_vector(3 downto 0);
DATAWR : in std_logic_vector(7 downto 0);
Tx : out std_logic
);
end component;
component FsmWrite
port(
RST : in std_logic;
CLK : in std_logic;
STR : in std_logic;
FBaud : in std_logic;
EOT : out std_logic;
CTRL : out std_logic_vector(3 downto 0)
);
end component;
begin
U00 : BaudRate port map(RST,CLK,NBaud,FBaud);
U01 : RightShift port map(RST,CLK,CTRL,DATAWR,Tx);
U02 : FsmWrite port map(RST,CLK,STR,FBaud,EOT,CTRL);
end moore;
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_4 is
SIGNAL mem : UNSIGNED(31 downto 0);
begin
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
mem <= TO_UNSIGNED( 0, 32);
ELSE
IF INPUT_1_valid = '1' THEN
mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
ELSE
mem <= mem;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
|
---------------------------------------------------------------------
-- TITLE: Arithmetic Logic Unit
-- AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/8/01
-- FILENAME: alu.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Implements the ALU.
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.mlite_pack.all;
entity coproc_4 is
port(
clock : in std_logic;
reset : in std_logic;
INPUT_1 : in std_logic_vector(31 downto 0);
INPUT_1_valid : in std_logic;
OUTPUT_1 : out std_logic_vector(31 downto 0)
);
end; --comb_alu_1
architecture logic of coproc_4 is
SIGNAL mem : UNSIGNED(31 downto 0);
begin
-------------------------------------------------------------------------
process (clock, reset)
begin
IF clock'event AND clock = '1' THEN
IF reset = '1' THEN
mem <= TO_UNSIGNED( 0, 32);
ELSE
IF INPUT_1_valid = '1' THEN
mem <= UNSIGNED(INPUT_1) + TO_UNSIGNED( 4, 32);
ELSE
mem <= mem;
END IF;
END IF;
END IF;
end process;
-------------------------------------------------------------------------
OUTPUT_1 <= STD_LOGIC_VECTOR( mem );
end; --architecture logic
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2011, Aeroflex Gaisler AB - all rights reserved.
--
-- ANY USE OR REDISTRIBUTION IN PART OR IN WHOLE MUST BE HANDLED IN
-- ACCORDANCE WITH THE GAISLER LICENSE AGREEMENT AND MUST BE APPROVED
-- IN ADVANCE IN WRITING.
------------------------------------------------------------------------------
--
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library synplify;
entity spictrl_unisim is
generic (
slvselen : integer range 0 to 1 := 0;
slvselsz : integer range 1 to 32 := 1);
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector((slvselsz-1) downto 0));
end spictrl_unisim;
architecture rtl of spictrl_unisim is
-- Combination 0, 32 slave selects
component spictrl_unisim_comb0
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector(31 downto 0));
end component;
-- Combination 1, 32 disabled slave selects
component spictrl_unisim_comb1
port (
rstn : in std_ulogic;
clk : in std_ulogic;
-- APB signals
apbi_psel : in std_ulogic;
apbi_penable : in std_ulogic;
apbi_paddr : in std_logic_vector(31 downto 0);
apbi_pwrite : in std_ulogic;
apbi_pwdata : in std_logic_vector(31 downto 0);
apbi_testen : in std_ulogic;
apbi_testrst : in std_ulogic;
apbi_scanen : in std_ulogic;
apbi_testoen : in std_ulogic;
apbo_prdata : out std_logic_vector(31 downto 0);
apbo_pirq : out std_ulogic;
-- SPI signals
spii_miso : in std_ulogic;
spii_mosi : in std_ulogic;
spii_sck : in std_ulogic;
spii_spisel : in std_ulogic;
spii_astart : in std_ulogic;
spii_cstart : in std_ulogic;
spio_miso : out std_ulogic;
spio_misooen : out std_ulogic;
spio_mosi : out std_ulogic;
spio_mosioen : out std_ulogic;
spio_sck : out std_ulogic;
spio_sckoen : out std_ulogic;
spio_enable : out std_ulogic;
spio_astart : out std_ulogic;
spio_aready : out std_ulogic;
slvsel : out std_logic_vector(31 downto 0));
end component;
begin
slvselact : if slvselen /= 0 generate
spic0 : spictrl_unisim_comb0
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi_psel,
apbi_penable => apbi_penable,
apbi_paddr => apbi_paddr,
apbi_pwrite => apbi_pwrite,
apbi_pwdata => apbi_pwdata,
apbi_testen => apbi_testen,
apbi_testrst => apbi_testrst,
apbi_scanen => apbi_scanen,
apbi_testoen => apbi_testoen,
apbo_prdata => apbo_prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii_miso,
spii_mosi => spii_mosi,
spii_sck => spii_sck,
spii_spisel => spii_spisel,
spii_astart => spii_astart,
spii_cstart => spii_cstart,
spio_miso => spio_miso,
spio_misooen => spio_misooen,
spio_mosi => spio_mosi,
spio_mosioen => spio_mosioen,
spio_sck => spio_sck,
spio_sckoen => spio_sckoen,
spio_enable => spio_enable,
spio_astart => spio_astart,
spio_aready => spio_aready,
slvsel => slvsel);
end generate;
noslvsel : if slvselen = 0 generate
spic0 : spictrl_unisim_comb1
port map (
rstn => rstn,
clk => clk,
-- APB signals
apbi_psel => apbi_psel,
apbi_penable => apbi_penable,
apbi_paddr => apbi_paddr,
apbi_pwrite => apbi_pwrite,
apbi_pwdata => apbi_pwdata,
apbi_testen => apbi_testen,
apbi_testrst => apbi_testrst,
apbi_scanen => apbi_scanen,
apbi_testoen => apbi_testoen,
apbo_prdata => apbo_prdata,
apbo_pirq => apbo_pirq,
-- SPI signals
spii_miso => spii_miso,
spii_mosi => spii_mosi,
spii_sck => spii_sck,
spii_spisel => spii_spisel,
spii_astart => spii_astart,
spii_cstart => spii_cstart,
spio_miso => spio_miso,
spio_misooen => spio_misooen,
spio_mosi => spio_mosi,
spio_mosioen => spio_mosioen,
spio_sck => spio_sck,
spio_sckoen => spio_sckoen,
spio_enable => spio_enable,
spio_astart => spio_astart,
spio_aready => spio_aready,
slvsel => slvsel);
end generate;
end rtl;
|
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_unsigned.all;
-- library std;
library work;
use work.ComFlow_pkg.all;
entity usb_cypress_CY7C68014A_hal is
port (
-- external port, to CY7C68014A physical component
usb_ifclk : in std_logic;
usb_flaga : in std_logic;
usb_flagb : in std_logic;
usb_flagc : in std_logic;
usb_flagd : in std_logic;
usb_fd_io : inout std_logic_vector(15 downto 0);
usb_sloe : out std_logic;
usb_slrd : out std_logic;
usb_slwr : out std_logic;
usb_pktend : out std_logic;
usb_addr : out std_logic_vector(1 downto 0);
usb_rst : in std_logic;
-- connection to com manager
out_data_o : out std_logic_vector(15 downto 0);
out_data_wr_o : out std_logic;
out_data_full_i : in std_logic;
out_data_end_o : out std_logic;
in_data_i : in std_logic_vector(15 downto 0);
in_data_rd_o : out std_logic;
in_data_empty_i : in std_logic;
in_data_rdy_i : in std_logic
);
end usb_cypress_CY7C68014A_hal;
architecture rtl of usb_cypress_CY7C68014A_hal is
type sm is (idle, rd, wr, wr_end, WaitOneCycleBeforeWr);
signal state : sm := idle;
signal write_enable : std_logic;
signal flow_out_rdy_r : std_logic := '0';
signal usb_flaga_r : std_logic := '0';
signal status_rdy_r : std_logic := '0';
signal in_data_empty_i_r : std_logic := '0';
signal fifo_tx_flow_rdy_s : std_logic := '0';
begin
process(usb_ifclk,usb_rst)
begin
if (usb_rst = '0') then
state <= idle;
out_data_wr_o <= '0';
in_data_rd_o <= '0';
out_data_end_o <= '0';
usb_addr <= "00"; -- Connected to End Point 2 - OUT - (EP2 = "00")
usb_sloe <= '1';
usb_slrd <= '1';
usb_slwr <= '1';
usb_pktend <= '1';
write_enable <= '0';
usb_fd_io <= (others => 'Z');
flow_out_rdy_r <= '0';
-- end_status_wr_s <='0';
-- status_nb := (others=>'0');
in_data_empty_i_r <= '0';
elsif (rising_edge(usb_ifclk)) then
flow_out_rdy_r <= in_data_rdy_i;
in_data_empty_i_r <= in_data_empty_i;
case state is
when idle =>
-- EZ-USB Interface : Do Nothing
usb_addr <= "00"; -- Connected to End Point 2 - OUT - (EP2 = "00")
usb_sloe <= '1';
usb_slrd <= '1';
usb_slwr <= '1';
usb_pktend <= '1';
out_data_end_o <= '0';
usb_fd_io <= (others => 'Z');
out_data_wr_o <= '0';
in_data_rd_o <= '0';
-- end_status_wr_s <='0';
if (usb_flaga = '1') then -- flaga : EP2 pas vide
state <= rd;
usb_sloe <= '0';
usb_slrd <= '0';
-- elsif(status_rdy_s = '1' and usb_flagd='1')then
-- state <= ReturnStatus;
elsif (in_data_rdy_i = '1' and usb_flagd='1') then
state <= WaitOneCycleBeforeWr;
usb_sloe <= '1'; -- for test
in_data_rd_o <= '1';
else
state <= idle;
end if;
when rd =>
-- EZ-USB Interface : Read Request to EP2
usb_addr <= "00"; -- Connected to End Point 2 (EP2 = "00")
usb_slwr <= '1';
usb_pktend <= '1';
out_data_end_o <='0';
if (usb_flaga = '1') then
usb_sloe <= '0';
usb_slrd <= '0';
-- ecrire usb_fd_io dans fifo EP2
if (out_data_full_i = '0') then
--TODO: inversion octets pour USB
out_data_o(15 downto 8) <= usb_fd_io(7 downto 0);
out_data_o(7 downto 0) <= usb_fd_io(15 downto 8);
usb_fd_io <= (others => 'Z');
out_data_wr_o <= '1';
else
out_data_wr_o <= '0';
end if;
state <= rd;
else
out_data_wr_o <= '0';
usb_pktend <='0';
out_data_end_o <='1';
state <= idle;
end if;
when WaitOneCycleBeforeWr =>
state <= wr;
usb_addr <= "10";
when wr =>
usb_addr <= "10"; -- Connected to End Point 6 - IN - (EP6 = "10")
usb_sloe <= '1';
usb_slrd <= '1';
usb_pktend <= '1';
if(usb_flagd = '1') then -- flagd : EP6 pas plein
usb_slwr <= '0';
if (in_data_rdy_i = '1') then
in_data_rd_o <= '1';
-- TODO:inversion pour USB
usb_fd_io(7 downto 0) <= in_data_i(15 downto 8) ;
usb_fd_io(15 downto 8) <= in_data_i(7 downto 0) ;
state <= wr;
elsif(flow_out_rdy_r='1'and in_data_rdy_i = '0') then
-- in_data_rd_o <='0';
-- state <= wr_end;
-- usb_pktend <= '1';
-- usb_slwr <= '1';
usb_fd_io(7 downto 0) <= in_data_i(15 downto 8) ;
usb_fd_io(15 downto 8) <= in_data_i(7 downto 0) ;
usb_pktend <= '0';
in_data_rd_o <='0';
state <= wr_end;
else
state <= wr_end;
end if;
else
usb_slwr <= '1';
state <= idle;
end if;
-- Waiting for usb_start_read falling to zero
when wr_end =>
usb_pktend <= '1';
usb_slwr <= '1';
state <= idle;
end case;
end if;
end process;
end rtl;
|
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.genram_pkg.all;
entity gc_shiftreg is
generic (
g_size : integer);
port (
clk_i : in std_logic;
en_i : in std_logic;
d_i : in std_logic;
q_o : out std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0));
end gc_shiftreg;
architecture wrapper of gc_shiftreg is
component SRLC32E
port (
Q : out std_ulogic;
A : in std_logic_vector (4 downto 0);
CE : in std_ulogic;
CLK : in std_ulogic;
D : in std_ulogic);
end component;
signal a : std_logic_vector(4 downto 0);
signal sr : std_logic_vector(g_size-1 downto 0);
begin -- wrapper
assert (g_size <= 32) report "gc_shiftreg[xilinx]: forced SRL32 implementation can be done only for 32-bit or smaller shift registers" severity warning;
a <= std_logic_vector(resize(unsigned(a_i), 5));
gen_srl32 : if(g_size <= 32) generate
U_SRLC32 : SRLC32E
port map (
Q => q_o,
A => a,
CE => en_i,
CLK => clk_i,
D => d_i);
end generate gen_srl32;
gen_inferred : if(g_size > 32) generate
p_srl : process(clk_i)
begin
if rising_edge(clk_i) then
if en_i = '1' then
sr <= sr(sr'left - 1 downto 0) & d_i;
end if;
end if;
end process;
q_o <= sr(TO_INTEGER(unsigned(a_i)));
end generate gen_inferred;
end wrapper;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_fifo_v1_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_fifo_v1_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_fifo_v1_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
-- *************************************************************************
--
-- (c) Copyright 2010-2011 Xilinx, Inc. All rights reserved.
--
-- This file contains confidential and proprietary information
-- of Xilinx, Inc. and is protected under U.S. and
-- international copyright and other intellectual property
-- laws.
--
-- DISCLAIMER
-- This disclaimer is not a license and does not grant any
-- rights to the materials distributed herewith. Except as
-- otherwise provided in a valid license issued to you by
-- Xilinx, and to the maximum extent permitted by applicable
-- law: (1) THESE MATERIALS ARE MADE AVAILABLE "AS IS" AND
-- WITH ALL FAULTS, AND XILINX HEREBY DISCLAIMS ALL WARRANTIES
-- AND CONDITIONS, EXPRESS, IMPLIED, OR STATUTORY, INCLUDING
-- BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, NON-
-- INFRINGEMENT, OR FITNESS FOR ANY PARTICULAR PURPOSE; and
-- (2) Xilinx shall not be liable (whether in contract or tort,
-- including negligence, or under any other theory of
-- liability) for any loss or damage of any kind or nature
-- related to, arising under or in connection with these
-- materials, including for any direct, or any indirect,
-- special, incidental, or consequential loss or damage
-- (including loss of data, profits, goodwill, or any type of
-- loss or damage suffered as a result of any action brought
-- by a third party) even if such damage or loss was
-- reasonably foreseeable or Xilinx had been advised of the
-- possibility of the same.
--
-- CRITICAL APPLICATIONS
-- Xilinx products are not designed or intended to be fail-
-- safe, or for use in any application requiring fail-safe
-- performance, such as life-support or safety devices or
-- systems, Class III medical devices, nuclear facilities,
-- applications related to the deployment of airbags, or any
-- other applications that could lead to death, personal
-- injury, or severe property or environmental damage
-- (individually and collectively, "Critical
-- Applications"). Customer assumes the sole risk and
-- liability of any use of Xilinx products in Critical
-- Applications, subject only to applicable laws and
-- regulations governing limitations on product liability.
--
-- THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
-- PART OF THIS FILE AT ALL TIMES.
--
-- *************************************************************************
--
-------------------------------------------------------------------------------
-- Filename: axi_sg_cntrl_strm.vhd
-- Description: This entity is MM2S control stream logic
--
-- VHDL-Standard: VHDL'93
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_misc.all;
library unisim;
use unisim.vcomponents.all;
library axi_sg_v4_1;
use axi_sg_v4_1.axi_sg_pkg.all;
library lib_fifo_v1_0;
library lib_cdc_v1_0;
library lib_pkg_v1_0;
use lib_pkg_v1_0.lib_pkg.clog2;
use lib_pkg_v1_0.lib_pkg.max2;
-------------------------------------------------------------------------------
entity axi_sg_cntrl_strm is
generic(
C_PRMRY_IS_ACLK_ASYNC : integer range 0 to 1 := 0;
-- Primary MM2S/S2MM sync/async mode
-- 0 = synchronous mode - all clocks are synchronous
-- 1 = asynchronous mode - Primary data path channels (MM2S and S2MM)
-- run asynchronous to AXI Lite, DMA Control,
-- and SG.
C_PRMY_CMDFIFO_DEPTH : integer range 1 to 16 := 1;
-- Depth of DataMover command FIFO
C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH : integer range 32 to 32 := 32;
-- Master AXI Control Stream Data Width
C_FAMILY : string := "virtex7"
-- Target FPGA Device Family
);
port (
-- Secondary clock / reset
m_axi_sg_aclk : in std_logic ; --
m_axi_sg_aresetn : in std_logic ; --
--
-- Primary clock / reset --
axi_prmry_aclk : in std_logic ; --
p_reset_n : in std_logic ; --
--
-- MM2S Error --
mm2s_stop : in std_logic ; --
--
-- Control Stream FIFO write signals (from axi_dma_mm2s_sg_if) --
cntrlstrm_fifo_wren : in std_logic ; --
cntrlstrm_fifo_din : in std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0); --
cntrlstrm_fifo_full : out std_logic ; --
--
--
-- Memory Map to Stream Control Stream Interface --
m_axis_mm2s_cntrl_tdata : out std_logic_vector --
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0); --
m_axis_mm2s_cntrl_tkeep : out std_logic_vector --
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0);--
m_axis_mm2s_cntrl_tvalid : out std_logic ; --
m_axis_mm2s_cntrl_tready : in std_logic ; --
m_axis_mm2s_cntrl_tlast : out std_logic --
);
end axi_sg_cntrl_strm;
-------------------------------------------------------------------------------
-- Architecture
-------------------------------------------------------------------------------
architecture implementation of axi_sg_cntrl_strm is
attribute DowngradeIPIdentifiedWarnings: string;
attribute DowngradeIPIdentifiedWarnings of implementation : architecture is "yes";
-------------------------------------------------------------------------------
-- Functions
-------------------------------------------------------------------------------
-- No Functions Declared
-------------------------------------------------------------------------------
-- Constants Declarations
-------------------------------------------------------------------------------
-- Number of words deep fifo needs to be
-- Only 5 app fields, but set to 8 so depth is a power of 2
constant CNTRL_FIFO_DEPTH : integer := max2(16,8 * C_PRMY_CMDFIFO_DEPTH);
-- Width of fifo rd and wr counts - only used for proper fifo operation
constant CNTRL_FIFO_CNT_WIDTH : integer := clog2(CNTRL_FIFO_DEPTH+1);
constant USE_LOGIC_FIFOS : integer := 0; -- Use Logic FIFOs
constant USE_BRAM_FIFOS : integer := 1; -- Use BRAM FIFOs
-------------------------------------------------------------------------------
-- Signal / Type Declarations
-------------------------------------------------------------------------------
-- FIFO signals
signal cntrl_fifo_rden : std_logic := '0';
signal cntrl_fifo_empty : std_logic := '0';
signal cntrl_fifo_dout, follower_reg_mm2s : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH downto 0) := (others => '0');
signal cntrl_fifo_dvalid: std_logic := '0';
signal cntrl_tdata : std_logic_vector
(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal cntrl_tkeep : std_logic_vector
((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal follower_full_mm2s, follower_empty_mm2s : std_logic := '0';
signal cntrl_tvalid : std_logic := '0';
signal cntrl_tready : std_logic := '0';
signal cntrl_tlast : std_logic := '0';
signal sinit : std_logic := '0';
signal m_valid : std_logic := '0';
signal m_ready : std_logic := '0';
signal m_data : std_logic_vector(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0) := (others => '0');
signal m_strb : std_logic_vector((C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH/8)-1 downto 0) := (others => '0');
signal m_last : std_logic := '0';
signal skid_rst : std_logic := '0';
-------------------------------------------------------------------------------
-- Begin architecture logic
-------------------------------------------------------------------------------
begin
-- All bytes always valid
cntrl_tkeep <= (others => '1');
-- Primary Clock is synchronous to Secondary Clock therfore
-- instantiate a sync fifo.
GEN_SYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 0 generate
signal mm2s_stop_d1 : std_logic := '0';
signal mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
begin
-- reset on hard reset or mm2s stop
sinit <= not m_axi_sg_aresetn or mm2s_stop;
-- Generate Synchronous FIFO
I_CNTRL_FIFO : entity lib_fifo_v1_0.sync_fifo_fg
generic map (
C_FAMILY => C_FAMILY ,
C_MEMORY_TYPE => USE_LOGIC_FIFOS,
C_WRITE_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_WRITE_DEPTH => CNTRL_FIFO_DEPTH ,
C_READ_DATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1,
C_READ_DEPTH => CNTRL_FIFO_DEPTH ,
C_PORTS_DIFFER => 0,
C_HAS_DCOUNT => 0, --req for proper fifo operation
C_HAS_ALMOST_FULL => 0,
C_HAS_RD_ACK => 0,
C_HAS_RD_ERR => 0,
C_HAS_WR_ACK => 0,
C_HAS_WR_ERR => 0,
C_RD_ACK_LOW => 0,
C_RD_ERR_LOW => 0,
C_WR_ACK_LOW => 0,
C_WR_ERR_LOW => 0,
C_PRELOAD_REGS => 1,-- 1 = first word fall through
C_PRELOAD_LATENCY => 0 -- 0 = first word fall through
-- C_USE_EMBEDDED_REG => 1 -- 0 ;
)
port map (
Clk => m_axi_sg_aclk ,
Sinit => sinit ,
Din => cntrlstrm_fifo_din ,
Wr_en => cntrlstrm_fifo_wren ,
Rd_en => cntrl_fifo_rden ,
Dout => cntrl_fifo_dout ,
Full => cntrlstrm_fifo_full ,
Empty => cntrl_fifo_empty ,
Almost_full => open ,
Data_count => open ,
Rd_ack => open ,
Rd_err => open ,
Wr_ack => open ,
Wr_err => open
);
-- I_UPDT_DATA_FIFO : entity proc_common_srl_fifo_v5_0.srl_fifo_f
-- generic map (
-- C_DWIDTH => 33 ,
-- C_DEPTH => 24 ,
-- C_FAMILY => C_FAMILY
-- )
-- port map (
-- Clk => m_axi_sg_aclk ,
-- Reset => sinit ,
-- FIFO_Write => cntrlstrm_fifo_wren ,
-- Data_In => cntrlstrm_fifo_din ,
-- FIFO_Read => cntrl_fifo_rden ,
-- Data_Out => cntrl_fifo_dout ,
-- FIFO_Empty => cntrl_fifo_empty ,
-- FIFO_Full => cntrlstrm_fifo_full,
-- Addr => open
-- );
cntrl_fifo_rden <= follower_empty_mm2s and (not cntrl_fifo_empty);
VALID_REG_MM2S_ACTIVE : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0' or (cntrl_tready = '1' and follower_full_mm2s = '1'))then
-- follower_reg_mm2s <= (others => '0');
follower_full_mm2s <= '0';
follower_empty_mm2s <= '1';
else
if (cntrl_fifo_rden = '1') then
-- follower_reg_mm2s <= sts_queue_dout;
follower_full_mm2s <= '1';
follower_empty_mm2s <= '0';
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE;
VALID_REG_MM2S_ACTIVE1 : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
follower_reg_mm2s <= (others => '0');
else
if (cntrl_fifo_rden = '1') then
follower_reg_mm2s <= cntrl_fifo_dout;
end if;
end if;
end if;
end process VALID_REG_MM2S_ACTIVE1;
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
-- cntrl_fifo_rden <= not cntrl_fifo_empty
-- and cntrl_tready;
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= follower_full_mm2s --not cntrl_fifo_empty
or (xfer_in_progress and mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= (cntrl_tvalid and follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
or (xfer_in_progress and mm2s_stop_re);
cntrl_tdata <= follower_reg_mm2s(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- Register stop to create re pulse for cleaning shutting down
-- stream out during soft reset.
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_d1 <= '0';
else
mm2s_stop_d1 <= mm2s_stop;
end if;
end if;
end process REG_STOP;
mm2s_stop_re <= mm2s_stop and not mm2s_stop_d1;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast and tvalid need to be asserted during soft
-- reset else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not m_axi_sg_aresetn;
---------------------------------------------------------------------------
-- Buffer AXI Signals
---------------------------------------------------------------------------
-- CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
-- generic map(
-- C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
-- )
-- port map(
-- -- System Ports
-- ACLK => m_axi_sg_aclk ,
-- ARST => skid_rst ,
-- skid_stop => mm2s_stop_re ,
-- -- Slave Side (Stream Data Input)
-- S_VALID => cntrl_tvalid ,
-- S_READY => cntrl_tready ,
-- S_Data => cntrl_tdata ,
-- S_STRB => cntrl_tkeep ,
-- S_Last => cntrl_tlast ,
-- -- Master Side (Stream Data Output
-- M_VALID => m_axis_mm2s_cntrl_tvalid ,
-- M_READY => m_axis_mm2s_cntrl_tready ,
-- M_Data => m_axis_mm2s_cntrl_tdata ,
-- M_STRB => m_axis_mm2s_cntrl_tkeep ,
-- M_Last => m_axis_mm2s_cntrl_tlast
-- );
m_axis_mm2s_cntrl_tvalid <= cntrl_tvalid;
cntrl_tready <= m_axis_mm2s_cntrl_tready;
m_axis_mm2s_cntrl_tdata <= cntrl_tdata;
m_axis_mm2s_cntrl_tkeep <= cntrl_tkeep;
m_axis_mm2s_cntrl_tlast <= cntrl_tlast;
end generate GEN_SYNC_FIFO;
-- Primary Clock is asynchronous to Secondary Clock therfore
-- instantiate an async fifo.
GEN_ASYNC_FIFO : if C_PRMRY_IS_ACLK_ASYNC = 1 generate
ATTRIBUTE async_reg : STRING;
signal mm2s_stop_reg : std_logic := '0'; -- CR605883
signal p_mm2s_stop_d1_cdc_tig : std_logic := '0';
signal p_mm2s_stop_d2 : std_logic := '0';
signal p_mm2s_stop_d3 : std_logic := '0';
signal p_mm2s_stop_re : std_logic := '0';
signal xfer_in_progress : std_logic := '0';
-- ATTRIBUTE async_reg OF p_mm2s_stop_d1_cdc_tig : SIGNAL IS "true";
-- ATTRIBUTE async_reg OF p_mm2s_stop_d2 : SIGNAL IS "true";
begin
-- reset on hard reset, soft reset, or mm2s error
sinit <= not p_reset_n or p_mm2s_stop_d2;
-- Generate Asynchronous FIFO
I_CNTRL_STRM_FIFO : entity axi_sg_v4_1.axi_sg_afifo_autord
generic map(
C_DWIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH + 1 ,
-- Temp work around for issue in async fifo model
C_DEPTH => CNTRL_FIFO_DEPTH-1 ,
C_CNT_WIDTH => CNTRL_FIFO_CNT_WIDTH ,
-- C_DEPTH => 31 ,
-- C_CNT_WIDTH => 5 ,
C_USE_BLKMEM => USE_LOGIC_FIFOS ,
C_FAMILY => C_FAMILY
)
port map(
-- Inputs
AFIFO_Ainit => sinit ,
AFIFO_Wr_clk => m_axi_sg_aclk ,
AFIFO_Wr_en => cntrlstrm_fifo_wren ,
AFIFO_Din => cntrlstrm_fifo_din ,
AFIFO_Rd_clk => axi_prmry_aclk ,
AFIFO_Rd_en => cntrl_fifo_rden ,
AFIFO_Clr_Rd_Data_Valid => '0' ,
-- Outputs
AFIFO_DValid => cntrl_fifo_dvalid ,
AFIFO_Dout => cntrl_fifo_dout ,
AFIFO_Full => cntrlstrm_fifo_full ,
AFIFO_Empty => cntrl_fifo_empty ,
AFIFO_Almost_full => open ,
AFIFO_Almost_empty => open ,
AFIFO_Wr_count => open ,
AFIFO_Rd_count => open ,
AFIFO_Corr_Rd_count => open ,
AFIFO_Corr_Rd_count_minus1 => open ,
AFIFO_Rd_ack => open
);
-----------------------------------------------------------------------
-- Control Stream OUT Side
-----------------------------------------------------------------------
-- Read if fifo is not empty and target is ready
cntrl_fifo_rden <= not cntrl_fifo_empty -- fifo has data
and cntrl_tready; -- target ready
-- Drive valid if fifo is not empty or in the middle
-- of transfer and stop issued.
cntrl_tvalid <= cntrl_fifo_dvalid
or (xfer_in_progress and p_mm2s_stop_re);
-- Pass data out to control channel with MSB driving tlast
cntrl_tlast <= cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH);
-- cntrl_tlast <= (cntrl_tvalid and cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH))
-- or (xfer_in_progress and p_mm2s_stop_re);
cntrl_tdata <= cntrl_fifo_dout(C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH-1 downto 0);
-- CR605883
-- Register stop to provide pure FF output for synchronizer
REG_STOP : process(m_axi_sg_aclk)
begin
if(m_axi_sg_aclk'EVENT and m_axi_sg_aclk = '1')then
if(m_axi_sg_aresetn = '0')then
mm2s_stop_reg <= '0';
else
mm2s_stop_reg <= mm2s_stop;
end if;
end if;
end process REG_STOP;
-- Double/triple register mm2s error into primary clock domain
-- Triple register to give two versions with min double reg for use
-- in rising edge detection.
IMP_SYNC_FLOP : entity lib_cdc_v1_0.cdc_sync
generic map (
C_CDC_TYPE => 1,
C_RESET_STATE => 0,
C_SINGLE_BIT => 1,
C_VECTOR_WIDTH => 32,
C_MTBF_STAGES => 2
)
port map (
prmry_aclk => '0',
prmry_resetn => '0',
prmry_in => mm2s_stop_reg,
prmry_vect_in => (others => '0'),
scndry_aclk => axi_prmry_aclk,
scndry_resetn => '0',
scndry_out => p_mm2s_stop_d2,
scndry_vect_out => open
);
REG_ERR2PRMRY : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(p_reset_n = '0')then
-- p_mm2s_stop_d1_cdc_tig <= '0';
-- p_mm2s_stop_d2 <= '0';
p_mm2s_stop_d3 <= '0';
else
--p_mm2s_stop_d1_cdc_tig <= mm2s_stop;
-- p_mm2s_stop_d1_cdc_tig <= mm2s_stop_reg;
-- p_mm2s_stop_d2 <= p_mm2s_stop_d1_cdc_tig;
p_mm2s_stop_d3 <= p_mm2s_stop_d2;
end if;
end if;
end process REG_ERR2PRMRY;
-- Rising edge pulse for use in shutting down stream output
p_mm2s_stop_re <= p_mm2s_stop_d2 and not p_mm2s_stop_d3;
-------------------------------------------------------------
-- Flag transfer in progress. If xfer in progress then
-- a fake tlast needs to be asserted during soft reset.
-- else no need of tlast.
-------------------------------------------------------------
TRANSFER_IN_PROGRESS : process(axi_prmry_aclk)
begin
if(axi_prmry_aclk'EVENT and axi_prmry_aclk = '1')then
if(cntrl_tlast = '1' and cntrl_tvalid = '1' and cntrl_tready = '1')then
xfer_in_progress <= '0';
elsif(xfer_in_progress = '0' and cntrl_tvalid = '1')then
xfer_in_progress <= '1';
end if;
end if;
end process TRANSFER_IN_PROGRESS;
skid_rst <= not p_reset_n;
CNTRL_SKID_BUF_I : entity axi_sg_v4_1.axi_sg_skid_buf
generic map(
C_WDATA_WIDTH => C_M_AXIS_MM2S_CNTRL_TDATA_WIDTH
)
port map(
-- System Ports
ACLK => axi_prmry_aclk ,
ARST => skid_rst ,
skid_stop => p_mm2s_stop_re ,
-- Slave Side (Stream Data Input)
S_VALID => cntrl_tvalid ,
S_READY => cntrl_tready ,
S_Data => cntrl_tdata ,
S_STRB => cntrl_tkeep ,
S_Last => cntrl_tlast ,
-- Master Side (Stream Data Output
M_VALID => m_axis_mm2s_cntrl_tvalid ,
M_READY => m_axis_mm2s_cntrl_tready ,
M_Data => m_axis_mm2s_cntrl_tdata ,
M_STRB => m_axis_mm2s_cntrl_tkeep ,
M_Last => m_axis_mm2s_cntrl_tlast
);
end generate GEN_ASYNC_FIFO;
end implementation;
|
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library techmap;
use techmap.gencomp.all;
-- pragma translate_off
library altera_mf;
use altera_mf.altpll;
-- pragma translate_on
entity cyclone3_pll is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic
);
end;
architecture rtl of cyclone3_pll is
component altpll
generic (
intended_device_family : string := "CycloneIII" ;
operation_mode : string := "NORMAL" ;
compensate_clock : string := "clock0";
inclk0_input_frequency : positive;
width_clock : positive := 6;
clk0_multiply_by : positive := 1;
clk0_divide_by : positive := 1;
clk1_multiply_by : positive := 1;
clk1_divide_by : positive := 1;
clk2_multiply_by : positive := 1;
clk2_divide_by : positive := 1;
port_clkena0 : string := "PORT_CONNECTIVITY";
port_clkena1 : string := "PORT_CONNECTIVITY";
port_clkena2 : string := "PORT_CONNECTIVITY";
port_clkena3 : string := "PORT_CONNECTIVITY";
port_clkena4 : string := "PORT_CONNECTIVITY";
port_clkena5 : string := "PORT_CONNECTIVITY"
);
port (
inclk : in std_logic_vector(1 downto 0);
clkena : in std_logic_vector(5 downto 0);
clk : out std_logic_vector(width_clock-1 downto 0);
locked : out std_logic
);
end component;
signal clkena : std_logic_vector (5 downto 0);
signal clkout : std_logic_vector (4 downto 0);
signal inclk : std_logic_vector (1 downto 0);
constant clk_period : integer := 1000000000/clk_freq;
constant CLK_MUL2X : integer := clk_mul * 2;
begin
clkena(5 downto 3) <= (others => '0');
clkena(0) <= '1';
clkena(1) <= '1' when sdramen = 1 else '0';
clkena(2) <= '1' when clk2xen = 1 else '0';
inclk <= '0' & inclk0;
c0 <= clkout(0); c0_2x <= clkout(2); e0 <= clkout(1);
sden : if sdramen = 1 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "ZERO_DELAY_BUFFER", inclk0_input_frequency => clk_period,
width_clock => 5, compensate_clock => "CLK1",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
-- Must use operation_mode other than "ZERO_DELAY_BUFFER" due to
-- tool issues with ZERO_DELAY_BUFFER and non-existent output clock
nosd : if sdramen = 0 generate
altpll0 : altpll
generic map (
intended_device_family => "Cyclone III",
operation_mode => "NORMAL", inclk0_input_frequency => clk_period,
width_clock => 5,
port_clkena1 => "PORT_UNUSED",
port_clkena2 => "PORT_UNUSED", port_clkena3 => "PORT_UNUSED",
port_clkena4 => "PORT_UNUSED", port_clkena5 => "PORT_UNUSED",
clk0_multiply_by => clk_mul, clk0_divide_by => clk_div,
clk1_multiply_by => clk_mul, clk1_divide_by => clk_div,
clk2_multiply_by => CLK_MUL2X, clk2_divide_by => clk_div)
port map ( clkena => clkena, inclk => inclk,
clk => clkout, locked => locked);
end generate;
end;
library ieee;
use ieee.std_logic_1164.all;
-- pragma translate_off
library altera_mf;
library grlib;
use grlib.stdlib.all;
-- pragma translate_on
library techmap;
use techmap.gencomp.all;
entity clkgen_cycloneiii is
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
sdramen : integer := 0;
sdinvclk : integer := 0;
pcien : integer := 0;
pcidll : integer := 0;
pcisysclk: integer := 0;
freq : integer := 25000;
clk2xen : integer := 0;
tech : integer := 0);
port (
clkin : in std_logic;
pciclkin: in std_logic;
clk : out std_logic; -- main clock
clkn : out std_logic; -- inverted main clock
clk2x : out std_logic; -- double clock
sdclk : out std_logic; -- SDRAM clock
pciclk : out std_logic; -- PCI clock
cgi : in clkgen_in_type;
cgo : out clkgen_out_type);
end;
architecture rtl of clkgen_cycloneiii is
constant VERSION : integer := 1;
constant CLKIN_PERIOD : integer := 20;
signal clk_i : std_logic;
signal clkint, pciclkint : std_logic;
signal pllclk, pllclkn : std_logic; -- generated clocks
signal s_clk : std_logic;
component cyclone3_pll
generic (
clk_mul : integer := 1;
clk_div : integer := 1;
clk_freq : integer := 25000;
clk2xen : integer := 0;
sdramen : integer := 0
);
port (
inclk0 : in std_ulogic;
c0 : out std_ulogic;
c0_2x : out std_ulogic;
e0 : out std_ulogic;
locked : out std_ulogic);
end component;
begin
cgo.pcilock <= '1';
-- c0 : if (PCISYSCLK = 0) generate
-- Clkint <= Clkin;
-- end generate;
-- c1 : if (PCISYSCLK = 1) generate
-- Clkint <= pciclkin;
-- end generate;
-- c2 : if (PCIEN = 1) generate
-- p0 : if (PCIDLL = 1) generate
-- pciclkint <= pciclkin;
-- pciclk <= pciclkint;
-- end generate;
-- p1 : if (PCIDLL = 0) generate
-- u0 : if (PCISYSCLK = 0) generate
-- pciclkint <= pciclkin;
-- end generate;
-- pciclk <= clk_i when (PCISYSCLK = 1) else pciclkint;
-- end generate;
-- end generate;
-- c3 : if (PCIEN = 0) generate
-- pciclk <= Clkint;
-- end generate;
c0: if (PCISYSCLK = 0) or (PCIEN = 0) generate
clkint <= clkin;
end generate c0;
c1: if PCIEN /= 0 generate
d0: if PCISYSCLK = 1 generate
clkint <= pciclkin;
end generate d0;
pciclk <= pciclkin;
end generate c1;
c2: if PCIEN = 0 generate
pciclk <= '0';
end generate c2;
sdclk_pll : cyclone3_pll
generic map (clk_mul, clk_div, freq, clk2xen, sdramen)
port map ( inclk0 => clkint, e0 => sdclk, c0 => s_clk, c0_2x => clk2x,
locked => cgo.clklock);
clk <= s_clk;
clkn <= not s_clk;
-- pragma translate_off
bootmsg : report_version
generic map (
"clkgen_cycloneiii" & ": altpll sdram/pci clock generator, version " & tost(VERSION),
"clkgen_cycloneiii" & ": Frequency " & tost(freq) & " KHz, PLL scaler " & tost(clk_mul) & "/" & tost(clk_div));
-- pragma translate_on
end;
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
XFCDfr1HDOhx50HsfgTURxczpXP2emtacLRrIRh40EDfpgGQkLOWm1e0nTUYecA/OSOfrqB80C/7
ZTe0XFVajA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
LJRwkIC0jUW/piEU2RsIJJMlMpXnmbaYsUhPA3pLZzMTkJCd7UId/BrmtcoBJzcFC4Xw/pBXQpih
8LnWx8hUvpTRL7SbWwXxhk7T44icvPr3BnotpwOiMOuMdo9dadaM9Z825icBOCdvBnX5so7JgVwE
bQPVlCsUfnx1MuYRuF8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RZ1nmRt71qFJueOX2poYVBkK+kJFvtg57Y5isUkUbfMl3jfXP2SrlxIxD5ugo6qj5a05fQLBCm6S
cnl1Zhwb5CIrXtycGWPPksKmUTgOuT4ohRSTpFKgQKU7Hs2dr3ut9SLBQiSjyk+GesxlULHZm7bj
EO/5lQQydikgyT793rgRPGN1bStbDXSDX42Rj/HLrkf1KsCwM1bHM1RZCOPu48LH7PAEKrnX12aM
9bDXylqLef/rvFFqLuxTh6uMS6aWA92d5R94eAFyRqqLr1jaJFpgYMmLiPmsBxiIs7Pe43w5Ta2M
jOrv472DXnyBs1gwD/SCZQLnegik9p1sMwbzIQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SHoX70mBVgQokgktfshpvtbHYCUEjXtz+fg6WJVCf5mFFwqRxNXz4pt9lRXS7T97YXNkBcmJQDc/
1u7EFOiLW7WFMsR0rt9h472TP/h1BjNCIPLpyp+AvGBIbm0q6imhhtp2T0PKbod+NXdaeqalmFcW
miczXSV+Kw7+vcNDOI8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
AfZ9d75Fo753l6VG8mCJkj+QXtpUI2pvKj0CEOOLrPmRXAtlpVaIg1UemhXY3vCk/nRduPJaYepX
6on4/R1PLE+WDYbyyipaqWT+wxu7tFapvduzY+3hZ+1qA0KUqJbJkIAhDDnktWdxA9c432qLAbWT
6KATZ93Cj0O6usKL2wsk7wtaxWywthOSTkWfsrvlRtQshJMIpJQANRKPABoatP4Sdm3+s9WSJvNi
JY1PMH38BnxXBcJl79/rnMtLPPv30cfL9UJTyBt2gcf2FYcOFuzQItrW7cLp1w+OZC+auK9s44GQ
M2+KbOFL2rkwANFqClHM+LShBh//fXNL7TAs7w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15456)
`protect data_block
WPzW3AjpmP5i//aUXhJDhrQGi8++Ur8sZa1lEH2HEmjNfAKwSCG6oN627UXZSCSmC7Q0jcmVPZds
/uRslihxcltiJTdH0lskDlCNLZ1gLwzuqzJopRb5xBEs7fAA0KCOKiZp+eJN6gY65DBL7BrVjB3d
17pAv4jk6nhAwSRjnSLbS1zPKwhngesj6Y4VPAQSswf5De91kMDX5arkBetpxdp2//Mlt2gl5KeW
899oDBZ9OQwnqZzRTQFWadSPrKvUUfpaqpm+2n5f5CowQMk8ZLgh9rAJjpD3/V18xCUGt6vu7Toe
9sv6sOgxoN+2wz/mM1oca7a+ZvDq582WeFs3gUxeXfLa1a4Xh2oVy45hI2NKCdaewHrIuRmpaQhC
MLqOUKXyqOAtqz70x88HnybrJX5ysomV6NSI5yPnOSNm0ARPLZwQ8iJtXgdjLXJOCbq9GCLdAFe+
E45XGjIm6hkUQ6lWK4TDLbPubbV0IBEFcu4/RYWFD5nlLThUrEGL5NxQGZpHamnsdH8Wbkizyeip
YqRX+NeFsYo4JvCHaCnkPRrdtQ7erW3nUvvJmaa8fY4jdvhpbY7AhF//32aI8jTe3KxoK8r56ZR1
wwH86gfrsn7RfnKNKpsFp73JZtDfNfD1QhJuYStEn5onppzxAcJ03DD26fUteGErq13aFkEkBPaH
DnNZpVeboL4O9MwdjOxdhkDD7F0VXt0kwhWtXp0ql9L78YBhZTdfNTB+UaAI5rrEH5ZIesYBtZHi
j0YSZLvKbovxpD4Qs2sIWpFRwdBgjBfLDQKOLZDfMCEN/GPfkUf0Z561BPmSe5VE3cSu3osWlNhC
Lfx2HYLT2wozzKAW8EGlcMslrw63zQ7aF63jCjipteV5ccB+EGldbwnxyPaehZEt5H2njeOhH2A+
+sBKONyDkk+18T+dPyAwoiN+/AKHqgSuoCD2Vok08ZOM8o6f3yGWFGfI6lH+YUbXUKs1WQrGKfw1
n78bGhrgzNK65VxIp/xJyVAjirmL8zJ+hdkbBxuS+B1jKf0Y1CWiRto+AuHmQ4PR04bP0oBkoUhw
nL/c9Vwj5/6MfQg1vepZuOn/mBZ2nDBoR04ItF0aV/8PYzmgLCf0Vu4lbYEnXdv89Q2LrTBmlv9i
+P5KtALAw40b0ohm4cxcHpePZmg4f08Kuxo+GsDIfJJPR9VbyFZGJJC3Q0R8ZbZ2bulr2Sna8708
mozCfmcmbZQLY3incIfIs0HHki+/5Fma0wEp6w3gGFbdzk1enT0vTzsex2Zd2/3cQfGySD4IlH4F
NYEanD3KrCMR2iGrXztY3CmL76G8MBf7QmXzlx1PuQ/ZASAdSh2Wt2vN5HXKo+7Y1NS+Lv33+CWR
qTRbBbgjPNaWhJr0zTTh1gbFiX0bZNATxTVZpkGsOA9/FWp5rRizi48KiJmhggLS2b2RAm0UxMdv
39o3aD3mmYuk6+TVu+/KzGWAsVe+PvyQxTPV3394N02fKrqRmVoSDk8APgqF8Kai7S5FiL5X+K3u
TXqUOT7PAVL7r66HkkF9ko67xKY8fbLExehNc+uaxh35WrOdCjWShyuqLN8BI51HA4mywu4kabMW
KF8Tco3zN16z71EHOV8ymMtE5kQ/AzIUVDHTxn9esby09i32Rmx2jN0i8afkaupgZ2xwZfdl7OSj
Hmik0SYEUIE2RwGWFi0ZQwavZAfjJM0ChDSTDLf1zc1HbL92G/BGxExDzFDrTqfys3pblhUzxJdp
NClfciK7+degWiAT1y/ZcBssiiOOEs/+ZwLE+w6lbZayZopx7z/F6f2W/+Py+xMU9QyevODT8DJW
c2BNTfgMXwnWBOTaCWRxPC+kGIThQcxtp6QTSOH3/AkFvtoQISW6zqzf7BoCubMcAECE+EA8coP1
g6Jky1DME0uOsp3wDCJMe2EygNh5K2wrB3Oxg8r6bdNLFrKn0lirYYNZxBpjqR0DmIRnDougSRTH
zdNBKZ5N9CHDAZJC5Ngnw4pUlNrF8vfoe8HZOU5vr84/5wZJAFOBJxU+MJimgzfjWzvVtL9aiVUS
JXciWIP3myfNtLUJG94A89vt4A3qHEAsDMM9c5qTYnHfTANUbFoqob4F0KfFKirUsbVjgKnGTTcz
nal9LCkUk4LBvPShrxawQP/QQCDmyA3w5ISfQQwA6mCv4jTWTu/xIL1ppAz8mMyNtnqNZxu8eHGa
y9Cyp5gKg8Fa/wjuXQxlkJUAtzbsX9A/OAViRex+mkD71qyRvd9ZrLWKoYqyC8blBz9tandeh+D4
zQIqNkpwAZWxnbp2OnkWWE9nF3JLnTAdYrwobIFxGNY7AQhMf/0pGXp/xEIirPZSIGDGCF1J5/FC
SaHTy+6c7HotVX2Nijrz21+9bhaKtYjbWpwCICk+lUIN88t7+x47+gLi/FM5Ej6c90Bb4ofpweAR
du2mjOv9slgmFIaEmOeWyszMPOAhkL2r5ajyGNFkRmTpor6GadLQcQEt7FZ8DIv1AYX1eosQJpkm
urft2rWaNSZohCx3dvinXA28WH4khsxPi0FYLhawfSNpsVt6sTbOcUglBAZKYjV8uAc3H3jEVqrm
NdJZz5FIePiRxl4i8YZn0wDiyd1nK9hjfbRcY3//skfwGX3Xp6rrGLGfJjZmdbFlQjhb9Ghfw/gj
ccvjwuB0VxuYO1d18xbCSO66PMIHKtVxgdW8/cjs2P5lhdUNwooRU2wj2VrpODsQ7zmej0qOLbY9
ziyAovk7EFYlkRd+rS07+N4hvp6xz39PwL+qiu81gLkW0LXgoE2TtjNC8b6eH9/bwZpYdK12NgIz
nYbktUKXfJQLkb9EX/KN5+t0IoxLhgwCIgu7k3w/H38EfHxiIpRizNw61SSjuUKufAasPNMOq8YE
JfZFkaQXyoIa6UpcKxUQEqB3PrlhEEJk43uaXBxyIH6asPchEkiATPbMJXwDMMlzeTUMRGSBI3gt
dPygnsyAYoUgn5ENEOubZDwGQmxB0rJJf0fZxRGGqpQoe1klJS3fM3fvmVSPpr8SCbyGfcX8sFQ3
ZHo9CmhhR8Ugf3o7vw6CSyZGMvSAEhyi3BOQ0Di4qsFlqwnI1m2uGpG7RZKkVkc7L6kcGuHF8lws
8q7YzLFslBBGDTp2hgPAU0Tc4xZPWRlBeaqvLLl8L2zoBX12g4xbQqNoW5KR/TKcI7n1jbQZfh0l
8FnkgEXriqj1ImkDpdhZ5mTTiPbGOIiSOV+mOm7Dt60POPmI0tzqH4nc3mQMBQJR2C5K/fMAOxdt
/PhsOFcPLvU2j4DiDaEZx2RBg3ZvWnLy3T15HyU1JtHFA4zAEYuN/lXurHy2o0iXkOv5OBo5G3Lk
fY+PAuRDcqOjWP0dJVFYREDJCTdlF3V9kLwsbfCpIUU59isEqY2jiIxr4jVwSQvEsCbvgdYlBVbw
b0jKGigV06kNzexRPNlRwdYt9MW1/ZBFjfrt/nm6KjvQuwhW9vY5BC4YAu09mgsnLCzbvYUNeyoL
NCeDa8xCRvFXAEWP1OaloAHYUqBB8fhieZR8GcgzBbzaEcpIMWJdHGF+Mk09GXsh4Y2Uz60CO3ET
Kgr3Fl1SAtp27i6D6XQ46hKTC9xsTmy9XwI2uCIOdYeTlSIuTDYzjBZCo8JQ3TDbj0z5lZYUZWXx
CxsZRXtOrw3qf1P00yjGBx48KXZKNFoodD9S9A6lPrtz5OSxZBc0Nu1e4/3EH6X8uwPCRT9w0u7E
Yl5Dxzkk4rWwpzSgeHxEXtnPnE0Z9SDhVUuUtRmrf8GJ4NZRgArDhSb4Qfz/Okwtdqa+K1Ebjk+7
XlT9uQh7MW80AUfznLaug9Yxa7yG7Vuad6bH8qIw8WgkTYP2AN/nT7benPsH9G19i4g7VRd+NPGr
deBxDM2aXBhPEfJW+QyqRsOkYDLpTKOWn/wOZBI3btaVxedUuCUErnUxn9GrJxnZBfgmIJTLxmVC
6My+/5MrYoj2ly3161SSXvyTDeOGVZstChcw0IhsQ4Xc9TGpszwCsaTryMhv/j73QoYlW+dbkeTJ
ROJSKiYY0k8lLpCkDcDdaW2fCNcRTzTvWVjFkTiN01YZEuRztu8/nkthluDEQJ4jCHMkhguJItje
me0FqIu/BTWj+KdHLKgVGMmvgvkef0jVTH6Rb44yWsiHHKSecd/UCNCb1Cyl/dg1HEfCD5BssPwf
0jgx2S+8P6//Fi6sCQFOcLEpJ2xW4/JxonTTY2OlzcHhNwJFQSaglbZMxWww3JYPuT1oDqL7dsLP
/phH3Q/JrViVKppimQxt6AIIjXaUgl6y45keNu3VaiXmfTpoNHF7PqviDRuEZ4NLDxlLzuz4CfBi
aAKm2H6zOtI/+y51J+QiwGo1b1dAH6h/Dv/KVyYCAuYNYkg5TmHe28uiiMBghtkVmNBtlWI0Sec0
UEm+ONTLDEnmy+45KAIvY1jTYIgkfmVtjQiny6eg5dq8HAgE195fbmifCLhYTn+2nWIQujW6K2+V
5qZ1UUE+yTjC8l/gm91n8wU22pUv4R0oF136LXFT1vxY087G4gHmBLj/VyKPIOmpVtCsniqyyprU
79CCR34AjOlR3wvk+5ityoHmic6D1MKrbdFaWSFCUx/6VxQE9UYc6KTUUw4m4UoRWn7gtWvyj/st
kJV7hNWi2J2DXTSLB8egekAt3VbwIOC3hZvir3ibt5U7HQjKtfhsO2BNwKeFwH4pVUN/SU0c/GFL
vn82bdk6iXbJtRHkADlrQg6qUkUyFW5225TRHynsPD6CTa/p0R0V01iUgu7WxAzHQqvO36pwQZkR
OWz5nIHUBuBpu90TrRThO5En3jFS2a6e2SCdjFs2QTtU14bdKHHW9MFUH3MaOp38lfzkUys+dURO
O1pjawmdG5ZtB88YsIgHJZ3RudYUH/ihWXV7LnuWDQZawW8KnDQ9LJdn9f0i2D2dPRd+N+qabGeM
r+T0pJ7eHk9dm+Es7jwvrro6pWm84TGdsBg/CgzOqunrJIg9fxJTDkYrwuy53o52jr4PwrpyxcBs
gku3V9uWOet3UA52iPoJP5DxvoFM+XYINqj5ItZrhFaCkr1ML0PwXJI3pnkm2ZuckEbQfzMCKw0q
bNi2jO9Bt1v2Dk88JpkZ+yuno1u9TcSkEggeX0m4HvD2uGf2K4SADLvbSfms59eqAJ9FHF8hAjn9
3JFBoiqR9QR5raDHJDQRyx62WYTv5ms6D2N2vZdHb4CHLKJv1k06PQF/cv7VRxTiaxzOgArrun0+
Z4U0evoyClniMd5nMEBMmq5jlzLIGnHZ8VR2H3briE+DkLtFP9iV6GTQiNIykWluzz+InbMozODB
zGHvWLsOppox8E4N8VKSHjfg96Edgl/yvSgoJ6RPRyv9RRJNoyPHgd5Et/ZhL8ht+f7GPGkaKt8r
hBfRq56waTuYQSHGCvtZTrUMFJt2fRD5n32HH/D5khU1YpsaEbZwnsYVcGPgdCUQ68Wm0iaIRhLn
nWhnJKgzfr9idk5oV/yKIzq00NbwHPs1JqzDrnUg2uxIt/jRONrqSuURwSYYf7iEGrpSyFDyvlzL
T2QUwM0LjDq7/LyYEBtehxRoxVcDLIPUSLmY0gIInvrFp3Nxn8LgVWN1l8D2UrrSXuzIDxzk72yV
i0gGtlRgB3IdL/Dif6ucThtInTWtUskXUX6Ow2g1tAM6YF0kr6yAfp7J2Yro1OE7yQziAElfF/vM
7bSntpqz86b7AOZKm0Qlo3X1C1RO3A3PaeYd+IkmLw0buE6gj6TY8Z6wve2xj6fY2VrDGzD3L05e
mF1KbsP2NGsbCh590h9SvB7KAkI6E0pEMrBMcTojKu4hQ0Db+L2CernoTdIktUwxE3qa7Bz/8WXp
/3Km8vYUNTMaZJ42HeWi0iQeb8Yo+M0oo+qSp3/fFB8GFcPQWcJLQ+A7LZNwgH+WBZfVdrmQ1qIb
VBcCPf1awMnCfHrDUnZE6AhEWqG/ui7P5ipzMLT/f1ukK/hWWMWydgF3qVWygXHfJTwveui+u7ts
ayN0wDe7GaXCSjaklxRyH+o4sF8VJZ74GyrOWEwlM4qp95zTyHSjpkmy2+GzKavgp9suks7Z5iJy
RMjxhavN4didfjqWFd940onVoCp7mMP7zcQvZwiAuGG+9QvzSDatMLNRfyXFSxZPcRkHa6nHoAVT
TfVOqkvFe5J2PSGnjPn20MUzB2e2WQBvUUokVwI3H/RJfaNCHf32had9L18vje+zwI3Oy/tLgeSa
DdLAY2TI25AzktWWqDslZHIb+CB44/vL2Y68j0XNSOz5Fu4KsH/UrG3ngJAxb0rZZH4nCRbc9mTw
hB42eJiLI9YTkaphEBYuzZq9qQVnetEDoCmVRWvp+WiUz4LnxDPUgUjdF1XDFqimwZFbIxwRYJk8
VCqhY/twxOR5StYnTfEF2SnwUAwNtYRvHwGWwRrThWebJhE9lQMlg9jJGYYVlBoeBYyquMuHaPsk
/c7Mj4JLz2ZS0b6aQFeXzwbTvjsatLOPFrOXVnzHX1rtd/rRojFWmQX3Bde/U+C7TThH6KhrB9ZE
wMA2b/jIs0czBZZbPIt8tfV5IWYJ9PahGw90L2uZHC0JBB7klcjlvGfylVU4h9ivrjzp56jE3tuW
mEJzI9Q2PaqTJIMHsnfbbOjdXe9jGogtN4KnGl7VkFh86mqfMInuQbhXcqrNPAjFXoYBZTltbXPj
KTVcLFam3Lb4COBYdA3Al3LKe0dvW28214H8XM6A2clo4qNvdZnPl1zRAFO46zCyH+4wEMR2a+fZ
/Vq1rCJyYh3KF2gpzFK16nuEgXH/eHAwR49hV22edcN6v1C09f0UsyUtW6XqxHh9P+0o2tQR71Lu
/sHtULTwhkEz1VFqUL4Uv0dSKXGe/qRcc2dA6UsZxE67mW55umtsXnoeV8G0gqEx8K4VRAAU7XMg
Wxo8C1QSSZ6sP3tuWX7IjytjvZpGzPt/t5s3jvV1szdeYaBCCQzYWI8eX7BhamB48szebzGjV+Yj
7onLQJ0eFdnIykMWJwia+RqZRthCq6G2n6TfcMyZ2iPBsSKL7qZN7t09FaFoel1zYe5luL2DiMfW
ZaPGyp06IV0nOGTKg6kxizANav8L6sjqbMZm2dU15j29wGymdnbTKSsPRdlS23jdEgTfDxM/moKp
zDSDzYjxq7tsONGvrySABnVnyiIN8jYUINbgAmH0uJIH0J/WDD6jidDvTP0Vq3GL3EudlsQusN/1
uu+/kRXDssfebk9ulRd4WVlIeq6XxgtdQ2O38FkUdHmodEPFcyDVY6IniRNfpcOd/WRpF+jk9RP+
yw03guNmpBaRXPdQAdTQwZVqUsfWf8p+rk4K+OvTWyO3Qii6DW9Gur3NngAGl9qqkmC8LHfxafsg
15EMUaT9rxDfe7ky6ec2PDsiyBuOLak21vFJKQ0GZPm/gWHeg4HfK94SvM8KQVhUCX7huN3hrRFs
5Hb2eCJNyTlXCIlZdQnTLZ0ZSC2iAKwXV4Lks6g+xZi1SGba3VMNFMqZJqlkYZDzt+xCGYFKNleC
Ilq+qcX3wPkq5kv48t528GnhxUtEA0Ct/GlbIiHlZyvC1pTNMbExr9GIvVTtVhOC8g0LHURZ4oAv
Edt3tuMBTWfa1M8hF1blQgiHLPnTZvBNx/zxtUF9ez1YJvZoEixwJvcxUBitvpR5mWoSqn4qdI4t
ifYaVabs6FZm+MF9+cuQLFVRw/iitPKdqvyVfMvj4dZBoz8KhA8cVnrL/M/PpMN6rcqsXmQmQSfM
Jh6IfDGzrnnsmOo/TiBrEnnavVZB7B69ctTIuaYRaN5vjtbbN8R+kfsgLMsHYccFhaxuiNHLa5wZ
JoVm40EH/SlcKJLqoUoL862nLSdkKPAiurahYvP2tEa/uySA/SPFdBHMviJ3RaSB9kGeAOYMyeB+
Vry438iw+WgWbeuh3r+fijYyx7zJ84Iapa7znzNVqO4wnfZFf7KEnwn55lNZXgBr7GAQVmkHRCqQ
x2U1jBrm49n31H7MXDwRs8+fNtdrnTezo+ee4i9RuIH2BuZPiR33X6qzTA3VvwTfQFK4MrQU0rMA
BDNEkNHSg7sjYVWiGRhsutmbhXYuBmazLl7nFHR2HAoq/ayUWxQJqLiXXhPED/feZqrURcRkZ6ra
ecVy1HojKvIdmLjDrf4/HRCzBkoEZCaOddCJnW37boj/noOvJIxX2fVhVKLCCP3199uQeXRQCiHJ
DXT1ZwRSoVw/Mut6F7GeJDhsiCDjtnbGstEMlZta9wCWi3H4sTIlcjvqnu92Wu4C69x43TWfFQQg
os3kMFQ6c7TMRho/6NRK0ewDXzeJBF8TSZlAmtuxG9OVyYxg6B2sKuOySWJUmBb7TXTRvZu9ddS8
0HFAOlplsorMoIGLZtonWyZGfD7IPk1OJITB7utuTWKgfWkLdBZsuylZ5yYhvcuiquWadscNd/Mm
4a7hHqoQCPdl0LA6DO704MaIAq1W+Rlvq3iwlA9FBC1txTW37KoigZVTZHb5N5D75vHe1Ge3wJDn
v/8jKijbMbar7ocAh+inaAQmWlUq2FqqOPhTO6IMH1qpcVeycJNOGwBc8dojJfzCP6hR2JEmrjsv
XZe8PxaMFUDkYiRNR0rGLxY4jcvYuqtBVyhBvFuXqRdZujf21xaASkVcd9xguPS3Ssjm248YrASV
kuCnrdDjN26/FNx/yzL7kLSMYrdbjNLjIsITLP+Gce7B3siI9QTvveC7fbZVdqVAw8oZS74BxxYk
kSgX1CLPBulwlLCphKj6GZ7R6JuMb+ftOyVCeN9CEiirBucBF7PGEsHSUlG91qrzWqFaoXrcGcfK
Avbn+7n5tQ1UJXXgHG0f7tEai684dya/lInbi5ke5kwWg6tl17EWYBziA1vbxXPBN9pW8qr2V55X
Snd4TccSa09mBv4YL46I8s/peO5l10HS+/25RV1rMURdLa6hqFMLg8Lu9fTPCXOyX3gsM9BQk9HT
nxUzW28RjDZdAH+CqzoiD8soUngpoDIPvKbaLxQSx6A3G1BQPAk+C9XWug989Lfy7RyuhcK9ANUy
j8DbQ/2etT1sAbnOg9YgIKJmTtfdNJ/4MpXHzdXrB600cWnP+Hi006LyN+5lFX7KWGmliU5vZ1DG
rRG/0vNFMEwb3RInrqbrUrjEJSB4JI1vMGOj9JWMop7B40qJHmG0GpK/Gi6QXD0oza4xygR/izD4
ZlUAxzMh1sfdgq2cGS6VkYqGt2VZca/bPCdEk/EdPdpLJ97bkS6PDr+IX1MIKEmvalRHXDVr7wn6
dFaX+GhILRRnByiRqtkM4h5Ai/e1A1egjhFc9FvdFCRKahVbDP3jsPicw6OejjU6f1Z1wRbvOLmy
VMvnh7hqaECJ/EflFMO2D6oWWSMbsiYAaW9Kcx7mJMCZpapK5y5Y0OkipF8TZ0hsu+CEPFxzJVHB
5STGfCIqqjaEeaR9m+7zFrNPl7BYfgRxDUUG4D9HYFTJsrVVAI9rO8F70iqHtL2yVkqH34dQwiH8
gWDiM15wmxxt4tH4tZab0ehQtJE/82rOdn48JJBbCKADV/iecZi5CAt4gzbrA7D3AfyoqbX2xWll
RqHOBOSVqXYsmxxSAXU4lj92fYp2qxYc++Se+Rh/zb/70eD3vTGVdxcHI1pqj16+nHCjOGuQJgYS
d/ef+xsrcZdBw6Wl9wA3qQP4JJaFwCjXBV6KTqNmwuiUeXc8Gxx1UdBSR0FcuKgzi3v9NfezIMWD
Nt+vJy5JTKx4vWa4zVt/BMMCYfS0/mI84y94hXiT0T4tR/3yrqsSkeBYGhX9WhOPAitmwZX09pfA
ZpMC6e+tDpDR4RxX8aCpM4Z0w9JKuoH48O519E79Tmvekfu6/a5dggTccKMuFxluAgo3dyKGNt7R
fTW4tvG/B/zZpmNbD7IykaCqYTS1c9pE9eDKvOF2ETi3+1pW7NwdCRg//dKhSJ5CfOx+lZu+vqmE
QfkKoIGG52428mGqJfr+2QiobcEF46YUKz2Ys5j3xravm+uuN9jEmoOk8No3JRrgUTMUwzrdvGel
EgCpGPHXUW9EwkjUd1+5QveKA8moqoEP1OXVplKxXpRGhEZVtGvwHNdgVC65/bYNbmjIp5ooSWX4
6eM/9vnHSGuxfhTBNT+4s4ZSdn1iEqC/79ZcBGu+NhOKn4vytTHXIfr6916/zBWURpYx9heIOyNK
7fMc+uw58qakHflztZOwx0JXMukPp0lShDacCb2Y1Onajy3RI5/3aa32IfueDOQEbPP0FK97Ytjd
F3gG1S5V1iOGvHPf8mvLbbzIsJoE4XQF8vG5n1hqlvqWM1pimwehW6GHUfX3grONPeCikwLeuz2P
klXFl86HbIlpGCj8E7LzQR9wlTeek4ZpVsj4mpM9MT2mSzJmLEz1QNkUfAzSfwQacMT/YdXj2t7D
FFqa+fxh2cBFV+J6iCS3UHa6beGC7aCOwH0NDLYjn1LvVrLiRaY8oG1GDmDdp8GJv4EyeRq8yg+N
0K6/Ih6V4LLIpUkdSe9l1ijsF2yNyYlEPsilXjwQgLcxfmJvdMvBhreMCAPmnLqfrZhCAbQn3xc9
IJpE1LJWLBKEli5jll1opVpID+jQqlLsCP0IJJiaAc3b92HBUxX5OlXetuFciaor5AQ260arkLJe
zUrFTm7T78UMVWepUmv0u5mRoiyhVx6WUU7rxtp99JRV8BK3zMX9DnPzKSQR4hgQFeoKOGGOroX0
bcGc1FzkbiFDv+NUq1oRAEtNHBjLFentgwInolKma8APgypy6Ie3dVQ8qGFAACsWwE3Nzl54PvQD
+MpYd+w2cw8X+YK1OpSZkJwPg6yRA3sK/Mg7mM/SMeYTbtuehGB/pNMuAG0XCf8nbguCxdLRYKgV
x3MqdWHYhUhX4pQyD8k8Cie30hhuGV77/LzTmNlV/ygsS6uhjZAaYIMKmj41QvKPSdPN3rkTPiPn
y4sYkBItnQiIzPjuafVah9e2WpF+tcHZOvAOXL42Vo/OJ86IVeqRXEihB+b/dRwwteCIXBkjvYDq
8Hk5f8BOTHyQz/EUlMA0+4lgBPDEM2T82eDzn3nGcDT/BQuvpwSGqEHJ4lR143DTP7UQbyCaK/Ml
iLDFSc5ApK8wyTdoHtCvLG1eXurftO5LFQDX4gYOAacCWH6ccdWCHIKXSP65rYrHfQI4q7TEzPvr
dfpVjWB+4ATDN57lDy+RdojEgvu/QkYDxS8WjWX2ByOioJ7LR6fGMyX4YzpCXyqJ/YPnXZ3g4fE1
3fLp4B0T+nsclo9t8YCkHUMmXwCqejHHwjBI8K35ngn0JOABqUvp98xoTkrmt1PaohgUVwbNXhYr
AX6d+kkKlERN7W8UhzscQgkoyE4bayRQ7NO2xzipAiirjGxNMdaoxEZOufIIhzkctGYLlHfkY0Rv
4CMtSggfaMPMUcj4tU87H4JMGcoLE64Cba1TeZYBWHoSvmX5M5UOR0OzALKhfB47y3oopmOoUwaE
uGLcV2+hnxFWHiOuKpog62DCVTWZvU2EXCNmk5msAKk1UkS6/5zcwco0nmXBvNjqvOerD1R/+CiZ
mNC6bJkK91v7tNIk0Nz8W5NvPhBdPIunRM3XFu3LH92MXFPW34uaDP6RYqY8L7o0BK5Y7LH4Ti4S
lYPtwoBD6ldmaKrRzW517VtDQOOGfAdO+aDAsrbe24p2xbeae5jJlngMaTfew0wCR19idVfWmtgH
90m45aa767S16+Y2+YioccjYQft/V9F+ucEb1RTM51bin39rRBPOubqpr0i+IUmzE/Z983l9XAKy
Z/mT8ocpO++aup6YleWNQzBLiajIQEk7FV9ETwRM+mUAsURWpEPTJVpasdcbZWUTfKLdYo5CXaSq
9kOH5fSSB03dSGqGun7Zx6oAIvPyQcQ1GUlZA92lolSxDzB+7k6BqUffAPwlvnss68d98+p7fNAZ
S0t25/T5HfOxPqiQ8NA22B5xOEajRNA05uwp/ih29rw43UQ2648aScWwx/2lPVfmb76vjmeIbtBe
bDu9dtJZDlCTMroEsIqKA55yIemlvQLETHiErcx/jf+jtykGsn9PUec6zG7AQ5zL9A9T45MjzaTa
5Odw56x1sSmwaSk2ODOIrNR4w6Kl89loAvFz1nSD3fDLwsWifEwK9NjwQjtxYXCPzjo7HfW04AUK
Pg9/0pcQkehiMBBYrhva46Af1L0FE9INiWppQTc4GKqMVoet22MWYdqVfCYOyJ2mBIkRdKzDwY6E
5g25yqs9ifgIS3MTteujq5PNzJQ8ACoLH+95XGJbNkDAIgL+y3Oms8Og332pANNgop39mBHpiZ3i
r8mXJXl5xm4/P8EXDwh22EBl15W1iF8PwNWJnfxL12dwr9bJcXFhk3ckbKKBhqju7qSRnN89toOV
OlLI3HxSbIhA9o5F6q6bS1Q1XlRb+3pA4sha4KufPt0wsCDaHn6VT+3Sthz2oyL5XdvbWmhJzpMm
dQYm3IIv3hgwXnCPZ6YhLmMqGP5FIjDVGEbzgx5O49P0gwHJ3CfY8xorBWUsRjGdCAG2xvfNnqEk
5f3TIPD6Nc9zrg5ezIMKKYMXkWo+o1V3w/r6prtqmilUOBoFYX4VYslQZ0Yocs+CGt1/mEC+KSuR
Af4MiuWiW5RPNfwcbDT06O5Af3DrbRQZQCBpBghTdQlxkZXtnAzst8KxXbiEVqXX66bBiavtm0O3
ipRE9n3/ld707Q/qbTjAP5HrUX1ysnVMOhc3LIeXM/8hOkXt5mpFmIx0LtCnsuJxeHniUQUS8V7G
MmsU4Wm5barg0Zh7yyJ1IFkcyA6d5hSu2IXy3zKcNIhhERXIIeHaoTA2FpSuwcVR0TSNED5e5azW
CFRid51r9ftkUroTCdaaPwte/gyRxJXNVYrQ4hLl2eTYcfY02Vl7g1VP/7ppeMoR1jK3FyLT2B3N
p+q49uggfzk/MhJBKFSp4EvOIaUDoRiwGg4TAHSNvrNSwdQMCwxrzRc4vI580YpRtx62o/vCBugd
mfFshpmYtEw83POB5X4+EHa05ySins7fTkhtIKQ9LpTLmsG6ZvM/heCtk8ee3OeudfVdTFrAN6Bt
8vClT8TV/74/6grsbdb1WdFfcYd4izua0C5Dzj8G1fPDKnljCXA3ful1RRZlvaGohPbU8OzgiQQZ
O/HtzPShfJ1XlnpgLbj759pJw2+lR1qljNSFiwDgZiZZf5WAytVlRGstLufPRHytGG0a9NckYrI3
DNRZeMFjRonbu+HK5I1/Lhgg0bwqEVRA1jcrNSsMYzJU4+WNwmj7Valn5M6RTDejTkSsOrmk/BDI
JXHMf/3eKHFeRzKKL4r77S/X+nCIYP1zm8D4G2zfu+hFw5BsrY5v01B2zvyil8mzXc6rchCAMeY+
Ihn3z8Xed5JWn0+V34/WfCEs1w/fYlRbv9yPnkiv+UK09CajnRSUvTw/urBDAJ9S6KPmoQlFh/H+
5Xdv7vZMOiIywd5NAO0YbvU2Y8G6pEX00iRkBxdzqAZZ65TaLOh0iGD3JgGMP3qPR8xQ+vQeyTyO
0AbmNjB+lGgoNHMSmIvXc2zTdWvojeSxxoAKKgFFCUim3MatNRm/JqnQswqK1jbAeh9+85MSQlAs
c/vhzHn5awcyFAN27haTnemJ6BFcb+MiB7lndGDdfJpSYaGKsDhafmJOm9fdvKBp2s0vpWhYEFrh
kEf0U6ojK/fBgK38qOeKhq0LPWAPKwXffgXdt9x/kFtqjxwJdV9GeTq1AlLYjRhnRuL68/N2KTd/
/PQ6Da9O9cw/HLzXXrL5XkIHrJG/8B4QXVj2WieWhj/U7B2QTFru9jus0+zlQRUYNBPOtC7m+deu
nEjZW+2vOMMEmFKovn87ovwe70hhzKsfG331CAR86VeOUfIKKbNINhMb5eJPsrmSEYjWBrxgEHG0
RoUuWLo8nXJI66hxc5LkzRBZOXbhIB4zohUwtoNXYjqlxHb0KIGMKr3riEPQd/fKNPAniwu6WaoQ
LkvP4J648ZPLA1yazm0DVzLf/Hsl7hUl5J7yxNZpq/xAmxmlBGv5TJaawRjsdcWJbHlhd5Bxs5tu
H/CxAtDpzctKE22yPBSDJbli+q58lJfkxi9J8AF4+kg0aOPqsPSDXZVy7IF7DXMPi6WZ/zUsQrwF
4yF6FLQ9XBWF8L1XYXX16lUJMu5WCD7SJ3bJb65qr0+8NLa/En3qOV9CNX1AAdaqi+sVl7WC6OJr
yUYLGJIrUB7w5xWtGDwSsoH0h5q5S9hfHFzcp2GQnwnjA1lMFtlKFYaY3eAIGprgGAHi/QFx3eKc
57xnNn1/2h5lbOAMdl4f6JvfDW6LI8vKDQqzUsVSOTAnnl3WZ2U7OltBOsnzEstgsUSu/9jZe/FU
Q65FQMKRMHKBzc7Z/s+pmU6yswfMaQb7hlRPC7NfqOaQ4ZcGZi/gBGxn0McPMeqyKp9DG3nY3PTk
gl837Amd1iHWywGMqD7+8SQdUaIQNDlWvmrdp4StvguvI3qxbBBXJHlFSdLrfpBVpjG1QTLhzVC9
3jhxOJlXjUxiJSvZeQ/O3QfmS8ahJLaE+uUYv1ur5Z7mIav/ABKQFxH7tozEuxcLefJB1bJKusyO
45tJEvlyhvDyCIAxnBjxUDSeFm+HOjYpx/1SPDfpfGRrfG0b+nERdRadJP1GkfVbnJOhdFtyOGIi
AdemUt1qhrZiXNayoq+Yr4rpI15omEvC2i6HMCFkWNpUIMI6W8kObdWtC9uPxZ1RWtQd5lM3aHqc
mO+Bgl//PPC8O6v1avUua5biiX3DkNx6JkmmPtIFrgdyYWiKU6dG47YLcrfIOIn8zeOQ4CoAQvLU
ZHscoOcOKIgc6CSwubocETPtPXdxiSoxDqNVQrGcmKMSFWFZJ8bjdZ8RlR6t+XleMsN+vW9lWupZ
9aDkFY5daJsk0s64/9jGGlZoT+vaZNXJreekk4HdLclW8sr4mhKN75MXySYAxl5uJ0CiYzGG/qzl
/lAf3Y71Ic7VjF75fxxGBy1/uz8IhzW2qToouPIIveKl1EFbYdctq1nLce9iIQXCjlQHBcpDjfsm
6PszWmc1Nb3HYXZg72axtTYWjZt2R3EYX8mHNsHLixcztCqps2lfrqgQGFDMCZXo84IKVagYzaIx
yxNWUsfj9TXqPaToq1sAk7XRbdkw3oqEQOrgNEn+E8AJ7bViP3XeUrRoq5KRMdQcpR7UkMSYcqS3
iBtldReCPZwATLuBTEF1xImp/ieHt/PY5Fv6WShxkiE9mPOwoSqbjNfwyIFUGWmJ6A2GhO0p+GZH
gdEqM9+dOPC4UJu0fdMUYQPDuxTdy1e0TwAKzjpt2PoD+u4BwkHePQWTKxsF/ORUbSU+MLrC6JVR
3SHI2oXihzejmNTIcl+gnVhcVn+G2zGevmMJnneCvXA/0IRvie9SeWovFfsv8WCdA8kuJ8aOvLyX
OLotDgGAaD+5NwOXWhfc4EHaRI3+dYNYRnqm6v+dfiVC8LS/Qe12K7KlQ+2MYp4CMqh/lXaUYdzi
lwGLoDAm8X/+OQfcO9TpMmOJtB8r1lFgU/MuBddtLx29wj3Jslp4wJ+EMJyYkHiLLkETDPt3Bt9K
XS3iMsd8MNhB/PCWrbYyg/GL8teSkt+tFsEC++Zhv/6R0+ul0l8q4buzzi1X2xSlnousAdX6gojl
AhauX1FiaIA2rd0qWzP2LPo4dkvFc4cR4EifwMfGWhIeyfBZEGblbgzPOqeKihSQNpwQD6HAQ0US
EN7wsErtyRXs1GmOt5N4Kru0Ge/B2OGiZuTZo397Fat+u2xgImWwCuUdx08LJgD6W7BMe2K5WTiF
aLP8s24iaJpS4GLfnJ0bM2k1ovNbExmOswWVKwpxoJ2rRcT2LKbtmJ1DbsVasWSjQ/IOHO7ZorvN
tBIHq0jDRxTNAuE6hBC/z6Ddh4ZWa3o171otZWOqOf7q+WnBQY9LS1NqKrZ722cYavOk1P2zIj/j
dNRJ/503uQ2a2Go1/M1n5MZtcalvoFIggyt1ge8yykFzgd6PTHarjDAeVPQ4ftnRWRm1EuCcW0kj
9um8V4B8NINnLbB4YAXQFqP0wZrpzcw8Xp/iF93GF2YuzwYUlkgffGZQItN5UEVVUxPtEff++qhv
T7/xUoBvCtO3aSsnwxLbfwaW83mMZitgMjSz5547BSVvdflhiegFTVstgNGnRf9EQXCYy3vVPHy4
VFxqZFsBTjWNrVO3X7D+eBlR48jntw8fXWjNYx4Ce5lxbS2EauuBOshwLOJmEJnboxmdIMRt37Jt
wqzErziCNtReLlfwaWL6RXlp+00SZxR6E9tQxZzGURXqyi+5LJF/cXyUNp//hLh5CHXyk7nWhSE6
8vL1BDy1nkI81o1+Uo8PCQZ8aVWTTXKoW9+wgBnGYRgqHLfanXZ6aWtbyP7rG9QqvruwQN1ixyhu
b4/1lgL7sXsoFwSRA+3ifKJKy0M9lZAk2XDEHhRczPjnxW6k6GeijwF/rQQYDtEYeKTz26r1P/iQ
z9tFZQNRcjxL5kcWZCIyBF8s3V8o0yhJ9HQn1UaTQAtxY52vMvPZmp96pzi0d37V4HjWZhoyVYX5
J5OmwmqFR+JzkXepJvRspbW9HQdGWIkea4OSW+ghl5mQVd5jKem0dLuXpHO9kZepQwpO0g72FADo
2A816A+rZkgcbZ8f9JLKsBCW80qdkv2mXMgLhH+Q7aZORbIkWF3F+iKhm5//lCIyXSBrXXpBIfNA
5FFK+32ubAJNU79gLtZ/83Mu0rFNDvzMYjk15crvY4bkdYx9tRawm/Yh9PwvT9cQ1SUvdycmRft6
ZkX1BhuebOsUSeMnjvUZMCNhhtc1LhwN9zhR+OuJUP5bHhJoXkpewL1R//NMcRwWQrXZgsPzPwvl
EvuCv6p1rf5f/y1O5F69PBRxsM2T+4omea4FACIKvQhYk1QiSKT9C3erXmmLlckPPUiKibhZKUYk
2p3WPISTSxCL4DUksWGxeveWtGR9xgyVOy/d691i/eAPgKuXvC5s9ZCsNSrPfPJnjxUVn7pTZz50
KuaTevLXwkFWq2a9oXGNPqPTZv6D8J9dxA2QKdyUflw5JM9xja7517Nld7SEPFzHJVvkJWyh3Z2P
6l/hEsWCqkRebFlx4JJ3fqVHYIerguka8HhqM8bOTCFazeOvH0EOX6dckoYWA88NJTkBmjiZJHde
HHFqc5OW1L4ByhRnzB6vg1WkcEguZ1TL+WH4oP+Mvl21+yCNkhoeXmIBhmMjSSTcRcQEXlZvoa/e
i6T9pR1qpDGMe4F3S12ZkoYCqDnnE1qupZr685yYnRFMuyMf1VjBlA3PEr8Hl7gdxjuQU9lzqItF
95gQMyAFSDsuuuqCc6lsPU6090hgQdb/rr0ijX4HQUoHQTuCwSLyBRDDTTSJ0JijVeqNF7RUyVzB
SwxYsT7Ghn0cS1CQjxUaas7bLaO35QsSTgiHlP480KeD5K/o1+IhWvQXGgpa+bsmlKdwV/ZCYbbx
aRG+eaIlt5qY8p65mN360N054GdXfCgonKBvvPN9/o1KlKrJbj+Eykhr2B0BO1NSlUwx2c7cEUQ/
CVY7R3yipNcs2WNjqNKV+mZGvgEOGhRpTuf5vkaHoeKWOgmkNiHuql1kQ+IwIg0xa1iVVocH1JWr
IPnLnLJ+MnpUoXyokJWlP6H5n2ww/NWN4qNxG4hRFvo1RJ1Km1VkzFhfjaMQw851eED4iIJdAUEP
ECHQDiUDcvENFVsx4rxkrsGPEjlRP/y/N+0F3OQEDJbMjH42wlIzYKeMM/6Nt4jt3SldI/96bxmf
uexWmc9cWCsdKcQwzv8l2XKQ/CGwH77tt9+riw4YEzLQ2XKY1s54ZikfQLp+jLaFFFfHwxJE8iYa
zCbTfXP3RPV04YUQoU5efkHMgyJ/qm7ptK3PvFbquSgCDilTbVLKFDMOYaBSfbj39Yuxj6G1HE4w
Aou2O3bNlUd08j4B1zD7p2dF1y+b0XJjdqY3dzsor6zyCzXUZVL4dvhMVd7nJYoM6JyCOfQ0OUVD
QA9ljqWKw5QJelb8VL3pTS8PVOSCfYmaKoC9Eb5+iLhRsED2t2/OS7QBmk3mJw98nwAgfid87WkW
3VlUO7MrYfXpx5gM63/XAt0qL1bFHVdA39k4+eLwf15zWsfq3r6wvToLUGjYRm/f7ZjnLNuMfdLW
p1B1eAKMCNEZbONAlKcMjqa6KRO8/Q6al2gLq/NykPz1SqLa/N/4VVAI5t2h4bm1P11HnUvfzRlq
Guq3hMVlFVUmRNdmsHmmdn0MMwptZWdwxeoF8b+C7rlx8fB/RkhZhPkdwAd4zAXrsY5b/JndAIj7
uacaIlEH7g7/Xk/ShrZ3Z++yl5Y05LmV1s9bU7T5aP3Bl/C8G+S8kU67xV2Z71tRBkrcwwMLe6j0
rxJkhRrA0j6AQOJKom79SeZh53QOCrrmtjNqouue5Y9UIk6Jt3nqvYtB6LHmS/FmQHff3Tx2k/j8
5p1waIQrfGd5eKLZaqsr8bzfh0PYm+NIcc07Au6uNrX89VupJT1sfd0X2an0IGJyc7wSrkuvY6MP
b2g1PzLomAu6vuaNbduyooMvY7EAtKLml6orJ5guDFAuR3Wtbvt73QtZWhfK2iruN1rE7z35sjN2
J7mkxoXEHpDnDnHdpBi6+mwrDtVMqi1424fv870/AaCS55V0ZyoL8c397hneQ5Laa9FSCb7hAdf5
B1fsAkw9zvYw0ITyQwjk9cLvRPJfQQ4/aAFcLqPDNgsMtJE3TAUG7CUeOf8Aoxi6P9u6ApQK0rlm
wMASz9f4V/3plQs7Oexe5yVsGvmFavnK2VqrN+KSRXrz/IRbkeR7IAS52fqAQ0C7STw8oVTMr5yq
maOPEfsBOEcbUwdYzfhI9oI9vVr6vZCxfZ0vltKJW+Z/p9yfScOjWWshk0IE6T1aQ/j5U7yqD5n7
LgB7I9yeKChyjOmF5Iw91J6+J6V69cSIKEy9uLU/XLrj6LMWYb4tcVQrxNXLKARsI5BCcrXhnaJl
5QdYprRdn521MzKkKOyB0ZbC2KKj4G9vfSVnqRJvI4sIwXgNt+Ri0qIhA+mMsIE1rljVKbh9f9sq
p05h8Ez15HG+NcO70Yt9BTNFy/z+vyh1S8z4taiNZkCtPPtpR9PSsS4txqiCRQW3dEM4wHPTWX6L
GEjtbu+MFNg8aG/U7JlsPIlT2XDXXwaVINs73tz6tJWWRQdhUF2kM56EQnPbzv7+ZHJv7X36ubsu
BCZMWCmaBOQmkHIPuIlRp47xGkIMHuUIMF9yOABCtb4FePTkB0UG1rRQrGGQgaV47IJCRzMlLjC/
U3ftnz3/uKtjoYbv/9ATzm5/qZTktBCt+0SbwwHne6mGaply7iwzulBBB03cqUBSQZKGfqD8eTGC
95Fe9s/yeD7yYGsqMa+ebyhzGuuQpa3k7zQckn+bwF5IaXnwCorLtEDmgQx/wbf9PhOWP3L/lD4o
8/MM2veLTsfQALbYevn5zBK1fgPkP/4Bm9Jhq1HOZsKn6yaDBIb1f92QoaIuL078Wj5vm9om7RFw
SQ+lYU1kzU8m6vCXixhGSjXwlsyqnXvnwT8eF/h8fG/ELkMMp7zeDg4Y0VwLSlntcf2H4PwRAwRK
C7DYX1MAZwBQ8jZp4LgM67dSHm24Ebc6z+8hbkhjMeGsYP7HX+YhdqswleX+X3QB1ezeWKGtsoRt
L1Fib7TqdIZUj+LnDdGq4wWDDgQL6pz4T4S41NMvPM4c8W7S3FvHLj8YybtcPVE3qDvFt/jlh+B3
mVqufjrlPMAf4iJWvSkVePMEm8fWNKSLJMJP8qgMvBo1malN4+44uqNM2g2229iCufjrlciVs04/
2eHcdhjEC9dLpUIDMadigdOcm3qwnqBPP7W4R4GFtGV944wuRJnsj4vXCv9Bo5hMykPvwKSUNjO2
sLTG5Xw/ZINcx1feXxGQ1Ku8zfHe3wZderi+XWveR/Sn31JvvYmc8cJXmsaytRlcaWIxVaTI+qvd
raMg3KmZfp7oMnw/7NDsZrMg2eM5bd8XGj5QNZC0BT15v2ejm1qa8saTldUtBM5SxgDSvyGfJNYG
8FLuas+uOCzvgLlaRSt80k7ORFCtDO5laXokzPxi5ZHvrLRU+xFP3R6K9PPnf6x55HDFI5YZJN13
EPJpuVS4Cmf36ErHjKNKns+zudqe3VhsYOh/LfSZZ8A4YjjUP8QSZrkUZEqyb0tO3LHpwKAeKwI5
rUaT5FKl1I+gpur1gyvjzYC4vzul+qAXM6vOur4SS4T5IXhUg/12Du3mPQI4bECMJHpZoczrai8g
RtpEVeS7apoXsWnMYCPwMBfuyTmQJxyCZ9eb5K/mQOSwRNXn5mVgbAZZkFUFmh9clk9zBqCvdc2p
Jr6q+LVyQGhU9oL8EDj9GExgO83utSA8bFRCbXuSJrtkR0xTNyLQX4EVjk6V4ZPPEzsnC6T+cv51
LGxd/diEcnNRFlhz87Kyf992aPNMsPM6T3PERlZapgMpZ6Cs5+V+GRgYfY5mPw3T9GqCJTVfGiou
VbVtHrJ2pzEn0NYa9SN1tspP7h5DpVv+mlautuUyNlx1nuFVHgqWknqihXu3KlGSBQJ8I8gTuKsq
uMf2QIh/wHWw
`protect end_protected
|
`protect begin_protected
`protect version = 1
`protect encrypt_agent = "XILINX"
`protect encrypt_agent_info = "Xilinx Encryption Tool 2013"
`protect key_keyowner = "Cadence Design Systems.", key_keyname= "cds_rsa_key", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 64)
`protect key_block
XFCDfr1HDOhx50HsfgTURxczpXP2emtacLRrIRh40EDfpgGQkLOWm1e0nTUYecA/OSOfrqB80C/7
ZTe0XFVajA==
`protect key_keyowner = "Mentor Graphics Corporation", key_keyname= "MGC-VERIF-SIM-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
LJRwkIC0jUW/piEU2RsIJJMlMpXnmbaYsUhPA3pLZzMTkJCd7UId/BrmtcoBJzcFC4Xw/pBXQpih
8LnWx8hUvpTRL7SbWwXxhk7T44icvPr3BnotpwOiMOuMdo9dadaM9Z825icBOCdvBnX5so7JgVwE
bQPVlCsUfnx1MuYRuF8=
`protect key_keyowner = "Xilinx", key_keyname= "xilinx_2013_09", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
RZ1nmRt71qFJueOX2poYVBkK+kJFvtg57Y5isUkUbfMl3jfXP2SrlxIxD5ugo6qj5a05fQLBCm6S
cnl1Zhwb5CIrXtycGWPPksKmUTgOuT4ohRSTpFKgQKU7Hs2dr3ut9SLBQiSjyk+GesxlULHZm7bj
EO/5lQQydikgyT793rgRPGN1bStbDXSDX42Rj/HLrkf1KsCwM1bHM1RZCOPu48LH7PAEKrnX12aM
9bDXylqLef/rvFFqLuxTh6uMS6aWA92d5R94eAFyRqqLr1jaJFpgYMmLiPmsBxiIs7Pe43w5Ta2M
jOrv472DXnyBs1gwD/SCZQLnegik9p1sMwbzIQ==
`protect key_keyowner = "Synopsys", key_keyname= "SNPS-VCS-RSA-1", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 128)
`protect key_block
SHoX70mBVgQokgktfshpvtbHYCUEjXtz+fg6WJVCf5mFFwqRxNXz4pt9lRXS7T97YXNkBcmJQDc/
1u7EFOiLW7WFMsR0rt9h472TP/h1BjNCIPLpyp+AvGBIbm0q6imhhtp2T0PKbod+NXdaeqalmFcW
miczXSV+Kw7+vcNDOI8=
`protect key_keyowner = "Aldec", key_keyname= "ALDEC08_001", key_method = "rsa"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 256)
`protect key_block
AfZ9d75Fo753l6VG8mCJkj+QXtpUI2pvKj0CEOOLrPmRXAtlpVaIg1UemhXY3vCk/nRduPJaYepX
6on4/R1PLE+WDYbyyipaqWT+wxu7tFapvduzY+3hZ+1qA0KUqJbJkIAhDDnktWdxA9c432qLAbWT
6KATZ93Cj0O6usKL2wsk7wtaxWywthOSTkWfsrvlRtQshJMIpJQANRKPABoatP4Sdm3+s9WSJvNi
JY1PMH38BnxXBcJl79/rnMtLPPv30cfL9UJTyBt2gcf2FYcOFuzQItrW7cLp1w+OZC+auK9s44GQ
M2+KbOFL2rkwANFqClHM+LShBh//fXNL7TAs7w==
`protect data_method = "AES128-CBC"
`protect encoding = (enctype = "BASE64", line_length = 76, bytes = 15456)
`protect data_block
WPzW3AjpmP5i//aUXhJDhrQGi8++Ur8sZa1lEH2HEmjNfAKwSCG6oN627UXZSCSmC7Q0jcmVPZds
/uRslihxcltiJTdH0lskDlCNLZ1gLwzuqzJopRb5xBEs7fAA0KCOKiZp+eJN6gY65DBL7BrVjB3d
17pAv4jk6nhAwSRjnSLbS1zPKwhngesj6Y4VPAQSswf5De91kMDX5arkBetpxdp2//Mlt2gl5KeW
899oDBZ9OQwnqZzRTQFWadSPrKvUUfpaqpm+2n5f5CowQMk8ZLgh9rAJjpD3/V18xCUGt6vu7Toe
9sv6sOgxoN+2wz/mM1oca7a+ZvDq582WeFs3gUxeXfLa1a4Xh2oVy45hI2NKCdaewHrIuRmpaQhC
MLqOUKXyqOAtqz70x88HnybrJX5ysomV6NSI5yPnOSNm0ARPLZwQ8iJtXgdjLXJOCbq9GCLdAFe+
E45XGjIm6hkUQ6lWK4TDLbPubbV0IBEFcu4/RYWFD5nlLThUrEGL5NxQGZpHamnsdH8Wbkizyeip
YqRX+NeFsYo4JvCHaCnkPRrdtQ7erW3nUvvJmaa8fY4jdvhpbY7AhF//32aI8jTe3KxoK8r56ZR1
wwH86gfrsn7RfnKNKpsFp73JZtDfNfD1QhJuYStEn5onppzxAcJ03DD26fUteGErq13aFkEkBPaH
DnNZpVeboL4O9MwdjOxdhkDD7F0VXt0kwhWtXp0ql9L78YBhZTdfNTB+UaAI5rrEH5ZIesYBtZHi
j0YSZLvKbovxpD4Qs2sIWpFRwdBgjBfLDQKOLZDfMCEN/GPfkUf0Z561BPmSe5VE3cSu3osWlNhC
Lfx2HYLT2wozzKAW8EGlcMslrw63zQ7aF63jCjipteV5ccB+EGldbwnxyPaehZEt5H2njeOhH2A+
+sBKONyDkk+18T+dPyAwoiN+/AKHqgSuoCD2Vok08ZOM8o6f3yGWFGfI6lH+YUbXUKs1WQrGKfw1
n78bGhrgzNK65VxIp/xJyVAjirmL8zJ+hdkbBxuS+B1jKf0Y1CWiRto+AuHmQ4PR04bP0oBkoUhw
nL/c9Vwj5/6MfQg1vepZuOn/mBZ2nDBoR04ItF0aV/8PYzmgLCf0Vu4lbYEnXdv89Q2LrTBmlv9i
+P5KtALAw40b0ohm4cxcHpePZmg4f08Kuxo+GsDIfJJPR9VbyFZGJJC3Q0R8ZbZ2bulr2Sna8708
mozCfmcmbZQLY3incIfIs0HHki+/5Fma0wEp6w3gGFbdzk1enT0vTzsex2Zd2/3cQfGySD4IlH4F
NYEanD3KrCMR2iGrXztY3CmL76G8MBf7QmXzlx1PuQ/ZASAdSh2Wt2vN5HXKo+7Y1NS+Lv33+CWR
qTRbBbgjPNaWhJr0zTTh1gbFiX0bZNATxTVZpkGsOA9/FWp5rRizi48KiJmhggLS2b2RAm0UxMdv
39o3aD3mmYuk6+TVu+/KzGWAsVe+PvyQxTPV3394N02fKrqRmVoSDk8APgqF8Kai7S5FiL5X+K3u
TXqUOT7PAVL7r66HkkF9ko67xKY8fbLExehNc+uaxh35WrOdCjWShyuqLN8BI51HA4mywu4kabMW
KF8Tco3zN16z71EHOV8ymMtE5kQ/AzIUVDHTxn9esby09i32Rmx2jN0i8afkaupgZ2xwZfdl7OSj
Hmik0SYEUIE2RwGWFi0ZQwavZAfjJM0ChDSTDLf1zc1HbL92G/BGxExDzFDrTqfys3pblhUzxJdp
NClfciK7+degWiAT1y/ZcBssiiOOEs/+ZwLE+w6lbZayZopx7z/F6f2W/+Py+xMU9QyevODT8DJW
c2BNTfgMXwnWBOTaCWRxPC+kGIThQcxtp6QTSOH3/AkFvtoQISW6zqzf7BoCubMcAECE+EA8coP1
g6Jky1DME0uOsp3wDCJMe2EygNh5K2wrB3Oxg8r6bdNLFrKn0lirYYNZxBpjqR0DmIRnDougSRTH
zdNBKZ5N9CHDAZJC5Ngnw4pUlNrF8vfoe8HZOU5vr84/5wZJAFOBJxU+MJimgzfjWzvVtL9aiVUS
JXciWIP3myfNtLUJG94A89vt4A3qHEAsDMM9c5qTYnHfTANUbFoqob4F0KfFKirUsbVjgKnGTTcz
nal9LCkUk4LBvPShrxawQP/QQCDmyA3w5ISfQQwA6mCv4jTWTu/xIL1ppAz8mMyNtnqNZxu8eHGa
y9Cyp5gKg8Fa/wjuXQxlkJUAtzbsX9A/OAViRex+mkD71qyRvd9ZrLWKoYqyC8blBz9tandeh+D4
zQIqNkpwAZWxnbp2OnkWWE9nF3JLnTAdYrwobIFxGNY7AQhMf/0pGXp/xEIirPZSIGDGCF1J5/FC
SaHTy+6c7HotVX2Nijrz21+9bhaKtYjbWpwCICk+lUIN88t7+x47+gLi/FM5Ej6c90Bb4ofpweAR
du2mjOv9slgmFIaEmOeWyszMPOAhkL2r5ajyGNFkRmTpor6GadLQcQEt7FZ8DIv1AYX1eosQJpkm
urft2rWaNSZohCx3dvinXA28WH4khsxPi0FYLhawfSNpsVt6sTbOcUglBAZKYjV8uAc3H3jEVqrm
NdJZz5FIePiRxl4i8YZn0wDiyd1nK9hjfbRcY3//skfwGX3Xp6rrGLGfJjZmdbFlQjhb9Ghfw/gj
ccvjwuB0VxuYO1d18xbCSO66PMIHKtVxgdW8/cjs2P5lhdUNwooRU2wj2VrpODsQ7zmej0qOLbY9
ziyAovk7EFYlkRd+rS07+N4hvp6xz39PwL+qiu81gLkW0LXgoE2TtjNC8b6eH9/bwZpYdK12NgIz
nYbktUKXfJQLkb9EX/KN5+t0IoxLhgwCIgu7k3w/H38EfHxiIpRizNw61SSjuUKufAasPNMOq8YE
JfZFkaQXyoIa6UpcKxUQEqB3PrlhEEJk43uaXBxyIH6asPchEkiATPbMJXwDMMlzeTUMRGSBI3gt
dPygnsyAYoUgn5ENEOubZDwGQmxB0rJJf0fZxRGGqpQoe1klJS3fM3fvmVSPpr8SCbyGfcX8sFQ3
ZHo9CmhhR8Ugf3o7vw6CSyZGMvSAEhyi3BOQ0Di4qsFlqwnI1m2uGpG7RZKkVkc7L6kcGuHF8lws
8q7YzLFslBBGDTp2hgPAU0Tc4xZPWRlBeaqvLLl8L2zoBX12g4xbQqNoW5KR/TKcI7n1jbQZfh0l
8FnkgEXriqj1ImkDpdhZ5mTTiPbGOIiSOV+mOm7Dt60POPmI0tzqH4nc3mQMBQJR2C5K/fMAOxdt
/PhsOFcPLvU2j4DiDaEZx2RBg3ZvWnLy3T15HyU1JtHFA4zAEYuN/lXurHy2o0iXkOv5OBo5G3Lk
fY+PAuRDcqOjWP0dJVFYREDJCTdlF3V9kLwsbfCpIUU59isEqY2jiIxr4jVwSQvEsCbvgdYlBVbw
b0jKGigV06kNzexRPNlRwdYt9MW1/ZBFjfrt/nm6KjvQuwhW9vY5BC4YAu09mgsnLCzbvYUNeyoL
NCeDa8xCRvFXAEWP1OaloAHYUqBB8fhieZR8GcgzBbzaEcpIMWJdHGF+Mk09GXsh4Y2Uz60CO3ET
Kgr3Fl1SAtp27i6D6XQ46hKTC9xsTmy9XwI2uCIOdYeTlSIuTDYzjBZCo8JQ3TDbj0z5lZYUZWXx
CxsZRXtOrw3qf1P00yjGBx48KXZKNFoodD9S9A6lPrtz5OSxZBc0Nu1e4/3EH6X8uwPCRT9w0u7E
Yl5Dxzkk4rWwpzSgeHxEXtnPnE0Z9SDhVUuUtRmrf8GJ4NZRgArDhSb4Qfz/Okwtdqa+K1Ebjk+7
XlT9uQh7MW80AUfznLaug9Yxa7yG7Vuad6bH8qIw8WgkTYP2AN/nT7benPsH9G19i4g7VRd+NPGr
deBxDM2aXBhPEfJW+QyqRsOkYDLpTKOWn/wOZBI3btaVxedUuCUErnUxn9GrJxnZBfgmIJTLxmVC
6My+/5MrYoj2ly3161SSXvyTDeOGVZstChcw0IhsQ4Xc9TGpszwCsaTryMhv/j73QoYlW+dbkeTJ
ROJSKiYY0k8lLpCkDcDdaW2fCNcRTzTvWVjFkTiN01YZEuRztu8/nkthluDEQJ4jCHMkhguJItje
me0FqIu/BTWj+KdHLKgVGMmvgvkef0jVTH6Rb44yWsiHHKSecd/UCNCb1Cyl/dg1HEfCD5BssPwf
0jgx2S+8P6//Fi6sCQFOcLEpJ2xW4/JxonTTY2OlzcHhNwJFQSaglbZMxWww3JYPuT1oDqL7dsLP
/phH3Q/JrViVKppimQxt6AIIjXaUgl6y45keNu3VaiXmfTpoNHF7PqviDRuEZ4NLDxlLzuz4CfBi
aAKm2H6zOtI/+y51J+QiwGo1b1dAH6h/Dv/KVyYCAuYNYkg5TmHe28uiiMBghtkVmNBtlWI0Sec0
UEm+ONTLDEnmy+45KAIvY1jTYIgkfmVtjQiny6eg5dq8HAgE195fbmifCLhYTn+2nWIQujW6K2+V
5qZ1UUE+yTjC8l/gm91n8wU22pUv4R0oF136LXFT1vxY087G4gHmBLj/VyKPIOmpVtCsniqyyprU
79CCR34AjOlR3wvk+5ityoHmic6D1MKrbdFaWSFCUx/6VxQE9UYc6KTUUw4m4UoRWn7gtWvyj/st
kJV7hNWi2J2DXTSLB8egekAt3VbwIOC3hZvir3ibt5U7HQjKtfhsO2BNwKeFwH4pVUN/SU0c/GFL
vn82bdk6iXbJtRHkADlrQg6qUkUyFW5225TRHynsPD6CTa/p0R0V01iUgu7WxAzHQqvO36pwQZkR
OWz5nIHUBuBpu90TrRThO5En3jFS2a6e2SCdjFs2QTtU14bdKHHW9MFUH3MaOp38lfzkUys+dURO
O1pjawmdG5ZtB88YsIgHJZ3RudYUH/ihWXV7LnuWDQZawW8KnDQ9LJdn9f0i2D2dPRd+N+qabGeM
r+T0pJ7eHk9dm+Es7jwvrro6pWm84TGdsBg/CgzOqunrJIg9fxJTDkYrwuy53o52jr4PwrpyxcBs
gku3V9uWOet3UA52iPoJP5DxvoFM+XYINqj5ItZrhFaCkr1ML0PwXJI3pnkm2ZuckEbQfzMCKw0q
bNi2jO9Bt1v2Dk88JpkZ+yuno1u9TcSkEggeX0m4HvD2uGf2K4SADLvbSfms59eqAJ9FHF8hAjn9
3JFBoiqR9QR5raDHJDQRyx62WYTv5ms6D2N2vZdHb4CHLKJv1k06PQF/cv7VRxTiaxzOgArrun0+
Z4U0evoyClniMd5nMEBMmq5jlzLIGnHZ8VR2H3briE+DkLtFP9iV6GTQiNIykWluzz+InbMozODB
zGHvWLsOppox8E4N8VKSHjfg96Edgl/yvSgoJ6RPRyv9RRJNoyPHgd5Et/ZhL8ht+f7GPGkaKt8r
hBfRq56waTuYQSHGCvtZTrUMFJt2fRD5n32HH/D5khU1YpsaEbZwnsYVcGPgdCUQ68Wm0iaIRhLn
nWhnJKgzfr9idk5oV/yKIzq00NbwHPs1JqzDrnUg2uxIt/jRONrqSuURwSYYf7iEGrpSyFDyvlzL
T2QUwM0LjDq7/LyYEBtehxRoxVcDLIPUSLmY0gIInvrFp3Nxn8LgVWN1l8D2UrrSXuzIDxzk72yV
i0gGtlRgB3IdL/Dif6ucThtInTWtUskXUX6Ow2g1tAM6YF0kr6yAfp7J2Yro1OE7yQziAElfF/vM
7bSntpqz86b7AOZKm0Qlo3X1C1RO3A3PaeYd+IkmLw0buE6gj6TY8Z6wve2xj6fY2VrDGzD3L05e
mF1KbsP2NGsbCh590h9SvB7KAkI6E0pEMrBMcTojKu4hQ0Db+L2CernoTdIktUwxE3qa7Bz/8WXp
/3Km8vYUNTMaZJ42HeWi0iQeb8Yo+M0oo+qSp3/fFB8GFcPQWcJLQ+A7LZNwgH+WBZfVdrmQ1qIb
VBcCPf1awMnCfHrDUnZE6AhEWqG/ui7P5ipzMLT/f1ukK/hWWMWydgF3qVWygXHfJTwveui+u7ts
ayN0wDe7GaXCSjaklxRyH+o4sF8VJZ74GyrOWEwlM4qp95zTyHSjpkmy2+GzKavgp9suks7Z5iJy
RMjxhavN4didfjqWFd940onVoCp7mMP7zcQvZwiAuGG+9QvzSDatMLNRfyXFSxZPcRkHa6nHoAVT
TfVOqkvFe5J2PSGnjPn20MUzB2e2WQBvUUokVwI3H/RJfaNCHf32had9L18vje+zwI3Oy/tLgeSa
DdLAY2TI25AzktWWqDslZHIb+CB44/vL2Y68j0XNSOz5Fu4KsH/UrG3ngJAxb0rZZH4nCRbc9mTw
hB42eJiLI9YTkaphEBYuzZq9qQVnetEDoCmVRWvp+WiUz4LnxDPUgUjdF1XDFqimwZFbIxwRYJk8
VCqhY/twxOR5StYnTfEF2SnwUAwNtYRvHwGWwRrThWebJhE9lQMlg9jJGYYVlBoeBYyquMuHaPsk
/c7Mj4JLz2ZS0b6aQFeXzwbTvjsatLOPFrOXVnzHX1rtd/rRojFWmQX3Bde/U+C7TThH6KhrB9ZE
wMA2b/jIs0czBZZbPIt8tfV5IWYJ9PahGw90L2uZHC0JBB7klcjlvGfylVU4h9ivrjzp56jE3tuW
mEJzI9Q2PaqTJIMHsnfbbOjdXe9jGogtN4KnGl7VkFh86mqfMInuQbhXcqrNPAjFXoYBZTltbXPj
KTVcLFam3Lb4COBYdA3Al3LKe0dvW28214H8XM6A2clo4qNvdZnPl1zRAFO46zCyH+4wEMR2a+fZ
/Vq1rCJyYh3KF2gpzFK16nuEgXH/eHAwR49hV22edcN6v1C09f0UsyUtW6XqxHh9P+0o2tQR71Lu
/sHtULTwhkEz1VFqUL4Uv0dSKXGe/qRcc2dA6UsZxE67mW55umtsXnoeV8G0gqEx8K4VRAAU7XMg
Wxo8C1QSSZ6sP3tuWX7IjytjvZpGzPt/t5s3jvV1szdeYaBCCQzYWI8eX7BhamB48szebzGjV+Yj
7onLQJ0eFdnIykMWJwia+RqZRthCq6G2n6TfcMyZ2iPBsSKL7qZN7t09FaFoel1zYe5luL2DiMfW
ZaPGyp06IV0nOGTKg6kxizANav8L6sjqbMZm2dU15j29wGymdnbTKSsPRdlS23jdEgTfDxM/moKp
zDSDzYjxq7tsONGvrySABnVnyiIN8jYUINbgAmH0uJIH0J/WDD6jidDvTP0Vq3GL3EudlsQusN/1
uu+/kRXDssfebk9ulRd4WVlIeq6XxgtdQ2O38FkUdHmodEPFcyDVY6IniRNfpcOd/WRpF+jk9RP+
yw03guNmpBaRXPdQAdTQwZVqUsfWf8p+rk4K+OvTWyO3Qii6DW9Gur3NngAGl9qqkmC8LHfxafsg
15EMUaT9rxDfe7ky6ec2PDsiyBuOLak21vFJKQ0GZPm/gWHeg4HfK94SvM8KQVhUCX7huN3hrRFs
5Hb2eCJNyTlXCIlZdQnTLZ0ZSC2iAKwXV4Lks6g+xZi1SGba3VMNFMqZJqlkYZDzt+xCGYFKNleC
Ilq+qcX3wPkq5kv48t528GnhxUtEA0Ct/GlbIiHlZyvC1pTNMbExr9GIvVTtVhOC8g0LHURZ4oAv
Edt3tuMBTWfa1M8hF1blQgiHLPnTZvBNx/zxtUF9ez1YJvZoEixwJvcxUBitvpR5mWoSqn4qdI4t
ifYaVabs6FZm+MF9+cuQLFVRw/iitPKdqvyVfMvj4dZBoz8KhA8cVnrL/M/PpMN6rcqsXmQmQSfM
Jh6IfDGzrnnsmOo/TiBrEnnavVZB7B69ctTIuaYRaN5vjtbbN8R+kfsgLMsHYccFhaxuiNHLa5wZ
JoVm40EH/SlcKJLqoUoL862nLSdkKPAiurahYvP2tEa/uySA/SPFdBHMviJ3RaSB9kGeAOYMyeB+
Vry438iw+WgWbeuh3r+fijYyx7zJ84Iapa7znzNVqO4wnfZFf7KEnwn55lNZXgBr7GAQVmkHRCqQ
x2U1jBrm49n31H7MXDwRs8+fNtdrnTezo+ee4i9RuIH2BuZPiR33X6qzTA3VvwTfQFK4MrQU0rMA
BDNEkNHSg7sjYVWiGRhsutmbhXYuBmazLl7nFHR2HAoq/ayUWxQJqLiXXhPED/feZqrURcRkZ6ra
ecVy1HojKvIdmLjDrf4/HRCzBkoEZCaOddCJnW37boj/noOvJIxX2fVhVKLCCP3199uQeXRQCiHJ
DXT1ZwRSoVw/Mut6F7GeJDhsiCDjtnbGstEMlZta9wCWi3H4sTIlcjvqnu92Wu4C69x43TWfFQQg
os3kMFQ6c7TMRho/6NRK0ewDXzeJBF8TSZlAmtuxG9OVyYxg6B2sKuOySWJUmBb7TXTRvZu9ddS8
0HFAOlplsorMoIGLZtonWyZGfD7IPk1OJITB7utuTWKgfWkLdBZsuylZ5yYhvcuiquWadscNd/Mm
4a7hHqoQCPdl0LA6DO704MaIAq1W+Rlvq3iwlA9FBC1txTW37KoigZVTZHb5N5D75vHe1Ge3wJDn
v/8jKijbMbar7ocAh+inaAQmWlUq2FqqOPhTO6IMH1qpcVeycJNOGwBc8dojJfzCP6hR2JEmrjsv
XZe8PxaMFUDkYiRNR0rGLxY4jcvYuqtBVyhBvFuXqRdZujf21xaASkVcd9xguPS3Ssjm248YrASV
kuCnrdDjN26/FNx/yzL7kLSMYrdbjNLjIsITLP+Gce7B3siI9QTvveC7fbZVdqVAw8oZS74BxxYk
kSgX1CLPBulwlLCphKj6GZ7R6JuMb+ftOyVCeN9CEiirBucBF7PGEsHSUlG91qrzWqFaoXrcGcfK
Avbn+7n5tQ1UJXXgHG0f7tEai684dya/lInbi5ke5kwWg6tl17EWYBziA1vbxXPBN9pW8qr2V55X
Snd4TccSa09mBv4YL46I8s/peO5l10HS+/25RV1rMURdLa6hqFMLg8Lu9fTPCXOyX3gsM9BQk9HT
nxUzW28RjDZdAH+CqzoiD8soUngpoDIPvKbaLxQSx6A3G1BQPAk+C9XWug989Lfy7RyuhcK9ANUy
j8DbQ/2etT1sAbnOg9YgIKJmTtfdNJ/4MpXHzdXrB600cWnP+Hi006LyN+5lFX7KWGmliU5vZ1DG
rRG/0vNFMEwb3RInrqbrUrjEJSB4JI1vMGOj9JWMop7B40qJHmG0GpK/Gi6QXD0oza4xygR/izD4
ZlUAxzMh1sfdgq2cGS6VkYqGt2VZca/bPCdEk/EdPdpLJ97bkS6PDr+IX1MIKEmvalRHXDVr7wn6
dFaX+GhILRRnByiRqtkM4h5Ai/e1A1egjhFc9FvdFCRKahVbDP3jsPicw6OejjU6f1Z1wRbvOLmy
VMvnh7hqaECJ/EflFMO2D6oWWSMbsiYAaW9Kcx7mJMCZpapK5y5Y0OkipF8TZ0hsu+CEPFxzJVHB
5STGfCIqqjaEeaR9m+7zFrNPl7BYfgRxDUUG4D9HYFTJsrVVAI9rO8F70iqHtL2yVkqH34dQwiH8
gWDiM15wmxxt4tH4tZab0ehQtJE/82rOdn48JJBbCKADV/iecZi5CAt4gzbrA7D3AfyoqbX2xWll
RqHOBOSVqXYsmxxSAXU4lj92fYp2qxYc++Se+Rh/zb/70eD3vTGVdxcHI1pqj16+nHCjOGuQJgYS
d/ef+xsrcZdBw6Wl9wA3qQP4JJaFwCjXBV6KTqNmwuiUeXc8Gxx1UdBSR0FcuKgzi3v9NfezIMWD
Nt+vJy5JTKx4vWa4zVt/BMMCYfS0/mI84y94hXiT0T4tR/3yrqsSkeBYGhX9WhOPAitmwZX09pfA
ZpMC6e+tDpDR4RxX8aCpM4Z0w9JKuoH48O519E79Tmvekfu6/a5dggTccKMuFxluAgo3dyKGNt7R
fTW4tvG/B/zZpmNbD7IykaCqYTS1c9pE9eDKvOF2ETi3+1pW7NwdCRg//dKhSJ5CfOx+lZu+vqmE
QfkKoIGG52428mGqJfr+2QiobcEF46YUKz2Ys5j3xravm+uuN9jEmoOk8No3JRrgUTMUwzrdvGel
EgCpGPHXUW9EwkjUd1+5QveKA8moqoEP1OXVplKxXpRGhEZVtGvwHNdgVC65/bYNbmjIp5ooSWX4
6eM/9vnHSGuxfhTBNT+4s4ZSdn1iEqC/79ZcBGu+NhOKn4vytTHXIfr6916/zBWURpYx9heIOyNK
7fMc+uw58qakHflztZOwx0JXMukPp0lShDacCb2Y1Onajy3RI5/3aa32IfueDOQEbPP0FK97Ytjd
F3gG1S5V1iOGvHPf8mvLbbzIsJoE4XQF8vG5n1hqlvqWM1pimwehW6GHUfX3grONPeCikwLeuz2P
klXFl86HbIlpGCj8E7LzQR9wlTeek4ZpVsj4mpM9MT2mSzJmLEz1QNkUfAzSfwQacMT/YdXj2t7D
FFqa+fxh2cBFV+J6iCS3UHa6beGC7aCOwH0NDLYjn1LvVrLiRaY8oG1GDmDdp8GJv4EyeRq8yg+N
0K6/Ih6V4LLIpUkdSe9l1ijsF2yNyYlEPsilXjwQgLcxfmJvdMvBhreMCAPmnLqfrZhCAbQn3xc9
IJpE1LJWLBKEli5jll1opVpID+jQqlLsCP0IJJiaAc3b92HBUxX5OlXetuFciaor5AQ260arkLJe
zUrFTm7T78UMVWepUmv0u5mRoiyhVx6WUU7rxtp99JRV8BK3zMX9DnPzKSQR4hgQFeoKOGGOroX0
bcGc1FzkbiFDv+NUq1oRAEtNHBjLFentgwInolKma8APgypy6Ie3dVQ8qGFAACsWwE3Nzl54PvQD
+MpYd+w2cw8X+YK1OpSZkJwPg6yRA3sK/Mg7mM/SMeYTbtuehGB/pNMuAG0XCf8nbguCxdLRYKgV
x3MqdWHYhUhX4pQyD8k8Cie30hhuGV77/LzTmNlV/ygsS6uhjZAaYIMKmj41QvKPSdPN3rkTPiPn
y4sYkBItnQiIzPjuafVah9e2WpF+tcHZOvAOXL42Vo/OJ86IVeqRXEihB+b/dRwwteCIXBkjvYDq
8Hk5f8BOTHyQz/EUlMA0+4lgBPDEM2T82eDzn3nGcDT/BQuvpwSGqEHJ4lR143DTP7UQbyCaK/Ml
iLDFSc5ApK8wyTdoHtCvLG1eXurftO5LFQDX4gYOAacCWH6ccdWCHIKXSP65rYrHfQI4q7TEzPvr
dfpVjWB+4ATDN57lDy+RdojEgvu/QkYDxS8WjWX2ByOioJ7LR6fGMyX4YzpCXyqJ/YPnXZ3g4fE1
3fLp4B0T+nsclo9t8YCkHUMmXwCqejHHwjBI8K35ngn0JOABqUvp98xoTkrmt1PaohgUVwbNXhYr
AX6d+kkKlERN7W8UhzscQgkoyE4bayRQ7NO2xzipAiirjGxNMdaoxEZOufIIhzkctGYLlHfkY0Rv
4CMtSggfaMPMUcj4tU87H4JMGcoLE64Cba1TeZYBWHoSvmX5M5UOR0OzALKhfB47y3oopmOoUwaE
uGLcV2+hnxFWHiOuKpog62DCVTWZvU2EXCNmk5msAKk1UkS6/5zcwco0nmXBvNjqvOerD1R/+CiZ
mNC6bJkK91v7tNIk0Nz8W5NvPhBdPIunRM3XFu3LH92MXFPW34uaDP6RYqY8L7o0BK5Y7LH4Ti4S
lYPtwoBD6ldmaKrRzW517VtDQOOGfAdO+aDAsrbe24p2xbeae5jJlngMaTfew0wCR19idVfWmtgH
90m45aa767S16+Y2+YioccjYQft/V9F+ucEb1RTM51bin39rRBPOubqpr0i+IUmzE/Z983l9XAKy
Z/mT8ocpO++aup6YleWNQzBLiajIQEk7FV9ETwRM+mUAsURWpEPTJVpasdcbZWUTfKLdYo5CXaSq
9kOH5fSSB03dSGqGun7Zx6oAIvPyQcQ1GUlZA92lolSxDzB+7k6BqUffAPwlvnss68d98+p7fNAZ
S0t25/T5HfOxPqiQ8NA22B5xOEajRNA05uwp/ih29rw43UQ2648aScWwx/2lPVfmb76vjmeIbtBe
bDu9dtJZDlCTMroEsIqKA55yIemlvQLETHiErcx/jf+jtykGsn9PUec6zG7AQ5zL9A9T45MjzaTa
5Odw56x1sSmwaSk2ODOIrNR4w6Kl89loAvFz1nSD3fDLwsWifEwK9NjwQjtxYXCPzjo7HfW04AUK
Pg9/0pcQkehiMBBYrhva46Af1L0FE9INiWppQTc4GKqMVoet22MWYdqVfCYOyJ2mBIkRdKzDwY6E
5g25yqs9ifgIS3MTteujq5PNzJQ8ACoLH+95XGJbNkDAIgL+y3Oms8Og332pANNgop39mBHpiZ3i
r8mXJXl5xm4/P8EXDwh22EBl15W1iF8PwNWJnfxL12dwr9bJcXFhk3ckbKKBhqju7qSRnN89toOV
OlLI3HxSbIhA9o5F6q6bS1Q1XlRb+3pA4sha4KufPt0wsCDaHn6VT+3Sthz2oyL5XdvbWmhJzpMm
dQYm3IIv3hgwXnCPZ6YhLmMqGP5FIjDVGEbzgx5O49P0gwHJ3CfY8xorBWUsRjGdCAG2xvfNnqEk
5f3TIPD6Nc9zrg5ezIMKKYMXkWo+o1V3w/r6prtqmilUOBoFYX4VYslQZ0Yocs+CGt1/mEC+KSuR
Af4MiuWiW5RPNfwcbDT06O5Af3DrbRQZQCBpBghTdQlxkZXtnAzst8KxXbiEVqXX66bBiavtm0O3
ipRE9n3/ld707Q/qbTjAP5HrUX1ysnVMOhc3LIeXM/8hOkXt5mpFmIx0LtCnsuJxeHniUQUS8V7G
MmsU4Wm5barg0Zh7yyJ1IFkcyA6d5hSu2IXy3zKcNIhhERXIIeHaoTA2FpSuwcVR0TSNED5e5azW
CFRid51r9ftkUroTCdaaPwte/gyRxJXNVYrQ4hLl2eTYcfY02Vl7g1VP/7ppeMoR1jK3FyLT2B3N
p+q49uggfzk/MhJBKFSp4EvOIaUDoRiwGg4TAHSNvrNSwdQMCwxrzRc4vI580YpRtx62o/vCBugd
mfFshpmYtEw83POB5X4+EHa05ySins7fTkhtIKQ9LpTLmsG6ZvM/heCtk8ee3OeudfVdTFrAN6Bt
8vClT8TV/74/6grsbdb1WdFfcYd4izua0C5Dzj8G1fPDKnljCXA3ful1RRZlvaGohPbU8OzgiQQZ
O/HtzPShfJ1XlnpgLbj759pJw2+lR1qljNSFiwDgZiZZf5WAytVlRGstLufPRHytGG0a9NckYrI3
DNRZeMFjRonbu+HK5I1/Lhgg0bwqEVRA1jcrNSsMYzJU4+WNwmj7Valn5M6RTDejTkSsOrmk/BDI
JXHMf/3eKHFeRzKKL4r77S/X+nCIYP1zm8D4G2zfu+hFw5BsrY5v01B2zvyil8mzXc6rchCAMeY+
Ihn3z8Xed5JWn0+V34/WfCEs1w/fYlRbv9yPnkiv+UK09CajnRSUvTw/urBDAJ9S6KPmoQlFh/H+
5Xdv7vZMOiIywd5NAO0YbvU2Y8G6pEX00iRkBxdzqAZZ65TaLOh0iGD3JgGMP3qPR8xQ+vQeyTyO
0AbmNjB+lGgoNHMSmIvXc2zTdWvojeSxxoAKKgFFCUim3MatNRm/JqnQswqK1jbAeh9+85MSQlAs
c/vhzHn5awcyFAN27haTnemJ6BFcb+MiB7lndGDdfJpSYaGKsDhafmJOm9fdvKBp2s0vpWhYEFrh
kEf0U6ojK/fBgK38qOeKhq0LPWAPKwXffgXdt9x/kFtqjxwJdV9GeTq1AlLYjRhnRuL68/N2KTd/
/PQ6Da9O9cw/HLzXXrL5XkIHrJG/8B4QXVj2WieWhj/U7B2QTFru9jus0+zlQRUYNBPOtC7m+deu
nEjZW+2vOMMEmFKovn87ovwe70hhzKsfG331CAR86VeOUfIKKbNINhMb5eJPsrmSEYjWBrxgEHG0
RoUuWLo8nXJI66hxc5LkzRBZOXbhIB4zohUwtoNXYjqlxHb0KIGMKr3riEPQd/fKNPAniwu6WaoQ
LkvP4J648ZPLA1yazm0DVzLf/Hsl7hUl5J7yxNZpq/xAmxmlBGv5TJaawRjsdcWJbHlhd5Bxs5tu
H/CxAtDpzctKE22yPBSDJbli+q58lJfkxi9J8AF4+kg0aOPqsPSDXZVy7IF7DXMPi6WZ/zUsQrwF
4yF6FLQ9XBWF8L1XYXX16lUJMu5WCD7SJ3bJb65qr0+8NLa/En3qOV9CNX1AAdaqi+sVl7WC6OJr
yUYLGJIrUB7w5xWtGDwSsoH0h5q5S9hfHFzcp2GQnwnjA1lMFtlKFYaY3eAIGprgGAHi/QFx3eKc
57xnNn1/2h5lbOAMdl4f6JvfDW6LI8vKDQqzUsVSOTAnnl3WZ2U7OltBOsnzEstgsUSu/9jZe/FU
Q65FQMKRMHKBzc7Z/s+pmU6yswfMaQb7hlRPC7NfqOaQ4ZcGZi/gBGxn0McPMeqyKp9DG3nY3PTk
gl837Amd1iHWywGMqD7+8SQdUaIQNDlWvmrdp4StvguvI3qxbBBXJHlFSdLrfpBVpjG1QTLhzVC9
3jhxOJlXjUxiJSvZeQ/O3QfmS8ahJLaE+uUYv1ur5Z7mIav/ABKQFxH7tozEuxcLefJB1bJKusyO
45tJEvlyhvDyCIAxnBjxUDSeFm+HOjYpx/1SPDfpfGRrfG0b+nERdRadJP1GkfVbnJOhdFtyOGIi
AdemUt1qhrZiXNayoq+Yr4rpI15omEvC2i6HMCFkWNpUIMI6W8kObdWtC9uPxZ1RWtQd5lM3aHqc
mO+Bgl//PPC8O6v1avUua5biiX3DkNx6JkmmPtIFrgdyYWiKU6dG47YLcrfIOIn8zeOQ4CoAQvLU
ZHscoOcOKIgc6CSwubocETPtPXdxiSoxDqNVQrGcmKMSFWFZJ8bjdZ8RlR6t+XleMsN+vW9lWupZ
9aDkFY5daJsk0s64/9jGGlZoT+vaZNXJreekk4HdLclW8sr4mhKN75MXySYAxl5uJ0CiYzGG/qzl
/lAf3Y71Ic7VjF75fxxGBy1/uz8IhzW2qToouPIIveKl1EFbYdctq1nLce9iIQXCjlQHBcpDjfsm
6PszWmc1Nb3HYXZg72axtTYWjZt2R3EYX8mHNsHLixcztCqps2lfrqgQGFDMCZXo84IKVagYzaIx
yxNWUsfj9TXqPaToq1sAk7XRbdkw3oqEQOrgNEn+E8AJ7bViP3XeUrRoq5KRMdQcpR7UkMSYcqS3
iBtldReCPZwATLuBTEF1xImp/ieHt/PY5Fv6WShxkiE9mPOwoSqbjNfwyIFUGWmJ6A2GhO0p+GZH
gdEqM9+dOPC4UJu0fdMUYQPDuxTdy1e0TwAKzjpt2PoD+u4BwkHePQWTKxsF/ORUbSU+MLrC6JVR
3SHI2oXihzejmNTIcl+gnVhcVn+G2zGevmMJnneCvXA/0IRvie9SeWovFfsv8WCdA8kuJ8aOvLyX
OLotDgGAaD+5NwOXWhfc4EHaRI3+dYNYRnqm6v+dfiVC8LS/Qe12K7KlQ+2MYp4CMqh/lXaUYdzi
lwGLoDAm8X/+OQfcO9TpMmOJtB8r1lFgU/MuBddtLx29wj3Jslp4wJ+EMJyYkHiLLkETDPt3Bt9K
XS3iMsd8MNhB/PCWrbYyg/GL8teSkt+tFsEC++Zhv/6R0+ul0l8q4buzzi1X2xSlnousAdX6gojl
AhauX1FiaIA2rd0qWzP2LPo4dkvFc4cR4EifwMfGWhIeyfBZEGblbgzPOqeKihSQNpwQD6HAQ0US
EN7wsErtyRXs1GmOt5N4Kru0Ge/B2OGiZuTZo397Fat+u2xgImWwCuUdx08LJgD6W7BMe2K5WTiF
aLP8s24iaJpS4GLfnJ0bM2k1ovNbExmOswWVKwpxoJ2rRcT2LKbtmJ1DbsVasWSjQ/IOHO7ZorvN
tBIHq0jDRxTNAuE6hBC/z6Ddh4ZWa3o171otZWOqOf7q+WnBQY9LS1NqKrZ722cYavOk1P2zIj/j
dNRJ/503uQ2a2Go1/M1n5MZtcalvoFIggyt1ge8yykFzgd6PTHarjDAeVPQ4ftnRWRm1EuCcW0kj
9um8V4B8NINnLbB4YAXQFqP0wZrpzcw8Xp/iF93GF2YuzwYUlkgffGZQItN5UEVVUxPtEff++qhv
T7/xUoBvCtO3aSsnwxLbfwaW83mMZitgMjSz5547BSVvdflhiegFTVstgNGnRf9EQXCYy3vVPHy4
VFxqZFsBTjWNrVO3X7D+eBlR48jntw8fXWjNYx4Ce5lxbS2EauuBOshwLOJmEJnboxmdIMRt37Jt
wqzErziCNtReLlfwaWL6RXlp+00SZxR6E9tQxZzGURXqyi+5LJF/cXyUNp//hLh5CHXyk7nWhSE6
8vL1BDy1nkI81o1+Uo8PCQZ8aVWTTXKoW9+wgBnGYRgqHLfanXZ6aWtbyP7rG9QqvruwQN1ixyhu
b4/1lgL7sXsoFwSRA+3ifKJKy0M9lZAk2XDEHhRczPjnxW6k6GeijwF/rQQYDtEYeKTz26r1P/iQ
z9tFZQNRcjxL5kcWZCIyBF8s3V8o0yhJ9HQn1UaTQAtxY52vMvPZmp96pzi0d37V4HjWZhoyVYX5
J5OmwmqFR+JzkXepJvRspbW9HQdGWIkea4OSW+ghl5mQVd5jKem0dLuXpHO9kZepQwpO0g72FADo
2A816A+rZkgcbZ8f9JLKsBCW80qdkv2mXMgLhH+Q7aZORbIkWF3F+iKhm5//lCIyXSBrXXpBIfNA
5FFK+32ubAJNU79gLtZ/83Mu0rFNDvzMYjk15crvY4bkdYx9tRawm/Yh9PwvT9cQ1SUvdycmRft6
ZkX1BhuebOsUSeMnjvUZMCNhhtc1LhwN9zhR+OuJUP5bHhJoXkpewL1R//NMcRwWQrXZgsPzPwvl
EvuCv6p1rf5f/y1O5F69PBRxsM2T+4omea4FACIKvQhYk1QiSKT9C3erXmmLlckPPUiKibhZKUYk
2p3WPISTSxCL4DUksWGxeveWtGR9xgyVOy/d691i/eAPgKuXvC5s9ZCsNSrPfPJnjxUVn7pTZz50
KuaTevLXwkFWq2a9oXGNPqPTZv6D8J9dxA2QKdyUflw5JM9xja7517Nld7SEPFzHJVvkJWyh3Z2P
6l/hEsWCqkRebFlx4JJ3fqVHYIerguka8HhqM8bOTCFazeOvH0EOX6dckoYWA88NJTkBmjiZJHde
HHFqc5OW1L4ByhRnzB6vg1WkcEguZ1TL+WH4oP+Mvl21+yCNkhoeXmIBhmMjSSTcRcQEXlZvoa/e
i6T9pR1qpDGMe4F3S12ZkoYCqDnnE1qupZr685yYnRFMuyMf1VjBlA3PEr8Hl7gdxjuQU9lzqItF
95gQMyAFSDsuuuqCc6lsPU6090hgQdb/rr0ijX4HQUoHQTuCwSLyBRDDTTSJ0JijVeqNF7RUyVzB
SwxYsT7Ghn0cS1CQjxUaas7bLaO35QsSTgiHlP480KeD5K/o1+IhWvQXGgpa+bsmlKdwV/ZCYbbx
aRG+eaIlt5qY8p65mN360N054GdXfCgonKBvvPN9/o1KlKrJbj+Eykhr2B0BO1NSlUwx2c7cEUQ/
CVY7R3yipNcs2WNjqNKV+mZGvgEOGhRpTuf5vkaHoeKWOgmkNiHuql1kQ+IwIg0xa1iVVocH1JWr
IPnLnLJ+MnpUoXyokJWlP6H5n2ww/NWN4qNxG4hRFvo1RJ1Km1VkzFhfjaMQw851eED4iIJdAUEP
ECHQDiUDcvENFVsx4rxkrsGPEjlRP/y/N+0F3OQEDJbMjH42wlIzYKeMM/6Nt4jt3SldI/96bxmf
uexWmc9cWCsdKcQwzv8l2XKQ/CGwH77tt9+riw4YEzLQ2XKY1s54ZikfQLp+jLaFFFfHwxJE8iYa
zCbTfXP3RPV04YUQoU5efkHMgyJ/qm7ptK3PvFbquSgCDilTbVLKFDMOYaBSfbj39Yuxj6G1HE4w
Aou2O3bNlUd08j4B1zD7p2dF1y+b0XJjdqY3dzsor6zyCzXUZVL4dvhMVd7nJYoM6JyCOfQ0OUVD
QA9ljqWKw5QJelb8VL3pTS8PVOSCfYmaKoC9Eb5+iLhRsED2t2/OS7QBmk3mJw98nwAgfid87WkW
3VlUO7MrYfXpx5gM63/XAt0qL1bFHVdA39k4+eLwf15zWsfq3r6wvToLUGjYRm/f7ZjnLNuMfdLW
p1B1eAKMCNEZbONAlKcMjqa6KRO8/Q6al2gLq/NykPz1SqLa/N/4VVAI5t2h4bm1P11HnUvfzRlq
Guq3hMVlFVUmRNdmsHmmdn0MMwptZWdwxeoF8b+C7rlx8fB/RkhZhPkdwAd4zAXrsY5b/JndAIj7
uacaIlEH7g7/Xk/ShrZ3Z++yl5Y05LmV1s9bU7T5aP3Bl/C8G+S8kU67xV2Z71tRBkrcwwMLe6j0
rxJkhRrA0j6AQOJKom79SeZh53QOCrrmtjNqouue5Y9UIk6Jt3nqvYtB6LHmS/FmQHff3Tx2k/j8
5p1waIQrfGd5eKLZaqsr8bzfh0PYm+NIcc07Au6uNrX89VupJT1sfd0X2an0IGJyc7wSrkuvY6MP
b2g1PzLomAu6vuaNbduyooMvY7EAtKLml6orJ5guDFAuR3Wtbvt73QtZWhfK2iruN1rE7z35sjN2
J7mkxoXEHpDnDnHdpBi6+mwrDtVMqi1424fv870/AaCS55V0ZyoL8c397hneQ5Laa9FSCb7hAdf5
B1fsAkw9zvYw0ITyQwjk9cLvRPJfQQ4/aAFcLqPDNgsMtJE3TAUG7CUeOf8Aoxi6P9u6ApQK0rlm
wMASz9f4V/3plQs7Oexe5yVsGvmFavnK2VqrN+KSRXrz/IRbkeR7IAS52fqAQ0C7STw8oVTMr5yq
maOPEfsBOEcbUwdYzfhI9oI9vVr6vZCxfZ0vltKJW+Z/p9yfScOjWWshk0IE6T1aQ/j5U7yqD5n7
LgB7I9yeKChyjOmF5Iw91J6+J6V69cSIKEy9uLU/XLrj6LMWYb4tcVQrxNXLKARsI5BCcrXhnaJl
5QdYprRdn521MzKkKOyB0ZbC2KKj4G9vfSVnqRJvI4sIwXgNt+Ri0qIhA+mMsIE1rljVKbh9f9sq
p05h8Ez15HG+NcO70Yt9BTNFy/z+vyh1S8z4taiNZkCtPPtpR9PSsS4txqiCRQW3dEM4wHPTWX6L
GEjtbu+MFNg8aG/U7JlsPIlT2XDXXwaVINs73tz6tJWWRQdhUF2kM56EQnPbzv7+ZHJv7X36ubsu
BCZMWCmaBOQmkHIPuIlRp47xGkIMHuUIMF9yOABCtb4FePTkB0UG1rRQrGGQgaV47IJCRzMlLjC/
U3ftnz3/uKtjoYbv/9ATzm5/qZTktBCt+0SbwwHne6mGaply7iwzulBBB03cqUBSQZKGfqD8eTGC
95Fe9s/yeD7yYGsqMa+ebyhzGuuQpa3k7zQckn+bwF5IaXnwCorLtEDmgQx/wbf9PhOWP3L/lD4o
8/MM2veLTsfQALbYevn5zBK1fgPkP/4Bm9Jhq1HOZsKn6yaDBIb1f92QoaIuL078Wj5vm9om7RFw
SQ+lYU1kzU8m6vCXixhGSjXwlsyqnXvnwT8eF/h8fG/ELkMMp7zeDg4Y0VwLSlntcf2H4PwRAwRK
C7DYX1MAZwBQ8jZp4LgM67dSHm24Ebc6z+8hbkhjMeGsYP7HX+YhdqswleX+X3QB1ezeWKGtsoRt
L1Fib7TqdIZUj+LnDdGq4wWDDgQL6pz4T4S41NMvPM4c8W7S3FvHLj8YybtcPVE3qDvFt/jlh+B3
mVqufjrlPMAf4iJWvSkVePMEm8fWNKSLJMJP8qgMvBo1malN4+44uqNM2g2229iCufjrlciVs04/
2eHcdhjEC9dLpUIDMadigdOcm3qwnqBPP7W4R4GFtGV944wuRJnsj4vXCv9Bo5hMykPvwKSUNjO2
sLTG5Xw/ZINcx1feXxGQ1Ku8zfHe3wZderi+XWveR/Sn31JvvYmc8cJXmsaytRlcaWIxVaTI+qvd
raMg3KmZfp7oMnw/7NDsZrMg2eM5bd8XGj5QNZC0BT15v2ejm1qa8saTldUtBM5SxgDSvyGfJNYG
8FLuas+uOCzvgLlaRSt80k7ORFCtDO5laXokzPxi5ZHvrLRU+xFP3R6K9PPnf6x55HDFI5YZJN13
EPJpuVS4Cmf36ErHjKNKns+zudqe3VhsYOh/LfSZZ8A4YjjUP8QSZrkUZEqyb0tO3LHpwKAeKwI5
rUaT5FKl1I+gpur1gyvjzYC4vzul+qAXM6vOur4SS4T5IXhUg/12Du3mPQI4bECMJHpZoczrai8g
RtpEVeS7apoXsWnMYCPwMBfuyTmQJxyCZ9eb5K/mQOSwRNXn5mVgbAZZkFUFmh9clk9zBqCvdc2p
Jr6q+LVyQGhU9oL8EDj9GExgO83utSA8bFRCbXuSJrtkR0xTNyLQX4EVjk6V4ZPPEzsnC6T+cv51
LGxd/diEcnNRFlhz87Kyf992aPNMsPM6T3PERlZapgMpZ6Cs5+V+GRgYfY5mPw3T9GqCJTVfGiou
VbVtHrJ2pzEn0NYa9SN1tspP7h5DpVv+mlautuUyNlx1nuFVHgqWknqihXu3KlGSBQJ8I8gTuKsq
uMf2QIh/wHWw
`protect end_protected
|
--
-- FIFO. Part of libstorage
--
-- Copyright (C) 2015 Olof Kindgren <[email protected]>
--
-- Permission to use, copy, modify, and/or distribute this software for any
-- purpose with or without fee is hereby granted, provided that the above
-- copyright notice and this permission notice appear in all copies.
--
-- THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
-- WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
-- MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
-- ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
-- WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
-- ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
-- OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
--
library ieee;
use ieee.numeric_std.all;
use ieee.std_logic_1164.all;
library libstorage_1;
use libstorage_1.libstorage_pkg.all;
entity fifo_generic is
generic (
type data_type;
DEPTH : positive);
port (
clk : in std_ulogic;
rst : in std_ulogic;
rd_en_i : in std_ulogic;
rd_data_o : out data_type;
full_o : out std_ulogic;
wr_en_i : in std_ulogic;
wr_data_i : in data_type;
empty_o : out std_ulogic);
end entity fifo_generic;
architecture rtl of fifo_generic is
constant ADDR_WIDTH : natural := clog2(DEPTH);
signal wr_addr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal rd_addr : unsigned(ADDR_WIDTH downto 0) := (others => '0');
signal full_or_empty : std_ulogic;
signal empty_not_full : std_ulogic;
begin
full_o <= full_or_empty and not empty_not_full;
empty_o <= full_or_empty and empty_not_full;
empty_not_full <= (wr_addr(ADDR_WIDTH) ?= rd_addr(ADDR_WIDTH));
full_or_empty <= (wr_addr(ADDR_WIDTH-1 downto 0) ?= rd_addr(ADDR_WIDTH-1 downto 0));
p_main: process (clk) is
begin
if rising_edge(clk) then
if wr_en_i then
wr_addr <= wr_addr + 1;
end if;
if rd_en_i then
rd_addr <= rd_addr + 1;
end if;
if rst then
wr_addr <= (others => '0');
rd_addr <= (others => '0');
end if;
end if;
end process p_main;
dpram: entity libstorage_1.dpram_generic
generic map (
data_type => data_type,
DEPTH => DEPTH)
port map (
clk => clk,
rd_en_i => rd_en_i,
rd_addr_i => rd_addr(ADDR_WIDTH-1 downto 0),
rd_data_o => rd_data_o,
wr_en_i => wr_en_i,
wr_addr_i => wr_addr(ADDR_WIDTH-1 downto 0),
wr_data_i => wr_data_i);
end architecture rtl;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1709.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c09s02b00x00p10n01i01709pkg is
-- Type declarations.
type SWITCH_LEVEL is ( '0', '1', 'X' );
type S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
-- Define the bus resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
-- Further type declarations.
subtype SWITCH_T is switchF SWITCH_LEVEL;
type WORD is array(0 to 31) of SWITCH_T;
end c09s02b00x00p10n01i01709pkg;
package body c09s02b00x00p10n01i01709pkg is
function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
begin
return( S(1) );
end switchf;
end c09s02b00x00p10n01i01709pkg;
ENTITY c09s02b00x00p10n01i01709ent IS
END c09s02b00x00p10n01i01709ent;
use work.c09s02b00x00p10n01i01709pkg.all;
ARCHITECTURE c09s02b00x00p10n01i01709arch OF c09s02b00x00p10n01i01709ent IS
signal A : WORD;
BEGIN
-- Test signal arrays indexed using literal constants. (locally static)
TESTING: PROCESS(A(1))
variable INITED : BOOLEAN := FALSE;
variable NewTime: TIME;
BEGIN
-- Perform the first piece of assignments.
if (not(INITED)) then
INITED := TRUE;
A( 1 ) <= 'X' after 10 ns;
NewTime := NOW + 10 ns;
end if;
if (now = NewTime) then
assert NOT( A(1) = 'X' )
report "***PASSED TEST: c09s02b00x00p10n01i01709"
severity NOTE;
assert ( A(1) = 'X' )
report "***FAILED TEST: c09s02b00x00p10n01i01709 - Signal arrays indexed using literal constants may be used in the sentitivity list of a porcess statement."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s02b00x00p10n01i01709arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1709.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c09s02b00x00p10n01i01709pkg is
-- Type declarations.
type SWITCH_LEVEL is ( '0', '1', 'X' );
type S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
-- Define the bus resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
-- Further type declarations.
subtype SWITCH_T is switchF SWITCH_LEVEL;
type WORD is array(0 to 31) of SWITCH_T;
end c09s02b00x00p10n01i01709pkg;
package body c09s02b00x00p10n01i01709pkg is
function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
begin
return( S(1) );
end switchf;
end c09s02b00x00p10n01i01709pkg;
ENTITY c09s02b00x00p10n01i01709ent IS
END c09s02b00x00p10n01i01709ent;
use work.c09s02b00x00p10n01i01709pkg.all;
ARCHITECTURE c09s02b00x00p10n01i01709arch OF c09s02b00x00p10n01i01709ent IS
signal A : WORD;
BEGIN
-- Test signal arrays indexed using literal constants. (locally static)
TESTING: PROCESS(A(1))
variable INITED : BOOLEAN := FALSE;
variable NewTime: TIME;
BEGIN
-- Perform the first piece of assignments.
if (not(INITED)) then
INITED := TRUE;
A( 1 ) <= 'X' after 10 ns;
NewTime := NOW + 10 ns;
end if;
if (now = NewTime) then
assert NOT( A(1) = 'X' )
report "***PASSED TEST: c09s02b00x00p10n01i01709"
severity NOTE;
assert ( A(1) = 'X' )
report "***FAILED TEST: c09s02b00x00p10n01i01709 - Signal arrays indexed using literal constants may be used in the sentitivity list of a porcess statement."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s02b00x00p10n01i01709arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc1709.vhd,v 1.2 2001-10-26 16:29:43 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c09s02b00x00p10n01i01709pkg is
-- Type declarations.
type SWITCH_LEVEL is ( '0', '1', 'X' );
type S_logic_vector is array(positive range <>) of SWITCH_LEVEL;
-- Define the bus resolution function.
function switchf( s : S_logic_vector ) return SWITCH_LEVEL;
-- Further type declarations.
subtype SWITCH_T is switchF SWITCH_LEVEL;
type WORD is array(0 to 31) of SWITCH_T;
end c09s02b00x00p10n01i01709pkg;
package body c09s02b00x00p10n01i01709pkg is
function switchf( s : S_logic_vector ) return SWITCH_LEVEL is
begin
return( S(1) );
end switchf;
end c09s02b00x00p10n01i01709pkg;
ENTITY c09s02b00x00p10n01i01709ent IS
END c09s02b00x00p10n01i01709ent;
use work.c09s02b00x00p10n01i01709pkg.all;
ARCHITECTURE c09s02b00x00p10n01i01709arch OF c09s02b00x00p10n01i01709ent IS
signal A : WORD;
BEGIN
-- Test signal arrays indexed using literal constants. (locally static)
TESTING: PROCESS(A(1))
variable INITED : BOOLEAN := FALSE;
variable NewTime: TIME;
BEGIN
-- Perform the first piece of assignments.
if (not(INITED)) then
INITED := TRUE;
A( 1 ) <= 'X' after 10 ns;
NewTime := NOW + 10 ns;
end if;
if (now = NewTime) then
assert NOT( A(1) = 'X' )
report "***PASSED TEST: c09s02b00x00p10n01i01709"
severity NOTE;
assert ( A(1) = 'X' )
report "***FAILED TEST: c09s02b00x00p10n01i01709 - Signal arrays indexed using literal constants may be used in the sentitivity list of a porcess statement."
severity ERROR;
end if;
END PROCESS TESTING;
END c09s02b00x00p10n01i01709arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2960.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer;
FUNCTION boo ( PARM_VAL : character) RETURN integer;
FUNCTION boo ( PARM_VAL : integer) RETURN integer;
FUNCTION boo ( PARM_VAL : real) RETURN integer;
FUNCTION boo ( PARM_VAL : string) RETURN integer;
FUNCTION boo ( PARM_VAL : time) RETURN integer;
end c02s03b00x00p02n01i02960pkg;
package body c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN 1;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN 2;
END;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN 3;
END;
FUNCTION boo ( PARM_VAL : character) RETURN integer IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN 4;
END;
FUNCTION boo ( PARM_VAL : integer) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN 5;
END;
FUNCTION boo ( PARM_VAL : real) RETURN integer IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN 6;
END;
FUNCTION boo ( PARM_VAL : string) RETURN integer IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN 7;
END;
FUNCTION boo ( PARM_VAL : time) RETURN integer IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN 8;
END;
end c02s03b00x00p02n01i02960pkg;
ENTITY c02s03b00x00p02n01i02960ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
SUBTYPE bv_4 IS bit_vector(1 TO 4);
SUBTYPE bv_6 IS bit_vector(1 TO 6);
FUNCTION foo ( PARM_VAL : bv_4) RETURN bit_vector IS
BEGIN
assert false report "function foo in entity e" severity note;
RETURN PARM_VAL;
END;
END c02s03b00x00p02n01i02960ent;
use work.c02s03b00x00p02n01i02960pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02960arch OF c02s03b00x00p02n01i02960ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
c1 <= boo(bb);
c2 <= boo(bv);
c3 <= boo(bo);
c4 <= boo(cc);
c5 <= boo(ii);
c6 <= boo(rr);
c7 <= boo(ss);
c8 <= boo(tt);
WAIT FOR 1 ns;
assert NOT( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***PASSED TEST: c02s03b00x00p02n01i02960"
severity NOTE;
assert ( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***FAILED TEST: c02s03b00x00p02n01i02960 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02960arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2960.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer;
FUNCTION boo ( PARM_VAL : character) RETURN integer;
FUNCTION boo ( PARM_VAL : integer) RETURN integer;
FUNCTION boo ( PARM_VAL : real) RETURN integer;
FUNCTION boo ( PARM_VAL : string) RETURN integer;
FUNCTION boo ( PARM_VAL : time) RETURN integer;
end c02s03b00x00p02n01i02960pkg;
package body c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN 1;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN 2;
END;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN 3;
END;
FUNCTION boo ( PARM_VAL : character) RETURN integer IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN 4;
END;
FUNCTION boo ( PARM_VAL : integer) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN 5;
END;
FUNCTION boo ( PARM_VAL : real) RETURN integer IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN 6;
END;
FUNCTION boo ( PARM_VAL : string) RETURN integer IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN 7;
END;
FUNCTION boo ( PARM_VAL : time) RETURN integer IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN 8;
END;
end c02s03b00x00p02n01i02960pkg;
ENTITY c02s03b00x00p02n01i02960ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
SUBTYPE bv_4 IS bit_vector(1 TO 4);
SUBTYPE bv_6 IS bit_vector(1 TO 6);
FUNCTION foo ( PARM_VAL : bv_4) RETURN bit_vector IS
BEGIN
assert false report "function foo in entity e" severity note;
RETURN PARM_VAL;
END;
END c02s03b00x00p02n01i02960ent;
use work.c02s03b00x00p02n01i02960pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02960arch OF c02s03b00x00p02n01i02960ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
c1 <= boo(bb);
c2 <= boo(bv);
c3 <= boo(bo);
c4 <= boo(cc);
c5 <= boo(ii);
c6 <= boo(rr);
c7 <= boo(ss);
c8 <= boo(tt);
WAIT FOR 1 ns;
assert NOT( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***PASSED TEST: c02s03b00x00p02n01i02960"
severity NOTE;
assert ( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***FAILED TEST: c02s03b00x00p02n01i02960 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02960arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc2960.vhd,v 1.2 2001-10-26 16:29:50 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
package c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer;
FUNCTION boo ( PARM_VAL : character) RETURN integer;
FUNCTION boo ( PARM_VAL : integer) RETURN integer;
FUNCTION boo ( PARM_VAL : real) RETURN integer;
FUNCTION boo ( PARM_VAL : string) RETURN integer;
FUNCTION boo ( PARM_VAL : time) RETURN integer;
end c02s03b00x00p02n01i02960pkg;
package body c02s03b00x00p02n01i02960pkg is
FUNCTION boo ( PARM_VAL : bit) RETURN integer IS
BEGIN
assert false report "boo with BIT param" severity note;
RETURN 1;
END;
FUNCTION boo ( PARM_VAL : bit_vector) RETURN integer IS
BEGIN
assert false report "boo with BIT_VECTOR param" severity note;
RETURN 2;
END;
FUNCTION boo ( PARM_VAL : boolean) RETURN integer IS
BEGIN
assert false report "boo with BOOLEAN param" severity note;
RETURN 3;
END;
FUNCTION boo ( PARM_VAL : character) RETURN integer IS
BEGIN
assert false report "boo with CHARACTER param" severity note;
RETURN 4;
END;
FUNCTION boo ( PARM_VAL : integer) RETURN integer IS
BEGIN
assert false report "boo with INTEGER param" severity note;
RETURN 5;
END;
FUNCTION boo ( PARM_VAL : real) RETURN integer IS
BEGIN
assert false report "boo with REAL param" severity note;
RETURN 6;
END;
FUNCTION boo ( PARM_VAL : string) RETURN integer IS
BEGIN
assert false report "boo with STRING param" severity note;
RETURN 7;
END;
FUNCTION boo ( PARM_VAL : time) RETURN integer IS
BEGIN
assert false report "boo with TIME param" severity note;
RETURN 8;
END;
end c02s03b00x00p02n01i02960pkg;
ENTITY c02s03b00x00p02n01i02960ent IS
PORT (bb: INOUT bit;
bv: INOUT bit_vector(0 TO 3);
bo: INOUT boolean;
cc: INOUT character;
ii: INOUT integer;
rr: INOUT real;
ss: INOUT string(1 TO 6);
tt: INOUT time);
SUBTYPE bv_4 IS bit_vector(1 TO 4);
SUBTYPE bv_6 IS bit_vector(1 TO 6);
FUNCTION foo ( PARM_VAL : bv_4) RETURN bit_vector IS
BEGIN
assert false report "function foo in entity e" severity note;
RETURN PARM_VAL;
END;
END c02s03b00x00p02n01i02960ent;
use work.c02s03b00x00p02n01i02960pkg.all;
ARCHITECTURE c02s03b00x00p02n01i02960arch OF c02s03b00x00p02n01i02960ent IS
SIGNAL c1,c2,c3,c4,c5,c6,c7,c8 : INTEGER;
BEGIN
TESTING: PROCESS
BEGIN
WAIT FOR 1 ns;
c1 <= boo(bb);
c2 <= boo(bv);
c3 <= boo(bo);
c4 <= boo(cc);
c5 <= boo(ii);
c6 <= boo(rr);
c7 <= boo(ss);
c8 <= boo(tt);
WAIT FOR 1 ns;
assert NOT( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***PASSED TEST: c02s03b00x00p02n01i02960"
severity NOTE;
assert ( (c1 = 1) AND
(c2 = 2) AND
(c3 = 3) AND
(c4 = 4) AND
(c5 = 5) AND
(c6 = 6) AND
(c7 = 7) AND
(c8 = 8))
report "***FAILED TEST: c02s03b00x00p02n01i02960 - Overloaded functions test failed."
severity ERROR;
wait;
END PROCESS TESTING;
END c02s03b00x00p02n01i02960arch;
|
-- This is an implementation of -*- vhdl -*- ieee.std_logic_1164 based only
-- on the specifications. This file is part of GHDL.
-- Copyright (C) 2015 Tristan Gingold
--
-- GHDL is free software; you can redistribute it and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation; either version 2, or (at your option) any later
-- version.
--
-- GHDL is distributed in the hope that it will be useful, but WITHOUT ANY
-- WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with GCC; see the file COPYING2. If not see
-- <http://www.gnu.org/licenses/>.
package std_logic_1164 is
-- Unresolved logic state.
type std_ulogic is
(
'U', -- Uninitialized, this is also the default value.
'X', -- Unknown / conflict value (forcing level).
'0', -- 0 (forcing level).
'1', -- 1 (forcing level).
'Z', -- High impedance.
'W', -- Unknown / conflict (weak level).
'L', -- 0 (weak level).
'H', -- 1 (weak level).
'-' -- Don't care.
);
-- Vector of logic state.
type std_ulogic_vector is array (natural range <>) of std_ulogic;
-- Resolution function.
-- If S is empty, returns 'Z'.
-- If S has one element, return the element.
-- Otherwise, 'U' is the strongest.
-- then 'X'
-- then '0' and '1'
-- then 'W'
-- then 'H' and 'L'
-- then 'Z'.
function resolved (s : std_ulogic_vector) return std_ulogic;
-- Resolved logic state.
subtype std_logic is resolved std_ulogic;
-- Vector of std_logic.
type std_logic_vector is array (natural range <>) of std_logic;
-- Subtypes of std_ulogic. The names give the values.
subtype X01 is resolved std_ulogic range 'X' to '1';
subtype X01Z is resolved std_ulogic range 'X' to 'Z';
subtype UX01 is resolved std_ulogic range 'U' to '1';
subtype UX01Z is resolved std_ulogic range 'U' to 'Z';
-- Logical operators.
-- For logical operations, the inputs are first normalized to UX01:
-- 0 and L are normalized to 0, 1 and 1 are normalized to 1, U isnt changed,
-- all other states are normalized to X.
-- Then the classical electric rules are followed.
function "and" (l : std_ulogic; r : std_ulogic) return UX01;
function "nand" (l : std_ulogic; r : std_ulogic) return UX01;
function "or" (l : std_ulogic; r : std_ulogic) return UX01;
function "nor" (l : std_ulogic; r : std_ulogic) return UX01;
function "xor" (l : std_ulogic; r : std_ulogic) return UX01;
function "xnor" (l : std_ulogic; r : std_ulogic) return UX01;
function "not" (l : std_ulogic) return UX01;
-- Logical operators for vectors.
-- An assertion of severity failure fails if the length of L and R aren't
-- equal. The result range is 1 to L'Length.
function "and" (l, r : std_logic_vector) return std_logic_vector;
function "nand" (l, r : std_logic_vector) return std_logic_vector;
function "or" (l, r : std_logic_vector) return std_logic_vector;
function "nor" (l, r : std_logic_vector) return std_logic_vector;
function "xor" (l, r : std_logic_vector) return std_logic_vector;
function "xnor" (l, r : std_logic_vector) return std_logic_vector;
function "not" (l : std_logic_vector) return std_logic_vector;
function "and" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nand" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "or" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "nor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "xnor" (l, r : std_ulogic_vector) return std_ulogic_vector;
function "not" (l : std_ulogic_vector) return std_ulogic_vector;
-- Conversion functions.
-- The result range (for vectors) is S'Length - 1 downto 0.
-- XMAP is return for values not in '0', '1', 'L', 'H'.
function to_bit (s : std_ulogic; xmap : bit := '0') return bit;
function to_bitvector (s : std_logic_vector; xmap : bit := '0')
return bit_vector;
function to_bitvector (s : std_ulogic_vector; xmap : bit := '0')
return bit_vector;
function to_stdulogic (b : bit) return std_ulogic;
function to_stdlogicvector (b : bit_vector) return std_logic_vector;
function to_stdlogicvector (s : std_ulogic_vector) return std_logic_vector;
function to_stdulogicvector (b : bit_vector) return std_ulogic_vector;
function to_stdulogicvector (s : std_logic_vector) return std_ulogic_vector;
-- Normalization.
-- The result range (for vectors) is 1 to S'Length.
function to_X01 (s : std_logic_vector) return std_logic_vector;
function to_X01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01 (s : std_ulogic) return X01;
function to_X01 (b : bit_vector) return std_logic_vector;
function to_X01 (b : bit_vector) return std_ulogic_vector;
function to_X01 (b : bit) return X01;
function to_X01Z (s : std_logic_vector) return std_logic_vector;
function to_X01Z (s : std_ulogic_vector) return std_ulogic_vector;
function to_X01Z (s : std_ulogic) return X01Z;
function to_X01Z (b : bit_vector) return std_logic_vector;
function to_X01Z (b : bit_vector) return std_ulogic_vector;
function to_X01Z (b : bit) return X01Z;
function to_UX01 (s : std_logic_vector) return std_logic_vector;
function to_UX01 (s : std_ulogic_vector) return std_ulogic_vector;
function to_UX01 (s : std_ulogic) return UX01;
function to_UX01 (b : bit_vector) return std_logic_vector;
function to_UX01 (b : bit_vector) return std_ulogic_vector;
function to_UX01 (b : bit) return UX01;
-- Edge detection.
-- An edge is detected in case of event on s, and X01 normalized value
-- rises from 0 to 1 or falls from 1 to 0.
function rising_edge (signal s : std_ulogic) return boolean;
function falling_edge (signal s : std_ulogic) return boolean;
-- Test for unknown. Only 0, 1, L and H are known values.
function is_X (s : std_ulogic_vector) return boolean;
function is_X (s : std_logic_vector) return boolean;
function is_X (s : std_ulogic) return boolean;
end std_logic_1164;
|
-------------------------------------------------------------------------------
-- xps_timer_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
library UNISIM;
use UNISIM.VCOMPONENTS.ALL;
library xps_timer_v1_01_b;
use xps_timer_v1_01_b.all;
entity xps_timer_0_wrapper is
port (
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to 31);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to 0);
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to 15);
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to 127);
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to 127);
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to 0);
Sl_MWrErr : out std_logic_vector(0 to 0);
Sl_MRdErr : out std_logic_vector(0 to 0);
PLB_UABus : in std_logic_vector(0 to 31);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to 0)
);
attribute x_core_info : STRING;
attribute x_core_info of xps_timer_0_wrapper : entity is "xps_timer_v1_01_b";
end xps_timer_0_wrapper;
architecture STRUCTURE of xps_timer_0_wrapper is
component xps_timer is
generic (
C_FAMILY : STRING;
C_COUNT_WIDTH : INTEGER;
C_ONE_TIMER_ONLY : INTEGER;
C_TRIG0_ASSERT : std_logic;
C_TRIG1_ASSERT : std_logic;
C_GEN0_ASSERT : std_logic;
C_GEN1_ASSERT : std_logic;
C_BASEADDR : std_logic_vector;
C_HIGHADDR : std_logic_vector;
C_SPLB_AWIDTH : INTEGER;
C_SPLB_DWIDTH : INTEGER;
C_SPLB_P2P : INTEGER;
C_SPLB_MID_WIDTH : INTEGER;
C_SPLB_NUM_MASTERS : INTEGER;
C_SPLB_SUPPORT_BURSTS : INTEGER;
C_SPLB_NATIVE_DWIDTH : INTEGER
);
port (
CaptureTrig0 : in std_logic;
CaptureTrig1 : in std_logic;
GenerateOut0 : out std_logic;
GenerateOut1 : out std_logic;
PWM0 : out std_logic;
Interrupt : out std_logic;
Freeze : in std_logic;
SPLB_Clk : in std_logic;
SPLB_Rst : in std_logic;
PLB_ABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_PAValid : in std_logic;
PLB_masterID : in std_logic_vector(0 to (C_SPLB_MID_WIDTH-1));
PLB_RNW : in std_logic;
PLB_BE : in std_logic_vector(0 to ((C_SPLB_DWIDTH/8)-1));
PLB_size : in std_logic_vector(0 to 3);
PLB_type : in std_logic_vector(0 to 2);
PLB_wrDBus : in std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_addrAck : out std_logic;
Sl_SSize : out std_logic_vector(0 to 1);
Sl_wait : out std_logic;
Sl_rearbitrate : out std_logic;
Sl_wrDAck : out std_logic;
Sl_wrComp : out std_logic;
Sl_rdDBus : out std_logic_vector(0 to (C_SPLB_DWIDTH-1));
Sl_rdDAck : out std_logic;
Sl_rdComp : out std_logic;
Sl_MBusy : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MWrErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
Sl_MRdErr : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1));
PLB_UABus : in std_logic_vector(0 to C_SPLB_AWIDTH-1);
PLB_SAValid : in std_logic;
PLB_rdPrim : in std_logic;
PLB_wrPrim : in std_logic;
PLB_abort : in std_logic;
PLB_busLock : in std_logic;
PLB_MSize : in std_logic_vector(0 to 1);
PLB_lockErr : in std_logic;
PLB_wrBurst : in std_logic;
PLB_rdBurst : in std_logic;
PLB_wrPendReq : in std_logic;
PLB_rdPendReq : in std_logic;
PLB_wrPendPri : in std_logic_vector(0 to 1);
PLB_rdPendPri : in std_logic_vector(0 to 1);
PLB_reqPri : in std_logic_vector(0 to 1);
PLB_TAttribute : in std_logic_vector(0 to 15);
Sl_wrBTerm : out std_logic;
Sl_rdWdAddr : out std_logic_vector(0 to 3);
Sl_rdBTerm : out std_logic;
Sl_MIRQ : out std_logic_vector(0 to (C_SPLB_NUM_MASTERS-1))
);
end component;
begin
xps_timer_0 : xps_timer
generic map (
C_FAMILY => "virtex5",
C_COUNT_WIDTH => 32,
C_ONE_TIMER_ONLY => 0,
C_TRIG0_ASSERT => '1',
C_TRIG1_ASSERT => '1',
C_GEN0_ASSERT => '1',
C_GEN1_ASSERT => '1',
C_BASEADDR => X"83c00000",
C_HIGHADDR => X"83c0ffff",
C_SPLB_AWIDTH => 32,
C_SPLB_DWIDTH => 128,
C_SPLB_P2P => 0,
C_SPLB_MID_WIDTH => 1,
C_SPLB_NUM_MASTERS => 1,
C_SPLB_SUPPORT_BURSTS => 0,
C_SPLB_NATIVE_DWIDTH => 32
)
port map (
CaptureTrig0 => CaptureTrig0,
CaptureTrig1 => CaptureTrig1,
GenerateOut0 => GenerateOut0,
GenerateOut1 => GenerateOut1,
PWM0 => PWM0,
Interrupt => Interrupt,
Freeze => Freeze,
SPLB_Clk => SPLB_Clk,
SPLB_Rst => SPLB_Rst,
PLB_ABus => PLB_ABus,
PLB_PAValid => PLB_PAValid,
PLB_masterID => PLB_masterID,
PLB_RNW => PLB_RNW,
PLB_BE => PLB_BE,
PLB_size => PLB_size,
PLB_type => PLB_type,
PLB_wrDBus => PLB_wrDBus,
Sl_addrAck => Sl_addrAck,
Sl_SSize => Sl_SSize,
Sl_wait => Sl_wait,
Sl_rearbitrate => Sl_rearbitrate,
Sl_wrDAck => Sl_wrDAck,
Sl_wrComp => Sl_wrComp,
Sl_rdDBus => Sl_rdDBus,
Sl_rdDAck => Sl_rdDAck,
Sl_rdComp => Sl_rdComp,
Sl_MBusy => Sl_MBusy,
Sl_MWrErr => Sl_MWrErr,
Sl_MRdErr => Sl_MRdErr,
PLB_UABus => PLB_UABus,
PLB_SAValid => PLB_SAValid,
PLB_rdPrim => PLB_rdPrim,
PLB_wrPrim => PLB_wrPrim,
PLB_abort => PLB_abort,
PLB_busLock => PLB_busLock,
PLB_MSize => PLB_MSize,
PLB_lockErr => PLB_lockErr,
PLB_wrBurst => PLB_wrBurst,
PLB_rdBurst => PLB_rdBurst,
PLB_wrPendReq => PLB_wrPendReq,
PLB_rdPendReq => PLB_rdPendReq,
PLB_wrPendPri => PLB_wrPendPri,
PLB_rdPendPri => PLB_rdPendPri,
PLB_reqPri => PLB_reqPri,
PLB_TAttribute => PLB_TAttribute,
Sl_wrBTerm => Sl_wrBTerm,
Sl_rdWdAddr => Sl_rdWdAddr,
Sl_rdBTerm => Sl_rdBTerm,
Sl_MIRQ => Sl_MIRQ
);
end architecture STRUCTURE;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc156.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p17n01i00156ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p17n01i00156ent;
ARCHITECTURE c04s03b02x02p17n01i00156arch OF c04s03b02x02p17n01i00156ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>conv1(a2),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
assert FALSE
report "***FAILED TEST: c04s03b02x02p17n01i00156 - Type coversion return wrong type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p17n01i00156arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc156.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p17n01i00156ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p17n01i00156ent;
ARCHITECTURE c04s03b02x02p17n01i00156arch OF c04s03b02x02p17n01i00156ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>conv1(a2),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
assert FALSE
report "***FAILED TEST: c04s03b02x02p17n01i00156 - Type coversion return wrong type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p17n01i00156arch;
|
-- Copyright (C) 2001 Bill Billowitch.
-- Some of the work to develop this test suite was done with Air Force
-- support. The Air Force and Bill Billowitch assume no
-- responsibilities for this software.
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-- ---------------------------------------------------------------------
--
-- $Id: tc156.vhd,v 1.2 2001-10-26 16:30:11 paw Exp $
-- $Revision: 1.2 $
--
-- ---------------------------------------------------------------------
ENTITY c04s03b02x02p17n01i00156ent IS
PORT ( ii: INOUT integer);
PROCEDURE addup (i1,i2,i3:IN INTEGER;add:IN BOOLEAN;VARIABLE i4:OUT INTEGER) IS
BEGIN
IF add THEN
i4 := (i1+i2+i3);
ELSE
i4 := (i1-i2)-i3;
END IF;
END;
END c04s03b02x02p17n01i00156ent;
ARCHITECTURE c04s03b02x02p17n01i00156arch OF c04s03b02x02p17n01i00156ent IS
BEGIN
TESTING: PROCESS
VARIABLE a1 : INTEGER := 57;
VARIABLE a2 : INTEGER := 68;
VARIABLE a3 : INTEGER := 77;
VARIABLE b1 : BIT := '1';
VARIABLE b2 : BIT := '0';
FUNCTION convb (inp:IN INTEGER) RETURN BOOLEAN IS
BEGIN
IF (inp > 0) THEN
RETURN (TRUE);
ELSE
RETURN (FALSE);
END IF;
END;
FUNCTION conv1 (inp:IN BIT) RETURN INTEGER IS
BEGIN
IF (inp = '1') THEN
RETURN (22);
ELSE
RETURN (23);
END IF;
END;
BEGIN
WAIT FOR 1 ns;
addup(i2=>conv1(b1),add=>conv1(a2),i1=>conv1(b2),i3=>a1,i4=>a1);
WAIT FOR 1 ns;
assert FALSE
report "***FAILED TEST: c04s03b02x02p17n01i00156 - Type coversion return wrong type."
severity ERROR;
wait;
END PROCESS TESTING;
END c04s03b02x02p17n01i00156arch;
|
-----------------------------------------------------------------------------------------
-- --
-- This file is part of the CAPH Compiler distribution --
-- http://caph.univ-bpclermont.fr --
-- --
-- Jocelyn SEROT --
-- [email protected] --
-- --
-- Copyright 2011-2015 Jocelyn SEROT. All rights reserved. --
-- This file is distributed under the terms of the GNU Library General Public License --
-- with the special exception on linking described in file ../LICENSE. --
-- --
-----------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.ALL;
-- +-----------+
-- | | d1_f
-- | |<--------
-- | | d1
-- d_f | |-------->
-- <--------| | d1_wr
-- d | |-------->
-- -------->| SPLIT |
-- d_wr | | d2_f
-- -------->| |<--------
-- | | d2
-- | |-------->
-- | | d2_wr
-- | |-------->
-- +-----------+
entity split2 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic
);
end split2;
architecture arch of split2 is
begin
d1 <= d;
d2 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d_f <= d1_f or d2_f;
end arch;
library ieee;
use ieee.std_logic_1164.ALL;
entity split3 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic;
d3_f : in std_logic;
d3 : out std_logic_vector(size-1 downto 0);
d3_wr : out std_logic
);
end split3;
architecture arch of split3 is
begin
d1 <= d;
d2 <= d;
d3 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d3_wr <= d_wr;
d_f <= d1_f or d2_f or d3_f;
end arch;
library ieee;
use ieee.std_logic_1164.ALL;
entity split4 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic;
d3_f : in std_logic;
d3 : out std_logic_vector(size-1 downto 0);
d3_wr : out std_logic;
d4_f : in std_logic;
d4 : out std_logic_vector(size-1 downto 0);
d4_wr : out std_logic
);
end split4;
architecture arch of split4 is
begin
d1 <= d;
d2 <= d;
d3 <= d;
d4 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d3_wr <= d_wr;
d4_wr <= d_wr;
d_f <= d1_f or d2_f or d3_f or d4_f;
end arch;
library ieee;
use ieee.std_logic_1164.ALL;
entity split5 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic;
d3_f : in std_logic;
d3 : out std_logic_vector(size-1 downto 0);
d3_wr : out std_logic;
d4_f : in std_logic;
d4 : out std_logic_vector(size-1 downto 0);
d4_wr : out std_logic;
d5_f : in std_logic;
d5 : out std_logic_vector(size-1 downto 0);
d5_wr : out std_logic
);
end split5;
architecture arch of split5 is
begin
d1 <= d;
d2 <= d;
d3 <= d;
d4 <= d;
d5 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d3_wr <= d_wr;
d4_wr <= d_wr;
d5_wr <= d_wr;
d_f <= d1_f or d2_f or d3_f or d4_f or d5_f;
end arch;
library ieee;
use ieee.std_logic_1164.ALL;
entity split6 is
generic ( size: integer := 10);
port (
d_f: out std_logic;
d : in std_logic_vector (size-1 downto 0);
d_wr : in std_logic;
d1_f : in std_logic;
d1 : out std_logic_vector(size-1 downto 0);
d1_wr : out std_logic;
d2_f : in std_logic;
d2 : out std_logic_vector(size-1 downto 0);
d2_wr : out std_logic;
d3_f : in std_logic;
d3 : out std_logic_vector(size-1 downto 0);
d3_wr : out std_logic;
d4_f : in std_logic;
d4 : out std_logic_vector(size-1 downto 0);
d4_wr : out std_logic;
d5_f : in std_logic;
d5 : out std_logic_vector(size-1 downto 0);
d5_wr : out std_logic;
d6_f : in std_logic;
d6 : out std_logic_vector(size-1 downto 0);
d6_wr : out std_logic
);
end split6;
architecture arch of split6 is
begin
d1 <= d;
d2 <= d;
d3 <= d;
d4 <= d;
d5 <= d;
d6 <= d;
d1_wr <= d_wr;
d2_wr <= d_wr;
d3_wr <= d_wr;
d4_wr <= d_wr;
d5_wr <= d_wr;
d6_wr <= d_wr;
d_f <= d1_f or d2_f or d3_f or d4_f or d5_f or d6_f;
end arch;
|
-- $Id: serport_1clock.vhd 476 2013-01-26 22:23:53Z mueller $
--
-- Copyright 2011- by Walter F.J. Mueller <[email protected]>
--
-- This program is free software; you may redistribute and/or modify it under
-- the terms of the GNU General Public License as published by the Free
-- Software Foundation, either version 2, or at your option any later version.
--
-- This program is distributed in the hope that it will be useful, but
-- WITHOUT ANY WARRANTY, without even the implied warranty of MERCHANTABILITY
-- or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for complete details.
--
------------------------------------------------------------------------------
-- Module Name: serport_1clock - syn
-- Description: serial port: serial port module, 1 clock domain
--
-- Dependencies: serport_uart_rxtx_ab
-- serport_xonrx
-- serport_xontx
-- memlib/fifo_1c_dram
-- Test bench: -
-- Target Devices: generic
-- Tool versions: xst 13.1; ghdl 0.29
--
-- Synthesized (xst):
-- Date Rev ise Target flop lutl lutm slic t peri
-- 2011-11-13 424 13.1 O40d xc3s1000-4 157 337 64 232 s 9.9
--
-- Revision History:
-- Date Rev Version Comment
-- 2011-12-10 438 1.0.2 internal reset on abact
-- 2011-12-09 437 1.0.1 rename stat->moni port
-- 2011-11-13 424 1.0 Initial version
-- 2011-10-23 419 0.5 First draft
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.slvtypes.all;
use work.serportlib.all;
use work.memlib.all;
entity serport_1clock is -- serial port module, 1 clock domain
generic (
CDWIDTH : positive := 13; -- clk divider width
CDINIT : natural := 15; -- clk divider initial/reset setting
RXFAWIDTH : natural := 5; -- rx fifo address width
TXFAWIDTH : natural := 5); -- tx fifo address width
port (
CLK : in slbit; -- clock
CE_MSEC : in slbit; -- 1 msec clock enable
RESET : in slbit; -- reset
ENAXON : in slbit; -- enable xon/xoff handling
ENAESC : in slbit; -- enable xon/xoff escaping
RXDATA : out slv8; -- receiver data out
RXVAL : out slbit; -- receiver data valid
RXHOLD : in slbit; -- receiver data hold
TXDATA : in slv8; -- transmit data in
TXENA : in slbit; -- transmit data enable
TXBUSY : out slbit; -- transmit busy
MONI : out serport_moni_type; -- serport monitor port
RXSD : in slbit; -- receive serial data (uart view)
TXSD : out slbit; -- transmit serial data (uart view)
RXRTS_N : out slbit; -- receive rts (uart view, act.low)
TXCTS_N : in slbit -- transmit cts (uart view, act.low)
);
end serport_1clock;
architecture syn of serport_1clock is
signal R_RXOK : slbit := '1';
signal RESET_INT : slbit := '0';
signal UART_RXDATA : slv8 := (others=>'0');
signal UART_RXVAL : slbit := '0';
signal UART_TXDATA : slv8 := (others=>'0');
signal UART_TXENA : slbit := '0';
signal UART_TXBUSY : slbit := '0';
signal XONTX_TXENA : slbit := '0';
signal XONTX_TXBUSY : slbit := '0';
signal RXFIFO_DI : slv8 := (others=>'0');
signal RXFIFO_ENA : slbit := '0';
signal RXFIFO_BUSY : slbit := '0';
signal RXFIFO_SIZE : slv(RXFAWIDTH downto 0) := (others=>'0');
signal TXFIFO_DO : slv8 := (others=>'0');
signal TXFIFO_VAL : slbit := '0';
signal TXFIFO_HOLD : slbit := '0';
signal RXERR : slbit := '0';
signal RXOVR : slbit := '0';
signal RXACT : slbit := '0';
signal ABACT : slbit := '0';
signal ABDONE : slbit := '0';
signal ABCLKDIV : slv(CDWIDTH-1 downto 0) := (others=>'0');
signal TXOK : slbit := '0';
signal RXOK : slbit := '0';
begin
assert CDWIDTH<=16
report "assert(CDWIDTH<=16): max width of UART clock divider"
severity failure;
UART : serport_uart_rxtx_ab -- uart, rx+tx+autobauder combo
generic map (
CDWIDTH => CDWIDTH,
CDINIT => CDINIT)
port map (
CLK => CLK,
CE_MSEC => CE_MSEC,
RESET => RESET,
RXSD => RXSD,
RXDATA => UART_RXDATA,
RXVAL => UART_RXVAL,
RXERR => RXERR,
RXACT => RXACT,
TXSD => TXSD,
TXDATA => UART_TXDATA,
TXENA => UART_TXENA,
TXBUSY => UART_TXBUSY,
ABACT => ABACT,
ABDONE => ABDONE,
ABCLKDIV => ABCLKDIV
);
RESET_INT <= RESET or ABACT;
XONRX : serport_xonrx -- xon/xoff logic rx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_RXDATA => UART_RXDATA,
UART_RXVAL => UART_RXVAL,
RXDATA => RXFIFO_DI,
RXVAL => RXFIFO_ENA,
RXHOLD => RXFIFO_BUSY,
RXOVR => RXOVR,
TXOK => TXOK
);
XONTX : serport_xontx -- xon/xoff logic tx path
port map (
CLK => CLK,
RESET => RESET_INT,
ENAXON => ENAXON,
ENAESC => ENAESC,
UART_TXDATA => UART_TXDATA,
UART_TXENA => XONTX_TXENA,
UART_TXBUSY => XONTX_TXBUSY,
TXDATA => TXFIFO_DO,
TXENA => TXFIFO_VAL,
TXBUSY => TXFIFO_HOLD,
RXOK => RXOK,
TXOK => TXOK
);
RXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => RXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => RXFIFO_DI,
ENA => RXFIFO_ENA,
BUSY => RXFIFO_BUSY,
DO => RXDATA,
VAL => RXVAL,
HOLD => RXHOLD,
SIZE => RXFIFO_SIZE
);
TXFIFO : fifo_1c_dram -- input fifo, 1 clock, dram based
generic map (
AWIDTH => TXFAWIDTH,
DWIDTH => 8)
port map (
CLK => CLK,
RESET => RESET_INT,
DI => TXDATA,
ENA => TXENA,
BUSY => TXBUSY,
DO => TXFIFO_DO,
VAL => TXFIFO_VAL,
HOLD => TXFIFO_HOLD,
SIZE => open
);
-- receive back preasure
-- on if fifo more than 3/4 full
-- off if fifo less than 1/2 full
proc_rxok: process (CLK)
constant rxsize_rxok_off : slv3 := "011";
constant rxsize_rxok_on : slv3 := "010";
variable rxsize_msb : slv3 := "000";
begin
if rising_edge(CLK) then
if RESET_INT = '1' then
R_RXOK <= '1';
else
rxsize_msb := RXFIFO_SIZE(RXFAWIDTH downto RXFAWIDTH-2);
if unsigned(rxsize_msb) >= unsigned(rxsize_rxok_off) then
R_RXOK <= '0';
elsif unsigned(rxsize_msb) <= unsigned(rxsize_rxok_on) then
R_RXOK <= '1';
end if;
end if;
end if;
end process proc_rxok;
RXOK <= R_RXOK;
RXRTS_N <= not R_RXOK;
proc_cts: process (TXCTS_N, XONTX_TXENA, UART_TXBUSY)
begin
if TXCTS_N = '0' then -- transmit cts asserted
UART_TXENA <= XONTX_TXENA;
XONTX_TXBUSY <= UART_TXBUSY;
else -- transmit cts not asserted
UART_TXENA <= '0';
XONTX_TXBUSY <= '1';
end if;
end process proc_cts;
MONI.rxerr <= RXERR;
MONI.rxovr <= RXOVR;
MONI.rxact <= RXACT;
MONI.txact <= UART_TXBUSY;
MONI.abact <= ABACT;
MONI.abdone <= ABDONE;
MONI.rxok <= RXOK;
MONI.txok <= TXOK;
proc_abclkdiv: process (ABCLKDIV)
begin
MONI.abclkdiv <= (others=>'0');
MONI.abclkdiv(ABCLKDIV'range) <= ABCLKDIV;
end process proc_abclkdiv;
end syn;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_unsigned.all;
USE ieee.std_logic_arith.all;
--***************************************************
--*** ***
--*** FLOATING POINT CORE LIBRARY ***
--*** ***
--*** FP_FXSUB.VHD ***
--*** ***
--*** Function: Generic Fixed Point Subtractor ***
--*** ***
--*** 31/01/08 ML ***
--*** ***
--*** (c) 2008 Altera Corporation ***
--*** ***
--*** Change History ***
--*** ***
--*** ***
--*** ***
--*** ***
--*** ***
--***************************************************
ENTITY dp_fxsub IS
GENERIC (
width : positive := 64;
pipes : positive := 1;
synthesize : integer := 0
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
END dp_fxsub;
ARCHITECTURE rtl OF dp_fxsub IS
component dp_subb IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
component dp_subs IS
GENERIC (
width : positive := 64;
pipes : positive := 1
);
PORT (
sysclk : IN STD_LOGIC;
reset : IN STD_LOGIC;
enable : IN STD_LOGIC;
aa, bb : IN STD_LOGIC_VECTOR (width DOWNTO 1);
borrowin : IN STD_LOGIC;
cc : OUT STD_LOGIC_VECTOR (width DOWNTO 1)
);
end component;
BEGIN
gaa: IF (synthesize = 0) GENERATE
addone: dp_subb
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
gab: IF (synthesize = 1) GENERATE
addtwo: dp_subs
GENERIC MAP (width=>width,pipes=>pipes)
PORT MAP (sysclk=>sysclk,reset=>reset,enable=>enable,
aa=>aa,bb=>bb,borrowin=>borrowin,
cc=>cc);
END GENERATE;
END rtl;
|
-- $Id: sys_conf.vhd 1181 2019-07-08 17:00:50Z mueller $
-- SPDX-License-Identifier: GPL-3.0-or-later
-- Copyright 2015- by Walter F.J. Mueller <[email protected]>
--
------------------------------------------------------------------------------
-- Package Name: sys_conf
-- Description: Definitions for sys_tst_snhumanio_n4 (for synthesis)
--
-- Dependencies: -
-- Tool versions: viv 2014.4; ghdl 0.31
-- Revision History:
-- Date Rev Version Comment
-- 2015-01-31 640 1.0 Initial version
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use work.slvtypes.all;
package sys_conf is
constant sys_conf_hio_debounce : boolean := true; -- instantiate debouncers
end package sys_conf;
|
-----------------------------------------------------------------------------
-- LEON3/LEON4 Demonstration design
------------------------------------------------------------------------------
-- This file is a part of the GRLIB VHDL IP LIBRARY
-- Copyright (C) 2003 - 2008, Gaisler Research
-- Copyright (C) 2008 - 2014, Aeroflex Gaisler
-- Copyright (C) 2015 - 2016, Cobham Gaisler
--
-- This program is free software; you can redistribute it and/or modify
-- it under the terms of the GNU General Public License as published by
-- the Free Software Foundation; either version 2 of the License, or
-- (at your option) any later version.
--
-- This program is distributed in the hope that it will be useful,
-- but WITHOUT ANY WARRANTY; without even the implied warranty of
-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-- GNU General Public License for more details.
--
-- You should have received a copy of the GNU General Public License
-- along with this program; if not, write to the Free Software
-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
library grlib, techmap;
use grlib.amba.all;
use grlib.stdlib.all;
use grlib.devices.all;
use techmap.gencomp.all;
use techmap.allclkgen.all;
library gaisler;
use gaisler.memctrl.all;
use gaisler.leon3.all;
use gaisler.uart.all;
use gaisler.misc.all;
use gaisler.spi.all;
use gaisler.i2c.all;
use gaisler.net.all;
use gaisler.jtag.all;
use gaisler.pci.all;
use gaisler.ddrpkg.all;
use gaisler.l2cache.all;
use gaisler.subsys.all;
library esa;
use esa.memoryctrl.all;
use esa.pcicomp.all;
use work.config.all;
-- pragma translate_off
library unisim;
use unisim.BUFG;
use unisim.IBUFDS;
-- pragma translate_on
-- pragma translate_on
entity leon3mp is
generic (
fabtech : integer := CFG_FABTECH;
memtech : integer := CFG_MEMTECH;
padtech : integer := CFG_PADTECH;
transtech : integer := CFG_TRANSTECH;
ncpu : integer := CFG_NCPU;
disas : integer := CFG_DISAS; -- Enable disassembly to console
dbguart : integer := CFG_DUART; -- Print UART on console
pclow : integer := CFG_PCLOW
);
port (
fpga_cpu_reset_b : in std_ulogic;
user_clksys : in std_ulogic; -- 100 MHz main clock
sysace_fpga_clk : in std_ulogic; -- 33 MHz
-- Flash
flash_we_b : out std_ulogic;
flash_wait : in std_ulogic;
flash_reset_b : out std_ulogic;
flash_oe_b : out std_ulogic;
flash_d : inout std_logic_vector(15 downto 0);
flash_clk : out std_ulogic;
flash_ce_b : out std_ulogic;
flash_adv_b : out std_logic;
flash_a : out std_logic_vector(21 downto 0);
--pragma translate_off
-- For debug output module
sram_bw : out std_ulogic;
sim_d : inout std_logic_vector(31 downto 16);
iosn : out std_ulogic;
--pragma translate_on
-- DDR2 slot 1
dimm1_ddr2_we_b : out std_ulogic;
dimm1_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm1_ddr2_ras_b : out std_ulogic;
dimm1_ddr2_pll_clkin_p : out std_ulogic;
dimm1_ddr2_pll_clkin_n : out std_ulogic;
dimm1_ddr2_odt : out std_logic_vector(1 downto 0);
dimm1_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm1_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm1_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm1_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm1_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm1_ddr2_cas_b : out std_ulogic;
dimm1_ddr2_ba : out std_logic_vector(2 downto 0);
dimm1_ddr2_a : out std_logic_vector(13 downto 0);
-- DDR2 slot 0
dimm0_ddr2_we_b : out std_ulogic;
dimm0_ddr2_s_b : out std_logic_vector(1 downto 0);
dimm0_ddr2_ras_b : out std_ulogic;
dimm0_ddr2_pll_clkin_p : out std_ulogic;
dimm0_ddr2_pll_clkin_n : out std_ulogic;
dimm0_ddr2_odt : out std_logic_vector(1 downto 0);
dimm0_ddr2_dqs_p : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqs_n : inout std_logic_vector(8 downto 0);
dimm0_ddr2_dqm : out std_logic_vector(8 downto 0);
dimm0_ddr2_dq : inout std_logic_vector(71 downto 0);
dimm0_ddr2_cke : out std_logic_vector(1 downto 0);
-- dimm0_ddr2_cb : inout std_logic_vector(7 downto 0);
dimm0_ddr2_cas_b : out std_ulogic;
dimm0_ddr2_ba : out std_logic_vector(2 downto 0);
dimm0_ddr2_a : out std_logic_vector(13 downto 0);
dimm0_ddr2_reset_n : out std_ulogic;
-- Ethernet PHY0
phy0_txer : out std_ulogic;
phy0_txd : out std_logic_vector(3 downto 0);
phy0_txctl_txen : out std_ulogic;
phy0_txclk : in std_ulogic;
phy0_rxer : in std_ulogic;
phy0_rxd : in std_logic_vector(3 downto 0);
phy0_rxctl_rxdv : in std_ulogic;
phy0_rxclk : in std_ulogic;
phy0_reset : out std_ulogic;
phy0_mdio : inout std_logic;
phy0_mdc : out std_ulogic;
-- phy0_int : in std_ulogic;
-- Ethernet PHY1 SGMII
sgmiiclk_qo_p : in std_logic;
sgmiiclk_qo_n : in std_logic;
phy1_reset : out std_logic;
phy1_mdio : inout std_logic;
phy1_mdc : out std_logic;
phy1_int : out std_logic;
phy1_sgmii_tx_p : out std_logic;
phy1_sgmii_tx_n : out std_logic;
phy1_sgmii_rx_p : in std_logic;
phy1_sgmii_rx_n : in std_logic;
-- System ACE MPU
sysace_mpa : out std_logic_vector(6 downto 0);
sysace_mpce : out std_ulogic;
sysace_mpirq : in std_ulogic;
sysace_mpoe : out std_ulogic;
sysace_mpwe : out std_ulogic;
sysace_mpd : inout std_logic_vector(15 downto 0);
-- GPIO/Green LEDs
dbg_led : inout std_logic_vector(3 downto 0);
-- Red/Green LEDs
opb_bus_error : out std_ulogic;
plb_bus_error : out std_ulogic;
-- LCD
-- fpga_lcd_rw : out std_ulogic;
-- fpga_lcd_rs : out std_ulogic;
-- fpga_lcd_e : out std_ulogic;
-- fpga_lcd_db : out std_logic_vector(7 downto 0);
-- DVI
dvi_xclk_p : out std_ulogic;
dvi_xclk_n : out std_ulogic;
dvi_v : out std_ulogic;
dvi_reset_b : out std_ulogic;
dvi_h : out std_ulogic;
dvi_gpio1 : inout std_logic;
dvi_de : out std_ulogic;
dvi_d : out std_logic_vector(11 downto 0);
-- PCI
pci_p_trdy_b : inout std_logic;
pci_p_stop_b : inout std_logic;
pci_p_serr_b : inout std_logic;
pci_p_rst_b : inout std_logic;
pci_p_req_b : in std_logic_vector(0 to 4);
pci_p_perr_b : inout std_logic;
pci_p_par : inout std_logic;
pci_p_lock_b : inout std_logic;
pci_p_irdy_b : inout std_logic;
pci_p_intd_b : in std_logic;
pci_p_intc_b : in std_logic;
pci_p_intb_b : in std_logic;
pci_p_inta_b : in std_logic;
pci_p_gnt_b : out std_logic_vector(0 to 4);
pci_p_frame_b : inout std_logic;
pci_p_devsel_b : inout std_logic;
pci_p_clk5_r : out std_ulogic;
pci_p_clk5 : in std_ulogic;
pci_p_clk4_r : out std_ulogic;
pci_p_clk3_r : out std_ulogic;
pci_p_clk1_r : out std_ulogic;
pci_p_clk0_r : out std_ulogic;
pci_p_cbe_b : inout std_logic_vector(3 downto 0);
pci_p_ad : inout std_logic_vector(31 downto 0);
-- pci_fpga_idsel : in std_ulogic;
sbr_pwg_rsm_rstj : inout std_logic;
sbr_nmi_r : in std_ulogic;
sbr_intr_r : in std_ulogic;
sbr_ide_rst_b : inout std_logic;
-- IIC/SMBus and sideband signals
iic_sda_dvi : inout std_logic;
iic_scl_dvi : inout std_logic;
fpga_sda : inout std_logic;
fpga_scl : inout std_logic;
iic_therm_b : in std_ulogic;
iic_reset_b : out std_ulogic;
iic_irq_b : in std_ulogic;
iic_alert_b : in std_ulogic;
-- SPI
spi_data_out : in std_logic;
spi_data_in : out std_ulogic;
spi_data_cs_b : out std_ulogic;
spi_clk : out std_ulogic;
-- UARTs
uart1_txd : out std_ulogic;
uart1_rxd : in std_ulogic;
uart1_rts_b : out std_ulogic;
uart1_cts_b : in std_ulogic;
uart0_txd : out std_ulogic;
uart0_rxd : in std_ulogic;
uart0_rts_b : out std_ulogic
-- uart0_cts_b : in std_ulogic
-- System monitor
-- test_mon_vrefp : in std_ulogic;
-- test_mon_vp0_p : in std_ulogic;
-- test_mon_vn0_n : in std_ulogic
-- test_mon_avdd : in std_ulogic
);
end;
architecture rtl of leon3mp is
component svga2ch7301c
generic (
tech : integer := 0;
idf : integer := 0;
dynamic : integer := 0
);
port (
clk : in std_ulogic;
rstn : in std_ulogic;
clksel : in std_logic_vector(1 downto 0);
vgao : in apbvga_out_type;
vgaclk_fb : in std_ulogic;
clk25_fb : in std_ulogic;
clk40_fb : in std_ulogic;
clk65_fb : in std_ulogic;
vgaclk : out std_ulogic;
clk25 : out std_ulogic;
clk40 : out std_ulogic;
clk65 : out std_ulogic;
dclk_p : out std_ulogic;
dclk_n : out std_ulogic;
locked : out std_ulogic;
data : out std_logic_vector(11 downto 0);
hsync : out std_ulogic;
vsync : out std_ulogic;
de : out std_ulogic
);
end component;
component BUFG port (O : out std_logic; I : in std_logic); end component;
component IBUFDS
generic ( CAPACITANCE : string := "DONT_CARE";
DIFF_TERM : boolean := FALSE; IBUF_DELAY_VALUE : string := "0";
IFD_DELAY_VALUE : string := "AUTO"; IOSTANDARD : string := "DEFAULT");
port ( O : out std_ulogic; I : in std_ulogic; IB : in std_ulogic);
end component;
constant blength : integer := 12;
constant fifodepth : integer := 8;
constant maxahbm : integer := NCPU+CFG_AHB_UART+CFG_AHB_JTAG+
CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+CFG_GRPCI2_TARGET+CFG_GRPCI2_DMA;
signal ddr0_clk_fb, ddr1_clk_fb : std_logic;
signal vcc, gnd : std_logic_vector(31 downto 0);
signal memi : memory_in_type;
signal memo : memory_out_type;
signal wpo : wprot_out_type;
signal apbi, apb1i : apb_slv_in_type;
signal apbo, apb1o : apb_slv_out_vector := (others => apb_none);
signal ahbsi : ahb_slv_in_type;
signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal ahbmi : ahb_mst_in_type;
signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal ddr2spa_ahbsi : ahb_slv_in_type;
signal ddr2spa_ahbso : ahb_slv_out_vector_type(1 downto 0);
signal clkm, clkm2x, rstn, rstraw, flashclkl : std_ulogic;
signal clkddr, clk_200 : std_ulogic;
signal clk25, clk40, clk65 : std_ulogic;
signal cgi, cgi2, cgi3 : clkgen_in_type;
signal cgo, cgo2, cgo3 : clkgen_out_type;
signal u1i, dui : uart_in_type;
signal u1o, duo : uart_out_type;
signal irqi : irq_in_vector(0 to NCPU-1);
signal irqo : irq_out_vector(0 to NCPU-1);
signal sysi : leon_dsu_stat_base_in_type;
signal syso : leon_dsu_stat_base_out_type;
signal perf : l3stat_in_type;
signal ethi, ethi1, ethi2 : eth_in_type;
signal etho, etho1, etho2 : eth_out_type;
signal gpti : gptimer_in_type;
signal gpioi : gpio_in_type;
signal gpioo : gpio_out_type;
signal clklock, lock0, lock1, lclk, clkml0, clkml1 : std_ulogic;
signal tck, tckn, tms, tdi, tdo : std_ulogic;
signal rst : std_ulogic;
signal egtx_clk_fb : std_ulogic;
signal egtx_clk, legtx_clk, l2egtx_clk : std_ulogic;
signal sgmii_refclk, sgmii_rst: std_logic;
signal mdio_reset, mdio_o, mdio_oe, mdio_i, mdc, mdint : std_logic;
signal vgao : apbvga_out_type;
signal lcd_datal : std_logic_vector(11 downto 0);
signal lcd_hsyncl, lcd_vsyncl, lcd_del, lcd_reset_bl : std_ulogic;
signal clk_sel : std_logic_vector(1 downto 0);
signal vgalock : std_ulogic;
signal clkvga, clkvga_p, clkvga_n : std_ulogic;
signal i2ci, dvi_i2ci : i2c_in_type;
signal i2co, dvi_i2co : i2c_out_type;
signal spii : spi_in_type;
signal spio : spi_out_type;
signal slvsel : std_logic_vector(CFG_SPICTRL_SLVS-1 downto 0);
constant BOARD_FREQ_200 : integer := 200000; -- input frequency in KHz
constant BOARD_FREQ : integer := 100000; -- input frequency in KHz
constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
constant I2C_FILTER : integer := (CPU_FREQ*5+50000)/100000+1;
-- DDR clock is 200 MHz clock unless CFG_DDR2SP_NOSYNC is set. If that config
-- option is set the DDR clock is 2x CPU clock.
constant DDR_FREQ : integer :=
BOARD_FREQ_200 - (BOARD_FREQ_200 - 2*CPU_FREQ)*CFG_DDR2SP_NOSYNC;
constant IOAEN : integer := CFG_DDR2SP+CFG_GRACECTRL;
signal stati : ahbstat_in_type;
signal ddr0_clkv : std_logic_vector(2 downto 0);
signal ddr0_clkbv : std_logic_vector(2 downto 0);
signal ddr1_clkv : std_logic_vector(2 downto 0);
signal ddr1_clkbv : std_logic_vector(2 downto 0);
signal clkace : std_ulogic;
signal acei : gracectrl_in_type;
signal aceo : gracectrl_out_type;
signal sysmoni : grsysmon_in_type;
signal sysmono : grsysmon_out_type;
signal pciclk, pci_clk, pci_clk_fb : std_ulogic;
signal pci_arb_gnt : std_logic_vector(0 to 7);
signal pci_arb_req : std_logic_vector(0 to 7);
signal pci_arb_reql : std_logic_vector(0 to 4);
signal pci_reql : std_ulogic;
signal pci_host, pci_66 : std_ulogic;
signal pci_intv : std_logic_vector(3 downto 0);
signal pcii : pci_in_type;
signal pcio : pci_out_type;
signal pci_dirq : std_logic_vector(3 downto 0);
signal clkma, clkmb, clkmc : std_ulogic;
signal clk0_tb, rst0_tb, rst0_tbn : std_ulogic;
signal phy_init_done : std_ulogic;
attribute syn_keep : boolean;
attribute syn_preserve : boolean;
attribute syn_keep of clkml0 : signal is true;
attribute syn_preserve of clkml0 : signal is true;
attribute syn_keep of clkml1 : signal is true;
attribute syn_preserve of clkml1 : signal is true;
attribute syn_keep of clkm : signal is true;
attribute syn_preserve of clkm : signal is true;
attribute syn_keep of egtx_clk : signal is true;
attribute syn_preserve of egtx_clk : signal is true;
attribute syn_keep of clkvga : signal is true;
attribute syn_preserve of clkvga : signal is true;
attribute syn_keep of clk25 : signal is true;
attribute syn_preserve of clk25 : signal is true;
attribute syn_keep of clk40 : signal is true;
attribute syn_preserve of clk40 : signal is true;
attribute syn_keep of clk65 : signal is true;
attribute syn_preserve of clk65 : signal is true;
attribute syn_keep of phy_init_done : signal is true;
attribute syn_preserve of phy_init_done : signal is true;
attribute syn_keep of pciclk : signal is true;
attribute syn_preserve of pciclk : signal is true;
attribute syn_keep of sgmii_refclk : signal is true;
attribute syn_preserve of sgmii_refclk : signal is true;
attribute keep : boolean;
attribute keep of lock0 : signal is true;
attribute keep of lock1 : signal is true;
attribute keep of clkml0 : signal is true;
attribute keep of clkml1 : signal is true;
attribute keep of clkm : signal is true;
attribute keep of egtx_clk : signal is true;
attribute keep of clkvga : signal is true;
attribute keep of clk25 : signal is true;
attribute keep of clk40 : signal is true;
attribute keep of clk65 : signal is true;
attribute keep of pciclk : signal is true;
attribute keep of sgmii_refclk : signal is true;
attribute syn_noprune : boolean;
attribute syn_noprune of sysace_fpga_clk_pad : label is true;
begin
vcc <= (others => '1'); gnd <= (others => '0');
rst0_tbn <= not rst0_tb;
----------------------------------------------------------------------
--- Reset and Clock generation -------------------------------------
----------------------------------------------------------------------
flashclk_pad : outpad generic map (tech => padtech, slew => 1, strength => 24)
port map (flash_clk, flashclkl);
sysace_fpga_clk_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sysace_fpga_clk, clkace);
pci_p_clk5_pad : clkpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (pci_p_clk5, pci_clk_fb);
pci_p_clk5_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk5_r, pci_clk);
pci_p_clk4_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk4_r, pci_clk);
pci_p_clk3_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk3_r, pci_clk);
pci_p_clk1_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk1_r, pci_clk);
pci_p_clk0_r_pad : outpad generic map (tech => padtech, level => pci33)
port map (pci_p_clk0_r, pci_clk);
clkgen0 : clkgen -- system clock generator
generic map (CFG_FABTECH, CFG_CLKMUL, CFG_CLKDIV, 1, 1,
1, CFG_PCIDLL, CFG_PCISYSCLK, BOARD_FREQ, 1)
port map (lclk, pci_clk_fb, clkmc, open, clkm2x, flashclkl, pciclk, cgi, cgo,
open, open, clk_200);
cgi.pllctrl <= "00"; cgi.pllrst <= rstraw; cgi.pllref <= '0';
-- clkgen1 : clkgen -- Ethernet 1G PHY clock generator
-- generic map (CFG_FABTECH, 5, 4, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
-- port map (lclk, gnd(0), egtx_clk, open, open, open, open, cgi2, cgo2);
-- cgi2.pllctrl <= "00"; cgi2.pllrst <= rstraw; --cgi2.pllref <= egtx_clk_fb;
-- egtx_clk_pad : outpad generic map (tech => padtech)
-- port map (phy_gtx_clk, egtx_clk);
clkgen2 : clkgen -- PCI clock generator
generic map (CFG_FABTECH, 2, 6, 0, 0, 0, 0, 0, BOARD_FREQ, 0)
port map (lclk, gnd(0), pci_clk, open, open, open, open, cgi3, cgo3);
cgi3.pllctrl <= "00"; cgi3.pllrst <= rstraw; cgi3.pllref <= '0';
iic_reset_b_pad : outpad generic map (tech => padtech)
port map (iic_reset_b, rstn);
resetn_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (fpga_cpu_reset_b, rst);
rst0 : rstgen -- reset generator
port map (rst, clkm, clklock, rstn, rstraw);
clklock <= lock0 and lock1 and cgo.clklock and cgo3.clklock;
clk_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (user_clksys, lclk);
----------------------------------------------------------------------
--- AHB CONTROLLER --------------------------------------------------
----------------------------------------------------------------------
ahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, devid => XILINX_ML510,
ioen => IOAEN, nahbm => maxahbm, nahbs => 11)
port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
----------------------------------------------------------------------
--- LEON processor and DSU -----------------------------------------
----------------------------------------------------------------------
leon : leon_dsu_stat_base
generic map (
leon => CFG_LEON, ncpu => ncpu, fabtech => fabtech, memtech => memtech,
nwindows => CFG_NWIN, dsu => CFG_DSU, fpu => CFG_FPU, v8 => CFG_V8, cp => 0,
mac => CFG_MAC, pclow => pclow, notag => 0, nwp => CFG_NWP, icen => CFG_ICEN,
irepl => CFG_IREPL, isets => CFG_ISETS, ilinesize => CFG_ILINE,
isetsize => CFG_ISETSZ, isetlock => CFG_ILOCK, dcen => CFG_DCEN,
drepl => CFG_DREPL, dsets => CFG_DSETS, dlinesize => CFG_DLINE,
dsetsize => CFG_DSETSZ, dsetlock => CFG_DLOCK, dsnoop => CFG_DSNOOP,
ilram => CFG_ILRAMEN, ilramsize => CFG_ILRAMSZ, ilramstart => CFG_ILRAMADDR,
dlram => CFG_DLRAMEN, dlramsize => CFG_DLRAMSZ, dlramstart => CFG_DLRAMADDR,
mmuen => CFG_MMUEN, itlbnum => CFG_ITLBNUM, dtlbnum => CFG_DTLBNUM,
tlb_type => CFG_TLB_TYPE, tlb_rep => CFG_TLB_REP, lddel => CFG_LDDEL,
disas => disas, tbuf => CFG_ITBSZ, pwd => CFG_PWD, svt => CFG_SVT,
rstaddr => CFG_RSTADDR, smp => ncpu-1, cached => CFG_DFIXED,
wbmask => CFG_BWMASK, busw => CFG_CACHEBW, netlist => CFG_LEON_NETLIST,
ft => CFG_LEONFT_EN, npasi => CFG_NP_ASI, pwrpsr => CFG_WRPSR,
rex => CFG_REX, altwin => CFG_ALTWIN, grfpush => CFG_GRFPUSH,
dsu_hindex => 2, dsu_haddr => 16#D00#, dsu_hmask => 16#F00#, atbsz => CFG_ATBSZ,
stat => CFG_STAT_ENABLE, stat_pindex => 12, stat_paddr => 16#100#,
stat_pmask => 16#ffc#, stat_ncnt => CFG_STAT_CNT, stat_nmax => CFG_STAT_NMAX)
port map (
rstn => rstn, ahbclk => clkm, cpuclk => clkm, hclken => vcc(0),
leon_ahbmi => ahbmi, leon_ahbmo => ahbmo(CFG_NCPU-1 downto 0),
leon_ahbsi => ahbsi, leon_ahbso => ahbso,
irqi => irqi, irqo => irqo,
stat_apbi => apbi, stat_apbo => apbo(12), stat_ahbsi => ahbsi,
stati => perf,
dsu_ahbsi => ahbsi, dsu_ahbso => ahbso(2),
dsu_tahbmi => ahbmi, dsu_tahbsi => ahbsi,
sysi => sysi, syso => syso);
sysi.dsu_enable <= '1';
sysi.dsu_break <= not gpioo.val(0); -- Position on GPIO DIP switch
opb_bus_error_pad : outpad generic map (tech => padtech)
port map (opb_bus_error, syso.proc_errorn);
plb_bus_error_pad : outpad generic map (tech => padtech)
port map (plb_bus_error, syso.dsu_active);
dcomgen : if CFG_AHB_UART = 1 generate
dcom0: ahbuart -- Debug UART
generic map (hindex => NCPU, pindex => 7, paddr => 7)
port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(NCPU));
end generate;
nodcom : if CFG_AHB_UART = 0 generate
duo.txd <= '0'; duo.rtsn <= '1';
end generate;
dsurx_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rxd, dui.rxd);
dsutx_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_txd, duo.txd);
-- dsucts_pad : inpad generic map (tech => padtech, level => cmos, voltage => x33v)
-- port map (uart0_cts_b, dui.ctsn);
dsurts_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (uart0_rts_b, duo.rtsn);
ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => NCPU+CFG_AHB_UART)
port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(NCPU+CFG_AHB_UART),
open, open, open, open, open, open, open, gnd(0));
end generate;
----------------------------------------------------------------------
--- Memory controllers ----------------------------------------------
----------------------------------------------------------------------
memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "01";
memi.brdyn <= '1'; memi.bexcn <= '1';
mctrl0 : if CFG_MCTRL_LEON2 = 1 generate
mctrl0 : mctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0,
ram8 => CFG_MCTRL_RAM8BIT, ram16 => CFG_MCTRL_RAM16BIT,
sden => CFG_MCTRL_SDEN, invclk => CFG_MCTRL_INVCLK,
sepbus => CFG_MCTRL_SEPBUS)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
ftmctrl0 : if CFG_MCTRLFT = 1 generate -- FT memory controller
sr1 : ftmctrl generic map (hindex => 3, pindex => 0,
ramaddr => 0, rammask => 0, paddr => 0, srbanks => 0, sden => CFG_MCTRLFT_SDEN,
ram8 => CFG_MCTRLFT_RAM8BIT, ram16 => CFG_MCTRLFT_RAM16BIT,
invclk => CFG_MCTRLFT_INVCLK,
sepbus => CFG_MCTRLFT_SEPBUS,
edac => CFG_MCTRLFT_EDAC)
port map (rstn, clkm, memi, memo, ahbsi, ahbso(3), apbi, apbo(0), wpo);
end generate;
nomctrl: if (CFG_MCTRL_LEON2 + CFG_MCTRLFT) = 0 generate
memo.address <= (others => '0'); memo.romsn <= (others => '1');
memo.oen <= '1'; memo.wrn <= (others => '1');
memo.vbdrive <= (others => '1'); memo.writen <= '1';
end generate;
flash_reset_b_pad : outpad generic map (tech => padtech)
port map (flash_reset_b, rstn);
-- flash_wait_pad : inpad generic map (tech => padtech)
-- port map (flash_wait, );
flash_adv_b_pad : outpad generic map (tech => padtech)
port map (flash_adv_b, gnd(0));
flash_a_pads : outpadv generic map (width => 22, tech => padtech)
port map (flash_a, memo.address(22 downto 1));
flash_ce_b_pad : outpad generic map (tech => padtech)
port map (flash_ce_b, memo.romsn(0));
flash_oe_b_pad : outpad generic map (tech => padtech)
port map (flash_oe_b, memo.oen);
--pragma translate_off
rwen_pad : outpad generic map (tech => padtech)
port map (sram_bw, memo.wrn(3));
sim_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (sim_d, memo.data(15 downto 0),
memo.vbdrive(15 downto 0), memi.data(15 downto 0));
iosn_pad : outpad generic map (tech => padtech)
port map (iosn, memo.iosn);
--pragma translate_on
flash_we_b_pad : outpad generic map (tech => padtech)
port map (flash_we_b, memo.writen);
flash_d_pads : iopadvv generic map (tech => padtech, width => 16)
port map (flash_d, memo.data(31 downto 16),
memo.vbdrive(31 downto 16), memi.data(31 downto 16));
dbg_led0_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dbg_led(3), phy_init_done);
clkm <= clkma; clkma <= clkmb; clkmb <= clkmc;
-----------------------------------------------------------------------------
-- L2 cache, optionally covering DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
l2cen : if CFG_L2_EN /= 0 generate
l2cblock : block
signal mem_ahbsi : ahb_slv_in_type;
signal mem_ahbso : ahb_slv_out_vector := (others => ahbs_none);
signal mem_ahbmi : ahb_mst_in_type;
signal mem_ahbmo : ahb_mst_out_vector := (others => ahbm_none);
signal l2c_stato : std_logic_vector(10 downto 0);
begin
l2c0 : l2c generic map (
hslvidx => 0, hmstidx => 0, cen => CFG_L2_PEN,
haddr => 16#400#, hmask => 16#c00#, ioaddr => 16#FF0#,
cached => CFG_L2_MAP, repl => CFG_L2_RAN, ways => CFG_L2_WAYS,
linesize => CFG_L2_LSZ, waysize => CFG_L2_SIZE,
memtech => memtech, bbuswidth => AHBDW,
bioaddr => 16#FFE#, biomask => 16#fff#,
sbus => 0, mbus => 1, arch => CFG_L2_SHARE,
ft => CFG_L2_EDAC)
port map(rst => rstn, clk => clkm, ahbsi => ahbsi, ahbso => ahbso(0),
ahbmi => mem_ahbmi, ahbmo => mem_ahbmo(0), ahbsov => mem_ahbso,
sto => l2c_stato);
memahb0 : ahbctrl -- AHB arbiter/multiplexer
generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
rrobin => CFG_RROBIN, ioaddr => 16#FFE#,
ioen => 1, nahbm => 1, nahbs => 2)
port map (rstn, clkm, mem_ahbmi, mem_ahbmo, mem_ahbsi, mem_ahbso);
mem_ahbso(1 downto 0) <= ddr2spa_ahbso;
ddr2spa_ahbsi <= mem_ahbsi;
perf.event(15 downto 7) <= (others => '0');
perf.esource(15 downto 7) <= (others => (others => '0'));
perf.event(6) <= l2c_stato(10); -- Data uncorrectable error
perf.event(5) <= l2c_stato(9); -- Data correctable error
perf.event(4) <= l2c_stato(8); -- Tag uncorrectable error
perf.event(3) <= l2c_stato(7); -- Tag correctable error
perf.event(2) <= l2c_stato(2); -- Bus access
perf.event(1) <= l2c_stato(1); -- Miss
perf.event(0) <= l2c_stato(0); -- Hit
perf.esource(6 downto 3) <= (others => (others => '0'));
perf.esource(2 downto 0) <= (others => l2c_stato(6 downto 3));
perf.req <= (others => '0');
perf.sel <= (others => '0');
perf.latcnt <= '0';
--perf.timer <= dbgi(0).timer(31 downto 0);
end block l2cblock;
end generate l2cen;
nol2c : if CFG_L2_EN = 0 generate
ahbso(1 downto 0) <= ddr2spa_ahbso;
ddr2spa_ahbsi <= ahbsi;
perf <= l3stat_in_none;
end generate;
-----------------------------------------------------------------------------
-- DDR2 SDRAM memory controller
-----------------------------------------------------------------------------
ddrsp0 : if (CFG_DDR2SP /= 0) generate
phy_init_done <= '1';
-- DDR clock selection
-- If the synchronization registers are removed in the DDR controller, we
-- assume that the user wants to run at 2x the system clock. Otherwise the
-- DDR clock is generated from the 200 MHz clock.
ddrclkselarb: if CFG_DDR2SP_NOSYNC = 0 generate
BUFGDDR : BUFG port map (I => clk_200, O => clkddr);
end generate;
ddrclksel2x: if CFG_DDR2SP_NOSYNC /= 0 generate
clkddr <= clkm2x;
end generate;
dimm0_ddr2_reset_n_pad : outpad generic map (tech => padtech, level => cmos, voltage => x33v)
port map (dimm0_ddr2_reset_n, rst);
-- Slot 0
ddrc0 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 0, haddr => 16#400#, hmask => 16#e00#, ioaddr => 1,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
cbdelayb0 => CFG_DDR2SP_DELAY0, cbdelayb1 => CFG_DDR2SP_DELAY0,
cbdelayb2 => CFG_DDR2SP_DELAY0, cbdelayb3 => CFG_DDR2SP_DELAY0,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC, ft => CFG_DDR2SP_FTEN, ftbits => CFG_DDR2SP_FTWIDTH)
port map (rst, rstn, clkddr, clkm, clk_200, lock0, clkml0, clkml0,
ddr2spa_ahbsi, ddr2spa_ahbso(0),
ddr0_clkv, ddr0_clkbv, ddr0_clk_fb, ddr0_clk_fb,
dimm0_ddr2_cke, dimm0_ddr2_s_b, dimm0_ddr2_we_b, dimm0_ddr2_ras_b,
dimm0_ddr2_cas_b, dimm0_ddr2_dqm(CFG_DDR2SP_FTWIDTH/8+CFG_DDR2SP_DATAWIDTH/8-1 downto 0),
dimm0_ddr2_dqs_p(CFG_DDR2SP_FTWIDTH/8+CFG_DDR2SP_DATAWIDTH/8-1 downto 0),
dimm0_ddr2_dqs_n(CFG_DDR2SP_FTWIDTH/8+CFG_DDR2SP_DATAWIDTH/8-1 downto 0), dimm0_ddr2_a,
dimm0_ddr2_ba(2 downto 0), dimm0_ddr2_dq(CFG_DDR2SP_FTWIDTH+CFG_DDR2SP_DATAWIDTH-1 downto 0),
dimm0_ddr2_odt);
dimm0_ddr2_pll_clkin_p <= ddr0_clkv(0);
dimm0_ddr2_pll_clkin_n <= ddr0_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm0_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm0_ddr2_ba(2), gnd(0));
dimm0_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm0_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm0_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm0_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm0_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm0_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr032bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm0_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm0_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm0_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm0_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm0_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm0_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
-- Slot 1
ddrc1 : ddr2spa generic map ( fabtech => fabtech, memtech => memtech,
hindex => 1, haddr => 16#600#, hmask => 16#E00#, ioaddr => 2,
pwron => CFG_DDR2SP_INIT, MHz => DDR_FREQ/1000, TRFC => CFG_DDR2SP_TRFC,
clkmul => CFG_DDR2SP_FREQ/10 - (CFG_DDR2SP_FREQ/10-1)*CFG_DDR2SP_NOSYNC,
clkdiv => 20 - (19)*CFG_DDR2SP_NOSYNC, ahbfreq => CPU_FREQ/1000,
col => CFG_DDR2SP_COL, Mbyte => CFG_DDR2SP_SIZE, ddrbits => CFG_DDR2SP_DATAWIDTH,
ddelayb0 => CFG_DDR2SP_DELAY0, ddelayb1 => CFG_DDR2SP_DELAY1,
ddelayb2 => CFG_DDR2SP_DELAY2, ddelayb3 => CFG_DDR2SP_DELAY3,
ddelayb4 => CFG_DDR2SP_DELAY4, ddelayb5 => CFG_DDR2SP_DELAY5,
ddelayb6 => CFG_DDR2SP_DELAY6, ddelayb7 => CFG_DDR2SP_DELAY7,
readdly => 1, rskew => 0, oepol => 0,
dqsgating => 0, rstdel => 200, eightbanks => 1,
numidelctrl => 2 + CFG_DDR2SP_DATAWIDTH/64, norefclk => 0, odten => 3,
nosync => CFG_DDR2SP_NOSYNC)
port map (rst, rstn, clkddr, clkm, clk_200, lock1, clkml1, clkml1,
ddr2spa_ahbsi, ddr2spa_ahbso(1),
ddr1_clkv, ddr1_clkbv, ddr1_clk_fb, ddr1_clk_fb,
dimm1_ddr2_cke, dimm1_ddr2_s_b, dimm1_ddr2_we_b, dimm1_ddr2_ras_b,
dimm1_ddr2_cas_b, dimm1_ddr2_dqm(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_p(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_dqs_n(7 downto 4*(32/CFG_DDR2SP_DATAWIDTH)), dimm1_ddr2_a,
dimm1_ddr2_ba(2 downto 0), dimm1_ddr2_dq(63 downto 32*(32/ CFG_DDR2SP_DATAWIDTH)),
dimm1_ddr2_odt);
dimm1_ddr2_pll_clkin_p <= ddr1_clkv(0);
dimm1_ddr2_pll_clkin_n <= ddr1_clkbv(0);
-- Ground unused bank address and memory mask
-- dimm1_ddr2_ba_notused_pad : outpad generic map (tech => padtech, level => SSTL18_I)
-- port map (dimm1_ddr2_ba(2), gnd(0));
dimm1_ddr2_dqm_notused8_pad : outpad generic map (tech => padtech, level => SSTL18_I)
port map (dimm1_ddr2_dqm(8), gnd(0));
-- Tri-state unused data strobe
dimm1_dqsp_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(8), gnd(0), vcc(0), open);
dimm1_dqsn_notused8_pad : iopad generic map (tech => padtech, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(8), gnd(0), vcc(0), open);
-- Tristate unused check bits
dimm1_cb_notused_pad : iopadv generic map (tech => padtech, width => 8, level => SSTL18_II)
port map (dimm1_ddr2_dq(71 downto 64), gnd(7 downto 0), vcc(0), open);
-- Handle signals not used with 32-bit interface
ddr132bit: if CFG_DDR2SP_DATAWIDTH /= 64 generate
dimm1_ddr2_dqm_notused30_pads : outpadv generic map (tech => padtech, width => 4, level => SSTL18_I)
port map (dimm1_ddr2_dqm(3 downto 0), gnd(3 downto 0));
dimm1_dqsp_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_p(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dqsn_notused30_pads : iopadv generic map (tech => padtech, width => 4, level => SSTL18_II)
port map (dimm1_ddr2_dqs_n(3 downto 0), gnd(3 downto 0), vcc(0), open);
dimm1_dq_notused_pads : iopadv generic map (tech => padtech, width => 32, level => SSTL18_II)
port map (dimm1_ddr2_dq(31 downto 0), gnd, vcc(0), open);
end generate;
end generate;
-- noddr : if (CFG_DDR2SP = 0) generate lock0 <= '1'; lock1 <= '1'; end generate;
----------------------------------------------------------------------
--- System ACE I/F Controller ---------------------------------------
----------------------------------------------------------------------
grace: if CFG_GRACECTRL = 1 generate
grace0 : gracectrl generic map (hindex => 5, hirq => 5,
haddr => 16#000#, hmask => 16#fff#, split => CFG_SPLIT)
port map (rstn, clkm, clkace, ahbsi, ahbso(5), acei, aceo);
end generate;
nograce: if CFG_GRACECTRL = 0 generate
aceo <= gracectrl_none;
end generate nograce;
sysace_mpa_pads : outpadv generic map (width => 7, tech => padtech)
port map (sysace_mpa, aceo.addr);
sysace_mpce_pad : outpad generic map (tech => padtech)
port map (sysace_mpce, aceo.cen);
sysace_mpd_pads : iopadv generic map (tech => padtech, width => 16)
port map (sysace_mpd, aceo.do, aceo.doen, acei.di);
sysace_mpoe_pad : outpad generic map (tech => padtech)
port map (sysace_mpoe, aceo.oen);
sysace_mpwe_pad : outpad generic map (tech => padtech)
port map (sysace_mpwe, aceo.wen);
sysace_mpirq_pad : inpad generic map (tech => padtech)
port map (sysace_mpirq, acei.irq);
----------------------------------------------------------------------
--- AHB ROM ---------------------------------------------------------
----------------------------------------------------------------------
bpromgen : if CFG_AHBROMEN /= 0 generate
brom : entity work.ahbrom
generic map (hindex => 10, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
port map (rstn, clkm, ahbsi, ahbso(10));
end generate;
----------------------------------------------------------------------
--- APB Bridge and various periherals -------------------------------
----------------------------------------------------------------------
apb0 : apbctrl -- AHB/APB bridge
generic map (hindex => 4, haddr => CFG_APBADDR, nslaves => 16)
port map (rstn, clkm, ahbsi, ahbso(4), apbi, apbo);
ua1 : if CFG_UART1_ENABLE /= 0 generate
uart1 : apbuart -- UART 1
generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
fifosize => CFG_UART1_FIFO)
port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
u1i.extclk <= '0';
end generate;
noua1: if CFG_UART1_ENABLE = 0 generate u1o.txd <= '0'; u1o.rtsn <= '1'; end generate;
ua1rx_pad : inpad generic map (tech => padtech) port map (uart1_rxd, u1i.rxd);
ua1tx_pad : outpad generic map (tech => padtech) port map (uart1_txd, u1o.txd);
ua1cts_pad : inpad generic map (tech => padtech) port map (uart1_cts_b, u1i.ctsn);
ua1rts_pad : outpad generic map (tech => padtech) port map (uart1_rts_b, u1o.rtsn);
irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
irqctrl0 : irqmp -- interrupt controller
generic map (pindex => 2, paddr => 2, ncpu => NCPU)
port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
end generate;
irq3 : if CFG_IRQ3_ENABLE = 0 generate
x : for i in 0 to NCPU-1 generate
irqi(i).irl <= "0000";
end generate;
apbo(2) <= apb_none;
end generate;
pci_dirq(3 downto 1) <= (others => '0');
pci_dirq(0) <= orv(irqi(0).irl);
gpt : if CFG_GPT_ENABLE /= 0 generate
timer0 : gptimer -- timer unit
generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
nbits => CFG_GPT_TW)
port map (rstn, clkm, apbi, apbo(3), gpti, open);
gpti <= gpti_dhalt_drive(syso.dsu_tstop);
end generate;
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
svga : if CFG_SVGA_ENABLE /= 0 generate
svga0 : svgactrl generic map(memtech => memtech, pindex => 14, paddr => 14,
hindex => CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG,
clk0 => 40000, clk1 => 40000, clk2 => 25000, clk3 => 15385, burstlen => 6)
port map(rstn, clkm, clkvga, apbi, apbo(14), vgao, ahbmi,
ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_AHB_JTAG), clk_sel);
dvi0 : svga2ch7301c generic map (tech => fabtech, idf => 2)
port map (lclk, rstraw, clk_sel, vgao, clkvga, clk25, clk40, clk65,
clkvga, clk25, clk40, clk65, clkvga_p, clkvga_n,
vgalock, lcd_datal, lcd_hsyncl, lcd_vsyncl, lcd_del);
i2cdvi : i2cmst
generic map (pindex => 6, paddr => 6, pmask => 16#FFF#,
pirq => 6, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(6), dvi_i2ci, dvi_i2co);
end generate;
novga : if CFG_SVGA_ENABLE = 0 generate
apbo(14) <= apb_none; apbo(6) <= apb_none;
lcd_datal <= (others => '0'); clkvga_p <= '0'; clkvga_n <= '0';
lcd_hsyncl <= '0'; lcd_vsyncl <= '0'; lcd_del <= '0';
dvi_i2co.scloen <= '1'; dvi_i2co.sdaoen <= '1';
end generate;
dvi_d_pad : outpadv generic map (width => 12, tech => padtech)
port map (dvi_d, lcd_datal);
dvi_xclk_p_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_p, clkvga_p);
dvi_xclk_n_pad : outpad generic map (tech => padtech)
port map (dvi_xclk_n, clkvga_n);
dvi_h_pad : outpad generic map (tech => padtech)
port map (dvi_h, lcd_hsyncl);
dvi_v_pad : outpad generic map (tech => padtech)
port map (dvi_v, lcd_vsyncl);
dvi_de_pad : outpad generic map (tech => padtech)
port map (dvi_de, lcd_del);
dvi_reset_b_pad : outpad generic map (tech => padtech)
port map (dvi_reset_b, rstn);
iic_scl_dvi_pad : iopad generic map (tech => padtech)
port map (iic_scl_dvi, dvi_i2co.scl, dvi_i2co.scloen, dvi_i2ci.scl);
iic_sda_dvi_pad : iopad generic map (tech => padtech)
port map (iic_sda_dvi, dvi_i2co.sda, dvi_i2co.sdaoen, dvi_i2ci.sda);
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
grgpio0: grgpio
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => CFG_GRGPIO_WIDTH)
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
gpioi => gpioi, gpioo => gpioo);
end generate;
nogpio0: if CFG_GRGPIO_ENABLE = 0 generate
gpioo.oen <= (others => '1'); gpioo.val <= (others => '0');
gpioo.dout <= (others => '1');
end generate;
dbg_led_0 : inpad generic map (tech => padtech)
port map (dbg_led(0), gpioi.din(0));
dbg_led_pads : iopadvv generic map (tech => padtech, width => 2, level => cmos, voltage => x33v)
port map (dbg_led(2 downto 1), gpioo.dout(2 downto 1), gpioo.oen(2 downto 1),
gpioi.din(2 downto 1));
dvi_gpio_pad : iopad generic map (tech => padtech)
port map (dvi_gpio1, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
iic_therm_b_pad : inpad generic map (tech => padtech)
port map (iic_therm_b, gpioi.din(9));
iic_irq_b_pad : inpad generic map (tech => padtech)
port map (iic_irq_b, gpioi.din(10));
iic_alert_b_pad : inpad generic map (tech => padtech)
port map (iic_alert_b, gpioi.din(11));
sbr_pwg_rsm_rstj_pad : iopad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_pwg_rsm_rstj, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
sbr_nmi_r_pad : inpad generic map (tech => padtech)
port map (sbr_nmi_r, gpioi.din(6));
sbr_intr_r_pad : inpad generic map (tech => padtech, level => cmos, voltage => x25v)
port map (sbr_intr_r, gpioi.din(5));
sbr_ide_rst_b_pad : iopad generic map (tech => padtech)
port map (sbr_ide_rst_b, gpioo.dout(8), gpioo.oen(8), gpioi.din(8));
i2cm: if CFG_I2C_ENABLE = 1 generate -- I2C master
i2c0 : i2cmst
generic map (pindex => 9, paddr => 9, pmask => 16#FFF#,
pirq => 3, filter => I2C_FILTER)
port map (rstn, clkm, apbi, apbo(9), i2ci, i2co);
end generate;
noi2cm: if CFG_I2C_ENABLE = 0 generate
i2co.scloen <= '1'; i2co.sdaoen <= '1';
i2co.scl <= '0'; i2co.sda <= '0';
end generate;
i2c_scl_pad : iopad generic map (tech => padtech)
port map (fpga_scl, i2co.scl, i2co.scloen, i2ci.scl);
i2c_sda_pad : iopad generic map (tech => padtech)
port map (fpga_sda, i2co.sda, i2co.sdaoen, i2ci.sda);
spic: if CFG_SPICTRL_ENABLE = 1 generate -- SPI controller
spi1 : spictrl
generic map (pindex => 10, paddr => 10, pmask => 16#fff#, pirq => 12,
fdepth => CFG_SPICTRL_FIFO, slvselen => CFG_SPICTRL_SLVREG,
slvselsz => CFG_SPICTRL_SLVS, odmode => 0, netlist => 0,
syncram => CFG_SPICTRL_SYNCRAM, ft => CFG_SPICTRL_FT)
port map (rstn, clkm, apbi, apbo(10), spii, spio, slvsel);
spii.spisel <= '1'; -- Master only
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, spio.mosi);
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, spio.sck);
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, slvsel(0));
end generate spic;
nospi: if CFG_SPICTRL_ENABLE = 0 generate
miso_pad : inpad generic map (tech => padtech)
port map (spi_data_out, spii.miso);
mosi_pad : outpad generic map (tech => padtech)
port map (spi_data_in, vcc(0));
sck_pad : outpad generic map (tech => padtech)
port map (spi_clk, gnd(0));
slvsel_pad : outpad generic map (tech => padtech)
port map (spi_data_cs_b, vcc(0));
end generate;
ahbs : if CFG_AHBSTAT = 1 generate -- AHB status register
stati <= ahbstat_in_none;
ahbstat0 : ahbstat generic map (pindex => 15, paddr => 15, pirq => 7,
nftslv => CFG_AHBSTATN)
port map (rstn, clkm, ahbmi, ahbsi, stati, apbi, apbo(15));
end generate;
apb1 : apbctrl -- AHB/APB bridge
generic map (hindex => 6, haddr => CFG_APBADDR + 1, nslaves => 3)
port map (rstn, clkm, ahbsi, ahbso(6), apb1i, apb1o);
-----------------------------------------------------------------------
--- ETHERNET ---------------------------------------------------------
-----------------------------------------------------------------------
eth1 : if CFG_GRETH = 1 generate -- Gaisler ethernet MAC
e1 : grethm generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE,
pindex => 11, paddr => 11, pirq => 4, memtech => memtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH1G)
port map( rst => rstn, clk => clkm, ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE),
apbi => apbi, apbo => apbo(11), ethi => ethi, etho => etho);
emdio_pad : iopad generic map (tech => padtech)
port map (phy0_mdio, etho.mdio_o, etho.mdio_oe, ethi.mdio_i);
etxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_txclk, ethi.tx_clk);
erxc_pad : clkpad generic map (tech => padtech, arch => 2, level => cmos, voltage => x25v)
port map (phy0_rxclk, ethi.rx_clk);
erxd_pad : inpadv generic map (tech => padtech, width => 4)
port map (phy0_rxd, ethi.rxd(3 downto 0));
erxdv_pad : inpad generic map (tech => padtech)
port map (phy0_rxctl_rxdv, ethi.rx_dv);
erxer_pad : inpad generic map (tech => padtech)
port map (phy0_rxer, ethi.rx_er);
-- Collision detect and carrier sense are not connected on the
-- board.
ethi.rx_col <= '0';
ethi.rx_crs <= ethi.rx_dv;
etxd_pad : outpadv generic map (tech => padtech, width => 4)
port map (phy0_txd, etho.txd(3 downto 0));
etxen_pad : outpad generic map (tech => padtech)
port map (phy0_txctl_txen, etho.tx_en);
etxer_pad : outpad generic map (tech => padtech)
port map (phy0_txer, etho.tx_er);
emdc_pad : outpad generic map (tech => padtech)
port map (phy0_mdc, etho.mdc);
erst_pad : outpad generic map (tech => padtech)
port map (phy0_reset, rstn);
-- ethi.gtx_clk <= egtx_clk;
end generate;
eth2 : if CFG_GRETH2 = 1 generate -- Gaisler ethernet MAC
sgmii_rst <= not rst;
refclk_bufds : IBUFDS
port map (
I => sgmiiclk_qo_p,
IB => sgmiiclk_qo_n,
O => sgmii_refclk);
e2 : greths generic map(hindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH,
pindex => 2, paddr => 2, pirq => 10,
fabtech => fabtech, memtech => memtech, transtech => transtech,
mdcscaler => CPU_FREQ/1000, enable_mdio => 1, fifosize => CFG_ETH2_FIFO,
nsync => 1, edcl => CFG_DSU_ETH, edclbufsz => CFG_ETH_BUF,
macaddrh => CFG_ETH_ENM, macaddrl => CFG_ETH_ENL, phyrstadr => 7,
ipaddrh => CFG_ETH_IPM, ipaddrl => CFG_ETH_IPL, giga => CFG_GRETH21G)
port map(
rst => rstn,
clk => clkm,
ahbmi => ahbmi,
ahbmo => ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH),
apbi => apb1i,
apbo => apb1o(2),
-- High-speed Serial Interface
clk_125 => sgmii_refclk,
rst_125 => sgmii_rst,
eth_rx_p => phy1_sgmii_rx_p,
eth_rx_n => phy1_sgmii_rx_n,
eth_tx_p => phy1_sgmii_tx_p,
eth_tx_n => phy1_sgmii_tx_n,
-- MDIO interface
reset => mdio_reset,
mdio_o => mdio_o,
mdio_oe => mdio_oe,
mdio_i => mdio_i,
mdc => mdc,
mdint => mdint,
-- Control signals
phyrstaddr => "00000",
edcladdr => "0000",
edclsepahb => '0',
edcldisable => '0'
);
e2mdio_pad : iopad generic map (tech => padtech)
port map (phy1_mdio, mdio_o, mdio_oe, mdio_i);
e2mdc_pad : outpad generic map (tech => padtech)
port map (phy1_mdc, mdc);
e2rst_pad : outpad generic map (tech => padtech)
port map (phy1_reset, mdio_reset);
e2int_pad : outpad generic map (tech => padtech)
port map (phy1_int, mdint);
end generate;
-----------------------------------------------------------------------
--- PCI ------------------------------------------------------------
----------------------------------------------------------------------
pp : if (CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET) /= 0 generate
pci0 : grpci2
generic map (
memtech => memtech,
oepol => 0,
hmindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2,
hdmindex => NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+1,
hsindex => 7,
haddr => 16#800#,
hmask => 16#c00#,
ioaddr => 16#400#,
pindex => 4,
paddr => 4,
irq => 5,
irqmode => 0,
master => CFG_GRPCI2_MASTER,
target => CFG_GRPCI2_TARGET,
dma => CFG_GRPCI2_DMA,
tracebuffer => CFG_GRPCI2_TRACE,
vendorid => CFG_GRPCI2_VID,
deviceid => CFG_GRPCI2_DID,
classcode => CFG_GRPCI2_CLASS,
revisionid => CFG_GRPCI2_RID,
cap_pointer => CFG_GRPCI2_CAP,
ext_cap_pointer => CFG_GRPCI2_NCAP,
iobase => CFG_AHBIO,
extcfg => CFG_GRPCI2_EXTCFG,
bar0 => CFG_GRPCI2_BAR0,
bar1 => CFG_GRPCI2_BAR1,
bar2 => CFG_GRPCI2_BAR2,
bar3 => CFG_GRPCI2_BAR3,
bar4 => CFG_GRPCI2_BAR4,
bar5 => CFG_GRPCI2_BAR5,
fifo_depth => CFG_GRPCI2_FDEPTH,
fifo_count => CFG_GRPCI2_FCOUNT,
conv_endian => CFG_GRPCI2_ENDIAN,
deviceirq => CFG_GRPCI2_DEVINT,
deviceirqmask => CFG_GRPCI2_DEVINTMSK,
hostirq => CFG_GRPCI2_HOSTINT,
hostirqmask => CFG_GRPCI2_HOSTINTMSK,
nsync => 2,
hostrst => 1,
bypass => CFG_GRPCI2_BYPASS,
debug => 0,
tbapben => 0,
tbpindex => 5,
tbpaddr => 16#400#,
tbpmask => 16#C00#
)
port map (
rstn,
clkm,
pciclk,
pci_dirq,
pcii,
pcio,
apbi,
apbo(4),
ahbsi,
ahbso(7),
ahbmi,
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2),
ahbmi,
ahbmo(NCPU+CFG_AHB_UART+CFG_AHB_JTAG+CFG_SVGA_ENABLE+CFG_GRETH+CFG_GRETH2+1)
);
pcia0 : if CFG_PCI_ARB = 1 generate -- PCI arbiter
pciarb0 : pciarb generic map (pindex => 13, paddr => 13, nb_agents => CFG_PCI_ARB_NGNT,
apb_en => CFG_PCI_ARBAPB)
port map (clk => pciclk, rst_n => pcii.rst, req_n => pci_arb_req, frame_n => pcii.frame,
gnt_n => pci_arb_gnt, pclk => clkm, prst_n => rstn, apbi => apbi, apbo => apbo(13));
-- Internal connection of req(2)
pci_arb_req(0 to 4) <= pci_arb_reql(0 to 1) & pci_reql & pci_arb_reql(3 to 4);
pci_arb_req(5 to 7) <= (others => '1');
end generate;
end generate;
nopcia0: if CFG_GRPCI2_MASTER = 0 or CFG_PCI_ARB = 0 generate
pci_arb_gnt <= (others => '1');
end generate;
nopci_mtf: if CFG_GRPCI2_MASTER+CFG_GRPCI2_TARGET = 0 generate
pcio <= pci_out_none;
end generate;
pgnt_pad : outpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_gnt_b, pci_arb_gnt(0 to 4));
preq_pad : inpadv generic map (tech => padtech, width => 5, level => pci33)
port map (pci_p_req_b, pci_arb_reql);
pcipads0 : pcipads -- PCI pads
generic map (padtech => padtech, host => 2, int => 14, no66 => 1, onchipreqgnt => 1,
drivereset => 1, constidsel => 1)
port map (pci_rst => pci_p_rst_b, pci_gnt => pci_arb_gnt(2), pci_idsel => '0', --pci_fpga_idsel,
pci_lock => pci_p_lock_b, pci_ad => pci_p_ad, pci_cbe => pci_p_cbe_b,
pci_frame => pci_p_frame_b, pci_irdy => pci_p_irdy_b, pci_trdy => pci_p_trdy_b,
pci_devsel => pci_p_devsel_b, pci_stop => pci_p_stop_b, pci_perr => pci_p_perr_b,
pci_par => pci_p_par, pci_req => pci_reql, pci_serr => pci_p_serr_b,
pci_host => pci_host, pci_66 => pci_66, pcii => pcii, pcio => pcio, pci_int => pci_intv);
pci_intv <= pci_p_intd_b & pci_p_intc_b & pci_p_intb_b & pci_p_inta_b;
pci_host <= '0'; -- Always host
pci_66 <= '0';
-----------------------------------------------------------------------
--- SYSTEM MONITOR ---------------------------------------------------
-----------------------------------------------------------------------
grsmon: if CFG_GRSYSMON = 1 generate
sysm0 : grsysmon generic map (tech => fabtech, hindex => 8,
hirq => 1, caddr => 16#003#, cmask => 16#fff#,
saddr => 16#004#, smask => 16#ffe#, split => CFG_SPLIT,
extconvst => 0, wrdalign => 1, INIT_40 => X"0000",
INIT_41 => X"0000", INIT_42 => X"0800", INIT_43 => X"0000",
INIT_44 => X"0000", INIT_45 => X"0000", INIT_46 => X"0000",
INIT_47 => X"0000", INIT_48 => X"0000", INIT_49 => X"0000",
INIT_4A => X"0000", INIT_4B => X"0000", INIT_4C => X"0000",
INIT_4D => X"0000", INIT_4E => X"0000", INIT_4F => X"0000",
INIT_50 => X"0000", INIT_51 => X"0000", INIT_52 => X"0000",
INIT_53 => X"0000", INIT_54 => X"0000", INIT_55 => X"0000",
INIT_56 => X"0000", INIT_57 => X"0000",
SIM_MONITOR_FILE => "sysmon.txt")
port map (rstn, clkm, ahbsi, ahbso(8), sysmoni, sysmono);
sysmoni.convst <= '0';
sysmoni.convstclk <= '0';
sysmoni.vauxn <= (others => '0');
sysmoni.vauxp <= (others => '0');
-- sysmoni.vn <= test_mon_vn0_n;
-- sysmoni.vp <= test_mon_vp0_p;
end generate grsmon;
-----------------------------------------------------------------------
--- AHB RAM ----------------------------------------------------------
-----------------------------------------------------------------------
ocram : if CFG_AHBRAMEN = 1 generate
ahbram0 : ahbram generic map (hindex => 9, haddr => CFG_AHBRADDR,
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ, pipe => CFG_AHBRPIPE)
port map ( rstn, clkm, ahbsi, ahbso(9));
end generate;
-----------------------------------------------------------------------
--- AHB DEBUG --------------------------------------------------------
-----------------------------------------------------------------------
-- dma0 : ahbdma
-- generic map (hindex => CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRETH2+CFG_AHB_JTAG,
-- pindex => 13, paddr => 13, dbuf => 6)
-- port map (rstn, clkm, apbi, apbo(13), ahbmi,
-- ahbmo(CFG_NCPU+CFG_AHB_UART+CFG_GRETH+CFG_GRETH2+CFG_AHB_JTAG));
-- at0 : ahbtrace
-- generic map ( hindex => 7, ioaddr => 16#200#, iomask => 16#E00#,
-- tech => memtech, irq => 0, kbytes => 8)
-- port map ( rstn, clkm, ahbmi, ahbsi, ahbso(7));
-----------------------------------------------------------------------
--- Drive unused bus elements ---------------------------------------
-----------------------------------------------------------------------
-- nam1 : for i in (NCPU+CFG_AHB_UART+CFG_ETH+CFG_AHB_ETH+CFG_AHB_JTAG) to NAHBMST-1 generate
-- ahbmo(i) <= ahbm_none;
-- end generate;
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
-----------------------------------------------------------------------
--- Boot message ----------------------------------------------------
-----------------------------------------------------------------------
-- pragma translate_off
x : report_design
generic map (
msg1 => system_table(XILINX_ML510),
fabtech => tech_table(fabtech), memtech => tech_table(memtech),
mdel => 1
);
-- pragma translate_on
end;
|
-------------------------------------------------------------- ------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
----------------------------------- ----------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ro_filt_3x3 is
generic (
vwidth: integer:=8;
order: integer:=5;
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
Dout : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic;
FColPos : out integer;
FRowPos : out integer
);
end ro_filt_3x3;
architecture ro_filt_3x3 of ro_filt_3x3 is
component sort_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
w11 : in std_logic_vector((vwidth -1) downto 0);
w12 : in std_logic_vector((vwidth -1) downto 0);
w13 : in std_logic_vector((vwidth -1) downto 0);
w21 : in std_logic_vector((vwidth-1) downto 0);
w22 : in std_logic_vector((vwidth -1) downto 0);
w23 : in std_logic_vector((vwidth -1) downto 0);
w31 : in std_logic_vector((vwidth -1) downto 0);
w32 : in std_logic_vector((vwidth -1) downto 0);
w33 : in std_logic_vector((vwidth-1) downto 0);
DVw : in std_logic;
DVs : out std_logic;
s1 : out std_logic_vector(vwidth -1 downto 0);
s2 : out std_logic_vector(vwidth -1 downto 0);
s3 : out std_logic_vector(vwidth -1 downto 0);
s4 : out std_logic_vector(vwidth-1 downto 0);
s5 : out std_logic_vector(vwidth -1 downto 0);
s6 : out std_logic_vector(vwidth -1 downto 0);
s7 : out std_logic_vector(vwidth -1 downto 0);
s8 : out std_logic_vector(vwidth -1 downto 0);
s9 : out std_logic_vector(vwidth -1 downto 0)
);
end component sort_3x3;
signal w11: std_logic_vector((vwidth -1) downto 0);
signal w12: std_logic_vector((vwidth -1) downto 0);
signal w13: std_logic_vector((vwidth -1) downto 0);
signal w21: std_logic_vector((vwidth -1) downto 0);
signal w22: std_logic_vector((vwidth-1) downto 0);
signal w23: std_logic_vector((vwidth -1) downto 0);
signal w31: std_logic_vector((vwidth -1) downto 0);
signal w32: std_logic_vector((vwidth -1) downto 0);
signal w33: std_logic_vector((vwidth -1) downto 0);
signal DVw: std_logic;
signal DVs: std_logic;
signal s1: std_logic_vector(vwidth -1 downto 0);
signal s2: std_logic_vector(vwidth -1 downto 0);
signal s3: std_logic_vector(vwidth -1 downto 0);
signal s4: std_logic_vector(vwidth -1 downto 0);
signal s5: std_logic_vector(vwidth-1 downto 0);
signal s6: std_logic_vector(vwidth -1 downto 0);
signal s7: std_logic_vector(vwidth -1 downto 0);
signal s8: std_logic_vector(vwidth -1 downto 0);
signal s9: std_logic_vector(vwidth -1 downto 0);
component window_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth-1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth-1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end component window_3x3;
component rc_counter
generic (
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end component rc_counter;
signal ColPos: integer:=0;
signal RowPos: integer:=0;
signal ColPos_c: integer:=0; -- corrected positions
signal RowPos_c: integer:=0;
signal rt1: integer:=0;
signal rt2: integer:=0;
signal rt3: integer:=0;
signal rt4: integer:=0;
signal rt5: integer:=0;
signal rt6: integer:=0;
signal rt7: integer:=0;
signal rt8: integer:=0;
signal rt9: integer:=0;
signal rt10: integer:=0;
signal rt11: integer:=0;
signal rt12: integer:=0;
signal rt13: integer:=0;
signal rt14: integer:=0;
signal rt15: integer:=0;
signal rt16: integer:=0;
signal flag: std_logic:='0';
begin
sort_3x3x: sort_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DVw => DVw,
DVs => DVs,
s1 => s1,
s2 => s2,
s3 => s3,
s4 => s4,
s5 => s5,
s6 => s6,
s7 => s7,
s8 => s8,
s9 => s9
);
window_3x3x: window_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
D => D,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DV => DVw
);
rc_counterx: rc_counter
generic map (
num_cols => 512,
num_rows => 512
)
port map (
Clk => Clk,
RSTn => RSTn,
En => RSTn,
ColPos => ColPos,
RowPos => RowPos
);
FColPos <= ColPos;
FRowPos <= RowPos;
ro_filt_proc: process(RSTn,Clk)
begin
if RSTn = '0' then
ColPos_c <= 0;
rt1 <= 0;
rt2 <= 0;
rt3 <= 0;
rt4 <= 0;
rt5 <= 0;
rt6 <= 0;
rt7 <= 0;
rt8 <= 0;
rt9 <= 0;
rt10 <= 0;
rt11 <= 0;
rt12 <= 0;
rt13 <= 0;
rt14 <= 0;
rt15 <= 0;
rt16 <= 0;
RowPos_c <= 0;
Dout <= (others=>'0');
DV <= '0';
flag <= '0';
elsif rising_edge(Clk) then
-- counter correction
ColPos_c <= ((ColPos-17) mod 512);
rt1 <= ((RowPos-1) mod 512);
rt2 <= rt1;
rt3 <= rt2;
rt4 <= rt3;
rt5 <= rt4;
rt6 <= rt5;
rt7 <= rt6;
rt8 <= rt7;
rt9 <= rt8;
rt10 <= rt9;
rt11 <= rt10;
rt12 <= rt11;
rt13 <= rt12;
rt14 <= rt13;
rt15 <= rt14;
rt16 <= rt15;
RowPos_c <= rt16;
-- screen edge detection
if (ColPos_c = num_cols-1) or (RowPos_c = num_rows-1) or (ColPos_c
= num_cols-2) or (RowPos_c = 0) then
Dout <= (others=>'0');
else
if order = 1 then
Dout <= s1;
elsif order = 2 then
Dout <= s2;
elsif order = 3 then
Dout <= s3;
elsif order = 4 then
Dout <= s4;
elsif order = 5 then
Dout <= s5;
elsif order = 6 then
Dout <= s6;
elsif order = 7 then
Dout <= s7;
elsif order = 8 then
Dout <= s8;
elsif order = 9 then
Dout <= s9;
end if;
end if;
if ColPos >= 17 and RowPos >= 1 then
DV <= '1';
flag <= '1';
elsif flag = '1' then
DV <= '1';
else
DV <= '0';
end if;
end if;
end process;
end ro_filt_3x3; |
-------------------------------------------------------------- ------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
----------------------------------- ----------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ro_filt_3x3 is
generic (
vwidth: integer:=8;
order: integer:=5;
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
Dout : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic;
FColPos : out integer;
FRowPos : out integer
);
end ro_filt_3x3;
architecture ro_filt_3x3 of ro_filt_3x3 is
component sort_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
w11 : in std_logic_vector((vwidth -1) downto 0);
w12 : in std_logic_vector((vwidth -1) downto 0);
w13 : in std_logic_vector((vwidth -1) downto 0);
w21 : in std_logic_vector((vwidth-1) downto 0);
w22 : in std_logic_vector((vwidth -1) downto 0);
w23 : in std_logic_vector((vwidth -1) downto 0);
w31 : in std_logic_vector((vwidth -1) downto 0);
w32 : in std_logic_vector((vwidth -1) downto 0);
w33 : in std_logic_vector((vwidth-1) downto 0);
DVw : in std_logic;
DVs : out std_logic;
s1 : out std_logic_vector(vwidth -1 downto 0);
s2 : out std_logic_vector(vwidth -1 downto 0);
s3 : out std_logic_vector(vwidth -1 downto 0);
s4 : out std_logic_vector(vwidth-1 downto 0);
s5 : out std_logic_vector(vwidth -1 downto 0);
s6 : out std_logic_vector(vwidth -1 downto 0);
s7 : out std_logic_vector(vwidth -1 downto 0);
s8 : out std_logic_vector(vwidth -1 downto 0);
s9 : out std_logic_vector(vwidth -1 downto 0)
);
end component sort_3x3;
signal w11: std_logic_vector((vwidth -1) downto 0);
signal w12: std_logic_vector((vwidth -1) downto 0);
signal w13: std_logic_vector((vwidth -1) downto 0);
signal w21: std_logic_vector((vwidth -1) downto 0);
signal w22: std_logic_vector((vwidth-1) downto 0);
signal w23: std_logic_vector((vwidth -1) downto 0);
signal w31: std_logic_vector((vwidth -1) downto 0);
signal w32: std_logic_vector((vwidth -1) downto 0);
signal w33: std_logic_vector((vwidth -1) downto 0);
signal DVw: std_logic;
signal DVs: std_logic;
signal s1: std_logic_vector(vwidth -1 downto 0);
signal s2: std_logic_vector(vwidth -1 downto 0);
signal s3: std_logic_vector(vwidth -1 downto 0);
signal s4: std_logic_vector(vwidth -1 downto 0);
signal s5: std_logic_vector(vwidth-1 downto 0);
signal s6: std_logic_vector(vwidth -1 downto 0);
signal s7: std_logic_vector(vwidth -1 downto 0);
signal s8: std_logic_vector(vwidth -1 downto 0);
signal s9: std_logic_vector(vwidth -1 downto 0);
component window_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth-1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth-1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end component window_3x3;
component rc_counter
generic (
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end component rc_counter;
signal ColPos: integer:=0;
signal RowPos: integer:=0;
signal ColPos_c: integer:=0; -- corrected positions
signal RowPos_c: integer:=0;
signal rt1: integer:=0;
signal rt2: integer:=0;
signal rt3: integer:=0;
signal rt4: integer:=0;
signal rt5: integer:=0;
signal rt6: integer:=0;
signal rt7: integer:=0;
signal rt8: integer:=0;
signal rt9: integer:=0;
signal rt10: integer:=0;
signal rt11: integer:=0;
signal rt12: integer:=0;
signal rt13: integer:=0;
signal rt14: integer:=0;
signal rt15: integer:=0;
signal rt16: integer:=0;
signal flag: std_logic:='0';
begin
sort_3x3x: sort_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DVw => DVw,
DVs => DVs,
s1 => s1,
s2 => s2,
s3 => s3,
s4 => s4,
s5 => s5,
s6 => s6,
s7 => s7,
s8 => s8,
s9 => s9
);
window_3x3x: window_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
D => D,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DV => DVw
);
rc_counterx: rc_counter
generic map (
num_cols => 512,
num_rows => 512
)
port map (
Clk => Clk,
RSTn => RSTn,
En => RSTn,
ColPos => ColPos,
RowPos => RowPos
);
FColPos <= ColPos;
FRowPos <= RowPos;
ro_filt_proc: process(RSTn,Clk)
begin
if RSTn = '0' then
ColPos_c <= 0;
rt1 <= 0;
rt2 <= 0;
rt3 <= 0;
rt4 <= 0;
rt5 <= 0;
rt6 <= 0;
rt7 <= 0;
rt8 <= 0;
rt9 <= 0;
rt10 <= 0;
rt11 <= 0;
rt12 <= 0;
rt13 <= 0;
rt14 <= 0;
rt15 <= 0;
rt16 <= 0;
RowPos_c <= 0;
Dout <= (others=>'0');
DV <= '0';
flag <= '0';
elsif rising_edge(Clk) then
-- counter correction
ColPos_c <= ((ColPos-17) mod 512);
rt1 <= ((RowPos-1) mod 512);
rt2 <= rt1;
rt3 <= rt2;
rt4 <= rt3;
rt5 <= rt4;
rt6 <= rt5;
rt7 <= rt6;
rt8 <= rt7;
rt9 <= rt8;
rt10 <= rt9;
rt11 <= rt10;
rt12 <= rt11;
rt13 <= rt12;
rt14 <= rt13;
rt15 <= rt14;
rt16 <= rt15;
RowPos_c <= rt16;
-- screen edge detection
if (ColPos_c = num_cols-1) or (RowPos_c = num_rows-1) or (ColPos_c
= num_cols-2) or (RowPos_c = 0) then
Dout <= (others=>'0');
else
if order = 1 then
Dout <= s1;
elsif order = 2 then
Dout <= s2;
elsif order = 3 then
Dout <= s3;
elsif order = 4 then
Dout <= s4;
elsif order = 5 then
Dout <= s5;
elsif order = 6 then
Dout <= s6;
elsif order = 7 then
Dout <= s7;
elsif order = 8 then
Dout <= s8;
elsif order = 9 then
Dout <= s9;
end if;
end if;
if ColPos >= 17 and RowPos >= 1 then
DV <= '1';
flag <= '1';
elsif flag = '1' then
DV <= '1';
else
DV <= '0';
end if;
end if;
end process;
end ro_filt_3x3; |
-------------------------------------------------------------- ------------
-- Autor original: Antony Nelson.
-- Modificaciones de esta versión: Jorge Márquez
--
-- Esta rutina contiene las modificaciones indicadas en la sección de
-- Anexos del informe de trabajo de grado PROCESAMIENTO DE IMÁGENES DE
-- ANGIOGRAFÍA BIPLANA USANDO UNA TARJETA DE DESARROLLO SPARTAN-3E
--
-- UNIVERSIDAD DE LOS ANDES
-- FACULTAD DE INGENIERÍA
-- ESCUELA DE INGENIERÍA ELÉCTRICA
--
-- Mérida, Septiembre, 2008
----------------------------------- ----------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
entity ro_filt_3x3 is
generic (
vwidth: integer:=8;
order: integer:=5;
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
Dout : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic;
FColPos : out integer;
FRowPos : out integer
);
end ro_filt_3x3;
architecture ro_filt_3x3 of ro_filt_3x3 is
component sort_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
w11 : in std_logic_vector((vwidth -1) downto 0);
w12 : in std_logic_vector((vwidth -1) downto 0);
w13 : in std_logic_vector((vwidth -1) downto 0);
w21 : in std_logic_vector((vwidth-1) downto 0);
w22 : in std_logic_vector((vwidth -1) downto 0);
w23 : in std_logic_vector((vwidth -1) downto 0);
w31 : in std_logic_vector((vwidth -1) downto 0);
w32 : in std_logic_vector((vwidth -1) downto 0);
w33 : in std_logic_vector((vwidth-1) downto 0);
DVw : in std_logic;
DVs : out std_logic;
s1 : out std_logic_vector(vwidth -1 downto 0);
s2 : out std_logic_vector(vwidth -1 downto 0);
s3 : out std_logic_vector(vwidth -1 downto 0);
s4 : out std_logic_vector(vwidth-1 downto 0);
s5 : out std_logic_vector(vwidth -1 downto 0);
s6 : out std_logic_vector(vwidth -1 downto 0);
s7 : out std_logic_vector(vwidth -1 downto 0);
s8 : out std_logic_vector(vwidth -1 downto 0);
s9 : out std_logic_vector(vwidth -1 downto 0)
);
end component sort_3x3;
signal w11: std_logic_vector((vwidth -1) downto 0);
signal w12: std_logic_vector((vwidth -1) downto 0);
signal w13: std_logic_vector((vwidth -1) downto 0);
signal w21: std_logic_vector((vwidth -1) downto 0);
signal w22: std_logic_vector((vwidth-1) downto 0);
signal w23: std_logic_vector((vwidth -1) downto 0);
signal w31: std_logic_vector((vwidth -1) downto 0);
signal w32: std_logic_vector((vwidth -1) downto 0);
signal w33: std_logic_vector((vwidth -1) downto 0);
signal DVw: std_logic;
signal DVs: std_logic;
signal s1: std_logic_vector(vwidth -1 downto 0);
signal s2: std_logic_vector(vwidth -1 downto 0);
signal s3: std_logic_vector(vwidth -1 downto 0);
signal s4: std_logic_vector(vwidth -1 downto 0);
signal s5: std_logic_vector(vwidth-1 downto 0);
signal s6: std_logic_vector(vwidth -1 downto 0);
signal s7: std_logic_vector(vwidth -1 downto 0);
signal s8: std_logic_vector(vwidth -1 downto 0);
signal s9: std_logic_vector(vwidth -1 downto 0);
component window_3x3
generic (
vwidth: integer:=8
);
port (
Clk : in std_logic;
RSTn : in std_logic;
D : in std_logic_vector(vwidth-1 downto 0);
w11 : out std_logic_vector(vwidth -1 downto 0);
w12 : out std_logic_vector(vwidth -1 downto 0);
w13 : out std_logic_vector(vwidth-1 downto 0);
w21 : out std_logic_vector(vwidth -1 downto 0);
w22 : out std_logic_vector(vwidth -1 downto 0);
w23 : out std_logic_vector(vwidth -1 downto 0);
w31 : out std_logic_vector(vwidth -1 downto 0);
w32 : out std_logic_vector(vwidth-1 downto 0);
w33 : out std_logic_vector(vwidth -1 downto 0);
DV : out std_logic:='0'
);
end component window_3x3;
component rc_counter
generic (
num_cols: integer:=512;
num_rows: integer:=512
);
port (
Clk : in std_logic;
RSTn : in std_logic;
En : in std_logic;
ColPos : out integer;
RowPos : out integer
);
end component rc_counter;
signal ColPos: integer:=0;
signal RowPos: integer:=0;
signal ColPos_c: integer:=0; -- corrected positions
signal RowPos_c: integer:=0;
signal rt1: integer:=0;
signal rt2: integer:=0;
signal rt3: integer:=0;
signal rt4: integer:=0;
signal rt5: integer:=0;
signal rt6: integer:=0;
signal rt7: integer:=0;
signal rt8: integer:=0;
signal rt9: integer:=0;
signal rt10: integer:=0;
signal rt11: integer:=0;
signal rt12: integer:=0;
signal rt13: integer:=0;
signal rt14: integer:=0;
signal rt15: integer:=0;
signal rt16: integer:=0;
signal flag: std_logic:='0';
begin
sort_3x3x: sort_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DVw => DVw,
DVs => DVs,
s1 => s1,
s2 => s2,
s3 => s3,
s4 => s4,
s5 => s5,
s6 => s6,
s7 => s7,
s8 => s8,
s9 => s9
);
window_3x3x: window_3x3
generic map (
vwidth => 8
)
port map (
Clk => Clk,
RSTn => RSTn,
D => D,
w11 => w11,
w12 => w12,
w13 => w13,
w21 => w21,
w22 => w22,
w23 => w23,
w31 => w31,
w32 => w32,
w33 => w33,
DV => DVw
);
rc_counterx: rc_counter
generic map (
num_cols => 512,
num_rows => 512
)
port map (
Clk => Clk,
RSTn => RSTn,
En => RSTn,
ColPos => ColPos,
RowPos => RowPos
);
FColPos <= ColPos;
FRowPos <= RowPos;
ro_filt_proc: process(RSTn,Clk)
begin
if RSTn = '0' then
ColPos_c <= 0;
rt1 <= 0;
rt2 <= 0;
rt3 <= 0;
rt4 <= 0;
rt5 <= 0;
rt6 <= 0;
rt7 <= 0;
rt8 <= 0;
rt9 <= 0;
rt10 <= 0;
rt11 <= 0;
rt12 <= 0;
rt13 <= 0;
rt14 <= 0;
rt15 <= 0;
rt16 <= 0;
RowPos_c <= 0;
Dout <= (others=>'0');
DV <= '0';
flag <= '0';
elsif rising_edge(Clk) then
-- counter correction
ColPos_c <= ((ColPos-17) mod 512);
rt1 <= ((RowPos-1) mod 512);
rt2 <= rt1;
rt3 <= rt2;
rt4 <= rt3;
rt5 <= rt4;
rt6 <= rt5;
rt7 <= rt6;
rt8 <= rt7;
rt9 <= rt8;
rt10 <= rt9;
rt11 <= rt10;
rt12 <= rt11;
rt13 <= rt12;
rt14 <= rt13;
rt15 <= rt14;
rt16 <= rt15;
RowPos_c <= rt16;
-- screen edge detection
if (ColPos_c = num_cols-1) or (RowPos_c = num_rows-1) or (ColPos_c
= num_cols-2) or (RowPos_c = 0) then
Dout <= (others=>'0');
else
if order = 1 then
Dout <= s1;
elsif order = 2 then
Dout <= s2;
elsif order = 3 then
Dout <= s3;
elsif order = 4 then
Dout <= s4;
elsif order = 5 then
Dout <= s5;
elsif order = 6 then
Dout <= s6;
elsif order = 7 then
Dout <= s7;
elsif order = 8 then
Dout <= s8;
elsif order = 9 then
Dout <= s9;
end if;
end if;
if ColPos >= 17 and RowPos >= 1 then
DV <= '1';
flag <= '1';
elsif flag = '1' then
DV <= '1';
else
DV <= '0';
end if;
end if;
end process;
end ro_filt_3x3; |
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 02:50:10 04/24/2013
-- Design Name:
-- Module Name: servo_controller - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
library work ;
use work.logi_utils_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity servo_controller is
generic(
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port (clk : in std_logic;
rst : in std_logic;
servo_position : in std_logic_vector (pos_width-1 downto 0);
servo_out : out std_logic);
end servo_controller;
architecture Behavioral of servo_controller is
constant servo_PWM_period : integer := 20000000;
constant PWM_resolution_per_step : integer := ((maximum_high_pulse_width - minimum_high_pulse_width)/ 2**(servo_position'length));
constant PWM_resolution_per_step_clock_periods : integer := PWM_resolution_per_step / clock_period;
constant minimum_high_pulse_width_steps: integer := minimum_high_pulse_width / PWM_resolution_per_step;
constant maximum_high_pulse_width_steps : integer := (maximum_high_pulse_width / PWM_resolution_per_step) - minimum_high_pulse_width_steps;
constant low_pulse_width_steps : integer := (servo_PWM_period - maximum_high_pulse_width)/PWM_resolution_per_step ;
type main_fsm_type is (reset, min_high_pulse, servo_pulse, low_pulse);
signal current_state, next_state : main_fsm_type;
signal rst_step_gen, rst_servo_step_counter, servo_out_d : std_logic ;
signal servo_step_counter : std_logic_vector((nbit(low_pulse_width_steps)+1) downto 0) ;
signal step_gen_counter : std_logic_vector((nbit(PWM_resolution_per_step_clock_periods)+1) downto 0) ;
begin
state_machine_update : process(clk, rst)
begin
if (rst = '1') then
current_state <= reset;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
st_mach_dec : process(current_state, servo_step_counter)
begin
next_state <= current_state ;
case current_state is
when reset =>
next_state <= min_high_pulse;
when min_high_pulse =>
if (servo_step_counter = minimum_high_pulse_width_steps) then
next_state <= servo_pulse;
end if;
when servo_pulse =>
if (servo_step_counter = maximum_high_pulse_width_steps) then
next_state <= low_pulse;
end if;
when low_pulse =>
if (servo_step_counter = low_pulse_width_steps) then
next_state <= min_high_pulse;
end if;
when others =>
next_state <= reset;
end case;
end process;
with current_state select
rst_step_gen <= '1' when reset,
'0' when others ;
rst_servo_step_counter <= '1' when current_state = min_high_pulse and servo_step_counter = minimum_high_pulse_width_steps else
'1' when current_state = servo_pulse and servo_step_counter = maximum_high_pulse_width_steps else
'1' when current_state = low_pulse and servo_step_counter = low_pulse_width_steps else
'1' when current_state = reset else
'0' ;
servo_out_d <= '1' when current_state = min_high_pulse else
'1' when current_state = servo_pulse and servo_step_counter < servo_position else
'0' ;
servo_out_dff : process(clk)
begin
if (clk'event and clk = '1') then
servo_out <= servo_out_d ;
end if;
end process;
step_gen_counter_inst : process(clk, rst_step_gen)
begin
if (clk'event and clk = '1') then
if (rst_step_gen = '1') then
step_gen_counter <= (others => '0');
elsif (step_gen_counter = PWM_resolution_per_step_clock_periods) then
step_gen_counter <= (others => '0');
else
step_gen_counter <= step_gen_counter + 1;
end if;
end if;
end process;
servo_step_counter_inst : process(clk, rst_servo_step_counter)
begin
if (clk'event and clk = '1') then
if (rst_servo_step_counter = '1') then
servo_step_counter <= (others => '0');
elsif (step_gen_counter = PWM_resolution_per_step_clock_periods) then
servo_step_counter <= servo_step_counter + 1;
end if;
end if;
end process;
end Behavioral;
|
-- ----------------------------------------------------------------------
--LOGI-hard
--Copyright (c) 2013, Jonathan Piat, Michael Jones, All rights reserved.
--
--This library is free software; you can redistribute it and/or
--modify it under the terms of the GNU Lesser General Public
--License as published by the Free Software Foundation; either
--version 3.0 of the License, or (at your option) any later version.
--
--This library is distributed in the hope that it will be useful,
--but WITHOUT ANY WARRANTY; without even the implied warranty of
--MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
--Lesser General Public License for more details.
--
--You should have received a copy of the GNU Lesser General Public
--License along with this library.
-- ----------------------------------------------------------------------
----------------------------------------------------------------------------------
-- Company:LAAS-CNRS
-- Author:Jonathan Piat <[email protected]>
--
-- Create Date: 02:50:10 04/24/2013
-- Design Name:
-- Module Name: servo_controller - Behavioral
-- Project Name:
-- Target Devices: Spartan 6 Spartan 6
-- Tool versions: ISE 14.1 ISE 14.1
-- Description:
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use ieee.std_logic_unsigned.all;
library work ;
use work.logi_utils_pack.all ;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity servo_controller is
generic(
pos_width : integer := 8 ;
clock_period : integer := 10;
minimum_high_pulse_width : integer := 1000000;
maximum_high_pulse_width : integer := 2000000
);
port (clk : in std_logic;
rst : in std_logic;
servo_position : in std_logic_vector (pos_width-1 downto 0);
servo_out : out std_logic);
end servo_controller;
architecture Behavioral of servo_controller is
constant servo_PWM_period : integer := 20000000;
constant PWM_resolution_per_step : integer := ((maximum_high_pulse_width - minimum_high_pulse_width)/ 2**(servo_position'length));
constant PWM_resolution_per_step_clock_periods : integer := PWM_resolution_per_step / clock_period;
constant minimum_high_pulse_width_steps: integer := minimum_high_pulse_width / PWM_resolution_per_step;
constant maximum_high_pulse_width_steps : integer := (maximum_high_pulse_width / PWM_resolution_per_step) - minimum_high_pulse_width_steps;
constant low_pulse_width_steps : integer := (servo_PWM_period - maximum_high_pulse_width)/PWM_resolution_per_step ;
type main_fsm_type is (reset, min_high_pulse, servo_pulse, low_pulse);
signal current_state, next_state : main_fsm_type;
signal rst_step_gen, rst_servo_step_counter, servo_out_d : std_logic ;
signal servo_step_counter : std_logic_vector((nbit(low_pulse_width_steps)+1) downto 0) ;
signal step_gen_counter : std_logic_vector((nbit(PWM_resolution_per_step_clock_periods)+1) downto 0) ;
begin
state_machine_update : process(clk, rst)
begin
if (rst = '1') then
current_state <= reset;
elsif clk'event and clk = '1' then
current_state <= next_state;
end if;
end process;
st_mach_dec : process(current_state, servo_step_counter)
begin
next_state <= current_state ;
case current_state is
when reset =>
next_state <= min_high_pulse;
when min_high_pulse =>
if (servo_step_counter = minimum_high_pulse_width_steps) then
next_state <= servo_pulse;
end if;
when servo_pulse =>
if (servo_step_counter = maximum_high_pulse_width_steps) then
next_state <= low_pulse;
end if;
when low_pulse =>
if (servo_step_counter = low_pulse_width_steps) then
next_state <= min_high_pulse;
end if;
when others =>
next_state <= reset;
end case;
end process;
with current_state select
rst_step_gen <= '1' when reset,
'0' when others ;
rst_servo_step_counter <= '1' when current_state = min_high_pulse and servo_step_counter = minimum_high_pulse_width_steps else
'1' when current_state = servo_pulse and servo_step_counter = maximum_high_pulse_width_steps else
'1' when current_state = low_pulse and servo_step_counter = low_pulse_width_steps else
'1' when current_state = reset else
'0' ;
servo_out_d <= '1' when current_state = min_high_pulse else
'1' when current_state = servo_pulse and servo_step_counter < servo_position else
'0' ;
servo_out_dff : process(clk)
begin
if (clk'event and clk = '1') then
servo_out <= servo_out_d ;
end if;
end process;
step_gen_counter_inst : process(clk, rst_step_gen)
begin
if (clk'event and clk = '1') then
if (rst_step_gen = '1') then
step_gen_counter <= (others => '0');
elsif (step_gen_counter = PWM_resolution_per_step_clock_periods) then
step_gen_counter <= (others => '0');
else
step_gen_counter <= step_gen_counter + 1;
end if;
end if;
end process;
servo_step_counter_inst : process(clk, rst_servo_step_counter)
begin
if (clk'event and clk = '1') then
if (rst_servo_step_counter = '1') then
servo_step_counter <= (others => '0');
elsif (step_gen_counter = PWM_resolution_per_step_clock_periods) then
servo_step_counter <= servo_step_counter + 1;
end if;
end if;
end process;
end Behavioral;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_18 is
end entity inline_18;
----------------------------------------------------------------
architecture test of inline_18 is
begin
process_5_a : process is
constant initial_value : natural := 10;
constant max_value : natural := 8;
constant current_character : character := 'A';
constant input_string : string := "012ABC";
constant free_memory : natural := 0;
constant low_water_limit : natural := 1024;
constant packet_length : natural := 0;
constant clock_pulse_width : delay_length := 10 ns;
constant min_clock_width : delay_length := 20 ns;
constant last_position : natural := 10;
constant first_position : natural := 5;
constant number_of_entries : natural := 0;
begin
-- code from book:
assert initial_value <= max_value;
--
assert initial_value <= max_value
report "initial value too large";
--
assert current_character >= '0' and current_character <= '9'
report "Input number " & input_string & " contains a non-digit";
--
assert free_memory >= low_water_limit
report "low on memory, about to start garbage collect"
severity note;
--
assert packet_length /= 0
report "empty network packet received"
severity warning;
--
assert clock_pulse_width >= min_clock_width
severity error;
--
assert (last_position - first_position + 1) = number_of_entries
report "inconsistency in buffer model"
severity failure;
-- end of code from book
wait;
end process process_5_a;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_18 is
end entity inline_18;
----------------------------------------------------------------
architecture test of inline_18 is
begin
process_5_a : process is
constant initial_value : natural := 10;
constant max_value : natural := 8;
constant current_character : character := 'A';
constant input_string : string := "012ABC";
constant free_memory : natural := 0;
constant low_water_limit : natural := 1024;
constant packet_length : natural := 0;
constant clock_pulse_width : delay_length := 10 ns;
constant min_clock_width : delay_length := 20 ns;
constant last_position : natural := 10;
constant first_position : natural := 5;
constant number_of_entries : natural := 0;
begin
-- code from book:
assert initial_value <= max_value;
--
assert initial_value <= max_value
report "initial value too large";
--
assert current_character >= '0' and current_character <= '9'
report "Input number " & input_string & " contains a non-digit";
--
assert free_memory >= low_water_limit
report "low on memory, about to start garbage collect"
severity note;
--
assert packet_length /= 0
report "empty network packet received"
severity warning;
--
assert clock_pulse_width >= min_clock_width
severity error;
--
assert (last_position - first_position + 1) = number_of_entries
report "inconsistency in buffer model"
severity failure;
-- end of code from book
wait;
end process process_5_a;
end architecture test;
|
-- Copyright (C) 2002 Morgan Kaufmann Publishers, Inc
-- This file is part of VESTs (Vhdl tESTs).
-- VESTs is free software; you can redistribute it and/or modify it
-- under the terms of the GNU General Public License as published by the
-- Free Software Foundation; either version 2 of the License, or (at
-- your option) any later version.
-- VESTs is distributed in the hope that it will be useful, but WITHOUT
-- ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
-- FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
-- for more details.
-- You should have received a copy of the GNU General Public License
-- along with VESTs; if not, write to the Free Software Foundation,
-- Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
entity inline_18 is
end entity inline_18;
----------------------------------------------------------------
architecture test of inline_18 is
begin
process_5_a : process is
constant initial_value : natural := 10;
constant max_value : natural := 8;
constant current_character : character := 'A';
constant input_string : string := "012ABC";
constant free_memory : natural := 0;
constant low_water_limit : natural := 1024;
constant packet_length : natural := 0;
constant clock_pulse_width : delay_length := 10 ns;
constant min_clock_width : delay_length := 20 ns;
constant last_position : natural := 10;
constant first_position : natural := 5;
constant number_of_entries : natural := 0;
begin
-- code from book:
assert initial_value <= max_value;
--
assert initial_value <= max_value
report "initial value too large";
--
assert current_character >= '0' and current_character <= '9'
report "Input number " & input_string & " contains a non-digit";
--
assert free_memory >= low_water_limit
report "low on memory, about to start garbage collect"
severity note;
--
assert packet_length /= 0
report "empty network packet received"
severity warning;
--
assert clock_pulse_width >= min_clock_width
severity error;
--
assert (last_position - first_position + 1) = number_of_entries
report "inconsistency in buffer model"
severity failure;
-- end of code from book
wait;
end process process_5_a;
end architecture test;
|
---------------------------------------------------------------------
-- TITLE: Plasma Misc. Package
-- Main AUTHOR: Steve Rhoads ([email protected])
-- DATE CREATED: 2/15/01
-- FILENAME: mlite_pack.vhd
-- PROJECT: Plasma CPU core
-- COPYRIGHT: Software placed into the public domain by the author.
-- Software 'as is' without warranty. Author liable for nothing.
-- DESCRIPTION:
-- Data types, constants, and add functions needed for the Plasma CPU.
-- modified by: Siavoosh Payandeh Azad
-- Change logs:
-- * An NI has been added to the file as a new module
-- * some changes has been applied to the ports of the older modules
-- to facilitate the new module!
-- * memory mapped addresses are added!
---------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
package mlite_pack is
constant ZERO : std_logic_vector(31 downto 0) :=
"00000000000000000000000000000000";
constant ONES : std_logic_vector(31 downto 0) :=
"11111111111111111111111111111111";
--make HIGH_Z equal to ZERO if compiler complains
constant HIGH_Z : std_logic_vector(31 downto 0) :=
"ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
subtype alu_function_type is std_logic_vector(3 downto 0);
constant ALU_NOTHING : alu_function_type := "0000";
constant ALU_ADD : alu_function_type := "0001";
constant ALU_SUBTRACT : alu_function_type := "0010";
constant ALU_LESS_THAN : alu_function_type := "0011";
constant ALU_LESS_THAN_SIGNED : alu_function_type := "0100";
constant ALU_OR : alu_function_type := "0101";
constant ALU_AND : alu_function_type := "0110";
constant ALU_XOR : alu_function_type := "0111";
constant ALU_NOR : alu_function_type := "1000";
subtype shift_function_type is std_logic_vector(1 downto 0);
constant SHIFT_NOTHING : shift_function_type := "00";
constant SHIFT_LEFT_UNSIGNED : shift_function_type := "01";
constant SHIFT_RIGHT_SIGNED : shift_function_type := "11";
constant SHIFT_RIGHT_UNSIGNED : shift_function_type := "10";
subtype mult_function_type is std_logic_vector(3 downto 0);
constant MULT_NOTHING : mult_function_type := "0000";
constant MULT_READ_LO : mult_function_type := "0001";
constant MULT_READ_HI : mult_function_type := "0010";
constant MULT_WRITE_LO : mult_function_type := "0011";
constant MULT_WRITE_HI : mult_function_type := "0100";
constant MULT_MULT : mult_function_type := "0101";
constant MULT_SIGNED_MULT : mult_function_type := "0110";
constant MULT_DIVIDE : mult_function_type := "0111";
constant MULT_SIGNED_DIVIDE : mult_function_type := "1000";
subtype a_source_type is std_logic_vector(1 downto 0);
constant A_FROM_REG_SOURCE : a_source_type := "00";
constant A_FROM_IMM10_6 : a_source_type := "01";
constant A_FROM_PC : a_source_type := "10";
subtype b_source_type is std_logic_vector(1 downto 0);
constant B_FROM_REG_TARGET : b_source_type := "00";
constant B_FROM_IMM : b_source_type := "01";
constant B_FROM_SIGNED_IMM : b_source_type := "10";
constant B_FROM_IMMX4 : b_source_type := "11";
subtype c_source_type is std_logic_vector(2 downto 0);
constant C_FROM_NULL : c_source_type := "000";
constant C_FROM_ALU : c_source_type := "001";
constant C_FROM_SHIFT : c_source_type := "001"; --same as alu
constant C_FROM_MULT : c_source_type := "001"; --same as alu
constant C_FROM_MEMORY : c_source_type := "010";
constant C_FROM_PC : c_source_type := "011";
constant C_FROM_PC_PLUS4 : c_source_type := "100";
constant C_FROM_IMM_SHIFT16: c_source_type := "101";
constant C_FROM_REG_SOURCEN: c_source_type := "110";
subtype pc_source_type is std_logic_vector(1 downto 0);
constant FROM_INC4 : pc_source_type := "00";
constant FROM_OPCODE25_0 : pc_source_type := "01";
constant FROM_BRANCH : pc_source_type := "10";
constant FROM_LBRANCH : pc_source_type := "11";
subtype branch_function_type is std_logic_vector(2 downto 0);
constant BRANCH_LTZ : branch_function_type := "000";
constant BRANCH_LEZ : branch_function_type := "001";
constant BRANCH_EQ : branch_function_type := "010";
constant BRANCH_NE : branch_function_type := "011";
constant BRANCH_GEZ : branch_function_type := "100";
constant BRANCH_GTZ : branch_function_type := "101";
constant BRANCH_YES : branch_function_type := "110";
constant BRANCH_NO : branch_function_type := "111";
-- mode(32=1,16=2,8=3), signed, write
subtype mem_source_type is std_logic_vector(3 downto 0);
constant MEM_FETCH : mem_source_type := "0000";
constant MEM_READ32 : mem_source_type := "0100";
constant MEM_WRITE32 : mem_source_type := "0101";
constant MEM_READ16 : mem_source_type := "1000";
constant MEM_READ16S : mem_source_type := "1010";
constant MEM_WRITE16 : mem_source_type := "1001";
constant MEM_READ8 : mem_source_type := "1100";
constant MEM_READ8S : mem_source_type := "1110";
constant MEM_WRITE8 : mem_source_type := "1101";
-- memory mapped addresses
constant NI_reserved_data_address : std_logic_vector(29 downto 0) := "000000000000000001111111111111";
constant NI_flag_address : std_logic_vector(29 downto 0) := "000000000000000010000000000000";
constant NI_counter_address : std_logic_vector(29 downto 0) := "000000000000000010000000000001";
constant NI_reconfiguration_address : std_logic_vector(29 downto 0) := "000000000000000010000000000010";
constant NI_self_diagnosis_address : std_logic_vector(29 downto 0) := "000000000000000010000000000011";
constant uart_count_value_address : std_logic_vector(29 downto 0) := "000000000000000010000000000100";
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector;
function bv_negate(a : in std_logic_vector) return std_logic_vector;
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector;
function bv_inc(a : in std_logic_vector
) return std_logic_vector;
-- For Altera
COMPONENT lpm_ram_dp
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_RDADDRESS_CONTROL : string := "REGISTERED";
LPM_WRADDRESS_CONTROL : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DP";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
RDEN_USED : string := "TRUE";
LPM_HINT : string := "UNUSED");
port (
RDCLOCK : in std_logic := '0';
RDCLKEN : in std_logic := '1';
RDADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
RDEN : in std_logic := '1';
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
WRADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
WREN : in std_logic;
WRCLOCK : in std_logic := '0';
WRCLKEN : in std_logic := '1';
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
END COMPONENT;
-- For Altera
component LPM_RAM_DQ
generic (
LPM_WIDTH : natural; -- MUST be greater than 0
LPM_WIDTHAD : natural; -- MUST be greater than 0
LPM_NUMWORDS : natural := 0;
LPM_INDATA : string := "REGISTERED";
LPM_ADDRESS_CONTROL: string := "REGISTERED";
LPM_OUTDATA : string := "REGISTERED";
LPM_FILE : string := "UNUSED";
LPM_TYPE : string := "LPM_RAM_DQ";
USE_EAB : string := "OFF";
INTENDED_DEVICE_FAMILY : string := "UNUSED";
LPM_HINT : string := "UNUSED");
port (
DATA : in std_logic_vector(LPM_WIDTH-1 downto 0);
ADDRESS : in std_logic_vector(LPM_WIDTHAD-1 downto 0);
INCLOCK : in std_logic := '0';
OUTCLOCK : in std_logic := '0';
WE : in std_logic;
Q : out std_logic_vector(LPM_WIDTH-1 downto 0));
end component;
-- For Xilinx
component RAM16X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"0000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
-- For Xilinx Virtex-5
component RAM32X1D
-- synthesis translate_off
generic (INIT : bit_vector := X"00000000");
-- synthesis translate_on
port (DPO : out STD_ULOGIC;
SPO : out STD_ULOGIC;
A0 : in STD_ULOGIC;
A1 : in STD_ULOGIC;
A2 : in STD_ULOGIC;
A3 : in STD_ULOGIC;
A4 : in STD_ULOGIC;
D : in STD_ULOGIC;
DPRA0 : in STD_ULOGIC;
DPRA1 : in STD_ULOGIC;
DPRA2 : in STD_ULOGIC;
DPRA3 : in STD_ULOGIC;
DPRA4 : in STD_ULOGIC;
WCLK : in STD_ULOGIC;
WE : in STD_ULOGIC);
end component;
component pc_next
port(clk : in std_logic;
reset_in : in std_logic;
pc_new : in std_logic_vector(31 downto 2);
take_branch : in std_logic;
pause_in : in std_logic;
opcode25_0 : in std_logic_vector(25 downto 0);
pc_source : in pc_source_type;
pc_future : out std_logic_vector(31 downto 2);
pc_current : out std_logic_vector(31 downto 2);
pc_plus4 : out std_logic_vector(31 downto 2));
end component;
component mem_ctrl
port(clk : in std_logic;
reset_in : in std_logic;
pause_in : in std_logic;
nullify_op : in std_logic;
address_pc : in std_logic_vector(31 downto 2);
opcode_out : out std_logic_vector(31 downto 0);
address_in : in std_logic_vector(31 downto 0);
mem_source : in mem_source_type;
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
pause_out : out std_logic;
address_next : out std_logic_vector(31 downto 2);
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0));
end component;
component control
port(opcode : in std_logic_vector(31 downto 0);
intr_signal : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
rs_index : out std_logic_vector(5 downto 0);
rt_index : out std_logic_vector(5 downto 0);
rd_index : out std_logic_vector(5 downto 0);
imm_out : out std_logic_vector(15 downto 0);
alu_func : out alu_function_type;
shift_func : out shift_function_type;
mult_func : out mult_function_type;
branch_func : out branch_function_type;
a_source_out : out a_source_type;
b_source_out : out b_source_type;
c_source_out : out c_source_type;
pc_source_out: out pc_source_type;
mem_source_out:out mem_source_type;
exception_out: out std_logic);
end component;
component reg_bank
generic(memory_type : string := "XILINX_16X");
port(clk : in std_logic;
reset_in : in std_logic;
pause : in std_logic;
interrupt_in : in std_logic; -- modified
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
rd_index : in std_logic_vector(5 downto 0);
reg_source_out : out std_logic_vector(31 downto 0);
reg_target_out : out std_logic_vector(31 downto 0);
reg_dest_new : in std_logic_vector(31 downto 0);
intr_enable : out std_logic);
end component;
component bus_mux
port(imm_in : in std_logic_vector(15 downto 0);
reg_source : in std_logic_vector(31 downto 0);
a_mux : in a_source_type;
a_out : out std_logic_vector(31 downto 0);
reg_target : in std_logic_vector(31 downto 0);
b_mux : in b_source_type;
b_out : out std_logic_vector(31 downto 0);
c_bus : in std_logic_vector(31 downto 0);
c_memory : in std_logic_vector(31 downto 0);
c_pc : in std_logic_vector(31 downto 2);
c_pc_plus4 : in std_logic_vector(31 downto 2);
c_mux : in c_source_type;
reg_dest_out : out std_logic_vector(31 downto 0);
branch_func : in branch_function_type;
take_branch : out std_logic);
end component;
component alu
generic(alu_type : string := "DEFAULT");
port(a_in : in std_logic_vector(31 downto 0);
b_in : in std_logic_vector(31 downto 0);
alu_function : in alu_function_type;
c_alu : out std_logic_vector(31 downto 0));
end component;
component shifter
generic(shifter_type : string := "DEFAULT" );
port(value : in std_logic_vector(31 downto 0);
shift_amount : in std_logic_vector(4 downto 0);
shift_func : in shift_function_type;
c_shift : out std_logic_vector(31 downto 0));
end component;
component mult
generic(mult_type : string := "DEFAULT");
port(clk : in std_logic;
reset_in : in std_logic;
a, b : in std_logic_vector(31 downto 0);
mult_func : in mult_function_type;
c_mult : out std_logic_vector(31 downto 0);
pause_out : out std_logic);
end component;
component pipeline
port(clk : in std_logic;
reset : in std_logic;
a_bus : in std_logic_vector(31 downto 0);
a_busD : out std_logic_vector(31 downto 0);
b_bus : in std_logic_vector(31 downto 0);
b_busD : out std_logic_vector(31 downto 0);
alu_func : in alu_function_type;
alu_funcD : out alu_function_type;
shift_func : in shift_function_type;
shift_funcD : out shift_function_type;
mult_func : in mult_function_type;
mult_funcD : out mult_function_type;
reg_dest : in std_logic_vector(31 downto 0);
reg_destD : out std_logic_vector(31 downto 0);
rd_index : in std_logic_vector(5 downto 0);
rd_indexD : out std_logic_vector(5 downto 0);
rs_index : in std_logic_vector(5 downto 0);
rt_index : in std_logic_vector(5 downto 0);
pc_source : in pc_source_type;
mem_source : in mem_source_type;
a_source : in a_source_type;
b_source : in b_source_type;
c_source : in c_source_type;
c_bus : in std_logic_vector(31 downto 0);
pause_any : in std_logic;
pause_pipeline : out std_logic);
end component;
component mlite_cpu
generic(memory_type : string := "XILINX_16X"; --ALTERA_LPM, or DUAL_PORT_
mult_type : string := "DEFAULT";
shifter_type : string := "DEFAULT";
alu_type : string := "DEFAULT";
pipeline_stages : natural := 2); --2 or 3
port(clk : in std_logic;
reset_in : in std_logic;
intr_in : in std_logic;
--NI_read_flag : in std_logic;
--NI_write_flag : in std_logic;
address_next : out std_logic_vector(31 downto 2); --for synch ram
byte_we_next : out std_logic_vector(3 downto 0);
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_w : out std_logic_vector(31 downto 0);
data_r : in std_logic_vector(31 downto 0);
mem_pause : in std_logic);
end component;
component cache
generic(memory_type : string := "DEFAULT");
port(clk : in std_logic;
reset : in std_logic;
address_next : in std_logic_vector(31 downto 2);
byte_we_next : in std_logic_vector(3 downto 0);
cpu_address : in std_logic_vector(31 downto 2);
mem_busy : in std_logic;
cache_access : out std_logic; --access 4KB cache
cache_checking : out std_logic; --checking if cache hit
cache_miss : out std_logic); --cache miss
end component; --cache
-- change this if you want to use behavioral ram!
--component ram
-- generic(memory_type : string := "DEFAULT";
-- stim_file: string :="code.txt");
-- port(clk : in std_logic;
-- enable : in std_logic;
-- reset : in std_logic;
-- write_byte_enable : in std_logic_vector(3 downto 0);
-- address : in std_logic_vector(31 downto 2);
-- data_write : in std_logic_vector(31 downto 0);
-- data_read : out std_logic_vector(31 downto 0));
-- end component; --ram
component ram is
generic(memory_type : string := "DEFAULT";
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0));
end component; -- ram
component NI
generic(current_address : integer := 10; -- the current node's address
SHMU_address : integer := 0); -- reserved address for self diagnosis register
port(clk : in std_logic;
reset : in std_logic;
enable : in std_logic;
write_byte_enable : in std_logic_vector(3 downto 0);
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
data_read : out std_logic_vector(31 downto 0);
-- Flags used by JNIFR and JNIFW instructions
--NI_read_flag : out std_logic; -- One if the N2P fifo is empty. No read should be performed if one.
--NI_write_flag : out std_logic; -- One if P2N fifo is full. no write should be performed if one.
-- interrupt signal: generated evertime a packet is recieved!
irq_out : out std_logic;
-- signals for sending packets to network
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0); -- data sent to the NoC
-- signals for reciving packets from the network
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0); -- data recieved form the NoC
-- fault information signals from the router
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic
);
end component; --entity NI
component uart
generic(log_file : string := "UNUSED");
port(clk : in std_logic;
reset : in std_logic;
enable_read : in std_logic;
enable_write : in std_logic;
data_in : in std_logic_vector(7 downto 0);
data_out : out std_logic_vector(7 downto 0);
uart_read : in std_logic;
uart_write : out std_logic;
busy_write : out std_logic;
data_avail : out std_logic;
reg_enable : in std_logic;
reg_write_byte_enable : in std_logic_vector(3 downto 0);
reg_address : in std_logic_vector(31 downto 2);
reg_data_write : in std_logic_vector(31 downto 0);
reg_data_read : out std_logic_vector(31 downto 0)
);
end component; --uart
component eth_dma
port(clk : in std_logic; --25 MHz
reset : in std_logic;
enable_eth : in std_logic;
select_eth : in std_logic;
rec_isr : out std_logic;
send_isr : out std_logic;
address : out std_logic_vector(31 downto 2); --to DDR
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
pause_in : in std_logic;
mem_address : in std_logic_vector(31 downto 2); --from CPU
mem_byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
pause_out : out std_logic;
E_RX_CLK : in std_logic; --2.5 MHz receive
E_RX_DV : in std_logic; --data valid
E_RXD : in std_logic_vector(3 downto 0); --receive nibble
E_TX_CLK : in std_logic; --2.5 MHz transmit
E_TX_EN : out std_logic; --transmit enable
E_TXD : out std_logic_vector(3 downto 0)); --transmit nibble
end component; --eth_dma
component plasma
generic(memory_type : string := "XILINX_X16"; --"DUAL_PORT_" "ALTERA_LPM";
log_file : string := "UNUSED";
ethernet : std_logic := '0';
use_cache : std_logic := '0';
current_address : integer := 10;
stim_file: string :="code.txt");
port(clk : in std_logic;
reset : in std_logic;
uart_write : out std_logic;
uart_read : in std_logic;
address : out std_logic_vector(31 downto 2);
byte_we : out std_logic_vector(3 downto 0);
data_write : out std_logic_vector(31 downto 0);
data_read : in std_logic_vector(31 downto 0);
mem_pause_in : in std_logic;
no_ddr_start : out std_logic;
no_ddr_stop : out std_logic;
gpio0_out : out std_logic_vector(31 downto 0);
gpioA_in : in std_logic_vector(31 downto 0);
credit_in : in std_logic;
valid_out: out std_logic;
TX: out std_logic_vector(31 downto 0);
credit_out : out std_logic;
valid_in: in std_logic;
RX: in std_logic_vector(31 downto 0);
link_faults: in std_logic_vector(4 downto 0);
turn_faults: in std_logic_vector(19 downto 0);
Rxy_reconf_PE: out std_logic_vector(7 downto 0);
Cx_reconf_PE: out std_logic_vector(3 downto 0); -- if you are not going to update Cx you should write all ones! (it will be and will the current Cx bits)
Reconfig_command : out std_logic;
-- remove this part if you are using behavioral memory
IJTAG_select : in std_logic;
IJTAG_clk : in std_logic;
IJTAG_reset : in std_logic;
IJTAG_enable : in std_logic;
IJTAG_write_byte_enable : in std_logic_vector(3 downto 0);
IJTAG_address : in std_logic_vector(31 downto 2);
IJTAG_data_write : in std_logic_vector(31 downto 0);
IJTAG_data_read : out std_logic_vector(31 downto 0)
);
end component; --plasma
component ddr_ctrl
port(clk : in std_logic;
clk_2x : in std_logic;
reset_in : in std_logic;
address : in std_logic_vector(25 downto 2);
byte_we : in std_logic_vector(3 downto 0);
data_w : in std_logic_vector(31 downto 0);
data_r : out std_logic_vector(31 downto 0);
active : in std_logic;
no_start : in std_logic;
no_stop : in std_logic;
pause : out std_logic;
SD_CK_P : out std_logic; --clock_positive
SD_CK_N : out std_logic; --clock_negative
SD_CKE : out std_logic; --clock_enable
SD_BA : out std_logic_vector(1 downto 0); --bank_address
SD_A : out std_logic_vector(12 downto 0); --address(row or col)
SD_CS : out std_logic; --chip_select
SD_RAS : out std_logic; --row_address_strobe
SD_CAS : out std_logic; --column_address_strobe
SD_WE : out std_logic; --write_enable
SD_DQ : inout std_logic_vector(15 downto 0); --data
SD_UDM : out std_logic; --upper_byte_enable
SD_UDQS : inout std_logic; --upper_data_strobe
SD_LDM : out std_logic; --low_byte_enable
SD_LDQS : inout std_logic); --low_data_strobe
end component; --ddr
component memory
generic(address_width : natural := 16);
port(clk : in std_logic;
address : in std_logic_vector(31 downto 2);
data_write : in std_logic_vector(31 downto 0);
pause : in std_logic;
byte_we : in std_logic_vector(3 downto 0);
data_read : out std_logic_vector(31 downto 0)
);
end component; --entity memory
end; --package mlite_pack
package body mlite_pack is
--function bv_adder(a : in std_logic_vector;
-- b : in std_logic_vector;
-- do_add: in std_logic) return std_logic_vector is
-- variable carry_in : std_logic;
-- variable bb : std_logic_vector(a'length-1 downto 0);
-- variable result : std_logic_vector(a'length downto 0);
--begin
-- if do_add = '1' then
-- bb := b;
-- carry_in := '0';
-- else
-- bb := not b;
-- carry_in := '1';
-- end if;
-- for index in 0 to a'length-1 loop
-- result(index) := a(index) xor bb(index) xor carry_in;
-- carry_in := (carry_in and (a(index) or bb(index))) or
-- (a(index) and bb(index));
-- end loop;
-- result(a'length) := carry_in xnor do_add;
-- return result;
--end; --function
function bv_adder(a : in std_logic_vector;
b : in std_logic_vector;
do_add: in std_logic) return std_logic_vector is
variable A1, B1, S : UNSIGNED(a'length downto 0);
begin
A1 := resize(unsigned(a), A1'length);
B1 := resize(unsigned(b), B1'length);
if do_add = '1' then
S := A1 + B1;
else
S := A1 - B1;
end if;
return std_logic_vector(S);
end; --function
function bv_negate(a : in std_logic_vector) return std_logic_vector is
variable carry_in : std_logic;
variable not_a : std_logic_vector(a'length-1 downto 0);
variable result : std_logic_vector(a'length-1 downto 0);
begin
not_a := not a;
carry_in := '1';
for index in a'reverse_range loop
result(index) := not_a(index) xor carry_in;
carry_in := carry_in and not_a(index);
end loop;
return result;
end; --function
function bv_increment(a : in std_logic_vector(31 downto 2)
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(31 downto 2);
begin
carry_in := '1';
for index in 2 to 31 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
function bv_inc(a : in std_logic_vector
) return std_logic_vector is
variable carry_in : std_logic;
variable result : std_logic_vector(a'length-1 downto 0);
begin
carry_in := '1';
for index in 0 to a'length-1 loop
result(index) := a(index) xor carry_in;
carry_in := a(index) and carry_in;
end loop;
return result;
end; --function
end; --package body
|
Subsets and Splits
No community queries yet
The top public SQL queries from the community will appear here once available.